system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001bd04f_00000000-6_naivePrefixSum.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z14naivePrefixSumPiS_iiPiS_ii
.type _Z38__device_stub__Z14naivePrefixSumPiS_iiPiS_ii, @function
_Z38__device_stub__Z14naivePrefixSumPiS_iiPiS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14naivePrefixSumPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z14naivePrefixSumPiS_iiPiS_ii, .-_Z38__device_stub__Z14naivePrefixSumPiS_iiPiS_ii
.globl _Z14naivePrefixSumPiS_ii
.type _Z14naivePrefixSumPiS_ii, @function
_Z14naivePrefixSumPiS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z14naivePrefixSumPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14naivePrefixSumPiS_ii, .-_Z14naivePrefixSumPiS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14naivePrefixSumPiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14naivePrefixSumPiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl d_b
.bss
.align 8
.type d_b, @object
.size d_b, 8
d_b:
.zero 8
.globl d_a
.align 8
.type d_a, @object
.size d_a, 8
d_a:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "naivePrefixSum.hip"
.globl _Z29__device_stub__naivePrefixSumPiS_ii # -- Begin function _Z29__device_stub__naivePrefixSumPiS_ii
.p2align 4, 0x90
.type _Z29__device_stub__naivePrefixSumPiS_ii,@function
_Z29__device_stub__naivePrefixSumPiS_ii: # @_Z29__device_stub__naivePrefixSumPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14naivePrefixSumPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__naivePrefixSumPiS_ii, .Lfunc_end0-_Z29__device_stub__naivePrefixSumPiS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14naivePrefixSumPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type d_a,@object # @d_a
.bss
.globl d_a
.p2align 3, 0x0
d_a:
.quad 0
.size d_a, 8
.type d_b,@object # @d_b
.globl d_b
.p2align 3, 0x0
d_b:
.quad 0
.size d_b, 8
.type _Z14naivePrefixSumPiS_ii,@object # @_Z14naivePrefixSumPiS_ii
.section .rodata,"a",@progbits
.globl _Z14naivePrefixSumPiS_ii
.p2align 3, 0x0
_Z14naivePrefixSumPiS_ii:
.quad _Z29__device_stub__naivePrefixSumPiS_ii
.size _Z14naivePrefixSumPiS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14naivePrefixSumPiS_ii"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__naivePrefixSumPiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14naivePrefixSumPiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /**
* Concurrent Wave Equation
* Compilation Command: nvcc cuda1.cu -o cuda1
* This program was originally written in serial method by the teacher.
*/
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#define MAXPOINTS 1000000
#define MAXSTEPS 1000000
#define MINPOINTS 20
static void handleError(cudaError_t err, const char *file, int line) {
if (err != cudaSuccess) {
printf("%s in %s at line %d\n", cudaGetErrorString(err), file, line);
exit(EXIT_FAILURE);
}
}
#define HANDLE_ERROR(err) (handleError(err, __FILE__, __LINE__))
void checkParam();
__global__ void initLine(float*, float*, int);
__global__ void updateAll(float*, float*, int, int);
void printResult();
int totalSteps, totalPoints, allocPoints;
float *currVal;
float *devCurrVal, *devPrevVal;
int main(int argc, char *argv[]) {
sscanf(argv[1], "%d", &totalPoints);
sscanf(argv[2], "%d", &totalSteps);
checkParam();
allocPoints = totalPoints + 256;
currVal = (float*) malloc(allocPoints * sizeof(float));
if (!currVal)
exit(EXIT_FAILURE);
HANDLE_ERROR(cudaMalloc((void**) &devCurrVal, allocPoints * sizeof(float)));
HANDLE_ERROR(cudaMalloc((void**) &devPrevVal, allocPoints * sizeof(float)));
dim3 threadsPerBlock(256);
dim3 numOfBlocks(allocPoints/256);
printf("Initializing points on the line...\n");
initLine<<<numOfBlocks, threadsPerBlock>>>(devPrevVal, devCurrVal, totalPoints);
printf("Updating all points for all time steps...\n");
updateAll<<<numOfBlocks, threadsPerBlock>>>(devPrevVal, devCurrVal, totalPoints, totalSteps);
printf("Printing final results...\n");
HANDLE_ERROR(cudaMemcpy(currVal, devCurrVal, allocPoints * sizeof(float), cudaMemcpyDeviceToHost));
printResult();
printf("\nDone.\n\n");
cudaFree(devCurrVal);
cudaFree(devPrevVal);
free(currVal);
return EXIT_SUCCESS;
}
void checkParam() {
char temp[20];
while ((totalPoints < MINPOINTS) || (totalPoints > MAXPOINTS)) {
printf("Enter number of points along vibrating string [%d-%d]: ", MINPOINTS, MAXPOINTS);
scanf("%s", temp);
totalPoints = atoi(temp);
if ((totalPoints < MINPOINTS) || (totalPoints > MAXPOINTS))
printf("Invalid. Please enter value between %d and %d.\n", MINPOINTS, MAXPOINTS);
}
while ((totalSteps < 1) || (totalSteps > MAXSTEPS)) {
printf("Enter number of time steps [1-%d]: ", MAXSTEPS);
scanf("%s", temp);
totalSteps = atoi(temp);
if ((totalSteps < 1) || (totalSteps > MAXSTEPS))
printf("Invalid. Please enter value between 1 and %d.\n", MAXSTEPS);
}
printf("Using points = %d, steps = %d\n", totalPoints, totalSteps);
}
__global__ void initLine(float *__devPrevVal, float *__devCurrVal, int __totalPoints) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < __totalPoints) {
float x = (float) i / (__totalPoints - 1);
__devPrevVal[i] = __devCurrVal[i] = __sinf(6.28318530 * x);
}
}
__global__ void updateAll(float *__devPrevVal, float *__devCurrVal, int __totalPoints, int __totalSteps) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < __totalPoints) {
float locPrevVal = __devPrevVal[i], locCurrVal = __devCurrVal[i] , locNextVal;
for (int j = 0; j < __totalSteps; j++) {
if ((i == 0) || (i == __totalPoints - 1))
locNextVal = 0.0;
else
locNextVal = 1.82 * locCurrVal - locPrevVal;
locPrevVal = locCurrVal;
locCurrVal = locNextVal;
}
__devCurrVal[i] = locCurrVal;
}
}
void printResult() {
for (int i = 0; i < totalPoints; i++) {
printf("%6.4f ", currVal[i]);
if ((i + 1) % 10 == 0)
printf("\n");
}
} | code for sm_80
Function : _Z9updateAllPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x170], PT ; /* 0x00005c0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff007624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc600078e00ff */
/*0090*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe20003f06270 */
/*00a0*/ IMAD.WIDE R2, R6, R3, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fca00078e0203 */
/*00b0*/ LDG.E R15, [R2.64] ; /* 0x00000006020f7981 */
/* 0x00016e000c1e1900 */
/*00c0*/ @!P0 BRA 0x3c0 ; /* 0x000002f000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R7, R0, -0x1, RZ ; /* 0xffffffff00077810 */
/* 0x000fe20007ffe0ff */
/*00e0*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe20000000000 */
/*00f0*/ SHF.R.S32.HI R5, RZ, 0x1f, R6 ; /* 0x0000001fff057819 */
/* 0x000fe40000011406 */
/*0100*/ ISETP.GE.U32.AND P2, PT, R7, 0x3, PT ; /* 0x000000030700780c */
/* 0x000fe20003f46070 */
/*0110*/ ULDC UR5, c[0x0][0x170] ; /* 0x00005c0000057ab9 */
/* 0x000fe20000000800 */
/*0120*/ LEA R4, P0, R6, c[0x0][0x160], 0x2 ; /* 0x0000580006047a11 */
/* 0x000fe200078010ff */
/*0130*/ UIADD3 UR4, -UR4, UR5, URZ ; /* 0x0000000504047290 */
/* 0x000fc6000fffe13f */
/*0140*/ LEA.HI.X R5, R6, c[0x0][0x164], R5, 0x2, P0 ; /* 0x0000590006057a11 */
/* 0x000fe400000f1405 */
/*0150*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe400078ec0ff */
/*0160*/ ISETP.NE.AND P0, PT, R6, UR4, PT ; /* 0x0000000406007c0c */
/* 0x000fe2000bf05270 */
/*0170*/ LDG.E R14, [R4.64] ; /* 0x00000006040e7981 */
/* 0x000362000c1e1900 */
/*0180*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f25270 */
/*0190*/ ISETP.EQ.OR P0, PT, R6, RZ, !P0 ; /* 0x000000ff0600720c */
/* 0x000fe20004702670 */
/*01a0*/ @!P2 BRA 0x320 ; /* 0x000001700000a947 */
/* 0x000ff40003800000 */
/*01b0*/ IADD3 R4, -R0, c[0x0][0x174], RZ ; /* 0x00005d0000047a10 */
/* 0x002fc60007ffe1ff */
/*01c0*/ F2F.F64.F32 R6, R15 ; /* 0x0000000f00067310 */
/* 0x020fe20000201800 */
/*01d0*/ IADD3 R4, R4, -0x4, RZ ; /* 0xfffffffc04047810 */
/* 0x000fc80007ffe0ff */
/*01e0*/ ISETP.NE.AND P2, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f45270 */
/*01f0*/ F2F.F64.F32 R8, R14 ; /* 0x0000000e00087310 */
/* 0x000e640000201800 */
/*0200*/ DFMA R8, R6, c[0x2][0x0], -R8 ; /* 0x0080000006087a2b */
/* 0x002e540000000808 */
/*0210*/ F2F.F32.F64 R8, R8 ; /* 0x0000000800087310 */
/* 0x002e700000301000 */
/*0220*/ F2F.F64.F32 R10, R8 ; /* 0x00000008000a7310 */
/* 0x002e640000201800 */
/*0230*/ FSEL R10, R10, RZ, !P0 ; /* 0x000000ff0a0a7208 */
/* 0x002fc40004000000 */
/*0240*/ FSEL R11, R11, RZ, !P0 ; /* 0x000000ff0b0b7208 */
/* 0x000fcc0004000000 */
/*0250*/ DFMA R6, R10, c[0x2][0x0], -R6 ; /* 0x008000000a067a2b */
/* 0x000e540000000806 */
/*0260*/ F2F.F32.F64 R6, R6 ; /* 0x0000000600067310 */
/* 0x002e700000301000 */
/*0270*/ F2F.F64.F32 R12, R6 ; /* 0x00000006000c7310 */
/* 0x002e640000201800 */
/*0280*/ FSEL R12, R12, RZ, !P0 ; /* 0x000000ff0c0c7208 */
/* 0x002fc40004000000 */
/*0290*/ FSEL R13, R13, RZ, !P0 ; /* 0x000000ff0d0d7208 */
/* 0x000fcc0004000000 */
/*02a0*/ DFMA R10, R12, c[0x2][0x0], -R10 ; /* 0x008000000c0a7a2b */
/* 0x000e54000000080a */
/*02b0*/ F2F.F32.F64 R10, R10 ; /* 0x0000000a000a7310 */
/* 0x002e640000301000 */
/*02c0*/ FSEL R14, R10, RZ, !P0 ; /* 0x000000ff0a0e7208 */
/* 0x002fcc0004000000 */
/*02d0*/ F2F.F64.F32 R8, R14 ; /* 0x0000000e00087310 */
/* 0x000e640000201800 */
/*02e0*/ DFMA R8, R8, c[0x2][0x0], -R12 ; /* 0x0080000008087a2b */
/* 0x002e54000000080c */
/*02f0*/ F2F.F32.F64 R8, R8 ; /* 0x0000000800087310 */
/* 0x002e640000301000 */
/*0300*/ FSEL R15, R8, RZ, !P0 ; /* 0x000000ff080f7208 */
/* 0x002fe20004000000 */
/*0310*/ @P2 BRA 0x1c0 ; /* 0xfffffea000002947 */
/* 0x000fea000383ffff */
/*0320*/ @!P1 BRA 0x3c0 ; /* 0x0000009000009947 */
/* 0x000fea0003800000 */
/*0330*/ F2F.F64.F32 R6, R14 ; /* 0x0000000e00067310 */
/* 0x0205e20000201800 */
/*0340*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fc80007ffe0ff */
/*0350*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc60003f25270 */
/*0360*/ F2F.F64.F32 R4, R15 ; /* 0x0000000f00047310 */
/* 0x002e620000201800 */
/*0370*/ IMAD.MOV.U32 R14, RZ, RZ, R15 ; /* 0x000000ffff0e7224 */
/* 0x004fe200078e000f */
/*0380*/ DFMA R4, R4, c[0x2][0x0], -R6 ; /* 0x0080000004047a2b */
/* 0x002e540000000806 */
/*0390*/ F2F.F32.F64 R4, R4 ; /* 0x0000000400047310 */
/* 0x002e640000301000 */
/*03a0*/ FSEL R15, R4, RZ, !P0 ; /* 0x000000ff040f7208 */
/* 0x002fe20004000000 */
/*03b0*/ @P1 BRA 0x330 ; /* 0xffffff7000001947 */
/* 0x000fea000383ffff */
/*03c0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x020fe2000c101906 */
/*03d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03e0*/ BRA 0x3e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8initLinePfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000800 */
/*0070*/ I2F R4, R0 ; /* 0x0000000000047306 */
/* 0x000fe20000201400 */
/*0080*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*0090*/ BSSY B0, 0x170 ; /* 0x000000d000007945 */
/* 0x000ff00003800000 */
/*00a0*/ I2F R3, UR4 ; /* 0x0000000400037d06 */
/* 0x000e220008201400 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fce0000000a00 */
/*00c0*/ MUFU.RCP R2, R3 ; /* 0x0000000300027308 */
/* 0x001e300000001000 */
/*00d0*/ FCHK P0, R4, R3 ; /* 0x0000000304007302 */
/* 0x000e620000000000 */
/*00e0*/ FFMA R5, -R3, R2, 1 ; /* 0x3f80000003057423 */
/* 0x001fc80000000102 */
/*00f0*/ FFMA R5, R2, R5, R2 ; /* 0x0000000502057223 */
/* 0x000fc80000000002 */
/*0100*/ FFMA R2, R4, R5, RZ ; /* 0x0000000504027223 */
/* 0x000fc800000000ff */
/*0110*/ FFMA R6, -R3, R2, R4 ; /* 0x0000000203067223 */
/* 0x000fc80000000104 */
/*0120*/ FFMA R8, R5, R6, R2 ; /* 0x0000000605087223 */
/* 0x000fe20000000002 */
/*0130*/ @!P0 BRA 0x160 ; /* 0x0000002000008947 */
/* 0x002fea0003800000 */
/*0140*/ MOV R2, 0x160 ; /* 0x0000016000027802 */
/* 0x000fe40000000f00 */
/*0150*/ CALL.REL.NOINC 0x220 ; /* 0x000000c000007944 */
/* 0x000fea0003c00000 */
/*0160*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0170*/ F2F.F64.F32 R2, R8 ; /* 0x0000000800027310 */
/* 0x000e220000201800 */
/*0180*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fc800078e00ff */
/*0190*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*01a0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fe200078e0207 */
/*01b0*/ DMUL R2, R2, c[0x2][0x0] ; /* 0x0080000002027a28 */
/* 0x001e140000000000 */
/*01c0*/ F2F.F32.F64 R2, R2 ; /* 0x0000000200027310 */
/* 0x001e240000301000 */
/*01d0*/ FMUL.RZ R9, R2, 0.15915493667125701904 ; /* 0x3e22f98302097820 */
/* 0x001fcc000040c000 */
/*01e0*/ MUFU.SIN R9, R9 ; /* 0x0000000900097308 */
/* 0x000e240000000400 */
/*01f0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x001fe8000c101904 */
/*0200*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ SHF.R.U32.HI R6, RZ, 0x17, R3.reuse ; /* 0x00000017ff067819 */
/* 0x100fe20000011603 */
/*0230*/ BSSY B1, 0x880 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0240*/ SHF.R.U32.HI R5, RZ, 0x17, R4.reuse ; /* 0x00000017ff057819 */
/* 0x100fe20000011604 */
/*0250*/ IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0004 */
/*0260*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fe200078ec0ff */
/*0270*/ IMAD.MOV.U32 R8, RZ, RZ, R3 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0003 */
/*0280*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fc400078ec0ff */
/*0290*/ IADD3 R11, R6, -0x1, RZ ; /* 0xffffffff060b7810 */
/* 0x000fe40007ffe0ff */
/*02a0*/ IADD3 R10, R5, -0x1, RZ ; /* 0xffffffff050a7810 */
/* 0x000fe40007ffe0ff */
/*02b0*/ ISETP.GT.U32.AND P0, PT, R11, 0xfd, PT ; /* 0x000000fd0b00780c */
/* 0x000fc80003f04070 */
/*02c0*/ ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ; /* 0x000000fd0a00780c */
/* 0x000fda0000704470 */
/*02d0*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*02e0*/ @!P0 BRA 0x460 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*02f0*/ FSETP.GTU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f1c200 */
/*0300*/ FSETP.GTU.FTZ.AND P1, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fc80003f3c200 */
/*0310*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0320*/ @P0 BRA 0x860 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0330*/ LOP3.LUT P0, RZ, R8, 0x7fffffff, R7, 0xc8, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000780c807 */
/*0340*/ @!P0 BRA 0x840 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0350*/ FSETP.NEU.FTZ.AND P2, PT, |R4|.reuse, +INF , PT ; /* 0x7f8000000400780b */
/* 0x040fe40003f5d200 */
/*0360*/ FSETP.NEU.FTZ.AND P1, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fe40003f3d200 */
/*0370*/ FSETP.NEU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fd60003f1d200 */
/*0380*/ @!P1 BRA !P2, 0x840 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0390*/ LOP3.LUT P2, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000784c0ff */
/*03a0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*03b0*/ @P1 BRA 0x820 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*03c0*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000782c0ff */
/*03d0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*03e0*/ @P0 BRA 0x7f0 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*03f0*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f06270 */
/*0400*/ ISETP.GE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fd60003f26270 */
/*0410*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff090224 */
/* 0x000fe400078e00ff */
/*0420*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; /* 0xffffffc0ff098424 */
/* 0x000fe400078e00ff */
/*0430*/ @!P0 FFMA R7, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004078823 */
/* 0x000fe400000000ff */
/*0440*/ @!P1 FFMA R8, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003089823 */
/* 0x000fe200000000ff */
/*0450*/ @!P1 IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009099810 */
/* 0x000fe40007ffe0ff */
/*0460*/ LEA R3, R6, 0xc0800000, 0x17 ; /* 0xc080000006037811 */
/* 0x000fe200078eb8ff */
/*0470*/ BSSY B2, 0x7e0 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*0480*/ IADD3 R5, R5, -0x7f, RZ ; /* 0xffffff8105057810 */
/* 0x000fc60007ffe0ff */
/*0490*/ IMAD.IADD R8, R8, 0x1, -R3 ; /* 0x0000000108087824 */
/* 0x000fe200078e0a03 */
/*04a0*/ IADD3 R6, R5.reuse, 0x7f, -R6 ; /* 0x0000007f05067810 */
/* 0x040fe20007ffe806 */
/*04b0*/ IMAD R7, R5, -0x800000, R7 ; /* 0xff80000005077824 */
/* 0x000fe400078e0207 */
/*04c0*/ MUFU.RCP R3, R8 ; /* 0x0000000800037308 */
/* 0x000e220000001000 */
/*04d0*/ FADD.FTZ R4, -R8, -RZ ; /* 0x800000ff08047221 */
/* 0x000fe40000010100 */
/*04e0*/ IMAD.IADD R6, R6, 0x1, R9 ; /* 0x0000000106067824 */
/* 0x000fe400078e0209 */
/*04f0*/ FFMA R10, R3, R4, 1 ; /* 0x3f800000030a7423 */
/* 0x001fc80000000004 */
/*0500*/ FFMA R12, R3, R10, R3 ; /* 0x0000000a030c7223 */
/* 0x000fc80000000003 */
/*0510*/ FFMA R3, R7, R12, RZ ; /* 0x0000000c07037223 */
/* 0x000fc800000000ff */
/*0520*/ FFMA R10, R4, R3, R7 ; /* 0x00000003040a7223 */
/* 0x000fc80000000007 */
/*0530*/ FFMA R11, R12, R10, R3 ; /* 0x0000000a0c0b7223 */
/* 0x000fc80000000003 */
/*0540*/ FFMA R7, R4, R11, R7 ; /* 0x0000000b04077223 */
/* 0x000fc80000000007 */
/*0550*/ FFMA R3, R12, R7, R11 ; /* 0x000000070c037223 */
/* 0x000fca000000000b */
/*0560*/ SHF.R.U32.HI R4, RZ, 0x17, R3 ; /* 0x00000017ff047819 */
/* 0x000fc80000011603 */
/*0570*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fca00078ec0ff */
/*0580*/ IMAD.IADD R8, R4, 0x1, R6 ; /* 0x0000000104087824 */
/* 0x000fca00078e0206 */
/*0590*/ IADD3 R4, R8, -0x1, RZ ; /* 0xffffffff08047810 */
/* 0x000fc80007ffe0ff */
/*05a0*/ ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ; /* 0x000000fe0400780c */
/* 0x000fda0003f06070 */
/*05b0*/ @!P0 BRA 0x7c0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*05c0*/ ISETP.GT.AND P0, PT, R8, 0xfe, PT ; /* 0x000000fe0800780c */
/* 0x000fda0003f04270 */
/*05d0*/ @P0 BRA 0x790 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*05e0*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f06270 */
/*05f0*/ @P0 BRA 0x7d0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0600*/ ISETP.GE.AND P0, PT, R8, -0x18, PT ; /* 0xffffffe80800780c */
/* 0x000fe40003f06270 */
/*0610*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*0620*/ @!P0 BRA 0x7d0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0630*/ FFMA.RZ R4, R12, R7.reuse, R11.reuse ; /* 0x000000070c047223 */
/* 0x180fe2000000c00b */
/*0640*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f45270 */
/*0650*/ FFMA.RM R5, R12, R7.reuse, R11.reuse ; /* 0x000000070c057223 */
/* 0x180fe2000000400b */
/*0660*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f25270 */
/*0670*/ LOP3.LUT R6, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04067812 */
/* 0x000fe200078ec0ff */
/*0680*/ FFMA.RP R4, R12, R7, R11 ; /* 0x000000070c047223 */
/* 0x000fe2000000800b */
/*0690*/ IADD3 R7, R8, 0x20, RZ ; /* 0x0000002008077810 */
/* 0x000fe20007ffe0ff */
/*06a0*/ IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0a08 */
/*06b0*/ LOP3.LUT R6, R6, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000006067812 */
/* 0x000fe400078efcff */
/*06c0*/ FSETP.NEU.FTZ.AND P0, PT, R4, R5, PT ; /* 0x000000050400720b */
/* 0x000fc40003f1d000 */
/*06d0*/ SHF.L.U32 R7, R6, R7, RZ ; /* 0x0000000706077219 */
/* 0x000fe400000006ff */
/*06e0*/ SEL R5, R8, RZ, P2 ; /* 0x000000ff08057207 */
/* 0x000fe40001000000 */
/*06f0*/ ISETP.NE.AND P1, PT, R7, RZ, P1 ; /* 0x000000ff0700720c */
/* 0x000fe40000f25270 */
/*0700*/ SHF.R.U32.HI R5, RZ, R5, R6 ; /* 0x00000005ff057219 */
/* 0x000fe40000011606 */
/*0710*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0720*/ SHF.R.U32.HI R7, RZ, 0x1, R5 ; /* 0x00000001ff077819 */
/* 0x000fc40000011605 */
/*0730*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*0740*/ LOP3.LUT R4, R4, 0x1, R7, 0xf8, !PT ; /* 0x0000000104047812 */
/* 0x000fc800078ef807 */
/*0750*/ LOP3.LUT R4, R4, R5, RZ, 0xc0, !PT ; /* 0x0000000504047212 */
/* 0x000fca00078ec0ff */
/*0760*/ IMAD.IADD R4, R7, 0x1, R4 ; /* 0x0000000107047824 */
/* 0x000fca00078e0204 */
/*0770*/ LOP3.LUT R3, R4, R3, RZ, 0xfc, !PT ; /* 0x0000000304037212 */
/* 0x000fe200078efcff */
/*0780*/ BRA 0x7d0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0790*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*07a0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*07b0*/ BRA 0x7d0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*07c0*/ IMAD R3, R6, 0x800000, R3 ; /* 0x0080000006037824 */
/* 0x000fe400078e0203 */
/*07d0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*07e0*/ BRA 0x870 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*07f0*/ LOP3.LUT R3, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fc800078e4807 */
/*0800*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0810*/ BRA 0x870 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0820*/ LOP3.LUT R3, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fe200078e4807 */
/*0830*/ BRA 0x870 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0840*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*0850*/ BRA 0x870 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0860*/ FADD.FTZ R3, R4, R3 ; /* 0x0000000304037221 */
/* 0x000fe40000010000 */
/*0870*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0880*/ IMAD.MOV.U32 R8, RZ, RZ, R3 ; /* 0x000000ffff087224 */
/* 0x001fe400078e0003 */
/*0890*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*08a0*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff75002007950 */
/* 0x000fea0003c3ffff */
/*08b0*/ BRA 0x8b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**
* Concurrent Wave Equation
* Compilation Command: nvcc cuda1.cu -o cuda1
* This program was originally written in serial method by the teacher.
*/
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#define MAXPOINTS 1000000
#define MAXSTEPS 1000000
#define MINPOINTS 20
static void handleError(cudaError_t err, const char *file, int line) {
if (err != cudaSuccess) {
printf("%s in %s at line %d\n", cudaGetErrorString(err), file, line);
exit(EXIT_FAILURE);
}
}
#define HANDLE_ERROR(err) (handleError(err, __FILE__, __LINE__))
void checkParam();
__global__ void initLine(float*, float*, int);
__global__ void updateAll(float*, float*, int, int);
void printResult();
int totalSteps, totalPoints, allocPoints;
float *currVal;
float *devCurrVal, *devPrevVal;
int main(int argc, char *argv[]) {
sscanf(argv[1], "%d", &totalPoints);
sscanf(argv[2], "%d", &totalSteps);
checkParam();
allocPoints = totalPoints + 256;
currVal = (float*) malloc(allocPoints * sizeof(float));
if (!currVal)
exit(EXIT_FAILURE);
HANDLE_ERROR(cudaMalloc((void**) &devCurrVal, allocPoints * sizeof(float)));
HANDLE_ERROR(cudaMalloc((void**) &devPrevVal, allocPoints * sizeof(float)));
dim3 threadsPerBlock(256);
dim3 numOfBlocks(allocPoints/256);
printf("Initializing points on the line...\n");
initLine<<<numOfBlocks, threadsPerBlock>>>(devPrevVal, devCurrVal, totalPoints);
printf("Updating all points for all time steps...\n");
updateAll<<<numOfBlocks, threadsPerBlock>>>(devPrevVal, devCurrVal, totalPoints, totalSteps);
printf("Printing final results...\n");
HANDLE_ERROR(cudaMemcpy(currVal, devCurrVal, allocPoints * sizeof(float), cudaMemcpyDeviceToHost));
printResult();
printf("\nDone.\n\n");
cudaFree(devCurrVal);
cudaFree(devPrevVal);
free(currVal);
return EXIT_SUCCESS;
}
void checkParam() {
char temp[20];
while ((totalPoints < MINPOINTS) || (totalPoints > MAXPOINTS)) {
printf("Enter number of points along vibrating string [%d-%d]: ", MINPOINTS, MAXPOINTS);
scanf("%s", temp);
totalPoints = atoi(temp);
if ((totalPoints < MINPOINTS) || (totalPoints > MAXPOINTS))
printf("Invalid. Please enter value between %d and %d.\n", MINPOINTS, MAXPOINTS);
}
while ((totalSteps < 1) || (totalSteps > MAXSTEPS)) {
printf("Enter number of time steps [1-%d]: ", MAXSTEPS);
scanf("%s", temp);
totalSteps = atoi(temp);
if ((totalSteps < 1) || (totalSteps > MAXSTEPS))
printf("Invalid. Please enter value between 1 and %d.\n", MAXSTEPS);
}
printf("Using points = %d, steps = %d\n", totalPoints, totalSteps);
}
__global__ void initLine(float *__devPrevVal, float *__devCurrVal, int __totalPoints) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < __totalPoints) {
float x = (float) i / (__totalPoints - 1);
__devPrevVal[i] = __devCurrVal[i] = __sinf(6.28318530 * x);
}
}
__global__ void updateAll(float *__devPrevVal, float *__devCurrVal, int __totalPoints, int __totalSteps) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < __totalPoints) {
float locPrevVal = __devPrevVal[i], locCurrVal = __devCurrVal[i] , locNextVal;
for (int j = 0; j < __totalSteps; j++) {
if ((i == 0) || (i == __totalPoints - 1))
locNextVal = 0.0;
else
locNextVal = 1.82 * locCurrVal - locPrevVal;
locPrevVal = locCurrVal;
locCurrVal = locNextVal;
}
__devCurrVal[i] = locCurrVal;
}
}
void printResult() {
for (int i = 0; i < totalPoints; i++) {
printf("%6.4f ", currVal[i]);
if ((i + 1) % 10 == 0)
printf("\n");
}
} | .file "tmpxft_00083f02_00000000-6_cuda1.cudafe1.cpp"
.text
#APP
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s in %s at line %d\n"
#NO_APP
.text
.type _ZL11handleError9cudaErrorPKci, @function
_ZL11handleError9cudaErrorPKci:
.LFB2057:
.cfi_startproc
testl %edi, %edi
jne .L6
ret
.L6:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbx
movl %edx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rdx
movl %ebp, %r8d
movq %rbx, %rcx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _ZL11handleError9cudaErrorPKci, .-_ZL11handleError9cudaErrorPKci
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Enter number of points along vibrating string [%d-%d]: "
.section .rodata.str1.1
.LC2:
.string "%s"
.section .rodata.str1.8
.align 8
.LC3:
.string "Invalid. Please enter value between %d and %d.\n"
.align 8
.LC4:
.string "Enter number of time steps [1-%d]: "
.align 8
.LC5:
.string "Invalid. Please enter value between 1 and %d.\n"
.align 8
.LC6:
.string "Using points = %d, steps = %d\n"
.text
.globl _Z10checkParamv
.type _Z10checkParamv, @function
_Z10checkParamv:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq .LC1(%rip), %r12
movq %rsp, %rbx
leaq .LC2(%rip), %rbp
.L11:
movl totalPoints(%rip), %eax
subl $20, %eax
cmpl $999980, %eax
jbe .L20
movl $1000000, %ecx
movl $20, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl $10, %edx
movl $0, %esi
movq %rbx, %rdi
call __isoc23_strtol@PLT
movl %eax, totalPoints(%rip)
subl $20, %eax
cmpl $999980, %eax
jbe .L11
movl $1000000, %ecx
movl $20, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L11
.L20:
leaq .LC4(%rip), %r12
movq %rsp, %rbx
leaq .LC2(%rip), %rbp
.L14:
movl totalSteps(%rip), %ecx
leal -1(%rcx), %eax
cmpl $999999, %eax
jbe .L21
movl $1000000, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl $10, %edx
movl $0, %esi
movq %rbx, %rdi
call __isoc23_strtol@PLT
movl %eax, totalSteps(%rip)
subl $1, %eax
cmpl $999999, %eax
jbe .L14
movl $1000000, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L14
.L21:
movl totalPoints(%rip), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z10checkParamv, .-_Z10checkParamv
.section .rodata.str1.1
.LC7:
.string "%6.4f "
.LC8:
.string "\n"
.text
.globl _Z11printResultv
.type _Z11printResultv, @function
_Z11printResultv:
.LFB2060:
.cfi_startproc
endbr64
cmpl $0, totalPoints(%rip)
jle .L29
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl $0, %ebp
movl $0, %ebx
leaq .LC7(%rip), %r12
leaq .LC8(%rip), %r13
jmp .L26
.L25:
addq $4, %rbp
cmpl totalPoints(%rip), %ebx
jge .L32
.L26:
movq currVal(%rip), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbp), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addl $1, %ebx
movslq %ebx, %rax
imulq $1717986919, %rax, %rax
sarq $34, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,4), %eax
addl %eax, %eax
cmpl %eax, %ebx
jne .L25
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L25
.L32:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
ret
.cfi_endproc
.LFE2060:
.size _Z11printResultv, .-_Z11printResultv
.globl _Z30__device_stub__Z8initLinePfS_iPfS_i
.type _Z30__device_stub__Z8initLinePfS_iPfS_i, @function
_Z30__device_stub__Z8initLinePfS_iPfS_i:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L37
.L33:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8initLinePfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L33
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z30__device_stub__Z8initLinePfS_iPfS_i, .-_Z30__device_stub__Z8initLinePfS_iPfS_i
.globl _Z8initLinePfS_i
.type _Z8initLinePfS_i, @function
_Z8initLinePfS_i:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z8initLinePfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z8initLinePfS_i, .-_Z8initLinePfS_i
.globl _Z32__device_stub__Z9updateAllPfS_iiPfS_ii
.type _Z32__device_stub__Z9updateAllPfS_iiPfS_ii, @function
_Z32__device_stub__Z9updateAllPfS_iiPfS_ii:
.LFB2087:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L45
.L41:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L46
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9updateAllPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L41
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z32__device_stub__Z9updateAllPfS_iiPfS_ii, .-_Z32__device_stub__Z9updateAllPfS_iiPfS_ii
.globl _Z9updateAllPfS_ii
.type _Z9updateAllPfS_ii, @function
_Z9updateAllPfS_ii:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9updateAllPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z9updateAllPfS_ii, .-_Z9updateAllPfS_ii
.section .rodata.str1.1
.LC9:
.string "%d"
.section .rodata.str1.8
.align 8
.LC10:
.string "/home/ubuntu/Datasets/stackv2/train-structured/yuwen41200/parallel-programming/master/cuda/cuda1.cu"
.align 8
.LC11:
.string "Initializing points on the line...\n"
.align 8
.LC12:
.string "Updating all points for all time steps...\n"
.section .rodata.str1.1
.LC13:
.string "Printing final results...\n"
.LC14:
.string "\nDone.\n\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movq %rsi, %rbx
movq 8(%rsi), %rdi
leaq totalPoints(%rip), %rdx
leaq .LC9(%rip), %rbp
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
movq 16(%rbx), %rdi
leaq totalSteps(%rip), %rdx
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
call _Z10checkParamv
movl totalPoints(%rip), %eax
addl $256, %eax
movl %eax, allocPoints(%rip)
cltq
leaq 0(,%rax,4), %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, currVal(%rip)
testq %rax, %rax
je .L54
movq %rbx, %rsi
leaq devCurrVal(%rip), %rdi
call cudaMalloc@PLT
movl %eax, %edi
movl $43, %edx
leaq .LC10(%rip), %rbx
movq %rbx, %rsi
call _ZL11handleError9cudaErrorPKci
movslq allocPoints(%rip), %rsi
salq $2, %rsi
leaq devPrevVal(%rip), %rdi
call cudaMalloc@PLT
movl %eax, %edi
movl $44, %edx
movq %rbx, %rsi
call _ZL11handleError9cudaErrorPKci
movl $256, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl allocPoints(%rip), %edx
leal 255(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $8, %eax
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 16(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movq 20(%rsp), %rdi
movl 28(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L55
.L51:
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 16(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movq 20(%rsp), %rdi
movl 28(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L56
.L52:
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq allocPoints(%rip), %rdx
salq $2, %rdx
movl $2, %ecx
movq devCurrVal(%rip), %rsi
movq currVal(%rip), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $56, %edx
leaq .LC10(%rip), %rsi
call _ZL11handleError9cudaErrorPKci
call _Z11printResultv
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq devCurrVal(%rip), %rdi
call cudaFree@PLT
movq devPrevVal(%rip), %rdi
call cudaFree@PLT
movq currVal(%rip), %rdi
call free@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
movl $1, %edi
call exit@PLT
.L55:
movl totalPoints(%rip), %edx
movq devCurrVal(%rip), %rsi
movq devPrevVal(%rip), %rdi
call _Z30__device_stub__Z8initLinePfS_iPfS_i
jmp .L51
.L56:
movl totalSteps(%rip), %ecx
movl totalPoints(%rip), %edx
movq devCurrVal(%rip), %rsi
movq devPrevVal(%rip), %rdi
call _Z32__device_stub__Z9updateAllPfS_iiPfS_ii
jmp .L52
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC15:
.string "_Z9updateAllPfS_ii"
.LC16:
.string "_Z8initLinePfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z9updateAllPfS_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z8initLinePfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl devPrevVal
.bss
.align 8
.type devPrevVal, @object
.size devPrevVal, 8
devPrevVal:
.zero 8
.globl devCurrVal
.align 8
.type devCurrVal, @object
.size devCurrVal, 8
devCurrVal:
.zero 8
.globl currVal
.align 8
.type currVal, @object
.size currVal, 8
currVal:
.zero 8
.globl allocPoints
.align 4
.type allocPoints, @object
.size allocPoints, 4
allocPoints:
.zero 4
.globl totalPoints
.align 4
.type totalPoints, @object
.size totalPoints, 4
totalPoints:
.zero 4
.globl totalSteps
.align 4
.type totalSteps, @object
.size totalSteps, 4
totalSteps:
.zero 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
* Concurrent Wave Equation
* Compilation Command: nvcc cuda1.cu -o cuda1
* This program was originally written in serial method by the teacher.
*/
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#define MAXPOINTS 1000000
#define MAXSTEPS 1000000
#define MINPOINTS 20
static void handleError(cudaError_t err, const char *file, int line) {
if (err != cudaSuccess) {
printf("%s in %s at line %d\n", cudaGetErrorString(err), file, line);
exit(EXIT_FAILURE);
}
}
#define HANDLE_ERROR(err) (handleError(err, __FILE__, __LINE__))
void checkParam();
__global__ void initLine(float*, float*, int);
__global__ void updateAll(float*, float*, int, int);
void printResult();
int totalSteps, totalPoints, allocPoints;
float *currVal;
float *devCurrVal, *devPrevVal;
int main(int argc, char *argv[]) {
sscanf(argv[1], "%d", &totalPoints);
sscanf(argv[2], "%d", &totalSteps);
checkParam();
allocPoints = totalPoints + 256;
currVal = (float*) malloc(allocPoints * sizeof(float));
if (!currVal)
exit(EXIT_FAILURE);
HANDLE_ERROR(cudaMalloc((void**) &devCurrVal, allocPoints * sizeof(float)));
HANDLE_ERROR(cudaMalloc((void**) &devPrevVal, allocPoints * sizeof(float)));
dim3 threadsPerBlock(256);
dim3 numOfBlocks(allocPoints/256);
printf("Initializing points on the line...\n");
initLine<<<numOfBlocks, threadsPerBlock>>>(devPrevVal, devCurrVal, totalPoints);
printf("Updating all points for all time steps...\n");
updateAll<<<numOfBlocks, threadsPerBlock>>>(devPrevVal, devCurrVal, totalPoints, totalSteps);
printf("Printing final results...\n");
HANDLE_ERROR(cudaMemcpy(currVal, devCurrVal, allocPoints * sizeof(float), cudaMemcpyDeviceToHost));
printResult();
printf("\nDone.\n\n");
cudaFree(devCurrVal);
cudaFree(devPrevVal);
free(currVal);
return EXIT_SUCCESS;
}
void checkParam() {
char temp[20];
while ((totalPoints < MINPOINTS) || (totalPoints > MAXPOINTS)) {
printf("Enter number of points along vibrating string [%d-%d]: ", MINPOINTS, MAXPOINTS);
scanf("%s", temp);
totalPoints = atoi(temp);
if ((totalPoints < MINPOINTS) || (totalPoints > MAXPOINTS))
printf("Invalid. Please enter value between %d and %d.\n", MINPOINTS, MAXPOINTS);
}
while ((totalSteps < 1) || (totalSteps > MAXSTEPS)) {
printf("Enter number of time steps [1-%d]: ", MAXSTEPS);
scanf("%s", temp);
totalSteps = atoi(temp);
if ((totalSteps < 1) || (totalSteps > MAXSTEPS))
printf("Invalid. Please enter value between 1 and %d.\n", MAXSTEPS);
}
printf("Using points = %d, steps = %d\n", totalPoints, totalSteps);
}
__global__ void initLine(float *__devPrevVal, float *__devCurrVal, int __totalPoints) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < __totalPoints) {
float x = (float) i / (__totalPoints - 1);
__devPrevVal[i] = __devCurrVal[i] = __sinf(6.28318530 * x);
}
}
__global__ void updateAll(float *__devPrevVal, float *__devCurrVal, int __totalPoints, int __totalSteps) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < __totalPoints) {
float locPrevVal = __devPrevVal[i], locCurrVal = __devCurrVal[i] , locNextVal;
for (int j = 0; j < __totalSteps; j++) {
if ((i == 0) || (i == __totalPoints - 1))
locNextVal = 0.0;
else
locNextVal = 1.82 * locCurrVal - locPrevVal;
locPrevVal = locCurrVal;
locCurrVal = locNextVal;
}
__devCurrVal[i] = locCurrVal;
}
}
void printResult() {
for (int i = 0; i < totalPoints; i++) {
printf("%6.4f ", currVal[i]);
if ((i + 1) % 10 == 0)
printf("\n");
}
} | /**
* Concurrent Wave Equation
* Compilation Command: nvcc cuda1.cu -o cuda1
* This program was originally written in serial method by the teacher.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#define MAXPOINTS 1000000
#define MAXSTEPS 1000000
#define MINPOINTS 20
static void handleError(hipError_t err, const char *file, int line) {
if (err != hipSuccess) {
printf("%s in %s at line %d\n", hipGetErrorString(err), file, line);
exit(EXIT_FAILURE);
}
}
#define HANDLE_ERROR(err) (handleError(err, __FILE__, __LINE__))
void checkParam();
__global__ void initLine(float*, float*, int);
__global__ void updateAll(float*, float*, int, int);
void printResult();
int totalSteps, totalPoints, allocPoints;
float *currVal;
float *devCurrVal, *devPrevVal;
int main(int argc, char *argv[]) {
sscanf(argv[1], "%d", &totalPoints);
sscanf(argv[2], "%d", &totalSteps);
checkParam();
allocPoints = totalPoints + 256;
currVal = (float*) malloc(allocPoints * sizeof(float));
if (!currVal)
exit(EXIT_FAILURE);
HANDLE_ERROR(hipMalloc((void**) &devCurrVal, allocPoints * sizeof(float)));
HANDLE_ERROR(hipMalloc((void**) &devPrevVal, allocPoints * sizeof(float)));
dim3 threadsPerBlock(256);
dim3 numOfBlocks(allocPoints/256);
printf("Initializing points on the line...\n");
initLine<<<numOfBlocks, threadsPerBlock>>>(devPrevVal, devCurrVal, totalPoints);
printf("Updating all points for all time steps...\n");
updateAll<<<numOfBlocks, threadsPerBlock>>>(devPrevVal, devCurrVal, totalPoints, totalSteps);
printf("Printing final results...\n");
HANDLE_ERROR(hipMemcpy(currVal, devCurrVal, allocPoints * sizeof(float), hipMemcpyDeviceToHost));
printResult();
printf("\nDone.\n\n");
hipFree(devCurrVal);
hipFree(devPrevVal);
free(currVal);
return EXIT_SUCCESS;
}
void checkParam() {
char temp[20];
while ((totalPoints < MINPOINTS) || (totalPoints > MAXPOINTS)) {
printf("Enter number of points along vibrating string [%d-%d]: ", MINPOINTS, MAXPOINTS);
scanf("%s", temp);
totalPoints = atoi(temp);
if ((totalPoints < MINPOINTS) || (totalPoints > MAXPOINTS))
printf("Invalid. Please enter value between %d and %d.\n", MINPOINTS, MAXPOINTS);
}
while ((totalSteps < 1) || (totalSteps > MAXSTEPS)) {
printf("Enter number of time steps [1-%d]: ", MAXSTEPS);
scanf("%s", temp);
totalSteps = atoi(temp);
if ((totalSteps < 1) || (totalSteps > MAXSTEPS))
printf("Invalid. Please enter value between 1 and %d.\n", MAXSTEPS);
}
printf("Using points = %d, steps = %d\n", totalPoints, totalSteps);
}
__global__ void initLine(float *__devPrevVal, float *__devCurrVal, int __totalPoints) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < __totalPoints) {
float x = (float) i / (__totalPoints - 1);
__devPrevVal[i] = __devCurrVal[i] = __sinf(6.28318530 * x);
}
}
__global__ void updateAll(float *__devPrevVal, float *__devCurrVal, int __totalPoints, int __totalSteps) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < __totalPoints) {
float locPrevVal = __devPrevVal[i], locCurrVal = __devCurrVal[i] , locNextVal;
for (int j = 0; j < __totalSteps; j++) {
if ((i == 0) || (i == __totalPoints - 1))
locNextVal = 0.0;
else
locNextVal = 1.82 * locCurrVal - locPrevVal;
locPrevVal = locCurrVal;
locCurrVal = locNextVal;
}
__devCurrVal[i] = locCurrVal;
}
}
void printResult() {
for (int i = 0; i < totalPoints; i++) {
printf("%6.4f ", currVal[i]);
if ((i + 1) % 10 == 0)
printf("\n");
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /**
* Concurrent Wave Equation
* Compilation Command: nvcc cuda1.cu -o cuda1
* This program was originally written in serial method by the teacher.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#define MAXPOINTS 1000000
#define MAXSTEPS 1000000
#define MINPOINTS 20
static void handleError(hipError_t err, const char *file, int line) {
if (err != hipSuccess) {
printf("%s in %s at line %d\n", hipGetErrorString(err), file, line);
exit(EXIT_FAILURE);
}
}
#define HANDLE_ERROR(err) (handleError(err, __FILE__, __LINE__))
void checkParam();
__global__ void initLine(float*, float*, int);
__global__ void updateAll(float*, float*, int, int);
void printResult();
int totalSteps, totalPoints, allocPoints;
float *currVal;
float *devCurrVal, *devPrevVal;
int main(int argc, char *argv[]) {
sscanf(argv[1], "%d", &totalPoints);
sscanf(argv[2], "%d", &totalSteps);
checkParam();
allocPoints = totalPoints + 256;
currVal = (float*) malloc(allocPoints * sizeof(float));
if (!currVal)
exit(EXIT_FAILURE);
HANDLE_ERROR(hipMalloc((void**) &devCurrVal, allocPoints * sizeof(float)));
HANDLE_ERROR(hipMalloc((void**) &devPrevVal, allocPoints * sizeof(float)));
dim3 threadsPerBlock(256);
dim3 numOfBlocks(allocPoints/256);
printf("Initializing points on the line...\n");
initLine<<<numOfBlocks, threadsPerBlock>>>(devPrevVal, devCurrVal, totalPoints);
printf("Updating all points for all time steps...\n");
updateAll<<<numOfBlocks, threadsPerBlock>>>(devPrevVal, devCurrVal, totalPoints, totalSteps);
printf("Printing final results...\n");
HANDLE_ERROR(hipMemcpy(currVal, devCurrVal, allocPoints * sizeof(float), hipMemcpyDeviceToHost));
printResult();
printf("\nDone.\n\n");
hipFree(devCurrVal);
hipFree(devPrevVal);
free(currVal);
return EXIT_SUCCESS;
}
void checkParam() {
char temp[20];
while ((totalPoints < MINPOINTS) || (totalPoints > MAXPOINTS)) {
printf("Enter number of points along vibrating string [%d-%d]: ", MINPOINTS, MAXPOINTS);
scanf("%s", temp);
totalPoints = atoi(temp);
if ((totalPoints < MINPOINTS) || (totalPoints > MAXPOINTS))
printf("Invalid. Please enter value between %d and %d.\n", MINPOINTS, MAXPOINTS);
}
while ((totalSteps < 1) || (totalSteps > MAXSTEPS)) {
printf("Enter number of time steps [1-%d]: ", MAXSTEPS);
scanf("%s", temp);
totalSteps = atoi(temp);
if ((totalSteps < 1) || (totalSteps > MAXSTEPS))
printf("Invalid. Please enter value between 1 and %d.\n", MAXSTEPS);
}
printf("Using points = %d, steps = %d\n", totalPoints, totalSteps);
}
__global__ void initLine(float *__devPrevVal, float *__devCurrVal, int __totalPoints) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < __totalPoints) {
float x = (float) i / (__totalPoints - 1);
__devPrevVal[i] = __devCurrVal[i] = __sinf(6.28318530 * x);
}
}
__global__ void updateAll(float *__devPrevVal, float *__devCurrVal, int __totalPoints, int __totalSteps) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < __totalPoints) {
float locPrevVal = __devPrevVal[i], locCurrVal = __devCurrVal[i] , locNextVal;
for (int j = 0; j < __totalSteps; j++) {
if ((i == 0) || (i == __totalPoints - 1))
locNextVal = 0.0;
else
locNextVal = 1.82 * locCurrVal - locPrevVal;
locPrevVal = locCurrVal;
locCurrVal = locNextVal;
}
__devCurrVal[i] = locCurrVal;
}
}
void printResult() {
for (int i = 0; i < totalPoints; i++) {
printf("%6.4f ", currVal[i]);
if ((i + 1) % 10 == 0)
printf("\n");
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8initLinePfS_i
.globl _Z8initLinePfS_i
.p2align 8
.type _Z8initLinePfS_i,@function
_Z8initLinePfS_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s2, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_2
s_add_i32 s2, s2, -1
v_cvt_f32_i32_e32 v0, v1
v_cvt_f32_i32_e32 v2, s2
s_mov_b32 s3, 0x401921fb
s_mov_b32 s2, 0x53c8d4f1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v3, null, v2, v2, v0
v_div_scale_f32 v6, vcc_lo, v0, v2, v0
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v5, v4
v_mul_f32_e32 v5, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v3, v5, v6
v_fmac_f32_e32 v5, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, -v3, v5, v6
v_div_fmas_f32 v3, v3, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v0, v3, v2, v0
v_cvt_f64_f32_e32 v[2:3], v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f64 v[2:3], v[2:3], s[2:3]
s_load_b128 s[0:3], s[0:1], 0x0
v_cvt_f32_f64_e32 v0, v[2:3]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v3, 0.15915494, v0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sin_f32_e32 v4, v3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[2:3], v4, off
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8initLinePfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8initLinePfS_i, .Lfunc_end0-_Z8initLinePfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9updateAllPfS_ii
.globl _Z9updateAllPfS_ii
.p2align 8
.type _Z9updateAllPfS_ii,@function
_Z9updateAllPfS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v2
s_cbranch_execz .LBB1_8
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x8
s_load_b32 s2, s[0:1], 0x14
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v4, vcc_lo
s_cmp_lt_i32 s2, 1
global_load_b32 v5, v[0:1], off
s_cbranch_scc1 .LBB1_7
s_load_b64 s[0:1], s[0:1], 0x0
s_add_i32 s3, s3, -1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v2
v_cmp_ne_u32_e64 s0, s3, v2
s_mov_b32 s1, 0x3ffd1eb8
global_load_b32 v3, v[3:4], off
s_and_b32 s3, vcc_lo, s0
s_mov_b32 s0, 0x51eb851f
.LBB1_3:
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_2)
v_dual_mov_b32 v2, v5 :: v_dual_mov_b32 v5, 0
s_and_saveexec_b32 s4, s3
s_cbranch_execz .LBB1_5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[4:5], v2
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[6:7], v3
v_fma_f64 v[3:4], v[4:5], s[0:1], -v[6:7]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v5, v[3:4]
.LBB1_5:
s_or_b32 exec_lo, exec_lo, s4
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 0
s_cbranch_scc1 .LBB1_7
s_waitcnt vmcnt(0)
v_mov_b32_e32 v3, v2
s_branch .LBB1_3
.LBB1_7:
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v5, off
.LBB1_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9updateAllPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z9updateAllPfS_ii, .Lfunc_end1-_Z9updateAllPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
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.size: 4
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.size: 4
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.size: 4
.value_kind: hidden_block_count_z
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.size: 2
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.size: 2
.value_kind: hidden_group_size_y
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.size: 2
.value_kind: hidden_group_size_z
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.size: 2
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.size: 2
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.size: 2
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.value_kind: hidden_global_offset_z
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.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8initLinePfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8initLinePfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
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.size: 8
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.language: OpenCL C
.language_version:
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- 0
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.name: _Z9updateAllPfS_ii
.private_segment_fixed_size: 0
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.sgpr_spill_count: 0
.symbol: _Z9updateAllPfS_ii.kd
.uniform_work_group_size: 1
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.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /**
* Concurrent Wave Equation
* Compilation Command: nvcc cuda1.cu -o cuda1
* This program was originally written in serial method by the teacher.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#define MAXPOINTS 1000000
#define MAXSTEPS 1000000
#define MINPOINTS 20
static void handleError(hipError_t err, const char *file, int line) {
if (err != hipSuccess) {
printf("%s in %s at line %d\n", hipGetErrorString(err), file, line);
exit(EXIT_FAILURE);
}
}
#define HANDLE_ERROR(err) (handleError(err, __FILE__, __LINE__))
void checkParam();
__global__ void initLine(float*, float*, int);
__global__ void updateAll(float*, float*, int, int);
void printResult();
int totalSteps, totalPoints, allocPoints;
float *currVal;
float *devCurrVal, *devPrevVal;
int main(int argc, char *argv[]) {
sscanf(argv[1], "%d", &totalPoints);
sscanf(argv[2], "%d", &totalSteps);
checkParam();
allocPoints = totalPoints + 256;
currVal = (float*) malloc(allocPoints * sizeof(float));
if (!currVal)
exit(EXIT_FAILURE);
HANDLE_ERROR(hipMalloc((void**) &devCurrVal, allocPoints * sizeof(float)));
HANDLE_ERROR(hipMalloc((void**) &devPrevVal, allocPoints * sizeof(float)));
dim3 threadsPerBlock(256);
dim3 numOfBlocks(allocPoints/256);
printf("Initializing points on the line...\n");
initLine<<<numOfBlocks, threadsPerBlock>>>(devPrevVal, devCurrVal, totalPoints);
printf("Updating all points for all time steps...\n");
updateAll<<<numOfBlocks, threadsPerBlock>>>(devPrevVal, devCurrVal, totalPoints, totalSteps);
printf("Printing final results...\n");
HANDLE_ERROR(hipMemcpy(currVal, devCurrVal, allocPoints * sizeof(float), hipMemcpyDeviceToHost));
printResult();
printf("\nDone.\n\n");
hipFree(devCurrVal);
hipFree(devPrevVal);
free(currVal);
return EXIT_SUCCESS;
}
void checkParam() {
char temp[20];
while ((totalPoints < MINPOINTS) || (totalPoints > MAXPOINTS)) {
printf("Enter number of points along vibrating string [%d-%d]: ", MINPOINTS, MAXPOINTS);
scanf("%s", temp);
totalPoints = atoi(temp);
if ((totalPoints < MINPOINTS) || (totalPoints > MAXPOINTS))
printf("Invalid. Please enter value between %d and %d.\n", MINPOINTS, MAXPOINTS);
}
while ((totalSteps < 1) || (totalSteps > MAXSTEPS)) {
printf("Enter number of time steps [1-%d]: ", MAXSTEPS);
scanf("%s", temp);
totalSteps = atoi(temp);
if ((totalSteps < 1) || (totalSteps > MAXSTEPS))
printf("Invalid. Please enter value between 1 and %d.\n", MAXSTEPS);
}
printf("Using points = %d, steps = %d\n", totalPoints, totalSteps);
}
__global__ void initLine(float *__devPrevVal, float *__devCurrVal, int __totalPoints) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < __totalPoints) {
float x = (float) i / (__totalPoints - 1);
__devPrevVal[i] = __devCurrVal[i] = __sinf(6.28318530 * x);
}
}
__global__ void updateAll(float *__devPrevVal, float *__devCurrVal, int __totalPoints, int __totalSteps) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < __totalPoints) {
float locPrevVal = __devPrevVal[i], locCurrVal = __devCurrVal[i] , locNextVal;
for (int j = 0; j < __totalSteps; j++) {
if ((i == 0) || (i == __totalPoints - 1))
locNextVal = 0.0;
else
locNextVal = 1.82 * locCurrVal - locPrevVal;
locPrevVal = locCurrVal;
locCurrVal = locNextVal;
}
__devCurrVal[i] = locCurrVal;
}
}
void printResult() {
for (int i = 0; i < totalPoints; i++) {
printf("%6.4f ", currVal[i]);
if ((i + 1) % 10 == 0)
printf("\n");
}
} | .text
.file "cuda1.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $.L.str, %esi
movl $totalPoints, %edx
xorl %eax, %eax
callq __isoc23_sscanf
movq 16(%rbx), %rdi
movl $.L.str, %esi
movl $totalSteps, %edx
xorl %eax, %eax
callq __isoc23_sscanf
callq _Z10checkParamv
movslq totalPoints(%rip), %rax
leaq 256(%rax), %rcx
movl %ecx, allocPoints(%rip)
leaq 1024(,%rax,4), %rbx
movq %rbx, %rdi
callq malloc
movq %rax, currVal(%rip)
testq %rax, %rax
je .LBB0_18
# %bb.1:
movl $devCurrVal, %edi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB0_2
# %bb.4: # %_ZL11handleError10hipError_tPKci.exit
movslq allocPoints(%rip), %rsi
shlq $2, %rsi
movl $devPrevVal, %edi
callq hipMalloc
testl %eax, %eax
jne .LBB0_5
# %bb.6: # %_ZL11handleError10hipError_tPKci.exit22
movabsq $4294967552, %rbx # imm = 0x100000100
movl allocPoints(%rip), %eax
leal 255(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $8, %ecx
leaq (%rcx,%rbx), %r14
addq $-256, %r14
movl $.Lstr, %edi
callq puts@PLT
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_8
# %bb.7:
movq devPrevVal(%rip), %rax
movq devCurrVal(%rip), %rcx
movl totalPoints(%rip), %edx
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
movl %edx, 4(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 56(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8initLinePfS_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_8:
movl $.Lstr.1, %edi
callq puts@PLT
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_10
# %bb.9:
movq devPrevVal(%rip), %rax
movq devCurrVal(%rip), %rcx
movl totalPoints(%rip), %edx
movl totalSteps(%rip), %esi
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
movl %edx, 4(%rsp)
movl %esi, 76(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 56(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 76(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9updateAllPfS_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_10:
movl $.Lstr.2, %edi
callq puts@PLT
movq currVal(%rip), %rdi
movq devCurrVal(%rip), %rsi
movslq allocPoints(%rip), %rdx
shlq $2, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_11
# %bb.12: # %_ZL11handleError10hipError_tPKci.exit30
cmpl $0, totalPoints(%rip)
jle .LBB0_17
# %bb.13: # %.lr.ph.i.preheader
movl $1, %ebx
xorl %r14d, %r14d
movl $3435973837, %r15d # imm = 0xCCCCCCCD
jmp .LBB0_14
.p2align 4, 0x90
.LBB0_16: # in Loop: Header=BB0_14 Depth=1
incq %r14
movslq totalPoints(%rip), %rax
incl %ebx
cmpq %rax, %r14
jge .LBB0_17
.LBB0_14: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl %ebx, %eax
imulq %r15, %rax
shrq $35, %rax
leal (%rax,%rax,4), %eax
leal -1(,%rax,2), %ebp
movq currVal(%rip), %rax
movss (%rax,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.12, %edi
movb $1, %al
callq printf
cmpl %r14d, %ebp
jne .LBB0_16
# %bb.15: # in Loop: Header=BB0_14 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB0_16
.LBB0_17: # %_Z11printResultv.exit
movl $.Lstr.3, %edi
callq puts@PLT
movq devCurrVal(%rip), %rdi
callq hipFree
movq devPrevVal(%rip), %rdi
callq hipFree
movq currVal(%rip), %rdi
callq free
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_18:
.cfi_def_cfa_offset 160
movl $1, %edi
callq exit
.LBB0_2:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.14, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $45, %ecx
jmp .LBB0_3
.LBB0_5:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.14, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $46, %ecx
jmp .LBB0_3
.LBB0_11:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.14, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $58, %ecx
.LBB0_3:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z10checkParamv # -- Begin function _Z10checkParamv
.p2align 4, 0x90
.type _Z10checkParamv,@function
_Z10checkParamv: # @_Z10checkParamv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $24, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl $-1000001, %ebp # imm = 0xFFF0BDBF
movl totalPoints(%rip), %eax
addl %ebp, %eax
cmpl $-999982, %eax # imm = 0xFFF0BDD2
ja .LBB1_5
# %bb.1:
movq %rsp, %rbx
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_4: # in Loop: Header=BB1_2 Depth=1
movl totalPoints(%rip), %eax
addl %ebp, %eax
cmpl $-999981, %eax # imm = 0xFFF0BDD3
jae .LBB1_5
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.6, %edi
movl $20, %esi
movl $1000000, %edx # imm = 0xF4240
xorl %eax, %eax
callq printf
movl $.L.str.7, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movq %rbx, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, totalPoints(%rip)
addl $-1000001, %eax # imm = 0xFFF0BDBF
cmpl $-999982, %eax # imm = 0xFFF0BDD2
ja .LBB1_4
# %bb.3: # in Loop: Header=BB1_2 Depth=1
movl $.L.str.8, %edi
movl $20, %esi
movl $1000000, %edx # imm = 0xF4240
xorl %eax, %eax
callq printf
jmp .LBB1_4
.LBB1_5: # %.preheader
movl totalSteps(%rip), %edx
leal -1000001(%rdx), %eax
cmpl $-1000001, %eax # imm = 0xFFF0BDBF
ja .LBB1_10
# %bb.6:
movq %rsp, %rbx
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_9: # in Loop: Header=BB1_7 Depth=1
movl totalSteps(%rip), %edx
leal -1000001(%rdx), %eax
cmpl $-1000000, %eax # imm = 0xFFF0BDC0
jae .LBB1_10
.LBB1_7: # %.lr.ph4
# =>This Inner Loop Header: Depth=1
movl $.L.str.9, %edi
movl $1000000, %esi # imm = 0xF4240
xorl %eax, %eax
callq printf
movl $.L.str.7, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movq %rbx, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, totalSteps(%rip)
addl $-1000001, %eax # imm = 0xFFF0BDBF
cmpl $-1000001, %eax # imm = 0xFFF0BDBF
ja .LBB1_9
# %bb.8: # in Loop: Header=BB1_7 Depth=1
movl $.L.str.10, %edi
movl $1000000, %esi # imm = 0xF4240
xorl %eax, %eax
callq printf
jmp .LBB1_9
.LBB1_10: # %._crit_edge
movl totalPoints(%rip), %esi
movl $.L.str.11, %edi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z10checkParamv, .Lfunc_end1-_Z10checkParamv
.cfi_endproc
# -- End function
.globl _Z23__device_stub__initLinePfS_i # -- Begin function _Z23__device_stub__initLinePfS_i
.p2align 4, 0x90
.type _Z23__device_stub__initLinePfS_i,@function
_Z23__device_stub__initLinePfS_i: # @_Z23__device_stub__initLinePfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8initLinePfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z23__device_stub__initLinePfS_i, .Lfunc_end2-_Z23__device_stub__initLinePfS_i
.cfi_endproc
# -- End function
.globl _Z24__device_stub__updateAllPfS_ii # -- Begin function _Z24__device_stub__updateAllPfS_ii
.p2align 4, 0x90
.type _Z24__device_stub__updateAllPfS_ii,@function
_Z24__device_stub__updateAllPfS_ii: # @_Z24__device_stub__updateAllPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9updateAllPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z24__device_stub__updateAllPfS_ii, .Lfunc_end3-_Z24__device_stub__updateAllPfS_ii
.cfi_endproc
# -- End function
.globl _Z11printResultv # -- Begin function _Z11printResultv
.p2align 4, 0x90
.type _Z11printResultv,@function
_Z11printResultv: # @_Z11printResultv
.cfi_startproc
# %bb.0:
cmpl $0, totalPoints(%rip)
jle .LBB4_6
# %bb.1: # %.lr.ph.preheader
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $1, %ebx
xorl %r14d, %r14d
movl $3435973837, %r15d # imm = 0xCCCCCCCD
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_4: # in Loop: Header=BB4_2 Depth=1
incq %r14
movslq totalPoints(%rip), %rax
incl %ebx
cmpq %rax, %r14
jge .LBB4_5
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ebx, %eax
imulq %r15, %rax
shrq $35, %rax
leal (%rax,%rax,4), %eax
leal -1(,%rax,2), %ebp
movq currVal(%rip), %rax
movss (%rax,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.12, %edi
movb $1, %al
callq printf
cmpl %r14d, %ebp
jne .LBB4_4
# %bb.3: # in Loop: Header=BB4_2 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB4_4
.LBB4_5:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB4_6: # %._crit_edge
retq
.Lfunc_end4:
.size _Z11printResultv, .Lfunc_end4-_Z11printResultv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8initLinePfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9updateAllPfS_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type totalSteps,@object # @totalSteps
.bss
.globl totalSteps
.p2align 2, 0x0
totalSteps:
.long 0 # 0x0
.size totalSteps, 4
.type totalPoints,@object # @totalPoints
.globl totalPoints
.p2align 2, 0x0
totalPoints:
.long 0 # 0x0
.size totalPoints, 4
.type allocPoints,@object # @allocPoints
.globl allocPoints
.p2align 2, 0x0
allocPoints:
.long 0 # 0x0
.size allocPoints, 4
.type currVal,@object # @currVal
.globl currVal
.p2align 3, 0x0
currVal:
.quad 0
.size currVal, 8
.type devCurrVal,@object # @devCurrVal
.globl devCurrVal
.p2align 3, 0x0
devCurrVal:
.quad 0
.size devCurrVal, 8
.type devPrevVal,@object # @devPrevVal
.globl devPrevVal
.p2align 3, 0x0
devPrevVal:
.quad 0
.size devPrevVal, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/yuwen41200/parallel-programming/master/cuda/cuda1.hip"
.size .L.str.1, 111
.type _Z8initLinePfS_i,@object # @_Z8initLinePfS_i
.section .rodata,"a",@progbits
.globl _Z8initLinePfS_i
.p2align 3, 0x0
_Z8initLinePfS_i:
.quad _Z23__device_stub__initLinePfS_i
.size _Z8initLinePfS_i, 8
.type _Z9updateAllPfS_ii,@object # @_Z9updateAllPfS_ii
.globl _Z9updateAllPfS_ii
.p2align 3, 0x0
_Z9updateAllPfS_ii:
.quad _Z24__device_stub__updateAllPfS_ii
.size _Z9updateAllPfS_ii, 8
.type .L.str.6,@object # @.str.6
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.6:
.asciz "Enter number of points along vibrating string [%d-%d]: "
.size .L.str.6, 56
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%s"
.size .L.str.7, 3
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Invalid. Please enter value between %d and %d.\n"
.size .L.str.8, 48
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Enter number of time steps [1-%d]: "
.size .L.str.9, 36
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Invalid. Please enter value between 1 and %d.\n"
.size .L.str.10, 47
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Using points = %d, steps = %d\n"
.size .L.str.11, 31
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "%6.4f "
.size .L.str.12, 7
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "%s in %s at line %d\n"
.size .L.str.14, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8initLinePfS_i"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9updateAllPfS_ii"
.size .L__unnamed_2, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Initializing points on the line..."
.size .Lstr, 35
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Updating all points for all time steps..."
.size .Lstr.1, 42
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Printing final results..."
.size .Lstr.2, 26
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "\nDone.\n"
.size .Lstr.3, 8
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__initLinePfS_i
.addrsig_sym _Z24__device_stub__updateAllPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym totalSteps
.addrsig_sym totalPoints
.addrsig_sym devCurrVal
.addrsig_sym devPrevVal
.addrsig_sym _Z8initLinePfS_i
.addrsig_sym _Z9updateAllPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9updateAllPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x170], PT ; /* 0x00005c0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff007624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc600078e00ff */
/*0090*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe20003f06270 */
/*00a0*/ IMAD.WIDE R2, R6, R3, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fca00078e0203 */
/*00b0*/ LDG.E R15, [R2.64] ; /* 0x00000006020f7981 */
/* 0x00016e000c1e1900 */
/*00c0*/ @!P0 BRA 0x3c0 ; /* 0x000002f000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R7, R0, -0x1, RZ ; /* 0xffffffff00077810 */
/* 0x000fe20007ffe0ff */
/*00e0*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe20000000000 */
/*00f0*/ SHF.R.S32.HI R5, RZ, 0x1f, R6 ; /* 0x0000001fff057819 */
/* 0x000fe40000011406 */
/*0100*/ ISETP.GE.U32.AND P2, PT, R7, 0x3, PT ; /* 0x000000030700780c */
/* 0x000fe20003f46070 */
/*0110*/ ULDC UR5, c[0x0][0x170] ; /* 0x00005c0000057ab9 */
/* 0x000fe20000000800 */
/*0120*/ LEA R4, P0, R6, c[0x0][0x160], 0x2 ; /* 0x0000580006047a11 */
/* 0x000fe200078010ff */
/*0130*/ UIADD3 UR4, -UR4, UR5, URZ ; /* 0x0000000504047290 */
/* 0x000fc6000fffe13f */
/*0140*/ LEA.HI.X R5, R6, c[0x0][0x164], R5, 0x2, P0 ; /* 0x0000590006057a11 */
/* 0x000fe400000f1405 */
/*0150*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe400078ec0ff */
/*0160*/ ISETP.NE.AND P0, PT, R6, UR4, PT ; /* 0x0000000406007c0c */
/* 0x000fe2000bf05270 */
/*0170*/ LDG.E R14, [R4.64] ; /* 0x00000006040e7981 */
/* 0x000362000c1e1900 */
/*0180*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f25270 */
/*0190*/ ISETP.EQ.OR P0, PT, R6, RZ, !P0 ; /* 0x000000ff0600720c */
/* 0x000fe20004702670 */
/*01a0*/ @!P2 BRA 0x320 ; /* 0x000001700000a947 */
/* 0x000ff40003800000 */
/*01b0*/ IADD3 R4, -R0, c[0x0][0x174], RZ ; /* 0x00005d0000047a10 */
/* 0x002fc60007ffe1ff */
/*01c0*/ F2F.F64.F32 R6, R15 ; /* 0x0000000f00067310 */
/* 0x020fe20000201800 */
/*01d0*/ IADD3 R4, R4, -0x4, RZ ; /* 0xfffffffc04047810 */
/* 0x000fc80007ffe0ff */
/*01e0*/ ISETP.NE.AND P2, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f45270 */
/*01f0*/ F2F.F64.F32 R8, R14 ; /* 0x0000000e00087310 */
/* 0x000e640000201800 */
/*0200*/ DFMA R8, R6, c[0x2][0x0], -R8 ; /* 0x0080000006087a2b */
/* 0x002e540000000808 */
/*0210*/ F2F.F32.F64 R8, R8 ; /* 0x0000000800087310 */
/* 0x002e700000301000 */
/*0220*/ F2F.F64.F32 R10, R8 ; /* 0x00000008000a7310 */
/* 0x002e640000201800 */
/*0230*/ FSEL R10, R10, RZ, !P0 ; /* 0x000000ff0a0a7208 */
/* 0x002fc40004000000 */
/*0240*/ FSEL R11, R11, RZ, !P0 ; /* 0x000000ff0b0b7208 */
/* 0x000fcc0004000000 */
/*0250*/ DFMA R6, R10, c[0x2][0x0], -R6 ; /* 0x008000000a067a2b */
/* 0x000e540000000806 */
/*0260*/ F2F.F32.F64 R6, R6 ; /* 0x0000000600067310 */
/* 0x002e700000301000 */
/*0270*/ F2F.F64.F32 R12, R6 ; /* 0x00000006000c7310 */
/* 0x002e640000201800 */
/*0280*/ FSEL R12, R12, RZ, !P0 ; /* 0x000000ff0c0c7208 */
/* 0x002fc40004000000 */
/*0290*/ FSEL R13, R13, RZ, !P0 ; /* 0x000000ff0d0d7208 */
/* 0x000fcc0004000000 */
/*02a0*/ DFMA R10, R12, c[0x2][0x0], -R10 ; /* 0x008000000c0a7a2b */
/* 0x000e54000000080a */
/*02b0*/ F2F.F32.F64 R10, R10 ; /* 0x0000000a000a7310 */
/* 0x002e640000301000 */
/*02c0*/ FSEL R14, R10, RZ, !P0 ; /* 0x000000ff0a0e7208 */
/* 0x002fcc0004000000 */
/*02d0*/ F2F.F64.F32 R8, R14 ; /* 0x0000000e00087310 */
/* 0x000e640000201800 */
/*02e0*/ DFMA R8, R8, c[0x2][0x0], -R12 ; /* 0x0080000008087a2b */
/* 0x002e54000000080c */
/*02f0*/ F2F.F32.F64 R8, R8 ; /* 0x0000000800087310 */
/* 0x002e640000301000 */
/*0300*/ FSEL R15, R8, RZ, !P0 ; /* 0x000000ff080f7208 */
/* 0x002fe20004000000 */
/*0310*/ @P2 BRA 0x1c0 ; /* 0xfffffea000002947 */
/* 0x000fea000383ffff */
/*0320*/ @!P1 BRA 0x3c0 ; /* 0x0000009000009947 */
/* 0x000fea0003800000 */
/*0330*/ F2F.F64.F32 R6, R14 ; /* 0x0000000e00067310 */
/* 0x0205e20000201800 */
/*0340*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fc80007ffe0ff */
/*0350*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc60003f25270 */
/*0360*/ F2F.F64.F32 R4, R15 ; /* 0x0000000f00047310 */
/* 0x002e620000201800 */
/*0370*/ IMAD.MOV.U32 R14, RZ, RZ, R15 ; /* 0x000000ffff0e7224 */
/* 0x004fe200078e000f */
/*0380*/ DFMA R4, R4, c[0x2][0x0], -R6 ; /* 0x0080000004047a2b */
/* 0x002e540000000806 */
/*0390*/ F2F.F32.F64 R4, R4 ; /* 0x0000000400047310 */
/* 0x002e640000301000 */
/*03a0*/ FSEL R15, R4, RZ, !P0 ; /* 0x000000ff040f7208 */
/* 0x002fe20004000000 */
/*03b0*/ @P1 BRA 0x330 ; /* 0xffffff7000001947 */
/* 0x000fea000383ffff */
/*03c0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x020fe2000c101906 */
/*03d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03e0*/ BRA 0x3e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8initLinePfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000800 */
/*0070*/ I2F R4, R0 ; /* 0x0000000000047306 */
/* 0x000fe20000201400 */
/*0080*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*0090*/ BSSY B0, 0x170 ; /* 0x000000d000007945 */
/* 0x000ff00003800000 */
/*00a0*/ I2F R3, UR4 ; /* 0x0000000400037d06 */
/* 0x000e220008201400 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fce0000000a00 */
/*00c0*/ MUFU.RCP R2, R3 ; /* 0x0000000300027308 */
/* 0x001e300000001000 */
/*00d0*/ FCHK P0, R4, R3 ; /* 0x0000000304007302 */
/* 0x000e620000000000 */
/*00e0*/ FFMA R5, -R3, R2, 1 ; /* 0x3f80000003057423 */
/* 0x001fc80000000102 */
/*00f0*/ FFMA R5, R2, R5, R2 ; /* 0x0000000502057223 */
/* 0x000fc80000000002 */
/*0100*/ FFMA R2, R4, R5, RZ ; /* 0x0000000504027223 */
/* 0x000fc800000000ff */
/*0110*/ FFMA R6, -R3, R2, R4 ; /* 0x0000000203067223 */
/* 0x000fc80000000104 */
/*0120*/ FFMA R8, R5, R6, R2 ; /* 0x0000000605087223 */
/* 0x000fe20000000002 */
/*0130*/ @!P0 BRA 0x160 ; /* 0x0000002000008947 */
/* 0x002fea0003800000 */
/*0140*/ MOV R2, 0x160 ; /* 0x0000016000027802 */
/* 0x000fe40000000f00 */
/*0150*/ CALL.REL.NOINC 0x220 ; /* 0x000000c000007944 */
/* 0x000fea0003c00000 */
/*0160*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0170*/ F2F.F64.F32 R2, R8 ; /* 0x0000000800027310 */
/* 0x000e220000201800 */
/*0180*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fc800078e00ff */
/*0190*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*01a0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fe200078e0207 */
/*01b0*/ DMUL R2, R2, c[0x2][0x0] ; /* 0x0080000002027a28 */
/* 0x001e140000000000 */
/*01c0*/ F2F.F32.F64 R2, R2 ; /* 0x0000000200027310 */
/* 0x001e240000301000 */
/*01d0*/ FMUL.RZ R9, R2, 0.15915493667125701904 ; /* 0x3e22f98302097820 */
/* 0x001fcc000040c000 */
/*01e0*/ MUFU.SIN R9, R9 ; /* 0x0000000900097308 */
/* 0x000e240000000400 */
/*01f0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x001fe8000c101904 */
/*0200*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ SHF.R.U32.HI R6, RZ, 0x17, R3.reuse ; /* 0x00000017ff067819 */
/* 0x100fe20000011603 */
/*0230*/ BSSY B1, 0x880 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0240*/ SHF.R.U32.HI R5, RZ, 0x17, R4.reuse ; /* 0x00000017ff057819 */
/* 0x100fe20000011604 */
/*0250*/ IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0004 */
/*0260*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fe200078ec0ff */
/*0270*/ IMAD.MOV.U32 R8, RZ, RZ, R3 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0003 */
/*0280*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fc400078ec0ff */
/*0290*/ IADD3 R11, R6, -0x1, RZ ; /* 0xffffffff060b7810 */
/* 0x000fe40007ffe0ff */
/*02a0*/ IADD3 R10, R5, -0x1, RZ ; /* 0xffffffff050a7810 */
/* 0x000fe40007ffe0ff */
/*02b0*/ ISETP.GT.U32.AND P0, PT, R11, 0xfd, PT ; /* 0x000000fd0b00780c */
/* 0x000fc80003f04070 */
/*02c0*/ ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ; /* 0x000000fd0a00780c */
/* 0x000fda0000704470 */
/*02d0*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*02e0*/ @!P0 BRA 0x460 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*02f0*/ FSETP.GTU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f1c200 */
/*0300*/ FSETP.GTU.FTZ.AND P1, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fc80003f3c200 */
/*0310*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0320*/ @P0 BRA 0x860 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0330*/ LOP3.LUT P0, RZ, R8, 0x7fffffff, R7, 0xc8, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000780c807 */
/*0340*/ @!P0 BRA 0x840 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0350*/ FSETP.NEU.FTZ.AND P2, PT, |R4|.reuse, +INF , PT ; /* 0x7f8000000400780b */
/* 0x040fe40003f5d200 */
/*0360*/ FSETP.NEU.FTZ.AND P1, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fe40003f3d200 */
/*0370*/ FSETP.NEU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fd60003f1d200 */
/*0380*/ @!P1 BRA !P2, 0x840 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0390*/ LOP3.LUT P2, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000784c0ff */
/*03a0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*03b0*/ @P1 BRA 0x820 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*03c0*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000782c0ff */
/*03d0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*03e0*/ @P0 BRA 0x7f0 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*03f0*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f06270 */
/*0400*/ ISETP.GE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fd60003f26270 */
/*0410*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff090224 */
/* 0x000fe400078e00ff */
/*0420*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; /* 0xffffffc0ff098424 */
/* 0x000fe400078e00ff */
/*0430*/ @!P0 FFMA R7, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004078823 */
/* 0x000fe400000000ff */
/*0440*/ @!P1 FFMA R8, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003089823 */
/* 0x000fe200000000ff */
/*0450*/ @!P1 IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009099810 */
/* 0x000fe40007ffe0ff */
/*0460*/ LEA R3, R6, 0xc0800000, 0x17 ; /* 0xc080000006037811 */
/* 0x000fe200078eb8ff */
/*0470*/ BSSY B2, 0x7e0 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*0480*/ IADD3 R5, R5, -0x7f, RZ ; /* 0xffffff8105057810 */
/* 0x000fc60007ffe0ff */
/*0490*/ IMAD.IADD R8, R8, 0x1, -R3 ; /* 0x0000000108087824 */
/* 0x000fe200078e0a03 */
/*04a0*/ IADD3 R6, R5.reuse, 0x7f, -R6 ; /* 0x0000007f05067810 */
/* 0x040fe20007ffe806 */
/*04b0*/ IMAD R7, R5, -0x800000, R7 ; /* 0xff80000005077824 */
/* 0x000fe400078e0207 */
/*04c0*/ MUFU.RCP R3, R8 ; /* 0x0000000800037308 */
/* 0x000e220000001000 */
/*04d0*/ FADD.FTZ R4, -R8, -RZ ; /* 0x800000ff08047221 */
/* 0x000fe40000010100 */
/*04e0*/ IMAD.IADD R6, R6, 0x1, R9 ; /* 0x0000000106067824 */
/* 0x000fe400078e0209 */
/*04f0*/ FFMA R10, R3, R4, 1 ; /* 0x3f800000030a7423 */
/* 0x001fc80000000004 */
/*0500*/ FFMA R12, R3, R10, R3 ; /* 0x0000000a030c7223 */
/* 0x000fc80000000003 */
/*0510*/ FFMA R3, R7, R12, RZ ; /* 0x0000000c07037223 */
/* 0x000fc800000000ff */
/*0520*/ FFMA R10, R4, R3, R7 ; /* 0x00000003040a7223 */
/* 0x000fc80000000007 */
/*0530*/ FFMA R11, R12, R10, R3 ; /* 0x0000000a0c0b7223 */
/* 0x000fc80000000003 */
/*0540*/ FFMA R7, R4, R11, R7 ; /* 0x0000000b04077223 */
/* 0x000fc80000000007 */
/*0550*/ FFMA R3, R12, R7, R11 ; /* 0x000000070c037223 */
/* 0x000fca000000000b */
/*0560*/ SHF.R.U32.HI R4, RZ, 0x17, R3 ; /* 0x00000017ff047819 */
/* 0x000fc80000011603 */
/*0570*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fca00078ec0ff */
/*0580*/ IMAD.IADD R8, R4, 0x1, R6 ; /* 0x0000000104087824 */
/* 0x000fca00078e0206 */
/*0590*/ IADD3 R4, R8, -0x1, RZ ; /* 0xffffffff08047810 */
/* 0x000fc80007ffe0ff */
/*05a0*/ ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ; /* 0x000000fe0400780c */
/* 0x000fda0003f06070 */
/*05b0*/ @!P0 BRA 0x7c0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*05c0*/ ISETP.GT.AND P0, PT, R8, 0xfe, PT ; /* 0x000000fe0800780c */
/* 0x000fda0003f04270 */
/*05d0*/ @P0 BRA 0x790 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*05e0*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f06270 */
/*05f0*/ @P0 BRA 0x7d0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0600*/ ISETP.GE.AND P0, PT, R8, -0x18, PT ; /* 0xffffffe80800780c */
/* 0x000fe40003f06270 */
/*0610*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*0620*/ @!P0 BRA 0x7d0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0630*/ FFMA.RZ R4, R12, R7.reuse, R11.reuse ; /* 0x000000070c047223 */
/* 0x180fe2000000c00b */
/*0640*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f45270 */
/*0650*/ FFMA.RM R5, R12, R7.reuse, R11.reuse ; /* 0x000000070c057223 */
/* 0x180fe2000000400b */
/*0660*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f25270 */
/*0670*/ LOP3.LUT R6, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04067812 */
/* 0x000fe200078ec0ff */
/*0680*/ FFMA.RP R4, R12, R7, R11 ; /* 0x000000070c047223 */
/* 0x000fe2000000800b */
/*0690*/ IADD3 R7, R8, 0x20, RZ ; /* 0x0000002008077810 */
/* 0x000fe20007ffe0ff */
/*06a0*/ IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0a08 */
/*06b0*/ LOP3.LUT R6, R6, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000006067812 */
/* 0x000fe400078efcff */
/*06c0*/ FSETP.NEU.FTZ.AND P0, PT, R4, R5, PT ; /* 0x000000050400720b */
/* 0x000fc40003f1d000 */
/*06d0*/ SHF.L.U32 R7, R6, R7, RZ ; /* 0x0000000706077219 */
/* 0x000fe400000006ff */
/*06e0*/ SEL R5, R8, RZ, P2 ; /* 0x000000ff08057207 */
/* 0x000fe40001000000 */
/*06f0*/ ISETP.NE.AND P1, PT, R7, RZ, P1 ; /* 0x000000ff0700720c */
/* 0x000fe40000f25270 */
/*0700*/ SHF.R.U32.HI R5, RZ, R5, R6 ; /* 0x00000005ff057219 */
/* 0x000fe40000011606 */
/*0710*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0720*/ SHF.R.U32.HI R7, RZ, 0x1, R5 ; /* 0x00000001ff077819 */
/* 0x000fc40000011605 */
/*0730*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*0740*/ LOP3.LUT R4, R4, 0x1, R7, 0xf8, !PT ; /* 0x0000000104047812 */
/* 0x000fc800078ef807 */
/*0750*/ LOP3.LUT R4, R4, R5, RZ, 0xc0, !PT ; /* 0x0000000504047212 */
/* 0x000fca00078ec0ff */
/*0760*/ IMAD.IADD R4, R7, 0x1, R4 ; /* 0x0000000107047824 */
/* 0x000fca00078e0204 */
/*0770*/ LOP3.LUT R3, R4, R3, RZ, 0xfc, !PT ; /* 0x0000000304037212 */
/* 0x000fe200078efcff */
/*0780*/ BRA 0x7d0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0790*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*07a0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*07b0*/ BRA 0x7d0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*07c0*/ IMAD R3, R6, 0x800000, R3 ; /* 0x0080000006037824 */
/* 0x000fe400078e0203 */
/*07d0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*07e0*/ BRA 0x870 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*07f0*/ LOP3.LUT R3, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fc800078e4807 */
/*0800*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0810*/ BRA 0x870 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0820*/ LOP3.LUT R3, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fe200078e4807 */
/*0830*/ BRA 0x870 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0840*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*0850*/ BRA 0x870 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0860*/ FADD.FTZ R3, R4, R3 ; /* 0x0000000304037221 */
/* 0x000fe40000010000 */
/*0870*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0880*/ IMAD.MOV.U32 R8, RZ, RZ, R3 ; /* 0x000000ffff087224 */
/* 0x001fe400078e0003 */
/*0890*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*08a0*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff75002007950 */
/* 0x000fea0003c3ffff */
/*08b0*/ BRA 0x8b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8initLinePfS_i
.globl _Z8initLinePfS_i
.p2align 8
.type _Z8initLinePfS_i,@function
_Z8initLinePfS_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s2, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_2
s_add_i32 s2, s2, -1
v_cvt_f32_i32_e32 v0, v1
v_cvt_f32_i32_e32 v2, s2
s_mov_b32 s3, 0x401921fb
s_mov_b32 s2, 0x53c8d4f1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v3, null, v2, v2, v0
v_div_scale_f32 v6, vcc_lo, v0, v2, v0
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v5, v4
v_mul_f32_e32 v5, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v3, v5, v6
v_fmac_f32_e32 v5, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, -v3, v5, v6
v_div_fmas_f32 v3, v3, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v0, v3, v2, v0
v_cvt_f64_f32_e32 v[2:3], v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f64 v[2:3], v[2:3], s[2:3]
s_load_b128 s[0:3], s[0:1], 0x0
v_cvt_f32_f64_e32 v0, v[2:3]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v3, 0.15915494, v0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sin_f32_e32 v4, v3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[2:3], v4, off
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8initLinePfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8initLinePfS_i, .Lfunc_end0-_Z8initLinePfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9updateAllPfS_ii
.globl _Z9updateAllPfS_ii
.p2align 8
.type _Z9updateAllPfS_ii,@function
_Z9updateAllPfS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v2
s_cbranch_execz .LBB1_8
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x8
s_load_b32 s2, s[0:1], 0x14
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v4, vcc_lo
s_cmp_lt_i32 s2, 1
global_load_b32 v5, v[0:1], off
s_cbranch_scc1 .LBB1_7
s_load_b64 s[0:1], s[0:1], 0x0
s_add_i32 s3, s3, -1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v2
v_cmp_ne_u32_e64 s0, s3, v2
s_mov_b32 s1, 0x3ffd1eb8
global_load_b32 v3, v[3:4], off
s_and_b32 s3, vcc_lo, s0
s_mov_b32 s0, 0x51eb851f
.LBB1_3:
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_2)
v_dual_mov_b32 v2, v5 :: v_dual_mov_b32 v5, 0
s_and_saveexec_b32 s4, s3
s_cbranch_execz .LBB1_5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[4:5], v2
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[6:7], v3
v_fma_f64 v[3:4], v[4:5], s[0:1], -v[6:7]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v5, v[3:4]
.LBB1_5:
s_or_b32 exec_lo, exec_lo, s4
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 0
s_cbranch_scc1 .LBB1_7
s_waitcnt vmcnt(0)
v_mov_b32_e32 v3, v2
s_branch .LBB1_3
.LBB1_7:
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v5, off
.LBB1_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9updateAllPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z9updateAllPfS_ii, .Lfunc_end1-_Z9updateAllPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8initLinePfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8initLinePfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9updateAllPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9updateAllPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00083f02_00000000-6_cuda1.cudafe1.cpp"
.text
#APP
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s in %s at line %d\n"
#NO_APP
.text
.type _ZL11handleError9cudaErrorPKci, @function
_ZL11handleError9cudaErrorPKci:
.LFB2057:
.cfi_startproc
testl %edi, %edi
jne .L6
ret
.L6:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbx
movl %edx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rdx
movl %ebp, %r8d
movq %rbx, %rcx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _ZL11handleError9cudaErrorPKci, .-_ZL11handleError9cudaErrorPKci
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Enter number of points along vibrating string [%d-%d]: "
.section .rodata.str1.1
.LC2:
.string "%s"
.section .rodata.str1.8
.align 8
.LC3:
.string "Invalid. Please enter value between %d and %d.\n"
.align 8
.LC4:
.string "Enter number of time steps [1-%d]: "
.align 8
.LC5:
.string "Invalid. Please enter value between 1 and %d.\n"
.align 8
.LC6:
.string "Using points = %d, steps = %d\n"
.text
.globl _Z10checkParamv
.type _Z10checkParamv, @function
_Z10checkParamv:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq .LC1(%rip), %r12
movq %rsp, %rbx
leaq .LC2(%rip), %rbp
.L11:
movl totalPoints(%rip), %eax
subl $20, %eax
cmpl $999980, %eax
jbe .L20
movl $1000000, %ecx
movl $20, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl $10, %edx
movl $0, %esi
movq %rbx, %rdi
call __isoc23_strtol@PLT
movl %eax, totalPoints(%rip)
subl $20, %eax
cmpl $999980, %eax
jbe .L11
movl $1000000, %ecx
movl $20, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L11
.L20:
leaq .LC4(%rip), %r12
movq %rsp, %rbx
leaq .LC2(%rip), %rbp
.L14:
movl totalSteps(%rip), %ecx
leal -1(%rcx), %eax
cmpl $999999, %eax
jbe .L21
movl $1000000, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl $10, %edx
movl $0, %esi
movq %rbx, %rdi
call __isoc23_strtol@PLT
movl %eax, totalSteps(%rip)
subl $1, %eax
cmpl $999999, %eax
jbe .L14
movl $1000000, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L14
.L21:
movl totalPoints(%rip), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z10checkParamv, .-_Z10checkParamv
.section .rodata.str1.1
.LC7:
.string "%6.4f "
.LC8:
.string "\n"
.text
.globl _Z11printResultv
.type _Z11printResultv, @function
_Z11printResultv:
.LFB2060:
.cfi_startproc
endbr64
cmpl $0, totalPoints(%rip)
jle .L29
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl $0, %ebp
movl $0, %ebx
leaq .LC7(%rip), %r12
leaq .LC8(%rip), %r13
jmp .L26
.L25:
addq $4, %rbp
cmpl totalPoints(%rip), %ebx
jge .L32
.L26:
movq currVal(%rip), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbp), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addl $1, %ebx
movslq %ebx, %rax
imulq $1717986919, %rax, %rax
sarq $34, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,4), %eax
addl %eax, %eax
cmpl %eax, %ebx
jne .L25
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L25
.L32:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
ret
.cfi_endproc
.LFE2060:
.size _Z11printResultv, .-_Z11printResultv
.globl _Z30__device_stub__Z8initLinePfS_iPfS_i
.type _Z30__device_stub__Z8initLinePfS_iPfS_i, @function
_Z30__device_stub__Z8initLinePfS_iPfS_i:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L37
.L33:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8initLinePfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L33
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z30__device_stub__Z8initLinePfS_iPfS_i, .-_Z30__device_stub__Z8initLinePfS_iPfS_i
.globl _Z8initLinePfS_i
.type _Z8initLinePfS_i, @function
_Z8initLinePfS_i:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z8initLinePfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z8initLinePfS_i, .-_Z8initLinePfS_i
.globl _Z32__device_stub__Z9updateAllPfS_iiPfS_ii
.type _Z32__device_stub__Z9updateAllPfS_iiPfS_ii, @function
_Z32__device_stub__Z9updateAllPfS_iiPfS_ii:
.LFB2087:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L45
.L41:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L46
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9updateAllPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L41
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z32__device_stub__Z9updateAllPfS_iiPfS_ii, .-_Z32__device_stub__Z9updateAllPfS_iiPfS_ii
.globl _Z9updateAllPfS_ii
.type _Z9updateAllPfS_ii, @function
_Z9updateAllPfS_ii:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9updateAllPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z9updateAllPfS_ii, .-_Z9updateAllPfS_ii
.section .rodata.str1.1
.LC9:
.string "%d"
.section .rodata.str1.8
.align 8
.LC10:
.string "/home/ubuntu/Datasets/stackv2/train-structured/yuwen41200/parallel-programming/master/cuda/cuda1.cu"
.align 8
.LC11:
.string "Initializing points on the line...\n"
.align 8
.LC12:
.string "Updating all points for all time steps...\n"
.section .rodata.str1.1
.LC13:
.string "Printing final results...\n"
.LC14:
.string "\nDone.\n\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movq %rsi, %rbx
movq 8(%rsi), %rdi
leaq totalPoints(%rip), %rdx
leaq .LC9(%rip), %rbp
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
movq 16(%rbx), %rdi
leaq totalSteps(%rip), %rdx
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
call _Z10checkParamv
movl totalPoints(%rip), %eax
addl $256, %eax
movl %eax, allocPoints(%rip)
cltq
leaq 0(,%rax,4), %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, currVal(%rip)
testq %rax, %rax
je .L54
movq %rbx, %rsi
leaq devCurrVal(%rip), %rdi
call cudaMalloc@PLT
movl %eax, %edi
movl $43, %edx
leaq .LC10(%rip), %rbx
movq %rbx, %rsi
call _ZL11handleError9cudaErrorPKci
movslq allocPoints(%rip), %rsi
salq $2, %rsi
leaq devPrevVal(%rip), %rdi
call cudaMalloc@PLT
movl %eax, %edi
movl $44, %edx
movq %rbx, %rsi
call _ZL11handleError9cudaErrorPKci
movl $256, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl allocPoints(%rip), %edx
leal 255(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $8, %eax
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 16(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movq 20(%rsp), %rdi
movl 28(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L55
.L51:
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 16(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movq 20(%rsp), %rdi
movl 28(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L56
.L52:
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq allocPoints(%rip), %rdx
salq $2, %rdx
movl $2, %ecx
movq devCurrVal(%rip), %rsi
movq currVal(%rip), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $56, %edx
leaq .LC10(%rip), %rsi
call _ZL11handleError9cudaErrorPKci
call _Z11printResultv
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq devCurrVal(%rip), %rdi
call cudaFree@PLT
movq devPrevVal(%rip), %rdi
call cudaFree@PLT
movq currVal(%rip), %rdi
call free@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
movl $1, %edi
call exit@PLT
.L55:
movl totalPoints(%rip), %edx
movq devCurrVal(%rip), %rsi
movq devPrevVal(%rip), %rdi
call _Z30__device_stub__Z8initLinePfS_iPfS_i
jmp .L51
.L56:
movl totalSteps(%rip), %ecx
movl totalPoints(%rip), %edx
movq devCurrVal(%rip), %rsi
movq devPrevVal(%rip), %rdi
call _Z32__device_stub__Z9updateAllPfS_iiPfS_ii
jmp .L52
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC15:
.string "_Z9updateAllPfS_ii"
.LC16:
.string "_Z8initLinePfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z9updateAllPfS_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z8initLinePfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl devPrevVal
.bss
.align 8
.type devPrevVal, @object
.size devPrevVal, 8
devPrevVal:
.zero 8
.globl devCurrVal
.align 8
.type devCurrVal, @object
.size devCurrVal, 8
devCurrVal:
.zero 8
.globl currVal
.align 8
.type currVal, @object
.size currVal, 8
currVal:
.zero 8
.globl allocPoints
.align 4
.type allocPoints, @object
.size allocPoints, 4
allocPoints:
.zero 4
.globl totalPoints
.align 4
.type totalPoints, @object
.size totalPoints, 4
totalPoints:
.zero 4
.globl totalSteps
.align 4
.type totalSteps, @object
.size totalSteps, 4
totalSteps:
.zero 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda1.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $.L.str, %esi
movl $totalPoints, %edx
xorl %eax, %eax
callq __isoc23_sscanf
movq 16(%rbx), %rdi
movl $.L.str, %esi
movl $totalSteps, %edx
xorl %eax, %eax
callq __isoc23_sscanf
callq _Z10checkParamv
movslq totalPoints(%rip), %rax
leaq 256(%rax), %rcx
movl %ecx, allocPoints(%rip)
leaq 1024(,%rax,4), %rbx
movq %rbx, %rdi
callq malloc
movq %rax, currVal(%rip)
testq %rax, %rax
je .LBB0_18
# %bb.1:
movl $devCurrVal, %edi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB0_2
# %bb.4: # %_ZL11handleError10hipError_tPKci.exit
movslq allocPoints(%rip), %rsi
shlq $2, %rsi
movl $devPrevVal, %edi
callq hipMalloc
testl %eax, %eax
jne .LBB0_5
# %bb.6: # %_ZL11handleError10hipError_tPKci.exit22
movabsq $4294967552, %rbx # imm = 0x100000100
movl allocPoints(%rip), %eax
leal 255(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $8, %ecx
leaq (%rcx,%rbx), %r14
addq $-256, %r14
movl $.Lstr, %edi
callq puts@PLT
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_8
# %bb.7:
movq devPrevVal(%rip), %rax
movq devCurrVal(%rip), %rcx
movl totalPoints(%rip), %edx
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
movl %edx, 4(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 56(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8initLinePfS_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_8:
movl $.Lstr.1, %edi
callq puts@PLT
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_10
# %bb.9:
movq devPrevVal(%rip), %rax
movq devCurrVal(%rip), %rcx
movl totalPoints(%rip), %edx
movl totalSteps(%rip), %esi
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
movl %edx, 4(%rsp)
movl %esi, 76(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 56(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 76(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9updateAllPfS_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_10:
movl $.Lstr.2, %edi
callq puts@PLT
movq currVal(%rip), %rdi
movq devCurrVal(%rip), %rsi
movslq allocPoints(%rip), %rdx
shlq $2, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_11
# %bb.12: # %_ZL11handleError10hipError_tPKci.exit30
cmpl $0, totalPoints(%rip)
jle .LBB0_17
# %bb.13: # %.lr.ph.i.preheader
movl $1, %ebx
xorl %r14d, %r14d
movl $3435973837, %r15d # imm = 0xCCCCCCCD
jmp .LBB0_14
.p2align 4, 0x90
.LBB0_16: # in Loop: Header=BB0_14 Depth=1
incq %r14
movslq totalPoints(%rip), %rax
incl %ebx
cmpq %rax, %r14
jge .LBB0_17
.LBB0_14: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl %ebx, %eax
imulq %r15, %rax
shrq $35, %rax
leal (%rax,%rax,4), %eax
leal -1(,%rax,2), %ebp
movq currVal(%rip), %rax
movss (%rax,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.12, %edi
movb $1, %al
callq printf
cmpl %r14d, %ebp
jne .LBB0_16
# %bb.15: # in Loop: Header=BB0_14 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB0_16
.LBB0_17: # %_Z11printResultv.exit
movl $.Lstr.3, %edi
callq puts@PLT
movq devCurrVal(%rip), %rdi
callq hipFree
movq devPrevVal(%rip), %rdi
callq hipFree
movq currVal(%rip), %rdi
callq free
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_18:
.cfi_def_cfa_offset 160
movl $1, %edi
callq exit
.LBB0_2:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.14, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $45, %ecx
jmp .LBB0_3
.LBB0_5:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.14, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $46, %ecx
jmp .LBB0_3
.LBB0_11:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.14, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $58, %ecx
.LBB0_3:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z10checkParamv # -- Begin function _Z10checkParamv
.p2align 4, 0x90
.type _Z10checkParamv,@function
_Z10checkParamv: # @_Z10checkParamv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $24, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl $-1000001, %ebp # imm = 0xFFF0BDBF
movl totalPoints(%rip), %eax
addl %ebp, %eax
cmpl $-999982, %eax # imm = 0xFFF0BDD2
ja .LBB1_5
# %bb.1:
movq %rsp, %rbx
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_4: # in Loop: Header=BB1_2 Depth=1
movl totalPoints(%rip), %eax
addl %ebp, %eax
cmpl $-999981, %eax # imm = 0xFFF0BDD3
jae .LBB1_5
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.6, %edi
movl $20, %esi
movl $1000000, %edx # imm = 0xF4240
xorl %eax, %eax
callq printf
movl $.L.str.7, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movq %rbx, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, totalPoints(%rip)
addl $-1000001, %eax # imm = 0xFFF0BDBF
cmpl $-999982, %eax # imm = 0xFFF0BDD2
ja .LBB1_4
# %bb.3: # in Loop: Header=BB1_2 Depth=1
movl $.L.str.8, %edi
movl $20, %esi
movl $1000000, %edx # imm = 0xF4240
xorl %eax, %eax
callq printf
jmp .LBB1_4
.LBB1_5: # %.preheader
movl totalSteps(%rip), %edx
leal -1000001(%rdx), %eax
cmpl $-1000001, %eax # imm = 0xFFF0BDBF
ja .LBB1_10
# %bb.6:
movq %rsp, %rbx
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_9: # in Loop: Header=BB1_7 Depth=1
movl totalSteps(%rip), %edx
leal -1000001(%rdx), %eax
cmpl $-1000000, %eax # imm = 0xFFF0BDC0
jae .LBB1_10
.LBB1_7: # %.lr.ph4
# =>This Inner Loop Header: Depth=1
movl $.L.str.9, %edi
movl $1000000, %esi # imm = 0xF4240
xorl %eax, %eax
callq printf
movl $.L.str.7, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movq %rbx, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, totalSteps(%rip)
addl $-1000001, %eax # imm = 0xFFF0BDBF
cmpl $-1000001, %eax # imm = 0xFFF0BDBF
ja .LBB1_9
# %bb.8: # in Loop: Header=BB1_7 Depth=1
movl $.L.str.10, %edi
movl $1000000, %esi # imm = 0xF4240
xorl %eax, %eax
callq printf
jmp .LBB1_9
.LBB1_10: # %._crit_edge
movl totalPoints(%rip), %esi
movl $.L.str.11, %edi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z10checkParamv, .Lfunc_end1-_Z10checkParamv
.cfi_endproc
# -- End function
.globl _Z23__device_stub__initLinePfS_i # -- Begin function _Z23__device_stub__initLinePfS_i
.p2align 4, 0x90
.type _Z23__device_stub__initLinePfS_i,@function
_Z23__device_stub__initLinePfS_i: # @_Z23__device_stub__initLinePfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8initLinePfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z23__device_stub__initLinePfS_i, .Lfunc_end2-_Z23__device_stub__initLinePfS_i
.cfi_endproc
# -- End function
.globl _Z24__device_stub__updateAllPfS_ii # -- Begin function _Z24__device_stub__updateAllPfS_ii
.p2align 4, 0x90
.type _Z24__device_stub__updateAllPfS_ii,@function
_Z24__device_stub__updateAllPfS_ii: # @_Z24__device_stub__updateAllPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9updateAllPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z24__device_stub__updateAllPfS_ii, .Lfunc_end3-_Z24__device_stub__updateAllPfS_ii
.cfi_endproc
# -- End function
.globl _Z11printResultv # -- Begin function _Z11printResultv
.p2align 4, 0x90
.type _Z11printResultv,@function
_Z11printResultv: # @_Z11printResultv
.cfi_startproc
# %bb.0:
cmpl $0, totalPoints(%rip)
jle .LBB4_6
# %bb.1: # %.lr.ph.preheader
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $1, %ebx
xorl %r14d, %r14d
movl $3435973837, %r15d # imm = 0xCCCCCCCD
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_4: # in Loop: Header=BB4_2 Depth=1
incq %r14
movslq totalPoints(%rip), %rax
incl %ebx
cmpq %rax, %r14
jge .LBB4_5
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ebx, %eax
imulq %r15, %rax
shrq $35, %rax
leal (%rax,%rax,4), %eax
leal -1(,%rax,2), %ebp
movq currVal(%rip), %rax
movss (%rax,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.12, %edi
movb $1, %al
callq printf
cmpl %r14d, %ebp
jne .LBB4_4
# %bb.3: # in Loop: Header=BB4_2 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB4_4
.LBB4_5:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB4_6: # %._crit_edge
retq
.Lfunc_end4:
.size _Z11printResultv, .Lfunc_end4-_Z11printResultv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8initLinePfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9updateAllPfS_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type totalSteps,@object # @totalSteps
.bss
.globl totalSteps
.p2align 2, 0x0
totalSteps:
.long 0 # 0x0
.size totalSteps, 4
.type totalPoints,@object # @totalPoints
.globl totalPoints
.p2align 2, 0x0
totalPoints:
.long 0 # 0x0
.size totalPoints, 4
.type allocPoints,@object # @allocPoints
.globl allocPoints
.p2align 2, 0x0
allocPoints:
.long 0 # 0x0
.size allocPoints, 4
.type currVal,@object # @currVal
.globl currVal
.p2align 3, 0x0
currVal:
.quad 0
.size currVal, 8
.type devCurrVal,@object # @devCurrVal
.globl devCurrVal
.p2align 3, 0x0
devCurrVal:
.quad 0
.size devCurrVal, 8
.type devPrevVal,@object # @devPrevVal
.globl devPrevVal
.p2align 3, 0x0
devPrevVal:
.quad 0
.size devPrevVal, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/yuwen41200/parallel-programming/master/cuda/cuda1.hip"
.size .L.str.1, 111
.type _Z8initLinePfS_i,@object # @_Z8initLinePfS_i
.section .rodata,"a",@progbits
.globl _Z8initLinePfS_i
.p2align 3, 0x0
_Z8initLinePfS_i:
.quad _Z23__device_stub__initLinePfS_i
.size _Z8initLinePfS_i, 8
.type _Z9updateAllPfS_ii,@object # @_Z9updateAllPfS_ii
.globl _Z9updateAllPfS_ii
.p2align 3, 0x0
_Z9updateAllPfS_ii:
.quad _Z24__device_stub__updateAllPfS_ii
.size _Z9updateAllPfS_ii, 8
.type .L.str.6,@object # @.str.6
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.6:
.asciz "Enter number of points along vibrating string [%d-%d]: "
.size .L.str.6, 56
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%s"
.size .L.str.7, 3
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Invalid. Please enter value between %d and %d.\n"
.size .L.str.8, 48
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Enter number of time steps [1-%d]: "
.size .L.str.9, 36
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Invalid. Please enter value between 1 and %d.\n"
.size .L.str.10, 47
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Using points = %d, steps = %d\n"
.size .L.str.11, 31
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "%6.4f "
.size .L.str.12, 7
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "%s in %s at line %d\n"
.size .L.str.14, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8initLinePfS_i"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9updateAllPfS_ii"
.size .L__unnamed_2, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Initializing points on the line..."
.size .Lstr, 35
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Updating all points for all time steps..."
.size .Lstr.1, 42
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Printing final results..."
.size .Lstr.2, 26
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "\nDone.\n"
.size .Lstr.3, 8
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__initLinePfS_i
.addrsig_sym _Z24__device_stub__updateAllPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym totalSteps
.addrsig_sym totalPoints
.addrsig_sym devCurrVal
.addrsig_sym devPrevVal
.addrsig_sym _Z8initLinePfS_i
.addrsig_sym _Z9updateAllPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void ewsum_kernel(float *d_a, float *d_w, float *d_out, int num_w, int width, int total_dim) {
// Get the id and make sure it is within bounds
const int id = threadIdx.x + blockIdx.x * blockDim.x;
if (id >= total_dim) {
return;
}
const int non_width = total_dim / width;
const int x = id / non_width;
const int num_sets = width / num_w;
const int w_x = x / num_sets;
d_out[id] = d_a[id] * d_w[w_x];
}
__global__ void ewsum_sum_kernel(float *d_a, float *d_out, int num_w, int width, int total_dim) {
// out is (width / num_w) x (total_dim / width)
const int in_set = width / num_w;
const int non_width = total_dim / width;
const int out_total_dim = in_set * non_width;
// Get the id and make sure it is within bounds
const int id = threadIdx.x + blockIdx.x * blockDim.x;
if (id >= out_total_dim) {
return;
}
const int out_x = id / non_width;
const int non_x_loc = id % non_width;
// TODO: this is probably slow...
float out = 0;
for (int i = out_x; i < width; i += in_set) {
out += d_a[i*non_width + non_x_loc];
}
d_out[id] = out;
}
__global__ void ewsum_back_kernel(float *d_error, float *d_w, float *d_out,
int num_w, int err_width, int width, int total_dim) {
// Get the id and make sure it is within bounds
const int id = threadIdx.x + blockIdx.x * blockDim.x;
if (id >= total_dim) {
return;
}
const int non_width = total_dim / width;
const int x = id / non_width;
const int num_sets = width / num_w;
const int w_x = x / num_sets;
const int err_x = x % err_width;
const int non_x_loc = id % non_width;
d_out[id] = d_w[w_x] * d_error[err_x*non_width + non_x_loc];
} | .file "tmpxft_001106c9_00000000-6_ewsum.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z12ewsum_kernelPfS_S_iiiPfS_S_iii
.type _Z39__device_stub__Z12ewsum_kernelPfS_S_iiiPfS_S_iii, @function
_Z39__device_stub__Z12ewsum_kernelPfS_S_iiiPfS_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12ewsum_kernelPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z12ewsum_kernelPfS_S_iiiPfS_S_iii, .-_Z39__device_stub__Z12ewsum_kernelPfS_S_iiiPfS_S_iii
.globl _Z12ewsum_kernelPfS_S_iii
.type _Z12ewsum_kernelPfS_S_iii, @function
_Z12ewsum_kernelPfS_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z12ewsum_kernelPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12ewsum_kernelPfS_S_iii, .-_Z12ewsum_kernelPfS_S_iii
.globl _Z41__device_stub__Z16ewsum_sum_kernelPfS_iiiPfS_iii
.type _Z41__device_stub__Z16ewsum_sum_kernelPfS_iiiPfS_iii, @function
_Z41__device_stub__Z16ewsum_sum_kernelPfS_iiiPfS_iii:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16ewsum_sum_kernelPfS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z41__device_stub__Z16ewsum_sum_kernelPfS_iiiPfS_iii, .-_Z41__device_stub__Z16ewsum_sum_kernelPfS_iiiPfS_iii
.globl _Z16ewsum_sum_kernelPfS_iii
.type _Z16ewsum_sum_kernelPfS_iii, @function
_Z16ewsum_sum_kernelPfS_iii:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z16ewsum_sum_kernelPfS_iiiPfS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z16ewsum_sum_kernelPfS_iii, .-_Z16ewsum_sum_kernelPfS_iii
.globl _Z45__device_stub__Z17ewsum_back_kernelPfS_S_iiiiPfS_S_iiii
.type _Z45__device_stub__Z17ewsum_back_kernelPfS_S_iiiiPfS_S_iiii, @function
_Z45__device_stub__Z17ewsum_back_kernelPfS_S_iiiiPfS_S_iiii:
.LFB2055:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z17ewsum_back_kernelPfS_S_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z45__device_stub__Z17ewsum_back_kernelPfS_S_iiiiPfS_S_iiii, .-_Z45__device_stub__Z17ewsum_back_kernelPfS_S_iiiiPfS_S_iiii
.globl _Z17ewsum_back_kernelPfS_S_iiii
.type _Z17ewsum_back_kernelPfS_S_iiii, @function
_Z17ewsum_back_kernelPfS_S_iiii:
.LFB2056:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z45__device_stub__Z17ewsum_back_kernelPfS_S_iiiiPfS_S_iiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z17ewsum_back_kernelPfS_S_iiii, .-_Z17ewsum_back_kernelPfS_S_iiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z17ewsum_back_kernelPfS_S_iiii"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z16ewsum_sum_kernelPfS_iii"
.LC2:
.string "_Z12ewsum_kernelPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17ewsum_back_kernelPfS_S_iiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z16ewsum_sum_kernelPfS_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z12ewsum_kernelPfS_S_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void ewsum_kernel(float *d_a, float *d_w, float *d_out, int num_w, int width, int total_dim) {
// Get the id and make sure it is within bounds
const int id = threadIdx.x + blockIdx.x * blockDim.x;
if (id >= total_dim) {
return;
}
const int non_width = total_dim / width;
const int x = id / non_width;
const int num_sets = width / num_w;
const int w_x = x / num_sets;
d_out[id] = d_a[id] * d_w[w_x];
}
__global__ void ewsum_sum_kernel(float *d_a, float *d_out, int num_w, int width, int total_dim) {
// out is (width / num_w) x (total_dim / width)
const int in_set = width / num_w;
const int non_width = total_dim / width;
const int out_total_dim = in_set * non_width;
// Get the id and make sure it is within bounds
const int id = threadIdx.x + blockIdx.x * blockDim.x;
if (id >= out_total_dim) {
return;
}
const int out_x = id / non_width;
const int non_x_loc = id % non_width;
// TODO: this is probably slow...
float out = 0;
for (int i = out_x; i < width; i += in_set) {
out += d_a[i*non_width + non_x_loc];
}
d_out[id] = out;
}
__global__ void ewsum_back_kernel(float *d_error, float *d_w, float *d_out,
int num_w, int err_width, int width, int total_dim) {
// Get the id and make sure it is within bounds
const int id = threadIdx.x + blockIdx.x * blockDim.x;
if (id >= total_dim) {
return;
}
const int non_width = total_dim / width;
const int x = id / non_width;
const int num_sets = width / num_w;
const int w_x = x / num_sets;
const int err_x = x % err_width;
const int non_x_loc = id % non_width;
d_out[id] = d_w[w_x] * d_error[err_x*non_width + non_x_loc];
} | #include <hip/hip_runtime.h>
__global__ void ewsum_kernel(float *d_a, float *d_w, float *d_out, int num_w, int width, int total_dim) {
// Get the id and make sure it is within bounds
const int id = threadIdx.x + blockIdx.x * blockDim.x;
if (id >= total_dim) {
return;
}
const int non_width = total_dim / width;
const int x = id / non_width;
const int num_sets = width / num_w;
const int w_x = x / num_sets;
d_out[id] = d_a[id] * d_w[w_x];
}
__global__ void ewsum_sum_kernel(float *d_a, float *d_out, int num_w, int width, int total_dim) {
// out is (width / num_w) x (total_dim / width)
const int in_set = width / num_w;
const int non_width = total_dim / width;
const int out_total_dim = in_set * non_width;
// Get the id and make sure it is within bounds
const int id = threadIdx.x + blockIdx.x * blockDim.x;
if (id >= out_total_dim) {
return;
}
const int out_x = id / non_width;
const int non_x_loc = id % non_width;
// TODO: this is probably slow...
float out = 0;
for (int i = out_x; i < width; i += in_set) {
out += d_a[i*non_width + non_x_loc];
}
d_out[id] = out;
}
__global__ void ewsum_back_kernel(float *d_error, float *d_w, float *d_out,
int num_w, int err_width, int width, int total_dim) {
// Get the id and make sure it is within bounds
const int id = threadIdx.x + blockIdx.x * blockDim.x;
if (id >= total_dim) {
return;
}
const int non_width = total_dim / width;
const int x = id / non_width;
const int num_sets = width / num_w;
const int w_x = x / num_sets;
const int err_x = x % err_width;
const int non_x_loc = id % non_width;
d_out[id] = d_w[w_x] * d_error[err_x*non_width + non_x_loc];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void ewsum_kernel(float *d_a, float *d_w, float *d_out, int num_w, int width, int total_dim) {
// Get the id and make sure it is within bounds
const int id = threadIdx.x + blockIdx.x * blockDim.x;
if (id >= total_dim) {
return;
}
const int non_width = total_dim / width;
const int x = id / non_width;
const int num_sets = width / num_w;
const int w_x = x / num_sets;
d_out[id] = d_a[id] * d_w[w_x];
}
__global__ void ewsum_sum_kernel(float *d_a, float *d_out, int num_w, int width, int total_dim) {
// out is (width / num_w) x (total_dim / width)
const int in_set = width / num_w;
const int non_width = total_dim / width;
const int out_total_dim = in_set * non_width;
// Get the id and make sure it is within bounds
const int id = threadIdx.x + blockIdx.x * blockDim.x;
if (id >= out_total_dim) {
return;
}
const int out_x = id / non_width;
const int non_x_loc = id % non_width;
// TODO: this is probably slow...
float out = 0;
for (int i = out_x; i < width; i += in_set) {
out += d_a[i*non_width + non_x_loc];
}
d_out[id] = out;
}
__global__ void ewsum_back_kernel(float *d_error, float *d_w, float *d_out,
int num_w, int err_width, int width, int total_dim) {
// Get the id and make sure it is within bounds
const int id = threadIdx.x + blockIdx.x * blockDim.x;
if (id >= total_dim) {
return;
}
const int non_width = total_dim / width;
const int x = id / non_width;
const int num_sets = width / num_w;
const int w_x = x / num_sets;
const int err_x = x % err_width;
const int non_x_loc = id % non_width;
d_out[id] = d_w[w_x] * d_error[err_x*non_width + non_x_loc];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12ewsum_kernelPfS_S_iii
.globl _Z12ewsum_kernelPfS_S_iii
.p2align 8
.type _Z12ewsum_kernelPfS_S_iii,@function
_Z12ewsum_kernelPfS_S_iii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s8, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_2
s_load_b256 s[0:7], s[0:1], 0x0
s_ashr_i32 s12, s8, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s8, s8, s12
s_xor_b32 s8, s8, s12
s_waitcnt lgkmcnt(0)
s_ashr_i32 s9, s7, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s9
s_xor_b32 s12, s12, s9
s_xor_b32 s7, s7, s9
v_cvt_f32_u32_e32 v0, s7
s_sub_i32 s11, 0, s7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s10, v0
s_mul_i32 s11, s11, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s11, s10, s11
s_add_i32 s10, s10, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s10, s8, s10
s_mul_i32 s11, s10, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s8, s8, s11
s_add_i32 s11, s10, 1
s_sub_i32 s13, s8, s7
s_cmp_ge_u32 s8, s7
s_cselect_b32 s10, s11, s10
s_cselect_b32 s8, s13, s8
s_add_i32 s11, s10, 1
s_cmp_ge_u32 s8, s7
s_cselect_b32 s8, s11, s10
s_ashr_i32 s10, s6, 31
s_xor_b32 s8, s8, s12
s_add_i32 s6, s6, s10
s_sub_i32 s8, s8, s12
s_xor_b32 s6, s6, s10
s_ashr_i32 s11, s8, 31
v_cvt_f32_u32_e32 v0, s6
s_add_i32 s8, s8, s11
s_sub_i32 s14, 0, s6
s_xor_b32 s8, s8, s11
s_xor_b32 s9, s9, s10
v_cvt_f32_u32_e32 v2, s8
v_rcp_iflag_f32_e32 v0, v0
s_sub_i32 s13, 0, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_mul_f32_e32 v2, 0x4f7ffffe, v2
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v2, v2
v_readfirstlane_b32 s12, v0
v_ashrrev_i32_e32 v0, 31, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_lo_u32 v3, s13, v2
s_mul_i32 s14, s14, s12
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v4, v1, v0
s_mul_hi_u32 s13, s12, s14
s_add_i32 s12, s12, s13
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_mul_hi_u32 s12, s7, s12
v_mul_hi_u32 v3, v2, v3
v_xor_b32_e32 v4, v4, v0
s_mul_i32 s13, s12, s6
s_add_i32 s10, s12, 1
s_sub_i32 s7, s7, s13
v_xor_b32_e32 v0, s11, v0
s_sub_i32 s13, s7, s6
s_cmp_ge_u32 s7, s6
v_add_nc_u32_e32 v2, v2, v3
s_cselect_b32 s10, s10, s12
s_cselect_b32 s7, s13, s7
s_add_i32 s12, s10, 1
s_cmp_ge_u32 s7, s6
v_mul_hi_u32 v2, v4, v2
s_cselect_b32 s6, s12, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s6, s6, s9
s_sub_i32 s6, s6, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_ashr_i32 s7, s6, 31
v_mul_lo_u32 v3, v2, s8
s_add_i32 s6, s6, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s6, s6, s7
v_cvt_f32_u32_e32 v5, s6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v3, v4, v3
v_add_nc_u32_e32 v4, 1, v2
v_rcp_iflag_f32_e32 v5, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v6, s8, v3
v_cmp_le_u32_e32 vcc_lo, s8, v3
v_dual_cndmask_b32 v2, v2, v4 :: v_dual_cndmask_b32 v3, v3, v6
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v5, 0x4f7ffffe, v5 :: v_dual_add_nc_u32 v4, 1, v2
v_cmp_le_u32_e32 vcc_lo, s8, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cvt_u32_f32_e32 v3, v5
s_sub_i32 s8, 0, s6
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v4, s8, v3
v_xor_b32_e32 v2, v2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v4, v3, v4
v_sub_nc_u32_e32 v0, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v2, 31, v0
v_add_nc_u32_e32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v2
v_xor_b32_e32 v0, v0, v2
v_xor_b32_e32 v2, s7, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v0, v3
v_mul_lo_u32 v4, v3, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v0, v0, v4
v_add_nc_u32_e32 v4, 1, v3
v_subrev_nc_u32_e32 v5, s6, v0
v_cmp_le_u32_e32 vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v3, v3, v4 :: v_dual_cndmask_b32 v0, v0, v5
v_add_nc_u32_e32 v4, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s6, v0
v_cndmask_b32_e32 v0, v3, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v2
v_sub_nc_u32_e32 v3, v0, v2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[3:4]
v_add_co_u32 v4, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v4, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12ewsum_kernelPfS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12ewsum_kernelPfS_S_iii, .Lfunc_end0-_Z12ewsum_kernelPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z16ewsum_sum_kernelPfS_iii
.globl _Z16ewsum_sum_kernelPfS_iii
.p2align 8
.type _Z16ewsum_sum_kernelPfS_iii,@function
_Z16ewsum_sum_kernelPfS_iii:
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b32 s4, s[0:1], 0x18
s_load_b32 s5, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_ashr_i32 s6, s2, 31
s_ashr_i32 s7, s3, 31
s_add_i32 s2, s2, s6
s_add_i32 s8, s3, s7
s_xor_b32 s2, s2, s6
s_xor_b32 s8, s8, s7
v_cvt_f32_u32_e32 v1, s2
v_cvt_f32_u32_e32 v2, s8
s_sub_i32 s10, 0, s2
s_xor_b32 s6, s7, s6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_readfirstlane_b32 s9, v1
v_mul_f32_e32 v1, 0x4f7ffffe, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s10, s10, s9
v_cvt_u32_f32_e32 v1, v1
s_mul_hi_u32 s10, s9, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_add_i32 s9, s9, s10
v_readfirstlane_b32 s13, v1
s_mul_hi_u32 s9, s8, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mul_i32 s10, s9, s2
s_add_i32 s11, s9, 1
s_sub_i32 s10, s8, s10
s_sub_i32 s12, s10, s2
s_cmp_ge_u32 s10, s2
s_cselect_b32 s9, s11, s9
s_cselect_b32 s10, s12, s10
s_add_i32 s11, s9, 1
s_cmp_ge_u32 s10, s2
s_cselect_b32 s2, s11, s9
s_sub_i32 s9, 0, s8
s_ashr_i32 s10, s4, 31
s_mul_i32 s9, s9, s13
s_add_i32 s4, s4, s10
s_mul_hi_u32 s9, s13, s9
s_xor_b32 s4, s4, s10
s_add_i32 s13, s13, s9
s_xor_b32 s7, s10, s7
s_mul_hi_u32 s9, s4, s13
s_xor_b32 s2, s2, s6
s_mul_i32 s10, s9, s8
s_sub_i32 s2, s2, s6
s_sub_i32 s4, s4, s10
s_add_i32 s6, s9, 1
s_sub_i32 s10, s4, s8
s_cmp_ge_u32 s4, s8
s_cselect_b32 s6, s6, s9
s_cselect_b32 s4, s10, s4
s_add_i32 s9, s6, 1
s_cmp_ge_u32 s4, s8
s_cselect_b32 s4, s9, s6
s_and_b32 s5, s5, 0xffff
s_xor_b32 s4, s4, s7
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
s_sub_i32 s4, s4, s7
s_mov_b32 s5, exec_lo
s_mul_i32 s6, s4, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmpx_gt_i32_e64 s6, v1
s_cbranch_execz .LBB1_6
s_ashr_i32 s5, s4, 31
v_ashrrev_i32_e32 v3, 31, v1
s_add_i32 s4, s4, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_xor_b32 s4, s4, s5
v_add_nc_u32_e32 v4, v1, v3
v_cvt_f32_u32_e32 v0, s4
s_sub_i32 s7, 0, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v4, v3
v_rcp_iflag_f32_e32 v0, v0
v_xor_b32_e32 v3, s5, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v2, s7, v0
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
v_add_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v4, v0
v_mul_lo_u32 v2, v0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v4, v2
v_add_nc_u32_e32 v4, 1, v0
v_subrev_nc_u32_e32 v5, s4, v2
v_cmp_le_u32_e32 vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, 1, v0
v_cmp_le_u32_e32 vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v4, v0, v3
v_mov_b32_e32 v0, 0
v_cmpx_gt_i32_e64 s3, v4
s_cbranch_execz .LBB1_5
s_load_b64 s[4:5], s[0:1], 0x0
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v2, v1
s_mov_b32 s8, 0
.LBB1_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_add_nc_u32_e32 v4, s2, v4
v_lshlrev_b64 v[5:6], 2, v[2:3]
v_add_nc_u32_e32 v2, s6, v2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s3, v4
global_load_b32 v3, v[5:6], off
s_or_b32 s8, vcc_lo, s8
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v3
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB1_3
s_or_b32 exec_lo, exec_lo, s8
.LBB1_5:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s7
s_load_b64 s[0:1], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB1_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16ewsum_sum_kernelPfS_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z16ewsum_sum_kernelPfS_iii, .Lfunc_end1-_Z16ewsum_sum_kernelPfS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z17ewsum_back_kernelPfS_S_iiii
.globl _Z17ewsum_back_kernelPfS_S_iiii
.p2align 8
.type _Z17ewsum_back_kernelPfS_S_iiii,@function
_Z17ewsum_back_kernelPfS_S_iiii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x34
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB2_2
s_load_b32 s3, s[0:1], 0x20
s_ashr_i32 s10, s2, 31
v_ashrrev_i32_e32 v4, 31, v1
s_add_i32 s2, s2, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_xor_b32 s11, s2, s10
s_waitcnt lgkmcnt(0)
s_ashr_i32 s8, s3, 31
s_add_i32 s3, s3, s8
s_xor_b32 s10, s10, s8
s_xor_b32 s9, s3, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v0, s9
s_sub_i32 s4, 0, s9
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_readfirstlane_b32 s3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s4, s4, s3
s_mul_hi_u32 s4, s3, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s4
s_mul_hi_u32 s12, s11, s3
s_load_b256 s[0:7], s[0:1], 0x0
s_mul_i32 s13, s12, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s11, s11, s13
s_add_i32 s13, s12, 1
s_sub_i32 s14, s11, s9
s_cmp_ge_u32 s11, s9
s_cselect_b32 s12, s13, s12
s_cselect_b32 s11, s14, s11
s_add_i32 s13, s12, 1
s_cmp_ge_u32 s11, s9
s_cselect_b32 s11, s13, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s11, s11, s10
s_sub_i32 s10, s11, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_ashr_i32 s11, s10, 31
s_waitcnt lgkmcnt(0)
s_ashr_i32 s12, s6, 31
s_add_i32 s13, s10, s11
s_add_i32 s6, s6, s12
s_xor_b32 s13, s13, s11
s_xor_b32 s6, s6, s12
v_cvt_f32_u32_e32 v0, s13
v_cvt_f32_u32_e32 v2, s6
s_sub_i32 s14, 0, s13
s_sub_i32 s15, 0, s6
s_xor_b32 s8, s8, s12
v_rcp_iflag_f32_e32 v0, v0
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_mul_f32_e32 v2, 0x4f7ffffe, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v0, v0
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v3, s14, v0
v_readfirstlane_b32 s14, v2
v_add_nc_u32_e32 v2, v1, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s15, s15, s14
v_xor_b32_e32 v2, v2, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_mul_hi_u32 v3, v0, v3
s_mul_hi_u32 s15, s14, s15
v_xor_b32_e32 v4, s11, v4
s_add_i32 s14, s14, s15
s_mul_hi_u32 s14, s9, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_mul_i32 s12, s14, s6
v_add_nc_u32_e32 v0, v0, v3
s_sub_i32 s9, s9, s12
s_add_i32 s12, s14, 1
s_sub_i32 s15, s9, s6
s_cmp_ge_u32 s9, s6
v_mul_hi_u32 v0, v2, v0
s_cselect_b32 s12, s12, s14
s_cselect_b32 s9, s15, s9
s_add_i32 s14, s12, 1
s_cmp_ge_u32 s9, s6
s_cselect_b32 s6, s14, s12
s_ashr_i32 s9, s7, 31
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v3, v0, s13
s_xor_b32 s6, s6, s8
s_add_i32 s7, s7, s9
s_sub_i32 s6, s6, s8
s_xor_b32 s7, s7, s9
s_ashr_i32 s8, s6, 31
v_cvt_f32_u32_e32 v5, s7
s_add_i32 s6, s6, s8
v_sub_nc_u32_e32 v2, v2, v3
v_add_nc_u32_e32 v3, 1, v0
s_xor_b32 s6, s6, s8
v_rcp_iflag_f32_e32 v5, v5
v_cvt_f32_u32_e32 v6, s6
v_subrev_nc_u32_e32 v7, s13, v2
v_cmp_le_u32_e32 vcc_lo, s13, v2
s_sub_i32 s9, 0, s7
v_cndmask_b32_e32 v0, v0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_cndmask_b32_e32 v2, v2, v7, vcc_lo
v_rcp_iflag_f32_e32 v3, v6
s_delay_alu instid0(TRANS32_DEP_2) | instid1(VALU_DEP_2)
v_dual_mul_f32 v5, 0x4f7ffffe, v5 :: v_dual_add_nc_u32 v6, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s13, v2
v_cvt_u32_f32_e32 v2, v5
s_waitcnt_depctr 0xfff
v_dual_cndmask_b32 v0, v0, v6 :: v_dual_mul_f32 v3, 0x4f7ffffe, v3
v_mul_lo_u32 v5, s9, v2
s_sub_i32 s9, 0, s6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v0, v0, v4
v_cvt_u32_f32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_hi_u32 v5, v2, v5
v_sub_nc_u32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v4, s9, v3
v_ashrrev_i32_e32 v6, 31, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v2, v2, v5
v_mul_hi_u32 v4, v3, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v7, v0, v6
v_mul_lo_u32 v0, v0, s10
v_xor_b32_e32 v5, v7, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v3, v3, v4
v_sub_nc_u32_e32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_hi_u32 v2, v5, v2
v_mul_hi_u32 v3, v5, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v2, s7
v_mul_lo_u32 v4, v3, s6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v5, v2
v_sub_nc_u32_e32 v4, v5, v4
v_add_nc_u32_e32 v5, 1, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v7, s7, v2
v_cmp_le_u32_e32 vcc_lo, s7, v2
v_cndmask_b32_e32 v2, v2, v7, vcc_lo
v_subrev_nc_u32_e32 v7, s6, v4
v_cmp_le_u32_e32 vcc_lo, s6, v4
v_cndmask_b32_e32 v3, v3, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_subrev_nc_u32_e32 v5, s7, v2
v_cndmask_b32_e32 v4, v4, v7, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s7, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v2, v2, v5 :: v_dual_add_nc_u32 v7, 1, v3
v_cmp_le_u32_e32 vcc_lo, s6, v4
v_xor_b32_e32 v5, s8, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_xor_b32_e32 v2, v2, v6
v_cndmask_b32_e32 v3, v3, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v6, v2, v6
v_xor_b32_e32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v2, v3, v5
v_mad_u64_u32 v[4:5], null, v6, s10, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
global_load_b32 v3, v[2:3], off
global_load_b32 v4, v[4:5], off
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v3, v4
global_store_b32 v[0:1], v2, off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17ewsum_back_kernelPfS_S_iiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z17ewsum_back_kernelPfS_S_iiii, .Lfunc_end2-_Z17ewsum_back_kernelPfS_S_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12ewsum_kernelPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12ewsum_kernelPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16ewsum_sum_kernelPfS_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16ewsum_sum_kernelPfS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17ewsum_back_kernelPfS_S_iiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17ewsum_back_kernelPfS_S_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void ewsum_kernel(float *d_a, float *d_w, float *d_out, int num_w, int width, int total_dim) {
// Get the id and make sure it is within bounds
const int id = threadIdx.x + blockIdx.x * blockDim.x;
if (id >= total_dim) {
return;
}
const int non_width = total_dim / width;
const int x = id / non_width;
const int num_sets = width / num_w;
const int w_x = x / num_sets;
d_out[id] = d_a[id] * d_w[w_x];
}
__global__ void ewsum_sum_kernel(float *d_a, float *d_out, int num_w, int width, int total_dim) {
// out is (width / num_w) x (total_dim / width)
const int in_set = width / num_w;
const int non_width = total_dim / width;
const int out_total_dim = in_set * non_width;
// Get the id and make sure it is within bounds
const int id = threadIdx.x + blockIdx.x * blockDim.x;
if (id >= out_total_dim) {
return;
}
const int out_x = id / non_width;
const int non_x_loc = id % non_width;
// TODO: this is probably slow...
float out = 0;
for (int i = out_x; i < width; i += in_set) {
out += d_a[i*non_width + non_x_loc];
}
d_out[id] = out;
}
__global__ void ewsum_back_kernel(float *d_error, float *d_w, float *d_out,
int num_w, int err_width, int width, int total_dim) {
// Get the id and make sure it is within bounds
const int id = threadIdx.x + blockIdx.x * blockDim.x;
if (id >= total_dim) {
return;
}
const int non_width = total_dim / width;
const int x = id / non_width;
const int num_sets = width / num_w;
const int w_x = x / num_sets;
const int err_x = x % err_width;
const int non_x_loc = id % non_width;
d_out[id] = d_w[w_x] * d_error[err_x*non_width + non_x_loc];
} | .text
.file "ewsum.hip"
.globl _Z27__device_stub__ewsum_kernelPfS_S_iii # -- Begin function _Z27__device_stub__ewsum_kernelPfS_S_iii
.p2align 4, 0x90
.type _Z27__device_stub__ewsum_kernelPfS_S_iii,@function
_Z27__device_stub__ewsum_kernelPfS_S_iii: # @_Z27__device_stub__ewsum_kernelPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12ewsum_kernelPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z27__device_stub__ewsum_kernelPfS_S_iii, .Lfunc_end0-_Z27__device_stub__ewsum_kernelPfS_S_iii
.cfi_endproc
# -- End function
.globl _Z31__device_stub__ewsum_sum_kernelPfS_iii # -- Begin function _Z31__device_stub__ewsum_sum_kernelPfS_iii
.p2align 4, 0x90
.type _Z31__device_stub__ewsum_sum_kernelPfS_iii,@function
_Z31__device_stub__ewsum_sum_kernelPfS_iii: # @_Z31__device_stub__ewsum_sum_kernelPfS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16ewsum_sum_kernelPfS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z31__device_stub__ewsum_sum_kernelPfS_iii, .Lfunc_end1-_Z31__device_stub__ewsum_sum_kernelPfS_iii
.cfi_endproc
# -- End function
.globl _Z32__device_stub__ewsum_back_kernelPfS_S_iiii # -- Begin function _Z32__device_stub__ewsum_back_kernelPfS_S_iiii
.p2align 4, 0x90
.type _Z32__device_stub__ewsum_back_kernelPfS_S_iiii,@function
_Z32__device_stub__ewsum_back_kernelPfS_S_iiii: # @_Z32__device_stub__ewsum_back_kernelPfS_S_iiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17ewsum_back_kernelPfS_S_iiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _Z32__device_stub__ewsum_back_kernelPfS_S_iiii, .Lfunc_end2-_Z32__device_stub__ewsum_back_kernelPfS_S_iiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12ewsum_kernelPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16ewsum_sum_kernelPfS_iii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17ewsum_back_kernelPfS_S_iiii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12ewsum_kernelPfS_S_iii,@object # @_Z12ewsum_kernelPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z12ewsum_kernelPfS_S_iii
.p2align 3, 0x0
_Z12ewsum_kernelPfS_S_iii:
.quad _Z27__device_stub__ewsum_kernelPfS_S_iii
.size _Z12ewsum_kernelPfS_S_iii, 8
.type _Z16ewsum_sum_kernelPfS_iii,@object # @_Z16ewsum_sum_kernelPfS_iii
.globl _Z16ewsum_sum_kernelPfS_iii
.p2align 3, 0x0
_Z16ewsum_sum_kernelPfS_iii:
.quad _Z31__device_stub__ewsum_sum_kernelPfS_iii
.size _Z16ewsum_sum_kernelPfS_iii, 8
.type _Z17ewsum_back_kernelPfS_S_iiii,@object # @_Z17ewsum_back_kernelPfS_S_iiii
.globl _Z17ewsum_back_kernelPfS_S_iiii
.p2align 3, 0x0
_Z17ewsum_back_kernelPfS_S_iiii:
.quad _Z32__device_stub__ewsum_back_kernelPfS_S_iiii
.size _Z17ewsum_back_kernelPfS_S_iiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12ewsum_kernelPfS_S_iii"
.size .L__unnamed_1, 26
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z16ewsum_sum_kernelPfS_iii"
.size .L__unnamed_2, 28
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z17ewsum_back_kernelPfS_S_iiii"
.size .L__unnamed_3, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__ewsum_kernelPfS_S_iii
.addrsig_sym _Z31__device_stub__ewsum_sum_kernelPfS_iii
.addrsig_sym _Z32__device_stub__ewsum_back_kernelPfS_S_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12ewsum_kernelPfS_S_iii
.addrsig_sym _Z16ewsum_sum_kernelPfS_iii
.addrsig_sym _Z17ewsum_back_kernelPfS_S_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001106c9_00000000-6_ewsum.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z12ewsum_kernelPfS_S_iiiPfS_S_iii
.type _Z39__device_stub__Z12ewsum_kernelPfS_S_iiiPfS_S_iii, @function
_Z39__device_stub__Z12ewsum_kernelPfS_S_iiiPfS_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12ewsum_kernelPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z12ewsum_kernelPfS_S_iiiPfS_S_iii, .-_Z39__device_stub__Z12ewsum_kernelPfS_S_iiiPfS_S_iii
.globl _Z12ewsum_kernelPfS_S_iii
.type _Z12ewsum_kernelPfS_S_iii, @function
_Z12ewsum_kernelPfS_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z12ewsum_kernelPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12ewsum_kernelPfS_S_iii, .-_Z12ewsum_kernelPfS_S_iii
.globl _Z41__device_stub__Z16ewsum_sum_kernelPfS_iiiPfS_iii
.type _Z41__device_stub__Z16ewsum_sum_kernelPfS_iiiPfS_iii, @function
_Z41__device_stub__Z16ewsum_sum_kernelPfS_iiiPfS_iii:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16ewsum_sum_kernelPfS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z41__device_stub__Z16ewsum_sum_kernelPfS_iiiPfS_iii, .-_Z41__device_stub__Z16ewsum_sum_kernelPfS_iiiPfS_iii
.globl _Z16ewsum_sum_kernelPfS_iii
.type _Z16ewsum_sum_kernelPfS_iii, @function
_Z16ewsum_sum_kernelPfS_iii:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z16ewsum_sum_kernelPfS_iiiPfS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z16ewsum_sum_kernelPfS_iii, .-_Z16ewsum_sum_kernelPfS_iii
.globl _Z45__device_stub__Z17ewsum_back_kernelPfS_S_iiiiPfS_S_iiii
.type _Z45__device_stub__Z17ewsum_back_kernelPfS_S_iiiiPfS_S_iiii, @function
_Z45__device_stub__Z17ewsum_back_kernelPfS_S_iiiiPfS_S_iiii:
.LFB2055:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z17ewsum_back_kernelPfS_S_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z45__device_stub__Z17ewsum_back_kernelPfS_S_iiiiPfS_S_iiii, .-_Z45__device_stub__Z17ewsum_back_kernelPfS_S_iiiiPfS_S_iiii
.globl _Z17ewsum_back_kernelPfS_S_iiii
.type _Z17ewsum_back_kernelPfS_S_iiii, @function
_Z17ewsum_back_kernelPfS_S_iiii:
.LFB2056:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z45__device_stub__Z17ewsum_back_kernelPfS_S_iiiiPfS_S_iiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z17ewsum_back_kernelPfS_S_iiii, .-_Z17ewsum_back_kernelPfS_S_iiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z17ewsum_back_kernelPfS_S_iiii"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z16ewsum_sum_kernelPfS_iii"
.LC2:
.string "_Z12ewsum_kernelPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17ewsum_back_kernelPfS_S_iiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z16ewsum_sum_kernelPfS_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z12ewsum_kernelPfS_S_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ewsum.hip"
.globl _Z27__device_stub__ewsum_kernelPfS_S_iii # -- Begin function _Z27__device_stub__ewsum_kernelPfS_S_iii
.p2align 4, 0x90
.type _Z27__device_stub__ewsum_kernelPfS_S_iii,@function
_Z27__device_stub__ewsum_kernelPfS_S_iii: # @_Z27__device_stub__ewsum_kernelPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12ewsum_kernelPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z27__device_stub__ewsum_kernelPfS_S_iii, .Lfunc_end0-_Z27__device_stub__ewsum_kernelPfS_S_iii
.cfi_endproc
# -- End function
.globl _Z31__device_stub__ewsum_sum_kernelPfS_iii # -- Begin function _Z31__device_stub__ewsum_sum_kernelPfS_iii
.p2align 4, 0x90
.type _Z31__device_stub__ewsum_sum_kernelPfS_iii,@function
_Z31__device_stub__ewsum_sum_kernelPfS_iii: # @_Z31__device_stub__ewsum_sum_kernelPfS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16ewsum_sum_kernelPfS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z31__device_stub__ewsum_sum_kernelPfS_iii, .Lfunc_end1-_Z31__device_stub__ewsum_sum_kernelPfS_iii
.cfi_endproc
# -- End function
.globl _Z32__device_stub__ewsum_back_kernelPfS_S_iiii # -- Begin function _Z32__device_stub__ewsum_back_kernelPfS_S_iiii
.p2align 4, 0x90
.type _Z32__device_stub__ewsum_back_kernelPfS_S_iiii,@function
_Z32__device_stub__ewsum_back_kernelPfS_S_iiii: # @_Z32__device_stub__ewsum_back_kernelPfS_S_iiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17ewsum_back_kernelPfS_S_iiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _Z32__device_stub__ewsum_back_kernelPfS_S_iiii, .Lfunc_end2-_Z32__device_stub__ewsum_back_kernelPfS_S_iiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12ewsum_kernelPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16ewsum_sum_kernelPfS_iii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17ewsum_back_kernelPfS_S_iiii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12ewsum_kernelPfS_S_iii,@object # @_Z12ewsum_kernelPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z12ewsum_kernelPfS_S_iii
.p2align 3, 0x0
_Z12ewsum_kernelPfS_S_iii:
.quad _Z27__device_stub__ewsum_kernelPfS_S_iii
.size _Z12ewsum_kernelPfS_S_iii, 8
.type _Z16ewsum_sum_kernelPfS_iii,@object # @_Z16ewsum_sum_kernelPfS_iii
.globl _Z16ewsum_sum_kernelPfS_iii
.p2align 3, 0x0
_Z16ewsum_sum_kernelPfS_iii:
.quad _Z31__device_stub__ewsum_sum_kernelPfS_iii
.size _Z16ewsum_sum_kernelPfS_iii, 8
.type _Z17ewsum_back_kernelPfS_S_iiii,@object # @_Z17ewsum_back_kernelPfS_S_iiii
.globl _Z17ewsum_back_kernelPfS_S_iiii
.p2align 3, 0x0
_Z17ewsum_back_kernelPfS_S_iiii:
.quad _Z32__device_stub__ewsum_back_kernelPfS_S_iiii
.size _Z17ewsum_back_kernelPfS_S_iiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12ewsum_kernelPfS_S_iii"
.size .L__unnamed_1, 26
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z16ewsum_sum_kernelPfS_iii"
.size .L__unnamed_2, 28
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z17ewsum_back_kernelPfS_S_iiii"
.size .L__unnamed_3, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__ewsum_kernelPfS_S_iii
.addrsig_sym _Z31__device_stub__ewsum_sum_kernelPfS_iii
.addrsig_sym _Z32__device_stub__ewsum_back_kernelPfS_S_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12ewsum_kernelPfS_S_iii
.addrsig_sym _Z16ewsum_sum_kernelPfS_iii
.addrsig_sym _Z17ewsum_back_kernelPfS_S_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <math.h>
#include <vector>
#include <string>
#include <algorithm>
#include <random>
#include <chrono>
#include <stdio.h>
#define NB_THREADS 1024
#define NB_NUMBERS 200
#define NB_EXPERIMENTS 100
void print_vector(int* array, int k) {
for(size_t i=0; i < k; i++) {
printf("%d ", array[i]);
}
printf("\n");
}
bool compare_vectors(int *v1, std::vector<int> v2) {
for(int i=0; i < v2.size(); i++) {
if (v1[i] != v2[i]) {
printf("wrong at %d %d vs %d\n", i, v1[i], v2[i]);
return false;
}
}
return true;
}
std::vector<int> create_vector(int N) {
std::vector<int> res;
for(int i=0; i < N; i++) {
res.push_back(i);
}
return res;
}
__global__
void bubble_sort(int *A, int n) {
__shared__ int end[NB_THREADS]; // termination condition for each thread
__shared__ int race[NB_NUMBERS]; // race condition for each element of input array
for (int u=0; u<NB_THREADS; u++) { end[u] = 0; }
for (int v=0; v<NB_NUMBERS; v++) { race[v] = 1; }
int temp;
int index = threadIdx.x;
while (1) {
end[index] = 1;
for (int i=0; i<n; i++) {
while (1) {
if ((race[i] == 1 && race[i-1] == 1) || (i == 0 && race[i] == 1)) {
if (A[i-1] > A[i]) {
// Block race condition
race[i] = 0;
race[i-1] = 0;
// Swap
temp = A[i-1];
A[i-1] = A[i];
A[i] = temp;
// Release race condition
end[index] = 0;
race[i] = 1;
race[i-1] = 1;
}
break;
}
}
}
if (end[index] == 1) { break; }
}
}
int main(void) {
for (int e=0; e<NB_EXPERIMENTS; e++) {
// Init random input array
int range = NB_NUMBERS;
std::vector<int> v = create_vector(range);
std::vector<int> v_orig = create_vector(range);
std::random_shuffle ( v.begin(), v.end() );
std::random_shuffle ( v.begin(), v.end() );
int *x;
cudaMallocManaged(&x, range*sizeof(int));
for (int i = 0; i < range; i++) {
x[i] = v[i];
printf("%d %d\n", x[i], v[i]);
}
print_vector(x, range);
// Sort
bubble_sort<<<1, NB_THREADS>>>(x, range);
cudaDeviceSynchronize();
// Check output
if (!compare_vectors(x, v_orig)) {
printf("%s\n", "Wrong algorithm");
print_vector(x, range);
break;
} else { printf("%s %d\n", "True algorithm", e); }
// Free memory
cudaFree(x);
}
} | .file "tmpxft_000326a2_00000000-6_gpu_sort.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB5091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5091:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl _Z12print_vectorPii
.type _Z12print_vectorPii, @function
_Z12print_vectorPii:
.LFB5069:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
testl %esi, %esi
je .L4
movq %rdi, %rbp
movslq %esi, %r12
movl $0, %ebx
leaq .LC0(%rip), %r13
.L5:
movl 0(%rbp,%rbx,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %r12, %rbx
jne .L5
.L4:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5069:
.size _Z12print_vectorPii, .-_Z12print_vectorPii
.section .rodata.str1.1
.LC2:
.string "wrong at %d %d vs %d\n"
.text
.globl _Z15compare_vectorsPiSt6vectorIiSaIiEE
.type _Z15compare_vectorsPiSt6vectorIiSaIiEE, @function
_Z15compare_vectorsPiSt6vectorIiSaIiEE:
.LFB5070:
.cfi_startproc
endbr64
movq 8(%rsi), %rdx
movq (%rsi), %rax
movq %rdx, %rsi
subq %rax, %rsi
sarq $2, %rsi
cmpq %rax, %rdx
je .L12
movl $0, %edx
.L11:
movl (%rdi,%rdx,4), %ecx
movl (%rax,%rdx,4), %r8d
cmpl %r8d, %ecx
jne .L18
addq $1, %rdx
cmpq %rsi, %rdx
jb .L11
movl $1, %eax
ret
.L18:
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L12:
movl $1, %eax
ret
.cfi_endproc
.LFE5070:
.size _Z15compare_vectorsPiSt6vectorIiSaIiEE, .-_Z15compare_vectorsPiSt6vectorIiSaIiEE
.globl _Z32__device_stub__Z11bubble_sortPiiPii
.type _Z32__device_stub__Z11bubble_sortPiiPii, @function
_Z32__device_stub__Z11bubble_sortPiiPii:
.LFB5113:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11bubble_sortPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5113:
.size _Z32__device_stub__Z11bubble_sortPiiPii, .-_Z32__device_stub__Z11bubble_sortPiiPii
.globl _Z11bubble_sortPii
.type _Z11bubble_sortPii, @function
_Z11bubble_sortPii:
.LFB5114:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z11bubble_sortPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5114:
.size _Z11bubble_sortPii, .-_Z11bubble_sortPii
.section .rodata.str1.1
.LC3:
.string "_Z11bubble_sortPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB5116:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z11bubble_sortPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5116:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIiSaIiEED2Ev,"axG",@progbits,_ZNSt6vectorIiSaIiEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEED2Ev
.type _ZNSt6vectorIiSaIiEED2Ev, @function
_ZNSt6vectorIiSaIiEED2Ev:
.LFB5472:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L32
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L32:
ret
.cfi_endproc
.LFE5472:
.size _ZNSt6vectorIiSaIiEED2Ev, .-_ZNSt6vectorIiSaIiEED2Ev
.weak _ZNSt6vectorIiSaIiEED1Ev
.set _ZNSt6vectorIiSaIiEED1Ev,_ZNSt6vectorIiSaIiEED2Ev
.section .rodata._ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_.str1.1,"aMS",@progbits,1
.LC4:
.string "vector::_M_realloc_insert"
.section .text._ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_,"axG",@progbits,_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_
.type _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_, @function
_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_:
.LFB5662:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, (%rsp)
movq %rdx, 8(%rsp)
movq 8(%rdi), %rbp
movq (%rdi), %r13
movq %rbp, %rax
subq %r13, %rax
sarq $2, %rax
movabsq $2305843009213693951, %rdx
cmpq %rdx, %rax
je .L52
movq %rdi, %rbx
cmpq %r13, %rbp
movl $1, %edx
cmovne %rax, %rdx
addq %rdx, %rax
jc .L38
movabsq $2305843009213693951, %r14
cmpq %r14, %rax
cmovbe %rax, %r14
movq (%rsp), %r15
subq %r13, %r15
movl $0, %r12d
testq %rax, %rax
je .L39
jmp .L46
.L52:
leaq .LC4(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L53:
movq %r15, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memmove@PLT
leaq 4(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jg .L41
addq %rbp, %r15
movq 16(%rbx), %rsi
subq %r13, %rsi
jmp .L45
.L38:
movq (%rsp), %r15
subq %r13, %r15
movabsq $2305843009213693951, %r14
.L46:
leaq 0(,%r14,4), %rdi
call _Znwm@PLT
movq %rax, %r12
.L39:
movq 8(%rsp), %rax
movl (%rax), %eax
movl %eax, (%r12,%r15)
testq %r15, %r15
jg .L53
leaq 4(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jle .L43
.L41:
movq %rbp, %rdx
movq (%rsp), %rsi
movq %r15, %rdi
call memcpy@PLT
.L43:
addq %rbp, %r15
testq %r13, %r13
je .L44
movq 16(%rbx), %rsi
subq %r13, %rsi
.L45:
movq %r13, %rdi
call _ZdlPvm@PLT
.L44:
movq %r12, (%rbx)
movq %r15, 8(%rbx)
leaq (%r12,%r14,4), %rax
movq %rax, 16(%rbx)
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5662:
.size _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_, .-_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_
.text
.globl _Z13create_vectori
.type _Z13create_vectori, @function
_Z13create_vectori:
.LFB5071:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA5071
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq $0, (%rdi)
movq $0, 8(%rdi)
movq $0, 16(%rdi)
movl $0, 4(%rsp)
testl %esi, %esi
jle .L54
movl %esi, %r12d
movl $0, %ebx
leaq 4(%rsp), %r13
jmp .L58
.L56:
movq %r13, %rdx
movq %rbp, %rdi
.LEHB0:
call _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_
.LEHE0:
.L57:
addl $1, %ebx
movl %ebx, 4(%rsp)
cmpl %r12d, %ebx
je .L54
.L58:
movq 8(%rbp), %rsi
cmpq 16(%rbp), %rsi
je .L56
movl %ebx, (%rsi)
addq $4, 8(%rbp)
jmp .L57
.L62:
endbr64
movq %rax, %rbx
movq %rbp, %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq 8(%rsp), %rax
subq %fs:40, %rax
je .L60
call __stack_chk_fail@PLT
.L60:
movq %rbx, %rdi
.LEHB1:
call _Unwind_Resume@PLT
.LEHE1:
.L54:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L65
movq %rbp, %rax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L65:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5071:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA5071:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE5071-.LLSDACSB5071
.LLSDACSB5071:
.uleb128 .LEHB0-.LFB5071
.uleb128 .LEHE0-.LEHB0
.uleb128 .L62-.LFB5071
.uleb128 0
.uleb128 .LEHB1-.LFB5071
.uleb128 .LEHE1-.LEHB1
.uleb128 0
.uleb128 0
.LLSDACSE5071:
.text
.size _Z13create_vectori, .-_Z13create_vectori
.section .rodata.str1.1
.LC5:
.string "%d %d\n"
.LC6:
.string "Wrong algorithm"
.LC7:
.string "%s\n"
.LC8:
.string "True algorithm"
.LC9:
.string "%s %d\n"
.text
.globl main
.type main, @function
main:
.LFB5088:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA5088
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $0, %r15d
leaq .LC5(%rip), %rbp
jmp .L83
.L111:
movq 56(%rsp), %r14
movq 48(%rsp), %rbx
cmpq %r14, %rbx
je .L67
leaq 4(%rbx), %r12
cmpq %r12, %r14
je .L67
movq %r12, %r13
jmp .L69
.L68:
addq $4, %r13
cmpq %r13, %r14
je .L100
.L69:
call rand@PLT
cltq
movq %r13, %rcx
subq %rbx, %rcx
sarq $2, %rcx
addq $1, %rcx
cqto
idivq %rcx
leaq (%rbx,%rdx,4), %rax
cmpq %rax, %r13
je .L68
movl 0(%r13), %edx
movl (%rax), %ecx
movl %ecx, 0(%r13)
movl %edx, (%rax)
jmp .L68
.L100:
cmpq %r12, %r14
jne .L71
.L67:
leaq 24(%rsp), %rdi
movl $1, %edx
movl $800, %esi
.LEHB2:
call cudaMallocManaged@PLT
jmp .L101
.L70:
addq $4, %r12
cmpq %r12, %r14
je .L67
.L71:
call rand@PLT
cltq
movq %r12, %rcx
subq %rbx, %rcx
sarq $2, %rcx
addq $1, %rcx
cqto
idivq %rcx
leaq (%rbx,%rdx,4), %rax
cmpq %r12, %rax
je .L70
movl (%r12), %edx
movl (%rax), %ecx
movl %ecx, (%r12)
movl %edx, (%rax)
jmp .L70
.L101:
movl $0, %r12d
jmp .L72
.L103:
addq $4, %r12
cmpq $800, %r12
je .L102
.L72:
movl (%rbx,%r12), %ecx
movq 24(%rsp), %rax
movl %ecx, (%rax,%r12)
movq 24(%rsp), %rax
movl (%rax,%r12), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L103
.L102:
movl $200, %esi
movq 24(%rsp), %rdi
call _Z12print_vectorPii
movl $1024, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 112(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L73
movl $200, %esi
movq 24(%rsp), %rdi
call _Z32__device_stub__Z11bubble_sortPiiPii
.L73:
call cudaDeviceSynchronize@PLT
movq 80(%rsp), %r13
movq $0, 112(%rsp)
movq $0, 120(%rsp)
movq $0, 128(%rsp)
movq 88(%rsp), %r12
subq %r13, %r12
je .L74
movq %r12, 8(%rsp)
movabsq $9223372036854775804, %rax
cmpq %r12, %rax
jb .L104
movq %r12, %rdi
call _Znwm@PLT
jmp .L105
.L104:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L106
call _ZSt28__throw_bad_array_new_lengthv@PLT
.LEHE2:
.L91:
endbr64
movq %rax, %rbx
jmp .L86
.L106:
call __stack_chk_fail@PLT
.L105:
movq %rax, %r14
movq %rax, 112(%rsp)
leaq (%rax,%r12), %rax
movq %rax, (%rsp)
movq %rax, 128(%rsp)
cmpq $4, %r12
jle .L77
movq %r12, %rdx
movq %r13, %rsi
movq %r14, %rdi
call memmove@PLT
.L78:
movq (%rsp), %rax
movq %rax, 120(%rsp)
leaq 112(%rsp), %rsi
movq 24(%rsp), %rdi
.LEHB3:
call _Z15compare_vectorsPiSt6vectorIiSaIiEE
.LEHE3:
jmp .L107
.L77:
movl 0(%r13), %eax
movl %eax, (%r14)
jmp .L78
.L107:
movl %eax, %r12d
testq %r14, %r14
je .L79
movq 8(%rsp), %rsi
movq %r14, %rdi
call _ZdlPvm@PLT
.L79:
testb %r12b, %r12b
je .L108
movl %r15d, %ecx
leaq .LC8(%rip), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
.LEHB4:
call __printf_chk@PLT
jmp .L109
.L108:
leaq .LC6(%rip), %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $200, %esi
movq 24(%rsp), %rdi
call _Z12print_vectorPii
jmp .L110
.L109:
movq 24(%rsp), %rdi
call cudaFree@PLT
.LEHE4:
testq %r13, %r13
je .L82
movq 96(%rsp), %rsi
subq %r13, %rsi
movq %r13, %rdi
call _ZdlPvm@PLT
.L82:
movq 64(%rsp), %rsi
subq %rbx, %rsi
movq %rbx, %rdi
call _ZdlPvm@PLT
addl $1, %r15d
cmpl $100, %r15d
je .L84
.L83:
leaq 48(%rsp), %rdi
movl $200, %esi
.LEHB5:
call _Z13create_vectori
.LEHE5:
leaq 80(%rsp), %rdi
movl $200, %esi
.LEHB6:
call _Z13create_vectori
.LEHE6:
jmp .L111
.L110:
leaq 80(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
leaq 48(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
.L84:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L112
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L92:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 112(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
.L86:
leaq 80(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
.L87:
leaq 48(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq 136(%rsp), %rax
subq %fs:40, %rax
je .L88
call __stack_chk_fail@PLT
.L90:
endbr64
movq %rax, %rbx
jmp .L87
.L88:
movq %rbx, %rdi
.LEHB7:
call _Unwind_Resume@PLT
.LEHE7:
.L74:
movq $0, 112(%rsp)
movq $0, 128(%rsp)
movq $0, (%rsp)
movq $0, 8(%rsp)
movl $0, %r14d
jmp .L78
.L112:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5088:
.section .gcc_except_table
.LLSDA5088:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE5088-.LLSDACSB5088
.LLSDACSB5088:
.uleb128 .LEHB2-.LFB5088
.uleb128 .LEHE2-.LEHB2
.uleb128 .L91-.LFB5088
.uleb128 0
.uleb128 .LEHB3-.LFB5088
.uleb128 .LEHE3-.LEHB3
.uleb128 .L92-.LFB5088
.uleb128 0
.uleb128 .LEHB4-.LFB5088
.uleb128 .LEHE4-.LEHB4
.uleb128 .L91-.LFB5088
.uleb128 0
.uleb128 .LEHB5-.LFB5088
.uleb128 .LEHE5-.LEHB5
.uleb128 0
.uleb128 0
.uleb128 .LEHB6-.LFB5088
.uleb128 .LEHE6-.LEHB6
.uleb128 .L90-.LFB5088
.uleb128 0
.uleb128 .LEHB7-.LFB5088
.uleb128 .LEHE7-.LEHB7
.uleb128 0
.uleb128 0
.LLSDACSE5088:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <math.h>
#include <vector>
#include <string>
#include <algorithm>
#include <random>
#include <chrono>
#include <stdio.h>
#define NB_THREADS 1024
#define NB_NUMBERS 200
#define NB_EXPERIMENTS 100
void print_vector(int* array, int k) {
for(size_t i=0; i < k; i++) {
printf("%d ", array[i]);
}
printf("\n");
}
bool compare_vectors(int *v1, std::vector<int> v2) {
for(int i=0; i < v2.size(); i++) {
if (v1[i] != v2[i]) {
printf("wrong at %d %d vs %d\n", i, v1[i], v2[i]);
return false;
}
}
return true;
}
std::vector<int> create_vector(int N) {
std::vector<int> res;
for(int i=0; i < N; i++) {
res.push_back(i);
}
return res;
}
__global__
void bubble_sort(int *A, int n) {
__shared__ int end[NB_THREADS]; // termination condition for each thread
__shared__ int race[NB_NUMBERS]; // race condition for each element of input array
for (int u=0; u<NB_THREADS; u++) { end[u] = 0; }
for (int v=0; v<NB_NUMBERS; v++) { race[v] = 1; }
int temp;
int index = threadIdx.x;
while (1) {
end[index] = 1;
for (int i=0; i<n; i++) {
while (1) {
if ((race[i] == 1 && race[i-1] == 1) || (i == 0 && race[i] == 1)) {
if (A[i-1] > A[i]) {
// Block race condition
race[i] = 0;
race[i-1] = 0;
// Swap
temp = A[i-1];
A[i-1] = A[i];
A[i] = temp;
// Release race condition
end[index] = 0;
race[i] = 1;
race[i-1] = 1;
}
break;
}
}
}
if (end[index] == 1) { break; }
}
}
int main(void) {
for (int e=0; e<NB_EXPERIMENTS; e++) {
// Init random input array
int range = NB_NUMBERS;
std::vector<int> v = create_vector(range);
std::vector<int> v_orig = create_vector(range);
std::random_shuffle ( v.begin(), v.end() );
std::random_shuffle ( v.begin(), v.end() );
int *x;
cudaMallocManaged(&x, range*sizeof(int));
for (int i = 0; i < range; i++) {
x[i] = v[i];
printf("%d %d\n", x[i], v[i]);
}
print_vector(x, range);
// Sort
bubble_sort<<<1, NB_THREADS>>>(x, range);
cudaDeviceSynchronize();
// Check output
if (!compare_vectors(x, v_orig)) {
printf("%s\n", "Wrong algorithm");
print_vector(x, range);
break;
} else { printf("%s %d\n", "True algorithm", e); }
// Free memory
cudaFree(x);
}
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
#include <vector>
#include <string>
#include <algorithm>
#include <random>
#include <chrono>
#include <stdio.h>
#define NB_THREADS 1024
#define NB_NUMBERS 200
#define NB_EXPERIMENTS 100
void print_vector(int* array, int k) {
for(size_t i=0; i < k; i++) {
printf("%d ", array[i]);
}
printf("\n");
}
bool compare_vectors(int *v1, std::vector<int> v2) {
for(int i=0; i < v2.size(); i++) {
if (v1[i] != v2[i]) {
printf("wrong at %d %d vs %d\n", i, v1[i], v2[i]);
return false;
}
}
return true;
}
std::vector<int> create_vector(int N) {
std::vector<int> res;
for(int i=0; i < N; i++) {
res.push_back(i);
}
return res;
}
__global__
void bubble_sort(int *A, int n) {
__shared__ int end[NB_THREADS]; // termination condition for each thread
__shared__ int race[NB_NUMBERS]; // race condition for each element of input array
for (int u=0; u<NB_THREADS; u++) { end[u] = 0; }
for (int v=0; v<NB_NUMBERS; v++) { race[v] = 1; }
int temp;
int index = threadIdx.x;
while (1) {
end[index] = 1;
for (int i=0; i<n; i++) {
while (1) {
if ((race[i] == 1 && race[i-1] == 1) || (i == 0 && race[i] == 1)) {
if (A[i-1] > A[i]) {
// Block race condition
race[i] = 0;
race[i-1] = 0;
// Swap
temp = A[i-1];
A[i-1] = A[i];
A[i] = temp;
// Release race condition
end[index] = 0;
race[i] = 1;
race[i-1] = 1;
}
break;
}
}
}
if (end[index] == 1) { break; }
}
}
int main(void) {
for (int e=0; e<NB_EXPERIMENTS; e++) {
// Init random input array
int range = NB_NUMBERS;
std::vector<int> v = create_vector(range);
std::vector<int> v_orig = create_vector(range);
std::random_shuffle ( v.begin(), v.end() );
std::random_shuffle ( v.begin(), v.end() );
int *x;
hipMallocManaged(&x, range*sizeof(int));
for (int i = 0; i < range; i++) {
x[i] = v[i];
printf("%d %d\n", x[i], v[i]);
}
print_vector(x, range);
// Sort
bubble_sort<<<1, NB_THREADS>>>(x, range);
hipDeviceSynchronize();
// Check output
if (!compare_vectors(x, v_orig)) {
printf("%s\n", "Wrong algorithm");
print_vector(x, range);
break;
} else { printf("%s %d\n", "True algorithm", e); }
// Free memory
hipFree(x);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
#include <vector>
#include <string>
#include <algorithm>
#include <random>
#include <chrono>
#include <stdio.h>
#define NB_THREADS 1024
#define NB_NUMBERS 200
#define NB_EXPERIMENTS 100
void print_vector(int* array, int k) {
for(size_t i=0; i < k; i++) {
printf("%d ", array[i]);
}
printf("\n");
}
bool compare_vectors(int *v1, std::vector<int> v2) {
for(int i=0; i < v2.size(); i++) {
if (v1[i] != v2[i]) {
printf("wrong at %d %d vs %d\n", i, v1[i], v2[i]);
return false;
}
}
return true;
}
std::vector<int> create_vector(int N) {
std::vector<int> res;
for(int i=0; i < N; i++) {
res.push_back(i);
}
return res;
}
__global__
void bubble_sort(int *A, int n) {
__shared__ int end[NB_THREADS]; // termination condition for each thread
__shared__ int race[NB_NUMBERS]; // race condition for each element of input array
for (int u=0; u<NB_THREADS; u++) { end[u] = 0; }
for (int v=0; v<NB_NUMBERS; v++) { race[v] = 1; }
int temp;
int index = threadIdx.x;
while (1) {
end[index] = 1;
for (int i=0; i<n; i++) {
while (1) {
if ((race[i] == 1 && race[i-1] == 1) || (i == 0 && race[i] == 1)) {
if (A[i-1] > A[i]) {
// Block race condition
race[i] = 0;
race[i-1] = 0;
// Swap
temp = A[i-1];
A[i-1] = A[i];
A[i] = temp;
// Release race condition
end[index] = 0;
race[i] = 1;
race[i-1] = 1;
}
break;
}
}
}
if (end[index] == 1) { break; }
}
}
int main(void) {
for (int e=0; e<NB_EXPERIMENTS; e++) {
// Init random input array
int range = NB_NUMBERS;
std::vector<int> v = create_vector(range);
std::vector<int> v_orig = create_vector(range);
std::random_shuffle ( v.begin(), v.end() );
std::random_shuffle ( v.begin(), v.end() );
int *x;
hipMallocManaged(&x, range*sizeof(int));
for (int i = 0; i < range; i++) {
x[i] = v[i];
printf("%d %d\n", x[i], v[i]);
}
print_vector(x, range);
// Sort
bubble_sort<<<1, NB_THREADS>>>(x, range);
hipDeviceSynchronize();
// Check output
if (!compare_vectors(x, v_orig)) {
printf("%s\n", "Wrong algorithm");
print_vector(x, range);
break;
} else { printf("%s %d\n", "True algorithm", e); }
// Free memory
hipFree(x);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11bubble_sortPii
.globl _Z11bubble_sortPii
.p2align 8
.type _Z11bubble_sortPii,@function
_Z11bubble_sortPii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s4, 0
s_cselect_b32 s5, -1, 0
s_add_u32 s0, s0, -4
s_addc_u32 s1, s1, -1
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_cmp_eq_u32 s6, 1
s_cbranch_scc1 .LBB0_7
.LBB0_2:
s_and_not1_b32 vcc_lo, exec_lo, s5
s_mov_b32 s6, 1
s_cbranch_vccnz .LBB0_1
s_mov_b32 s7, s4
s_mov_b64 s[2:3], s[0:1]
s_branch .LBB0_5
.LBB0_4:
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_add_i32 s7, s7, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s7, 0
s_cbranch_scc1 .LBB0_1
.LBB0_5:
global_load_b64 v[0:1], v2, s[2:3]
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v0, v1
s_cbranch_vccz .LBB0_4
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v4, v0
s_mov_b32 s6, 0
global_store_b64 v2, v[3:4], s[2:3]
s_branch .LBB0_4
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11bubble_sortPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11bubble_sortPii, .Lfunc_end0-_Z11bubble_sortPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11bubble_sortPii
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z11bubble_sortPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
#include <vector>
#include <string>
#include <algorithm>
#include <random>
#include <chrono>
#include <stdio.h>
#define NB_THREADS 1024
#define NB_NUMBERS 200
#define NB_EXPERIMENTS 100
void print_vector(int* array, int k) {
for(size_t i=0; i < k; i++) {
printf("%d ", array[i]);
}
printf("\n");
}
bool compare_vectors(int *v1, std::vector<int> v2) {
for(int i=0; i < v2.size(); i++) {
if (v1[i] != v2[i]) {
printf("wrong at %d %d vs %d\n", i, v1[i], v2[i]);
return false;
}
}
return true;
}
std::vector<int> create_vector(int N) {
std::vector<int> res;
for(int i=0; i < N; i++) {
res.push_back(i);
}
return res;
}
__global__
void bubble_sort(int *A, int n) {
__shared__ int end[NB_THREADS]; // termination condition for each thread
__shared__ int race[NB_NUMBERS]; // race condition for each element of input array
for (int u=0; u<NB_THREADS; u++) { end[u] = 0; }
for (int v=0; v<NB_NUMBERS; v++) { race[v] = 1; }
int temp;
int index = threadIdx.x;
while (1) {
end[index] = 1;
for (int i=0; i<n; i++) {
while (1) {
if ((race[i] == 1 && race[i-1] == 1) || (i == 0 && race[i] == 1)) {
if (A[i-1] > A[i]) {
// Block race condition
race[i] = 0;
race[i-1] = 0;
// Swap
temp = A[i-1];
A[i-1] = A[i];
A[i] = temp;
// Release race condition
end[index] = 0;
race[i] = 1;
race[i-1] = 1;
}
break;
}
}
}
if (end[index] == 1) { break; }
}
}
int main(void) {
for (int e=0; e<NB_EXPERIMENTS; e++) {
// Init random input array
int range = NB_NUMBERS;
std::vector<int> v = create_vector(range);
std::vector<int> v_orig = create_vector(range);
std::random_shuffle ( v.begin(), v.end() );
std::random_shuffle ( v.begin(), v.end() );
int *x;
hipMallocManaged(&x, range*sizeof(int));
for (int i = 0; i < range; i++) {
x[i] = v[i];
printf("%d %d\n", x[i], v[i]);
}
print_vector(x, range);
// Sort
bubble_sort<<<1, NB_THREADS>>>(x, range);
hipDeviceSynchronize();
// Check output
if (!compare_vectors(x, v_orig)) {
printf("%s\n", "Wrong algorithm");
print_vector(x, range);
break;
} else { printf("%s %d\n", "True algorithm", e); }
// Free memory
hipFree(x);
}
} | .text
.file "gpu_sort.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z12print_vectorPii # -- Begin function _Z12print_vectorPii
.p2align 4, 0x90
.type _Z12print_vectorPii,@function
_Z12print_vectorPii: # @_Z12print_vectorPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
je .LBB0_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movslq %esi, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB0_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB0_4: # %._crit_edge
movl $10, %edi
jmp putchar@PLT # TAILCALL
.Lfunc_end0:
.size _Z12print_vectorPii, .Lfunc_end0-_Z12print_vectorPii
.cfi_endproc
# -- End function
.globl _Z15compare_vectorsPiSt6vectorIiSaIiEE # -- Begin function _Z15compare_vectorsPiSt6vectorIiSaIiEE
.p2align 4, 0x90
.type _Z15compare_vectorsPiSt6vectorIiSaIiEE,@function
_Z15compare_vectorsPiSt6vectorIiSaIiEE: # @_Z15compare_vectorsPiSt6vectorIiSaIiEE
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq (%rsi), %r8
movq 8(%rsi), %rax
subq %r8, %rax
sete %bl
je .LBB1_8
# %bb.1: # %.lr.ph.preheader
sarq $2, %rax
cmpq $1, %rax
movq %rax, %r9
adcq $0, %r9
movl (%rdi), %edx
movl (%r8), %ecx
xorl %esi, %esi
cmpl %ecx, %edx
jne .LBB1_6
# %bb.2: # %.lr.ph34.preheader
decq %r9
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_3: # %.lr.ph34
# =>This Inner Loop Header: Depth=1
cmpq %rsi, %r9
je .LBB1_7
# %bb.4: # %.lr.ph
# in Loop: Header=BB1_3 Depth=1
movl 4(%rdi,%rsi,4), %edx
movl 4(%r8,%rsi,4), %ecx
incq %rsi
cmpl %ecx, %edx
je .LBB1_3
# %bb.5: # %.lr.ph._crit_edge
cmpq %rsi, %rax
setbe %bl
.LBB1_6:
movl $.L.str.2, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
jmp .LBB1_8
.LBB1_7: # %.loopexit.loopexit
incq %rsi
cmpq %rsi, %rax
setbe %bl
.LBB1_8: # %.loopexit
movl %ebx, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z15compare_vectorsPiSt6vectorIiSaIiEE, .Lfunc_end1-_Z15compare_vectorsPiSt6vectorIiSaIiEE
.cfi_endproc
# -- End function
.globl _Z13create_vectori # -- Begin function _Z13create_vectori
.p2align 4, 0x90
.type _Z13create_vectori,@function
_Z13create_vectori: # @_Z13create_vectori
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
xorps %xmm0, %xmm0
movups %xmm0, (%rdi)
movq $0, 16(%rdi)
xorl %r13d, %r13d
testl %esi, %esi
jle .LBB2_1
# %bb.3: # %.lr.ph
movabsq $2305843009213693951, %rbp # imm = 0x1FFFFFFFFFFFFFFF
xorl %eax, %eax
movl %esi, 20(%rsp) # 4-byte Spill
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_5: # in Loop: Header=BB2_4 Depth=1
movl %r13d, (%r15)
addq $4, %r15
movq %r15, 8(%rbx)
movq %rax, %r12
.LBB2_22: # %_ZNSt6vectorIiSaIiEE9push_backERKi.exit
# in Loop: Header=BB2_4 Depth=1
incl %r13d
cmpl %r13d, %esi
je .LBB2_2
.LBB2_4: # =>This Inner Loop Header: Depth=1
movq 8(%rbx), %r15
cmpq 16(%rbx), %r15
jne .LBB2_5
# %bb.6: # in Loop: Header=BB2_4 Depth=1
movq %rax, 8(%rsp) # 8-byte Spill
subq %rax, %r15
movabsq $9223372036854775804, %rax # imm = 0x7FFFFFFFFFFFFFFC
cmpq %rax, %r15
je .LBB2_7
# %bb.9: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i
# in Loop: Header=BB2_4 Depth=1
movq %r15, %r14
sarq $2, %r14
cmpq $1, %r14
movq %r14, %rax
adcq $0, %rax
leaq (%rax,%r14), %rcx
cmpq %rbp, %rcx
jae .LBB2_10
# %bb.11: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i
# in Loop: Header=BB2_4 Depth=1
addq %r14, %rax
jae .LBB2_12
.LBB2_13: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i
# in Loop: Header=BB2_4 Depth=1
testq %rbp, %rbp
je .LBB2_14
.LBB2_15: # in Loop: Header=BB2_4 Depth=1
leaq (,%rbp,4), %rdi
.Ltmp0:
callq _Znwm
.Ltmp1:
# %bb.16: # in Loop: Header=BB2_4 Depth=1
movq %rax, %r12
jmp .LBB2_17
.LBB2_10: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i
# in Loop: Header=BB2_4 Depth=1
movq %rbp, %rcx
addq %r14, %rax
jb .LBB2_13
.LBB2_12: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i
# in Loop: Header=BB2_4 Depth=1
movq %rcx, %rbp
testq %rbp, %rbp
jne .LBB2_15
.LBB2_14: # in Loop: Header=BB2_4 Depth=1
xorl %r12d, %r12d
.LBB2_17: # %_ZNSt12_Vector_baseIiSaIiEE11_M_allocateEm.exit.i.i
# in Loop: Header=BB2_4 Depth=1
movl %r13d, (%r12,%r14,4)
testq %r15, %r15
movq 8(%rsp), %r14 # 8-byte Reload
jle .LBB2_19
# %bb.18: # in Loop: Header=BB2_4 Depth=1
movq %r12, %rdi
movq %r14, %rsi
movq %r15, %rdx
callq memmove@PLT
.LBB2_19: # %_ZNSt6vectorIiSaIiEE11_S_relocateEPiS2_S2_RS0_.exit.i.i
# in Loop: Header=BB2_4 Depth=1
testq %r14, %r14
je .LBB2_21
# %bb.20: # in Loop: Header=BB2_4 Depth=1
movq %r14, %rdi
callq _ZdlPv
.LBB2_21: # %_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_.exit.i
# in Loop: Header=BB2_4 Depth=1
leaq (%r12,%r15), %rax
addq $4, %rax
movq %rax, 8(%rbx)
leaq (%r12,%rbp,4), %rax
movq %rax, 16(%rbx)
movq %r12, %rax
movl 20(%rsp), %esi # 4-byte Reload
movabsq $2305843009213693951, %rbp # imm = 0x1FFFFFFFFFFFFFFF
jmp .LBB2_22
.LBB2_1:
xorl %r12d, %r12d
.LBB2_2: # %._crit_edge
movq %r12, (%rbx)
movq %rbx, %rax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_7:
.cfi_def_cfa_offset 80
movq 8(%rsp), %rax # 8-byte Reload
movq %rax, (%rbx)
.Ltmp3:
movl $.L.str.8, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp4:
# %bb.8: # %.noexc
.LBB2_23: # %.loopexit
.Ltmp2:
movq %rax, %r15
movq 8(%rsp), %rax # 8-byte Reload
movq %rax, (%rbx)
jmp .LBB2_25
.LBB2_24: # %.loopexit.split-lp
.Ltmp5:
movq %rax, %r15
.LBB2_25:
cmpq $0, 8(%rsp) # 8-byte Folded Reload
je .LBB2_27
# %bb.26:
movq 8(%rsp), %rdi # 8-byte Reload
callq _ZdlPv
.LBB2_27: # %_ZNSt6vectorIiSaIiEED2Ev.exit
movq %r15, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size _Z13create_vectori, .Lfunc_end2-_Z13create_vectori
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp3-.Ltmp1 # Call between .Ltmp1 and .Ltmp3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Lfunc_end2-.Ltmp4 # Call between .Ltmp4 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.globl _Z26__device_stub__bubble_sortPii # -- Begin function _Z26__device_stub__bubble_sortPii
.p2align 4, 0x90
.type _Z26__device_stub__bubble_sortPii,@function
_Z26__device_stub__bubble_sortPii: # @_Z26__device_stub__bubble_sortPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11bubble_sortPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z26__device_stub__bubble_sortPii, .Lfunc_end3-_Z26__device_stub__bubble_sortPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $0, 4(%rsp) # 4-byte Folded Spill
jmp .LBB4_1
.p2align 4, 0x90
.LBB4_66: # %_ZNSt6vectorIiSaIiEED2Ev.exit56
# in Loop: Header=BB4_1 Depth=1
movl 4(%rsp), %eax # 4-byte Reload
incl %eax
movl %eax, 4(%rsp) # 4-byte Spill
cmpl $100, %eax
setne %al
testb %al, %r13b
je .LBB4_67
.LBB4_1: # =>This Loop Header: Depth=1
# Child Loop BB4_5 Depth 2
# Child Loop BB4_11 Depth 2
# Child Loop BB4_16 Depth 2
# Child Loop BB4_18 Depth 2
# Child Loop BB4_53 Depth 2
# Child Loop BB4_59 Depth 2
.cfi_escape 0x2e, 0x00
leaq 128(%rsp), %rdi
movl $200, %esi
callq _Z13create_vectori
.Ltmp6:
.cfi_escape 0x2e, 0x00
leaq 104(%rsp), %rdi
movl $200, %esi
callq _Z13create_vectori
.Ltmp7:
# %bb.2: # in Loop: Header=BB4_1 Depth=1
movq 128(%rsp), %rbx
movq 136(%rsp), %r14
cmpq %r14, %rbx
je .LBB4_14
# %bb.3: # %.preheader.i
# in Loop: Header=BB4_1 Depth=1
leaq 4(%rbx), %r15
cmpq %r14, %r15
je .LBB4_8
# %bb.4: # %.lr.ph.i
# in Loop: Header=BB4_1 Depth=1
movl $4, %r12d
jmp .LBB4_5
.p2align 4, 0x90
.LBB4_7: # in Loop: Header=BB4_5 Depth=2
leaq (%rbx,%r12), %rax
addq $4, %rax
addq $4, %r12
cmpq %r14, %rax
je .LBB4_8
.LBB4_5: # Parent Loop BB4_1 Depth=1
# => This Inner Loop Header: Depth=2
.cfi_escape 0x2e, 0x00
callq rand
cltq
movq %r12, %rcx
sarq $2, %rcx
incq %rcx
cqto
idivq %rcx
leaq (,%rdx,4), %rax
cmpq %rax, %r12
je .LBB4_7
# %bb.6: # in Loop: Header=BB4_5 Depth=2
leaq (%rbx,%r12), %rax
leaq (%rbx,%rdx,4), %rcx
movl (%rax), %edx
movl (%rcx), %esi
movl %esi, (%rax)
movl %edx, (%rcx)
jmp .LBB4_7
.p2align 4, 0x90
.LBB4_8: # %_ZSt14random_shuffleIN9__gnu_cxx17__normal_iteratorIPiSt6vectorIiSaIiEEEEEvT_S7_.exit
# in Loop: Header=BB4_1 Depth=1
cmpq %r14, %rbx
je .LBB4_14
# %bb.9: # %.preheader.i34
# in Loop: Header=BB4_1 Depth=1
cmpq %r14, %r15
je .LBB4_14
# %bb.10: # %.lr.ph.i36
# in Loop: Header=BB4_1 Depth=1
movl $4, %r15d
jmp .LBB4_11
.p2align 4, 0x90
.LBB4_13: # in Loop: Header=BB4_11 Depth=2
leaq (%rbx,%r15), %rax
addq $4, %rax
addq $4, %r15
cmpq %r14, %rax
je .LBB4_14
.LBB4_11: # Parent Loop BB4_1 Depth=1
# => This Inner Loop Header: Depth=2
.cfi_escape 0x2e, 0x00
callq rand
cltq
movq %r15, %rcx
sarq $2, %rcx
incq %rcx
cqto
idivq %rcx
leaq (,%rdx,4), %rax
cmpq %rax, %r15
je .LBB4_13
# %bb.12: # in Loop: Header=BB4_11 Depth=2
leaq (%rbx,%r15), %rax
leaq (%rbx,%rdx,4), %rcx
movl (%rax), %edx
movl (%rcx), %esi
movl %esi, (%rax)
movl %edx, (%rcx)
jmp .LBB4_13
.p2align 4, 0x90
.LBB4_14: # %_ZSt14random_shuffleIN9__gnu_cxx17__normal_iteratorIPiSt6vectorIiSaIiEEEEEvT_S7_.exit39
# in Loop: Header=BB4_1 Depth=1
.Ltmp9:
.cfi_escape 0x2e, 0x00
movl $800, %esi # imm = 0x320
leaq 8(%rsp), %rdi
movl $1, %edx
callq hipMallocManaged
.Ltmp10:
# %bb.15: # %_ZL16hipMallocManagedIiE10hipError_tPPT_mj.exit.preheader
# in Loop: Header=BB4_1 Depth=1
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_16: # %_ZL16hipMallocManagedIiE10hipError_tPPT_mj.exit
# Parent Loop BB4_1 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r14,4), %esi
movq 8(%rsp), %rax
movl %esi, (%rax,%r14,4)
movl (%rbx,%r14,4), %edx
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $200, %r14
jne .LBB4_16
# %bb.17: # in Loop: Header=BB4_1 Depth=1
movq 8(%rsp), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_18: # %.lr.ph.i40
# Parent Loop BB4_1 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r15,4), %esi
.cfi_escape 0x2e, 0x00
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $200, %r15
jne .LBB4_18
# %bb.19: # %_Z12print_vectorPii.exit
# in Loop: Header=BB4_1 Depth=1
.cfi_escape 0x2e, 0x00
movl $10, %edi
callq putchar@PLT
.Ltmp11:
.cfi_escape 0x2e, 0x00
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movabsq $4294968320, %rdx # imm = 0x100000400
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp12:
# %bb.20: # in Loop: Header=BB4_1 Depth=1
testl %eax, %eax
jne .LBB4_23
# %bb.21: # in Loop: Header=BB4_1 Depth=1
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $200, 20(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
.Ltmp13:
.cfi_escape 0x2e, 0x00
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp14:
# %bb.22: # %.noexc
# in Loop: Header=BB4_1 Depth=1
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
.Ltmp15:
.cfi_escape 0x2e, 0x10
movl $_Z11bubble_sortPii, %edi
leaq 80(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp16:
.LBB4_23: # in Loop: Header=BB4_1 Depth=1
.Ltmp17:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.Ltmp18:
# %bb.24: # in Loop: Header=BB4_1 Depth=1
movq 8(%rsp), %rbp
movq 104(%rsp), %r14
movq 112(%rsp), %r13
movq %r13, %r12
subq %r14, %r12
je .LBB4_25
# %bb.34: # in Loop: Header=BB4_1 Depth=1
movq %r12, %rax
sarq $2, %rax
movq %rax, %rcx
shrq $61, %rcx
jne .LBB4_35
# %bb.40: # %_ZNSt16allocator_traitsISaIiEE8allocateERS0_m.exit.i.i.i.i
# in Loop: Header=BB4_1 Depth=1
.Ltmp19:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _Znwm
.Ltmp20:
# %bb.41: # in Loop: Header=BB4_1 Depth=1
movq %rax, %r15
cmpq $5, %r12
jl .LBB4_44
.LBB4_43: # in Loop: Header=BB4_1 Depth=1
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movq %r14, %rsi
movq %r12, %rdx
callq memmove@PLT
.LBB4_46: # %_ZNSt6vectorIiSaIiEEC2ERKS1_.exit
# in Loop: Header=BB4_1 Depth=1
cmpq %r14, %r13
sete %r13b
je .LBB4_55
# %bb.47: # %.lr.ph.preheader.i
# in Loop: Header=BB4_1 Depth=1
sarq $2, %r12
cmpq $1, %r12
movq %r12, %rax
adcq $0, %rax
movl (%rbp), %edx
movl (%r15), %ecx
cmpl %ecx, %edx
jne .LBB4_48
# %bb.52: # %.lr.ph.preheader
# in Loop: Header=BB4_1 Depth=1
movl $1, %esi
.p2align 4, 0x90
.LBB4_53: # %.lr.ph
# Parent Loop BB4_1 Depth=1
# => This Inner Loop Header: Depth=2
cmpq %rsi, %rax
je .LBB4_54
# %bb.49: # %.lr.ph.i45
# in Loop: Header=BB4_53 Depth=2
movl (%rbp,%rsi,4), %edx
movl (%r15,%rsi,4), %ecx
incq %rsi
cmpl %ecx, %edx
je .LBB4_53
# %bb.50: # %.lr.ph.i45._crit_edge.loopexit
# in Loop: Header=BB4_1 Depth=1
decq %rsi
cmpq %rsi, %r12
setbe %r13b
jmp .LBB4_51
.p2align 4, 0x90
.LBB4_25: # in Loop: Header=BB4_1 Depth=1
xorl %r15d, %r15d
cmpq $5, %r12
jge .LBB4_43
.LBB4_44: # in Loop: Header=BB4_1 Depth=1
cmpq $4, %r12
jne .LBB4_46
# %bb.45: # in Loop: Header=BB4_1 Depth=1
movl (%r14), %eax
movl %eax, (%r15)
jmp .LBB4_46
.p2align 4, 0x90
.LBB4_48: # in Loop: Header=BB4_1 Depth=1
xorl %esi, %esi
xorl %r13d, %r13d
.LBB4_51: # %.lr.ph.i45._crit_edge
# in Loop: Header=BB4_1 Depth=1
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
.LBB4_55: # %_Z15compare_vectorsPiSt6vectorIiSaIiEE.exit
# in Loop: Header=BB4_1 Depth=1
testq %r15, %r15
je .LBB4_57
.LBB4_56: # in Loop: Header=BB4_1 Depth=1
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZdlPv
.LBB4_57: # %_ZNSt6vectorIiSaIiEED2Ev.exit
# in Loop: Header=BB4_1 Depth=1
testb %r13b, %r13b
je .LBB4_58
# %bb.61: # in Loop: Header=BB4_1 Depth=1
.cfi_escape 0x2e, 0x00
movl $.L.str.6, %edi
movl $.L.str.7, %esi
movl 4(%rsp), %edx # 4-byte Reload
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
.Ltmp26:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp27:
# %bb.62: # in Loop: Header=BB4_1 Depth=1
testq %r14, %r14
je .LBB4_64
.LBB4_63: # in Loop: Header=BB4_1 Depth=1
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.LBB4_64: # %_ZNSt6vectorIiSaIiEED2Ev.exit54
# in Loop: Header=BB4_1 Depth=1
testq %rbx, %rbx
je .LBB4_66
# %bb.65: # in Loop: Header=BB4_1 Depth=1
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
jmp .LBB4_66
.p2align 4, 0x90
.LBB4_58: # in Loop: Header=BB4_1 Depth=1
.cfi_escape 0x2e, 0x00
movl $.L.str.5, %edi
callq puts@PLT
movq 8(%rsp), %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_59: # %.lr.ph.i46
# Parent Loop BB4_1 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r15,%r12,4), %esi
.cfi_escape 0x2e, 0x00
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $200, %r12
jne .LBB4_59
# %bb.60: # %_Z12print_vectorPii.exit50
# in Loop: Header=BB4_1 Depth=1
.cfi_escape 0x2e, 0x00
movl $10, %edi
callq putchar@PLT
testq %r14, %r14
jne .LBB4_63
jmp .LBB4_64
.LBB4_54: # %_Z15compare_vectorsPiSt6vectorIiSaIiEE.exit.loopexit
# in Loop: Header=BB4_1 Depth=1
cmpq %rsi, %r12
setbe %r13b
testq %r15, %r15
jne .LBB4_56
jmp .LBB4_57
.LBB4_67:
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_35:
.cfi_def_cfa_offset 208
shrq $62, %rax
je .LBB4_38
# %bb.36: # %.noexc.i.i
.Ltmp23:
.cfi_escape 0x2e, 0x00
callq _ZSt28__throw_bad_array_new_lengthv
.Ltmp24:
# %bb.37: # %.noexc42
.LBB4_38: # %.noexc4.i.i
.Ltmp21:
.cfi_escape 0x2e, 0x00
callq _ZSt17__throw_bad_allocv
.Ltmp22:
# %bb.39: # %.noexc43
.LBB4_26:
.Ltmp8:
movq %rax, %rbx
jmp .LBB4_27
.LBB4_30: # %.loopexit
.Ltmp28:
jmp .LBB4_32
.LBB4_31: # %.loopexit.split-lp
.Ltmp25:
.LBB4_32:
movq %rax, %rbx
movq 104(%rsp), %rdi
testq %rdi, %rdi
je .LBB4_27
# %bb.33:
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB4_27: # %_ZNSt6vectorIiSaIiEED2Ev.exit58
movq 128(%rsp), %rdi
testq %rdi, %rdi
je .LBB4_29
# %bb.28:
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB4_29: # %_ZNSt6vectorIiSaIiEED2Ev.exit60
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table4:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Lfunc_begin1-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp6-.Lfunc_begin1 # Call between .Lfunc_begin1 and .Ltmp6
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin1 # >> Call Site 2 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin1 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin1 # >> Call Site 3 <<
.uleb128 .Ltmp20-.Ltmp9 # Call between .Ltmp9 and .Ltmp20
.uleb128 .Ltmp28-.Lfunc_begin1 # jumps to .Ltmp28
.byte 0 # On action: cleanup
.uleb128 .Ltmp20-.Lfunc_begin1 # >> Call Site 4 <<
.uleb128 .Ltmp26-.Ltmp20 # Call between .Ltmp20 and .Ltmp26
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp26-.Lfunc_begin1 # >> Call Site 5 <<
.uleb128 .Ltmp27-.Ltmp26 # Call between .Ltmp26 and .Ltmp27
.uleb128 .Ltmp28-.Lfunc_begin1 # jumps to .Ltmp28
.byte 0 # On action: cleanup
.uleb128 .Ltmp23-.Lfunc_begin1 # >> Call Site 6 <<
.uleb128 .Ltmp22-.Ltmp23 # Call between .Ltmp23 and .Ltmp22
.uleb128 .Ltmp25-.Lfunc_begin1 # jumps to .Ltmp25
.byte 0 # On action: cleanup
.uleb128 .Ltmp22-.Lfunc_begin1 # >> Call Site 7 <<
.uleb128 .Lfunc_end4-.Ltmp22 # Call between .Ltmp22 and .Lfunc_end4
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end1:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11bubble_sortPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "wrong at %d %d vs %d\n"
.size .L.str.2, 22
.type _Z11bubble_sortPii,@object # @_Z11bubble_sortPii
.section .rodata,"a",@progbits
.globl _Z11bubble_sortPii
.p2align 3, 0x0
_Z11bubble_sortPii:
.quad _Z26__device_stub__bubble_sortPii
.size _Z11bubble_sortPii, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "%d %d\n"
.size .L.str.3, 7
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Wrong algorithm"
.size .L.str.5, 16
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%s %d\n"
.size .L.str.6, 7
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "True algorithm"
.size .L.str.7, 15
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "vector::_M_realloc_insert"
.size .L.str.8, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11bubble_sortPii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Z26__device_stub__bubble_sortPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z11bubble_sortPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000326a2_00000000-6_gpu_sort.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB5091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5091:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl _Z12print_vectorPii
.type _Z12print_vectorPii, @function
_Z12print_vectorPii:
.LFB5069:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
testl %esi, %esi
je .L4
movq %rdi, %rbp
movslq %esi, %r12
movl $0, %ebx
leaq .LC0(%rip), %r13
.L5:
movl 0(%rbp,%rbx,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %r12, %rbx
jne .L5
.L4:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5069:
.size _Z12print_vectorPii, .-_Z12print_vectorPii
.section .rodata.str1.1
.LC2:
.string "wrong at %d %d vs %d\n"
.text
.globl _Z15compare_vectorsPiSt6vectorIiSaIiEE
.type _Z15compare_vectorsPiSt6vectorIiSaIiEE, @function
_Z15compare_vectorsPiSt6vectorIiSaIiEE:
.LFB5070:
.cfi_startproc
endbr64
movq 8(%rsi), %rdx
movq (%rsi), %rax
movq %rdx, %rsi
subq %rax, %rsi
sarq $2, %rsi
cmpq %rax, %rdx
je .L12
movl $0, %edx
.L11:
movl (%rdi,%rdx,4), %ecx
movl (%rax,%rdx,4), %r8d
cmpl %r8d, %ecx
jne .L18
addq $1, %rdx
cmpq %rsi, %rdx
jb .L11
movl $1, %eax
ret
.L18:
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L12:
movl $1, %eax
ret
.cfi_endproc
.LFE5070:
.size _Z15compare_vectorsPiSt6vectorIiSaIiEE, .-_Z15compare_vectorsPiSt6vectorIiSaIiEE
.globl _Z32__device_stub__Z11bubble_sortPiiPii
.type _Z32__device_stub__Z11bubble_sortPiiPii, @function
_Z32__device_stub__Z11bubble_sortPiiPii:
.LFB5113:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11bubble_sortPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5113:
.size _Z32__device_stub__Z11bubble_sortPiiPii, .-_Z32__device_stub__Z11bubble_sortPiiPii
.globl _Z11bubble_sortPii
.type _Z11bubble_sortPii, @function
_Z11bubble_sortPii:
.LFB5114:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z11bubble_sortPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5114:
.size _Z11bubble_sortPii, .-_Z11bubble_sortPii
.section .rodata.str1.1
.LC3:
.string "_Z11bubble_sortPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB5116:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z11bubble_sortPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5116:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIiSaIiEED2Ev,"axG",@progbits,_ZNSt6vectorIiSaIiEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEED2Ev
.type _ZNSt6vectorIiSaIiEED2Ev, @function
_ZNSt6vectorIiSaIiEED2Ev:
.LFB5472:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L32
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L32:
ret
.cfi_endproc
.LFE5472:
.size _ZNSt6vectorIiSaIiEED2Ev, .-_ZNSt6vectorIiSaIiEED2Ev
.weak _ZNSt6vectorIiSaIiEED1Ev
.set _ZNSt6vectorIiSaIiEED1Ev,_ZNSt6vectorIiSaIiEED2Ev
.section .rodata._ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_.str1.1,"aMS",@progbits,1
.LC4:
.string "vector::_M_realloc_insert"
.section .text._ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_,"axG",@progbits,_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_
.type _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_, @function
_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_:
.LFB5662:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, (%rsp)
movq %rdx, 8(%rsp)
movq 8(%rdi), %rbp
movq (%rdi), %r13
movq %rbp, %rax
subq %r13, %rax
sarq $2, %rax
movabsq $2305843009213693951, %rdx
cmpq %rdx, %rax
je .L52
movq %rdi, %rbx
cmpq %r13, %rbp
movl $1, %edx
cmovne %rax, %rdx
addq %rdx, %rax
jc .L38
movabsq $2305843009213693951, %r14
cmpq %r14, %rax
cmovbe %rax, %r14
movq (%rsp), %r15
subq %r13, %r15
movl $0, %r12d
testq %rax, %rax
je .L39
jmp .L46
.L52:
leaq .LC4(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L53:
movq %r15, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memmove@PLT
leaq 4(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jg .L41
addq %rbp, %r15
movq 16(%rbx), %rsi
subq %r13, %rsi
jmp .L45
.L38:
movq (%rsp), %r15
subq %r13, %r15
movabsq $2305843009213693951, %r14
.L46:
leaq 0(,%r14,4), %rdi
call _Znwm@PLT
movq %rax, %r12
.L39:
movq 8(%rsp), %rax
movl (%rax), %eax
movl %eax, (%r12,%r15)
testq %r15, %r15
jg .L53
leaq 4(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jle .L43
.L41:
movq %rbp, %rdx
movq (%rsp), %rsi
movq %r15, %rdi
call memcpy@PLT
.L43:
addq %rbp, %r15
testq %r13, %r13
je .L44
movq 16(%rbx), %rsi
subq %r13, %rsi
.L45:
movq %r13, %rdi
call _ZdlPvm@PLT
.L44:
movq %r12, (%rbx)
movq %r15, 8(%rbx)
leaq (%r12,%r14,4), %rax
movq %rax, 16(%rbx)
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5662:
.size _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_, .-_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_
.text
.globl _Z13create_vectori
.type _Z13create_vectori, @function
_Z13create_vectori:
.LFB5071:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA5071
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq $0, (%rdi)
movq $0, 8(%rdi)
movq $0, 16(%rdi)
movl $0, 4(%rsp)
testl %esi, %esi
jle .L54
movl %esi, %r12d
movl $0, %ebx
leaq 4(%rsp), %r13
jmp .L58
.L56:
movq %r13, %rdx
movq %rbp, %rdi
.LEHB0:
call _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_
.LEHE0:
.L57:
addl $1, %ebx
movl %ebx, 4(%rsp)
cmpl %r12d, %ebx
je .L54
.L58:
movq 8(%rbp), %rsi
cmpq 16(%rbp), %rsi
je .L56
movl %ebx, (%rsi)
addq $4, 8(%rbp)
jmp .L57
.L62:
endbr64
movq %rax, %rbx
movq %rbp, %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq 8(%rsp), %rax
subq %fs:40, %rax
je .L60
call __stack_chk_fail@PLT
.L60:
movq %rbx, %rdi
.LEHB1:
call _Unwind_Resume@PLT
.LEHE1:
.L54:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L65
movq %rbp, %rax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L65:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5071:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA5071:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE5071-.LLSDACSB5071
.LLSDACSB5071:
.uleb128 .LEHB0-.LFB5071
.uleb128 .LEHE0-.LEHB0
.uleb128 .L62-.LFB5071
.uleb128 0
.uleb128 .LEHB1-.LFB5071
.uleb128 .LEHE1-.LEHB1
.uleb128 0
.uleb128 0
.LLSDACSE5071:
.text
.size _Z13create_vectori, .-_Z13create_vectori
.section .rodata.str1.1
.LC5:
.string "%d %d\n"
.LC6:
.string "Wrong algorithm"
.LC7:
.string "%s\n"
.LC8:
.string "True algorithm"
.LC9:
.string "%s %d\n"
.text
.globl main
.type main, @function
main:
.LFB5088:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA5088
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $0, %r15d
leaq .LC5(%rip), %rbp
jmp .L83
.L111:
movq 56(%rsp), %r14
movq 48(%rsp), %rbx
cmpq %r14, %rbx
je .L67
leaq 4(%rbx), %r12
cmpq %r12, %r14
je .L67
movq %r12, %r13
jmp .L69
.L68:
addq $4, %r13
cmpq %r13, %r14
je .L100
.L69:
call rand@PLT
cltq
movq %r13, %rcx
subq %rbx, %rcx
sarq $2, %rcx
addq $1, %rcx
cqto
idivq %rcx
leaq (%rbx,%rdx,4), %rax
cmpq %rax, %r13
je .L68
movl 0(%r13), %edx
movl (%rax), %ecx
movl %ecx, 0(%r13)
movl %edx, (%rax)
jmp .L68
.L100:
cmpq %r12, %r14
jne .L71
.L67:
leaq 24(%rsp), %rdi
movl $1, %edx
movl $800, %esi
.LEHB2:
call cudaMallocManaged@PLT
jmp .L101
.L70:
addq $4, %r12
cmpq %r12, %r14
je .L67
.L71:
call rand@PLT
cltq
movq %r12, %rcx
subq %rbx, %rcx
sarq $2, %rcx
addq $1, %rcx
cqto
idivq %rcx
leaq (%rbx,%rdx,4), %rax
cmpq %r12, %rax
je .L70
movl (%r12), %edx
movl (%rax), %ecx
movl %ecx, (%r12)
movl %edx, (%rax)
jmp .L70
.L101:
movl $0, %r12d
jmp .L72
.L103:
addq $4, %r12
cmpq $800, %r12
je .L102
.L72:
movl (%rbx,%r12), %ecx
movq 24(%rsp), %rax
movl %ecx, (%rax,%r12)
movq 24(%rsp), %rax
movl (%rax,%r12), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L103
.L102:
movl $200, %esi
movq 24(%rsp), %rdi
call _Z12print_vectorPii
movl $1024, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 112(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L73
movl $200, %esi
movq 24(%rsp), %rdi
call _Z32__device_stub__Z11bubble_sortPiiPii
.L73:
call cudaDeviceSynchronize@PLT
movq 80(%rsp), %r13
movq $0, 112(%rsp)
movq $0, 120(%rsp)
movq $0, 128(%rsp)
movq 88(%rsp), %r12
subq %r13, %r12
je .L74
movq %r12, 8(%rsp)
movabsq $9223372036854775804, %rax
cmpq %r12, %rax
jb .L104
movq %r12, %rdi
call _Znwm@PLT
jmp .L105
.L104:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L106
call _ZSt28__throw_bad_array_new_lengthv@PLT
.LEHE2:
.L91:
endbr64
movq %rax, %rbx
jmp .L86
.L106:
call __stack_chk_fail@PLT
.L105:
movq %rax, %r14
movq %rax, 112(%rsp)
leaq (%rax,%r12), %rax
movq %rax, (%rsp)
movq %rax, 128(%rsp)
cmpq $4, %r12
jle .L77
movq %r12, %rdx
movq %r13, %rsi
movq %r14, %rdi
call memmove@PLT
.L78:
movq (%rsp), %rax
movq %rax, 120(%rsp)
leaq 112(%rsp), %rsi
movq 24(%rsp), %rdi
.LEHB3:
call _Z15compare_vectorsPiSt6vectorIiSaIiEE
.LEHE3:
jmp .L107
.L77:
movl 0(%r13), %eax
movl %eax, (%r14)
jmp .L78
.L107:
movl %eax, %r12d
testq %r14, %r14
je .L79
movq 8(%rsp), %rsi
movq %r14, %rdi
call _ZdlPvm@PLT
.L79:
testb %r12b, %r12b
je .L108
movl %r15d, %ecx
leaq .LC8(%rip), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
.LEHB4:
call __printf_chk@PLT
jmp .L109
.L108:
leaq .LC6(%rip), %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $200, %esi
movq 24(%rsp), %rdi
call _Z12print_vectorPii
jmp .L110
.L109:
movq 24(%rsp), %rdi
call cudaFree@PLT
.LEHE4:
testq %r13, %r13
je .L82
movq 96(%rsp), %rsi
subq %r13, %rsi
movq %r13, %rdi
call _ZdlPvm@PLT
.L82:
movq 64(%rsp), %rsi
subq %rbx, %rsi
movq %rbx, %rdi
call _ZdlPvm@PLT
addl $1, %r15d
cmpl $100, %r15d
je .L84
.L83:
leaq 48(%rsp), %rdi
movl $200, %esi
.LEHB5:
call _Z13create_vectori
.LEHE5:
leaq 80(%rsp), %rdi
movl $200, %esi
.LEHB6:
call _Z13create_vectori
.LEHE6:
jmp .L111
.L110:
leaq 80(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
leaq 48(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
.L84:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L112
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L92:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 112(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
.L86:
leaq 80(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
.L87:
leaq 48(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq 136(%rsp), %rax
subq %fs:40, %rax
je .L88
call __stack_chk_fail@PLT
.L90:
endbr64
movq %rax, %rbx
jmp .L87
.L88:
movq %rbx, %rdi
.LEHB7:
call _Unwind_Resume@PLT
.LEHE7:
.L74:
movq $0, 112(%rsp)
movq $0, 128(%rsp)
movq $0, (%rsp)
movq $0, 8(%rsp)
movl $0, %r14d
jmp .L78
.L112:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5088:
.section .gcc_except_table
.LLSDA5088:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE5088-.LLSDACSB5088
.LLSDACSB5088:
.uleb128 .LEHB2-.LFB5088
.uleb128 .LEHE2-.LEHB2
.uleb128 .L91-.LFB5088
.uleb128 0
.uleb128 .LEHB3-.LFB5088
.uleb128 .LEHE3-.LEHB3
.uleb128 .L92-.LFB5088
.uleb128 0
.uleb128 .LEHB4-.LFB5088
.uleb128 .LEHE4-.LEHB4
.uleb128 .L91-.LFB5088
.uleb128 0
.uleb128 .LEHB5-.LFB5088
.uleb128 .LEHE5-.LEHB5
.uleb128 0
.uleb128 0
.uleb128 .LEHB6-.LFB5088
.uleb128 .LEHE6-.LEHB6
.uleb128 .L90-.LFB5088
.uleb128 0
.uleb128 .LEHB7-.LFB5088
.uleb128 .LEHE7-.LEHB7
.uleb128 0
.uleb128 0
.LLSDACSE5088:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gpu_sort.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z12print_vectorPii # -- Begin function _Z12print_vectorPii
.p2align 4, 0x90
.type _Z12print_vectorPii,@function
_Z12print_vectorPii: # @_Z12print_vectorPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
je .LBB0_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movslq %esi, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB0_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB0_4: # %._crit_edge
movl $10, %edi
jmp putchar@PLT # TAILCALL
.Lfunc_end0:
.size _Z12print_vectorPii, .Lfunc_end0-_Z12print_vectorPii
.cfi_endproc
# -- End function
.globl _Z15compare_vectorsPiSt6vectorIiSaIiEE # -- Begin function _Z15compare_vectorsPiSt6vectorIiSaIiEE
.p2align 4, 0x90
.type _Z15compare_vectorsPiSt6vectorIiSaIiEE,@function
_Z15compare_vectorsPiSt6vectorIiSaIiEE: # @_Z15compare_vectorsPiSt6vectorIiSaIiEE
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq (%rsi), %r8
movq 8(%rsi), %rax
subq %r8, %rax
sete %bl
je .LBB1_8
# %bb.1: # %.lr.ph.preheader
sarq $2, %rax
cmpq $1, %rax
movq %rax, %r9
adcq $0, %r9
movl (%rdi), %edx
movl (%r8), %ecx
xorl %esi, %esi
cmpl %ecx, %edx
jne .LBB1_6
# %bb.2: # %.lr.ph34.preheader
decq %r9
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_3: # %.lr.ph34
# =>This Inner Loop Header: Depth=1
cmpq %rsi, %r9
je .LBB1_7
# %bb.4: # %.lr.ph
# in Loop: Header=BB1_3 Depth=1
movl 4(%rdi,%rsi,4), %edx
movl 4(%r8,%rsi,4), %ecx
incq %rsi
cmpl %ecx, %edx
je .LBB1_3
# %bb.5: # %.lr.ph._crit_edge
cmpq %rsi, %rax
setbe %bl
.LBB1_6:
movl $.L.str.2, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
jmp .LBB1_8
.LBB1_7: # %.loopexit.loopexit
incq %rsi
cmpq %rsi, %rax
setbe %bl
.LBB1_8: # %.loopexit
movl %ebx, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z15compare_vectorsPiSt6vectorIiSaIiEE, .Lfunc_end1-_Z15compare_vectorsPiSt6vectorIiSaIiEE
.cfi_endproc
# -- End function
.globl _Z13create_vectori # -- Begin function _Z13create_vectori
.p2align 4, 0x90
.type _Z13create_vectori,@function
_Z13create_vectori: # @_Z13create_vectori
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
xorps %xmm0, %xmm0
movups %xmm0, (%rdi)
movq $0, 16(%rdi)
xorl %r13d, %r13d
testl %esi, %esi
jle .LBB2_1
# %bb.3: # %.lr.ph
movabsq $2305843009213693951, %rbp # imm = 0x1FFFFFFFFFFFFFFF
xorl %eax, %eax
movl %esi, 20(%rsp) # 4-byte Spill
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_5: # in Loop: Header=BB2_4 Depth=1
movl %r13d, (%r15)
addq $4, %r15
movq %r15, 8(%rbx)
movq %rax, %r12
.LBB2_22: # %_ZNSt6vectorIiSaIiEE9push_backERKi.exit
# in Loop: Header=BB2_4 Depth=1
incl %r13d
cmpl %r13d, %esi
je .LBB2_2
.LBB2_4: # =>This Inner Loop Header: Depth=1
movq 8(%rbx), %r15
cmpq 16(%rbx), %r15
jne .LBB2_5
# %bb.6: # in Loop: Header=BB2_4 Depth=1
movq %rax, 8(%rsp) # 8-byte Spill
subq %rax, %r15
movabsq $9223372036854775804, %rax # imm = 0x7FFFFFFFFFFFFFFC
cmpq %rax, %r15
je .LBB2_7
# %bb.9: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i
# in Loop: Header=BB2_4 Depth=1
movq %r15, %r14
sarq $2, %r14
cmpq $1, %r14
movq %r14, %rax
adcq $0, %rax
leaq (%rax,%r14), %rcx
cmpq %rbp, %rcx
jae .LBB2_10
# %bb.11: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i
# in Loop: Header=BB2_4 Depth=1
addq %r14, %rax
jae .LBB2_12
.LBB2_13: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i
# in Loop: Header=BB2_4 Depth=1
testq %rbp, %rbp
je .LBB2_14
.LBB2_15: # in Loop: Header=BB2_4 Depth=1
leaq (,%rbp,4), %rdi
.Ltmp0:
callq _Znwm
.Ltmp1:
# %bb.16: # in Loop: Header=BB2_4 Depth=1
movq %rax, %r12
jmp .LBB2_17
.LBB2_10: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i
# in Loop: Header=BB2_4 Depth=1
movq %rbp, %rcx
addq %r14, %rax
jb .LBB2_13
.LBB2_12: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i
# in Loop: Header=BB2_4 Depth=1
movq %rcx, %rbp
testq %rbp, %rbp
jne .LBB2_15
.LBB2_14: # in Loop: Header=BB2_4 Depth=1
xorl %r12d, %r12d
.LBB2_17: # %_ZNSt12_Vector_baseIiSaIiEE11_M_allocateEm.exit.i.i
# in Loop: Header=BB2_4 Depth=1
movl %r13d, (%r12,%r14,4)
testq %r15, %r15
movq 8(%rsp), %r14 # 8-byte Reload
jle .LBB2_19
# %bb.18: # in Loop: Header=BB2_4 Depth=1
movq %r12, %rdi
movq %r14, %rsi
movq %r15, %rdx
callq memmove@PLT
.LBB2_19: # %_ZNSt6vectorIiSaIiEE11_S_relocateEPiS2_S2_RS0_.exit.i.i
# in Loop: Header=BB2_4 Depth=1
testq %r14, %r14
je .LBB2_21
# %bb.20: # in Loop: Header=BB2_4 Depth=1
movq %r14, %rdi
callq _ZdlPv
.LBB2_21: # %_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_.exit.i
# in Loop: Header=BB2_4 Depth=1
leaq (%r12,%r15), %rax
addq $4, %rax
movq %rax, 8(%rbx)
leaq (%r12,%rbp,4), %rax
movq %rax, 16(%rbx)
movq %r12, %rax
movl 20(%rsp), %esi # 4-byte Reload
movabsq $2305843009213693951, %rbp # imm = 0x1FFFFFFFFFFFFFFF
jmp .LBB2_22
.LBB2_1:
xorl %r12d, %r12d
.LBB2_2: # %._crit_edge
movq %r12, (%rbx)
movq %rbx, %rax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_7:
.cfi_def_cfa_offset 80
movq 8(%rsp), %rax # 8-byte Reload
movq %rax, (%rbx)
.Ltmp3:
movl $.L.str.8, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp4:
# %bb.8: # %.noexc
.LBB2_23: # %.loopexit
.Ltmp2:
movq %rax, %r15
movq 8(%rsp), %rax # 8-byte Reload
movq %rax, (%rbx)
jmp .LBB2_25
.LBB2_24: # %.loopexit.split-lp
.Ltmp5:
movq %rax, %r15
.LBB2_25:
cmpq $0, 8(%rsp) # 8-byte Folded Reload
je .LBB2_27
# %bb.26:
movq 8(%rsp), %rdi # 8-byte Reload
callq _ZdlPv
.LBB2_27: # %_ZNSt6vectorIiSaIiEED2Ev.exit
movq %r15, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size _Z13create_vectori, .Lfunc_end2-_Z13create_vectori
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp3-.Ltmp1 # Call between .Ltmp1 and .Ltmp3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Lfunc_end2-.Ltmp4 # Call between .Ltmp4 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.globl _Z26__device_stub__bubble_sortPii # -- Begin function _Z26__device_stub__bubble_sortPii
.p2align 4, 0x90
.type _Z26__device_stub__bubble_sortPii,@function
_Z26__device_stub__bubble_sortPii: # @_Z26__device_stub__bubble_sortPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11bubble_sortPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z26__device_stub__bubble_sortPii, .Lfunc_end3-_Z26__device_stub__bubble_sortPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $0, 4(%rsp) # 4-byte Folded Spill
jmp .LBB4_1
.p2align 4, 0x90
.LBB4_66: # %_ZNSt6vectorIiSaIiEED2Ev.exit56
# in Loop: Header=BB4_1 Depth=1
movl 4(%rsp), %eax # 4-byte Reload
incl %eax
movl %eax, 4(%rsp) # 4-byte Spill
cmpl $100, %eax
setne %al
testb %al, %r13b
je .LBB4_67
.LBB4_1: # =>This Loop Header: Depth=1
# Child Loop BB4_5 Depth 2
# Child Loop BB4_11 Depth 2
# Child Loop BB4_16 Depth 2
# Child Loop BB4_18 Depth 2
# Child Loop BB4_53 Depth 2
# Child Loop BB4_59 Depth 2
.cfi_escape 0x2e, 0x00
leaq 128(%rsp), %rdi
movl $200, %esi
callq _Z13create_vectori
.Ltmp6:
.cfi_escape 0x2e, 0x00
leaq 104(%rsp), %rdi
movl $200, %esi
callq _Z13create_vectori
.Ltmp7:
# %bb.2: # in Loop: Header=BB4_1 Depth=1
movq 128(%rsp), %rbx
movq 136(%rsp), %r14
cmpq %r14, %rbx
je .LBB4_14
# %bb.3: # %.preheader.i
# in Loop: Header=BB4_1 Depth=1
leaq 4(%rbx), %r15
cmpq %r14, %r15
je .LBB4_8
# %bb.4: # %.lr.ph.i
# in Loop: Header=BB4_1 Depth=1
movl $4, %r12d
jmp .LBB4_5
.p2align 4, 0x90
.LBB4_7: # in Loop: Header=BB4_5 Depth=2
leaq (%rbx,%r12), %rax
addq $4, %rax
addq $4, %r12
cmpq %r14, %rax
je .LBB4_8
.LBB4_5: # Parent Loop BB4_1 Depth=1
# => This Inner Loop Header: Depth=2
.cfi_escape 0x2e, 0x00
callq rand
cltq
movq %r12, %rcx
sarq $2, %rcx
incq %rcx
cqto
idivq %rcx
leaq (,%rdx,4), %rax
cmpq %rax, %r12
je .LBB4_7
# %bb.6: # in Loop: Header=BB4_5 Depth=2
leaq (%rbx,%r12), %rax
leaq (%rbx,%rdx,4), %rcx
movl (%rax), %edx
movl (%rcx), %esi
movl %esi, (%rax)
movl %edx, (%rcx)
jmp .LBB4_7
.p2align 4, 0x90
.LBB4_8: # %_ZSt14random_shuffleIN9__gnu_cxx17__normal_iteratorIPiSt6vectorIiSaIiEEEEEvT_S7_.exit
# in Loop: Header=BB4_1 Depth=1
cmpq %r14, %rbx
je .LBB4_14
# %bb.9: # %.preheader.i34
# in Loop: Header=BB4_1 Depth=1
cmpq %r14, %r15
je .LBB4_14
# %bb.10: # %.lr.ph.i36
# in Loop: Header=BB4_1 Depth=1
movl $4, %r15d
jmp .LBB4_11
.p2align 4, 0x90
.LBB4_13: # in Loop: Header=BB4_11 Depth=2
leaq (%rbx,%r15), %rax
addq $4, %rax
addq $4, %r15
cmpq %r14, %rax
je .LBB4_14
.LBB4_11: # Parent Loop BB4_1 Depth=1
# => This Inner Loop Header: Depth=2
.cfi_escape 0x2e, 0x00
callq rand
cltq
movq %r15, %rcx
sarq $2, %rcx
incq %rcx
cqto
idivq %rcx
leaq (,%rdx,4), %rax
cmpq %rax, %r15
je .LBB4_13
# %bb.12: # in Loop: Header=BB4_11 Depth=2
leaq (%rbx,%r15), %rax
leaq (%rbx,%rdx,4), %rcx
movl (%rax), %edx
movl (%rcx), %esi
movl %esi, (%rax)
movl %edx, (%rcx)
jmp .LBB4_13
.p2align 4, 0x90
.LBB4_14: # %_ZSt14random_shuffleIN9__gnu_cxx17__normal_iteratorIPiSt6vectorIiSaIiEEEEEvT_S7_.exit39
# in Loop: Header=BB4_1 Depth=1
.Ltmp9:
.cfi_escape 0x2e, 0x00
movl $800, %esi # imm = 0x320
leaq 8(%rsp), %rdi
movl $1, %edx
callq hipMallocManaged
.Ltmp10:
# %bb.15: # %_ZL16hipMallocManagedIiE10hipError_tPPT_mj.exit.preheader
# in Loop: Header=BB4_1 Depth=1
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_16: # %_ZL16hipMallocManagedIiE10hipError_tPPT_mj.exit
# Parent Loop BB4_1 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r14,4), %esi
movq 8(%rsp), %rax
movl %esi, (%rax,%r14,4)
movl (%rbx,%r14,4), %edx
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $200, %r14
jne .LBB4_16
# %bb.17: # in Loop: Header=BB4_1 Depth=1
movq 8(%rsp), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_18: # %.lr.ph.i40
# Parent Loop BB4_1 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r15,4), %esi
.cfi_escape 0x2e, 0x00
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $200, %r15
jne .LBB4_18
# %bb.19: # %_Z12print_vectorPii.exit
# in Loop: Header=BB4_1 Depth=1
.cfi_escape 0x2e, 0x00
movl $10, %edi
callq putchar@PLT
.Ltmp11:
.cfi_escape 0x2e, 0x00
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movabsq $4294968320, %rdx # imm = 0x100000400
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp12:
# %bb.20: # in Loop: Header=BB4_1 Depth=1
testl %eax, %eax
jne .LBB4_23
# %bb.21: # in Loop: Header=BB4_1 Depth=1
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $200, 20(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
.Ltmp13:
.cfi_escape 0x2e, 0x00
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp14:
# %bb.22: # %.noexc
# in Loop: Header=BB4_1 Depth=1
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
.Ltmp15:
.cfi_escape 0x2e, 0x10
movl $_Z11bubble_sortPii, %edi
leaq 80(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp16:
.LBB4_23: # in Loop: Header=BB4_1 Depth=1
.Ltmp17:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.Ltmp18:
# %bb.24: # in Loop: Header=BB4_1 Depth=1
movq 8(%rsp), %rbp
movq 104(%rsp), %r14
movq 112(%rsp), %r13
movq %r13, %r12
subq %r14, %r12
je .LBB4_25
# %bb.34: # in Loop: Header=BB4_1 Depth=1
movq %r12, %rax
sarq $2, %rax
movq %rax, %rcx
shrq $61, %rcx
jne .LBB4_35
# %bb.40: # %_ZNSt16allocator_traitsISaIiEE8allocateERS0_m.exit.i.i.i.i
# in Loop: Header=BB4_1 Depth=1
.Ltmp19:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _Znwm
.Ltmp20:
# %bb.41: # in Loop: Header=BB4_1 Depth=1
movq %rax, %r15
cmpq $5, %r12
jl .LBB4_44
.LBB4_43: # in Loop: Header=BB4_1 Depth=1
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movq %r14, %rsi
movq %r12, %rdx
callq memmove@PLT
.LBB4_46: # %_ZNSt6vectorIiSaIiEEC2ERKS1_.exit
# in Loop: Header=BB4_1 Depth=1
cmpq %r14, %r13
sete %r13b
je .LBB4_55
# %bb.47: # %.lr.ph.preheader.i
# in Loop: Header=BB4_1 Depth=1
sarq $2, %r12
cmpq $1, %r12
movq %r12, %rax
adcq $0, %rax
movl (%rbp), %edx
movl (%r15), %ecx
cmpl %ecx, %edx
jne .LBB4_48
# %bb.52: # %.lr.ph.preheader
# in Loop: Header=BB4_1 Depth=1
movl $1, %esi
.p2align 4, 0x90
.LBB4_53: # %.lr.ph
# Parent Loop BB4_1 Depth=1
# => This Inner Loop Header: Depth=2
cmpq %rsi, %rax
je .LBB4_54
# %bb.49: # %.lr.ph.i45
# in Loop: Header=BB4_53 Depth=2
movl (%rbp,%rsi,4), %edx
movl (%r15,%rsi,4), %ecx
incq %rsi
cmpl %ecx, %edx
je .LBB4_53
# %bb.50: # %.lr.ph.i45._crit_edge.loopexit
# in Loop: Header=BB4_1 Depth=1
decq %rsi
cmpq %rsi, %r12
setbe %r13b
jmp .LBB4_51
.p2align 4, 0x90
.LBB4_25: # in Loop: Header=BB4_1 Depth=1
xorl %r15d, %r15d
cmpq $5, %r12
jge .LBB4_43
.LBB4_44: # in Loop: Header=BB4_1 Depth=1
cmpq $4, %r12
jne .LBB4_46
# %bb.45: # in Loop: Header=BB4_1 Depth=1
movl (%r14), %eax
movl %eax, (%r15)
jmp .LBB4_46
.p2align 4, 0x90
.LBB4_48: # in Loop: Header=BB4_1 Depth=1
xorl %esi, %esi
xorl %r13d, %r13d
.LBB4_51: # %.lr.ph.i45._crit_edge
# in Loop: Header=BB4_1 Depth=1
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
.LBB4_55: # %_Z15compare_vectorsPiSt6vectorIiSaIiEE.exit
# in Loop: Header=BB4_1 Depth=1
testq %r15, %r15
je .LBB4_57
.LBB4_56: # in Loop: Header=BB4_1 Depth=1
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZdlPv
.LBB4_57: # %_ZNSt6vectorIiSaIiEED2Ev.exit
# in Loop: Header=BB4_1 Depth=1
testb %r13b, %r13b
je .LBB4_58
# %bb.61: # in Loop: Header=BB4_1 Depth=1
.cfi_escape 0x2e, 0x00
movl $.L.str.6, %edi
movl $.L.str.7, %esi
movl 4(%rsp), %edx # 4-byte Reload
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
.Ltmp26:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp27:
# %bb.62: # in Loop: Header=BB4_1 Depth=1
testq %r14, %r14
je .LBB4_64
.LBB4_63: # in Loop: Header=BB4_1 Depth=1
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.LBB4_64: # %_ZNSt6vectorIiSaIiEED2Ev.exit54
# in Loop: Header=BB4_1 Depth=1
testq %rbx, %rbx
je .LBB4_66
# %bb.65: # in Loop: Header=BB4_1 Depth=1
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
jmp .LBB4_66
.p2align 4, 0x90
.LBB4_58: # in Loop: Header=BB4_1 Depth=1
.cfi_escape 0x2e, 0x00
movl $.L.str.5, %edi
callq puts@PLT
movq 8(%rsp), %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_59: # %.lr.ph.i46
# Parent Loop BB4_1 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r15,%r12,4), %esi
.cfi_escape 0x2e, 0x00
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $200, %r12
jne .LBB4_59
# %bb.60: # %_Z12print_vectorPii.exit50
# in Loop: Header=BB4_1 Depth=1
.cfi_escape 0x2e, 0x00
movl $10, %edi
callq putchar@PLT
testq %r14, %r14
jne .LBB4_63
jmp .LBB4_64
.LBB4_54: # %_Z15compare_vectorsPiSt6vectorIiSaIiEE.exit.loopexit
# in Loop: Header=BB4_1 Depth=1
cmpq %rsi, %r12
setbe %r13b
testq %r15, %r15
jne .LBB4_56
jmp .LBB4_57
.LBB4_67:
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_35:
.cfi_def_cfa_offset 208
shrq $62, %rax
je .LBB4_38
# %bb.36: # %.noexc.i.i
.Ltmp23:
.cfi_escape 0x2e, 0x00
callq _ZSt28__throw_bad_array_new_lengthv
.Ltmp24:
# %bb.37: # %.noexc42
.LBB4_38: # %.noexc4.i.i
.Ltmp21:
.cfi_escape 0x2e, 0x00
callq _ZSt17__throw_bad_allocv
.Ltmp22:
# %bb.39: # %.noexc43
.LBB4_26:
.Ltmp8:
movq %rax, %rbx
jmp .LBB4_27
.LBB4_30: # %.loopexit
.Ltmp28:
jmp .LBB4_32
.LBB4_31: # %.loopexit.split-lp
.Ltmp25:
.LBB4_32:
movq %rax, %rbx
movq 104(%rsp), %rdi
testq %rdi, %rdi
je .LBB4_27
# %bb.33:
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB4_27: # %_ZNSt6vectorIiSaIiEED2Ev.exit58
movq 128(%rsp), %rdi
testq %rdi, %rdi
je .LBB4_29
# %bb.28:
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB4_29: # %_ZNSt6vectorIiSaIiEED2Ev.exit60
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table4:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Lfunc_begin1-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp6-.Lfunc_begin1 # Call between .Lfunc_begin1 and .Ltmp6
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin1 # >> Call Site 2 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin1 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin1 # >> Call Site 3 <<
.uleb128 .Ltmp20-.Ltmp9 # Call between .Ltmp9 and .Ltmp20
.uleb128 .Ltmp28-.Lfunc_begin1 # jumps to .Ltmp28
.byte 0 # On action: cleanup
.uleb128 .Ltmp20-.Lfunc_begin1 # >> Call Site 4 <<
.uleb128 .Ltmp26-.Ltmp20 # Call between .Ltmp20 and .Ltmp26
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp26-.Lfunc_begin1 # >> Call Site 5 <<
.uleb128 .Ltmp27-.Ltmp26 # Call between .Ltmp26 and .Ltmp27
.uleb128 .Ltmp28-.Lfunc_begin1 # jumps to .Ltmp28
.byte 0 # On action: cleanup
.uleb128 .Ltmp23-.Lfunc_begin1 # >> Call Site 6 <<
.uleb128 .Ltmp22-.Ltmp23 # Call between .Ltmp23 and .Ltmp22
.uleb128 .Ltmp25-.Lfunc_begin1 # jumps to .Ltmp25
.byte 0 # On action: cleanup
.uleb128 .Ltmp22-.Lfunc_begin1 # >> Call Site 7 <<
.uleb128 .Lfunc_end4-.Ltmp22 # Call between .Ltmp22 and .Lfunc_end4
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end1:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11bubble_sortPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "wrong at %d %d vs %d\n"
.size .L.str.2, 22
.type _Z11bubble_sortPii,@object # @_Z11bubble_sortPii
.section .rodata,"a",@progbits
.globl _Z11bubble_sortPii
.p2align 3, 0x0
_Z11bubble_sortPii:
.quad _Z26__device_stub__bubble_sortPii
.size _Z11bubble_sortPii, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "%d %d\n"
.size .L.str.3, 7
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Wrong algorithm"
.size .L.str.5, 16
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%s %d\n"
.size .L.str.6, 7
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "True algorithm"
.size .L.str.7, 15
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "vector::_M_realloc_insert"
.size .L.str.8, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11bubble_sortPii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Z26__device_stub__bubble_sortPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z11bubble_sortPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
extern "C" {
}
#define TB 256
#define EPS 0.1
#undef MIN
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#undef MAX
#define MAX(a, b) ((a) > (b) ? (a) : (b))
__global__ void hist_remap2_kernel( float *I, int nI, float *mI, float *histJ, float *cumJ, float *_minJ, float *_maxJ, int nbins, float *_sortI, int *_idxI, float *R, int c, int h, int w )
{
int _id = blockIdx.x * blockDim.x + threadIdx.x;
int size = h * w;
if (_id < c * size) {
// _id = dc * size + id
int id = _id % size, dc = _id / size;
float minJ = _minJ[dc];
float maxJ = _maxJ[dc];
float stepJ = (maxJ - minJ) / nbins;
int idxI = _idxI[_id] - 1;
if (mI[idxI] < EPS)
return ;
int offset = h * w - nI;
int cdf = id - offset;
int s = 0;
int e = nbins - 1;
int m = (s + e) / 2;
int binIdx = -1;
while (s <= e) {
// special handling for range boundary
float cdf_e = m == nbins - 1 ?
cumJ[dc * nbins + m] + 0.5f :
cumJ[dc * nbins + m];
float cdf_s = m == 0 ?
-0.5f :
cumJ[dc * nbins + m - 1];
if (cdf >= cdf_e) {
s = m + 1;
m = (s + e) / 2;
} else if (cdf < cdf_s) {
e = m - 1;
m = (s + e) / 2;
} else {
binIdx = m; break;
}
}
float hist = histJ[dc * nbins + binIdx];
float cdf_e = cumJ[dc * nbins + binIdx];
float cdf_s = cdf_e - hist;
float ratio = MIN(MAX((cdf - cdf_s) / (hist + 1e-8), 0.0f), 1.0f);
float activation = minJ + (static_cast<float>(binIdx) + ratio) * stepJ;
R[dc * size + idxI] = activation;
}
return ;
} | .file "tmpxft_00053203_00000000-6_hist_remap2_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z59__device_stub__Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iiiPfiS_S_S_S_S_iS_PiS_iii
.type _Z59__device_stub__Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iiiPfiS_S_S_S_S_iS_PiS_iii, @function
_Z59__device_stub__Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iiiPfiS_S_S_S_S_iS_PiS_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $280, %rsp
.cfi_def_cfa_offset 288
movq %rdi, 72(%rsp)
movl %esi, 68(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
movq %r8, 40(%rsp)
movq %r9, 32(%rsp)
movq 288(%rsp), %rax
movq %rax, 24(%rsp)
movq 304(%rsp), %rax
movq %rax, 16(%rsp)
movq 312(%rsp), %rax
movq %rax, 8(%rsp)
movq 320(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 68(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 24(%rsp), %rax
movq %rax, 192(%rsp)
leaq 296(%rsp), %rax
movq %rax, 200(%rsp)
leaq 16(%rsp), %rax
movq %rax, 208(%rsp)
leaq 8(%rsp), %rax
movq %rax, 216(%rsp)
movq %rsp, %rax
movq %rax, 224(%rsp)
leaq 328(%rsp), %rax
movq %rax, 232(%rsp)
leaq 336(%rsp), %rax
movq %rax, 240(%rsp)
leaq 344(%rsp), %rax
movq %rax, 248(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 296
pushq 88(%rsp)
.cfi_def_cfa_offset 304
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 288
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z59__device_stub__Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iiiPfiS_S_S_S_S_iS_PiS_iii, .-_Z59__device_stub__Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iiiPfiS_S_S_S_S_iS_PiS_iii
.globl _Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii
.type _Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii, @function
_Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 72(%rsp)
.cfi_def_cfa_offset 48
pushq 72(%rsp)
.cfi_def_cfa_offset 56
pushq 72(%rsp)
.cfi_def_cfa_offset 64
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 72
pushq 72(%rsp)
.cfi_def_cfa_offset 80
call _Z59__device_stub__Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iiiPfiS_S_S_S_S_iS_PiS_iii
addq $72, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii, .-_Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
extern "C" {
}
#define TB 256
#define EPS 0.1
#undef MIN
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#undef MAX
#define MAX(a, b) ((a) > (b) ? (a) : (b))
__global__ void hist_remap2_kernel( float *I, int nI, float *mI, float *histJ, float *cumJ, float *_minJ, float *_maxJ, int nbins, float *_sortI, int *_idxI, float *R, int c, int h, int w )
{
int _id = blockIdx.x * blockDim.x + threadIdx.x;
int size = h * w;
if (_id < c * size) {
// _id = dc * size + id
int id = _id % size, dc = _id / size;
float minJ = _minJ[dc];
float maxJ = _maxJ[dc];
float stepJ = (maxJ - minJ) / nbins;
int idxI = _idxI[_id] - 1;
if (mI[idxI] < EPS)
return ;
int offset = h * w - nI;
int cdf = id - offset;
int s = 0;
int e = nbins - 1;
int m = (s + e) / 2;
int binIdx = -1;
while (s <= e) {
// special handling for range boundary
float cdf_e = m == nbins - 1 ?
cumJ[dc * nbins + m] + 0.5f :
cumJ[dc * nbins + m];
float cdf_s = m == 0 ?
-0.5f :
cumJ[dc * nbins + m - 1];
if (cdf >= cdf_e) {
s = m + 1;
m = (s + e) / 2;
} else if (cdf < cdf_s) {
e = m - 1;
m = (s + e) / 2;
} else {
binIdx = m; break;
}
}
float hist = histJ[dc * nbins + binIdx];
float cdf_e = cumJ[dc * nbins + binIdx];
float cdf_s = cdf_e - hist;
float ratio = MIN(MAX((cdf - cdf_s) / (hist + 1e-8), 0.0f), 1.0f);
float activation = minJ + (static_cast<float>(binIdx) + ratio) * stepJ;
R[dc * size + idxI] = activation;
}
return ;
} | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C" {
}
#define TB 256
#define EPS 0.1
#undef MIN
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#undef MAX
#define MAX(a, b) ((a) > (b) ? (a) : (b))
__global__ void hist_remap2_kernel( float *I, int nI, float *mI, float *histJ, float *cumJ, float *_minJ, float *_maxJ, int nbins, float *_sortI, int *_idxI, float *R, int c, int h, int w )
{
int _id = blockIdx.x * blockDim.x + threadIdx.x;
int size = h * w;
if (_id < c * size) {
// _id = dc * size + id
int id = _id % size, dc = _id / size;
float minJ = _minJ[dc];
float maxJ = _maxJ[dc];
float stepJ = (maxJ - minJ) / nbins;
int idxI = _idxI[_id] - 1;
if (mI[idxI] < EPS)
return ;
int offset = h * w - nI;
int cdf = id - offset;
int s = 0;
int e = nbins - 1;
int m = (s + e) / 2;
int binIdx = -1;
while (s <= e) {
// special handling for range boundary
float cdf_e = m == nbins - 1 ?
cumJ[dc * nbins + m] + 0.5f :
cumJ[dc * nbins + m];
float cdf_s = m == 0 ?
-0.5f :
cumJ[dc * nbins + m - 1];
if (cdf >= cdf_e) {
s = m + 1;
m = (s + e) / 2;
} else if (cdf < cdf_s) {
e = m - 1;
m = (s + e) / 2;
} else {
binIdx = m; break;
}
}
float hist = histJ[dc * nbins + binIdx];
float cdf_e = cumJ[dc * nbins + binIdx];
float cdf_s = cdf_e - hist;
float ratio = MIN(MAX((cdf - cdf_s) / (hist + 1e-8), 0.0f), 1.0f);
float activation = minJ + (static_cast<float>(binIdx) + ratio) * stepJ;
R[dc * size + idxI] = activation;
}
return ;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C" {
}
#define TB 256
#define EPS 0.1
#undef MIN
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#undef MAX
#define MAX(a, b) ((a) > (b) ? (a) : (b))
__global__ void hist_remap2_kernel( float *I, int nI, float *mI, float *histJ, float *cumJ, float *_minJ, float *_maxJ, int nbins, float *_sortI, int *_idxI, float *R, int c, int h, int w )
{
int _id = blockIdx.x * blockDim.x + threadIdx.x;
int size = h * w;
if (_id < c * size) {
// _id = dc * size + id
int id = _id % size, dc = _id / size;
float minJ = _minJ[dc];
float maxJ = _maxJ[dc];
float stepJ = (maxJ - minJ) / nbins;
int idxI = _idxI[_id] - 1;
if (mI[idxI] < EPS)
return ;
int offset = h * w - nI;
int cdf = id - offset;
int s = 0;
int e = nbins - 1;
int m = (s + e) / 2;
int binIdx = -1;
while (s <= e) {
// special handling for range boundary
float cdf_e = m == nbins - 1 ?
cumJ[dc * nbins + m] + 0.5f :
cumJ[dc * nbins + m];
float cdf_s = m == 0 ?
-0.5f :
cumJ[dc * nbins + m - 1];
if (cdf >= cdf_e) {
s = m + 1;
m = (s + e) / 2;
} else if (cdf < cdf_s) {
e = m - 1;
m = (s + e) / 2;
} else {
binIdx = m; break;
}
}
float hist = histJ[dc * nbins + binIdx];
float cdf_e = cumJ[dc * nbins + binIdx];
float cdf_s = cdf_e - hist;
float ratio = MIN(MAX((cdf - cdf_s) / (hist + 1e-8), 0.0f), 1.0f);
float activation = minJ + (static_cast<float>(binIdx) + ratio) * stepJ;
R[dc * size + idxI] = activation;
}
return ;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii
.globl _Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii
.p2align 8
.type _Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii,@function
_Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x74
s_load_b64 s[4:5], s[0:1], 0x58
s_load_b32 s3, s[0:1], 0x60
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
s_mul_i32 s2, s3, s5
s_mul_i32 s3, s2, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v3
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_21
s_load_b64 s[4:5], s[0:1], 0x48
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_load_b64 s[4:5], s[0:1], 0x10
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, -1, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
s_mov_b32 s5, 0x3fb99999
s_mov_b32 s4, 0x9999999a
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[1:2], v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ngt_f64_e32 vcc_lo, s[4:5], v[1:2]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_21
s_ashr_i32 s3, s2, 31
v_ashrrev_i32_e32 v4, 31, v3
s_add_i32 s4, s2, s3
s_load_b64 s[8:9], s[0:1], 0x30
s_xor_b32 s4, s4, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v5, v3, v4
v_cvt_f32_u32_e32 v1, s4
s_sub_i32 s5, 0, s4
v_xor_b32_e32 v5, v5, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
v_xor_b32_e32 v4, s3, v4
s_load_b32 s3, s[0:1], 0x38
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s5, v1
v_mul_hi_u32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v6, v1, v2
v_mad_u64_u32 v[1:2], null, v5, v6, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v2, s4
v_sub_nc_u32_e32 v1, v5, v1
v_add_nc_u32_e32 v5, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v6, s4, v1
v_cmp_le_u32_e32 vcc_lo, s4, v1
v_dual_cndmask_b32 v2, v2, v5 :: v_dual_cndmask_b32 v1, v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v5, 1, v2
v_cmp_le_u32_e32 vcc_lo, s4, v1
s_load_b128 s[4:7], s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, v2, v5, vcc_lo
v_xor_b32_e32 v1, v1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v1, v1, v4
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_mul_lo_u32 v2, v1, s2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s6, v4
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v5, vcc_lo
s_load_b32 s7, s[0:1], 0x8
v_add_co_u32 v8, vcc_lo, s8, v4
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v5, vcc_lo
global_load_b32 v4, v[6:7], off
global_load_b32 v5, v[8:9], off
v_sub_nc_u32_e32 v2, v3, v2
s_add_i32 s6, s3, -1
v_mul_lo_u32 v6, v1, s3
s_lshr_b32 s8, s6, 31
v_dual_mov_b32 v7, s6 :: v_dual_mov_b32 v8, 0
s_waitcnt lgkmcnt(0)
s_sub_i32 s7, s7, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v2, s7, v2
s_add_i32 s7, s6, s8
s_ashr_i32 s7, s7, 1
s_add_u32 s8, s4, -4
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_i32_e32 v3, v2
v_dual_mov_b32 v2, -1 :: v_dual_mov_b32 v9, s7
s_mov_b32 s7, 0
s_addc_u32 s9, s5, -1
s_branch .LBB0_5
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s13
s_xor_b32 s12, s14, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_dual_mov_b32 v2, v9 :: v_dual_mov_b32 v9, v11
s_and_not1_b32 s10, s10, exec_lo
s_and_b32 s12, s12, exec_lo
s_or_b32 s10, s10, s12
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s11, exec_lo, s10
s_or_b32 s7, s11, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execz .LBB0_20
.LBB0_5:
s_or_b32 s10, s10, exec_lo
s_mov_b32 s11, exec_lo
v_cmpx_le_i32_e64 v8, v7
s_cbranch_execz .LBB0_4
s_mov_b32 s12, exec_lo
v_cmpx_ne_u32_e64 s6, v9
s_xor_b32 s12, exec_lo, s12
s_cbranch_execz .LBB0_8
v_add_nc_u32_e32 v10, v9, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[10:11], 2, v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, s4, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v11, vcc_lo
global_load_b32 v10, v[10:11], off
.LBB0_8:
s_and_not1_saveexec_b32 s12, s12
s_cbranch_execz .LBB0_10
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v10, v9, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[10:11], 2, v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, s4, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v11, vcc_lo
global_load_b32 v10, v[10:11], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v10, 0.5, v10
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s12
v_mov_b32_e32 v11, -0.5
s_mov_b32 s12, exec_lo
v_cmpx_ne_u32_e32 0, v9
s_cbranch_execz .LBB0_12
v_add_nc_u32_e32 v11, v9, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v12, 31, v11
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v11, vcc_lo, s8, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s9, v12, vcc_lo
global_load_b32 v11, v[11:12], off
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s12
s_waitcnt vmcnt(0)
v_cmp_le_f32_e32 vcc_lo, v10, v3
s_mov_b32 s12, 0
s_and_saveexec_b32 s13, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s13, exec_lo, s13
v_add_nc_u32_e32 v8, 1, v9
s_mov_b32 s12, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v10, v8, v7
s_or_saveexec_b32 s13, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 exec_lo, exec_lo, s13
s_cbranch_execz .LBB0_18
s_mov_b32 s14, s12
s_mov_b32 s15, exec_lo
v_cmpx_gt_f32_e32 v11, v3
v_add_nc_u32_e32 v7, -1, v9
s_or_b32 s14, s12, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v10, v8, v7
s_or_b32 exec_lo, exec_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 s12, s12, exec_lo
s_and_b32 s15, s14, exec_lo
s_mov_b32 s14, 0
s_or_b32 s12, s12, s15
.LBB0_18:
s_or_b32 exec_lo, exec_lo, s13
v_mov_b32_e32 v11, v9
s_and_saveexec_b32 s13, s12
s_cbranch_execz .LBB0_3
v_lshrrev_b32_e32 v9, 31, v10
s_or_b32 s14, s14, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v9, v10, v9
v_ashrrev_i32_e32 v11, 1, v9
v_mov_b32_e32 v9, v2
s_branch .LBB0_3
.LBB0_20:
s_or_b32 exec_lo, exec_lo, s7
s_clause 0x1
s_load_b64 s[6:7], s[0:1], 0x18
s_load_b64 s[8:9], s[0:1], 0x50
v_mad_u64_u32 v[6:7], null, v1, s3, v[2:3]
s_mov_b32 s1, 0x3e45798e
s_mov_b32 s0, 0xe2308c3a
v_cvt_f32_i32_e32 v18, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v7, vcc_lo
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_b32 v8, v[8:9], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e32 v[6:7], v8
s_waitcnt vmcnt(0)
v_sub_f32_e32 v8, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v8, v3
v_cvt_f64_f32_e32 v[8:9], v3
v_sub_f32_e32 v3, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v5, null, v18, v18, v3
v_rcp_f32_e32 v19, v5
v_add_f64 v[6:7], v[6:7], s[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f64 v[10:11], null, v[6:7], v[6:7], v[8:9]
v_div_scale_f64 v[16:17], s0, v[8:9], v[6:7], v[8:9]
v_rcp_f64_e32 v[12:13], v[10:11]
s_waitcnt_depctr 0xfff
v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
v_mul_f64 v[14:15], v[16:17], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fma_f64 v[10:11], -v[10:11], v[14:15], v[16:17]
v_fma_f32 v16, -v5, v19, 1.0
v_div_scale_f32 v17, vcc_lo, v3, v18, v3
v_fmac_f32_e32 v19, v16, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v16, v17, v19
v_fma_f32 v20, -v5, v16, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v16, v20, v19
v_fma_f32 v5, -v5, v16, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_div_fmas_f32 v16, v5, v19, v16
s_mov_b32 vcc_lo, s0
v_div_fmas_f64 v[10:11], v[10:11], v[12:13], v[14:15]
v_div_fixup_f64 v[5:6], v[10:11], v[6:7], v[8:9]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_nlt_f64_e32 vcc_lo, 0, v[5:6]
v_cmp_gt_f64_e64 s0, 1.0, v[5:6]
v_cmp_ngt_f64_e64 s1, 1.0, v[5:6]
v_cvt_f32_f64_e32 v7, v[5:6]
v_mad_u64_u32 v[5:6], null, v1, s2, v[0:1]
v_cvt_f32_i32_e32 v1, v2
v_div_fixup_f32 v2, v16, v18, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
s_or_b32 s0, vcc_lo, s0
s_or_b32 vcc_lo, vcc_lo, s1
v_cndmask_b32_e64 v0, 1.0, 0, s0
v_cndmask_b32_e32 v0, v7, v0, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v3, v0, v1
v_lshlrev_b64 v[0:1], 2, v[5:6]
v_fmac_f32_e32 v4, v2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_21:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 360
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii, .Lfunc_end0-_Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 80
.size: 8
.value_kind: global_buffer
- .offset: 88
.size: 4
.value_kind: by_value
- .offset: 92
.size: 4
.value_kind: by_value
- .offset: 96
.size: 4
.value_kind: by_value
- .offset: 104
.size: 4
.value_kind: hidden_block_count_x
- .offset: 108
.size: 4
.value_kind: hidden_block_count_y
- .offset: 112
.size: 4
.value_kind: hidden_block_count_z
- .offset: 116
.size: 2
.value_kind: hidden_group_size_x
- .offset: 118
.size: 2
.value_kind: hidden_group_size_y
- .offset: 120
.size: 2
.value_kind: hidden_group_size_z
- .offset: 122
.size: 2
.value_kind: hidden_remainder_x
- .offset: 124
.size: 2
.value_kind: hidden_remainder_y
- .offset: 126
.size: 2
.value_kind: hidden_remainder_z
- .offset: 144
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 152
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 160
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 168
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 360
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C" {
}
#define TB 256
#define EPS 0.1
#undef MIN
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#undef MAX
#define MAX(a, b) ((a) > (b) ? (a) : (b))
__global__ void hist_remap2_kernel( float *I, int nI, float *mI, float *histJ, float *cumJ, float *_minJ, float *_maxJ, int nbins, float *_sortI, int *_idxI, float *R, int c, int h, int w )
{
int _id = blockIdx.x * blockDim.x + threadIdx.x;
int size = h * w;
if (_id < c * size) {
// _id = dc * size + id
int id = _id % size, dc = _id / size;
float minJ = _minJ[dc];
float maxJ = _maxJ[dc];
float stepJ = (maxJ - minJ) / nbins;
int idxI = _idxI[_id] - 1;
if (mI[idxI] < EPS)
return ;
int offset = h * w - nI;
int cdf = id - offset;
int s = 0;
int e = nbins - 1;
int m = (s + e) / 2;
int binIdx = -1;
while (s <= e) {
// special handling for range boundary
float cdf_e = m == nbins - 1 ?
cumJ[dc * nbins + m] + 0.5f :
cumJ[dc * nbins + m];
float cdf_s = m == 0 ?
-0.5f :
cumJ[dc * nbins + m - 1];
if (cdf >= cdf_e) {
s = m + 1;
m = (s + e) / 2;
} else if (cdf < cdf_s) {
e = m - 1;
m = (s + e) / 2;
} else {
binIdx = m; break;
}
}
float hist = histJ[dc * nbins + binIdx];
float cdf_e = cumJ[dc * nbins + binIdx];
float cdf_s = cdf_e - hist;
float ratio = MIN(MAX((cdf - cdf_s) / (hist + 1e-8), 0.0f), 1.0f);
float activation = minJ + (static_cast<float>(binIdx) + ratio) * stepJ;
R[dc * size + idxI] = activation;
}
return ;
} | .text
.file "hist_remap2_kernel.hip"
.globl _Z33__device_stub__hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii # -- Begin function _Z33__device_stub__hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii
.p2align 4, 0x90
.type _Z33__device_stub__hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii,@function
_Z33__device_stub__hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii: # @_Z33__device_stub__hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 88(%rsp)
movl %esi, 4(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 224(%rsp), %rax
movq %rax, 144(%rsp)
leaq 232(%rsp), %rax
movq %rax, 152(%rsp)
leaq 240(%rsp), %rax
movq %rax, 160(%rsp)
leaq 248(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
leaq 264(%rsp), %rax
movq %rax, 184(%rsp)
leaq 272(%rsp), %rax
movq %rax, 192(%rsp)
leaq 280(%rsp), %rax
movq %rax, 200(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end0:
.size _Z33__device_stub__hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii, .Lfunc_end0-_Z33__device_stub__hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii,@object # @_Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii
.section .rodata,"a",@progbits
.globl _Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii
.p2align 3, 0x0
_Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii:
.quad _Z33__device_stub__hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii
.size _Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii"
.size .L__unnamed_1, 46
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00053203_00000000-6_hist_remap2_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z59__device_stub__Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iiiPfiS_S_S_S_S_iS_PiS_iii
.type _Z59__device_stub__Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iiiPfiS_S_S_S_S_iS_PiS_iii, @function
_Z59__device_stub__Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iiiPfiS_S_S_S_S_iS_PiS_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $280, %rsp
.cfi_def_cfa_offset 288
movq %rdi, 72(%rsp)
movl %esi, 68(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
movq %r8, 40(%rsp)
movq %r9, 32(%rsp)
movq 288(%rsp), %rax
movq %rax, 24(%rsp)
movq 304(%rsp), %rax
movq %rax, 16(%rsp)
movq 312(%rsp), %rax
movq %rax, 8(%rsp)
movq 320(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 68(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 24(%rsp), %rax
movq %rax, 192(%rsp)
leaq 296(%rsp), %rax
movq %rax, 200(%rsp)
leaq 16(%rsp), %rax
movq %rax, 208(%rsp)
leaq 8(%rsp), %rax
movq %rax, 216(%rsp)
movq %rsp, %rax
movq %rax, 224(%rsp)
leaq 328(%rsp), %rax
movq %rax, 232(%rsp)
leaq 336(%rsp), %rax
movq %rax, 240(%rsp)
leaq 344(%rsp), %rax
movq %rax, 248(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 296
pushq 88(%rsp)
.cfi_def_cfa_offset 304
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 288
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z59__device_stub__Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iiiPfiS_S_S_S_S_iS_PiS_iii, .-_Z59__device_stub__Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iiiPfiS_S_S_S_S_iS_PiS_iii
.globl _Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii
.type _Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii, @function
_Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 72(%rsp)
.cfi_def_cfa_offset 48
pushq 72(%rsp)
.cfi_def_cfa_offset 56
pushq 72(%rsp)
.cfi_def_cfa_offset 64
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 72
pushq 72(%rsp)
.cfi_def_cfa_offset 80
call _Z59__device_stub__Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iiiPfiS_S_S_S_S_iS_PiS_iii
addq $72, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii, .-_Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hist_remap2_kernel.hip"
.globl _Z33__device_stub__hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii # -- Begin function _Z33__device_stub__hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii
.p2align 4, 0x90
.type _Z33__device_stub__hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii,@function
_Z33__device_stub__hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii: # @_Z33__device_stub__hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 88(%rsp)
movl %esi, 4(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 224(%rsp), %rax
movq %rax, 144(%rsp)
leaq 232(%rsp), %rax
movq %rax, 152(%rsp)
leaq 240(%rsp), %rax
movq %rax, 160(%rsp)
leaq 248(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
leaq 264(%rsp), %rax
movq %rax, 184(%rsp)
leaq 272(%rsp), %rax
movq %rax, 192(%rsp)
leaq 280(%rsp), %rax
movq %rax, 200(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end0:
.size _Z33__device_stub__hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii, .Lfunc_end0-_Z33__device_stub__hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii,@object # @_Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii
.section .rodata,"a",@progbits
.globl _Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii
.p2align 3, 0x0
_Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii:
.quad _Z33__device_stub__hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii
.size _Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii"
.size .L__unnamed_1, 46
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18hist_remap2_kernelPfiS_S_S_S_S_iS_PiS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
__global__ void nabeatsuKernel(bool* result, int result_len)
{
int i = (blockIdx.x * blockDim.x) + threadIdx.x;
if (i < result_len) {
int val = i + 1;
result[i] = (val % 3) == 0;
while (val > 0) {
result[i] |= (val % 10) == 3;
val /= 10;
}
}
}
void showInfo() {
cudaDeviceProp devProp;
cudaGetDeviceProperties(&devProp, 0);
std::cout << "Devuce: " << devProp.name << std::endl;
std::cout << "Global memory available on device in bytes: " << devProp.totalGlobalMem << std::endl;
std::cout << "Shared memory available per block in bytes: " << devProp.sharedMemPerBlock << std::endl;
std::cout << "Warp size in threads: " << devProp.warpSize << std::endl;
std::cout << "Maximum number of threads per block: " << devProp.maxThreadsPerBlock << std::endl;
std::cout << "Compute capacity: " << devProp.major << "." << devProp.minor << std::endl;
std::cout << "Clock frequency in kilohertz: " << devProp.clockRate << std::endl;
std::cout << "Number of multiprocessors on device: " << devProp.multiProcessorCount << std::endl;
}
int getMaxThreadsPerBlock() {
cudaDeviceProp devProp;
cudaGetDeviceProperties(&devProp, 0);
return devProp.maxThreadsPerBlock;
}
bool invokeNabeatsu(bool *result, int result_len, int nBlock, int nThread)
{
cudaError_t cudaStatus;
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess) {
std::cerr << "cudaSetDevice failed!" << std::endl;
return false;
}
bool* dev_result = NULL;
cudaStatus = cudaMalloc((void**)&dev_result, result_len * sizeof(bool));
if (cudaStatus != cudaSuccess) {
std::cerr << "cudaMalloc failed!" << std::endl;
return false;
}
nabeatsuKernel <<<nBlock, nThread>>> (dev_result, result_len);
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess) {
std::cerr << "nabeatsuKernel failed: " << cudaGetErrorString(cudaStatus) << std::endl;
cudaFree(dev_result);
return false;
}
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess) {
std::cerr << "cudaDeviceSynchronize failed!" << std::endl;
cudaFree(dev_result);
return false;
}
cudaStatus = cudaMemcpy(result, dev_result, result_len * sizeof(bool), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
std::cerr << "cudaMemcpy failed!" << std::endl;
cudaFree(dev_result);
return false;
}
cudaFree(dev_result);
cudaDeviceReset();
return true;
} | code for sm_80
Function : _Z14nabeatsuKernelPbi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IADD3 R4, R0, 0x1, RZ ; /* 0x0000000100047810 */
/* 0x000fe20007ffe0ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0080*/ IMAD.HI R2, R4, 0x55555556, RZ ; /* 0x5555555604027827 */
/* 0x000fca00078e02ff */
/*0090*/ LEA.HI R3, R2, R2, RZ, 0x1 ; /* 0x0000000202037211 */
/* 0x000fe400078f08ff */
/*00a0*/ IADD3 R2, P1, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fc60007f3e0ff */
/*00b0*/ IMAD R3, R3, -0x3, R4 ; /* 0xfffffffd03037824 */
/* 0x000fca00078e0204 */
/*00c0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe40003f05270 */
/*00d0*/ LEA.HI.X.SX32 R3, R0.reuse, c[0x0][0x164], 0x1, P1 ; /* 0x0000590000037a11 */
/* 0x040fe400008f0eff */
/*00e0*/ SEL R5, RZ, 0x1, P0 ; /* 0x00000001ff057807 */
/* 0x000fe40000000000 */
/*00f0*/ ISETP.GE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc60003f06270 */
/*0100*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001f4000c101104 */
/*0110*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0120*/ BSSY B0, 0x200 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*0130*/ IMAD.MOV.U32 R0, RZ, RZ, R4 ; /* 0x000000ffff007224 */
/* 0x000fe200078e0004 */
/*0140*/ PRMT R7, R5, 0x7610, R7 ; /* 0x0000761005077816 */
/* 0x000fc60000000007 */
/*0150*/ IMAD.WIDE.U32 R4, R0.reuse, -0x33333333, RZ ; /* 0xcccccccd00047825 */
/* 0x041fe200078e00ff */
/*0160*/ ISETP.GT.U32.AND P1, PT, R0, 0x9, PT ; /* 0x000000090000780c */
/* 0x000fc80003f24070 */
/*0170*/ SHF.R.U32.HI R5, RZ, 0x3, R5 ; /* 0x00000003ff057819 */
/* 0x000fca0000011605 */
/*0180*/ IMAD R4, R5, -0xa, R0 ; /* 0xfffffff605047824 */
/* 0x000fe400078e0200 */
/*0190*/ IMAD.MOV.U32 R0, RZ, RZ, R5 ; /* 0x000000ffff007224 */
/* 0x000fc600078e0005 */
/*01a0*/ ISETP.NE.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fc80003f05270 */
/*01b0*/ SEL R4, RZ, 0x1, P0 ; /* 0x00000001ff047807 */
/* 0x000fc80000000000 */
/*01c0*/ LOP3.LUT P0, RZ, R4, 0xff, R7, 0xf8, !PT ; /* 0x000000ff04ff7812 */
/* 0x000fc8000780f807 */
/*01d0*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fe20004000000 */
/*01e0*/ @P1 BRA 0x150 ; /* 0xffffff6000001947 */
/* 0x000fea000383ffff */
/*01f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0200*/ STG.E.U8 [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101104 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ BRA 0x220; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
__global__ void nabeatsuKernel(bool* result, int result_len)
{
int i = (blockIdx.x * blockDim.x) + threadIdx.x;
if (i < result_len) {
int val = i + 1;
result[i] = (val % 3) == 0;
while (val > 0) {
result[i] |= (val % 10) == 3;
val /= 10;
}
}
}
void showInfo() {
cudaDeviceProp devProp;
cudaGetDeviceProperties(&devProp, 0);
std::cout << "Devuce: " << devProp.name << std::endl;
std::cout << "Global memory available on device in bytes: " << devProp.totalGlobalMem << std::endl;
std::cout << "Shared memory available per block in bytes: " << devProp.sharedMemPerBlock << std::endl;
std::cout << "Warp size in threads: " << devProp.warpSize << std::endl;
std::cout << "Maximum number of threads per block: " << devProp.maxThreadsPerBlock << std::endl;
std::cout << "Compute capacity: " << devProp.major << "." << devProp.minor << std::endl;
std::cout << "Clock frequency in kilohertz: " << devProp.clockRate << std::endl;
std::cout << "Number of multiprocessors on device: " << devProp.multiProcessorCount << std::endl;
}
int getMaxThreadsPerBlock() {
cudaDeviceProp devProp;
cudaGetDeviceProperties(&devProp, 0);
return devProp.maxThreadsPerBlock;
}
bool invokeNabeatsu(bool *result, int result_len, int nBlock, int nThread)
{
cudaError_t cudaStatus;
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess) {
std::cerr << "cudaSetDevice failed!" << std::endl;
return false;
}
bool* dev_result = NULL;
cudaStatus = cudaMalloc((void**)&dev_result, result_len * sizeof(bool));
if (cudaStatus != cudaSuccess) {
std::cerr << "cudaMalloc failed!" << std::endl;
return false;
}
nabeatsuKernel <<<nBlock, nThread>>> (dev_result, result_len);
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess) {
std::cerr << "nabeatsuKernel failed: " << cudaGetErrorString(cudaStatus) << std::endl;
cudaFree(dev_result);
return false;
}
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess) {
std::cerr << "cudaDeviceSynchronize failed!" << std::endl;
cudaFree(dev_result);
return false;
}
cudaStatus = cudaMemcpy(result, dev_result, result_len * sizeof(bool), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
std::cerr << "cudaMemcpy failed!" << std::endl;
cudaFree(dev_result);
return false;
}
cudaFree(dev_result);
cudaDeviceReset();
return true;
} | .file "tmpxft_0015c73b_00000000-6_nabeatsu.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Devuce: "
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Global memory available on device in bytes: "
.align 8
.LC2:
.string "Shared memory available per block in bytes: "
.section .rodata.str1.1
.LC3:
.string "Warp size in threads: "
.section .rodata.str1.8
.align 8
.LC4:
.string "Maximum number of threads per block: "
.section .rodata.str1.1
.LC5:
.string "Compute capacity: "
.LC6:
.string "."
.section .rodata.str1.8
.align 8
.LC7:
.string "Clock frequency in kilohertz: "
.align 8
.LC8:
.string "Number of multiprocessors on device: "
.text
.globl _Z8showInfov
.type _Z8showInfov, @function
_Z8showInfov:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $1048, %rsp
.cfi_def_cfa_offset 1072
movq %fs:40, %rax
movq %rax, 1032(%rsp)
xorl %eax, %eax
movq %rsp, %rbp
movl $0, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
movl $8, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rbp, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L38
cmpb $0, 56(%rbx)
je .L6
movzbl 67(%rbx), %esi
.L7:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $44, %edx
leaq .LC1(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 288(%rsp), %rsi
movq %rbx, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L39
cmpb $0, 56(%rbp)
je .L10
movzbl 67(%rbp), %esi
.L11:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $44, %edx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 296(%rsp), %rsi
movq %rbx, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L40
cmpb $0, 56(%rbp)
je .L14
movzbl 67(%rbp), %esi
.L15:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $22, %edx
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 308(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L41
cmpb $0, 56(%rbp)
je .L18
movzbl 67(%rbp), %esi
.L19:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $37, %edx
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 320(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L42
cmpb $0, 56(%rbp)
je .L22
movzbl 67(%rbp), %esi
.L23:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $18, %edx
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 360(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $1, %edx
leaq .LC6(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 364(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L43
cmpb $0, 56(%rbp)
je .L26
movzbl 67(%rbp), %esi
.L27:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $30, %edx
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 348(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L44
cmpb $0, 56(%rbp)
je .L30
movzbl 67(%rbp), %esi
.L31:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $37, %edx
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 388(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L45
cmpb $0, 56(%rbp)
je .L34
movzbl 67(%rbp), %esi
.L35:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L46
addq $1048, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L47
call _ZSt16__throw_bad_castv@PLT
.L47:
call __stack_chk_fail@PLT
.L6:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L7
.L39:
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L48
call _ZSt16__throw_bad_castv@PLT
.L48:
call __stack_chk_fail@PLT
.L10:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L11
.L40:
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L49
call _ZSt16__throw_bad_castv@PLT
.L49:
call __stack_chk_fail@PLT
.L14:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L15
.L41:
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L50
call _ZSt16__throw_bad_castv@PLT
.L50:
call __stack_chk_fail@PLT
.L18:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L19
.L42:
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L51
call _ZSt16__throw_bad_castv@PLT
.L51:
call __stack_chk_fail@PLT
.L22:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L23
.L43:
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L52
call _ZSt16__throw_bad_castv@PLT
.L52:
call __stack_chk_fail@PLT
.L26:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L27
.L44:
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L53
call _ZSt16__throw_bad_castv@PLT
.L53:
call __stack_chk_fail@PLT
.L30:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L31
.L45:
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L54
call _ZSt16__throw_bad_castv@PLT
.L54:
call __stack_chk_fail@PLT
.L34:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L35
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z8showInfov, .-_Z8showInfov
.globl _Z21getMaxThreadsPerBlockv
.type _Z21getMaxThreadsPerBlockv, @function
_Z21getMaxThreadsPerBlockv:
.LFB3670:
.cfi_startproc
endbr64
subq $1048, %rsp
.cfi_def_cfa_offset 1056
movq %fs:40, %rax
movq %rax, 1032(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
movl 320(%rsp), %eax
movq 1032(%rsp), %rdx
subq %fs:40, %rdx
jne .L58
addq $1048, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L58:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size _Z21getMaxThreadsPerBlockv, .-_Z21getMaxThreadsPerBlockv
.globl _Z35__device_stub__Z14nabeatsuKernelPbiPbi
.type _Z35__device_stub__Z14nabeatsuKernelPbiPbi, @function
_Z35__device_stub__Z14nabeatsuKernelPbiPbi:
.LFB3696:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L63
.L59:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L64
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L63:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14nabeatsuKernelPbi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L59
.L64:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z35__device_stub__Z14nabeatsuKernelPbiPbi, .-_Z35__device_stub__Z14nabeatsuKernelPbiPbi
.globl _Z14nabeatsuKernelPbi
.type _Z14nabeatsuKernelPbi, @function
_Z14nabeatsuKernelPbi:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z14nabeatsuKernelPbiPbi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z14nabeatsuKernelPbi, .-_Z14nabeatsuKernelPbi
.section .rodata.str1.1
.LC9:
.string "cudaSetDevice failed!"
.LC10:
.string "cudaMalloc failed!"
.LC11:
.string "nabeatsuKernel failed: "
.LC12:
.string "cudaDeviceSynchronize failed!"
.LC13:
.string "cudaMemcpy failed!"
.text
.globl _Z14invokeNabeatsuPbiii
.type _Z14invokeNabeatsuPbiii, @function
_Z14invokeNabeatsuPbiii:
.LFB3671:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r12
movl %esi, %ebx
movl %edx, %r13d
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L99
movq $0, 8(%rsp)
movslq %ebx, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L100
movl %ebp, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl %r13d, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L101
.L79:
call cudaGetLastError@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L102
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L103
movl $2, %ecx
movq %r14, %rdx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L104
movq 8(%rsp), %rdi
call cudaFree@PLT
call cudaDeviceReset@PLT
movl $1, %eax
jmp .L67
.L99:
movl $21, %edx
leaq .LC9(%rip), %rsi
leaq _ZSt4cerr(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L105
cmpb $0, 56(%rbx)
je .L71
movzbl 67(%rbx), %esi
.L72:
movsbl %sil, %esi
leaq _ZSt4cerr(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $0, %eax
.L67:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L106
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L105:
.cfi_restore_state
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L107
call _ZSt16__throw_bad_castv@PLT
.L107:
call __stack_chk_fail@PLT
.L71:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L72
.L100:
movl $18, %edx
leaq .LC10(%rip), %rsi
leaq _ZSt4cerr(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L108
cmpb $0, 56(%rbx)
je .L77
movzbl 67(%rbx), %esi
.L78:
movsbl %sil, %esi
leaq _ZSt4cerr(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $0, %eax
jmp .L67
.L108:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L109
call _ZSt16__throw_bad_castv@PLT
.L109:
call __stack_chk_fail@PLT
.L77:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L78
.L101:
movl %ebx, %esi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z14nabeatsuKernelPbiPbi
jmp .L79
.L102:
movl $23, %edx
leaq .LC11(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rbx
testq %rax, %rax
je .L110
movq %rax, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbx, %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L82:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rip), %rdx
movq 240(%rdx,%rax), %rbx
testq %rbx, %rbx
je .L111
cmpb $0, 56(%rbx)
je .L85
movzbl 67(%rbx), %esi
.L86:
movsbl %sil, %esi
leaq _ZSt4cerr(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
jmp .L67
.L110:
leaq _ZSt4cerr(%rip), %rdi
movq _ZSt4cerr(%rip), %rax
addq -24(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L82
.L111:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L112
call _ZSt16__throw_bad_castv@PLT
.L112:
call __stack_chk_fail@PLT
.L85:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L86
.L103:
movl $29, %edx
leaq .LC12(%rip), %rsi
leaq _ZSt4cerr(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L113
cmpb $0, 56(%rbx)
je .L90
movzbl 67(%rbx), %esi
.L91:
movsbl %sil, %esi
leaq _ZSt4cerr(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
jmp .L67
.L113:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L114
call _ZSt16__throw_bad_castv@PLT
.L114:
call __stack_chk_fail@PLT
.L90:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L91
.L104:
movl $18, %edx
leaq .LC13(%rip), %rsi
leaq _ZSt4cerr(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L115
cmpb $0, 56(%rbx)
je .L95
movzbl 67(%rbx), %esi
.L96:
movsbl %sil, %esi
leaq _ZSt4cerr(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
jmp .L67
.L115:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L116
call _ZSt16__throw_bad_castv@PLT
.L116:
call __stack_chk_fail@PLT
.L95:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L96
.L106:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size _Z14invokeNabeatsuPbiii, .-_Z14invokeNabeatsuPbiii
.section .rodata.str1.1
.LC14:
.string "_Z14nabeatsuKernelPbi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z14nabeatsuKernelPbi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
__global__ void nabeatsuKernel(bool* result, int result_len)
{
int i = (blockIdx.x * blockDim.x) + threadIdx.x;
if (i < result_len) {
int val = i + 1;
result[i] = (val % 3) == 0;
while (val > 0) {
result[i] |= (val % 10) == 3;
val /= 10;
}
}
}
void showInfo() {
cudaDeviceProp devProp;
cudaGetDeviceProperties(&devProp, 0);
std::cout << "Devuce: " << devProp.name << std::endl;
std::cout << "Global memory available on device in bytes: " << devProp.totalGlobalMem << std::endl;
std::cout << "Shared memory available per block in bytes: " << devProp.sharedMemPerBlock << std::endl;
std::cout << "Warp size in threads: " << devProp.warpSize << std::endl;
std::cout << "Maximum number of threads per block: " << devProp.maxThreadsPerBlock << std::endl;
std::cout << "Compute capacity: " << devProp.major << "." << devProp.minor << std::endl;
std::cout << "Clock frequency in kilohertz: " << devProp.clockRate << std::endl;
std::cout << "Number of multiprocessors on device: " << devProp.multiProcessorCount << std::endl;
}
int getMaxThreadsPerBlock() {
cudaDeviceProp devProp;
cudaGetDeviceProperties(&devProp, 0);
return devProp.maxThreadsPerBlock;
}
bool invokeNabeatsu(bool *result, int result_len, int nBlock, int nThread)
{
cudaError_t cudaStatus;
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess) {
std::cerr << "cudaSetDevice failed!" << std::endl;
return false;
}
bool* dev_result = NULL;
cudaStatus = cudaMalloc((void**)&dev_result, result_len * sizeof(bool));
if (cudaStatus != cudaSuccess) {
std::cerr << "cudaMalloc failed!" << std::endl;
return false;
}
nabeatsuKernel <<<nBlock, nThread>>> (dev_result, result_len);
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess) {
std::cerr << "nabeatsuKernel failed: " << cudaGetErrorString(cudaStatus) << std::endl;
cudaFree(dev_result);
return false;
}
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess) {
std::cerr << "cudaDeviceSynchronize failed!" << std::endl;
cudaFree(dev_result);
return false;
}
cudaStatus = cudaMemcpy(result, dev_result, result_len * sizeof(bool), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
std::cerr << "cudaMemcpy failed!" << std::endl;
cudaFree(dev_result);
return false;
}
cudaFree(dev_result);
cudaDeviceReset();
return true;
} | #include "hip/hip_runtime.h"
#include <iostream>
__global__ void nabeatsuKernel(bool* result, int result_len)
{
int i = (blockIdx.x * blockDim.x) + threadIdx.x;
if (i < result_len) {
int val = i + 1;
result[i] = (val % 3) == 0;
while (val > 0) {
result[i] |= (val % 10) == 3;
val /= 10;
}
}
}
void showInfo() {
hipDeviceProp_t devProp;
hipGetDeviceProperties(&devProp, 0);
std::cout << "Devuce: " << devProp.name << std::endl;
std::cout << "Global memory available on device in bytes: " << devProp.totalGlobalMem << std::endl;
std::cout << "Shared memory available per block in bytes: " << devProp.sharedMemPerBlock << std::endl;
std::cout << "Warp size in threads: " << devProp.warpSize << std::endl;
std::cout << "Maximum number of threads per block: " << devProp.maxThreadsPerBlock << std::endl;
std::cout << "Compute capacity: " << devProp.major << "." << devProp.minor << std::endl;
std::cout << "Clock frequency in kilohertz: " << devProp.clockRate << std::endl;
std::cout << "Number of multiprocessors on device: " << devProp.multiProcessorCount << std::endl;
}
int getMaxThreadsPerBlock() {
hipDeviceProp_t devProp;
hipGetDeviceProperties(&devProp, 0);
return devProp.maxThreadsPerBlock;
}
bool invokeNabeatsu(bool *result, int result_len, int nBlock, int nThread)
{
hipError_t cudaStatus;
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess) {
std::cerr << "hipSetDevice failed!" << std::endl;
return false;
}
bool* dev_result = NULL;
cudaStatus = hipMalloc((void**)&dev_result, result_len * sizeof(bool));
if (cudaStatus != hipSuccess) {
std::cerr << "hipMalloc failed!" << std::endl;
return false;
}
nabeatsuKernel <<<nBlock, nThread>>> (dev_result, result_len);
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess) {
std::cerr << "nabeatsuKernel failed: " << hipGetErrorString(cudaStatus) << std::endl;
hipFree(dev_result);
return false;
}
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
std::cerr << "hipDeviceSynchronize failed!" << std::endl;
hipFree(dev_result);
return false;
}
cudaStatus = hipMemcpy(result, dev_result, result_len * sizeof(bool), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
std::cerr << "hipMemcpy failed!" << std::endl;
hipFree(dev_result);
return false;
}
hipFree(dev_result);
hipDeviceReset();
return true;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <iostream>
__global__ void nabeatsuKernel(bool* result, int result_len)
{
int i = (blockIdx.x * blockDim.x) + threadIdx.x;
if (i < result_len) {
int val = i + 1;
result[i] = (val % 3) == 0;
while (val > 0) {
result[i] |= (val % 10) == 3;
val /= 10;
}
}
}
void showInfo() {
hipDeviceProp_t devProp;
hipGetDeviceProperties(&devProp, 0);
std::cout << "Devuce: " << devProp.name << std::endl;
std::cout << "Global memory available on device in bytes: " << devProp.totalGlobalMem << std::endl;
std::cout << "Shared memory available per block in bytes: " << devProp.sharedMemPerBlock << std::endl;
std::cout << "Warp size in threads: " << devProp.warpSize << std::endl;
std::cout << "Maximum number of threads per block: " << devProp.maxThreadsPerBlock << std::endl;
std::cout << "Compute capacity: " << devProp.major << "." << devProp.minor << std::endl;
std::cout << "Clock frequency in kilohertz: " << devProp.clockRate << std::endl;
std::cout << "Number of multiprocessors on device: " << devProp.multiProcessorCount << std::endl;
}
int getMaxThreadsPerBlock() {
hipDeviceProp_t devProp;
hipGetDeviceProperties(&devProp, 0);
return devProp.maxThreadsPerBlock;
}
bool invokeNabeatsu(bool *result, int result_len, int nBlock, int nThread)
{
hipError_t cudaStatus;
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess) {
std::cerr << "hipSetDevice failed!" << std::endl;
return false;
}
bool* dev_result = NULL;
cudaStatus = hipMalloc((void**)&dev_result, result_len * sizeof(bool));
if (cudaStatus != hipSuccess) {
std::cerr << "hipMalloc failed!" << std::endl;
return false;
}
nabeatsuKernel <<<nBlock, nThread>>> (dev_result, result_len);
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess) {
std::cerr << "nabeatsuKernel failed: " << hipGetErrorString(cudaStatus) << std::endl;
hipFree(dev_result);
return false;
}
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
std::cerr << "hipDeviceSynchronize failed!" << std::endl;
hipFree(dev_result);
return false;
}
cudaStatus = hipMemcpy(result, dev_result, result_len * sizeof(bool), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
std::cerr << "hipMemcpy failed!" << std::endl;
hipFree(dev_result);
return false;
}
hipFree(dev_result);
hipDeviceReset();
return true;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14nabeatsuKernelPbi
.globl _Z14nabeatsuKernelPbi
.p2align 8
.type _Z14nabeatsuKernelPbi,@function
_Z14nabeatsuKernelPbi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v2
s_cbranch_execz .LBB0_5
s_load_b64 s[0:1], s[0:1], 0x0
v_add_nc_u32_e32 v3, 1, v2
s_mov_b32 s2, 0xaaaaaaab
v_ashrrev_i32_e32 v1, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[4:5], null, v3, s2, 0x2aaaaaaa
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_cmp_gt_u32_e32 vcc_lo, 0x55555555, v4
v_cndmask_b32_e64 v4, 0, 1, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, -1, v2
global_store_b8 v[0:1], v4, off
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_5
global_load_u8 v2, v[0:1], off
s_mov_b32 s0, 0
.LBB0_3:
v_mul_hi_u32 v4, v3, 0xcccccccd
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v4, 3, v4
v_mul_lo_u32 v5, v4, 10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v3, v5
v_cmp_eq_u32_e32 vcc_lo, 3, v5
v_cndmask_b32_e64 v5, 0, 1, vcc_lo
v_cmp_gt_u32_e32 vcc_lo, 10, v3
v_mov_b32_e32 v3, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_or_b32_e32 v2, v2, v5
s_or_b32 s0, vcc_lo, s0
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s0
global_store_b8 v[0:1], v2, off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14nabeatsuKernelPbi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14nabeatsuKernelPbi, .Lfunc_end0-_Z14nabeatsuKernelPbi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14nabeatsuKernelPbi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14nabeatsuKernelPbi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <iostream>
__global__ void nabeatsuKernel(bool* result, int result_len)
{
int i = (blockIdx.x * blockDim.x) + threadIdx.x;
if (i < result_len) {
int val = i + 1;
result[i] = (val % 3) == 0;
while (val > 0) {
result[i] |= (val % 10) == 3;
val /= 10;
}
}
}
void showInfo() {
hipDeviceProp_t devProp;
hipGetDeviceProperties(&devProp, 0);
std::cout << "Devuce: " << devProp.name << std::endl;
std::cout << "Global memory available on device in bytes: " << devProp.totalGlobalMem << std::endl;
std::cout << "Shared memory available per block in bytes: " << devProp.sharedMemPerBlock << std::endl;
std::cout << "Warp size in threads: " << devProp.warpSize << std::endl;
std::cout << "Maximum number of threads per block: " << devProp.maxThreadsPerBlock << std::endl;
std::cout << "Compute capacity: " << devProp.major << "." << devProp.minor << std::endl;
std::cout << "Clock frequency in kilohertz: " << devProp.clockRate << std::endl;
std::cout << "Number of multiprocessors on device: " << devProp.multiProcessorCount << std::endl;
}
int getMaxThreadsPerBlock() {
hipDeviceProp_t devProp;
hipGetDeviceProperties(&devProp, 0);
return devProp.maxThreadsPerBlock;
}
bool invokeNabeatsu(bool *result, int result_len, int nBlock, int nThread)
{
hipError_t cudaStatus;
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess) {
std::cerr << "hipSetDevice failed!" << std::endl;
return false;
}
bool* dev_result = NULL;
cudaStatus = hipMalloc((void**)&dev_result, result_len * sizeof(bool));
if (cudaStatus != hipSuccess) {
std::cerr << "hipMalloc failed!" << std::endl;
return false;
}
nabeatsuKernel <<<nBlock, nThread>>> (dev_result, result_len);
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess) {
std::cerr << "nabeatsuKernel failed: " << hipGetErrorString(cudaStatus) << std::endl;
hipFree(dev_result);
return false;
}
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
std::cerr << "hipDeviceSynchronize failed!" << std::endl;
hipFree(dev_result);
return false;
}
cudaStatus = hipMemcpy(result, dev_result, result_len * sizeof(bool), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
std::cerr << "hipMemcpy failed!" << std::endl;
hipFree(dev_result);
return false;
}
hipFree(dev_result);
hipDeviceReset();
return true;
} | .text
.file "nabeatsu.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z29__device_stub__nabeatsuKernelPbi # -- Begin function _Z29__device_stub__nabeatsuKernelPbi
.p2align 4, 0x90
.type _Z29__device_stub__nabeatsuKernelPbi,@function
_Z29__device_stub__nabeatsuKernelPbi: # @_Z29__device_stub__nabeatsuKernelPbi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14nabeatsuKernelPbi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z29__device_stub__nabeatsuKernelPbi, .Lfunc_end0-_Z29__device_stub__nabeatsuKernelPbi
.cfi_endproc
# -- End function
.globl _Z8showInfov # -- Begin function _Z8showInfov
.p2align 4, 0x90
.type _Z8showInfov,@function
_Z8showInfov: # @_Z8showInfov
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 8(%rsp), %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
callq strlen
movl $_ZSt4cout, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_33
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB1_4
.LBB1_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $44, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 296(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_33
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i2
cmpb $0, 56(%rbx)
je .LBB1_7
# %bb.6:
movzbl 67(%rbx), %ecx
jmp .LBB1_8
.LBB1_7:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit5
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $44, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 304(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_33
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i7
cmpb $0, 56(%rbx)
je .LBB1_11
# %bb.10:
movzbl 67(%rbx), %ecx
jmp .LBB1_12
.LBB1_11:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit10
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 316(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_33
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i12
cmpb $0, 56(%rbx)
je .LBB1_15
# %bb.14:
movzbl 67(%rbx), %ecx
jmp .LBB1_16
.LBB1_15:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit15
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $37, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 328(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_33
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i17
cmpb $0, 56(%rbx)
je .LBB1_19
# %bb.18:
movzbl 67(%rbx), %ecx
jmp .LBB1_20
.LBB1_19:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit20
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 368(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.6, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 372(%rsp), %esi
movq %rbx, %rdi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_33
# %bb.21: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i22
cmpb $0, 56(%rbx)
je .LBB1_23
# %bb.22:
movzbl 67(%rbx), %ecx
jmp .LBB1_24
.LBB1_23:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_24: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit25
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $30, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 356(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_33
# %bb.25: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i27
cmpb $0, 56(%rbx)
je .LBB1_27
# %bb.26:
movzbl 67(%rbx), %ecx
jmp .LBB1_28
.LBB1_27:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_28: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit30
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $37, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 396(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_33
# %bb.29: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i32
cmpb $0, 56(%rbx)
je .LBB1_31
# %bb.30:
movzbl 67(%rbx), %ecx
jmp .LBB1_32
.LBB1_31:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_32: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit35
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_33:
.cfi_def_cfa_offset 1504
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size _Z8showInfov, .Lfunc_end1-_Z8showInfov
.cfi_endproc
# -- End function
.globl _Z21getMaxThreadsPerBlockv # -- Begin function _Z21getMaxThreadsPerBlockv
.p2align 4, 0x90
.type _Z21getMaxThreadsPerBlockv,@function
_Z21getMaxThreadsPerBlockv: # @_Z21getMaxThreadsPerBlockv
.cfi_startproc
# %bb.0:
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1488
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl 328(%rsp), %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z21getMaxThreadsPerBlockv, .Lfunc_end2-_Z21getMaxThreadsPerBlockv
.cfi_endproc
# -- End function
.globl _Z14invokeNabeatsuPbiii # -- Begin function _Z14invokeNabeatsuPbiii
.p2align 4, 0x90
.type _Z14invokeNabeatsuPbiii,@function
_Z14invokeNabeatsuPbiii: # @_Z14invokeNabeatsuPbiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $96, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %r15d
movl %edx, %r12d
movl %esi, %ebp
movq %rdi, %rbx
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
je .LBB3_4
# %bb.1:
movl $_ZSt4cerr, %edi
movl $.L.str.9, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %rbx
testq %rbx, %rbx
je .LBB3_31
# %bb.2: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB3_8
.LBB3_3:
movzbl 67(%rbx), %eax
jmp .LBB3_9
.LBB3_4:
movq $0, 8(%rsp)
movslq %ebp, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
je .LBB3_12
# %bb.5:
movl $_ZSt4cerr, %edi
movl $.L.str.10, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %rbx
testq %rbx, %rbx
je .LBB3_31
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i21
cmpb $0, 56(%rbx)
jne .LBB3_3
.LBB3_8:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB3_10:
xorl %eax, %eax
.LBB3_11:
# kill: def $al killed $al killed $eax
addq $96, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_12:
.cfi_def_cfa_offset 144
movl %r12d, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %r15d, %edx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_14
# %bb.13:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl %ebp, 20(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14nabeatsuKernelPbi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_14:
callq hipGetLastError
testl %eax, %eax
je .LBB3_17
# %bb.15:
movl %eax, %ebp
movl $_ZSt4cerr, %edi
movl $.L.str.11, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebp, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB3_21
# %bb.16:
movq %rax, %rdi
movq %rax, %rbx
callq strlen
movl $_ZSt4cerr, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB3_22
.LBB3_17:
callq hipDeviceSynchronize
testl %eax, %eax
je .LBB3_28
# %bb.18:
movl $_ZSt4cerr, %edi
movl $.L.str.12, %esi
movl $28, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %rbx
testq %rbx, %rbx
je .LBB3_31
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i31
cmpb $0, 56(%rbx)
jne .LBB3_24
.LBB3_25:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
jmp .LBB3_26
.LBB3_21:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl _ZSt4cerr+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB3_22: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %rbx
testq %rbx, %rbx
je .LBB3_31
# %bb.23: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i26
cmpb $0, 56(%rbx)
je .LBB3_25
.LBB3_24:
movzbl 67(%rbx), %eax
.LBB3_26: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit29
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB3_27:
movq 8(%rsp), %rdi
callq hipFree
jmp .LBB3_10
.LBB3_28:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB3_30
# %bb.29:
movl $_ZSt4cerr, %edi
movl $.L.str.13, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cerr, %edi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
jmp .LBB3_27
.LBB3_30:
movq 8(%rsp), %rdi
callq hipFree
callq hipDeviceReset
movb $1, %al
jmp .LBB3_11
.LBB3_31:
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size _Z14invokeNabeatsuPbiii, .Lfunc_end3-_Z14invokeNabeatsuPbiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14nabeatsuKernelPbi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14nabeatsuKernelPbi,@object # @_Z14nabeatsuKernelPbi
.section .rodata,"a",@progbits
.globl _Z14nabeatsuKernelPbi
.p2align 3, 0x0
_Z14nabeatsuKernelPbi:
.quad _Z29__device_stub__nabeatsuKernelPbi
.size _Z14nabeatsuKernelPbi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Devuce: "
.size .L.str, 9
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Global memory available on device in bytes: "
.size .L.str.1, 45
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Shared memory available per block in bytes: "
.size .L.str.2, 45
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Warp size in threads: "
.size .L.str.3, 23
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Maximum number of threads per block: "
.size .L.str.4, 38
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Compute capacity: "
.size .L.str.5, 19
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "."
.size .L.str.6, 2
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Clock frequency in kilohertz: "
.size .L.str.7, 31
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Number of multiprocessors on device: "
.size .L.str.8, 38
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "hipSetDevice failed!"
.size .L.str.9, 21
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "hipMalloc failed!"
.size .L.str.10, 18
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "nabeatsuKernel failed: "
.size .L.str.11, 24
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "hipDeviceSynchronize failed!"
.size .L.str.12, 29
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "hipMemcpy failed!"
.size .L.str.13, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14nabeatsuKernelPbi"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__nabeatsuKernelPbi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14nabeatsuKernelPbi
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt4cerr
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14nabeatsuKernelPbi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IADD3 R4, R0, 0x1, RZ ; /* 0x0000000100047810 */
/* 0x000fe20007ffe0ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0080*/ IMAD.HI R2, R4, 0x55555556, RZ ; /* 0x5555555604027827 */
/* 0x000fca00078e02ff */
/*0090*/ LEA.HI R3, R2, R2, RZ, 0x1 ; /* 0x0000000202037211 */
/* 0x000fe400078f08ff */
/*00a0*/ IADD3 R2, P1, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fc60007f3e0ff */
/*00b0*/ IMAD R3, R3, -0x3, R4 ; /* 0xfffffffd03037824 */
/* 0x000fca00078e0204 */
/*00c0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe40003f05270 */
/*00d0*/ LEA.HI.X.SX32 R3, R0.reuse, c[0x0][0x164], 0x1, P1 ; /* 0x0000590000037a11 */
/* 0x040fe400008f0eff */
/*00e0*/ SEL R5, RZ, 0x1, P0 ; /* 0x00000001ff057807 */
/* 0x000fe40000000000 */
/*00f0*/ ISETP.GE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc60003f06270 */
/*0100*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001f4000c101104 */
/*0110*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0120*/ BSSY B0, 0x200 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*0130*/ IMAD.MOV.U32 R0, RZ, RZ, R4 ; /* 0x000000ffff007224 */
/* 0x000fe200078e0004 */
/*0140*/ PRMT R7, R5, 0x7610, R7 ; /* 0x0000761005077816 */
/* 0x000fc60000000007 */
/*0150*/ IMAD.WIDE.U32 R4, R0.reuse, -0x33333333, RZ ; /* 0xcccccccd00047825 */
/* 0x041fe200078e00ff */
/*0160*/ ISETP.GT.U32.AND P1, PT, R0, 0x9, PT ; /* 0x000000090000780c */
/* 0x000fc80003f24070 */
/*0170*/ SHF.R.U32.HI R5, RZ, 0x3, R5 ; /* 0x00000003ff057819 */
/* 0x000fca0000011605 */
/*0180*/ IMAD R4, R5, -0xa, R0 ; /* 0xfffffff605047824 */
/* 0x000fe400078e0200 */
/*0190*/ IMAD.MOV.U32 R0, RZ, RZ, R5 ; /* 0x000000ffff007224 */
/* 0x000fc600078e0005 */
/*01a0*/ ISETP.NE.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fc80003f05270 */
/*01b0*/ SEL R4, RZ, 0x1, P0 ; /* 0x00000001ff047807 */
/* 0x000fc80000000000 */
/*01c0*/ LOP3.LUT P0, RZ, R4, 0xff, R7, 0xf8, !PT ; /* 0x000000ff04ff7812 */
/* 0x000fc8000780f807 */
/*01d0*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fe20004000000 */
/*01e0*/ @P1 BRA 0x150 ; /* 0xffffff6000001947 */
/* 0x000fea000383ffff */
/*01f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0200*/ STG.E.U8 [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101104 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ BRA 0x220; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14nabeatsuKernelPbi
.globl _Z14nabeatsuKernelPbi
.p2align 8
.type _Z14nabeatsuKernelPbi,@function
_Z14nabeatsuKernelPbi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v2
s_cbranch_execz .LBB0_5
s_load_b64 s[0:1], s[0:1], 0x0
v_add_nc_u32_e32 v3, 1, v2
s_mov_b32 s2, 0xaaaaaaab
v_ashrrev_i32_e32 v1, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[4:5], null, v3, s2, 0x2aaaaaaa
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_cmp_gt_u32_e32 vcc_lo, 0x55555555, v4
v_cndmask_b32_e64 v4, 0, 1, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, -1, v2
global_store_b8 v[0:1], v4, off
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_5
global_load_u8 v2, v[0:1], off
s_mov_b32 s0, 0
.LBB0_3:
v_mul_hi_u32 v4, v3, 0xcccccccd
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v4, 3, v4
v_mul_lo_u32 v5, v4, 10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v3, v5
v_cmp_eq_u32_e32 vcc_lo, 3, v5
v_cndmask_b32_e64 v5, 0, 1, vcc_lo
v_cmp_gt_u32_e32 vcc_lo, 10, v3
v_mov_b32_e32 v3, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_or_b32_e32 v2, v2, v5
s_or_b32 s0, vcc_lo, s0
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s0
global_store_b8 v[0:1], v2, off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14nabeatsuKernelPbi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14nabeatsuKernelPbi, .Lfunc_end0-_Z14nabeatsuKernelPbi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14nabeatsuKernelPbi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14nabeatsuKernelPbi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0015c73b_00000000-6_nabeatsu.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Devuce: "
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Global memory available on device in bytes: "
.align 8
.LC2:
.string "Shared memory available per block in bytes: "
.section .rodata.str1.1
.LC3:
.string "Warp size in threads: "
.section .rodata.str1.8
.align 8
.LC4:
.string "Maximum number of threads per block: "
.section .rodata.str1.1
.LC5:
.string "Compute capacity: "
.LC6:
.string "."
.section .rodata.str1.8
.align 8
.LC7:
.string "Clock frequency in kilohertz: "
.align 8
.LC8:
.string "Number of multiprocessors on device: "
.text
.globl _Z8showInfov
.type _Z8showInfov, @function
_Z8showInfov:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $1048, %rsp
.cfi_def_cfa_offset 1072
movq %fs:40, %rax
movq %rax, 1032(%rsp)
xorl %eax, %eax
movq %rsp, %rbp
movl $0, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
movl $8, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rbp, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L38
cmpb $0, 56(%rbx)
je .L6
movzbl 67(%rbx), %esi
.L7:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $44, %edx
leaq .LC1(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 288(%rsp), %rsi
movq %rbx, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L39
cmpb $0, 56(%rbp)
je .L10
movzbl 67(%rbp), %esi
.L11:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $44, %edx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 296(%rsp), %rsi
movq %rbx, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L40
cmpb $0, 56(%rbp)
je .L14
movzbl 67(%rbp), %esi
.L15:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $22, %edx
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 308(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L41
cmpb $0, 56(%rbp)
je .L18
movzbl 67(%rbp), %esi
.L19:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $37, %edx
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 320(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L42
cmpb $0, 56(%rbp)
je .L22
movzbl 67(%rbp), %esi
.L23:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $18, %edx
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 360(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $1, %edx
leaq .LC6(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 364(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L43
cmpb $0, 56(%rbp)
je .L26
movzbl 67(%rbp), %esi
.L27:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $30, %edx
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 348(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L44
cmpb $0, 56(%rbp)
je .L30
movzbl 67(%rbp), %esi
.L31:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $37, %edx
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 388(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L45
cmpb $0, 56(%rbp)
je .L34
movzbl 67(%rbp), %esi
.L35:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L46
addq $1048, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L47
call _ZSt16__throw_bad_castv@PLT
.L47:
call __stack_chk_fail@PLT
.L6:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L7
.L39:
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L48
call _ZSt16__throw_bad_castv@PLT
.L48:
call __stack_chk_fail@PLT
.L10:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L11
.L40:
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L49
call _ZSt16__throw_bad_castv@PLT
.L49:
call __stack_chk_fail@PLT
.L14:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L15
.L41:
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L50
call _ZSt16__throw_bad_castv@PLT
.L50:
call __stack_chk_fail@PLT
.L18:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L19
.L42:
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L51
call _ZSt16__throw_bad_castv@PLT
.L51:
call __stack_chk_fail@PLT
.L22:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L23
.L43:
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L52
call _ZSt16__throw_bad_castv@PLT
.L52:
call __stack_chk_fail@PLT
.L26:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L27
.L44:
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L53
call _ZSt16__throw_bad_castv@PLT
.L53:
call __stack_chk_fail@PLT
.L30:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L31
.L45:
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L54
call _ZSt16__throw_bad_castv@PLT
.L54:
call __stack_chk_fail@PLT
.L34:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L35
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z8showInfov, .-_Z8showInfov
.globl _Z21getMaxThreadsPerBlockv
.type _Z21getMaxThreadsPerBlockv, @function
_Z21getMaxThreadsPerBlockv:
.LFB3670:
.cfi_startproc
endbr64
subq $1048, %rsp
.cfi_def_cfa_offset 1056
movq %fs:40, %rax
movq %rax, 1032(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
movl 320(%rsp), %eax
movq 1032(%rsp), %rdx
subq %fs:40, %rdx
jne .L58
addq $1048, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L58:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size _Z21getMaxThreadsPerBlockv, .-_Z21getMaxThreadsPerBlockv
.globl _Z35__device_stub__Z14nabeatsuKernelPbiPbi
.type _Z35__device_stub__Z14nabeatsuKernelPbiPbi, @function
_Z35__device_stub__Z14nabeatsuKernelPbiPbi:
.LFB3696:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L63
.L59:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L64
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L63:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14nabeatsuKernelPbi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L59
.L64:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z35__device_stub__Z14nabeatsuKernelPbiPbi, .-_Z35__device_stub__Z14nabeatsuKernelPbiPbi
.globl _Z14nabeatsuKernelPbi
.type _Z14nabeatsuKernelPbi, @function
_Z14nabeatsuKernelPbi:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z14nabeatsuKernelPbiPbi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z14nabeatsuKernelPbi, .-_Z14nabeatsuKernelPbi
.section .rodata.str1.1
.LC9:
.string "cudaSetDevice failed!"
.LC10:
.string "cudaMalloc failed!"
.LC11:
.string "nabeatsuKernel failed: "
.LC12:
.string "cudaDeviceSynchronize failed!"
.LC13:
.string "cudaMemcpy failed!"
.text
.globl _Z14invokeNabeatsuPbiii
.type _Z14invokeNabeatsuPbiii, @function
_Z14invokeNabeatsuPbiii:
.LFB3671:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r12
movl %esi, %ebx
movl %edx, %r13d
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L99
movq $0, 8(%rsp)
movslq %ebx, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L100
movl %ebp, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl %r13d, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L101
.L79:
call cudaGetLastError@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L102
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L103
movl $2, %ecx
movq %r14, %rdx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L104
movq 8(%rsp), %rdi
call cudaFree@PLT
call cudaDeviceReset@PLT
movl $1, %eax
jmp .L67
.L99:
movl $21, %edx
leaq .LC9(%rip), %rsi
leaq _ZSt4cerr(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L105
cmpb $0, 56(%rbx)
je .L71
movzbl 67(%rbx), %esi
.L72:
movsbl %sil, %esi
leaq _ZSt4cerr(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $0, %eax
.L67:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L106
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L105:
.cfi_restore_state
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L107
call _ZSt16__throw_bad_castv@PLT
.L107:
call __stack_chk_fail@PLT
.L71:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L72
.L100:
movl $18, %edx
leaq .LC10(%rip), %rsi
leaq _ZSt4cerr(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L108
cmpb $0, 56(%rbx)
je .L77
movzbl 67(%rbx), %esi
.L78:
movsbl %sil, %esi
leaq _ZSt4cerr(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $0, %eax
jmp .L67
.L108:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L109
call _ZSt16__throw_bad_castv@PLT
.L109:
call __stack_chk_fail@PLT
.L77:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L78
.L101:
movl %ebx, %esi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z14nabeatsuKernelPbiPbi
jmp .L79
.L102:
movl $23, %edx
leaq .LC11(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rbx
testq %rax, %rax
je .L110
movq %rax, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbx, %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L82:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rip), %rdx
movq 240(%rdx,%rax), %rbx
testq %rbx, %rbx
je .L111
cmpb $0, 56(%rbx)
je .L85
movzbl 67(%rbx), %esi
.L86:
movsbl %sil, %esi
leaq _ZSt4cerr(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
jmp .L67
.L110:
leaq _ZSt4cerr(%rip), %rdi
movq _ZSt4cerr(%rip), %rax
addq -24(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L82
.L111:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L112
call _ZSt16__throw_bad_castv@PLT
.L112:
call __stack_chk_fail@PLT
.L85:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L86
.L103:
movl $29, %edx
leaq .LC12(%rip), %rsi
leaq _ZSt4cerr(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L113
cmpb $0, 56(%rbx)
je .L90
movzbl 67(%rbx), %esi
.L91:
movsbl %sil, %esi
leaq _ZSt4cerr(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
jmp .L67
.L113:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L114
call _ZSt16__throw_bad_castv@PLT
.L114:
call __stack_chk_fail@PLT
.L90:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L91
.L104:
movl $18, %edx
leaq .LC13(%rip), %rsi
leaq _ZSt4cerr(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L115
cmpb $0, 56(%rbx)
je .L95
movzbl 67(%rbx), %esi
.L96:
movsbl %sil, %esi
leaq _ZSt4cerr(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
jmp .L67
.L115:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L116
call _ZSt16__throw_bad_castv@PLT
.L116:
call __stack_chk_fail@PLT
.L95:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L96
.L106:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size _Z14invokeNabeatsuPbiii, .-_Z14invokeNabeatsuPbiii
.section .rodata.str1.1
.LC14:
.string "_Z14nabeatsuKernelPbi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z14nabeatsuKernelPbi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "nabeatsu.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z29__device_stub__nabeatsuKernelPbi # -- Begin function _Z29__device_stub__nabeatsuKernelPbi
.p2align 4, 0x90
.type _Z29__device_stub__nabeatsuKernelPbi,@function
_Z29__device_stub__nabeatsuKernelPbi: # @_Z29__device_stub__nabeatsuKernelPbi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14nabeatsuKernelPbi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z29__device_stub__nabeatsuKernelPbi, .Lfunc_end0-_Z29__device_stub__nabeatsuKernelPbi
.cfi_endproc
# -- End function
.globl _Z8showInfov # -- Begin function _Z8showInfov
.p2align 4, 0x90
.type _Z8showInfov,@function
_Z8showInfov: # @_Z8showInfov
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 8(%rsp), %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
callq strlen
movl $_ZSt4cout, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_33
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB1_4
.LBB1_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $44, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 296(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_33
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i2
cmpb $0, 56(%rbx)
je .LBB1_7
# %bb.6:
movzbl 67(%rbx), %ecx
jmp .LBB1_8
.LBB1_7:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit5
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $44, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 304(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_33
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i7
cmpb $0, 56(%rbx)
je .LBB1_11
# %bb.10:
movzbl 67(%rbx), %ecx
jmp .LBB1_12
.LBB1_11:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit10
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 316(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_33
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i12
cmpb $0, 56(%rbx)
je .LBB1_15
# %bb.14:
movzbl 67(%rbx), %ecx
jmp .LBB1_16
.LBB1_15:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit15
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $37, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 328(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_33
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i17
cmpb $0, 56(%rbx)
je .LBB1_19
# %bb.18:
movzbl 67(%rbx), %ecx
jmp .LBB1_20
.LBB1_19:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit20
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 368(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.6, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 372(%rsp), %esi
movq %rbx, %rdi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_33
# %bb.21: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i22
cmpb $0, 56(%rbx)
je .LBB1_23
# %bb.22:
movzbl 67(%rbx), %ecx
jmp .LBB1_24
.LBB1_23:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_24: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit25
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $30, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 356(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_33
# %bb.25: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i27
cmpb $0, 56(%rbx)
je .LBB1_27
# %bb.26:
movzbl 67(%rbx), %ecx
jmp .LBB1_28
.LBB1_27:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_28: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit30
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $37, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 396(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_33
# %bb.29: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i32
cmpb $0, 56(%rbx)
je .LBB1_31
# %bb.30:
movzbl 67(%rbx), %ecx
jmp .LBB1_32
.LBB1_31:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_32: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit35
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_33:
.cfi_def_cfa_offset 1504
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size _Z8showInfov, .Lfunc_end1-_Z8showInfov
.cfi_endproc
# -- End function
.globl _Z21getMaxThreadsPerBlockv # -- Begin function _Z21getMaxThreadsPerBlockv
.p2align 4, 0x90
.type _Z21getMaxThreadsPerBlockv,@function
_Z21getMaxThreadsPerBlockv: # @_Z21getMaxThreadsPerBlockv
.cfi_startproc
# %bb.0:
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1488
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl 328(%rsp), %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z21getMaxThreadsPerBlockv, .Lfunc_end2-_Z21getMaxThreadsPerBlockv
.cfi_endproc
# -- End function
.globl _Z14invokeNabeatsuPbiii # -- Begin function _Z14invokeNabeatsuPbiii
.p2align 4, 0x90
.type _Z14invokeNabeatsuPbiii,@function
_Z14invokeNabeatsuPbiii: # @_Z14invokeNabeatsuPbiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $96, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %r15d
movl %edx, %r12d
movl %esi, %ebp
movq %rdi, %rbx
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
je .LBB3_4
# %bb.1:
movl $_ZSt4cerr, %edi
movl $.L.str.9, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %rbx
testq %rbx, %rbx
je .LBB3_31
# %bb.2: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB3_8
.LBB3_3:
movzbl 67(%rbx), %eax
jmp .LBB3_9
.LBB3_4:
movq $0, 8(%rsp)
movslq %ebp, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
je .LBB3_12
# %bb.5:
movl $_ZSt4cerr, %edi
movl $.L.str.10, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %rbx
testq %rbx, %rbx
je .LBB3_31
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i21
cmpb $0, 56(%rbx)
jne .LBB3_3
.LBB3_8:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB3_10:
xorl %eax, %eax
.LBB3_11:
# kill: def $al killed $al killed $eax
addq $96, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_12:
.cfi_def_cfa_offset 144
movl %r12d, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %r15d, %edx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_14
# %bb.13:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl %ebp, 20(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14nabeatsuKernelPbi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_14:
callq hipGetLastError
testl %eax, %eax
je .LBB3_17
# %bb.15:
movl %eax, %ebp
movl $_ZSt4cerr, %edi
movl $.L.str.11, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebp, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB3_21
# %bb.16:
movq %rax, %rdi
movq %rax, %rbx
callq strlen
movl $_ZSt4cerr, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB3_22
.LBB3_17:
callq hipDeviceSynchronize
testl %eax, %eax
je .LBB3_28
# %bb.18:
movl $_ZSt4cerr, %edi
movl $.L.str.12, %esi
movl $28, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %rbx
testq %rbx, %rbx
je .LBB3_31
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i31
cmpb $0, 56(%rbx)
jne .LBB3_24
.LBB3_25:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
jmp .LBB3_26
.LBB3_21:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl _ZSt4cerr+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB3_22: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %rbx
testq %rbx, %rbx
je .LBB3_31
# %bb.23: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i26
cmpb $0, 56(%rbx)
je .LBB3_25
.LBB3_24:
movzbl 67(%rbx), %eax
.LBB3_26: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit29
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB3_27:
movq 8(%rsp), %rdi
callq hipFree
jmp .LBB3_10
.LBB3_28:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB3_30
# %bb.29:
movl $_ZSt4cerr, %edi
movl $.L.str.13, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cerr, %edi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
jmp .LBB3_27
.LBB3_30:
movq 8(%rsp), %rdi
callq hipFree
callq hipDeviceReset
movb $1, %al
jmp .LBB3_11
.LBB3_31:
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size _Z14invokeNabeatsuPbiii, .Lfunc_end3-_Z14invokeNabeatsuPbiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14nabeatsuKernelPbi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14nabeatsuKernelPbi,@object # @_Z14nabeatsuKernelPbi
.section .rodata,"a",@progbits
.globl _Z14nabeatsuKernelPbi
.p2align 3, 0x0
_Z14nabeatsuKernelPbi:
.quad _Z29__device_stub__nabeatsuKernelPbi
.size _Z14nabeatsuKernelPbi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Devuce: "
.size .L.str, 9
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Global memory available on device in bytes: "
.size .L.str.1, 45
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Shared memory available per block in bytes: "
.size .L.str.2, 45
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Warp size in threads: "
.size .L.str.3, 23
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Maximum number of threads per block: "
.size .L.str.4, 38
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Compute capacity: "
.size .L.str.5, 19
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "."
.size .L.str.6, 2
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Clock frequency in kilohertz: "
.size .L.str.7, 31
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Number of multiprocessors on device: "
.size .L.str.8, 38
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "hipSetDevice failed!"
.size .L.str.9, 21
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "hipMalloc failed!"
.size .L.str.10, 18
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "nabeatsuKernel failed: "
.size .L.str.11, 24
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "hipDeviceSynchronize failed!"
.size .L.str.12, 29
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "hipMemcpy failed!"
.size .L.str.13, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14nabeatsuKernelPbi"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__nabeatsuKernelPbi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14nabeatsuKernelPbi
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt4cerr
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <time.h>
#include <sys/time.h>
#include <curand_kernel.h>
#define D 5
#define TRIALS_PER_THREAD 2048
#define BLOCKS 256
#define THREADS 256
__global__ void mc_int(double *res, curandState *states) {
unsigned int tid = threadIdx.x + blockDim.x*blockIdx.x;
double integral = 0.0;
double X[D];
curand_init(tid, 0, 0, &states[tid]);
for (int i = 0; i < TRIALS_PER_THREAD; i++) {
for (int j = 0; j < D; j++) {
X[j] = curand_uniform(&states[tid]);
}
double t = 0.0;
for (int j = 0; j < D; j++) {
t -= X[j] * X[j];
}
integral += exp(t) / TRIALS_PER_THREAD;
}
res[tid] = integral;
}
int main(int argc, char **argv) {
double host[BLOCKS * THREADS];
double *dev;
curandState *states;
double integral = 0.0;
double vol = 1.0;
clock_t ts = clock();
struct timeval start, end;
gettimeofday(&start, NULL);
cudaMalloc((void**) &dev, BLOCKS * THREADS * sizeof(double));
cudaMalloc((void**)&states,
BLOCKS * THREADS * sizeof(curandState));
mc_int<<<BLOCKS, THREADS>>>(dev, states);
cudaMemcpy(host, dev, BLOCKS * THREADS * sizeof(double),
cudaMemcpyDeviceToHost);
for(int i = 0; i < BLOCKS * THREADS; i++) {
integral += host[i];
}
integral /= BLOCKS * THREADS;
for (int j = 0; j < D; j++) {
vol *= 1.0;
}
integral *= vol;
gettimeofday(&end, NULL);
double elapsed = ((end.tv_sec - start.tv_sec) * 1000000u +
end.tv_usec - start.tv_usec) / 1.e6;
ts = clock() - ts;
printf("%ld clocks (%lf seconds)\n", ts, elapsed);
printf("integral is: %lf\n", integral);
cudaFree(dev);
cudaFree(states);
} | code for sm_80
Function : _Z6mc_intPdP17curandStateXORWOW
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R14, SR_CTAID.X ; /* 0x00000000000e7919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R15, RZ, RZ, 0x30 ; /* 0x00000030ff0f7424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R13, RZ, RZ, -0x75bd8fc ; /* 0xf8a42704ff0d7424 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ IMAD.MOV.U32 R6, RZ, RZ, -0x23270784 ; /* 0xdcd8f87cff067424 */
/* 0x000fe200078e00ff */
/*0070*/ CS2R R4, SRZ ; /* 0x0000000000047805 */
/* 0x000fe2000001ff00 */
/*0080*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe400078e00ff */
/*0090*/ IMAD.MOV.U32 R11, RZ, RZ, -0x75bd8fc ; /* 0xf8a42704ff0b7424 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD.MOV.U32 R8, RZ, RZ, -0x23270784 ; /* 0xdcd8f87cff087424 */
/* 0x000fc400078e00ff */
/*00b0*/ IMAD R14, R14, c[0x0][0x0], R3 ; /* 0x000000000e0e7a24 */
/* 0x001fca00078e0203 */
/*00c0*/ LOP3.LUT R0, R14.reuse, 0xaad26b49, RZ, 0x3c, !PT ; /* 0xaad26b490e007812 */
/* 0x040fe200078e3cff */
/*00d0*/ IMAD.WIDE.U32 R14, R14, R15, c[0x0][0x168] ; /* 0x00005a000e0e7625 */
/* 0x000fc800078e000f */
/*00e0*/ IMAD R0, R0, 0x4182bed5, RZ ; /* 0x4182bed500007824 */
/* 0x000fe200078e02ff */
/*00f0*/ STG.E.64 [R14.64+0x18], RZ ; /* 0x000018ff0e007986 */
/* 0x0001e8000c101b04 */
/*0100*/ IADD3 R3, R0.reuse, 0x75bcd15, RZ ; /* 0x075bcd1500037810 */
/* 0x040fe20007ffe0ff */
/*0110*/ STG.E [R14.64+0x20], RZ ; /* 0x000020ff0e007986 */
/* 0x0001e2000c101904 */
/*0120*/ IADD3 R2, R0.reuse, -0x260923e8, RZ ; /* 0xd9f6dc1800027810 */
/* 0x040fe40007ffe0ff */
/*0130*/ LOP3.LUT R12, R0.reuse, 0x159a55e5, RZ, 0x3c, !PT ; /* 0x159a55e5000c7812 */
/* 0x040fe200078e3cff */
/*0140*/ STG.E.64 [R14.64+0x28], RZ ; /* 0x000028ff0e007986 */
/* 0x0001e2000c101b04 */
/*0150*/ IADD3 R7, R0, 0x583f19, RZ ; /* 0x00583f1900077810 */
/* 0x000fc60007ffe0ff */
/*0160*/ STG.E.64 [R14.64], R2 ; /* 0x000000020e007986 */
/* 0x0001e8000c101b04 */
/*0170*/ STG.E.64 [R14.64+0x8], R12 ; /* 0x0000080c0e007986 */
/* 0x0001e8000c101b04 */
/*0180*/ STG.E.64 [R14.64+0x10], R6 ; /* 0x000010060e007986 */
/* 0x0001e4000c101b04 */
/*0190*/ SHF.R.U32.HI R2, RZ, 0x2, R3 ; /* 0x00000002ff027819 */
/* 0x001fe20000011603 */
/*01a0*/ IMAD.SHL.U32 R6, R7, 0x10, RZ ; /* 0x0000001007067824 */
/* 0x000fe200078e00ff */
/*01b0*/ SHF.R.U32.HI R13, RZ, 0x2, R12 ; /* 0x00000002ff0d7819 */
/* 0x000fe2000001160c */
/*01c0*/ BSSY B0, 0x780 ; /* 0x000005b000007945 */
/* 0x000fe20003800000 */
/*01d0*/ LOP3.LUT R2, R2, R3, RZ, 0x3c, !PT ; /* 0x0000000302027212 */
/* 0x000fc400078e3cff */
/*01e0*/ LOP3.LUT R12, R13, R12, RZ, 0x3c, !PT ; /* 0x0000000c0d0c7212 */
/* 0x000fe400078e3cff */
/*01f0*/ SHF.R.U32.HI R17, RZ, 0x2, R8 ; /* 0x00000002ff117819 */
/* 0x000fe20000011608 */
/*0200*/ IMAD.SHL.U32 R3, R2, 0x2, RZ ; /* 0x0000000202037824 */
/* 0x000fe200078e00ff */
/*0210*/ SHF.R.U32.HI R18, RZ, 0x2, R7 ; /* 0x00000002ff127819 */
/* 0x000fe40000011607 */
/*0220*/ LOP3.LUT R8, R17, R8, RZ, 0x3c, !PT ; /* 0x0000000811087212 */
/* 0x000fe400078e3cff */
/*0230*/ LOP3.LUT R3, R7, R3, R2, 0x96, !PT ; /* 0x0000000307037212 */
/* 0x000fe200078e9602 */
/*0240*/ IMAD.SHL.U32 R2, R12, 0x2, RZ ; /* 0x000000020c027824 */
/* 0x000fe200078e00ff */
/*0250*/ LOP3.LUT R7, R18, R7, RZ, 0x3c, !PT ; /* 0x0000000712077212 */
/* 0x000fc400078e3cff */
/*0260*/ LOP3.LUT R3, R3, R6, RZ, 0x3c, !PT ; /* 0x0000000603037212 */
/* 0x000fe400078e3cff */
/*0270*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fe40007ffe0ff */
/*0280*/ LOP3.LUT R15, R3.reuse, R2, R12, 0x96, !PT ; /* 0x00000002030f7212 */
/* 0x040fe200078e960c */
/*0290*/ IMAD.SHL.U32 R12, R3, 0x10, RZ ; /* 0x00000010030c7824 */
/* 0x000fe200078e00ff */
/*02a0*/ SHF.R.U32.HI R2, RZ, 0x2, R11 ; /* 0x00000002ff027819 */
/* 0x000fe4000001160b */
/*02b0*/ IADD3 R6, R0, -0x26039c23, R3 ; /* 0xd9fc63dd00067810 */
/* 0x000fe40007ffe003 */
/*02c0*/ LOP3.LUT R11, R2, R11, RZ, 0x3c, !PT ; /* 0x0000000b020b7212 */
/* 0x000fe200078e3cff */
/*02d0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x2f800000 ; /* 0x2f800000ff027424 */
/* 0x000fe200078e00ff */
/*02e0*/ LOP3.LUT R12, R15, R12, RZ, 0x3c, !PT ; /* 0x0000000c0f0c7212 */
/* 0x000fe200078e3cff */
/*02f0*/ I2F.U32 R13, R6 ; /* 0x00000006000d7306 */
/* 0x000e220000201000 */
/*0300*/ ISETP.NE.AND P0, PT, R9, 0x800, PT ; /* 0x000008000900780c */
/* 0x000fe20003f05270 */
/*0310*/ IMAD.SHL.U32 R14, R11, 0x2, RZ ; /* 0x000000020b0e7824 */
/* 0x000fe200078e00ff */
/*0320*/ IADD3 R10, R0, -0x25fe145e, R12 ; /* 0xda01eba2000a7810 */
/* 0x000fc80007ffe00c */
/*0330*/ LOP3.LUT R14, R12.reuse, R14, R11, 0x96, !PT ; /* 0x0000000e0c0e7212 */
/* 0x040fe200078e960b */
/*0340*/ IMAD.SHL.U32 R11, R12, 0x10, RZ ; /* 0x000000100c0b7824 */
/* 0x000fe200078e00ff */
/*0350*/ I2F.U32 R15, R10 ; /* 0x0000000a000f7306 */
/* 0x0002a80000201000 */
/*0360*/ LOP3.LUT R11, R14, R11, RZ, 0x3c, !PT ; /* 0x0000000b0e0b7212 */
/* 0x000fe200078e3cff */
/*0370*/ IMAD.SHL.U32 R14, R8, 0x2, RZ ; /* 0x00000002080e7824 */
/* 0x000fe400078e00ff */
/*0380*/ FFMA R13, R13, R2, 1.1641532182693481445e-10 ; /* 0x2f0000000d0d7423 */
/* 0x001fe20000000002 */
/*0390*/ IADD3 R6, R0, -0x25f88c99, R11 ; /* 0xda07736700067810 */
/* 0x000fe20007ffe00b */
/*03a0*/ IMAD.SHL.U32 R10, R7, 0x2, RZ ; /* 0x00000002070a7824 */
/* 0x002fe200078e00ff */
/*03b0*/ LOP3.LUT R19, R11.reuse, R14, R8, 0x96, !PT ; /* 0x0000000e0b137212 */
/* 0x040fe200078e9608 */
/*03c0*/ IMAD.SHL.U32 R8, R11, 0x10, RZ ; /* 0x000000100b087824 */
/* 0x000fe200078e00ff */
/*03d0*/ I2F.U32 R21, R6 ; /* 0x0000000600157306 */
/* 0x000e280000201000 */
/*03e0*/ LOP3.LUT R8, R19, R8, RZ, 0x3c, !PT ; /* 0x0000000813087212 */
/* 0x000fe200078e3cff */
/*03f0*/ FFMA R18, R15, R2, 1.1641532182693481445e-10 ; /* 0x2f0000000f127423 */
/* 0x004fc60000000002 */
/*0400*/ LOP3.LUT R14, R8.reuse, R10, R7, 0x96, !PT ; /* 0x0000000a080e7212 */
/* 0x040fe200078e9607 */
/*0410*/ IMAD.SHL.U32 R7, R8, 0x10, RZ ; /* 0x0000001008077824 */
/* 0x000fe200078e00ff */
/*0420*/ IADD3 R10, R0, -0x25f304d4, R8 ; /* 0xda0cfb2c000a7810 */
/* 0x000fe20007ffe008 */
/*0430*/ F2F.F64.F32 R16, R13 ; /* 0x0000000d00107310 */
/* 0x0002a60000201800 */
/*0440*/ LOP3.LUT R7, R14, R7, RZ, 0x3c, !PT ; /* 0x000000070e077212 */
/* 0x000fe200078e3cff */
/*0450*/ FFMA R6, R21, R2, 1.1641532182693481445e-10 ; /* 0x2f00000015067423 */
/* 0x001fc60000000002 */
/*0460*/ IADD3 R22, R0, -0x25ed7d0f, R7 ; /* 0xda1282f100167810 */
/* 0x000fe20007ffe007 */
/*0470*/ I2F.U32 R13, R10 ; /* 0x0000000a000d7306 */
/* 0x002e300000201000 */
/*0480*/ I2F.U32 R23, R22 ; /* 0x0000001600177306 */
/* 0x0002e20000201000 */
/*0490*/ DFMA R20, -R16, R16, RZ ; /* 0x000000101014722b */
/* 0x00450e00000001ff */
/*04a0*/ F2F.F64.F32 R18, R18 ; /* 0x0000001200127310 */
/* 0x000f220000201800 */
/*04b0*/ FFMA R13, R13, R2, 1.1641532182693481445e-10 ; /* 0x2f0000000d0d7423 */
/* 0x001fe40000000002 */
/*04c0*/ IMAD.MOV.U32 R22, RZ, RZ, 0x69ce2bdf ; /* 0x69ce2bdfff167424 */
/* 0x002fca00078e00ff */
/*04d0*/ F2F.F64.F32 R14, R6 ; /* 0x00000006000e7310 */
/* 0x000e220000201800 */
/*04e0*/ FFMA R2, R23, R2, 1.1641532182693481445e-10 ; /* 0x2f00000017027423 */
/* 0x008fe40000000002 */
/*04f0*/ IMAD.MOV.U32 R23, RZ, RZ, 0x3e5ade15 ; /* 0x3e5ade15ff177424 */
/* 0x000fca00078e00ff */
/*0500*/ F2F.F64.F32 R16, R13 ; /* 0x0000000d00107310 */
/* 0x004e620000201800 */
/*0510*/ DFMA R20, -R18, R18, R20 ; /* 0x000000121214722b */
/* 0x01040e0000000114 */
/*0520*/ F2F.F64.F32 R18, R2 ; /* 0x0000000200127310 */
/* 0x004ea20000201800 */
/*0530*/ DFMA R20, -R14, R14, R20 ; /* 0x0000000e0e14722b */
/* 0x001e4c0000000114 */
/*0540*/ DFMA R14, -R16, R16, R20 ; /* 0x00000010100e722b */
/* 0x0020a40000000114 */
/*0550*/ IMAD.MOV.U32 R16, RZ, RZ, 0x652b82fe ; /* 0x652b82feff107424 */
/* 0x001fe400078e00ff */
/*0560*/ IMAD.MOV.U32 R17, RZ, RZ, 0x3ff71547 ; /* 0x3ff71547ff117424 */
/* 0x000fe400078e00ff */
/*0570*/ DFMA R14, -R18, R18, R14 ; /* 0x00000012120e722b */
/* 0x004e0c000000010e */
/*0580*/ DFMA R16, R14, R16, 6.75539944105574400000e+15 ; /* 0x433800000e10742b */
/* 0x001e080000000010 */
/*0590*/ FSETP.GEU.AND P1, PT, |R15|, 4.1917929649353027344, PT ; /* 0x4086232b0f00780b */
/* 0x000fe40003f2e200 */
/*05a0*/ DADD R18, R16, -6.75539944105574400000e+15 ; /* 0xc338000010127429 */
/* 0x001e0c0000000000 */
/*05b0*/ DFMA R20, R18, c[0x2][0x0], R14 ; /* 0x0080000012147a2b */
/* 0x001e0c000000000e */
/*05c0*/ DFMA R18, R18, c[0x2][0x8], R20 ; /* 0x0080020012127a2b */
/* 0x001e0c0000000014 */
/*05d0*/ DFMA R20, R18, R22, c[0x2][0x10] ; /* 0x008004001214762b */
/* 0x001e0c0000000016 */
/*05e0*/ DFMA R20, R18, R20, c[0x2][0x18] ; /* 0x008006001214762b */
/* 0x001e0c0000000014 */
/*05f0*/ DFMA R20, R18, R20, c[0x2][0x20] ; /* 0x008008001214762b */
/* 0x001e0c0000000014 */
/*0600*/ DFMA R20, R18, R20, c[0x2][0x28] ; /* 0x00800a001214762b */
/* 0x001e0c0000000014 */
/*0610*/ DFMA R20, R18, R20, c[0x2][0x30] ; /* 0x00800c001214762b */
/* 0x001e0c0000000014 */
/*0620*/ DFMA R20, R18, R20, c[0x2][0x38] ; /* 0x00800e001214762b */
/* 0x001e0c0000000014 */
/*0630*/ DFMA R20, R18, R20, c[0x2][0x40] ; /* 0x008010001214762b */
/* 0x001e0c0000000014 */
/*0640*/ DFMA R20, R18, R20, c[0x2][0x48] ; /* 0x008012001214762b */
/* 0x001e0c0000000014 */
/*0650*/ DFMA R20, R18, R20, c[0x2][0x50] ; /* 0x008014001214762b */
/* 0x001e0c0000000014 */
/*0660*/ DFMA R20, R18, R20, 1 ; /* 0x3ff000001214742b */
/* 0x001e0c0000000014 */
/*0670*/ DFMA R20, R18, R20, 1 ; /* 0x3ff000001214742b */
/* 0x001e140000000014 */
/*0680*/ IMAD R19, R16, 0x100000, R21 ; /* 0x0010000010137824 */
/* 0x001fe400078e0215 */
/*0690*/ IMAD.MOV.U32 R18, RZ, RZ, R20 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0014 */
/*06a0*/ @!P1 BRA 0x770 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*06b0*/ FSETP.GEU.AND P2, PT, |R15|, 4.2275390625, PT ; /* 0x408748000f00780b */
/* 0x000fe20003f4e200 */
/*06c0*/ DADD R18, R14, +INF ; /* 0x7ff000000e127429 */
/* 0x000fc80000000000 */
/*06d0*/ DSETP.GEU.AND P1, PT, R14, RZ, PT ; /* 0x000000ff0e00722a */
/* 0x000e0c0003f2e000 */
/*06e0*/ FSEL R18, R18, RZ, P1 ; /* 0x000000ff12127208 */
/* 0x001fe40000800000 */
/*06f0*/ @!P2 LEA.HI R2, R16, R16, RZ, 0x1 ; /* 0x000000101002a211 */
/* 0x000fe400078f08ff */
/*0700*/ FSEL R19, R19, RZ, P1 ; /* 0x000000ff13137208 */
/* 0x000fe40000800000 */
/*0710*/ @!P2 SHF.R.S32.HI R13, RZ, 0x1, R2 ; /* 0x00000001ff0da819 */
/* 0x000fca0000011402 */
/*0720*/ @!P2 IMAD.IADD R14, R16, 0x1, -R13 ; /* 0x00000001100ea824 */
/* 0x000fe400078e0a0d */
/*0730*/ @!P2 IMAD R21, R13, 0x100000, R21 ; /* 0x001000000d15a824 */
/* 0x000fc600078e0215 */
/*0740*/ @!P2 LEA R15, R14, 0x3ff00000, 0x14 ; /* 0x3ff000000e0fa811 */
/* 0x000fe200078ea0ff */
/*0750*/ @!P2 IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0ea224 */
/* 0x000fcc00078e00ff */
/*0760*/ @!P2 DMUL R18, R20, R14 ; /* 0x0000000e1412a228 */
/* 0x00004c0000000000 */
/*0770*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0780*/ DFMA R4, R18, 0.00048828125, R4 ; /* 0x3f4000001204782b */
/* 0x0022a20000000004 */
/*0790*/ IADD3 R0, R0, 0x1ba6d9, RZ ; /* 0x001ba6d900007810 */
/* 0x000fe20007ffe0ff */
/*07a0*/ @P0 BRA 0x190 ; /* 0xfffff9e000000947 */
/* 0x006fea000383ffff */
/*07b0*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*07c0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4182bed5 ; /* 0x4182bed5ff067424 */
/* 0x000fe400078e00ff */
/*07d0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x30 ; /* 0x00000030ff0d7424 */
/* 0x000fe200078e00ff */
/*07e0*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e620000002500 */
/*07f0*/ IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e000c */
/*0800*/ IMAD R0, R9, c[0x0][0x0], R0 ; /* 0x0000000009007a24 */
/* 0x002fc800078e0200 */
/*0810*/ IMAD.WIDE.U32 R12, R0.reuse, R13, c[0x0][0x168] ; /* 0x00005a00000c7625 */
/* 0x040fe200078e000d */
/*0820*/ LOP3.LUT R9, R0.reuse, 0xaad26b49, RZ, 0x3c, !PT ; /* 0xaad26b4900097812 */
/* 0x040fe400078e3cff */
/*0830*/ LEA R2, P0, R0.reuse, c[0x0][0x160], 0x3 ; /* 0x0000580000027a11 */
/* 0x040fe400078018ff */
/*0840*/ STG.E.64 [R12.64+0x8], R10 ; /* 0x0000080a0c007986 */
/* 0x000fe2000c101b04 */
/*0850*/ IMAD R6, R9, R6, -0x48d25be8 ; /* 0xb72da41809067424 */
/* 0x000fe400078e0206 */
/*0860*/ IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0007 */
/*0870*/ IMAD.MOV.U32 R7, RZ, RZ, R3 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0003 */
/*0880*/ LEA.HI.X R3, R0, c[0x0][0x164], RZ, 0x3, P0 ; /* 0x0000590000037a11 */
/* 0x000fc400000f1cff */
/*0890*/ STG.E.64 [R12.64+0x10], R8 ; /* 0x000010080c007986 */
/* 0x000fe8000c101b04 */
/*08a0*/ STG.E.64 [R12.64], R6 ; /* 0x000000060c007986 */
/* 0x000fe8000c101b04 */
/*08b0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101b04 */
/*08c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08d0*/ BRA 0x8d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <time.h>
#include <sys/time.h>
#include <curand_kernel.h>
#define D 5
#define TRIALS_PER_THREAD 2048
#define BLOCKS 256
#define THREADS 256
__global__ void mc_int(double *res, curandState *states) {
unsigned int tid = threadIdx.x + blockDim.x*blockIdx.x;
double integral = 0.0;
double X[D];
curand_init(tid, 0, 0, &states[tid]);
for (int i = 0; i < TRIALS_PER_THREAD; i++) {
for (int j = 0; j < D; j++) {
X[j] = curand_uniform(&states[tid]);
}
double t = 0.0;
for (int j = 0; j < D; j++) {
t -= X[j] * X[j];
}
integral += exp(t) / TRIALS_PER_THREAD;
}
res[tid] = integral;
}
int main(int argc, char **argv) {
double host[BLOCKS * THREADS];
double *dev;
curandState *states;
double integral = 0.0;
double vol = 1.0;
clock_t ts = clock();
struct timeval start, end;
gettimeofday(&start, NULL);
cudaMalloc((void**) &dev, BLOCKS * THREADS * sizeof(double));
cudaMalloc((void**)&states,
BLOCKS * THREADS * sizeof(curandState));
mc_int<<<BLOCKS, THREADS>>>(dev, states);
cudaMemcpy(host, dev, BLOCKS * THREADS * sizeof(double),
cudaMemcpyDeviceToHost);
for(int i = 0; i < BLOCKS * THREADS; i++) {
integral += host[i];
}
integral /= BLOCKS * THREADS;
for (int j = 0; j < D; j++) {
vol *= 1.0;
}
integral *= vol;
gettimeofday(&end, NULL);
double elapsed = ((end.tv_sec - start.tv_sec) * 1000000u +
end.tv_usec - start.tv_usec) / 1.e6;
ts = clock() - ts;
printf("%ld clocks (%lf seconds)\n", ts, elapsed);
printf("integral is: %lf\n", integral);
cudaFree(dev);
cudaFree(states);
} | .file "tmpxft_001a7f4c_00000000-6_mc.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2274:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2274:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z6mc_intPdP17curandStateXORWOWPdP17curandStateXORWOW
.type _Z45__device_stub__Z6mc_intPdP17curandStateXORWOWPdP17curandStateXORWOW, @function
_Z45__device_stub__Z6mc_intPdP17curandStateXORWOWPdP17curandStateXORWOW:
.LFB2296:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6mc_intPdP17curandStateXORWOW(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2296:
.size _Z45__device_stub__Z6mc_intPdP17curandStateXORWOWPdP17curandStateXORWOW, .-_Z45__device_stub__Z6mc_intPdP17curandStateXORWOWPdP17curandStateXORWOW
.globl _Z6mc_intPdP17curandStateXORWOW
.type _Z6mc_intPdP17curandStateXORWOW, @function
_Z6mc_intPdP17curandStateXORWOW:
.LFB2297:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z6mc_intPdP17curandStateXORWOWPdP17curandStateXORWOW
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2297:
.size _Z6mc_intPdP17curandStateXORWOW, .-_Z6mc_intPdP17curandStateXORWOW
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "%ld clocks (%lf seconds)\n"
.LC4:
.string "integral is: %lf\n"
.text
.globl main
.type main, @function
main:
.LFB2271:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
leaq -524288(%rsp), %r11
.cfi_def_cfa 11, 524312
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $104, %rsp
.cfi_def_cfa_offset 524416
movq %fs:40, %rax
movq %rax, 524376(%rsp)
xorl %eax, %eax
call clock@PLT
movq %rax, %rbp
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
leaq 16(%rsp), %rdi
movl $524288, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $3145728, %esi
call cudaMalloc@PLT
movl $256, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $256, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
leaq 80(%rsp), %rbx
movl $2, %ecx
movl $524288, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rax
leaq 524368(%rsp), %rdx
pxor %xmm0, %xmm0
.L13:
addsd (%rax), %xmm0
addq $8, %rax
cmpq %rdx, %rax
jne .L13
mulsd .LC1(%rip), %xmm0
movq %xmm0, %rbx
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 64(%rsp), %rax
subq 48(%rsp), %rax
imulq $1000000, %rax, %rax
addq 72(%rsp), %rax
subq 56(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC2(%rip), %xmm0
movsd %xmm0, 8(%rsp)
call clock@PLT
subq %rbp, %rax
movq %rax, %rdx
movsd 8(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 524376(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $524392, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z45__device_stub__Z6mc_intPdP17curandStateXORWOWPdP17curandStateXORWOW
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2271:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "_Z6mc_intPdP17curandStateXORWOW"
.section .rodata.str1.1
.LC6:
.string "precalc_xorwow_matrix"
.LC7:
.string "precalc_xorwow_offset_matrix"
.LC8:
.string "mrg32k3aM1"
.LC9:
.string "mrg32k3aM2"
.LC10:
.string "mrg32k3aM1SubSeq"
.LC11:
.string "mrg32k3aM2SubSeq"
.LC12:
.string "mrg32k3aM1Seq"
.LC13:
.string "mrg32k3aM2Seq"
.LC14:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2299:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z6mc_intPdP17curandStateXORWOW(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2299:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1055916032
.align 8
.LC2:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <time.h>
#include <sys/time.h>
#include <curand_kernel.h>
#define D 5
#define TRIALS_PER_THREAD 2048
#define BLOCKS 256
#define THREADS 256
__global__ void mc_int(double *res, curandState *states) {
unsigned int tid = threadIdx.x + blockDim.x*blockIdx.x;
double integral = 0.0;
double X[D];
curand_init(tid, 0, 0, &states[tid]);
for (int i = 0; i < TRIALS_PER_THREAD; i++) {
for (int j = 0; j < D; j++) {
X[j] = curand_uniform(&states[tid]);
}
double t = 0.0;
for (int j = 0; j < D; j++) {
t -= X[j] * X[j];
}
integral += exp(t) / TRIALS_PER_THREAD;
}
res[tid] = integral;
}
int main(int argc, char **argv) {
double host[BLOCKS * THREADS];
double *dev;
curandState *states;
double integral = 0.0;
double vol = 1.0;
clock_t ts = clock();
struct timeval start, end;
gettimeofday(&start, NULL);
cudaMalloc((void**) &dev, BLOCKS * THREADS * sizeof(double));
cudaMalloc((void**)&states,
BLOCKS * THREADS * sizeof(curandState));
mc_int<<<BLOCKS, THREADS>>>(dev, states);
cudaMemcpy(host, dev, BLOCKS * THREADS * sizeof(double),
cudaMemcpyDeviceToHost);
for(int i = 0; i < BLOCKS * THREADS; i++) {
integral += host[i];
}
integral /= BLOCKS * THREADS;
for (int j = 0; j < D; j++) {
vol *= 1.0;
}
integral *= vol;
gettimeofday(&end, NULL);
double elapsed = ((end.tv_sec - start.tv_sec) * 1000000u +
end.tv_usec - start.tv_usec) / 1.e6;
ts = clock() - ts;
printf("%ld clocks (%lf seconds)\n", ts, elapsed);
printf("integral is: %lf\n", integral);
cudaFree(dev);
cudaFree(states);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <time.h>
#include <sys/time.h>
#include <hiprand/hiprand_kernel.h>
#define D 5
#define TRIALS_PER_THREAD 2048
#define BLOCKS 256
#define THREADS 256
__global__ void mc_int(double *res, hiprandState *states) {
unsigned int tid = threadIdx.x + blockDim.x*blockIdx.x;
double integral = 0.0;
double X[D];
hiprand_init(tid, 0, 0, &states[tid]);
for (int i = 0; i < TRIALS_PER_THREAD; i++) {
for (int j = 0; j < D; j++) {
X[j] = hiprand_uniform(&states[tid]);
}
double t = 0.0;
for (int j = 0; j < D; j++) {
t -= X[j] * X[j];
}
integral += exp(t) / TRIALS_PER_THREAD;
}
res[tid] = integral;
}
int main(int argc, char **argv) {
double host[BLOCKS * THREADS];
double *dev;
hiprandState *states;
double integral = 0.0;
double vol = 1.0;
clock_t ts = clock();
struct timeval start, end;
gettimeofday(&start, NULL);
hipMalloc((void**) &dev, BLOCKS * THREADS * sizeof(double));
hipMalloc((void**)&states,
BLOCKS * THREADS * sizeof(hiprandState));
mc_int<<<BLOCKS, THREADS>>>(dev, states);
hipMemcpy(host, dev, BLOCKS * THREADS * sizeof(double),
hipMemcpyDeviceToHost);
for(int i = 0; i < BLOCKS * THREADS; i++) {
integral += host[i];
}
integral /= BLOCKS * THREADS;
for (int j = 0; j < D; j++) {
vol *= 1.0;
}
integral *= vol;
gettimeofday(&end, NULL);
double elapsed = ((end.tv_sec - start.tv_sec) * 1000000u +
end.tv_usec - start.tv_usec) / 1.e6;
ts = clock() - ts;
printf("%ld clocks (%lf seconds)\n", ts, elapsed);
printf("integral is: %lf\n", integral);
hipFree(dev);
hipFree(states);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <time.h>
#include <sys/time.h>
#include <hiprand/hiprand_kernel.h>
#define D 5
#define TRIALS_PER_THREAD 2048
#define BLOCKS 256
#define THREADS 256
__global__ void mc_int(double *res, hiprandState *states) {
unsigned int tid = threadIdx.x + blockDim.x*blockIdx.x;
double integral = 0.0;
double X[D];
hiprand_init(tid, 0, 0, &states[tid]);
for (int i = 0; i < TRIALS_PER_THREAD; i++) {
for (int j = 0; j < D; j++) {
X[j] = hiprand_uniform(&states[tid]);
}
double t = 0.0;
for (int j = 0; j < D; j++) {
t -= X[j] * X[j];
}
integral += exp(t) / TRIALS_PER_THREAD;
}
res[tid] = integral;
}
int main(int argc, char **argv) {
double host[BLOCKS * THREADS];
double *dev;
hiprandState *states;
double integral = 0.0;
double vol = 1.0;
clock_t ts = clock();
struct timeval start, end;
gettimeofday(&start, NULL);
hipMalloc((void**) &dev, BLOCKS * THREADS * sizeof(double));
hipMalloc((void**)&states,
BLOCKS * THREADS * sizeof(hiprandState));
mc_int<<<BLOCKS, THREADS>>>(dev, states);
hipMemcpy(host, dev, BLOCKS * THREADS * sizeof(double),
hipMemcpyDeviceToHost);
for(int i = 0; i < BLOCKS * THREADS; i++) {
integral += host[i];
}
integral /= BLOCKS * THREADS;
for (int j = 0; j < D; j++) {
vol *= 1.0;
}
integral *= vol;
gettimeofday(&end, NULL);
double elapsed = ((end.tv_sec - start.tv_sec) * 1000000u +
end.tv_usec - start.tv_usec) / 1.e6;
ts = clock() - ts;
printf("%ld clocks (%lf seconds)\n", ts, elapsed);
printf("integral is: %lf\n", integral);
hipFree(dev);
hipFree(states);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6mc_intPdP12hiprandState
.globl _Z6mc_intPdP12hiprandState
.p2align 8
.type _Z6mc_intPdP12hiprandState,@function
_Z6mc_intPdP12hiprandState:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
v_dual_mov_b32 v21, 0 :: v_dual_mov_b32 v18, 0xa96f9d04
v_mov_b32_e32 v23, 0
v_dual_mov_b32 v19, 0x8f14727c :: v_dual_mov_b32 v24, 0
s_delay_alu instid0(VALU_DEP_3)
v_mov_b32_e32 v22, v21
s_mov_b32 s33, 0
s_mov_b32 s7, 0x3ff71547
s_mov_b32 s6, 0x652b82fe
s_mov_b32 s9, 0xbfe62e42
s_mov_b32 s8, 0xfefa39ef
s_mov_b32 s11, 0xbc7abc9e
s_mov_b32 s10, 0x3b39803f
s_mov_b32 s13, 0x3e928af3
s_mov_b32 s12, 0xfca7ab0c
s_mov_b32 s17, 0x3e5ade15
s_mov_b32 s16, 0x6a5dcb37
s_mov_b32 s14, 0x623fde64
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_mov_b32 s19, 0x3efa0199
v_mad_u64_u32 v[25:26], null, s15, s4, v[0:1]
s_mov_b32 s15, 0x3ec71dee
s_mov_b32 s18, 0x7c89e6b0
s_mov_b32 s21, 0x3f2a01a0
s_mov_b32 s20, 0x14761f6e
s_mov_b32 s23, 0x3f56c16c
s_mov_b32 s22, 0x1852b7b0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_xor_b32_e32 v0, 0x2c7f967f, v25
v_mad_u64_u32 v[27:28], null, v25, 48, s[2:3]
s_mov_b32 s25, 0x3f811111
s_mov_b32 s24, 0x11122322
v_mul_lo_u32 v0, v0, 0x493c4aa1
v_mov_b32_e32 v26, 0
s_mov_b32 s27, 0x3fa55555
s_mov_b32 s26, 0x555502a1
s_mov_b32 s29, 0x3fc55555
s_mov_b32 s28, 0x55555511
s_mov_b32 s31, 0x3fe00000
s_mov_b32 s30, 11
v_add_nc_u32_e32 v29, 0x583f19, v0
v_add_nc_u32_e32 v16, 0x75bcd15, v0
v_add_nc_u32_e32 v20, 0x8ac25218, v0
v_xor_b32_e32 v17, 0x159a55e5, v0
v_add_nc_u32_e32 v30, 0x8ac7d9dd, v0
s_clause 0x2
global_store_b96 v[27:28], v[20:22], off
global_store_b128 v[27:28], v[16:19], off offset:24
global_store_b32 v[27:28], v29, off offset:40
.LBB0_1:
v_dual_mov_b32 v10, v30 :: v_dual_mov_b32 v13, v16
v_dual_mov_b32 v11, v17 :: v_dual_mov_b32 v12, v18
s_mov_b64 s[34:35], 0
.LBB0_2:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshrrev_b32_e32 v14, 2, v13
v_dual_mov_b32 v18, v19 :: v_dual_mov_b32 v19, v29
s_cmp_eq_u32 s34, 4
v_mov_b32_e32 v17, v12
v_xor_b32_e32 v13, v14, v13
s_cselect_b32 vcc_lo, -1, 0
v_lshlrev_b32_e32 v14, 4, v19
s_cmp_eq_u32 s34, 3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v11 :: v_dual_lshlrev_b32 v15, 1, v13
s_cselect_b32 s2, -1, 0
s_cmp_eq_u32 s34, 2
s_cselect_b32 s3, -1, 0
v_xor_b32_e32 v14, v15, v14
s_cmp_eq_u32 s34, 1
s_cselect_b32 s4, -1, 0
s_cmp_eq_u32 s34, 0
s_delay_alu instid0(VALU_DEP_1)
v_xor3_b32 v29, v14, v13, v19
s_cselect_b32 s5, -1, 0
s_add_u32 s34, s34, 1
s_addc_u32 s35, s35, 0
s_cmp_lg_u32 s34, 5
v_add_nc_u32_e32 v13, v10, v29
v_add_nc_u32_e32 v10, 0x587c5, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v13, v13
v_fmaak_f32 v13, 0x2f800000, v13, 0x2f800000
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cvt_f64_f32_e32 v[14:15], v13
v_mov_b32_e32 v13, v11
v_dual_mov_b32 v11, v12 :: v_dual_mov_b32 v12, v18
v_dual_cndmask_b32 v9, v9, v15 :: v_dual_cndmask_b32 v8, v8, v14
v_cndmask_b32_e64 v7, v7, v15, s2
v_cndmask_b32_e64 v6, v6, v14, s2
v_cndmask_b32_e64 v5, v5, v15, s3
v_cndmask_b32_e64 v4, v4, v14, s3
v_cndmask_b32_e64 v3, v3, v15, s4
v_cndmask_b32_e64 v2, v2, v14, s4
v_cndmask_b32_e64 v1, v1, v15, s5
v_cndmask_b32_e64 v0, v0, v14, s5
s_cbranch_scc1 .LBB0_2
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_mov_b64 s[2:3], 0
.p2align 6
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 1
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s2, 2
v_dual_cndmask_b32 v12, v1, v3 :: v_dual_cndmask_b32 v13, v0, v2
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s2, 3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v12, v12, v5 :: v_dual_cndmask_b32 v13, v13, v4
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s2, 4
v_cndmask_b32_e32 v12, v12, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v14, v13, v6, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_add_u32 s2, s2, 1
s_addc_u32 s3, s3, 0
v_dual_cndmask_b32 v13, v12, v9 :: v_dual_cndmask_b32 v12, v14, v8
s_cmp_eq_u32 s2, 5
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[10:11], -v[12:13], v[12:13], v[10:11]
s_cbranch_scc0 .LBB0_4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_mul_f64 v[12:13], v[10:11], s[6:7]
v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[10:11]
v_cmp_ngt_f64_e64 s2, 0xc090cc00, v[10:11]
v_add_nc_u32_e32 v30, 0x1ba6d9, v30
s_add_i32 s33, s33, 1
v_rndne_f64_e32 v[12:13], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[14:15], v[12:13], s[8:9], v[10:11]
v_cvt_i32_f64_e32 v31, v[12:13]
v_fma_f64 v[14:15], v[12:13], s[10:11], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[21:22], v[14:15], s[16:17], s[12:13]
v_fma_f64 v[21:22], v[14:15], v[21:22], s[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[21:22], v[14:15], v[21:22], s[18:19]
v_fma_f64 v[21:22], v[14:15], v[21:22], s[20:21]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[21:22], v[14:15], v[21:22], s[22:23]
v_fma_f64 v[21:22], v[14:15], v[21:22], s[24:25]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[21:22], v[14:15], v[21:22], s[26:27]
v_fma_f64 v[21:22], v[14:15], v[21:22], s[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[21:22], v[14:15], v[21:22], s[30:31]
v_fma_f64 v[21:22], v[14:15], v[21:22], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], v[14:15], v[21:22], 1.0
v_ldexp_f64 v[12:13], v[12:13], v31
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[12:13], v[12:13], -11
v_cndmask_b32_e32 v13, 0x7ff00000, v13, vcc_lo
s_and_b32 vcc_lo, s2, vcc_lo
s_cmpk_eq_i32 s33, 0x800
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v10, 0, v12, vcc_lo
v_cndmask_b32_e64 v11, 0, v13, s2
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[23:24], v[23:24], v[10:11]
s_cbranch_scc0 .LBB0_1
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 3, v[25:26]
v_add_nc_u32_e32 v2, 0xdd36c800, v20
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_clause 0x2
global_store_b32 v[27:28], v29, off offset:40
global_store_b128 v[27:28], v[16:19], off offset:24
global_store_b32 v[27:28], v2, off
global_store_b64 v[0:1], v[23:24], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6mc_intPdP12hiprandState
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 36
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6mc_intPdP12hiprandState, .Lfunc_end0-_Z6mc_intPdP12hiprandState
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6mc_intPdP12hiprandState
.private_segment_fixed_size: 0
.sgpr_count: 38
.sgpr_spill_count: 0
.symbol: _Z6mc_intPdP12hiprandState.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <time.h>
#include <sys/time.h>
#include <hiprand/hiprand_kernel.h>
#define D 5
#define TRIALS_PER_THREAD 2048
#define BLOCKS 256
#define THREADS 256
__global__ void mc_int(double *res, hiprandState *states) {
unsigned int tid = threadIdx.x + blockDim.x*blockIdx.x;
double integral = 0.0;
double X[D];
hiprand_init(tid, 0, 0, &states[tid]);
for (int i = 0; i < TRIALS_PER_THREAD; i++) {
for (int j = 0; j < D; j++) {
X[j] = hiprand_uniform(&states[tid]);
}
double t = 0.0;
for (int j = 0; j < D; j++) {
t -= X[j] * X[j];
}
integral += exp(t) / TRIALS_PER_THREAD;
}
res[tid] = integral;
}
int main(int argc, char **argv) {
double host[BLOCKS * THREADS];
double *dev;
hiprandState *states;
double integral = 0.0;
double vol = 1.0;
clock_t ts = clock();
struct timeval start, end;
gettimeofday(&start, NULL);
hipMalloc((void**) &dev, BLOCKS * THREADS * sizeof(double));
hipMalloc((void**)&states,
BLOCKS * THREADS * sizeof(hiprandState));
mc_int<<<BLOCKS, THREADS>>>(dev, states);
hipMemcpy(host, dev, BLOCKS * THREADS * sizeof(double),
hipMemcpyDeviceToHost);
for(int i = 0; i < BLOCKS * THREADS; i++) {
integral += host[i];
}
integral /= BLOCKS * THREADS;
for (int j = 0; j < D; j++) {
vol *= 1.0;
}
integral *= vol;
gettimeofday(&end, NULL);
double elapsed = ((end.tv_sec - start.tv_sec) * 1000000u +
end.tv_usec - start.tv_usec) / 1.e6;
ts = clock() - ts;
printf("%ld clocks (%lf seconds)\n", ts, elapsed);
printf("integral is: %lf\n", integral);
hipFree(dev);
hipFree(states);
} | .text
.file "mc.hip"
.globl _Z21__device_stub__mc_intPdP12hiprandState # -- Begin function _Z21__device_stub__mc_intPdP12hiprandState
.p2align 4, 0x90
.type _Z21__device_stub__mc_intPdP12hiprandState,@function
_Z21__device_stub__mc_intPdP12hiprandState: # @_Z21__device_stub__mc_intPdP12hiprandState
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6mc_intPdP12hiprandState, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__mc_intPdP12hiprandState, .Lfunc_end0-_Z21__device_stub__mc_intPdP12hiprandState
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3ef0000000000000 # double 1.52587890625E-5
.LCPI1_1:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $524400, %rsp # imm = 0x80070
.cfi_def_cfa_offset 524416
.cfi_offset %rbx, -16
callq clock
movq %rax, %rbx
leaq 96(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq %rsp, %rdi
movl $524288, %esi # imm = 0x80000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $3145728, %esi # imm = 0x300000
callq hipMalloc
movabsq $4294967552, %rdi # imm = 0x100000100
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq (%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6mc_intPdP12hiprandState, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
leaq 112(%rsp), %rdi
movl $524288, %edx # imm = 0x80000
movl $2, %ecx
callq hipMemcpy
xorpd %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
addsd 112(%rsp,%rax,8), %xmm0
incq %rax
cmpq $65536, %rax # imm = 0x10000
jne .LBB1_3
# %bb.4: # %.preheader
mulsd .LCPI1_0(%rip), %xmm0
movsd %xmm0, 40(%rsp) # 8-byte Spill
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 8(%rsp), %rax
subq 96(%rsp), %rax
imulq $1000000, %rax, %rax # imm = 0xF4240
addq 16(%rsp), %rax
subq 104(%rsp), %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI1_1(%rip), %xmm0
movsd %xmm0, 32(%rsp) # 8-byte Spill
callq clock
subq %rbx, %rax
movl $.L.str, %edi
movq %rax, %rsi
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $.L.str.1, %edi
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movq (%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $524400, %rsp # imm = 0x80070
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6mc_intPdP12hiprandState, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6mc_intPdP12hiprandState,@object # @_Z6mc_intPdP12hiprandState
.section .rodata,"a",@progbits
.globl _Z6mc_intPdP12hiprandState
.p2align 3, 0x0
_Z6mc_intPdP12hiprandState:
.quad _Z21__device_stub__mc_intPdP12hiprandState
.size _Z6mc_intPdP12hiprandState, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%ld clocks (%lf seconds)\n"
.size .L.str, 26
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "integral is: %lf\n"
.size .L.str.1, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6mc_intPdP12hiprandState"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__mc_intPdP12hiprandState
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6mc_intPdP12hiprandState
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6mc_intPdP17curandStateXORWOW
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R14, SR_CTAID.X ; /* 0x00000000000e7919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R15, RZ, RZ, 0x30 ; /* 0x00000030ff0f7424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R13, RZ, RZ, -0x75bd8fc ; /* 0xf8a42704ff0d7424 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ IMAD.MOV.U32 R6, RZ, RZ, -0x23270784 ; /* 0xdcd8f87cff067424 */
/* 0x000fe200078e00ff */
/*0070*/ CS2R R4, SRZ ; /* 0x0000000000047805 */
/* 0x000fe2000001ff00 */
/*0080*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe400078e00ff */
/*0090*/ IMAD.MOV.U32 R11, RZ, RZ, -0x75bd8fc ; /* 0xf8a42704ff0b7424 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD.MOV.U32 R8, RZ, RZ, -0x23270784 ; /* 0xdcd8f87cff087424 */
/* 0x000fc400078e00ff */
/*00b0*/ IMAD R14, R14, c[0x0][0x0], R3 ; /* 0x000000000e0e7a24 */
/* 0x001fca00078e0203 */
/*00c0*/ LOP3.LUT R0, R14.reuse, 0xaad26b49, RZ, 0x3c, !PT ; /* 0xaad26b490e007812 */
/* 0x040fe200078e3cff */
/*00d0*/ IMAD.WIDE.U32 R14, R14, R15, c[0x0][0x168] ; /* 0x00005a000e0e7625 */
/* 0x000fc800078e000f */
/*00e0*/ IMAD R0, R0, 0x4182bed5, RZ ; /* 0x4182bed500007824 */
/* 0x000fe200078e02ff */
/*00f0*/ STG.E.64 [R14.64+0x18], RZ ; /* 0x000018ff0e007986 */
/* 0x0001e8000c101b04 */
/*0100*/ IADD3 R3, R0.reuse, 0x75bcd15, RZ ; /* 0x075bcd1500037810 */
/* 0x040fe20007ffe0ff */
/*0110*/ STG.E [R14.64+0x20], RZ ; /* 0x000020ff0e007986 */
/* 0x0001e2000c101904 */
/*0120*/ IADD3 R2, R0.reuse, -0x260923e8, RZ ; /* 0xd9f6dc1800027810 */
/* 0x040fe40007ffe0ff */
/*0130*/ LOP3.LUT R12, R0.reuse, 0x159a55e5, RZ, 0x3c, !PT ; /* 0x159a55e5000c7812 */
/* 0x040fe200078e3cff */
/*0140*/ STG.E.64 [R14.64+0x28], RZ ; /* 0x000028ff0e007986 */
/* 0x0001e2000c101b04 */
/*0150*/ IADD3 R7, R0, 0x583f19, RZ ; /* 0x00583f1900077810 */
/* 0x000fc60007ffe0ff */
/*0160*/ STG.E.64 [R14.64], R2 ; /* 0x000000020e007986 */
/* 0x0001e8000c101b04 */
/*0170*/ STG.E.64 [R14.64+0x8], R12 ; /* 0x0000080c0e007986 */
/* 0x0001e8000c101b04 */
/*0180*/ STG.E.64 [R14.64+0x10], R6 ; /* 0x000010060e007986 */
/* 0x0001e4000c101b04 */
/*0190*/ SHF.R.U32.HI R2, RZ, 0x2, R3 ; /* 0x00000002ff027819 */
/* 0x001fe20000011603 */
/*01a0*/ IMAD.SHL.U32 R6, R7, 0x10, RZ ; /* 0x0000001007067824 */
/* 0x000fe200078e00ff */
/*01b0*/ SHF.R.U32.HI R13, RZ, 0x2, R12 ; /* 0x00000002ff0d7819 */
/* 0x000fe2000001160c */
/*01c0*/ BSSY B0, 0x780 ; /* 0x000005b000007945 */
/* 0x000fe20003800000 */
/*01d0*/ LOP3.LUT R2, R2, R3, RZ, 0x3c, !PT ; /* 0x0000000302027212 */
/* 0x000fc400078e3cff */
/*01e0*/ LOP3.LUT R12, R13, R12, RZ, 0x3c, !PT ; /* 0x0000000c0d0c7212 */
/* 0x000fe400078e3cff */
/*01f0*/ SHF.R.U32.HI R17, RZ, 0x2, R8 ; /* 0x00000002ff117819 */
/* 0x000fe20000011608 */
/*0200*/ IMAD.SHL.U32 R3, R2, 0x2, RZ ; /* 0x0000000202037824 */
/* 0x000fe200078e00ff */
/*0210*/ SHF.R.U32.HI R18, RZ, 0x2, R7 ; /* 0x00000002ff127819 */
/* 0x000fe40000011607 */
/*0220*/ LOP3.LUT R8, R17, R8, RZ, 0x3c, !PT ; /* 0x0000000811087212 */
/* 0x000fe400078e3cff */
/*0230*/ LOP3.LUT R3, R7, R3, R2, 0x96, !PT ; /* 0x0000000307037212 */
/* 0x000fe200078e9602 */
/*0240*/ IMAD.SHL.U32 R2, R12, 0x2, RZ ; /* 0x000000020c027824 */
/* 0x000fe200078e00ff */
/*0250*/ LOP3.LUT R7, R18, R7, RZ, 0x3c, !PT ; /* 0x0000000712077212 */
/* 0x000fc400078e3cff */
/*0260*/ LOP3.LUT R3, R3, R6, RZ, 0x3c, !PT ; /* 0x0000000603037212 */
/* 0x000fe400078e3cff */
/*0270*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fe40007ffe0ff */
/*0280*/ LOP3.LUT R15, R3.reuse, R2, R12, 0x96, !PT ; /* 0x00000002030f7212 */
/* 0x040fe200078e960c */
/*0290*/ IMAD.SHL.U32 R12, R3, 0x10, RZ ; /* 0x00000010030c7824 */
/* 0x000fe200078e00ff */
/*02a0*/ SHF.R.U32.HI R2, RZ, 0x2, R11 ; /* 0x00000002ff027819 */
/* 0x000fe4000001160b */
/*02b0*/ IADD3 R6, R0, -0x26039c23, R3 ; /* 0xd9fc63dd00067810 */
/* 0x000fe40007ffe003 */
/*02c0*/ LOP3.LUT R11, R2, R11, RZ, 0x3c, !PT ; /* 0x0000000b020b7212 */
/* 0x000fe200078e3cff */
/*02d0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x2f800000 ; /* 0x2f800000ff027424 */
/* 0x000fe200078e00ff */
/*02e0*/ LOP3.LUT R12, R15, R12, RZ, 0x3c, !PT ; /* 0x0000000c0f0c7212 */
/* 0x000fe200078e3cff */
/*02f0*/ I2F.U32 R13, R6 ; /* 0x00000006000d7306 */
/* 0x000e220000201000 */
/*0300*/ ISETP.NE.AND P0, PT, R9, 0x800, PT ; /* 0x000008000900780c */
/* 0x000fe20003f05270 */
/*0310*/ IMAD.SHL.U32 R14, R11, 0x2, RZ ; /* 0x000000020b0e7824 */
/* 0x000fe200078e00ff */
/*0320*/ IADD3 R10, R0, -0x25fe145e, R12 ; /* 0xda01eba2000a7810 */
/* 0x000fc80007ffe00c */
/*0330*/ LOP3.LUT R14, R12.reuse, R14, R11, 0x96, !PT ; /* 0x0000000e0c0e7212 */
/* 0x040fe200078e960b */
/*0340*/ IMAD.SHL.U32 R11, R12, 0x10, RZ ; /* 0x000000100c0b7824 */
/* 0x000fe200078e00ff */
/*0350*/ I2F.U32 R15, R10 ; /* 0x0000000a000f7306 */
/* 0x0002a80000201000 */
/*0360*/ LOP3.LUT R11, R14, R11, RZ, 0x3c, !PT ; /* 0x0000000b0e0b7212 */
/* 0x000fe200078e3cff */
/*0370*/ IMAD.SHL.U32 R14, R8, 0x2, RZ ; /* 0x00000002080e7824 */
/* 0x000fe400078e00ff */
/*0380*/ FFMA R13, R13, R2, 1.1641532182693481445e-10 ; /* 0x2f0000000d0d7423 */
/* 0x001fe20000000002 */
/*0390*/ IADD3 R6, R0, -0x25f88c99, R11 ; /* 0xda07736700067810 */
/* 0x000fe20007ffe00b */
/*03a0*/ IMAD.SHL.U32 R10, R7, 0x2, RZ ; /* 0x00000002070a7824 */
/* 0x002fe200078e00ff */
/*03b0*/ LOP3.LUT R19, R11.reuse, R14, R8, 0x96, !PT ; /* 0x0000000e0b137212 */
/* 0x040fe200078e9608 */
/*03c0*/ IMAD.SHL.U32 R8, R11, 0x10, RZ ; /* 0x000000100b087824 */
/* 0x000fe200078e00ff */
/*03d0*/ I2F.U32 R21, R6 ; /* 0x0000000600157306 */
/* 0x000e280000201000 */
/*03e0*/ LOP3.LUT R8, R19, R8, RZ, 0x3c, !PT ; /* 0x0000000813087212 */
/* 0x000fe200078e3cff */
/*03f0*/ FFMA R18, R15, R2, 1.1641532182693481445e-10 ; /* 0x2f0000000f127423 */
/* 0x004fc60000000002 */
/*0400*/ LOP3.LUT R14, R8.reuse, R10, R7, 0x96, !PT ; /* 0x0000000a080e7212 */
/* 0x040fe200078e9607 */
/*0410*/ IMAD.SHL.U32 R7, R8, 0x10, RZ ; /* 0x0000001008077824 */
/* 0x000fe200078e00ff */
/*0420*/ IADD3 R10, R0, -0x25f304d4, R8 ; /* 0xda0cfb2c000a7810 */
/* 0x000fe20007ffe008 */
/*0430*/ F2F.F64.F32 R16, R13 ; /* 0x0000000d00107310 */
/* 0x0002a60000201800 */
/*0440*/ LOP3.LUT R7, R14, R7, RZ, 0x3c, !PT ; /* 0x000000070e077212 */
/* 0x000fe200078e3cff */
/*0450*/ FFMA R6, R21, R2, 1.1641532182693481445e-10 ; /* 0x2f00000015067423 */
/* 0x001fc60000000002 */
/*0460*/ IADD3 R22, R0, -0x25ed7d0f, R7 ; /* 0xda1282f100167810 */
/* 0x000fe20007ffe007 */
/*0470*/ I2F.U32 R13, R10 ; /* 0x0000000a000d7306 */
/* 0x002e300000201000 */
/*0480*/ I2F.U32 R23, R22 ; /* 0x0000001600177306 */
/* 0x0002e20000201000 */
/*0490*/ DFMA R20, -R16, R16, RZ ; /* 0x000000101014722b */
/* 0x00450e00000001ff */
/*04a0*/ F2F.F64.F32 R18, R18 ; /* 0x0000001200127310 */
/* 0x000f220000201800 */
/*04b0*/ FFMA R13, R13, R2, 1.1641532182693481445e-10 ; /* 0x2f0000000d0d7423 */
/* 0x001fe40000000002 */
/*04c0*/ IMAD.MOV.U32 R22, RZ, RZ, 0x69ce2bdf ; /* 0x69ce2bdfff167424 */
/* 0x002fca00078e00ff */
/*04d0*/ F2F.F64.F32 R14, R6 ; /* 0x00000006000e7310 */
/* 0x000e220000201800 */
/*04e0*/ FFMA R2, R23, R2, 1.1641532182693481445e-10 ; /* 0x2f00000017027423 */
/* 0x008fe40000000002 */
/*04f0*/ IMAD.MOV.U32 R23, RZ, RZ, 0x3e5ade15 ; /* 0x3e5ade15ff177424 */
/* 0x000fca00078e00ff */
/*0500*/ F2F.F64.F32 R16, R13 ; /* 0x0000000d00107310 */
/* 0x004e620000201800 */
/*0510*/ DFMA R20, -R18, R18, R20 ; /* 0x000000121214722b */
/* 0x01040e0000000114 */
/*0520*/ F2F.F64.F32 R18, R2 ; /* 0x0000000200127310 */
/* 0x004ea20000201800 */
/*0530*/ DFMA R20, -R14, R14, R20 ; /* 0x0000000e0e14722b */
/* 0x001e4c0000000114 */
/*0540*/ DFMA R14, -R16, R16, R20 ; /* 0x00000010100e722b */
/* 0x0020a40000000114 */
/*0550*/ IMAD.MOV.U32 R16, RZ, RZ, 0x652b82fe ; /* 0x652b82feff107424 */
/* 0x001fe400078e00ff */
/*0560*/ IMAD.MOV.U32 R17, RZ, RZ, 0x3ff71547 ; /* 0x3ff71547ff117424 */
/* 0x000fe400078e00ff */
/*0570*/ DFMA R14, -R18, R18, R14 ; /* 0x00000012120e722b */
/* 0x004e0c000000010e */
/*0580*/ DFMA R16, R14, R16, 6.75539944105574400000e+15 ; /* 0x433800000e10742b */
/* 0x001e080000000010 */
/*0590*/ FSETP.GEU.AND P1, PT, |R15|, 4.1917929649353027344, PT ; /* 0x4086232b0f00780b */
/* 0x000fe40003f2e200 */
/*05a0*/ DADD R18, R16, -6.75539944105574400000e+15 ; /* 0xc338000010127429 */
/* 0x001e0c0000000000 */
/*05b0*/ DFMA R20, R18, c[0x2][0x0], R14 ; /* 0x0080000012147a2b */
/* 0x001e0c000000000e */
/*05c0*/ DFMA R18, R18, c[0x2][0x8], R20 ; /* 0x0080020012127a2b */
/* 0x001e0c0000000014 */
/*05d0*/ DFMA R20, R18, R22, c[0x2][0x10] ; /* 0x008004001214762b */
/* 0x001e0c0000000016 */
/*05e0*/ DFMA R20, R18, R20, c[0x2][0x18] ; /* 0x008006001214762b */
/* 0x001e0c0000000014 */
/*05f0*/ DFMA R20, R18, R20, c[0x2][0x20] ; /* 0x008008001214762b */
/* 0x001e0c0000000014 */
/*0600*/ DFMA R20, R18, R20, c[0x2][0x28] ; /* 0x00800a001214762b */
/* 0x001e0c0000000014 */
/*0610*/ DFMA R20, R18, R20, c[0x2][0x30] ; /* 0x00800c001214762b */
/* 0x001e0c0000000014 */
/*0620*/ DFMA R20, R18, R20, c[0x2][0x38] ; /* 0x00800e001214762b */
/* 0x001e0c0000000014 */
/*0630*/ DFMA R20, R18, R20, c[0x2][0x40] ; /* 0x008010001214762b */
/* 0x001e0c0000000014 */
/*0640*/ DFMA R20, R18, R20, c[0x2][0x48] ; /* 0x008012001214762b */
/* 0x001e0c0000000014 */
/*0650*/ DFMA R20, R18, R20, c[0x2][0x50] ; /* 0x008014001214762b */
/* 0x001e0c0000000014 */
/*0660*/ DFMA R20, R18, R20, 1 ; /* 0x3ff000001214742b */
/* 0x001e0c0000000014 */
/*0670*/ DFMA R20, R18, R20, 1 ; /* 0x3ff000001214742b */
/* 0x001e140000000014 */
/*0680*/ IMAD R19, R16, 0x100000, R21 ; /* 0x0010000010137824 */
/* 0x001fe400078e0215 */
/*0690*/ IMAD.MOV.U32 R18, RZ, RZ, R20 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0014 */
/*06a0*/ @!P1 BRA 0x770 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*06b0*/ FSETP.GEU.AND P2, PT, |R15|, 4.2275390625, PT ; /* 0x408748000f00780b */
/* 0x000fe20003f4e200 */
/*06c0*/ DADD R18, R14, +INF ; /* 0x7ff000000e127429 */
/* 0x000fc80000000000 */
/*06d0*/ DSETP.GEU.AND P1, PT, R14, RZ, PT ; /* 0x000000ff0e00722a */
/* 0x000e0c0003f2e000 */
/*06e0*/ FSEL R18, R18, RZ, P1 ; /* 0x000000ff12127208 */
/* 0x001fe40000800000 */
/*06f0*/ @!P2 LEA.HI R2, R16, R16, RZ, 0x1 ; /* 0x000000101002a211 */
/* 0x000fe400078f08ff */
/*0700*/ FSEL R19, R19, RZ, P1 ; /* 0x000000ff13137208 */
/* 0x000fe40000800000 */
/*0710*/ @!P2 SHF.R.S32.HI R13, RZ, 0x1, R2 ; /* 0x00000001ff0da819 */
/* 0x000fca0000011402 */
/*0720*/ @!P2 IMAD.IADD R14, R16, 0x1, -R13 ; /* 0x00000001100ea824 */
/* 0x000fe400078e0a0d */
/*0730*/ @!P2 IMAD R21, R13, 0x100000, R21 ; /* 0x001000000d15a824 */
/* 0x000fc600078e0215 */
/*0740*/ @!P2 LEA R15, R14, 0x3ff00000, 0x14 ; /* 0x3ff000000e0fa811 */
/* 0x000fe200078ea0ff */
/*0750*/ @!P2 IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0ea224 */
/* 0x000fcc00078e00ff */
/*0760*/ @!P2 DMUL R18, R20, R14 ; /* 0x0000000e1412a228 */
/* 0x00004c0000000000 */
/*0770*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0780*/ DFMA R4, R18, 0.00048828125, R4 ; /* 0x3f4000001204782b */
/* 0x0022a20000000004 */
/*0790*/ IADD3 R0, R0, 0x1ba6d9, RZ ; /* 0x001ba6d900007810 */
/* 0x000fe20007ffe0ff */
/*07a0*/ @P0 BRA 0x190 ; /* 0xfffff9e000000947 */
/* 0x006fea000383ffff */
/*07b0*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*07c0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4182bed5 ; /* 0x4182bed5ff067424 */
/* 0x000fe400078e00ff */
/*07d0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x30 ; /* 0x00000030ff0d7424 */
/* 0x000fe200078e00ff */
/*07e0*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e620000002500 */
/*07f0*/ IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e000c */
/*0800*/ IMAD R0, R9, c[0x0][0x0], R0 ; /* 0x0000000009007a24 */
/* 0x002fc800078e0200 */
/*0810*/ IMAD.WIDE.U32 R12, R0.reuse, R13, c[0x0][0x168] ; /* 0x00005a00000c7625 */
/* 0x040fe200078e000d */
/*0820*/ LOP3.LUT R9, R0.reuse, 0xaad26b49, RZ, 0x3c, !PT ; /* 0xaad26b4900097812 */
/* 0x040fe400078e3cff */
/*0830*/ LEA R2, P0, R0.reuse, c[0x0][0x160], 0x3 ; /* 0x0000580000027a11 */
/* 0x040fe400078018ff */
/*0840*/ STG.E.64 [R12.64+0x8], R10 ; /* 0x0000080a0c007986 */
/* 0x000fe2000c101b04 */
/*0850*/ IMAD R6, R9, R6, -0x48d25be8 ; /* 0xb72da41809067424 */
/* 0x000fe400078e0206 */
/*0860*/ IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0007 */
/*0870*/ IMAD.MOV.U32 R7, RZ, RZ, R3 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0003 */
/*0880*/ LEA.HI.X R3, R0, c[0x0][0x164], RZ, 0x3, P0 ; /* 0x0000590000037a11 */
/* 0x000fc400000f1cff */
/*0890*/ STG.E.64 [R12.64+0x10], R8 ; /* 0x000010080c007986 */
/* 0x000fe8000c101b04 */
/*08a0*/ STG.E.64 [R12.64], R6 ; /* 0x000000060c007986 */
/* 0x000fe8000c101b04 */
/*08b0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101b04 */
/*08c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08d0*/ BRA 0x8d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6mc_intPdP12hiprandState
.globl _Z6mc_intPdP12hiprandState
.p2align 8
.type _Z6mc_intPdP12hiprandState,@function
_Z6mc_intPdP12hiprandState:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
v_dual_mov_b32 v21, 0 :: v_dual_mov_b32 v18, 0xa96f9d04
v_mov_b32_e32 v23, 0
v_dual_mov_b32 v19, 0x8f14727c :: v_dual_mov_b32 v24, 0
s_delay_alu instid0(VALU_DEP_3)
v_mov_b32_e32 v22, v21
s_mov_b32 s33, 0
s_mov_b32 s7, 0x3ff71547
s_mov_b32 s6, 0x652b82fe
s_mov_b32 s9, 0xbfe62e42
s_mov_b32 s8, 0xfefa39ef
s_mov_b32 s11, 0xbc7abc9e
s_mov_b32 s10, 0x3b39803f
s_mov_b32 s13, 0x3e928af3
s_mov_b32 s12, 0xfca7ab0c
s_mov_b32 s17, 0x3e5ade15
s_mov_b32 s16, 0x6a5dcb37
s_mov_b32 s14, 0x623fde64
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_mov_b32 s19, 0x3efa0199
v_mad_u64_u32 v[25:26], null, s15, s4, v[0:1]
s_mov_b32 s15, 0x3ec71dee
s_mov_b32 s18, 0x7c89e6b0
s_mov_b32 s21, 0x3f2a01a0
s_mov_b32 s20, 0x14761f6e
s_mov_b32 s23, 0x3f56c16c
s_mov_b32 s22, 0x1852b7b0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_xor_b32_e32 v0, 0x2c7f967f, v25
v_mad_u64_u32 v[27:28], null, v25, 48, s[2:3]
s_mov_b32 s25, 0x3f811111
s_mov_b32 s24, 0x11122322
v_mul_lo_u32 v0, v0, 0x493c4aa1
v_mov_b32_e32 v26, 0
s_mov_b32 s27, 0x3fa55555
s_mov_b32 s26, 0x555502a1
s_mov_b32 s29, 0x3fc55555
s_mov_b32 s28, 0x55555511
s_mov_b32 s31, 0x3fe00000
s_mov_b32 s30, 11
v_add_nc_u32_e32 v29, 0x583f19, v0
v_add_nc_u32_e32 v16, 0x75bcd15, v0
v_add_nc_u32_e32 v20, 0x8ac25218, v0
v_xor_b32_e32 v17, 0x159a55e5, v0
v_add_nc_u32_e32 v30, 0x8ac7d9dd, v0
s_clause 0x2
global_store_b96 v[27:28], v[20:22], off
global_store_b128 v[27:28], v[16:19], off offset:24
global_store_b32 v[27:28], v29, off offset:40
.LBB0_1:
v_dual_mov_b32 v10, v30 :: v_dual_mov_b32 v13, v16
v_dual_mov_b32 v11, v17 :: v_dual_mov_b32 v12, v18
s_mov_b64 s[34:35], 0
.LBB0_2:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshrrev_b32_e32 v14, 2, v13
v_dual_mov_b32 v18, v19 :: v_dual_mov_b32 v19, v29
s_cmp_eq_u32 s34, 4
v_mov_b32_e32 v17, v12
v_xor_b32_e32 v13, v14, v13
s_cselect_b32 vcc_lo, -1, 0
v_lshlrev_b32_e32 v14, 4, v19
s_cmp_eq_u32 s34, 3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v11 :: v_dual_lshlrev_b32 v15, 1, v13
s_cselect_b32 s2, -1, 0
s_cmp_eq_u32 s34, 2
s_cselect_b32 s3, -1, 0
v_xor_b32_e32 v14, v15, v14
s_cmp_eq_u32 s34, 1
s_cselect_b32 s4, -1, 0
s_cmp_eq_u32 s34, 0
s_delay_alu instid0(VALU_DEP_1)
v_xor3_b32 v29, v14, v13, v19
s_cselect_b32 s5, -1, 0
s_add_u32 s34, s34, 1
s_addc_u32 s35, s35, 0
s_cmp_lg_u32 s34, 5
v_add_nc_u32_e32 v13, v10, v29
v_add_nc_u32_e32 v10, 0x587c5, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v13, v13
v_fmaak_f32 v13, 0x2f800000, v13, 0x2f800000
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cvt_f64_f32_e32 v[14:15], v13
v_mov_b32_e32 v13, v11
v_dual_mov_b32 v11, v12 :: v_dual_mov_b32 v12, v18
v_dual_cndmask_b32 v9, v9, v15 :: v_dual_cndmask_b32 v8, v8, v14
v_cndmask_b32_e64 v7, v7, v15, s2
v_cndmask_b32_e64 v6, v6, v14, s2
v_cndmask_b32_e64 v5, v5, v15, s3
v_cndmask_b32_e64 v4, v4, v14, s3
v_cndmask_b32_e64 v3, v3, v15, s4
v_cndmask_b32_e64 v2, v2, v14, s4
v_cndmask_b32_e64 v1, v1, v15, s5
v_cndmask_b32_e64 v0, v0, v14, s5
s_cbranch_scc1 .LBB0_2
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_mov_b64 s[2:3], 0
.p2align 6
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 1
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s2, 2
v_dual_cndmask_b32 v12, v1, v3 :: v_dual_cndmask_b32 v13, v0, v2
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s2, 3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v12, v12, v5 :: v_dual_cndmask_b32 v13, v13, v4
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s2, 4
v_cndmask_b32_e32 v12, v12, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v14, v13, v6, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_add_u32 s2, s2, 1
s_addc_u32 s3, s3, 0
v_dual_cndmask_b32 v13, v12, v9 :: v_dual_cndmask_b32 v12, v14, v8
s_cmp_eq_u32 s2, 5
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[10:11], -v[12:13], v[12:13], v[10:11]
s_cbranch_scc0 .LBB0_4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_mul_f64 v[12:13], v[10:11], s[6:7]
v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[10:11]
v_cmp_ngt_f64_e64 s2, 0xc090cc00, v[10:11]
v_add_nc_u32_e32 v30, 0x1ba6d9, v30
s_add_i32 s33, s33, 1
v_rndne_f64_e32 v[12:13], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[14:15], v[12:13], s[8:9], v[10:11]
v_cvt_i32_f64_e32 v31, v[12:13]
v_fma_f64 v[14:15], v[12:13], s[10:11], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[21:22], v[14:15], s[16:17], s[12:13]
v_fma_f64 v[21:22], v[14:15], v[21:22], s[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[21:22], v[14:15], v[21:22], s[18:19]
v_fma_f64 v[21:22], v[14:15], v[21:22], s[20:21]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[21:22], v[14:15], v[21:22], s[22:23]
v_fma_f64 v[21:22], v[14:15], v[21:22], s[24:25]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[21:22], v[14:15], v[21:22], s[26:27]
v_fma_f64 v[21:22], v[14:15], v[21:22], s[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[21:22], v[14:15], v[21:22], s[30:31]
v_fma_f64 v[21:22], v[14:15], v[21:22], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], v[14:15], v[21:22], 1.0
v_ldexp_f64 v[12:13], v[12:13], v31
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[12:13], v[12:13], -11
v_cndmask_b32_e32 v13, 0x7ff00000, v13, vcc_lo
s_and_b32 vcc_lo, s2, vcc_lo
s_cmpk_eq_i32 s33, 0x800
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v10, 0, v12, vcc_lo
v_cndmask_b32_e64 v11, 0, v13, s2
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[23:24], v[23:24], v[10:11]
s_cbranch_scc0 .LBB0_1
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 3, v[25:26]
v_add_nc_u32_e32 v2, 0xdd36c800, v20
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_clause 0x2
global_store_b32 v[27:28], v29, off offset:40
global_store_b128 v[27:28], v[16:19], off offset:24
global_store_b32 v[27:28], v2, off
global_store_b64 v[0:1], v[23:24], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6mc_intPdP12hiprandState
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 36
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6mc_intPdP12hiprandState, .Lfunc_end0-_Z6mc_intPdP12hiprandState
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6mc_intPdP12hiprandState
.private_segment_fixed_size: 0
.sgpr_count: 38
.sgpr_spill_count: 0
.symbol: _Z6mc_intPdP12hiprandState.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a7f4c_00000000-6_mc.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2274:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2274:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z6mc_intPdP17curandStateXORWOWPdP17curandStateXORWOW
.type _Z45__device_stub__Z6mc_intPdP17curandStateXORWOWPdP17curandStateXORWOW, @function
_Z45__device_stub__Z6mc_intPdP17curandStateXORWOWPdP17curandStateXORWOW:
.LFB2296:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6mc_intPdP17curandStateXORWOW(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2296:
.size _Z45__device_stub__Z6mc_intPdP17curandStateXORWOWPdP17curandStateXORWOW, .-_Z45__device_stub__Z6mc_intPdP17curandStateXORWOWPdP17curandStateXORWOW
.globl _Z6mc_intPdP17curandStateXORWOW
.type _Z6mc_intPdP17curandStateXORWOW, @function
_Z6mc_intPdP17curandStateXORWOW:
.LFB2297:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z6mc_intPdP17curandStateXORWOWPdP17curandStateXORWOW
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2297:
.size _Z6mc_intPdP17curandStateXORWOW, .-_Z6mc_intPdP17curandStateXORWOW
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "%ld clocks (%lf seconds)\n"
.LC4:
.string "integral is: %lf\n"
.text
.globl main
.type main, @function
main:
.LFB2271:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
leaq -524288(%rsp), %r11
.cfi_def_cfa 11, 524312
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $104, %rsp
.cfi_def_cfa_offset 524416
movq %fs:40, %rax
movq %rax, 524376(%rsp)
xorl %eax, %eax
call clock@PLT
movq %rax, %rbp
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
leaq 16(%rsp), %rdi
movl $524288, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $3145728, %esi
call cudaMalloc@PLT
movl $256, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $256, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
leaq 80(%rsp), %rbx
movl $2, %ecx
movl $524288, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rax
leaq 524368(%rsp), %rdx
pxor %xmm0, %xmm0
.L13:
addsd (%rax), %xmm0
addq $8, %rax
cmpq %rdx, %rax
jne .L13
mulsd .LC1(%rip), %xmm0
movq %xmm0, %rbx
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 64(%rsp), %rax
subq 48(%rsp), %rax
imulq $1000000, %rax, %rax
addq 72(%rsp), %rax
subq 56(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC2(%rip), %xmm0
movsd %xmm0, 8(%rsp)
call clock@PLT
subq %rbp, %rax
movq %rax, %rdx
movsd 8(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 524376(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $524392, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z45__device_stub__Z6mc_intPdP17curandStateXORWOWPdP17curandStateXORWOW
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2271:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "_Z6mc_intPdP17curandStateXORWOW"
.section .rodata.str1.1
.LC6:
.string "precalc_xorwow_matrix"
.LC7:
.string "precalc_xorwow_offset_matrix"
.LC8:
.string "mrg32k3aM1"
.LC9:
.string "mrg32k3aM2"
.LC10:
.string "mrg32k3aM1SubSeq"
.LC11:
.string "mrg32k3aM2SubSeq"
.LC12:
.string "mrg32k3aM1Seq"
.LC13:
.string "mrg32k3aM2Seq"
.LC14:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2299:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z6mc_intPdP17curandStateXORWOW(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2299:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1055916032
.align 8
.LC2:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mc.hip"
.globl _Z21__device_stub__mc_intPdP12hiprandState # -- Begin function _Z21__device_stub__mc_intPdP12hiprandState
.p2align 4, 0x90
.type _Z21__device_stub__mc_intPdP12hiprandState,@function
_Z21__device_stub__mc_intPdP12hiprandState: # @_Z21__device_stub__mc_intPdP12hiprandState
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6mc_intPdP12hiprandState, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__mc_intPdP12hiprandState, .Lfunc_end0-_Z21__device_stub__mc_intPdP12hiprandState
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3ef0000000000000 # double 1.52587890625E-5
.LCPI1_1:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $524400, %rsp # imm = 0x80070
.cfi_def_cfa_offset 524416
.cfi_offset %rbx, -16
callq clock
movq %rax, %rbx
leaq 96(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq %rsp, %rdi
movl $524288, %esi # imm = 0x80000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $3145728, %esi # imm = 0x300000
callq hipMalloc
movabsq $4294967552, %rdi # imm = 0x100000100
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq (%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6mc_intPdP12hiprandState, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
leaq 112(%rsp), %rdi
movl $524288, %edx # imm = 0x80000
movl $2, %ecx
callq hipMemcpy
xorpd %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
addsd 112(%rsp,%rax,8), %xmm0
incq %rax
cmpq $65536, %rax # imm = 0x10000
jne .LBB1_3
# %bb.4: # %.preheader
mulsd .LCPI1_0(%rip), %xmm0
movsd %xmm0, 40(%rsp) # 8-byte Spill
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 8(%rsp), %rax
subq 96(%rsp), %rax
imulq $1000000, %rax, %rax # imm = 0xF4240
addq 16(%rsp), %rax
subq 104(%rsp), %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI1_1(%rip), %xmm0
movsd %xmm0, 32(%rsp) # 8-byte Spill
callq clock
subq %rbx, %rax
movl $.L.str, %edi
movq %rax, %rsi
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $.L.str.1, %edi
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movq (%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $524400, %rsp # imm = 0x80070
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6mc_intPdP12hiprandState, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6mc_intPdP12hiprandState,@object # @_Z6mc_intPdP12hiprandState
.section .rodata,"a",@progbits
.globl _Z6mc_intPdP12hiprandState
.p2align 3, 0x0
_Z6mc_intPdP12hiprandState:
.quad _Z21__device_stub__mc_intPdP12hiprandState
.size _Z6mc_intPdP12hiprandState, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%ld clocks (%lf seconds)\n"
.size .L.str, 26
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "integral is: %lf\n"
.size .L.str.1, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6mc_intPdP12hiprandState"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__mc_intPdP12hiprandState
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6mc_intPdP12hiprandState
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "sha512.cuh"
#define ROTRIGHT(a, b) (((a) >> (b)) | ((a) << (64 - (b))))
#define CH(x, y, z) (((x) & (y)) ^ (~(x) & (z)))
#define MAJ(x, y, z) (((x) & (y)) ^ ((x) & (z)) ^ ((y) & (z)))
#define EP0(x) (ROTRIGHT(x, 28) ^ ROTRIGHT(x, 34) ^ ROTRIGHT(x, 39))
#define EP1(x) (ROTRIGHT(x, 14) ^ ROTRIGHT(x, 18) ^ ROTRIGHT(x, 41))
#define SIG0(x) (ROTRIGHT(x, 1) ^ ROTRIGHT(x, 8) ^ ((x) >> 7))
#define SIG1(x) (ROTRIGHT(x, 19) ^ ROTRIGHT(x, 61) ^ ((x) >> 6))
__constant__ uint64_t sha512_kernel[] = {
0x428a2f98d728ae22ul, 0x7137449123ef65cdul, 0xb5c0fbcfec4d3b2ful, 0xe9b5dba58189dbbcul, 0x3956c25bf348b538ul,
0x59f111f1b605d019ul, 0x923f82a4af194f9bul, 0xab1c5ed5da6d8118ul, 0xd807aa98a3030242ul, 0x12835b0145706fbeul,
0x243185be4ee4b28cul, 0x550c7dc3d5ffb4e2ul, 0x72be5d74f27b896ful, 0x80deb1fe3b1696b1ul, 0x9bdc06a725c71235ul,
0xc19bf174cf692694ul, 0xe49b69c19ef14ad2ul, 0xefbe4786384f25e3ul, 0x0fc19dc68b8cd5b5ul, 0x240ca1cc77ac9c65ul,
0x2de92c6f592b0275ul, 0x4a7484aa6ea6e483ul, 0x5cb0a9dcbd41fbd4ul, 0x76f988da831153b5ul, 0x983e5152ee66dfabul,
0xa831c66d2db43210ul, 0xb00327c898fb213ful, 0xbf597fc7beef0ee4ul, 0xc6e00bf33da88fc2ul, 0xd5a79147930aa725ul,
0x06ca6351e003826ful, 0x142929670a0e6e70ul, 0x27b70a8546d22ffcul, 0x2e1b21385c26c926ul, 0x4d2c6dfc5ac42aedul,
0x53380d139d95b3dful, 0x650a73548baf63deul, 0x766a0abb3c77b2a8ul, 0x81c2c92e47edaee6ul, 0x92722c851482353bul,
0xa2bfe8a14cf10364ul, 0xa81a664bbc423001ul, 0xc24b8b70d0f89791ul, 0xc76c51a30654be30ul, 0xd192e819d6ef5218ul,
0xd69906245565a910ul, 0xf40e35855771202aul, 0x106aa07032bbd1b8ul, 0x19a4c116b8d2d0c8ul, 0x1e376c085141ab53ul,
0x2748774cdf8eeb99ul, 0x34b0bcb5e19b48a8ul, 0x391c0cb3c5c95a63ul, 0x4ed8aa4ae3418acbul, 0x5b9cca4f7763e373ul,
0x682e6ff3d6b2b8a3ul, 0x748f82ee5defb2fcul, 0x78a5636f43172f60ul, 0x84c87814a1f0ab72ul, 0x8cc702081a6439ecul,
0x90befffa23631e28ul, 0xa4506cebde82bde9ul, 0xbef9a3f7b2c67915ul, 0xc67178f2e372532bul, 0xca273eceea26619cul,
0xd186b8c721c0c207ul, 0xeada7dd6cde0eb1eul, 0xf57d4f7fee6ed178ul, 0x06f067aa72176fbaul, 0x0a637dc5a2c898a6ul,
0x113f9804bef90daeul, 0x1b710b35131c471bul, 0x28db77f523047d84ul, 0x32caab7b40c72493ul, 0x3c9ebe0a15c9bebcul,
0x431d67c49c100d4cul, 0x4cc5d4becb3e42b6ul, 0x597f299cfc657e2aul, 0x5fcb6fab3ad6faecul, 0x6c44198c4a475817ul};
__device__ void sha512_transform(Sha512Context *ctx, const uint8_t data[128]) {
uint64_t a, b, c, d, e, f, g, h, i, j, t1, t2, m[80];
#pragma unroll 16
for (i = 0, j = 0; i < 16; ++i, j += 8) {
m[i] = (static_cast<uint64_t>(data[j + 0]) << 56) | (static_cast<uint64_t>(data[j + 1]) << 48) |
(static_cast<uint64_t>(data[j + 2]) << 40) | (static_cast<uint64_t>(data[j + 3]) << 32) |
(static_cast<uint64_t>(data[j + 4]) << 24) | (static_cast<uint64_t>(data[j + 5]) << 16) |
(static_cast<uint64_t>(data[j + 6]) << 8) | (static_cast<uint64_t>(data[j + 7]));
}
#pragma unroll 80
for (; i < 80; ++i) {
m[i] = m[i - 16] + SIG0(m[i - 15]) + SIG1(m[i - 2]) + m[i - 7];
}
a = ctx->state[0];
b = ctx->state[1];
c = ctx->state[2];
d = ctx->state[3];
e = ctx->state[4];
f = ctx->state[5];
g = ctx->state[6];
h = ctx->state[7];
#pragma unroll 80
for (i = 0; i < 80; ++i) {
t1 = h + EP1(e) + CH(e, f, g) + sha512_kernel[i] + m[i];
t2 = EP0(a) + MAJ(a, b, c);
h = g;
g = f;
f = e;
e = d + t1;
d = c;
c = b;
b = a;
a = t1 + t2;
}
ctx->state[0] += a;
ctx->state[1] += b;
ctx->state[2] += c;
ctx->state[3] += d;
ctx->state[4] += e;
ctx->state[5] += f;
ctx->state[6] += g;
ctx->state[7] += h;
}
__device__ void sha512_init(Sha512Context *ctx) {
ctx->dataLen = 0;
ctx->bitLen = 0;
ctx->state[0] = 0x6a09e667f3bcc908UL;
ctx->state[1] = 0xbb67ae8584caa73bUL;
ctx->state[2] = 0x3c6ef372fe94f82bUL;
ctx->state[3] = 0xa54ff53a5f1d36f1UL;
ctx->state[4] = 0x510e527fade682d1UL;
ctx->state[5] = 0x9b05688c2b3e6c1fUL;
ctx->state[6] = 0x1f83d9abfb41bd6bUL;
ctx->state[7] = 0x5be0cd19137e2179UL;
}
__device__ void sha512_update(Sha512Context *ctx, const uint8_t data[], size_t len) {
for (auto i = 0; i < len; ++i) {
ctx->data[ctx->dataLen] = data[i];
ctx->dataLen++;
if (ctx->dataLen == 128) {
sha512_transform(ctx, ctx->data);
ctx->bitLen += 1024;
ctx->dataLen = 0;
}
}
}
__device__ void sha512_final(Sha512Context *ctx) {
uint32_t i;
i = ctx->dataLen;
// Pad whatever data is left in the buffer.
if (ctx->dataLen < 112) {
ctx->data[i++] = 0x80;
while (i < 112) {
ctx->data[i++] = 0x00;
}
} else {
ctx->data[i++] = 0x80;
while (i < 128) {
ctx->data[i++] = 0x00;
}
sha512_transform(ctx, ctx->data);
memset(ctx->data, 0, 112);
}
// Append to the padding the total message's length in bits and transform.
ctx->bitLen += ctx->dataLen * 8;
ctx->data[127] = ctx->bitLen;
ctx->data[126] = ctx->bitLen >> 8;
ctx->data[125] = ctx->bitLen >> 16;
ctx->data[124] = ctx->bitLen >> 24;
ctx->data[123] = ctx->bitLen >> 32;
ctx->data[122] = ctx->bitLen >> 40;
ctx->data[121] = ctx->bitLen >> 48;
ctx->data[120] = ctx->bitLen >> 56;
memset(ctx->data + 112, 0, 8);
sha512_transform(ctx, ctx->data);
}
__device__ void sha512_write_output(Sha512Context *ctx, uint8_t hash[]) {
for (auto i = 0; i < 8; ++i) {
hash[i] = (ctx->state[0] >> (56 - i * 8)) & 0x000000ff;
hash[i + 8] = (ctx->state[1] >> (56 - i * 8)) & 0x000000ff;
hash[i + 16] = (ctx->state[2] >> (56 - i * 8)) & 0x000000ff;
hash[i + 24] = (ctx->state[3] >> (56 - i * 8)) & 0x000000ff;
hash[i + 32] = (ctx->state[4] >> (56 - i * 8)) & 0x000000ff;
hash[i + 40] = (ctx->state[5] >> (56 - i * 8)) & 0x000000ff;
hash[i + 48] = (ctx->state[6] >> (56 - i * 8)) & 0x000000ff;
hash[i + 56] = (ctx->state[7] >> (56 - i * 8)) & 0x000000ff;
}
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "sha512.cuh"
#define ROTRIGHT(a, b) (((a) >> (b)) | ((a) << (64 - (b))))
#define CH(x, y, z) (((x) & (y)) ^ (~(x) & (z)))
#define MAJ(x, y, z) (((x) & (y)) ^ ((x) & (z)) ^ ((y) & (z)))
#define EP0(x) (ROTRIGHT(x, 28) ^ ROTRIGHT(x, 34) ^ ROTRIGHT(x, 39))
#define EP1(x) (ROTRIGHT(x, 14) ^ ROTRIGHT(x, 18) ^ ROTRIGHT(x, 41))
#define SIG0(x) (ROTRIGHT(x, 1) ^ ROTRIGHT(x, 8) ^ ((x) >> 7))
#define SIG1(x) (ROTRIGHT(x, 19) ^ ROTRIGHT(x, 61) ^ ((x) >> 6))
__constant__ uint64_t sha512_kernel[] = {
0x428a2f98d728ae22ul, 0x7137449123ef65cdul, 0xb5c0fbcfec4d3b2ful, 0xe9b5dba58189dbbcul, 0x3956c25bf348b538ul,
0x59f111f1b605d019ul, 0x923f82a4af194f9bul, 0xab1c5ed5da6d8118ul, 0xd807aa98a3030242ul, 0x12835b0145706fbeul,
0x243185be4ee4b28cul, 0x550c7dc3d5ffb4e2ul, 0x72be5d74f27b896ful, 0x80deb1fe3b1696b1ul, 0x9bdc06a725c71235ul,
0xc19bf174cf692694ul, 0xe49b69c19ef14ad2ul, 0xefbe4786384f25e3ul, 0x0fc19dc68b8cd5b5ul, 0x240ca1cc77ac9c65ul,
0x2de92c6f592b0275ul, 0x4a7484aa6ea6e483ul, 0x5cb0a9dcbd41fbd4ul, 0x76f988da831153b5ul, 0x983e5152ee66dfabul,
0xa831c66d2db43210ul, 0xb00327c898fb213ful, 0xbf597fc7beef0ee4ul, 0xc6e00bf33da88fc2ul, 0xd5a79147930aa725ul,
0x06ca6351e003826ful, 0x142929670a0e6e70ul, 0x27b70a8546d22ffcul, 0x2e1b21385c26c926ul, 0x4d2c6dfc5ac42aedul,
0x53380d139d95b3dful, 0x650a73548baf63deul, 0x766a0abb3c77b2a8ul, 0x81c2c92e47edaee6ul, 0x92722c851482353bul,
0xa2bfe8a14cf10364ul, 0xa81a664bbc423001ul, 0xc24b8b70d0f89791ul, 0xc76c51a30654be30ul, 0xd192e819d6ef5218ul,
0xd69906245565a910ul, 0xf40e35855771202aul, 0x106aa07032bbd1b8ul, 0x19a4c116b8d2d0c8ul, 0x1e376c085141ab53ul,
0x2748774cdf8eeb99ul, 0x34b0bcb5e19b48a8ul, 0x391c0cb3c5c95a63ul, 0x4ed8aa4ae3418acbul, 0x5b9cca4f7763e373ul,
0x682e6ff3d6b2b8a3ul, 0x748f82ee5defb2fcul, 0x78a5636f43172f60ul, 0x84c87814a1f0ab72ul, 0x8cc702081a6439ecul,
0x90befffa23631e28ul, 0xa4506cebde82bde9ul, 0xbef9a3f7b2c67915ul, 0xc67178f2e372532bul, 0xca273eceea26619cul,
0xd186b8c721c0c207ul, 0xeada7dd6cde0eb1eul, 0xf57d4f7fee6ed178ul, 0x06f067aa72176fbaul, 0x0a637dc5a2c898a6ul,
0x113f9804bef90daeul, 0x1b710b35131c471bul, 0x28db77f523047d84ul, 0x32caab7b40c72493ul, 0x3c9ebe0a15c9bebcul,
0x431d67c49c100d4cul, 0x4cc5d4becb3e42b6ul, 0x597f299cfc657e2aul, 0x5fcb6fab3ad6faecul, 0x6c44198c4a475817ul};
__device__ void sha512_transform(Sha512Context *ctx, const uint8_t data[128]) {
uint64_t a, b, c, d, e, f, g, h, i, j, t1, t2, m[80];
#pragma unroll 16
for (i = 0, j = 0; i < 16; ++i, j += 8) {
m[i] = (static_cast<uint64_t>(data[j + 0]) << 56) | (static_cast<uint64_t>(data[j + 1]) << 48) |
(static_cast<uint64_t>(data[j + 2]) << 40) | (static_cast<uint64_t>(data[j + 3]) << 32) |
(static_cast<uint64_t>(data[j + 4]) << 24) | (static_cast<uint64_t>(data[j + 5]) << 16) |
(static_cast<uint64_t>(data[j + 6]) << 8) | (static_cast<uint64_t>(data[j + 7]));
}
#pragma unroll 80
for (; i < 80; ++i) {
m[i] = m[i - 16] + SIG0(m[i - 15]) + SIG1(m[i - 2]) + m[i - 7];
}
a = ctx->state[0];
b = ctx->state[1];
c = ctx->state[2];
d = ctx->state[3];
e = ctx->state[4];
f = ctx->state[5];
g = ctx->state[6];
h = ctx->state[7];
#pragma unroll 80
for (i = 0; i < 80; ++i) {
t1 = h + EP1(e) + CH(e, f, g) + sha512_kernel[i] + m[i];
t2 = EP0(a) + MAJ(a, b, c);
h = g;
g = f;
f = e;
e = d + t1;
d = c;
c = b;
b = a;
a = t1 + t2;
}
ctx->state[0] += a;
ctx->state[1] += b;
ctx->state[2] += c;
ctx->state[3] += d;
ctx->state[4] += e;
ctx->state[5] += f;
ctx->state[6] += g;
ctx->state[7] += h;
}
__device__ void sha512_init(Sha512Context *ctx) {
ctx->dataLen = 0;
ctx->bitLen = 0;
ctx->state[0] = 0x6a09e667f3bcc908UL;
ctx->state[1] = 0xbb67ae8584caa73bUL;
ctx->state[2] = 0x3c6ef372fe94f82bUL;
ctx->state[3] = 0xa54ff53a5f1d36f1UL;
ctx->state[4] = 0x510e527fade682d1UL;
ctx->state[5] = 0x9b05688c2b3e6c1fUL;
ctx->state[6] = 0x1f83d9abfb41bd6bUL;
ctx->state[7] = 0x5be0cd19137e2179UL;
}
__device__ void sha512_update(Sha512Context *ctx, const uint8_t data[], size_t len) {
for (auto i = 0; i < len; ++i) {
ctx->data[ctx->dataLen] = data[i];
ctx->dataLen++;
if (ctx->dataLen == 128) {
sha512_transform(ctx, ctx->data);
ctx->bitLen += 1024;
ctx->dataLen = 0;
}
}
}
__device__ void sha512_final(Sha512Context *ctx) {
uint32_t i;
i = ctx->dataLen;
// Pad whatever data is left in the buffer.
if (ctx->dataLen < 112) {
ctx->data[i++] = 0x80;
while (i < 112) {
ctx->data[i++] = 0x00;
}
} else {
ctx->data[i++] = 0x80;
while (i < 128) {
ctx->data[i++] = 0x00;
}
sha512_transform(ctx, ctx->data);
memset(ctx->data, 0, 112);
}
// Append to the padding the total message's length in bits and transform.
ctx->bitLen += ctx->dataLen * 8;
ctx->data[127] = ctx->bitLen;
ctx->data[126] = ctx->bitLen >> 8;
ctx->data[125] = ctx->bitLen >> 16;
ctx->data[124] = ctx->bitLen >> 24;
ctx->data[123] = ctx->bitLen >> 32;
ctx->data[122] = ctx->bitLen >> 40;
ctx->data[121] = ctx->bitLen >> 48;
ctx->data[120] = ctx->bitLen >> 56;
memset(ctx->data + 112, 0, 8);
sha512_transform(ctx, ctx->data);
}
__device__ void sha512_write_output(Sha512Context *ctx, uint8_t hash[]) {
for (auto i = 0; i < 8; ++i) {
hash[i] = (ctx->state[0] >> (56 - i * 8)) & 0x000000ff;
hash[i + 8] = (ctx->state[1] >> (56 - i * 8)) & 0x000000ff;
hash[i + 16] = (ctx->state[2] >> (56 - i * 8)) & 0x000000ff;
hash[i + 24] = (ctx->state[3] >> (56 - i * 8)) & 0x000000ff;
hash[i + 32] = (ctx->state[4] >> (56 - i * 8)) & 0x000000ff;
hash[i + 40] = (ctx->state[5] >> (56 - i * 8)) & 0x000000ff;
hash[i + 48] = (ctx->state[6] >> (56 - i * 8)) & 0x000000ff;
hash[i + 56] = (ctx->state[7] >> (56 - i * 8)) & 0x000000ff;
}
} | .file "tmpxft_0004a888_00000000-6_sha512.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2034:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2034:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z16sha512_transformP13Sha512ContextPKh
.type _Z16sha512_transformP13Sha512ContextPKh, @function
_Z16sha512_transformP13Sha512ContextPKh:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z16sha512_transformP13Sha512ContextPKh, .-_Z16sha512_transformP13Sha512ContextPKh
.globl _Z11sha512_initP13Sha512Context
.type _Z11sha512_initP13Sha512Context, @function
_Z11sha512_initP13Sha512Context:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z11sha512_initP13Sha512Context, .-_Z11sha512_initP13Sha512Context
.globl _Z13sha512_updateP13Sha512ContextPKhm
.type _Z13sha512_updateP13Sha512ContextPKhm, @function
_Z13sha512_updateP13Sha512ContextPKhm:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z13sha512_updateP13Sha512ContextPKhm, .-_Z13sha512_updateP13Sha512ContextPKhm
.globl _Z12sha512_finalP13Sha512Context
.type _Z12sha512_finalP13Sha512Context, @function
_Z12sha512_finalP13Sha512Context:
.LFB2030:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2030:
.size _Z12sha512_finalP13Sha512Context, .-_Z12sha512_finalP13Sha512Context
.globl _Z19sha512_write_outputP13Sha512ContextPh
.type _Z19sha512_write_outputP13Sha512ContextPh, @function
_Z19sha512_write_outputP13Sha512ContextPh:
.LFB2031:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2031:
.size _Z19sha512_write_outputP13Sha512ContextPh, .-_Z19sha512_write_outputP13Sha512ContextPh
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "sha512_kernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $640, %r9d
movl $0, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13sha512_kernel(%rip), %rsi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL13sha512_kernel
.comm _ZL13sha512_kernel,640,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "sha512.cuh"
#define ROTRIGHT(a, b) (((a) >> (b)) | ((a) << (64 - (b))))
#define CH(x, y, z) (((x) & (y)) ^ (~(x) & (z)))
#define MAJ(x, y, z) (((x) & (y)) ^ ((x) & (z)) ^ ((y) & (z)))
#define EP0(x) (ROTRIGHT(x, 28) ^ ROTRIGHT(x, 34) ^ ROTRIGHT(x, 39))
#define EP1(x) (ROTRIGHT(x, 14) ^ ROTRIGHT(x, 18) ^ ROTRIGHT(x, 41))
#define SIG0(x) (ROTRIGHT(x, 1) ^ ROTRIGHT(x, 8) ^ ((x) >> 7))
#define SIG1(x) (ROTRIGHT(x, 19) ^ ROTRIGHT(x, 61) ^ ((x) >> 6))
__constant__ uint64_t sha512_kernel[] = {
0x428a2f98d728ae22ul, 0x7137449123ef65cdul, 0xb5c0fbcfec4d3b2ful, 0xe9b5dba58189dbbcul, 0x3956c25bf348b538ul,
0x59f111f1b605d019ul, 0x923f82a4af194f9bul, 0xab1c5ed5da6d8118ul, 0xd807aa98a3030242ul, 0x12835b0145706fbeul,
0x243185be4ee4b28cul, 0x550c7dc3d5ffb4e2ul, 0x72be5d74f27b896ful, 0x80deb1fe3b1696b1ul, 0x9bdc06a725c71235ul,
0xc19bf174cf692694ul, 0xe49b69c19ef14ad2ul, 0xefbe4786384f25e3ul, 0x0fc19dc68b8cd5b5ul, 0x240ca1cc77ac9c65ul,
0x2de92c6f592b0275ul, 0x4a7484aa6ea6e483ul, 0x5cb0a9dcbd41fbd4ul, 0x76f988da831153b5ul, 0x983e5152ee66dfabul,
0xa831c66d2db43210ul, 0xb00327c898fb213ful, 0xbf597fc7beef0ee4ul, 0xc6e00bf33da88fc2ul, 0xd5a79147930aa725ul,
0x06ca6351e003826ful, 0x142929670a0e6e70ul, 0x27b70a8546d22ffcul, 0x2e1b21385c26c926ul, 0x4d2c6dfc5ac42aedul,
0x53380d139d95b3dful, 0x650a73548baf63deul, 0x766a0abb3c77b2a8ul, 0x81c2c92e47edaee6ul, 0x92722c851482353bul,
0xa2bfe8a14cf10364ul, 0xa81a664bbc423001ul, 0xc24b8b70d0f89791ul, 0xc76c51a30654be30ul, 0xd192e819d6ef5218ul,
0xd69906245565a910ul, 0xf40e35855771202aul, 0x106aa07032bbd1b8ul, 0x19a4c116b8d2d0c8ul, 0x1e376c085141ab53ul,
0x2748774cdf8eeb99ul, 0x34b0bcb5e19b48a8ul, 0x391c0cb3c5c95a63ul, 0x4ed8aa4ae3418acbul, 0x5b9cca4f7763e373ul,
0x682e6ff3d6b2b8a3ul, 0x748f82ee5defb2fcul, 0x78a5636f43172f60ul, 0x84c87814a1f0ab72ul, 0x8cc702081a6439ecul,
0x90befffa23631e28ul, 0xa4506cebde82bde9ul, 0xbef9a3f7b2c67915ul, 0xc67178f2e372532bul, 0xca273eceea26619cul,
0xd186b8c721c0c207ul, 0xeada7dd6cde0eb1eul, 0xf57d4f7fee6ed178ul, 0x06f067aa72176fbaul, 0x0a637dc5a2c898a6ul,
0x113f9804bef90daeul, 0x1b710b35131c471bul, 0x28db77f523047d84ul, 0x32caab7b40c72493ul, 0x3c9ebe0a15c9bebcul,
0x431d67c49c100d4cul, 0x4cc5d4becb3e42b6ul, 0x597f299cfc657e2aul, 0x5fcb6fab3ad6faecul, 0x6c44198c4a475817ul};
__device__ void sha512_transform(Sha512Context *ctx, const uint8_t data[128]) {
uint64_t a, b, c, d, e, f, g, h, i, j, t1, t2, m[80];
#pragma unroll 16
for (i = 0, j = 0; i < 16; ++i, j += 8) {
m[i] = (static_cast<uint64_t>(data[j + 0]) << 56) | (static_cast<uint64_t>(data[j + 1]) << 48) |
(static_cast<uint64_t>(data[j + 2]) << 40) | (static_cast<uint64_t>(data[j + 3]) << 32) |
(static_cast<uint64_t>(data[j + 4]) << 24) | (static_cast<uint64_t>(data[j + 5]) << 16) |
(static_cast<uint64_t>(data[j + 6]) << 8) | (static_cast<uint64_t>(data[j + 7]));
}
#pragma unroll 80
for (; i < 80; ++i) {
m[i] = m[i - 16] + SIG0(m[i - 15]) + SIG1(m[i - 2]) + m[i - 7];
}
a = ctx->state[0];
b = ctx->state[1];
c = ctx->state[2];
d = ctx->state[3];
e = ctx->state[4];
f = ctx->state[5];
g = ctx->state[6];
h = ctx->state[7];
#pragma unroll 80
for (i = 0; i < 80; ++i) {
t1 = h + EP1(e) + CH(e, f, g) + sha512_kernel[i] + m[i];
t2 = EP0(a) + MAJ(a, b, c);
h = g;
g = f;
f = e;
e = d + t1;
d = c;
c = b;
b = a;
a = t1 + t2;
}
ctx->state[0] += a;
ctx->state[1] += b;
ctx->state[2] += c;
ctx->state[3] += d;
ctx->state[4] += e;
ctx->state[5] += f;
ctx->state[6] += g;
ctx->state[7] += h;
}
__device__ void sha512_init(Sha512Context *ctx) {
ctx->dataLen = 0;
ctx->bitLen = 0;
ctx->state[0] = 0x6a09e667f3bcc908UL;
ctx->state[1] = 0xbb67ae8584caa73bUL;
ctx->state[2] = 0x3c6ef372fe94f82bUL;
ctx->state[3] = 0xa54ff53a5f1d36f1UL;
ctx->state[4] = 0x510e527fade682d1UL;
ctx->state[5] = 0x9b05688c2b3e6c1fUL;
ctx->state[6] = 0x1f83d9abfb41bd6bUL;
ctx->state[7] = 0x5be0cd19137e2179UL;
}
__device__ void sha512_update(Sha512Context *ctx, const uint8_t data[], size_t len) {
for (auto i = 0; i < len; ++i) {
ctx->data[ctx->dataLen] = data[i];
ctx->dataLen++;
if (ctx->dataLen == 128) {
sha512_transform(ctx, ctx->data);
ctx->bitLen += 1024;
ctx->dataLen = 0;
}
}
}
__device__ void sha512_final(Sha512Context *ctx) {
uint32_t i;
i = ctx->dataLen;
// Pad whatever data is left in the buffer.
if (ctx->dataLen < 112) {
ctx->data[i++] = 0x80;
while (i < 112) {
ctx->data[i++] = 0x00;
}
} else {
ctx->data[i++] = 0x80;
while (i < 128) {
ctx->data[i++] = 0x00;
}
sha512_transform(ctx, ctx->data);
memset(ctx->data, 0, 112);
}
// Append to the padding the total message's length in bits and transform.
ctx->bitLen += ctx->dataLen * 8;
ctx->data[127] = ctx->bitLen;
ctx->data[126] = ctx->bitLen >> 8;
ctx->data[125] = ctx->bitLen >> 16;
ctx->data[124] = ctx->bitLen >> 24;
ctx->data[123] = ctx->bitLen >> 32;
ctx->data[122] = ctx->bitLen >> 40;
ctx->data[121] = ctx->bitLen >> 48;
ctx->data[120] = ctx->bitLen >> 56;
memset(ctx->data + 112, 0, 8);
sha512_transform(ctx, ctx->data);
}
__device__ void sha512_write_output(Sha512Context *ctx, uint8_t hash[]) {
for (auto i = 0; i < 8; ++i) {
hash[i] = (ctx->state[0] >> (56 - i * 8)) & 0x000000ff;
hash[i + 8] = (ctx->state[1] >> (56 - i * 8)) & 0x000000ff;
hash[i + 16] = (ctx->state[2] >> (56 - i * 8)) & 0x000000ff;
hash[i + 24] = (ctx->state[3] >> (56 - i * 8)) & 0x000000ff;
hash[i + 32] = (ctx->state[4] >> (56 - i * 8)) & 0x000000ff;
hash[i + 40] = (ctx->state[5] >> (56 - i * 8)) & 0x000000ff;
hash[i + 48] = (ctx->state[6] >> (56 - i * 8)) & 0x000000ff;
hash[i + 56] = (ctx->state[7] >> (56 - i * 8)) & 0x000000ff;
}
} | #pragma once
#include <hip/hip_runtime.h>
#include <cstdint>
struct Sha512Context {
uint8_t data[128];
uint32_t dataLen;
unsigned long long bitLen;
uint64_t state[8];
};
__device__ void sha512_init(Sha512Context *ctx);
__device__ void sha512_update(Sha512Context *ctx, const uint8_t data[], size_t len);
__device__ void sha512_final(Sha512Context *ctx);
__device__ void sha512_write_output(Sha512Context *ctx, uint8_t hash[]); |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #pragma once
#include <hip/hip_runtime.h>
#include <cstdint>
struct Sha512Context {
uint8_t data[128];
uint32_t dataLen;
unsigned long long bitLen;
uint64_t state[8];
};
__device__ void sha512_init(Sha512Context *ctx);
__device__ void sha512_update(Sha512Context *ctx, const uint8_t data[], size_t len);
__device__ void sha512_final(Sha512Context *ctx);
__device__ void sha512_write_output(Sha512Context *ctx, uint8_t hash[]); | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #pragma once
#include <hip/hip_runtime.h>
#include <cstdint>
struct Sha512Context {
uint8_t data[128];
uint32_t dataLen;
unsigned long long bitLen;
uint64_t state[8];
};
__device__ void sha512_init(Sha512Context *ctx);
__device__ void sha512_update(Sha512Context *ctx, const uint8_t data[], size_t len);
__device__ void sha512_final(Sha512Context *ctx);
__device__ void sha512_write_output(Sha512Context *ctx, uint8_t hash[]); | .text
.file "sha512.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004a888_00000000-6_sha512.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2034:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2034:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z16sha512_transformP13Sha512ContextPKh
.type _Z16sha512_transformP13Sha512ContextPKh, @function
_Z16sha512_transformP13Sha512ContextPKh:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z16sha512_transformP13Sha512ContextPKh, .-_Z16sha512_transformP13Sha512ContextPKh
.globl _Z11sha512_initP13Sha512Context
.type _Z11sha512_initP13Sha512Context, @function
_Z11sha512_initP13Sha512Context:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z11sha512_initP13Sha512Context, .-_Z11sha512_initP13Sha512Context
.globl _Z13sha512_updateP13Sha512ContextPKhm
.type _Z13sha512_updateP13Sha512ContextPKhm, @function
_Z13sha512_updateP13Sha512ContextPKhm:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z13sha512_updateP13Sha512ContextPKhm, .-_Z13sha512_updateP13Sha512ContextPKhm
.globl _Z12sha512_finalP13Sha512Context
.type _Z12sha512_finalP13Sha512Context, @function
_Z12sha512_finalP13Sha512Context:
.LFB2030:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2030:
.size _Z12sha512_finalP13Sha512Context, .-_Z12sha512_finalP13Sha512Context
.globl _Z19sha512_write_outputP13Sha512ContextPh
.type _Z19sha512_write_outputP13Sha512ContextPh, @function
_Z19sha512_write_outputP13Sha512ContextPh:
.LFB2031:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2031:
.size _Z19sha512_write_outputP13Sha512ContextPh, .-_Z19sha512_write_outputP13Sha512ContextPh
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "sha512_kernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $640, %r9d
movl $0, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13sha512_kernel(%rip), %rsi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL13sha512_kernel
.comm _ZL13sha512_kernel,640,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sha512.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <fstream>
#include <sstream>
#include <chrono>
#include <vector>
#include <cmath>
#include <dirent.h>
#include <cstring>
using namespace std;
#define N_REPEAT 3
// Complex numbers data type
typedef float2 Cplx;
// Complex numbers operations
static __device__ __host__ inline Cplx CplxAdd(Cplx a, Cplx b) {
Cplx c; c.x = a.x + b.x; c.y = a.y + b.y; return c;
}
static __device__ __host__ inline Cplx CplxInv(Cplx a) {
Cplx c; c.x = -a.x; c.y = -a.y; return c;
}
static __device__ __host__ inline Cplx CplxMul(Cplx a, Cplx b) {
Cplx c; c.x = a.x * b.x - a.y + b.y; c.y = a.x * b.y + a.y * b.x; return c;
}
/**
* Reorders array by bit-reversing the indexes.
*/
__global__ void bitrev_reorder(Cplx* __restrict__ r, Cplx* __restrict__ d, int s, size_t nthr) {
int id = blockIdx.x * nthr + threadIdx.x;
r[__brev(id) >> (32 - s)] = d[id];
}
/**
* Inner part of FFT loop. Contains the procedure itself.
*/
__device__ void inplace_fft_inner(Cplx* __restrict__ r, int j, int k, int m, int n) {
if (j + k + m / 2 < n) {
Cplx t, u;
t.x = __cosf((2.0 * M_PI * k) / (1.0 * m));
t.y = -__sinf((2.0 * M_PI * k) / (1.0 * m));
u = r[j + k];
t = CplxMul(t, r[j + k + m / 2]);
r[j + k] = CplxAdd(u, t);
r[j + k + m / 2] = CplxAdd(u, CplxInv(t));
}
}
/**
* Middle part of FFT for small scope paralelism.
*/
__global__ void inplace_fft(Cplx* __restrict__ r, int j, int m, int n, size_t nthr) {
int k = blockIdx.x * nthr + threadIdx.x;
inplace_fft_inner(r, j, k, m, n);
}
/**
* Outer part of FFT for large scope paralelism.
*/
__global__ void inplace_fft_outer(Cplx* __restrict__ r, int m, int n, size_t nthr) {
int j = (blockIdx.x * nthr + threadIdx.x) * m;
for (int k = 0; k < m / 2; k++) {
inplace_fft_inner(r, j, k, m, n);
}
}
/**
* Runs in-place Iterative Fast Fourier Transformation.
*/
void fft(Cplx* __restrict__ d, size_t n, size_t threads, int balance) {
size_t data_size = n * sizeof(Cplx);
Cplx *r, *dn;
// Copy data to GPU
cudaMalloc((void**)&r, data_size);
cudaMalloc((void**)&dn, data_size);
cudaMemcpy(dn, d, data_size, cudaMemcpyHostToDevice);
// Bit-reversal reordering
int s = log2(n);
bitrev_reorder<<<ceil(n / threads), threads>>>(r, dn, s, threads);
// Synchronize
cudaDeviceSynchronize();
// Iterative FFT (with loop paralelism balancing)
for (int i = 1; i <= s; i++) {
int m = 1 << i;
if (n/m > balance) {
inplace_fft_outer<<<ceil((float)n / m / threads), threads>>>(r, m, n, threads);
} else {
for (int j = 0; j < n; j += m) {
float repeats = m / 2;
inplace_fft<<<ceil(repeats / threads), threads>>>(r, j, m, n, threads);
}
}
}
// Copy data from GPU & free the memory blocks
Cplx* result;
result = (Cplx*)malloc(data_size / 2);
cudaMemcpy(result, r, data_size / 2, cudaMemcpyDeviceToHost);
cudaFree(r);
cudaFree(dn);
}
/**
* Reads numeric data from a file.
*/
void read_file(const char* filename, vector<Cplx>& out) {
ifstream file;
file.open(filename);
if (file.is_open()) {
while (!file.eof()) {
Cplx val;
if (file >> val.x) {
val.y = 0;
out.push_back(val);
}
}
} else {
cerr << "Can't open file " << filename << " for reading." << endl;
}
file.close();
}
/**
* Saves the result data to an output file.
*/
void save_results(const char* filename, Cplx* result, size_t count, int sample_rate) {
char* outfilename = new char[512];
// Compose the output filename
strcpy(outfilename, filename);
strcat(outfilename, ".out");
// Create the file
ofstream outfile;
outfile.open (outfilename);
outfile.precision(4);
// Save the data
outfile << "frequency, value" << endl;
for (int i = 0; i < count / 2; i++) {
outfile << i * ((float)sample_rate/count) << "," << result[i].x << endl;
}
outfile.close();
}
void compute_file(const char* filename, int sample_rate, size_t threads, int balance) {
vector<Cplx> buffer;
// Read the file
read_file(filename, buffer);
int count = buffer.size();
// Display active computation
cout << filename << "," << count << "," << sample_rate << "," << threads <<
"," << balance;
cout.flush();
// Start the stopwatch
auto start = chrono::high_resolution_clock::now();
// Run FFT algorithm with loaded data
fft(&buffer[0], count, threads, balance);
// Log the elapsed time
auto finish = chrono::high_resolution_clock::now();
auto microseconds = chrono::duration_cast<std::chrono::microseconds>(finish-start);
cout << "," << microseconds.count() << endl;
// Save the computed data
save_results(filename, &buffer[0], count, sample_rate);
}
int main(int argc, char** argv) {
srand (time(NULL));
// Deal with program arguments
if (argc < 2) {
cerr << "Usage: " << argv[0] << " [input_folder]"; return 2;
}
// Initialize CUDA
cudaFree(0);
// Print out the CSV header
cout << "file,samples,sample_rate,threads,balance,elapsed_us" << endl;
// Read the folder
DIR* dirp = opendir(argv[1]);
struct dirent *epdf;
// Compute all files in the folder
while ((epdf = readdir(dirp)) != NULL) {
size_t len = strlen(epdf->d_name);
// Pick only .dat files
if (strcmp(epdf->d_name,".") != 0 && strcmp(epdf->d_name,"..") != 0
&& strcmp(&epdf->d_name[len-3], "dat") == 0) {
stringstream fname(epdf->d_name);
string samples, sr;
// Read file properties
getline(fname, samples, '@');
getline(fname, sr, '.');
char* fold = new char[512];
strcpy(fold, argv[1]);
int smp = atoi(samples.c_str());
// Compute for all set parameters
for (int th = 0; th <= 1024; th <<= 1) {
if (th == 0) th = 1;
for (int bal = 2; bal <= smp / 2; bal <<= 1)
for (int r = 0; r < N_REPEAT; r++) {
char fname[512];
strcpy(fname, fold);
strcat(strcat(fname, "/"), epdf->d_name);
compute_file(fname, atoi(sr.c_str()), th, bal);
}
}
}
}
closedir(dirp);
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <fstream>
#include <sstream>
#include <chrono>
#include <vector>
#include <cmath>
#include <dirent.h>
#include <cstring>
using namespace std;
#define N_REPEAT 3
// Complex numbers data type
typedef float2 Cplx;
// Complex numbers operations
static __device__ __host__ inline Cplx CplxAdd(Cplx a, Cplx b) {
Cplx c; c.x = a.x + b.x; c.y = a.y + b.y; return c;
}
static __device__ __host__ inline Cplx CplxInv(Cplx a) {
Cplx c; c.x = -a.x; c.y = -a.y; return c;
}
static __device__ __host__ inline Cplx CplxMul(Cplx a, Cplx b) {
Cplx c; c.x = a.x * b.x - a.y + b.y; c.y = a.x * b.y + a.y * b.x; return c;
}
/**
* Reorders array by bit-reversing the indexes.
*/
__global__ void bitrev_reorder(Cplx* __restrict__ r, Cplx* __restrict__ d, int s, size_t nthr) {
int id = blockIdx.x * nthr + threadIdx.x;
r[__brev(id) >> (32 - s)] = d[id];
}
/**
* Inner part of FFT loop. Contains the procedure itself.
*/
__device__ void inplace_fft_inner(Cplx* __restrict__ r, int j, int k, int m, int n) {
if (j + k + m / 2 < n) {
Cplx t, u;
t.x = __cosf((2.0 * M_PI * k) / (1.0 * m));
t.y = -__sinf((2.0 * M_PI * k) / (1.0 * m));
u = r[j + k];
t = CplxMul(t, r[j + k + m / 2]);
r[j + k] = CplxAdd(u, t);
r[j + k + m / 2] = CplxAdd(u, CplxInv(t));
}
}
/**
* Middle part of FFT for small scope paralelism.
*/
__global__ void inplace_fft(Cplx* __restrict__ r, int j, int m, int n, size_t nthr) {
int k = blockIdx.x * nthr + threadIdx.x;
inplace_fft_inner(r, j, k, m, n);
}
/**
* Outer part of FFT for large scope paralelism.
*/
__global__ void inplace_fft_outer(Cplx* __restrict__ r, int m, int n, size_t nthr) {
int j = (blockIdx.x * nthr + threadIdx.x) * m;
for (int k = 0; k < m / 2; k++) {
inplace_fft_inner(r, j, k, m, n);
}
}
/**
* Runs in-place Iterative Fast Fourier Transformation.
*/
void fft(Cplx* __restrict__ d, size_t n, size_t threads, int balance) {
size_t data_size = n * sizeof(Cplx);
Cplx *r, *dn;
// Copy data to GPU
hipMalloc((void**)&r, data_size);
hipMalloc((void**)&dn, data_size);
hipMemcpy(dn, d, data_size, hipMemcpyHostToDevice);
// Bit-reversal reordering
int s = log2(n);
bitrev_reorder<<<ceil(n / threads), threads>>>(r, dn, s, threads);
// Synchronize
hipDeviceSynchronize();
// Iterative FFT (with loop paralelism balancing)
for (int i = 1; i <= s; i++) {
int m = 1 << i;
if (n/m > balance) {
inplace_fft_outer<<<ceil((float)n / m / threads), threads>>>(r, m, n, threads);
} else {
for (int j = 0; j < n; j += m) {
float repeats = m / 2;
inplace_fft<<<ceil(repeats / threads), threads>>>(r, j, m, n, threads);
}
}
}
// Copy data from GPU & free the memory blocks
Cplx* result;
result = (Cplx*)malloc(data_size / 2);
hipMemcpy(result, r, data_size / 2, hipMemcpyDeviceToHost);
hipFree(r);
hipFree(dn);
}
/**
* Reads numeric data from a file.
*/
void read_file(const char* filename, vector<Cplx>& out) {
ifstream file;
file.open(filename);
if (file.is_open()) {
while (!file.eof()) {
Cplx val;
if (file >> val.x) {
val.y = 0;
out.push_back(val);
}
}
} else {
cerr << "Can't open file " << filename << " for reading." << endl;
}
file.close();
}
/**
* Saves the result data to an output file.
*/
void save_results(const char* filename, Cplx* result, size_t count, int sample_rate) {
char* outfilename = new char[512];
// Compose the output filename
strcpy(outfilename, filename);
strcat(outfilename, ".out");
// Create the file
ofstream outfile;
outfile.open (outfilename);
outfile.precision(4);
// Save the data
outfile << "frequency, value" << endl;
for (int i = 0; i < count / 2; i++) {
outfile << i * ((float)sample_rate/count) << "," << result[i].x << endl;
}
outfile.close();
}
void compute_file(const char* filename, int sample_rate, size_t threads, int balance) {
vector<Cplx> buffer;
// Read the file
read_file(filename, buffer);
int count = buffer.size();
// Display active computation
cout << filename << "," << count << "," << sample_rate << "," << threads <<
"," << balance;
cout.flush();
// Start the stopwatch
auto start = chrono::high_resolution_clock::now();
// Run FFT algorithm with loaded data
fft(&buffer[0], count, threads, balance);
// Log the elapsed time
auto finish = chrono::high_resolution_clock::now();
auto microseconds = chrono::duration_cast<std::chrono::microseconds>(finish-start);
cout << "," << microseconds.count() << endl;
// Save the computed data
save_results(filename, &buffer[0], count, sample_rate);
}
int main(int argc, char** argv) {
srand (time(NULL));
// Deal with program arguments
if (argc < 2) {
cerr << "Usage: " << argv[0] << " [input_folder]"; return 2;
}
// Initialize CUDA
hipFree(0);
// Print out the CSV header
cout << "file,samples,sample_rate,threads,balance,elapsed_us" << endl;
// Read the folder
DIR* dirp = opendir(argv[1]);
struct dirent *epdf;
// Compute all files in the folder
while ((epdf = readdir(dirp)) != NULL) {
size_t len = strlen(epdf->d_name);
// Pick only .dat files
if (strcmp(epdf->d_name,".") != 0 && strcmp(epdf->d_name,"..") != 0
&& strcmp(&epdf->d_name[len-3], "dat") == 0) {
stringstream fname(epdf->d_name);
string samples, sr;
// Read file properties
getline(fname, samples, '@');
getline(fname, sr, '.');
char* fold = new char[512];
strcpy(fold, argv[1]);
int smp = atoi(samples.c_str());
// Compute for all set parameters
for (int th = 0; th <= 1024; th <<= 1) {
if (th == 0) th = 1;
for (int bal = 2; bal <= smp / 2; bal <<= 1)
for (int r = 0; r < N_REPEAT; r++) {
char fname[512];
strcpy(fname, fold);
strcat(strcat(fname, "/"), epdf->d_name);
compute_file(fname, atoi(sr.c_str()), th, bal);
}
}
}
}
closedir(dirp);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <fstream>
#include <sstream>
#include <chrono>
#include <vector>
#include <cmath>
#include <dirent.h>
#include <cstring>
using namespace std;
#define N_REPEAT 3
// Complex numbers data type
typedef float2 Cplx;
// Complex numbers operations
static __device__ __host__ inline Cplx CplxAdd(Cplx a, Cplx b) {
Cplx c; c.x = a.x + b.x; c.y = a.y + b.y; return c;
}
static __device__ __host__ inline Cplx CplxInv(Cplx a) {
Cplx c; c.x = -a.x; c.y = -a.y; return c;
}
static __device__ __host__ inline Cplx CplxMul(Cplx a, Cplx b) {
Cplx c; c.x = a.x * b.x - a.y + b.y; c.y = a.x * b.y + a.y * b.x; return c;
}
/**
* Reorders array by bit-reversing the indexes.
*/
__global__ void bitrev_reorder(Cplx* __restrict__ r, Cplx* __restrict__ d, int s, size_t nthr) {
int id = blockIdx.x * nthr + threadIdx.x;
r[__brev(id) >> (32 - s)] = d[id];
}
/**
* Inner part of FFT loop. Contains the procedure itself.
*/
__device__ void inplace_fft_inner(Cplx* __restrict__ r, int j, int k, int m, int n) {
if (j + k + m / 2 < n) {
Cplx t, u;
t.x = __cosf((2.0 * M_PI * k) / (1.0 * m));
t.y = -__sinf((2.0 * M_PI * k) / (1.0 * m));
u = r[j + k];
t = CplxMul(t, r[j + k + m / 2]);
r[j + k] = CplxAdd(u, t);
r[j + k + m / 2] = CplxAdd(u, CplxInv(t));
}
}
/**
* Middle part of FFT for small scope paralelism.
*/
__global__ void inplace_fft(Cplx* __restrict__ r, int j, int m, int n, size_t nthr) {
int k = blockIdx.x * nthr + threadIdx.x;
inplace_fft_inner(r, j, k, m, n);
}
/**
* Outer part of FFT for large scope paralelism.
*/
__global__ void inplace_fft_outer(Cplx* __restrict__ r, int m, int n, size_t nthr) {
int j = (blockIdx.x * nthr + threadIdx.x) * m;
for (int k = 0; k < m / 2; k++) {
inplace_fft_inner(r, j, k, m, n);
}
}
/**
* Runs in-place Iterative Fast Fourier Transformation.
*/
void fft(Cplx* __restrict__ d, size_t n, size_t threads, int balance) {
size_t data_size = n * sizeof(Cplx);
Cplx *r, *dn;
// Copy data to GPU
hipMalloc((void**)&r, data_size);
hipMalloc((void**)&dn, data_size);
hipMemcpy(dn, d, data_size, hipMemcpyHostToDevice);
// Bit-reversal reordering
int s = log2(n);
bitrev_reorder<<<ceil(n / threads), threads>>>(r, dn, s, threads);
// Synchronize
hipDeviceSynchronize();
// Iterative FFT (with loop paralelism balancing)
for (int i = 1; i <= s; i++) {
int m = 1 << i;
if (n/m > balance) {
inplace_fft_outer<<<ceil((float)n / m / threads), threads>>>(r, m, n, threads);
} else {
for (int j = 0; j < n; j += m) {
float repeats = m / 2;
inplace_fft<<<ceil(repeats / threads), threads>>>(r, j, m, n, threads);
}
}
}
// Copy data from GPU & free the memory blocks
Cplx* result;
result = (Cplx*)malloc(data_size / 2);
hipMemcpy(result, r, data_size / 2, hipMemcpyDeviceToHost);
hipFree(r);
hipFree(dn);
}
/**
* Reads numeric data from a file.
*/
void read_file(const char* filename, vector<Cplx>& out) {
ifstream file;
file.open(filename);
if (file.is_open()) {
while (!file.eof()) {
Cplx val;
if (file >> val.x) {
val.y = 0;
out.push_back(val);
}
}
} else {
cerr << "Can't open file " << filename << " for reading." << endl;
}
file.close();
}
/**
* Saves the result data to an output file.
*/
void save_results(const char* filename, Cplx* result, size_t count, int sample_rate) {
char* outfilename = new char[512];
// Compose the output filename
strcpy(outfilename, filename);
strcat(outfilename, ".out");
// Create the file
ofstream outfile;
outfile.open (outfilename);
outfile.precision(4);
// Save the data
outfile << "frequency, value" << endl;
for (int i = 0; i < count / 2; i++) {
outfile << i * ((float)sample_rate/count) << "," << result[i].x << endl;
}
outfile.close();
}
void compute_file(const char* filename, int sample_rate, size_t threads, int balance) {
vector<Cplx> buffer;
// Read the file
read_file(filename, buffer);
int count = buffer.size();
// Display active computation
cout << filename << "," << count << "," << sample_rate << "," << threads <<
"," << balance;
cout.flush();
// Start the stopwatch
auto start = chrono::high_resolution_clock::now();
// Run FFT algorithm with loaded data
fft(&buffer[0], count, threads, balance);
// Log the elapsed time
auto finish = chrono::high_resolution_clock::now();
auto microseconds = chrono::duration_cast<std::chrono::microseconds>(finish-start);
cout << "," << microseconds.count() << endl;
// Save the computed data
save_results(filename, &buffer[0], count, sample_rate);
}
int main(int argc, char** argv) {
srand (time(NULL));
// Deal with program arguments
if (argc < 2) {
cerr << "Usage: " << argv[0] << " [input_folder]"; return 2;
}
// Initialize CUDA
hipFree(0);
// Print out the CSV header
cout << "file,samples,sample_rate,threads,balance,elapsed_us" << endl;
// Read the folder
DIR* dirp = opendir(argv[1]);
struct dirent *epdf;
// Compute all files in the folder
while ((epdf = readdir(dirp)) != NULL) {
size_t len = strlen(epdf->d_name);
// Pick only .dat files
if (strcmp(epdf->d_name,".") != 0 && strcmp(epdf->d_name,"..") != 0
&& strcmp(&epdf->d_name[len-3], "dat") == 0) {
stringstream fname(epdf->d_name);
string samples, sr;
// Read file properties
getline(fname, samples, '@');
getline(fname, sr, '.');
char* fold = new char[512];
strcpy(fold, argv[1]);
int smp = atoi(samples.c_str());
// Compute for all set parameters
for (int th = 0; th <= 1024; th <<= 1) {
if (th == 0) th = 1;
for (int bal = 2; bal <= smp / 2; bal <<= 1)
for (int r = 0; r < N_REPEAT; r++) {
char fname[512];
strcpy(fname, fold);
strcat(strcat(fname, "/"), epdf->d_name);
compute_file(fname, atoi(sr.c_str()), th, bal);
}
}
}
}
closedir(dirp);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14bitrev_reorderP15HIP_vector_typeIfLj2EES1_im
.globl _Z14bitrev_reorderP15HIP_vector_typeIfLj2EES1_im
.p2align 8
.type _Z14bitrev_reorderP15HIP_vector_typeIfLj2EES1_im,@function
_Z14bitrev_reorderP15HIP_vector_typeIfLj2EES1_im:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_sub_i32 s0, 32, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_bfrev_b32_e32 v0, v1
v_lshlrev_b64 v[2:3], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshrrev_b32_e32 v0, s0, v0
v_mov_b32_e32 v1, 0
v_add_co_u32 v2, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
v_lshlrev_b64 v[0:1], 3, v[0:1]
global_load_b64 v[2:3], v[2:3], off
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14bitrev_reorderP15HIP_vector_typeIfLj2EES1_im
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14bitrev_reorderP15HIP_vector_typeIfLj2EES1_im, .Lfunc_end0-_Z14bitrev_reorderP15HIP_vector_typeIfLj2EES1_im
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11inplace_fftP15HIP_vector_typeIfLj2EEiiim
.globl _Z11inplace_fftP15HIP_vector_typeIfLj2EEiiim
.p2align 8
.type _Z11inplace_fftP15HIP_vector_typeIfLj2EEiiim,@function
_Z11inplace_fftP15HIP_vector_typeIfLj2EEiiim:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x18
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b32 s5, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, s15, s4, v[0:1]
s_lshr_b32 s4, s3, 31
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v0, s2, v2
s_add_i32 s2, s3, s4
s_ashr_i32 s2, s2, 1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v1, s2, v0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s5, v1
s_cbranch_execz .LBB1_2
v_cvt_f64_i32_e32 v[2:3], v2
s_mov_b32 s5, 0x401921fb
s_mov_b32 s4, 0x54442d18
v_cvt_f64_i32_e32 v[4:5], s3
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f64 v[6:7], v[2:3], s[4:5]
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[2:3], 3, v[1:2]
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[14:15], v[2:3], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_div_scale_f64 v[8:9], null, v[4:5], v[4:5], v[6:7]
v_div_scale_f64 v[18:19], vcc_lo, v[6:7], v[4:5], v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[10:11], v[8:9]
s_waitcnt_depctr 0xfff
v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
global_load_b64 v[12:13], v[0:1], off
v_fma_f64 v[16:17], -v[8:9], v[10:11], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], v[10:11], v[16:17], v[10:11]
v_mul_f64 v[16:17], v[18:19], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], -v[8:9], v[16:17], v[18:19]
v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[4:5], v[8:9], v[4:5], v[6:7]
v_cvt_f32_f64_e32 v4, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, 0.15915494, v4
v_cos_f32_e32 v5, v4
v_sin_f32_e32 v4, v4
s_waitcnt vmcnt(1)
s_waitcnt_depctr 0xfff
v_fma_f32 v6, v5, v14, v4
v_mul_f32_e32 v4, v4, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v6, v15, v6
v_fma_f32 v7, v5, v15, -v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_dual_add_f32 v4, v12, v6 :: v_dual_add_f32 v5, v13, v7
v_dual_sub_f32 v7, v13, v7 :: v_dual_sub_f32 v6, v12, v6
s_clause 0x1
global_store_b64 v[0:1], v[4:5], off
global_store_b64 v[2:3], v[6:7], off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11inplace_fftP15HIP_vector_typeIfLj2EEiiim
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 20
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z11inplace_fftP15HIP_vector_typeIfLj2EEiiim, .Lfunc_end1-_Z11inplace_fftP15HIP_vector_typeIfLj2EEiiim
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z17inplace_fft_outerP15HIP_vector_typeIfLj2EEiim
.globl _Z17inplace_fft_outerP15HIP_vector_typeIfLj2EEiim
.p2align 8
.type _Z17inplace_fft_outerP15HIP_vector_typeIfLj2EEiim,@function
_Z17inplace_fft_outerP15HIP_vector_typeIfLj2EEiim:
s_load_b32 s4, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 2
s_cbranch_scc1 .LBB2_5
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0xc
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_lshr_b32 s3, s4, 31
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v4, v1, s4
v_cvt_f64_i32_e32 v[0:1], s4
s_add_i32 s4, s4, s3
s_ashr_i32 s3, s4, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v4
v_add_nc_u32_e32 v2, s3, v4
v_lshlrev_b64 v[6:7], 3, v[4:5]
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[8:9], 3, v[2:3]
v_add_co_u32 v3, vcc_lo, v6, s0
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v8, vcc_lo, v8, s0
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v6, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v8, vcc_lo, v8, 4
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
s_mov_b32 s1, 0x401921fb
s_mov_b32 s0, 0x54442d18
s_branch .LBB2_3
.LBB2_2:
s_or_b32 exec_lo, exec_lo, s4
v_add_f64 v[4:5], v[4:5], 1.0
v_add_co_u32 v6, vcc_lo, v6, 8
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
v_add_co_u32 v8, vcc_lo, v8, 8
v_add_nc_u32_e32 v2, 1, v2
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s3, 0
s_cbranch_scc1 .LBB2_5
.LBB2_3:
s_mov_b32 s4, exec_lo
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB2_2
v_mul_f64 v[10:11], v[4:5], s[0:1]
s_clause 0x1
global_load_b32 v3, v[8:9], off offset:-4
global_load_b32 v20, v[8:9], off
s_clause 0x1
global_load_b32 v21, v[6:7], off offset:-4
global_load_b32 v22, v[6:7], off
v_div_scale_f64 v[12:13], null, v[0:1], v[0:1], v[10:11]
v_div_scale_f64 v[18:19], vcc_lo, v[10:11], v[0:1], v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[14:15], v[12:13]
s_waitcnt_depctr 0xfff
v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0
v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0
v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[16:17], v[18:19], v[14:15]
v_fma_f64 v[12:13], -v[12:13], v[16:17], v[18:19]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[12:13], v[12:13], v[14:15], v[16:17]
v_div_fixup_f64 v[10:11], v[12:13], v[0:1], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_f64_e32 v10, v[10:11]
v_mul_f32_e32 v10, 0.15915494, v10
s_delay_alu instid0(VALU_DEP_1)
v_cos_f32_e32 v11, v10
v_sin_f32_e32 v10, v10
s_waitcnt vmcnt(3)
s_waitcnt_depctr 0xfff
v_fma_f32 v12, v11, v3, v10
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v3, v10, v3 :: v_dual_add_f32 v10, v20, v12
v_fma_f32 v3, v11, v20, -v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_dual_add_f32 v11, v21, v10 :: v_dual_add_f32 v12, v22, v3
v_dual_sub_f32 v10, v21, v10 :: v_dual_sub_f32 v3, v22, v3
s_clause 0x1
global_store_b32 v[6:7], v11, off offset:-4
global_store_b32 v[6:7], v12, off
s_clause 0x1
global_store_b32 v[8:9], v10, off offset:-4
global_store_b32 v[8:9], v3, off
s_branch .LBB2_2
.LBB2_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17inplace_fft_outerP15HIP_vector_typeIfLj2EEiim
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 23
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z17inplace_fft_outerP15HIP_vector_typeIfLj2EEiim, .Lfunc_end2-_Z17inplace_fft_outerP15HIP_vector_typeIfLj2EEiim
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .actual_access: write_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14bitrev_reorderP15HIP_vector_typeIfLj2EES1_im
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14bitrev_reorderP15HIP_vector_typeIfLj2EES1_im.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11inplace_fftP15HIP_vector_typeIfLj2EEiiim
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11inplace_fftP15HIP_vector_typeIfLj2EEiiim.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 20
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17inplace_fft_outerP15HIP_vector_typeIfLj2EEiim
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17inplace_fft_outerP15HIP_vector_typeIfLj2EEiim.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 23
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include"stdio.h"
//#include "matrixmul.cuh"
#define BLOCK_SIZE 16
#define A_HEIGHT 128
#define A_WIDTH 128
#define B_HEIGHT 128
#define B_WIDTH 128
#define C_HEIGHT A_HEIGHT
#define C_WIDTH B_WIDTH
__global__ void matrix_mulKernel(int *c, int *a, int *b,
int a_height,int a_width, int b_width, int c_width)
{
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
if(row >= a_height || col >= b_width) return;
int i, sum=0;
for(i =0; i<a_width; ++i)
{
sum += a[row * a_width + i] * b[i * b_width + col];
}
c[row * c_width + col] =sum;
}
void matrix_multiplication(const int *a, const int *b, int *c, int a_hiehgt, int b_width, int b_height);
void print_matrix( int *matrix, int height, int width);
int main()
{
int *a = (int*) calloc(A_HEIGHT * A_WIDTH, sizeof(unsigned int) );
int *b = (int*) calloc(B_HEIGHT * B_WIDTH, sizeof(unsigned int) );
int *c = (int*) calloc(C_HEIGHT * C_WIDTH, sizeof(unsigned int) );
int *d = (int*) calloc(C_HEIGHT * C_WIDTH, sizeof(unsigned int) );
int i;
for (i =0; i < A_HEIGHT * A_WIDTH; i++)
{
a[i] = i;
b[i] = i;
}
int *dev_a = 0;
int *dev_b = 0;
int *dev_c = 0;
// Allocate GPU buffers for three vectors (two input, one output) .
cudaMalloc((void**)&dev_c, C_HEIGHT * C_WIDTH * sizeof(unsigned int));
cudaMalloc((void**)&dev_a, A_HEIGHT * A_WIDTH * sizeof(unsigned int));
cudaMalloc((void**)&dev_b, B_HEIGHT * B_WIDTH * sizeof(unsigned int));
// Copy input vectors from host memory to GPU buffers.
cudaMemcpy(dev_a, a, A_HEIGHT * A_WIDTH * sizeof(unsigned int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, B_HEIGHT * B_WIDTH * sizeof(unsigned int), cudaMemcpyHostToDevice);
dim3 dimBlock (BLOCK_SIZE,BLOCK_SIZE); // block( blockIdx, blockIDy)
dim3 grid ((B_WIDTH + dimBlock.x - 1) / dimBlock.x,
(A_HEIGHT + dimBlock.y - 1) / dimBlock.y); // grid(gloalsizeX + blockidx -1)/blockidx,gloalsizeY + blockidy -1)/blockidy);
matrix_mulKernel<<<grid, dimBlock>>>(dev_c, dev_a, dev_b, A_HEIGHT, A_WIDTH, B_WIDTH, C_WIDTH);
// Copy output vector from GPU buffer to host memory.
cudaMemcpy(c, dev_c, C_HEIGHT * C_WIDTH * sizeof(int), cudaMemcpyDeviceToHost);
matrix_multiplication(a, b ,d, A_HEIGHT, B_WIDTH, B_HEIGHT);
bool flag = true;
for(int i = 0; i < A_HEIGHT * B_WIDTH; i++ )
{
if (c[i] != d[i])
{
printf("Verification fail\n");
flag = false;
break;
}
}
if (flag)
printf("Verification pass\n");
//printf("Matrix A:\n");
//print_matrix(a, size);
//printf("Matrix B:\n");
//print_matrix(b, size);
printf("Matrix C:\n");
print_matrix(c, 10, 10);
printf("Matrix D:\n");
print_matrix(d,10, 10);
}
void matrix_multiplication(const int *a, const int *b, int *c, int a_height, int b_width, int b_height)
{
for(int i = 0; i < a_height; i++)
{
for(int j = 0; j < b_width; j++)
{
int sum = 0;
for(int k = 0; k < b_height ; k++)
{
sum+= a[i * b_height + k] * b[k * b_width + j];
}
c[i * b_width + j] = sum;
}
}
}
void print_matrix( int *matrix, int height, int width)
{
int i , j;
for(i = 0; i < width; i++)
{
for(j = 0; j < height; j++)
printf("%5d", matrix[i * width + j]);
printf("\n");
}
} | code for sm_80
Function : _Z16matrix_mulKernelPiS_S_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R4, c[0x0][0x17c] ; /* 0x00005f0000047a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe400000001ff */
/*00d0*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0xc30 ; /* 0x00000b4000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R2, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x040fe40007ffe0ff */
/*0100*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe400078ec0ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*0120*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fe40000000f00 */
/*0130*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fd20000000f00 */
/*0140*/ @!P0 BRA 0xb20 ; /* 0x000009d000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R5, -R4, c[0x0][0x17c], RZ ; /* 0x00005f0004057a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0170*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0180*/ IMAD R6, R3, c[0x0][0x17c], RZ ; /* 0x00005f0003067a24 */
/* 0x000fe200078e02ff */
/*0190*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f04270 */
/*01a0*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fca0000000f00 */
/*01b0*/ IMAD.WIDE R8, R0, R9, c[0x0][0x170] ; /* 0x00005c0000087625 */
/* 0x000fcc00078e0209 */
/*01c0*/ @!P0 BRA 0x980 ; /* 0x000007b000008947 */
/* 0x000fea0003800000 */
/*01d0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01f0*/ @!P1 BRA 0x6b0 ; /* 0x000004b000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0220*/ LDG.E R21, [R8.64] ; /* 0x0000000408157981 */
/* 0x0000a2000c1e1900 */
/*0230*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0240*/ IMAD.WIDE R12, R6, 0x4, R12 ; /* 0x00000004060c7825 */
/* 0x000fca00078e020c */
/*0250*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x000ea2000c1e1900 */
/*0260*/ MOV R7, c[0x0][0x180] ; /* 0x0000600000077a02 */
/* 0x000fc60000000f00 */
/*0270*/ LDG.E R14, [R12.64+0x4] ; /* 0x000004040c0e7981 */
/* 0x000ee4000c1e1900 */
/*0280*/ IMAD.WIDE R10, R7.reuse, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x040fe400078e0208 */
/*0290*/ LDG.E R27, [R12.64+0x8] ; /* 0x000008040c1b7981 */
/* 0x000f28000c1e1900 */
/*02a0*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x0002e2000c1e1900 */
/*02b0*/ IMAD.WIDE R22, R7, 0x4, R10 ; /* 0x0000000407167825 */
/* 0x000fc600078e020a */
/*02c0*/ LDG.E R18, [R12.64+0xc] ; /* 0x00000c040c127981 */
/* 0x000f66000c1e1900 */
/*02d0*/ IMAD.WIDE R28, R7.reuse, 0x4, R22 ; /* 0x00000004071c7825 */
/* 0x040fe200078e0216 */
/*02e0*/ LDG.E R26, [R22.64] ; /* 0x00000004161a7981 */
/* 0x000328000c1e1900 */
/*02f0*/ LDG.E R19, [R28.64] ; /* 0x000000041c137981 */
/* 0x000362000c1e1900 */
/*0300*/ IMAD.WIDE R16, R7, 0x4, R28 ; /* 0x0000000407107825 */
/* 0x000fc600078e021c */
/*0310*/ LDG.E R8, [R12.64+0x10] ; /* 0x000010040c087981 */
/* 0x001f68000c1e1900 */
/*0320*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000168000c1e1900 */
/*0330*/ LDG.E R10, [R12.64+0x14] ; /* 0x000014040c0a7981 */
/* 0x002f68000c1e1900 */
/*0340*/ LDG.E R28, [R12.64+0x1c] ; /* 0x00001c040c1c7981 */
/* 0x000f62000c1e1900 */
/*0350*/ IMAD.WIDE R16, R7, 0x4, R16 ; /* 0x0000000407107825 */
/* 0x001fca00078e0210 */
/*0360*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x000562000c1e1900 */
/*0370*/ IMAD.WIDE R22, R7, 0x4, R16 ; /* 0x0000000407167825 */
/* 0x000fc800078e0210 */
/*0380*/ IMAD R16, R21, R20, R24 ; /* 0x0000001415107224 */
/* 0x004fe400078e0218 */
/*0390*/ LDG.E R20, [R12.64+0x18] ; /* 0x000018040c147981 */
/* 0x000ea2000c1e1900 */
/*03a0*/ IMAD.WIDE R24, R7, 0x4, R22 ; /* 0x0000000407187825 */
/* 0x000fc600078e0216 */
/*03b0*/ LDG.E R21, [R22.64] ; /* 0x0000000416157981 */
/* 0x0000a8000c1e1900 */
/*03c0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0002a2000c1e1900 */
/*03d0*/ IMAD R16, R15, R14, R16 ; /* 0x0000000e0f107224 */
/* 0x008fe400078e0210 */
/*03e0*/ IMAD.WIDE R14, R7.reuse, 0x4, R24 ; /* 0x00000004070e7825 */
/* 0x040fe200078e0218 */
/*03f0*/ LDG.E R23, [R12.64+0x20] ; /* 0x000020040c177981 */
/* 0x001ee6000c1e1900 */
/*0400*/ IMAD R26, R26, R27, R16 ; /* 0x0000001b1a1a7224 */
/* 0x010fe200078e0210 */
/*0410*/ LDG.E R25, [R12.64+0x24] ; /* 0x000024040c197981 */
/* 0x002f22000c1e1900 */
/*0420*/ IMAD.WIDE R16, R7, 0x4, R14 ; /* 0x0000000407107825 */
/* 0x000fc600078e020e */
/*0430*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0000e2000c1e1900 */
/*0440*/ IMAD R26, R19, R18, R26 ; /* 0x00000012131a7224 */
/* 0x020fe400078e021a */
/*0450*/ IMAD.WIDE R18, R7, 0x4, R16 ; /* 0x0000000407127825 */
/* 0x000fe200078e0210 */
/*0460*/ LDG.E R22, [R12.64+0x28] ; /* 0x000028040c167981 */
/* 0x000f66000c1e1900 */
/*0470*/ IMAD R26, R9, R8, R26 ; /* 0x00000008091a7224 */
/* 0x000fe200078e021a */
/*0480*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000322000c1e1900 */
/*0490*/ IMAD.WIDE R8, R7, 0x4, R18 ; /* 0x0000000407087825 */
/* 0x000fc600078e0212 */
/*04a0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000368000c1e1900 */
/*04b0*/ LDG.E R24, [R8.64] ; /* 0x0000000408187981 */
/* 0x000568000c1e1900 */
/*04c0*/ LDG.E R15, [R12.64+0x2c] ; /* 0x00002c040c0f7981 */
/* 0x001f62000c1e1900 */
/*04d0*/ IMAD R26, R11, R10, R26 ; /* 0x0000000a0b1a7224 */
/* 0x000fe400078e021a */
/*04e0*/ IMAD.WIDE R10, R7, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x000fe200078e0208 */
/*04f0*/ LDG.E R17, [R12.64+0x30] ; /* 0x000030040c117981 */
/* 0x002f66000c1e1900 */
/*0500*/ IMAD R26, R21, R20, R26 ; /* 0x00000014151a7224 */
/* 0x004fc400078e021a */
/*0510*/ IMAD.WIDE R20, R7, 0x4, R10 ; /* 0x0000000407147825 */
/* 0x000fe400078e020a */
/*0520*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x0000a4000c1e1900 */
/*0530*/ IMAD R28, R29, R28, R26 ; /* 0x0000001c1d1c7224 */
/* 0x000fe400078e021a */
/*0540*/ IMAD.WIDE R26, R7.reuse, 0x4, R20 ; /* 0x00000004071a7825 */
/* 0x040fe200078e0214 */
/*0550*/ LDG.E R29, [R12.64+0x34] ; /* 0x000034040c1d7981 */
/* 0x000ea8000c1e1900 */
/*0560*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x0002a2000c1e1900 */
/*0570*/ IMAD.WIDE R8, R7, 0x4, R26 ; /* 0x0000000407087825 */
/* 0x000fc600078e021a */
/*0580*/ LDG.E R19, [R26.64] ; /* 0x000000041a137981 */
/* 0x0006a8000c1e1900 */
/*0590*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0010a8000c1e1900 */
/*05a0*/ LDG.E R21, [R12.64+0x38] ; /* 0x000038040c157981 */
/* 0x002ea8000c1e1900 */
/*05b0*/ LDG.E R26, [R12.64+0x3c] ; /* 0x00003c040c1a7981 */
/* 0x008ee2000c1e1900 */
/*05c0*/ IMAD R14, R14, R23, R28 ; /* 0x000000170e0e7224 */
/* 0x000fc800078e021c */
/*05d0*/ IMAD R25, R16, R25, R14 ; /* 0x0000001910197224 */
/* 0x010fe200078e020e */
/*05e0*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fc60007ffe0ff */
/*05f0*/ IMAD R18, R18, R22, R25 ; /* 0x0000001612127224 */
/* 0x020fe200078e0219 */
/*0600*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fc60003f24270 */
/*0610*/ IMAD R15, R24, R15, R18 ; /* 0x0000000f180f7224 */
/* 0x000fe200078e0212 */
/*0620*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0630*/ IMAD.WIDE R8, R7, 0x4, R8 ; /* 0x0000000407087825 */
/* 0x001fc600078e0208 */
/*0640*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0650*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe20007ffe0ff */
/*0660*/ IMAD R10, R10, R17, R15 ; /* 0x000000110a0a7224 */
/* 0x004fc800078e020f */
/*0670*/ IMAD R10, R20, R29, R10 ; /* 0x0000001d140a7224 */
/* 0x000fc800078e020a */
/*0680*/ IMAD R10, R19, R21, R10 ; /* 0x00000015130a7224 */
/* 0x000fc800078e020a */
/*0690*/ IMAD R24, R11, R26, R10 ; /* 0x0000001a0b187224 */
/* 0x008fe200078e020a */
/*06a0*/ @P1 BRA 0x210 ; /* 0xfffffb6000001947 */
/* 0x000fea000383ffff */
/*06b0*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*06c0*/ @!P1 BRA 0x960 ; /* 0x0000029000009947 */
/* 0x000fea0003800000 */
/*06d0*/ MOV R7, c[0x0][0x180] ; /* 0x0000600000077a02 */
/* 0x000fe20000000f00 */
/*06e0*/ LDG.E R23, [R8.64] ; /* 0x0000000408177981 */
/* 0x0000a2000c1e1900 */
/*06f0*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*0700*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe20008000f00 */
/*0710*/ IMAD.WIDE R16, R7, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x000fc800078e0208 */
/*0720*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*0730*/ IMAD.WIDE R12, R7.reuse, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x040fe200078e0210 */
/*0740*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x000ea8000c1e1900 */
/*0750*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0002e2000c1e1900 */
/*0760*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0770*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee6000c1e1900 */
/*0780*/ IMAD.WIDE R18, R7.reuse, 0x4, R14 ; /* 0x0000000407127825 */
/* 0x040fe200078e020e */
/*0790*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000968000c1e1900 */
/*07a0*/ LDG.E R27, [R10.64+0x8] ; /* 0x000008040a1b7981 */
/* 0x000f62000c1e1900 */
/*07b0*/ IMAD.WIDE R20, R7, 0x4, R18 ; /* 0x0000000407147825 */
/* 0x000fc600078e0212 */
/*07c0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07d0*/ LDG.E R29, [R10.64+0xc] ; /* 0x00000c040a1d7981 */
/* 0x000f62000c1e1900 */
/*07e0*/ IMAD.WIDE R8, R7, 0x4, R20 ; /* 0x0000000407087825 */
/* 0x001fc600078e0214 */
/*07f0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000168000c1e1900 */
/*0800*/ LDG.E R28, [R10.64+0x10] ; /* 0x000010040a1c7981 */
/* 0x000f62000c1e1900 */
/*0810*/ IMAD.WIDE R12, R7, 0x4, R8 ; /* 0x00000004070c7825 */
/* 0x010fc600078e0208 */
/*0820*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000968000c1e1900 */
/*0830*/ LDG.E R15, [R10.64+0x14] ; /* 0x000014040a0f7981 */
/* 0x002f68000c1e1900 */
/*0840*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000368000c1e1900 */
/*0850*/ LDG.E R21, [R10.64+0x1c] ; /* 0x00001c040a157981 */
/* 0x010f28000c1e1900 */
/*0860*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x001f28000c1e1900 */
/*0870*/ LDG.E R8, [R10.64+0x18] ; /* 0x000018040a087981 */
/* 0x002f22000c1e1900 */
/*0880*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0890*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*08a0*/ IADD3 R2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fe40007ffe0ff */
/*08b0*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*08c0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08d0*/ IMAD R22, R23, R22, R24 ; /* 0x0000001617167224 */
/* 0x004fc800078e0218 */
/*08e0*/ IMAD R16, R16, R25, R22 ; /* 0x0000001910107224 */
/* 0x008fc800078e0216 */
/*08f0*/ IMAD R16, R26, R27, R16 ; /* 0x0000001b1a107224 */
/* 0x020fc800078e0210 */
/*0900*/ IMAD R29, R14, R29, R16 ; /* 0x0000001d0e1d7224 */
/* 0x000fc800078e0210 */
/*0910*/ IMAD R18, R18, R28, R29 ; /* 0x0000001c12127224 */
/* 0x000fc800078e021d */
/*0920*/ IMAD R15, R20, R15, R18 ; /* 0x0000000f140f7224 */
/* 0x000fc800078e0212 */
/*0930*/ IMAD R24, R17, R8, R15 ; /* 0x0000000811187224 */
/* 0x010fe400078e020f */
/*0940*/ IMAD.WIDE R8, R7, 0x4, R12 ; /* 0x0000000407087825 */
/* 0x000fc800078e020c */
/*0950*/ IMAD R24, R19, R21, R24 ; /* 0x0000001513187224 */
/* 0x000fe400078e0218 */
/*0960*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0970*/ @!P0 BRA 0xb20 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0980*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*0990*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe40008000f00 */
/*09a0*/ MOV R7, c[0x0][0x180] ; /* 0x0000600000077a02 */
/* 0x000fc60000000f00 */
/*09b0*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*09c0*/ IMAD.WIDE R16, R7.reuse, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x040fe200078e0208 */
/*09d0*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*09f0*/ IMAD.WIDE R12, R7, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x000fc600078e0210 */
/*0a00*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ee8000c1e1900 */
/*0a10*/ LDG.E R19, [R10.64+0x4] ; /* 0x000004040a137981 */
/* 0x000ee2000c1e1900 */
/*0a20*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0a30*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000f28000c1e1900 */
/*0a40*/ LDG.E R20, [R10.64+0x8] ; /* 0x000008040a147981 */
/* 0x000f28000c1e1900 */
/*0a50*/ LDG.E R22, [R10.64+0xc] ; /* 0x00000c040a167981 */
/* 0x000f68000c1e1900 */
/*0a60*/ LDG.E R23, [R14.64] ; /* 0x000000040e177981 */
/* 0x000f62000c1e1900 */
/*0a70*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fc80007ffe0ff */
/*0a80*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0a90*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0aa0*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fc60007ffe0ff */
/*0ab0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0ac0*/ IMAD R18, R9, R18, R24 ; /* 0x0000001209127224 */
/* 0x004fc800078e0218 */
/*0ad0*/ IMAD R18, R17, R19, R18 ; /* 0x0000001311127224 */
/* 0x008fe400078e0212 */
/*0ae0*/ IMAD.WIDE R8, R7, 0x4, R14 ; /* 0x0000000407087825 */
/* 0x000fc800078e020e */
/*0af0*/ IMAD R18, R21, R20, R18 ; /* 0x0000001415127224 */
/* 0x010fc800078e0212 */
/*0b00*/ IMAD R24, R23, R22, R18 ; /* 0x0000001617187224 */
/* 0x020fe200078e0212 */
/*0b10*/ @P0 BRA 0x980 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0b20*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0b30*/ @!P0 BRA 0xc30 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0b40*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b50*/ IMAD R6, R3, c[0x0][0x17c], R2 ; /* 0x00005f0003067a24 */
/* 0x000fe400078e0202 */
/*0b60*/ IMAD R2, R2, c[0x0][0x180], R0 ; /* 0x0000600002027a24 */
/* 0x000fce00078e0200 */
/*0b70*/ IMAD.WIDE R6, R6, R9, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e0209 */
/*0b80*/ IMAD.WIDE R8, R2, R9, c[0x0][0x170] ; /* 0x00005c0002087625 */
/* 0x000fca00078e0209 */
/*0b90*/ LDG.E R5, [R8.64] ; /* 0x0000000408057981 */
/* 0x0000a8000c1e1900 */
/*0ba0*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x0002a2000c1e1900 */
/*0bb0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0bc0*/ MOV R11, c[0x0][0x180] ; /* 0x00006000000b7a02 */
/* 0x000fe40000000f00 */
/*0bd0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*0be0*/ IMAD.WIDE R8, R11, 0x4, R8 ; /* 0x000000040b087825 */
/* 0x001fe200078e0208 */
/*0bf0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0c00*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0c10*/ IMAD R24, R5, R2, R24 ; /* 0x0000000205187224 */
/* 0x004fc800078e0218 */
/*0c20*/ @P0 BRA 0xb90 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0c30*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0c40*/ IMAD R3, R3, c[0x0][0x184], R0 ; /* 0x0000610003037a24 */
/* 0x000fc800078e0200 */
/*0c50*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0202 */
/*0c60*/ STG.E [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x000fe2000c101904 */
/*0c70*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c80*/ BRA 0xc80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include"stdio.h"
//#include "matrixmul.cuh"
#define BLOCK_SIZE 16
#define A_HEIGHT 128
#define A_WIDTH 128
#define B_HEIGHT 128
#define B_WIDTH 128
#define C_HEIGHT A_HEIGHT
#define C_WIDTH B_WIDTH
__global__ void matrix_mulKernel(int *c, int *a, int *b,
int a_height,int a_width, int b_width, int c_width)
{
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
if(row >= a_height || col >= b_width) return;
int i, sum=0;
for(i =0; i<a_width; ++i)
{
sum += a[row * a_width + i] * b[i * b_width + col];
}
c[row * c_width + col] =sum;
}
void matrix_multiplication(const int *a, const int *b, int *c, int a_hiehgt, int b_width, int b_height);
void print_matrix( int *matrix, int height, int width);
int main()
{
int *a = (int*) calloc(A_HEIGHT * A_WIDTH, sizeof(unsigned int) );
int *b = (int*) calloc(B_HEIGHT * B_WIDTH, sizeof(unsigned int) );
int *c = (int*) calloc(C_HEIGHT * C_WIDTH, sizeof(unsigned int) );
int *d = (int*) calloc(C_HEIGHT * C_WIDTH, sizeof(unsigned int) );
int i;
for (i =0; i < A_HEIGHT * A_WIDTH; i++)
{
a[i] = i;
b[i] = i;
}
int *dev_a = 0;
int *dev_b = 0;
int *dev_c = 0;
// Allocate GPU buffers for three vectors (two input, one output) .
cudaMalloc((void**)&dev_c, C_HEIGHT * C_WIDTH * sizeof(unsigned int));
cudaMalloc((void**)&dev_a, A_HEIGHT * A_WIDTH * sizeof(unsigned int));
cudaMalloc((void**)&dev_b, B_HEIGHT * B_WIDTH * sizeof(unsigned int));
// Copy input vectors from host memory to GPU buffers.
cudaMemcpy(dev_a, a, A_HEIGHT * A_WIDTH * sizeof(unsigned int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, B_HEIGHT * B_WIDTH * sizeof(unsigned int), cudaMemcpyHostToDevice);
dim3 dimBlock (BLOCK_SIZE,BLOCK_SIZE); // block( blockIdx, blockIDy)
dim3 grid ((B_WIDTH + dimBlock.x - 1) / dimBlock.x,
(A_HEIGHT + dimBlock.y - 1) / dimBlock.y); // grid(gloalsizeX + blockidx -1)/blockidx,gloalsizeY + blockidy -1)/blockidy);
matrix_mulKernel<<<grid, dimBlock>>>(dev_c, dev_a, dev_b, A_HEIGHT, A_WIDTH, B_WIDTH, C_WIDTH);
// Copy output vector from GPU buffer to host memory.
cudaMemcpy(c, dev_c, C_HEIGHT * C_WIDTH * sizeof(int), cudaMemcpyDeviceToHost);
matrix_multiplication(a, b ,d, A_HEIGHT, B_WIDTH, B_HEIGHT);
bool flag = true;
for(int i = 0; i < A_HEIGHT * B_WIDTH; i++ )
{
if (c[i] != d[i])
{
printf("Verification fail\n");
flag = false;
break;
}
}
if (flag)
printf("Verification pass\n");
//printf("Matrix A:\n");
//print_matrix(a, size);
//printf("Matrix B:\n");
//print_matrix(b, size);
printf("Matrix C:\n");
print_matrix(c, 10, 10);
printf("Matrix D:\n");
print_matrix(d,10, 10);
}
void matrix_multiplication(const int *a, const int *b, int *c, int a_height, int b_width, int b_height)
{
for(int i = 0; i < a_height; i++)
{
for(int j = 0; j < b_width; j++)
{
int sum = 0;
for(int k = 0; k < b_height ; k++)
{
sum+= a[i * b_height + k] * b[k * b_width + j];
}
c[i * b_width + j] = sum;
}
}
}
void print_matrix( int *matrix, int height, int width)
{
int i , j;
for(i = 0; i < width; i++)
{
for(j = 0; j < height; j++)
printf("%5d", matrix[i * width + j]);
printf("\n");
}
} | .file "tmpxft_000b773b_00000000-6_matrixmul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z21matrix_multiplicationPKiS0_Piiii
.type _Z21matrix_multiplicationPKiS0_Piiii, @function
_Z21matrix_multiplicationPKiS0_Piiii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rsi, -16(%rsp)
movq %rdx, -8(%rsp)
movl %ecx, -20(%rsp)
testl %ecx, %ecx
jle .L3
movl %r8d, %edx
movl %r9d, %r11d
movslq %r8d, %r12
leaq 0(,%r12,4), %r8
movl $0, %r13d
movl $0, %ecx
movl $0, %eax
movslq %r9d, %r15
movq %rdi, %rsi
movq %r15, %rdi
jmp .L5
.L6:
movl (%rax), %ecx
imull (%r9), %ecx
addl %ecx, %r13d
addq $4, %rax
addq %r8, %r9
cmpq %r10, %rax
jne .L6
.L8:
movl %r13d, (%r14,%rbx,4)
addq $1, %rbx
addq $4, %rbp
cmpq %rbx, %r12
je .L13
.L9:
movq %rbp, %r9
movq %r15, %rax
movl $0, %r13d
testl %r11d, %r11d
jg .L6
jmp .L8
.L13:
movl -32(%rsp), %eax
movl -28(%rsp), %ecx
movl -24(%rsp), %r13d
.L7:
addl $1, %eax
addl %edx, %ecx
addl %r11d, %r13d
cmpl %eax, -20(%rsp)
je .L3
.L5:
testl %edx, %edx
jle .L7
movq -16(%rsp), %rbp
movslq %r13d, %r9
leaq (%rsi,%r9,4), %r15
addq %rdi, %r9
leaq (%rsi,%r9,4), %r10
movslq %ecx, %r9
movq -8(%rsp), %rbx
leaq (%rbx,%r9,4), %r14
movl $0, %ebx
movl %eax, -32(%rsp)
movl %ecx, -28(%rsp)
movl %r13d, -24(%rsp)
jmp .L9
.L3:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z21matrix_multiplicationPKiS0_Piiii, .-_Z21matrix_multiplicationPKiS0_Piiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%5d"
.LC1:
.string "\n"
.text
.globl _Z12print_matrixPiii
.type _Z12print_matrixPiii, @function
_Z12print_matrixPiii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
movl %esi, 12(%rsp)
testl %edx, %edx
jle .L16
movl %edx, %r15d
movl $0, %r14d
movl $0, %r13d
movslq %esi, %rax
movq %rax, 24(%rsp)
leaq .LC0(%rip), %r12
jmp .L18
.L20:
movslq %r14d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 24(%rsp), %rsi
addq %rsi, %rax
leaq (%rcx,%rax,4), %rbp
.L19:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L19
.L21:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addl %r15d, %r14d
cmpl %r13d, %r15d
je .L16
.L18:
cmpl $0, 12(%rsp)
jg .L20
jmp .L21
.L16:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z12print_matrixPiii, .-_Z12print_matrixPiii
.globl _Z44__device_stub__Z16matrix_mulKernelPiS_S_iiiiPiS_S_iiii
.type _Z44__device_stub__Z16matrix_mulKernelPiS_S_iiiiPiS_S_iiii, @function
_Z44__device_stub__Z16matrix_mulKernelPiS_S_iiiiPiS_S_iiii:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16matrix_mulKernelPiS_S_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L24
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z44__device_stub__Z16matrix_mulKernelPiS_S_iiiiPiS_S_iiii, .-_Z44__device_stub__Z16matrix_mulKernelPiS_S_iiiiPiS_S_iiii
.globl _Z16matrix_mulKernelPiS_S_iiii
.type _Z16matrix_mulKernelPiS_S_iiii, @function
_Z16matrix_mulKernelPiS_S_iiii:
.LFB2085:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z44__device_stub__Z16matrix_mulKernelPiS_S_iiiiPiS_S_iiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z16matrix_mulKernelPiS_S_iiii, .-_Z16matrix_mulKernelPiS_S_iiii
.section .rodata.str1.1
.LC2:
.string "Verification fail\n"
.LC3:
.string "Verification pass\n"
.LC4:
.string "Matrix C:\n"
.LC5:
.string "Matrix D:\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4, %esi
movl $16384, %edi
call calloc@PLT
movq %rax, %rbx
movl $4, %esi
movl $16384, %edi
call calloc@PLT
movq %rax, %rbp
movl $4, %esi
movl $16384, %edi
call calloc@PLT
movq %rax, %r13
movl $4, %esi
movl $16384, %edi
call calloc@PLT
movq %rax, %r12
movl $0, %eax
.L33:
movl %eax, (%rbx,%rax,4)
movl %eax, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $16384, %rax
jne .L33
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movq $0, 24(%rsp)
leaq 24(%rsp), %rdi
movl $65536, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $65536, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $65536, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $65536, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $65536, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $8, 44(%rsp)
movl $8, 48(%rsp)
movl $16, 32(%rsp)
movl $16, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L34:
movl $2, %ecx
movl $65536, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $128, %r9d
movl $128, %r8d
movl $128, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z21matrix_multiplicationPKiS0_Piiii
movl $0, %eax
.L37:
movl (%r12,%rax), %ecx
cmpl %ecx, 0(%r13,%rax)
jne .L43
addq $4, %rax
cmpq $65536, %rax
jne .L37
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L36
.L42:
subq $8, %rsp
.cfi_def_cfa_offset 120
pushq $128
.cfi_def_cfa_offset 128
movl $128, %r9d
movl $128, %r8d
movl $128, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z44__device_stub__Z16matrix_mulKernelPiS_S_iiiiPiS_S_iiii
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L34
.L43:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L36:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $10, %edx
movl $10, %esi
movq %r13, %rdi
call _Z12print_matrixPiii
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $10, %edx
movl $10, %esi
movq %r12, %rdi
call _Z12print_matrixPiii
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L44
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "_Z16matrix_mulKernelPiS_S_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z16matrix_mulKernelPiS_S_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include"stdio.h"
//#include "matrixmul.cuh"
#define BLOCK_SIZE 16
#define A_HEIGHT 128
#define A_WIDTH 128
#define B_HEIGHT 128
#define B_WIDTH 128
#define C_HEIGHT A_HEIGHT
#define C_WIDTH B_WIDTH
__global__ void matrix_mulKernel(int *c, int *a, int *b,
int a_height,int a_width, int b_width, int c_width)
{
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
if(row >= a_height || col >= b_width) return;
int i, sum=0;
for(i =0; i<a_width; ++i)
{
sum += a[row * a_width + i] * b[i * b_width + col];
}
c[row * c_width + col] =sum;
}
void matrix_multiplication(const int *a, const int *b, int *c, int a_hiehgt, int b_width, int b_height);
void print_matrix( int *matrix, int height, int width);
int main()
{
int *a = (int*) calloc(A_HEIGHT * A_WIDTH, sizeof(unsigned int) );
int *b = (int*) calloc(B_HEIGHT * B_WIDTH, sizeof(unsigned int) );
int *c = (int*) calloc(C_HEIGHT * C_WIDTH, sizeof(unsigned int) );
int *d = (int*) calloc(C_HEIGHT * C_WIDTH, sizeof(unsigned int) );
int i;
for (i =0; i < A_HEIGHT * A_WIDTH; i++)
{
a[i] = i;
b[i] = i;
}
int *dev_a = 0;
int *dev_b = 0;
int *dev_c = 0;
// Allocate GPU buffers for three vectors (two input, one output) .
cudaMalloc((void**)&dev_c, C_HEIGHT * C_WIDTH * sizeof(unsigned int));
cudaMalloc((void**)&dev_a, A_HEIGHT * A_WIDTH * sizeof(unsigned int));
cudaMalloc((void**)&dev_b, B_HEIGHT * B_WIDTH * sizeof(unsigned int));
// Copy input vectors from host memory to GPU buffers.
cudaMemcpy(dev_a, a, A_HEIGHT * A_WIDTH * sizeof(unsigned int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, B_HEIGHT * B_WIDTH * sizeof(unsigned int), cudaMemcpyHostToDevice);
dim3 dimBlock (BLOCK_SIZE,BLOCK_SIZE); // block( blockIdx, blockIDy)
dim3 grid ((B_WIDTH + dimBlock.x - 1) / dimBlock.x,
(A_HEIGHT + dimBlock.y - 1) / dimBlock.y); // grid(gloalsizeX + blockidx -1)/blockidx,gloalsizeY + blockidy -1)/blockidy);
matrix_mulKernel<<<grid, dimBlock>>>(dev_c, dev_a, dev_b, A_HEIGHT, A_WIDTH, B_WIDTH, C_WIDTH);
// Copy output vector from GPU buffer to host memory.
cudaMemcpy(c, dev_c, C_HEIGHT * C_WIDTH * sizeof(int), cudaMemcpyDeviceToHost);
matrix_multiplication(a, b ,d, A_HEIGHT, B_WIDTH, B_HEIGHT);
bool flag = true;
for(int i = 0; i < A_HEIGHT * B_WIDTH; i++ )
{
if (c[i] != d[i])
{
printf("Verification fail\n");
flag = false;
break;
}
}
if (flag)
printf("Verification pass\n");
//printf("Matrix A:\n");
//print_matrix(a, size);
//printf("Matrix B:\n");
//print_matrix(b, size);
printf("Matrix C:\n");
print_matrix(c, 10, 10);
printf("Matrix D:\n");
print_matrix(d,10, 10);
}
void matrix_multiplication(const int *a, const int *b, int *c, int a_height, int b_width, int b_height)
{
for(int i = 0; i < a_height; i++)
{
for(int j = 0; j < b_width; j++)
{
int sum = 0;
for(int k = 0; k < b_height ; k++)
{
sum+= a[i * b_height + k] * b[k * b_width + j];
}
c[i * b_width + j] = sum;
}
}
}
void print_matrix( int *matrix, int height, int width)
{
int i , j;
for(i = 0; i < width; i++)
{
for(j = 0; j < height; j++)
printf("%5d", matrix[i * width + j]);
printf("\n");
}
} | #include "hip/hip_runtime.h"
#include"stdio.h"
//#include "matrixmul.cuh"
#define BLOCK_SIZE 16
#define A_HEIGHT 128
#define A_WIDTH 128
#define B_HEIGHT 128
#define B_WIDTH 128
#define C_HEIGHT A_HEIGHT
#define C_WIDTH B_WIDTH
__global__ void matrix_mulKernel(int *c, int *a, int *b,
int a_height,int a_width, int b_width, int c_width)
{
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
if(row >= a_height || col >= b_width) return;
int i, sum=0;
for(i =0; i<a_width; ++i)
{
sum += a[row * a_width + i] * b[i * b_width + col];
}
c[row * c_width + col] =sum;
}
void matrix_multiplication(const int *a, const int *b, int *c, int a_hiehgt, int b_width, int b_height);
void print_matrix( int *matrix, int height, int width);
int main()
{
int *a = (int*) calloc(A_HEIGHT * A_WIDTH, sizeof(unsigned int) );
int *b = (int*) calloc(B_HEIGHT * B_WIDTH, sizeof(unsigned int) );
int *c = (int*) calloc(C_HEIGHT * C_WIDTH, sizeof(unsigned int) );
int *d = (int*) calloc(C_HEIGHT * C_WIDTH, sizeof(unsigned int) );
int i;
for (i =0; i < A_HEIGHT * A_WIDTH; i++)
{
a[i] = i;
b[i] = i;
}
int *dev_a = 0;
int *dev_b = 0;
int *dev_c = 0;
// Allocate GPU buffers for three vectors (two input, one output) .
hipMalloc((void**)&dev_c, C_HEIGHT * C_WIDTH * sizeof(unsigned int));
hipMalloc((void**)&dev_a, A_HEIGHT * A_WIDTH * sizeof(unsigned int));
hipMalloc((void**)&dev_b, B_HEIGHT * B_WIDTH * sizeof(unsigned int));
// Copy input vectors from host memory to GPU buffers.
hipMemcpy(dev_a, a, A_HEIGHT * A_WIDTH * sizeof(unsigned int), hipMemcpyHostToDevice);
hipMemcpy(dev_b, b, B_HEIGHT * B_WIDTH * sizeof(unsigned int), hipMemcpyHostToDevice);
dim3 dimBlock (BLOCK_SIZE,BLOCK_SIZE); // block( blockIdx, blockIDy)
dim3 grid ((B_WIDTH + dimBlock.x - 1) / dimBlock.x,
(A_HEIGHT + dimBlock.y - 1) / dimBlock.y); // grid(gloalsizeX + blockidx -1)/blockidx,gloalsizeY + blockidy -1)/blockidy);
matrix_mulKernel<<<grid, dimBlock>>>(dev_c, dev_a, dev_b, A_HEIGHT, A_WIDTH, B_WIDTH, C_WIDTH);
// Copy output vector from GPU buffer to host memory.
hipMemcpy(c, dev_c, C_HEIGHT * C_WIDTH * sizeof(int), hipMemcpyDeviceToHost);
matrix_multiplication(a, b ,d, A_HEIGHT, B_WIDTH, B_HEIGHT);
bool flag = true;
for(int i = 0; i < A_HEIGHT * B_WIDTH; i++ )
{
if (c[i] != d[i])
{
printf("Verification fail\n");
flag = false;
break;
}
}
if (flag)
printf("Verification pass\n");
//printf("Matrix A:\n");
//print_matrix(a, size);
//printf("Matrix B:\n");
//print_matrix(b, size);
printf("Matrix C:\n");
print_matrix(c, 10, 10);
printf("Matrix D:\n");
print_matrix(d,10, 10);
}
void matrix_multiplication(const int *a, const int *b, int *c, int a_height, int b_width, int b_height)
{
for(int i = 0; i < a_height; i++)
{
for(int j = 0; j < b_width; j++)
{
int sum = 0;
for(int k = 0; k < b_height ; k++)
{
sum+= a[i * b_height + k] * b[k * b_width + j];
}
c[i * b_width + j] = sum;
}
}
}
void print_matrix( int *matrix, int height, int width)
{
int i , j;
for(i = 0; i < width; i++)
{
for(j = 0; j < height; j++)
printf("%5d", matrix[i * width + j]);
printf("\n");
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include"stdio.h"
//#include "matrixmul.cuh"
#define BLOCK_SIZE 16
#define A_HEIGHT 128
#define A_WIDTH 128
#define B_HEIGHT 128
#define B_WIDTH 128
#define C_HEIGHT A_HEIGHT
#define C_WIDTH B_WIDTH
__global__ void matrix_mulKernel(int *c, int *a, int *b,
int a_height,int a_width, int b_width, int c_width)
{
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
if(row >= a_height || col >= b_width) return;
int i, sum=0;
for(i =0; i<a_width; ++i)
{
sum += a[row * a_width + i] * b[i * b_width + col];
}
c[row * c_width + col] =sum;
}
void matrix_multiplication(const int *a, const int *b, int *c, int a_hiehgt, int b_width, int b_height);
void print_matrix( int *matrix, int height, int width);
int main()
{
int *a = (int*) calloc(A_HEIGHT * A_WIDTH, sizeof(unsigned int) );
int *b = (int*) calloc(B_HEIGHT * B_WIDTH, sizeof(unsigned int) );
int *c = (int*) calloc(C_HEIGHT * C_WIDTH, sizeof(unsigned int) );
int *d = (int*) calloc(C_HEIGHT * C_WIDTH, sizeof(unsigned int) );
int i;
for (i =0; i < A_HEIGHT * A_WIDTH; i++)
{
a[i] = i;
b[i] = i;
}
int *dev_a = 0;
int *dev_b = 0;
int *dev_c = 0;
// Allocate GPU buffers for three vectors (two input, one output) .
hipMalloc((void**)&dev_c, C_HEIGHT * C_WIDTH * sizeof(unsigned int));
hipMalloc((void**)&dev_a, A_HEIGHT * A_WIDTH * sizeof(unsigned int));
hipMalloc((void**)&dev_b, B_HEIGHT * B_WIDTH * sizeof(unsigned int));
// Copy input vectors from host memory to GPU buffers.
hipMemcpy(dev_a, a, A_HEIGHT * A_WIDTH * sizeof(unsigned int), hipMemcpyHostToDevice);
hipMemcpy(dev_b, b, B_HEIGHT * B_WIDTH * sizeof(unsigned int), hipMemcpyHostToDevice);
dim3 dimBlock (BLOCK_SIZE,BLOCK_SIZE); // block( blockIdx, blockIDy)
dim3 grid ((B_WIDTH + dimBlock.x - 1) / dimBlock.x,
(A_HEIGHT + dimBlock.y - 1) / dimBlock.y); // grid(gloalsizeX + blockidx -1)/blockidx,gloalsizeY + blockidy -1)/blockidy);
matrix_mulKernel<<<grid, dimBlock>>>(dev_c, dev_a, dev_b, A_HEIGHT, A_WIDTH, B_WIDTH, C_WIDTH);
// Copy output vector from GPU buffer to host memory.
hipMemcpy(c, dev_c, C_HEIGHT * C_WIDTH * sizeof(int), hipMemcpyDeviceToHost);
matrix_multiplication(a, b ,d, A_HEIGHT, B_WIDTH, B_HEIGHT);
bool flag = true;
for(int i = 0; i < A_HEIGHT * B_WIDTH; i++ )
{
if (c[i] != d[i])
{
printf("Verification fail\n");
flag = false;
break;
}
}
if (flag)
printf("Verification pass\n");
//printf("Matrix A:\n");
//print_matrix(a, size);
//printf("Matrix B:\n");
//print_matrix(b, size);
printf("Matrix C:\n");
print_matrix(c, 10, 10);
printf("Matrix D:\n");
print_matrix(d,10, 10);
}
void matrix_multiplication(const int *a, const int *b, int *c, int a_height, int b_width, int b_height)
{
for(int i = 0; i < a_height; i++)
{
for(int j = 0; j < b_width; j++)
{
int sum = 0;
for(int k = 0; k < b_height ; k++)
{
sum+= a[i * b_height + k] * b[k * b_width + j];
}
c[i * b_width + j] = sum;
}
}
}
void print_matrix( int *matrix, int height, int width)
{
int i , j;
for(i = 0; i < width; i++)
{
for(j = 0; j < height; j++)
printf("%5d", matrix[i * width + j]);
printf("\n");
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16matrix_mulKernelPiS_S_iiii
.globl _Z16matrix_mulKernelPiS_S_iiii
.p2align 8
.type _Z16matrix_mulKernelPiS_S_iiii,@function
_Z16matrix_mulKernelPiS_S_iiii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s4, s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x20
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s15, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s5, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s4, v0
v_cmp_gt_i32_e64 s2, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_6
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x8
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v6, 31, v5
s_add_i32 s2, s2, -1
s_cmp_lg_u32 s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_load_b32 v8, v[3:4], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[6:7], null, v9, v8, v[2:3]
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v2, v6 :: v_dual_add_nc_u32 v5, s3, v5
s_cbranch_scc1 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
.LBB0_5:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[3:4], null, v0, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16matrix_mulKernelPiS_S_iiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16matrix_mulKernelPiS_S_iiii, .Lfunc_end0-_Z16matrix_mulKernelPiS_S_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16matrix_mulKernelPiS_S_iiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16matrix_mulKernelPiS_S_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include"stdio.h"
//#include "matrixmul.cuh"
#define BLOCK_SIZE 16
#define A_HEIGHT 128
#define A_WIDTH 128
#define B_HEIGHT 128
#define B_WIDTH 128
#define C_HEIGHT A_HEIGHT
#define C_WIDTH B_WIDTH
__global__ void matrix_mulKernel(int *c, int *a, int *b,
int a_height,int a_width, int b_width, int c_width)
{
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
if(row >= a_height || col >= b_width) return;
int i, sum=0;
for(i =0; i<a_width; ++i)
{
sum += a[row * a_width + i] * b[i * b_width + col];
}
c[row * c_width + col] =sum;
}
void matrix_multiplication(const int *a, const int *b, int *c, int a_hiehgt, int b_width, int b_height);
void print_matrix( int *matrix, int height, int width);
int main()
{
int *a = (int*) calloc(A_HEIGHT * A_WIDTH, sizeof(unsigned int) );
int *b = (int*) calloc(B_HEIGHT * B_WIDTH, sizeof(unsigned int) );
int *c = (int*) calloc(C_HEIGHT * C_WIDTH, sizeof(unsigned int) );
int *d = (int*) calloc(C_HEIGHT * C_WIDTH, sizeof(unsigned int) );
int i;
for (i =0; i < A_HEIGHT * A_WIDTH; i++)
{
a[i] = i;
b[i] = i;
}
int *dev_a = 0;
int *dev_b = 0;
int *dev_c = 0;
// Allocate GPU buffers for three vectors (two input, one output) .
hipMalloc((void**)&dev_c, C_HEIGHT * C_WIDTH * sizeof(unsigned int));
hipMalloc((void**)&dev_a, A_HEIGHT * A_WIDTH * sizeof(unsigned int));
hipMalloc((void**)&dev_b, B_HEIGHT * B_WIDTH * sizeof(unsigned int));
// Copy input vectors from host memory to GPU buffers.
hipMemcpy(dev_a, a, A_HEIGHT * A_WIDTH * sizeof(unsigned int), hipMemcpyHostToDevice);
hipMemcpy(dev_b, b, B_HEIGHT * B_WIDTH * sizeof(unsigned int), hipMemcpyHostToDevice);
dim3 dimBlock (BLOCK_SIZE,BLOCK_SIZE); // block( blockIdx, blockIDy)
dim3 grid ((B_WIDTH + dimBlock.x - 1) / dimBlock.x,
(A_HEIGHT + dimBlock.y - 1) / dimBlock.y); // grid(gloalsizeX + blockidx -1)/blockidx,gloalsizeY + blockidy -1)/blockidy);
matrix_mulKernel<<<grid, dimBlock>>>(dev_c, dev_a, dev_b, A_HEIGHT, A_WIDTH, B_WIDTH, C_WIDTH);
// Copy output vector from GPU buffer to host memory.
hipMemcpy(c, dev_c, C_HEIGHT * C_WIDTH * sizeof(int), hipMemcpyDeviceToHost);
matrix_multiplication(a, b ,d, A_HEIGHT, B_WIDTH, B_HEIGHT);
bool flag = true;
for(int i = 0; i < A_HEIGHT * B_WIDTH; i++ )
{
if (c[i] != d[i])
{
printf("Verification fail\n");
flag = false;
break;
}
}
if (flag)
printf("Verification pass\n");
//printf("Matrix A:\n");
//print_matrix(a, size);
//printf("Matrix B:\n");
//print_matrix(b, size);
printf("Matrix C:\n");
print_matrix(c, 10, 10);
printf("Matrix D:\n");
print_matrix(d,10, 10);
}
void matrix_multiplication(const int *a, const int *b, int *c, int a_height, int b_width, int b_height)
{
for(int i = 0; i < a_height; i++)
{
for(int j = 0; j < b_width; j++)
{
int sum = 0;
for(int k = 0; k < b_height ; k++)
{
sum+= a[i * b_height + k] * b[k * b_width + j];
}
c[i * b_width + j] = sum;
}
}
}
void print_matrix( int *matrix, int height, int width)
{
int i , j;
for(i = 0; i < width; i++)
{
for(j = 0; j < height; j++)
printf("%5d", matrix[i * width + j]);
printf("\n");
}
} | .text
.file "matrixmul.hip"
.globl _Z31__device_stub__matrix_mulKernelPiS_S_iiii # -- Begin function _Z31__device_stub__matrix_mulKernelPiS_S_iiii
.p2align 4, 0x90
.type _Z31__device_stub__matrix_mulKernelPiS_S_iiii,@function
_Z31__device_stub__matrix_mulKernelPiS_S_iiii: # @_Z31__device_stub__matrix_mulKernelPiS_S_iiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16matrix_mulKernelPiS_S_iiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z31__device_stub__matrix_mulKernelPiS_S_iiii, .Lfunc_end0-_Z31__device_stub__matrix_mulKernelPiS_S_iiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $168, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $16384, %edi # imm = 0x4000
movl $4, %esi
callq calloc
movq %rax, %r15
movl $16384, %edi # imm = 0x4000
movl $4, %esi
callq calloc
movq %rax, %r12
movl $16384, %edi # imm = 0x4000
movl $4, %esi
callq calloc
movq %rax, %r14
movl $16384, %edi # imm = 0x4000
movl $4, %esi
callq calloc
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%r15,%rax,4)
movl %eax, (%r12,%rax,4)
incq %rax
cmpq $16384, %rax # imm = 0x4000
jne .LBB1_1
# %bb.2:
movq $0, 16(%rsp)
movq $0, 8(%rsp)
movq $0, (%rsp)
movq %rsp, %rdi
movl $65536, %esi # imm = 0x10000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $65536, %esi # imm = 0x10000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $65536, %esi # imm = 0x10000
callq hipMalloc
movq 16(%rsp), %rdi
movl $65536, %edx # imm = 0x10000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $65536, %edx # imm = 0x10000
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $34359738376, %rdi # imm = 0x800000008
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq (%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $128, 36(%rsp)
movl $128, 32(%rsp)
movl $128, 28(%rsp)
movl $128, 24(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 28(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z16matrix_mulKernelPiS_S_iiii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
movl $65536, %edx # imm = 0x10000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_5: # %.preheader27.i
# =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
# Child Loop BB1_7 Depth 3
movq %rax, %rcx
shlq $9, %rcx
addq %rbx, %rcx
movq %r12, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_6: # %.preheader.i
# Parent Loop BB1_5 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_7 Depth 3
xorl %edi, %edi
movq %rdx, %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB1_7: # %.lr.ph.i
# Parent Loop BB1_5 Depth=1
# Parent Loop BB1_6 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r8), %r10d
imull (%r15,%rdi,4), %r10d
addl %r10d, %r9d
incq %rdi
addq $512, %r8 # imm = 0x200
cmpq $128, %rdi
jne .LBB1_7
# %bb.8: # %._crit_edge.i
# in Loop: Header=BB1_6 Depth=2
movl %r9d, (%rcx,%rsi,4)
incq %rsi
addq $4, %rdx
cmpq $128, %rsi
jne .LBB1_6
# %bb.9: # %._crit_edge31.i
# in Loop: Header=BB1_5 Depth=1
incq %rax
addq $512, %r15 # imm = 0x200
cmpq $128, %rax
jne .LBB1_5
# %bb.10: # %_Z21matrix_multiplicationPKiS0_Piiii.exit.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_11: # %_Z21matrix_multiplicationPKiS0_Piiii.exit.preheader
# =>This Inner Loop Header: Depth=1
movl (%r14,%rax,4), %ecx
cmpl (%rbx,%rax,4), %ecx
jne .LBB1_14
# %bb.12: # %_Z21matrix_multiplicationPKiS0_Piiii.exit
# in Loop: Header=BB1_11 Depth=1
incq %rax
cmpq $16384, %rax # imm = 0x4000
jne .LBB1_11
# %bb.13:
movl $.Lstr.1, %edi
jmp .LBB1_15
.LBB1_14:
movl $.Lstr, %edi
.LBB1_15: # %.critedge
callq puts@PLT
movl $.Lstr.2, %edi
callq puts@PLT
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_16: # %.preheader.i35
# =>This Loop Header: Depth=1
# Child Loop BB1_17 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_17: # Parent Loop BB1_16 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r12,4), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $10, %r12
jne .LBB1_17
# %bb.18: # %._crit_edge.i40
# in Loop: Header=BB1_16 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addq $40, %r14
cmpq $10, %r15
jne .LBB1_16
# %bb.19: # %_Z12print_matrixPiii.exit
movl $.Lstr.3, %edi
callq puts@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_20: # %.preheader.i41
# =>This Loop Header: Depth=1
# Child Loop BB1_21 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_21: # Parent Loop BB1_20 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r15,4), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $10, %r15
jne .LBB1_21
# %bb.22: # %._crit_edge.i47
# in Loop: Header=BB1_20 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $40, %rbx
cmpq $10, %r14
jne .LBB1_20
# %bb.23: # %_Z12print_matrixPiii.exit51
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z21matrix_multiplicationPKiS0_Piiii # -- Begin function _Z21matrix_multiplicationPKiS0_Piiii
.p2align 4, 0x90
.type _Z21matrix_multiplicationPKiS0_Piiii,@function
_Z21matrix_multiplicationPKiS0_Piiii: # @_Z21matrix_multiplicationPKiS0_Piiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, -36(%rsp) # 4-byte Spill
movq %rdx, -8(%rsp) # 8-byte Spill
movq %rsi, -16(%rsp) # 8-byte Spill
movq %rdi, -24(%rsp) # 8-byte Spill
testl %ecx, %ecx
jle .LBB2_7
# %bb.1: # %.preheader27.lr.ph
movslq -36(%rsp), %rax # 4-byte Folded Reload
movl %ecx, %r8d
movl %eax, %r10d
movl %r9d, %r11d
movq %rax, -32(%rsp) # 8-byte Spill
leaq (,%rax,4), %rbx
xorl %r14d, %r14d
xorl %r15d, %r15d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_6: # %._crit_edge31
# in Loop: Header=BB2_2 Depth=1
incq %r15
addl %r9d, %r14d
cmpq %r8, %r15
je .LBB2_7
.LBB2_2: # %.preheader27
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
# Child Loop BB2_9 Depth 3
cmpl $0, -36(%rsp) # 4-byte Folded Reload
jle .LBB2_6
# %bb.3: # %.preheader.lr.ph
# in Loop: Header=BB2_2 Depth=1
movl %r14d, %eax
movq -24(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r12
movq %r15, %rax
imulq -32(%rsp), %rax # 8-byte Folded Reload
movq -8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r13
movq -16(%rsp), %rdi # 8-byte Reload
xorl %eax, %eax
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_5: # in Loop: Header=BB2_4 Depth=2
xorl %edx, %edx
.LBB2_10: # %._crit_edge
# in Loop: Header=BB2_4 Depth=2
movl %edx, (%r13,%rax,4)
incq %rax
addq $4, %rdi
cmpq %r10, %rax
je .LBB2_6
.LBB2_4: # %.preheader
# Parent Loop BB2_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_9 Depth 3
testl %r9d, %r9d
jle .LBB2_5
# %bb.8: # %.lr.ph.preheader
# in Loop: Header=BB2_4 Depth=2
xorl %esi, %esi
movq %rdi, %rbp
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_9: # %.lr.ph
# Parent Loop BB2_2 Depth=1
# Parent Loop BB2_4 Depth=2
# => This Inner Loop Header: Depth=3
movl (%rbp), %ecx
imull (%r12,%rsi,4), %ecx
addl %ecx, %edx
incq %rsi
addq %rbx, %rbp
cmpq %rsi, %r11
jne .LBB2_9
jmp .LBB2_10
.LBB2_7: # %._crit_edge33
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z21matrix_multiplicationPKiS0_Piiii, .Lfunc_end2-_Z21matrix_multiplicationPKiS0_Piiii
.cfi_endproc
# -- End function
.globl _Z12print_matrixPiii # -- Begin function _Z12print_matrixPiii
.p2align 4, 0x90
.type _Z12print_matrixPiii,@function
_Z12print_matrixPiii: # @_Z12print_matrixPiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, 4(%rsp) # 4-byte Spill
movq %rdi, 8(%rsp) # 8-byte Spill
testl %edx, %edx
jle .LBB3_6
# %bb.1: # %.preheader.lr.ph
movl %edx, %ebx
movl %edx, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl 4(%rsp), %r12d # 4-byte Reload
xorl %r13d, %r13d
xorl %r14d, %r14d
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_5: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addl %ebx, %r13d
cmpq 16(%rsp), %r14 # 8-byte Folded Reload
je .LBB3_6
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
cmpl $0, 4(%rsp) # 4-byte Folded Reload
jle .LBB3_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB3_2 Depth=1
movl %r13d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_4: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbp,%r15,4), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r12
jne .LBB3_4
jmp .LBB3_5
.LBB3_6: # %._crit_edge13
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z12print_matrixPiii, .Lfunc_end3-_Z12print_matrixPiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16matrix_mulKernelPiS_S_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16matrix_mulKernelPiS_S_iiii,@object # @_Z16matrix_mulKernelPiS_S_iiii
.section .rodata,"a",@progbits
.globl _Z16matrix_mulKernelPiS_S_iiii
.p2align 3, 0x0
_Z16matrix_mulKernelPiS_S_iiii:
.quad _Z31__device_stub__matrix_mulKernelPiS_S_iiii
.size _Z16matrix_mulKernelPiS_S_iiii, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "%5d"
.size .L.str.4, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16matrix_mulKernelPiS_S_iiii"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Verification fail"
.size .Lstr, 18
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Verification pass"
.size .Lstr.1, 18
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Matrix C:"
.size .Lstr.2, 10
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Matrix D:"
.size .Lstr.3, 10
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__matrix_mulKernelPiS_S_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16matrix_mulKernelPiS_S_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16matrix_mulKernelPiS_S_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R4, c[0x0][0x17c] ; /* 0x00005f0000047a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe400000001ff */
/*00d0*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0xc30 ; /* 0x00000b4000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R2, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x040fe40007ffe0ff */
/*0100*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe400078ec0ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*0120*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fe40000000f00 */
/*0130*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fd20000000f00 */
/*0140*/ @!P0 BRA 0xb20 ; /* 0x000009d000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R5, -R4, c[0x0][0x17c], RZ ; /* 0x00005f0004057a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0170*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0180*/ IMAD R6, R3, c[0x0][0x17c], RZ ; /* 0x00005f0003067a24 */
/* 0x000fe200078e02ff */
/*0190*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f04270 */
/*01a0*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fca0000000f00 */
/*01b0*/ IMAD.WIDE R8, R0, R9, c[0x0][0x170] ; /* 0x00005c0000087625 */
/* 0x000fcc00078e0209 */
/*01c0*/ @!P0 BRA 0x980 ; /* 0x000007b000008947 */
/* 0x000fea0003800000 */
/*01d0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01f0*/ @!P1 BRA 0x6b0 ; /* 0x000004b000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0220*/ LDG.E R21, [R8.64] ; /* 0x0000000408157981 */
/* 0x0000a2000c1e1900 */
/*0230*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0240*/ IMAD.WIDE R12, R6, 0x4, R12 ; /* 0x00000004060c7825 */
/* 0x000fca00078e020c */
/*0250*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x000ea2000c1e1900 */
/*0260*/ MOV R7, c[0x0][0x180] ; /* 0x0000600000077a02 */
/* 0x000fc60000000f00 */
/*0270*/ LDG.E R14, [R12.64+0x4] ; /* 0x000004040c0e7981 */
/* 0x000ee4000c1e1900 */
/*0280*/ IMAD.WIDE R10, R7.reuse, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x040fe400078e0208 */
/*0290*/ LDG.E R27, [R12.64+0x8] ; /* 0x000008040c1b7981 */
/* 0x000f28000c1e1900 */
/*02a0*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x0002e2000c1e1900 */
/*02b0*/ IMAD.WIDE R22, R7, 0x4, R10 ; /* 0x0000000407167825 */
/* 0x000fc600078e020a */
/*02c0*/ LDG.E R18, [R12.64+0xc] ; /* 0x00000c040c127981 */
/* 0x000f66000c1e1900 */
/*02d0*/ IMAD.WIDE R28, R7.reuse, 0x4, R22 ; /* 0x00000004071c7825 */
/* 0x040fe200078e0216 */
/*02e0*/ LDG.E R26, [R22.64] ; /* 0x00000004161a7981 */
/* 0x000328000c1e1900 */
/*02f0*/ LDG.E R19, [R28.64] ; /* 0x000000041c137981 */
/* 0x000362000c1e1900 */
/*0300*/ IMAD.WIDE R16, R7, 0x4, R28 ; /* 0x0000000407107825 */
/* 0x000fc600078e021c */
/*0310*/ LDG.E R8, [R12.64+0x10] ; /* 0x000010040c087981 */
/* 0x001f68000c1e1900 */
/*0320*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000168000c1e1900 */
/*0330*/ LDG.E R10, [R12.64+0x14] ; /* 0x000014040c0a7981 */
/* 0x002f68000c1e1900 */
/*0340*/ LDG.E R28, [R12.64+0x1c] ; /* 0x00001c040c1c7981 */
/* 0x000f62000c1e1900 */
/*0350*/ IMAD.WIDE R16, R7, 0x4, R16 ; /* 0x0000000407107825 */
/* 0x001fca00078e0210 */
/*0360*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x000562000c1e1900 */
/*0370*/ IMAD.WIDE R22, R7, 0x4, R16 ; /* 0x0000000407167825 */
/* 0x000fc800078e0210 */
/*0380*/ IMAD R16, R21, R20, R24 ; /* 0x0000001415107224 */
/* 0x004fe400078e0218 */
/*0390*/ LDG.E R20, [R12.64+0x18] ; /* 0x000018040c147981 */
/* 0x000ea2000c1e1900 */
/*03a0*/ IMAD.WIDE R24, R7, 0x4, R22 ; /* 0x0000000407187825 */
/* 0x000fc600078e0216 */
/*03b0*/ LDG.E R21, [R22.64] ; /* 0x0000000416157981 */
/* 0x0000a8000c1e1900 */
/*03c0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0002a2000c1e1900 */
/*03d0*/ IMAD R16, R15, R14, R16 ; /* 0x0000000e0f107224 */
/* 0x008fe400078e0210 */
/*03e0*/ IMAD.WIDE R14, R7.reuse, 0x4, R24 ; /* 0x00000004070e7825 */
/* 0x040fe200078e0218 */
/*03f0*/ LDG.E R23, [R12.64+0x20] ; /* 0x000020040c177981 */
/* 0x001ee6000c1e1900 */
/*0400*/ IMAD R26, R26, R27, R16 ; /* 0x0000001b1a1a7224 */
/* 0x010fe200078e0210 */
/*0410*/ LDG.E R25, [R12.64+0x24] ; /* 0x000024040c197981 */
/* 0x002f22000c1e1900 */
/*0420*/ IMAD.WIDE R16, R7, 0x4, R14 ; /* 0x0000000407107825 */
/* 0x000fc600078e020e */
/*0430*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0000e2000c1e1900 */
/*0440*/ IMAD R26, R19, R18, R26 ; /* 0x00000012131a7224 */
/* 0x020fe400078e021a */
/*0450*/ IMAD.WIDE R18, R7, 0x4, R16 ; /* 0x0000000407127825 */
/* 0x000fe200078e0210 */
/*0460*/ LDG.E R22, [R12.64+0x28] ; /* 0x000028040c167981 */
/* 0x000f66000c1e1900 */
/*0470*/ IMAD R26, R9, R8, R26 ; /* 0x00000008091a7224 */
/* 0x000fe200078e021a */
/*0480*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000322000c1e1900 */
/*0490*/ IMAD.WIDE R8, R7, 0x4, R18 ; /* 0x0000000407087825 */
/* 0x000fc600078e0212 */
/*04a0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000368000c1e1900 */
/*04b0*/ LDG.E R24, [R8.64] ; /* 0x0000000408187981 */
/* 0x000568000c1e1900 */
/*04c0*/ LDG.E R15, [R12.64+0x2c] ; /* 0x00002c040c0f7981 */
/* 0x001f62000c1e1900 */
/*04d0*/ IMAD R26, R11, R10, R26 ; /* 0x0000000a0b1a7224 */
/* 0x000fe400078e021a */
/*04e0*/ IMAD.WIDE R10, R7, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x000fe200078e0208 */
/*04f0*/ LDG.E R17, [R12.64+0x30] ; /* 0x000030040c117981 */
/* 0x002f66000c1e1900 */
/*0500*/ IMAD R26, R21, R20, R26 ; /* 0x00000014151a7224 */
/* 0x004fc400078e021a */
/*0510*/ IMAD.WIDE R20, R7, 0x4, R10 ; /* 0x0000000407147825 */
/* 0x000fe400078e020a */
/*0520*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x0000a4000c1e1900 */
/*0530*/ IMAD R28, R29, R28, R26 ; /* 0x0000001c1d1c7224 */
/* 0x000fe400078e021a */
/*0540*/ IMAD.WIDE R26, R7.reuse, 0x4, R20 ; /* 0x00000004071a7825 */
/* 0x040fe200078e0214 */
/*0550*/ LDG.E R29, [R12.64+0x34] ; /* 0x000034040c1d7981 */
/* 0x000ea8000c1e1900 */
/*0560*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x0002a2000c1e1900 */
/*0570*/ IMAD.WIDE R8, R7, 0x4, R26 ; /* 0x0000000407087825 */
/* 0x000fc600078e021a */
/*0580*/ LDG.E R19, [R26.64] ; /* 0x000000041a137981 */
/* 0x0006a8000c1e1900 */
/*0590*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0010a8000c1e1900 */
/*05a0*/ LDG.E R21, [R12.64+0x38] ; /* 0x000038040c157981 */
/* 0x002ea8000c1e1900 */
/*05b0*/ LDG.E R26, [R12.64+0x3c] ; /* 0x00003c040c1a7981 */
/* 0x008ee2000c1e1900 */
/*05c0*/ IMAD R14, R14, R23, R28 ; /* 0x000000170e0e7224 */
/* 0x000fc800078e021c */
/*05d0*/ IMAD R25, R16, R25, R14 ; /* 0x0000001910197224 */
/* 0x010fe200078e020e */
/*05e0*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fc60007ffe0ff */
/*05f0*/ IMAD R18, R18, R22, R25 ; /* 0x0000001612127224 */
/* 0x020fe200078e0219 */
/*0600*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fc60003f24270 */
/*0610*/ IMAD R15, R24, R15, R18 ; /* 0x0000000f180f7224 */
/* 0x000fe200078e0212 */
/*0620*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0630*/ IMAD.WIDE R8, R7, 0x4, R8 ; /* 0x0000000407087825 */
/* 0x001fc600078e0208 */
/*0640*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0650*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe20007ffe0ff */
/*0660*/ IMAD R10, R10, R17, R15 ; /* 0x000000110a0a7224 */
/* 0x004fc800078e020f */
/*0670*/ IMAD R10, R20, R29, R10 ; /* 0x0000001d140a7224 */
/* 0x000fc800078e020a */
/*0680*/ IMAD R10, R19, R21, R10 ; /* 0x00000015130a7224 */
/* 0x000fc800078e020a */
/*0690*/ IMAD R24, R11, R26, R10 ; /* 0x0000001a0b187224 */
/* 0x008fe200078e020a */
/*06a0*/ @P1 BRA 0x210 ; /* 0xfffffb6000001947 */
/* 0x000fea000383ffff */
/*06b0*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*06c0*/ @!P1 BRA 0x960 ; /* 0x0000029000009947 */
/* 0x000fea0003800000 */
/*06d0*/ MOV R7, c[0x0][0x180] ; /* 0x0000600000077a02 */
/* 0x000fe20000000f00 */
/*06e0*/ LDG.E R23, [R8.64] ; /* 0x0000000408177981 */
/* 0x0000a2000c1e1900 */
/*06f0*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*0700*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe20008000f00 */
/*0710*/ IMAD.WIDE R16, R7, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x000fc800078e0208 */
/*0720*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*0730*/ IMAD.WIDE R12, R7.reuse, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x040fe200078e0210 */
/*0740*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x000ea8000c1e1900 */
/*0750*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0002e2000c1e1900 */
/*0760*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0770*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee6000c1e1900 */
/*0780*/ IMAD.WIDE R18, R7.reuse, 0x4, R14 ; /* 0x0000000407127825 */
/* 0x040fe200078e020e */
/*0790*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000968000c1e1900 */
/*07a0*/ LDG.E R27, [R10.64+0x8] ; /* 0x000008040a1b7981 */
/* 0x000f62000c1e1900 */
/*07b0*/ IMAD.WIDE R20, R7, 0x4, R18 ; /* 0x0000000407147825 */
/* 0x000fc600078e0212 */
/*07c0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07d0*/ LDG.E R29, [R10.64+0xc] ; /* 0x00000c040a1d7981 */
/* 0x000f62000c1e1900 */
/*07e0*/ IMAD.WIDE R8, R7, 0x4, R20 ; /* 0x0000000407087825 */
/* 0x001fc600078e0214 */
/*07f0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000168000c1e1900 */
/*0800*/ LDG.E R28, [R10.64+0x10] ; /* 0x000010040a1c7981 */
/* 0x000f62000c1e1900 */
/*0810*/ IMAD.WIDE R12, R7, 0x4, R8 ; /* 0x00000004070c7825 */
/* 0x010fc600078e0208 */
/*0820*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000968000c1e1900 */
/*0830*/ LDG.E R15, [R10.64+0x14] ; /* 0x000014040a0f7981 */
/* 0x002f68000c1e1900 */
/*0840*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000368000c1e1900 */
/*0850*/ LDG.E R21, [R10.64+0x1c] ; /* 0x00001c040a157981 */
/* 0x010f28000c1e1900 */
/*0860*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x001f28000c1e1900 */
/*0870*/ LDG.E R8, [R10.64+0x18] ; /* 0x000018040a087981 */
/* 0x002f22000c1e1900 */
/*0880*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0890*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*08a0*/ IADD3 R2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fe40007ffe0ff */
/*08b0*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*08c0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08d0*/ IMAD R22, R23, R22, R24 ; /* 0x0000001617167224 */
/* 0x004fc800078e0218 */
/*08e0*/ IMAD R16, R16, R25, R22 ; /* 0x0000001910107224 */
/* 0x008fc800078e0216 */
/*08f0*/ IMAD R16, R26, R27, R16 ; /* 0x0000001b1a107224 */
/* 0x020fc800078e0210 */
/*0900*/ IMAD R29, R14, R29, R16 ; /* 0x0000001d0e1d7224 */
/* 0x000fc800078e0210 */
/*0910*/ IMAD R18, R18, R28, R29 ; /* 0x0000001c12127224 */
/* 0x000fc800078e021d */
/*0920*/ IMAD R15, R20, R15, R18 ; /* 0x0000000f140f7224 */
/* 0x000fc800078e0212 */
/*0930*/ IMAD R24, R17, R8, R15 ; /* 0x0000000811187224 */
/* 0x010fe400078e020f */
/*0940*/ IMAD.WIDE R8, R7, 0x4, R12 ; /* 0x0000000407087825 */
/* 0x000fc800078e020c */
/*0950*/ IMAD R24, R19, R21, R24 ; /* 0x0000001513187224 */
/* 0x000fe400078e0218 */
/*0960*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0970*/ @!P0 BRA 0xb20 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0980*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*0990*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe40008000f00 */
/*09a0*/ MOV R7, c[0x0][0x180] ; /* 0x0000600000077a02 */
/* 0x000fc60000000f00 */
/*09b0*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*09c0*/ IMAD.WIDE R16, R7.reuse, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x040fe200078e0208 */
/*09d0*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*09f0*/ IMAD.WIDE R12, R7, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x000fc600078e0210 */
/*0a00*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ee8000c1e1900 */
/*0a10*/ LDG.E R19, [R10.64+0x4] ; /* 0x000004040a137981 */
/* 0x000ee2000c1e1900 */
/*0a20*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0a30*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000f28000c1e1900 */
/*0a40*/ LDG.E R20, [R10.64+0x8] ; /* 0x000008040a147981 */
/* 0x000f28000c1e1900 */
/*0a50*/ LDG.E R22, [R10.64+0xc] ; /* 0x00000c040a167981 */
/* 0x000f68000c1e1900 */
/*0a60*/ LDG.E R23, [R14.64] ; /* 0x000000040e177981 */
/* 0x000f62000c1e1900 */
/*0a70*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fc80007ffe0ff */
/*0a80*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0a90*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0aa0*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fc60007ffe0ff */
/*0ab0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0ac0*/ IMAD R18, R9, R18, R24 ; /* 0x0000001209127224 */
/* 0x004fc800078e0218 */
/*0ad0*/ IMAD R18, R17, R19, R18 ; /* 0x0000001311127224 */
/* 0x008fe400078e0212 */
/*0ae0*/ IMAD.WIDE R8, R7, 0x4, R14 ; /* 0x0000000407087825 */
/* 0x000fc800078e020e */
/*0af0*/ IMAD R18, R21, R20, R18 ; /* 0x0000001415127224 */
/* 0x010fc800078e0212 */
/*0b00*/ IMAD R24, R23, R22, R18 ; /* 0x0000001617187224 */
/* 0x020fe200078e0212 */
/*0b10*/ @P0 BRA 0x980 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0b20*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0b30*/ @!P0 BRA 0xc30 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0b40*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b50*/ IMAD R6, R3, c[0x0][0x17c], R2 ; /* 0x00005f0003067a24 */
/* 0x000fe400078e0202 */
/*0b60*/ IMAD R2, R2, c[0x0][0x180], R0 ; /* 0x0000600002027a24 */
/* 0x000fce00078e0200 */
/*0b70*/ IMAD.WIDE R6, R6, R9, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e0209 */
/*0b80*/ IMAD.WIDE R8, R2, R9, c[0x0][0x170] ; /* 0x00005c0002087625 */
/* 0x000fca00078e0209 */
/*0b90*/ LDG.E R5, [R8.64] ; /* 0x0000000408057981 */
/* 0x0000a8000c1e1900 */
/*0ba0*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x0002a2000c1e1900 */
/*0bb0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0bc0*/ MOV R11, c[0x0][0x180] ; /* 0x00006000000b7a02 */
/* 0x000fe40000000f00 */
/*0bd0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*0be0*/ IMAD.WIDE R8, R11, 0x4, R8 ; /* 0x000000040b087825 */
/* 0x001fe200078e0208 */
/*0bf0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0c00*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0c10*/ IMAD R24, R5, R2, R24 ; /* 0x0000000205187224 */
/* 0x004fc800078e0218 */
/*0c20*/ @P0 BRA 0xb90 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0c30*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0c40*/ IMAD R3, R3, c[0x0][0x184], R0 ; /* 0x0000610003037a24 */
/* 0x000fc800078e0200 */
/*0c50*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0202 */
/*0c60*/ STG.E [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x000fe2000c101904 */
/*0c70*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c80*/ BRA 0xc80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16matrix_mulKernelPiS_S_iiii
.globl _Z16matrix_mulKernelPiS_S_iiii
.p2align 8
.type _Z16matrix_mulKernelPiS_S_iiii,@function
_Z16matrix_mulKernelPiS_S_iiii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s4, s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x20
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s15, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s5, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s4, v0
v_cmp_gt_i32_e64 s2, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_6
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x8
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v6, 31, v5
s_add_i32 s2, s2, -1
s_cmp_lg_u32 s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_load_b32 v8, v[3:4], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[6:7], null, v9, v8, v[2:3]
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v2, v6 :: v_dual_add_nc_u32 v5, s3, v5
s_cbranch_scc1 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
.LBB0_5:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[3:4], null, v0, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16matrix_mulKernelPiS_S_iiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16matrix_mulKernelPiS_S_iiii, .Lfunc_end0-_Z16matrix_mulKernelPiS_S_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16matrix_mulKernelPiS_S_iiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16matrix_mulKernelPiS_S_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b773b_00000000-6_matrixmul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z21matrix_multiplicationPKiS0_Piiii
.type _Z21matrix_multiplicationPKiS0_Piiii, @function
_Z21matrix_multiplicationPKiS0_Piiii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rsi, -16(%rsp)
movq %rdx, -8(%rsp)
movl %ecx, -20(%rsp)
testl %ecx, %ecx
jle .L3
movl %r8d, %edx
movl %r9d, %r11d
movslq %r8d, %r12
leaq 0(,%r12,4), %r8
movl $0, %r13d
movl $0, %ecx
movl $0, %eax
movslq %r9d, %r15
movq %rdi, %rsi
movq %r15, %rdi
jmp .L5
.L6:
movl (%rax), %ecx
imull (%r9), %ecx
addl %ecx, %r13d
addq $4, %rax
addq %r8, %r9
cmpq %r10, %rax
jne .L6
.L8:
movl %r13d, (%r14,%rbx,4)
addq $1, %rbx
addq $4, %rbp
cmpq %rbx, %r12
je .L13
.L9:
movq %rbp, %r9
movq %r15, %rax
movl $0, %r13d
testl %r11d, %r11d
jg .L6
jmp .L8
.L13:
movl -32(%rsp), %eax
movl -28(%rsp), %ecx
movl -24(%rsp), %r13d
.L7:
addl $1, %eax
addl %edx, %ecx
addl %r11d, %r13d
cmpl %eax, -20(%rsp)
je .L3
.L5:
testl %edx, %edx
jle .L7
movq -16(%rsp), %rbp
movslq %r13d, %r9
leaq (%rsi,%r9,4), %r15
addq %rdi, %r9
leaq (%rsi,%r9,4), %r10
movslq %ecx, %r9
movq -8(%rsp), %rbx
leaq (%rbx,%r9,4), %r14
movl $0, %ebx
movl %eax, -32(%rsp)
movl %ecx, -28(%rsp)
movl %r13d, -24(%rsp)
jmp .L9
.L3:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z21matrix_multiplicationPKiS0_Piiii, .-_Z21matrix_multiplicationPKiS0_Piiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%5d"
.LC1:
.string "\n"
.text
.globl _Z12print_matrixPiii
.type _Z12print_matrixPiii, @function
_Z12print_matrixPiii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
movl %esi, 12(%rsp)
testl %edx, %edx
jle .L16
movl %edx, %r15d
movl $0, %r14d
movl $0, %r13d
movslq %esi, %rax
movq %rax, 24(%rsp)
leaq .LC0(%rip), %r12
jmp .L18
.L20:
movslq %r14d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 24(%rsp), %rsi
addq %rsi, %rax
leaq (%rcx,%rax,4), %rbp
.L19:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L19
.L21:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addl %r15d, %r14d
cmpl %r13d, %r15d
je .L16
.L18:
cmpl $0, 12(%rsp)
jg .L20
jmp .L21
.L16:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z12print_matrixPiii, .-_Z12print_matrixPiii
.globl _Z44__device_stub__Z16matrix_mulKernelPiS_S_iiiiPiS_S_iiii
.type _Z44__device_stub__Z16matrix_mulKernelPiS_S_iiiiPiS_S_iiii, @function
_Z44__device_stub__Z16matrix_mulKernelPiS_S_iiiiPiS_S_iiii:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16matrix_mulKernelPiS_S_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L24
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z44__device_stub__Z16matrix_mulKernelPiS_S_iiiiPiS_S_iiii, .-_Z44__device_stub__Z16matrix_mulKernelPiS_S_iiiiPiS_S_iiii
.globl _Z16matrix_mulKernelPiS_S_iiii
.type _Z16matrix_mulKernelPiS_S_iiii, @function
_Z16matrix_mulKernelPiS_S_iiii:
.LFB2085:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z44__device_stub__Z16matrix_mulKernelPiS_S_iiiiPiS_S_iiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z16matrix_mulKernelPiS_S_iiii, .-_Z16matrix_mulKernelPiS_S_iiii
.section .rodata.str1.1
.LC2:
.string "Verification fail\n"
.LC3:
.string "Verification pass\n"
.LC4:
.string "Matrix C:\n"
.LC5:
.string "Matrix D:\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4, %esi
movl $16384, %edi
call calloc@PLT
movq %rax, %rbx
movl $4, %esi
movl $16384, %edi
call calloc@PLT
movq %rax, %rbp
movl $4, %esi
movl $16384, %edi
call calloc@PLT
movq %rax, %r13
movl $4, %esi
movl $16384, %edi
call calloc@PLT
movq %rax, %r12
movl $0, %eax
.L33:
movl %eax, (%rbx,%rax,4)
movl %eax, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $16384, %rax
jne .L33
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movq $0, 24(%rsp)
leaq 24(%rsp), %rdi
movl $65536, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $65536, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $65536, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $65536, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $65536, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $8, 44(%rsp)
movl $8, 48(%rsp)
movl $16, 32(%rsp)
movl $16, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L34:
movl $2, %ecx
movl $65536, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $128, %r9d
movl $128, %r8d
movl $128, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z21matrix_multiplicationPKiS0_Piiii
movl $0, %eax
.L37:
movl (%r12,%rax), %ecx
cmpl %ecx, 0(%r13,%rax)
jne .L43
addq $4, %rax
cmpq $65536, %rax
jne .L37
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L36
.L42:
subq $8, %rsp
.cfi_def_cfa_offset 120
pushq $128
.cfi_def_cfa_offset 128
movl $128, %r9d
movl $128, %r8d
movl $128, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z44__device_stub__Z16matrix_mulKernelPiS_S_iiiiPiS_S_iiii
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L34
.L43:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L36:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $10, %edx
movl $10, %esi
movq %r13, %rdi
call _Z12print_matrixPiii
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $10, %edx
movl $10, %esi
movq %r12, %rdi
call _Z12print_matrixPiii
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L44
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "_Z16matrix_mulKernelPiS_S_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z16matrix_mulKernelPiS_S_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrixmul.hip"
.globl _Z31__device_stub__matrix_mulKernelPiS_S_iiii # -- Begin function _Z31__device_stub__matrix_mulKernelPiS_S_iiii
.p2align 4, 0x90
.type _Z31__device_stub__matrix_mulKernelPiS_S_iiii,@function
_Z31__device_stub__matrix_mulKernelPiS_S_iiii: # @_Z31__device_stub__matrix_mulKernelPiS_S_iiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16matrix_mulKernelPiS_S_iiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z31__device_stub__matrix_mulKernelPiS_S_iiii, .Lfunc_end0-_Z31__device_stub__matrix_mulKernelPiS_S_iiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $168, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $16384, %edi # imm = 0x4000
movl $4, %esi
callq calloc
movq %rax, %r15
movl $16384, %edi # imm = 0x4000
movl $4, %esi
callq calloc
movq %rax, %r12
movl $16384, %edi # imm = 0x4000
movl $4, %esi
callq calloc
movq %rax, %r14
movl $16384, %edi # imm = 0x4000
movl $4, %esi
callq calloc
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%r15,%rax,4)
movl %eax, (%r12,%rax,4)
incq %rax
cmpq $16384, %rax # imm = 0x4000
jne .LBB1_1
# %bb.2:
movq $0, 16(%rsp)
movq $0, 8(%rsp)
movq $0, (%rsp)
movq %rsp, %rdi
movl $65536, %esi # imm = 0x10000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $65536, %esi # imm = 0x10000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $65536, %esi # imm = 0x10000
callq hipMalloc
movq 16(%rsp), %rdi
movl $65536, %edx # imm = 0x10000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $65536, %edx # imm = 0x10000
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $34359738376, %rdi # imm = 0x800000008
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq (%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $128, 36(%rsp)
movl $128, 32(%rsp)
movl $128, 28(%rsp)
movl $128, 24(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 28(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z16matrix_mulKernelPiS_S_iiii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
movl $65536, %edx # imm = 0x10000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_5: # %.preheader27.i
# =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
# Child Loop BB1_7 Depth 3
movq %rax, %rcx
shlq $9, %rcx
addq %rbx, %rcx
movq %r12, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_6: # %.preheader.i
# Parent Loop BB1_5 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_7 Depth 3
xorl %edi, %edi
movq %rdx, %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB1_7: # %.lr.ph.i
# Parent Loop BB1_5 Depth=1
# Parent Loop BB1_6 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r8), %r10d
imull (%r15,%rdi,4), %r10d
addl %r10d, %r9d
incq %rdi
addq $512, %r8 # imm = 0x200
cmpq $128, %rdi
jne .LBB1_7
# %bb.8: # %._crit_edge.i
# in Loop: Header=BB1_6 Depth=2
movl %r9d, (%rcx,%rsi,4)
incq %rsi
addq $4, %rdx
cmpq $128, %rsi
jne .LBB1_6
# %bb.9: # %._crit_edge31.i
# in Loop: Header=BB1_5 Depth=1
incq %rax
addq $512, %r15 # imm = 0x200
cmpq $128, %rax
jne .LBB1_5
# %bb.10: # %_Z21matrix_multiplicationPKiS0_Piiii.exit.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_11: # %_Z21matrix_multiplicationPKiS0_Piiii.exit.preheader
# =>This Inner Loop Header: Depth=1
movl (%r14,%rax,4), %ecx
cmpl (%rbx,%rax,4), %ecx
jne .LBB1_14
# %bb.12: # %_Z21matrix_multiplicationPKiS0_Piiii.exit
# in Loop: Header=BB1_11 Depth=1
incq %rax
cmpq $16384, %rax # imm = 0x4000
jne .LBB1_11
# %bb.13:
movl $.Lstr.1, %edi
jmp .LBB1_15
.LBB1_14:
movl $.Lstr, %edi
.LBB1_15: # %.critedge
callq puts@PLT
movl $.Lstr.2, %edi
callq puts@PLT
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_16: # %.preheader.i35
# =>This Loop Header: Depth=1
# Child Loop BB1_17 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_17: # Parent Loop BB1_16 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r12,4), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $10, %r12
jne .LBB1_17
# %bb.18: # %._crit_edge.i40
# in Loop: Header=BB1_16 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addq $40, %r14
cmpq $10, %r15
jne .LBB1_16
# %bb.19: # %_Z12print_matrixPiii.exit
movl $.Lstr.3, %edi
callq puts@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_20: # %.preheader.i41
# =>This Loop Header: Depth=1
# Child Loop BB1_21 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_21: # Parent Loop BB1_20 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r15,4), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $10, %r15
jne .LBB1_21
# %bb.22: # %._crit_edge.i47
# in Loop: Header=BB1_20 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $40, %rbx
cmpq $10, %r14
jne .LBB1_20
# %bb.23: # %_Z12print_matrixPiii.exit51
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z21matrix_multiplicationPKiS0_Piiii # -- Begin function _Z21matrix_multiplicationPKiS0_Piiii
.p2align 4, 0x90
.type _Z21matrix_multiplicationPKiS0_Piiii,@function
_Z21matrix_multiplicationPKiS0_Piiii: # @_Z21matrix_multiplicationPKiS0_Piiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, -36(%rsp) # 4-byte Spill
movq %rdx, -8(%rsp) # 8-byte Spill
movq %rsi, -16(%rsp) # 8-byte Spill
movq %rdi, -24(%rsp) # 8-byte Spill
testl %ecx, %ecx
jle .LBB2_7
# %bb.1: # %.preheader27.lr.ph
movslq -36(%rsp), %rax # 4-byte Folded Reload
movl %ecx, %r8d
movl %eax, %r10d
movl %r9d, %r11d
movq %rax, -32(%rsp) # 8-byte Spill
leaq (,%rax,4), %rbx
xorl %r14d, %r14d
xorl %r15d, %r15d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_6: # %._crit_edge31
# in Loop: Header=BB2_2 Depth=1
incq %r15
addl %r9d, %r14d
cmpq %r8, %r15
je .LBB2_7
.LBB2_2: # %.preheader27
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
# Child Loop BB2_9 Depth 3
cmpl $0, -36(%rsp) # 4-byte Folded Reload
jle .LBB2_6
# %bb.3: # %.preheader.lr.ph
# in Loop: Header=BB2_2 Depth=1
movl %r14d, %eax
movq -24(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r12
movq %r15, %rax
imulq -32(%rsp), %rax # 8-byte Folded Reload
movq -8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r13
movq -16(%rsp), %rdi # 8-byte Reload
xorl %eax, %eax
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_5: # in Loop: Header=BB2_4 Depth=2
xorl %edx, %edx
.LBB2_10: # %._crit_edge
# in Loop: Header=BB2_4 Depth=2
movl %edx, (%r13,%rax,4)
incq %rax
addq $4, %rdi
cmpq %r10, %rax
je .LBB2_6
.LBB2_4: # %.preheader
# Parent Loop BB2_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_9 Depth 3
testl %r9d, %r9d
jle .LBB2_5
# %bb.8: # %.lr.ph.preheader
# in Loop: Header=BB2_4 Depth=2
xorl %esi, %esi
movq %rdi, %rbp
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_9: # %.lr.ph
# Parent Loop BB2_2 Depth=1
# Parent Loop BB2_4 Depth=2
# => This Inner Loop Header: Depth=3
movl (%rbp), %ecx
imull (%r12,%rsi,4), %ecx
addl %ecx, %edx
incq %rsi
addq %rbx, %rbp
cmpq %rsi, %r11
jne .LBB2_9
jmp .LBB2_10
.LBB2_7: # %._crit_edge33
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z21matrix_multiplicationPKiS0_Piiii, .Lfunc_end2-_Z21matrix_multiplicationPKiS0_Piiii
.cfi_endproc
# -- End function
.globl _Z12print_matrixPiii # -- Begin function _Z12print_matrixPiii
.p2align 4, 0x90
.type _Z12print_matrixPiii,@function
_Z12print_matrixPiii: # @_Z12print_matrixPiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, 4(%rsp) # 4-byte Spill
movq %rdi, 8(%rsp) # 8-byte Spill
testl %edx, %edx
jle .LBB3_6
# %bb.1: # %.preheader.lr.ph
movl %edx, %ebx
movl %edx, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl 4(%rsp), %r12d # 4-byte Reload
xorl %r13d, %r13d
xorl %r14d, %r14d
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_5: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addl %ebx, %r13d
cmpq 16(%rsp), %r14 # 8-byte Folded Reload
je .LBB3_6
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
cmpl $0, 4(%rsp) # 4-byte Folded Reload
jle .LBB3_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB3_2 Depth=1
movl %r13d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_4: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbp,%r15,4), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r12
jne .LBB3_4
jmp .LBB3_5
.LBB3_6: # %._crit_edge13
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z12print_matrixPiii, .Lfunc_end3-_Z12print_matrixPiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16matrix_mulKernelPiS_S_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16matrix_mulKernelPiS_S_iiii,@object # @_Z16matrix_mulKernelPiS_S_iiii
.section .rodata,"a",@progbits
.globl _Z16matrix_mulKernelPiS_S_iiii
.p2align 3, 0x0
_Z16matrix_mulKernelPiS_S_iiii:
.quad _Z31__device_stub__matrix_mulKernelPiS_S_iiii
.size _Z16matrix_mulKernelPiS_S_iiii, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "%5d"
.size .L.str.4, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16matrix_mulKernelPiS_S_iiii"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Verification fail"
.size .Lstr, 18
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Verification pass"
.size .Lstr.1, 18
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Matrix C:"
.size .Lstr.2, 10
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Matrix D:"
.size .Lstr.3, 10
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__matrix_mulKernelPiS_S_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16matrix_mulKernelPiS_S_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<cstdio>
#include<vector>
#include<string>
#include<cuda_runtime.h>
// #include <thrust/sequence.h>
#include <thrust/scan.h>
#include <thrust/execution_policy.h> // thrust::host/device
#define BLOCK_SIZE 32
using namespace std;
float average(const vector<float> &timing) {
double avg = 0;
for(vector<float>::const_iterator it = timing.begin(); it != timing.end(); it++) avg += *it;
avg /= timing.size();
//return us
avg /= 1000;
return avg;
}
void print_info(int *data, int len, string flag) {
printf("%s frist ten:\n", flag.c_str());
for (int i=0; i<10; i++){
printf("%d ", data[i]);
}
printf("\n");
printf("%s last ten:\n", flag.c_str());
for (int i=len -10; i<len; i++){
printf("%d ", data[i]);
}
printf("\n");
}
__global__ void exclusive_scan(int *A, int N) {
int thx = blockDim.x * blockIdx.x + threadIdx.x;
if (thx >= N) return;
__shared__ int logN;
if (thx == 0) {
logN = log2f(N);
}
__syncthreads();
for (int i=0; i<logN; i++) {
int d2 = powf(2, i+1);
int dd2 = d2/2;
if (thx%d2==d2-1) {
A[thx] += A[thx - dd2];
}
__syncthreads();
}
if (thx == 0) {
A[N-1] = 0;
}
__syncthreads();
for (int i=logN-1; i>=0; i--) {
int d2 = powf(2, i+1);
int dd2 = d2/2;
if (thx%d2==d2-1) {
int tmp = A[thx-dd2];
// A[thx-dd2] = tmp;
A[thx-dd2] = A[thx];
A[thx] += tmp;
}
__syncthreads();
}
}
int main() {
int len_a = BLOCK_SIZE;
int numThreads = BLOCK_SIZE;
int numBlocks = (len_a + numThreads - 1) / numThreads;
int* A = (int*) malloc(len_a * sizeof(int));
int* th_h_A = (int*) malloc(len_a * sizeof(int));
// file a,b
for (int i=0; i<len_a; i++) A[i] = i;
for (int i=0; i<len_a; i++) th_h_A[i] = i;
print_info(A, len_a, "A");
int *d_A, *th_A;
cudaMalloc((void**)&d_A, len_a * sizeof(int));
cudaMalloc((void**)&th_A, len_a * sizeof(int));
cudaMemcpy(d_A, A, len_a * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(th_A, A, len_a * sizeof(int), cudaMemcpyHostToDevice);
// thrust scan
thrust::exclusive_scan(thrust::device, th_A, th_A+len_a, th_A, 0);
cudaMemcpy(th_h_A, th_A, len_a * sizeof(int), cudaMemcpyDeviceToHost);
// thrust::exclusive_scan(thrust::host, th_h_A, th_h_A+len_a, th_h_A, 0);
print_info(th_h_A, len_a, "th_h_A");
vector<float> times;
int loops = 1;
for (int i=0; i<loops; i++) {
cudaEvent_t start, end;
cudaEventCreate(&start);
cudaEventCreate(&end);
cudaEventRecord(start, NULL);
exclusive_scan<<<numBlocks, numThreads>>>(d_A, len_a);
cudaEventRecord(end, NULL);
cudaEventSynchronize(end);
float time = 0;
cudaEventElapsedTime(&time, start, end);
times.push_back(time);
}
printf("exclusive scan avg time:%lf\n", average(times));
cudaMemcpy(A, d_A, len_a * sizeof(float), cudaMemcpyDeviceToHost);
print_info(A, len_a, "A");
} | #include<cstdio>
#include<vector>
#include<string>
#include<hip/hip_runtime.h>
// #include <thrust/sequence.h>
#include <thrust/scan.h>
#include <thrust/execution_policy.h> // thrust::host/device
#define BLOCK_SIZE 32
using namespace std;
float average(const vector<float> &timing) {
double avg = 0;
for(vector<float>::const_iterator it = timing.begin(); it != timing.end(); it++) avg += *it;
avg /= timing.size();
//return us
avg /= 1000;
return avg;
}
void print_info(int *data, int len, string flag) {
printf("%s frist ten:\n", flag.c_str());
for (int i=0; i<10; i++){
printf("%d ", data[i]);
}
printf("\n");
printf("%s last ten:\n", flag.c_str());
for (int i=len -10; i<len; i++){
printf("%d ", data[i]);
}
printf("\n");
}
__global__ void exclusive_scan(int *A, int N) {
int thx = blockDim.x * blockIdx.x + threadIdx.x;
if (thx >= N) return;
__shared__ int logN;
if (thx == 0) {
logN = log2f(N);
}
__syncthreads();
for (int i=0; i<logN; i++) {
int d2 = powf(2, i+1);
int dd2 = d2/2;
if (thx%d2==d2-1) {
A[thx] += A[thx - dd2];
}
__syncthreads();
}
if (thx == 0) {
A[N-1] = 0;
}
__syncthreads();
for (int i=logN-1; i>=0; i--) {
int d2 = powf(2, i+1);
int dd2 = d2/2;
if (thx%d2==d2-1) {
int tmp = A[thx-dd2];
// A[thx-dd2] = tmp;
A[thx-dd2] = A[thx];
A[thx] += tmp;
}
__syncthreads();
}
}
int main() {
int len_a = BLOCK_SIZE;
int numThreads = BLOCK_SIZE;
int numBlocks = (len_a + numThreads - 1) / numThreads;
int* A = (int*) malloc(len_a * sizeof(int));
int* th_h_A = (int*) malloc(len_a * sizeof(int));
// file a,b
for (int i=0; i<len_a; i++) A[i] = i;
for (int i=0; i<len_a; i++) th_h_A[i] = i;
print_info(A, len_a, "A");
int *d_A, *th_A;
hipMalloc((void**)&d_A, len_a * sizeof(int));
hipMalloc((void**)&th_A, len_a * sizeof(int));
hipMemcpy(d_A, A, len_a * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(th_A, A, len_a * sizeof(int), hipMemcpyHostToDevice);
// thrust scan
thrust::exclusive_scan(thrust::device, th_A, th_A+len_a, th_A, 0);
hipMemcpy(th_h_A, th_A, len_a * sizeof(int), hipMemcpyDeviceToHost);
// thrust::exclusive_scan(thrust::host, th_h_A, th_h_A+len_a, th_h_A, 0);
print_info(th_h_A, len_a, "th_h_A");
vector<float> times;
int loops = 1;
for (int i=0; i<loops; i++) {
hipEvent_t start, end;
hipEventCreate(&start);
hipEventCreate(&end);
hipEventRecord(start, NULL);
exclusive_scan<<<numBlocks, numThreads>>>(d_A, len_a);
hipEventRecord(end, NULL);
hipEventSynchronize(end);
float time = 0;
hipEventElapsedTime(&time, start, end);
times.push_back(time);
}
printf("exclusive scan avg time:%lf\n", average(times));
hipMemcpy(A, d_A, len_a * sizeof(float), hipMemcpyDeviceToHost);
print_info(A, len_a, "A");
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void update_mixed_derivatives(double *temppsix, double *temppsiy, double *temppsixy, unsigned int nx, unsigned int ny, double dx, double dy, unsigned int TileSize)
{
unsigned int bx = blockIdx.x;
unsigned int by = blockIdx.y;
unsigned int tx = threadIdx.x;
unsigned int ty = threadIdx.y;
unsigned int index_x = bx * TileSize + tx;
unsigned int index_y = by * TileSize + ty;
unsigned int indexToWrite = index_y * nx + index_x;
if ((index_y == 0 || index_y == ny - 1) && (index_x != 0 && index_x != nx - 1))
temppsixy[indexToWrite] = (temppsiy[indexToWrite+1] - temppsiy[indexToWrite-1])/(2 * dx);
else
if ((index_y != 0 && index_y != ny - 1) && (index_x == 0 || index_x == nx - 1))
temppsixy[indexToWrite] = (temppsix[indexToWrite + nx] - temppsix[indexToWrite - nx])/(2 * dy);
else
if((index_y == 0 || index_y == ny - 1) && (index_x == 0 || index_x == nx - 1)){
if(index_y == 0 && index_x == 0){
double d1 = (temppsiy[1] - temppsiy[0])/dx;
double d2 = (temppsix[nx] - temppsix[0])/dy;
double d3 = (temppsix[nx+1] - temppsix[1])/dy;
double d4 = (temppsiy[nx+1] - temppsiy[nx])/dx;
temppsixy[indexToWrite] = 0.75 * (d1 + d2) - 0.25 * (d3 + d4);
}
else if(index_y == 0 && index_x == nx-1){
double d1 = (temppsiy[nx-1] - temppsiy[nx-2])/dx;
double d2 = (temppsix[nx+nx-2] - temppsix[nx-2])/dy;
double d3 = (temppsix[nx+nx-1] - temppsix[nx-1])/dy;
double d4 = (temppsiy[nx+nx-1] - temppsiy[nx+nx-2])/dx;
temppsixy[indexToWrite] = 0.75 * (d1 + d3) - 0.25 * (d2 + d4);
}
else if(index_y == ny-1 && index_x == 0){
double d1 = (temppsiy[nx *(ny-2) + 1] - temppsiy[nx *(ny-2)])/dx;
double d2 = (temppsix[nx *(ny-1)] - temppsix[nx *(ny-2)])/dy;
double d3 = (temppsix[nx *(ny-1)] - temppsix[nx *(ny-2) + 1])/dy;
double d4 = (temppsiy[nx *(ny-1) + 1] - temppsiy[nx *(ny-1)])/dx;
temppsixy[indexToWrite] = 0.75 * (d2 + d4) - 0.25 * (d3 + d1);
}
else if(index_y == ny-1 && index_x == nx-1){
double d1 = (temppsiy[nx *(ny-2) + nx - 1] - temppsiy[nx *(ny-2) + nx - 2])/dx;
double d2 = (temppsix[nx *(ny-1) + nx - 2] - temppsix[nx *(ny-2) + nx - 2])/dy;
double d3 = (temppsix[nx *(ny-1) + nx - 1] - temppsix[nx *(ny-2) + nx - 1])/dy;
double d4 = (temppsiy[nx *(ny-1) + nx - 1] - temppsiy[nx *(ny-1) + nx - 2])/dx;
temppsixy[indexToWrite] = 0.75 * (d3 + d4) - 0.25 * (d1 + d2);
}
}
else{
double dxy1 = (temppsiy[indexToWrite+1] - temppsiy[indexToWrite-1])/(2 * dx);
double dxy2 = (temppsix[indexToWrite + nx] - temppsix[indexToWrite - nx])/(2 * dy);
temppsixy[indexToWrite] = (dxy1 + dxy2)/2.0;
}
} | .file "tmpxft_00137321_00000000-6_update_mixed_derivatives.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z53__device_stub__Z24update_mixed_derivativesPdS_S_jjddjPdS_S_jjddj
.type _Z53__device_stub__Z24update_mixed_derivativesPdS_S_jjddjPdS_S_jjddj, @function
_Z53__device_stub__Z24update_mixed_derivativesPdS_S_jjddjPdS_S_jjddj:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movl %ecx, 36(%rsp)
movl %r8d, 32(%rsp)
movsd %xmm0, 24(%rsp)
movsd %xmm1, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 12(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z24update_mixed_derivativesPdS_S_jjddj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z53__device_stub__Z24update_mixed_derivativesPdS_S_jjddjPdS_S_jjddj, .-_Z53__device_stub__Z24update_mixed_derivativesPdS_S_jjddjPdS_S_jjddj
.globl _Z24update_mixed_derivativesPdS_S_jjddj
.type _Z24update_mixed_derivativesPdS_S_jjddj, @function
_Z24update_mixed_derivativesPdS_S_jjddj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z24update_mixed_derivativesPdS_S_jjddjPdS_S_jjddj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z24update_mixed_derivativesPdS_S_jjddj, .-_Z24update_mixed_derivativesPdS_S_jjddj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24update_mixed_derivativesPdS_S_jjddj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24update_mixed_derivativesPdS_S_jjddj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void update_mixed_derivatives(double *temppsix, double *temppsiy, double *temppsixy, unsigned int nx, unsigned int ny, double dx, double dy, unsigned int TileSize)
{
unsigned int bx = blockIdx.x;
unsigned int by = blockIdx.y;
unsigned int tx = threadIdx.x;
unsigned int ty = threadIdx.y;
unsigned int index_x = bx * TileSize + tx;
unsigned int index_y = by * TileSize + ty;
unsigned int indexToWrite = index_y * nx + index_x;
if ((index_y == 0 || index_y == ny - 1) && (index_x != 0 && index_x != nx - 1))
temppsixy[indexToWrite] = (temppsiy[indexToWrite+1] - temppsiy[indexToWrite-1])/(2 * dx);
else
if ((index_y != 0 && index_y != ny - 1) && (index_x == 0 || index_x == nx - 1))
temppsixy[indexToWrite] = (temppsix[indexToWrite + nx] - temppsix[indexToWrite - nx])/(2 * dy);
else
if((index_y == 0 || index_y == ny - 1) && (index_x == 0 || index_x == nx - 1)){
if(index_y == 0 && index_x == 0){
double d1 = (temppsiy[1] - temppsiy[0])/dx;
double d2 = (temppsix[nx] - temppsix[0])/dy;
double d3 = (temppsix[nx+1] - temppsix[1])/dy;
double d4 = (temppsiy[nx+1] - temppsiy[nx])/dx;
temppsixy[indexToWrite] = 0.75 * (d1 + d2) - 0.25 * (d3 + d4);
}
else if(index_y == 0 && index_x == nx-1){
double d1 = (temppsiy[nx-1] - temppsiy[nx-2])/dx;
double d2 = (temppsix[nx+nx-2] - temppsix[nx-2])/dy;
double d3 = (temppsix[nx+nx-1] - temppsix[nx-1])/dy;
double d4 = (temppsiy[nx+nx-1] - temppsiy[nx+nx-2])/dx;
temppsixy[indexToWrite] = 0.75 * (d1 + d3) - 0.25 * (d2 + d4);
}
else if(index_y == ny-1 && index_x == 0){
double d1 = (temppsiy[nx *(ny-2) + 1] - temppsiy[nx *(ny-2)])/dx;
double d2 = (temppsix[nx *(ny-1)] - temppsix[nx *(ny-2)])/dy;
double d3 = (temppsix[nx *(ny-1)] - temppsix[nx *(ny-2) + 1])/dy;
double d4 = (temppsiy[nx *(ny-1) + 1] - temppsiy[nx *(ny-1)])/dx;
temppsixy[indexToWrite] = 0.75 * (d2 + d4) - 0.25 * (d3 + d1);
}
else if(index_y == ny-1 && index_x == nx-1){
double d1 = (temppsiy[nx *(ny-2) + nx - 1] - temppsiy[nx *(ny-2) + nx - 2])/dx;
double d2 = (temppsix[nx *(ny-1) + nx - 2] - temppsix[nx *(ny-2) + nx - 2])/dy;
double d3 = (temppsix[nx *(ny-1) + nx - 1] - temppsix[nx *(ny-2) + nx - 1])/dy;
double d4 = (temppsiy[nx *(ny-1) + nx - 1] - temppsiy[nx *(ny-1) + nx - 2])/dx;
temppsixy[indexToWrite] = 0.75 * (d3 + d4) - 0.25 * (d1 + d2);
}
}
else{
double dxy1 = (temppsiy[indexToWrite+1] - temppsiy[indexToWrite-1])/(2 * dx);
double dxy2 = (temppsix[indexToWrite + nx] - temppsix[indexToWrite - nx])/(2 * dy);
temppsixy[indexToWrite] = (dxy1 + dxy2)/2.0;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void update_mixed_derivatives(double *temppsix, double *temppsiy, double *temppsixy, unsigned int nx, unsigned int ny, double dx, double dy, unsigned int TileSize)
{
unsigned int bx = blockIdx.x;
unsigned int by = blockIdx.y;
unsigned int tx = threadIdx.x;
unsigned int ty = threadIdx.y;
unsigned int index_x = bx * TileSize + tx;
unsigned int index_y = by * TileSize + ty;
unsigned int indexToWrite = index_y * nx + index_x;
if ((index_y == 0 || index_y == ny - 1) && (index_x != 0 && index_x != nx - 1))
temppsixy[indexToWrite] = (temppsiy[indexToWrite+1] - temppsiy[indexToWrite-1])/(2 * dx);
else
if ((index_y != 0 && index_y != ny - 1) && (index_x == 0 || index_x == nx - 1))
temppsixy[indexToWrite] = (temppsix[indexToWrite + nx] - temppsix[indexToWrite - nx])/(2 * dy);
else
if((index_y == 0 || index_y == ny - 1) && (index_x == 0 || index_x == nx - 1)){
if(index_y == 0 && index_x == 0){
double d1 = (temppsiy[1] - temppsiy[0])/dx;
double d2 = (temppsix[nx] - temppsix[0])/dy;
double d3 = (temppsix[nx+1] - temppsix[1])/dy;
double d4 = (temppsiy[nx+1] - temppsiy[nx])/dx;
temppsixy[indexToWrite] = 0.75 * (d1 + d2) - 0.25 * (d3 + d4);
}
else if(index_y == 0 && index_x == nx-1){
double d1 = (temppsiy[nx-1] - temppsiy[nx-2])/dx;
double d2 = (temppsix[nx+nx-2] - temppsix[nx-2])/dy;
double d3 = (temppsix[nx+nx-1] - temppsix[nx-1])/dy;
double d4 = (temppsiy[nx+nx-1] - temppsiy[nx+nx-2])/dx;
temppsixy[indexToWrite] = 0.75 * (d1 + d3) - 0.25 * (d2 + d4);
}
else if(index_y == ny-1 && index_x == 0){
double d1 = (temppsiy[nx *(ny-2) + 1] - temppsiy[nx *(ny-2)])/dx;
double d2 = (temppsix[nx *(ny-1)] - temppsix[nx *(ny-2)])/dy;
double d3 = (temppsix[nx *(ny-1)] - temppsix[nx *(ny-2) + 1])/dy;
double d4 = (temppsiy[nx *(ny-1) + 1] - temppsiy[nx *(ny-1)])/dx;
temppsixy[indexToWrite] = 0.75 * (d2 + d4) - 0.25 * (d3 + d1);
}
else if(index_y == ny-1 && index_x == nx-1){
double d1 = (temppsiy[nx *(ny-2) + nx - 1] - temppsiy[nx *(ny-2) + nx - 2])/dx;
double d2 = (temppsix[nx *(ny-1) + nx - 2] - temppsix[nx *(ny-2) + nx - 2])/dy;
double d3 = (temppsix[nx *(ny-1) + nx - 1] - temppsix[nx *(ny-2) + nx - 1])/dy;
double d4 = (temppsiy[nx *(ny-1) + nx - 1] - temppsiy[nx *(ny-1) + nx - 2])/dx;
temppsixy[indexToWrite] = 0.75 * (d3 + d4) - 0.25 * (d1 + d2);
}
}
else{
double dxy1 = (temppsiy[indexToWrite+1] - temppsiy[indexToWrite-1])/(2 * dx);
double dxy2 = (temppsix[indexToWrite + nx] - temppsix[indexToWrite - nx])/(2 * dy);
temppsixy[indexToWrite] = (dxy1 + dxy2)/2.0;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void update_mixed_derivatives(double *temppsix, double *temppsiy, double *temppsixy, unsigned int nx, unsigned int ny, double dx, double dy, unsigned int TileSize)
{
unsigned int bx = blockIdx.x;
unsigned int by = blockIdx.y;
unsigned int tx = threadIdx.x;
unsigned int ty = threadIdx.y;
unsigned int index_x = bx * TileSize + tx;
unsigned int index_y = by * TileSize + ty;
unsigned int indexToWrite = index_y * nx + index_x;
if ((index_y == 0 || index_y == ny - 1) && (index_x != 0 && index_x != nx - 1))
temppsixy[indexToWrite] = (temppsiy[indexToWrite+1] - temppsiy[indexToWrite-1])/(2 * dx);
else
if ((index_y != 0 && index_y != ny - 1) && (index_x == 0 || index_x == nx - 1))
temppsixy[indexToWrite] = (temppsix[indexToWrite + nx] - temppsix[indexToWrite - nx])/(2 * dy);
else
if((index_y == 0 || index_y == ny - 1) && (index_x == 0 || index_x == nx - 1)){
if(index_y == 0 && index_x == 0){
double d1 = (temppsiy[1] - temppsiy[0])/dx;
double d2 = (temppsix[nx] - temppsix[0])/dy;
double d3 = (temppsix[nx+1] - temppsix[1])/dy;
double d4 = (temppsiy[nx+1] - temppsiy[nx])/dx;
temppsixy[indexToWrite] = 0.75 * (d1 + d2) - 0.25 * (d3 + d4);
}
else if(index_y == 0 && index_x == nx-1){
double d1 = (temppsiy[nx-1] - temppsiy[nx-2])/dx;
double d2 = (temppsix[nx+nx-2] - temppsix[nx-2])/dy;
double d3 = (temppsix[nx+nx-1] - temppsix[nx-1])/dy;
double d4 = (temppsiy[nx+nx-1] - temppsiy[nx+nx-2])/dx;
temppsixy[indexToWrite] = 0.75 * (d1 + d3) - 0.25 * (d2 + d4);
}
else if(index_y == ny-1 && index_x == 0){
double d1 = (temppsiy[nx *(ny-2) + 1] - temppsiy[nx *(ny-2)])/dx;
double d2 = (temppsix[nx *(ny-1)] - temppsix[nx *(ny-2)])/dy;
double d3 = (temppsix[nx *(ny-1)] - temppsix[nx *(ny-2) + 1])/dy;
double d4 = (temppsiy[nx *(ny-1) + 1] - temppsiy[nx *(ny-1)])/dx;
temppsixy[indexToWrite] = 0.75 * (d2 + d4) - 0.25 * (d3 + d1);
}
else if(index_y == ny-1 && index_x == nx-1){
double d1 = (temppsiy[nx *(ny-2) + nx - 1] - temppsiy[nx *(ny-2) + nx - 2])/dx;
double d2 = (temppsix[nx *(ny-1) + nx - 2] - temppsix[nx *(ny-2) + nx - 2])/dy;
double d3 = (temppsix[nx *(ny-1) + nx - 1] - temppsix[nx *(ny-2) + nx - 1])/dy;
double d4 = (temppsiy[nx *(ny-1) + nx - 1] - temppsiy[nx *(ny-1) + nx - 2])/dx;
temppsixy[indexToWrite] = 0.75 * (d3 + d4) - 0.25 * (d1 + d2);
}
}
else{
double dxy1 = (temppsiy[indexToWrite+1] - temppsiy[indexToWrite-1])/(2 * dx);
double dxy2 = (temppsix[indexToWrite + nx] - temppsix[indexToWrite - nx])/(2 * dy);
temppsixy[indexToWrite] = (dxy1 + dxy2)/2.0;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24update_mixed_derivativesPdS_S_jjddj
.globl _Z24update_mixed_derivativesPdS_S_jjddj
.p2align 8
.type _Z24update_mixed_derivativesPdS_S_jjddj,@function
_Z24update_mixed_derivativesPdS_S_jjddj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x30
s_load_b64 s[8:9], s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_mov_b32 s12, 0
s_mov_b32 s4, 0
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
v_mad_u64_u32 v[3:4], null, s14, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_2)
v_cmp_eq_u32_e64 s2, 0, v2
v_cmpx_ne_u32_e32 0, v2
s_xor_b32 s5, exec_lo, s3
s_add_i32 s3, s9, -1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, 0, v3
v_cmp_eq_u32_e64 s3, s3, v2
s_and_b32 s3, s3, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s4, s3, -1
s_and_b32 s12, s3, exec_lo
s_and_b32 s4, s4, exec_lo
s_or_saveexec_b32 s5, s5
s_load_b64 s[10:11], s[0:1], 0x8
v_mad_u64_u32 v[0:1], null, v2, s8, v[3:4]
s_xor_b32 exec_lo, exec_lo, s5
v_cmp_eq_u32_e32 vcc_lo, 0, v3
v_cmp_ne_u32_e64 s3, 0, v3
s_and_not1_b32 s4, s4, exec_lo
s_and_not1_b32 s6, s12, exec_lo
s_and_b32 s7, vcc_lo, exec_lo
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s3, s3, exec_lo
s_or_b32 s4, s4, s7
s_or_b32 s12, s6, s3
s_or_b32 exec_lo, exec_lo, s5
s_load_b64 s[6:7], s[0:1], 0x20
s_mov_b32 s5, 0
s_and_saveexec_b32 s3, s12
s_cbranch_execz .LBB0_8
s_add_i32 s5, s8, -1
s_mov_b32 s13, -1
v_cmp_ne_u32_e32 vcc_lo, s5, v3
s_mov_b32 s5, 0
s_and_saveexec_b32 s12, vcc_lo
s_cbranch_execz .LBB0_7
v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v4, 1, v0
s_waitcnt lgkmcnt(0)
v_add_f64 v[8:9], s[6:7], s[6:7]
s_mov_b32 s5, exec_lo
s_xor_b32 s13, exec_lo, -1
v_lshlrev_b64 v[6:7], 3, v[4:5]
v_add_nc_u32_e32 v4, -1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[4:5], 3, v[4:5]
v_add_co_u32 v6, vcc_lo, s10, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo
v_add_co_u32 v4, vcc_lo, s10, v4
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
s_clause 0x1
global_load_b64 v[6:7], v[6:7], off
global_load_b64 v[4:5], v[4:5], off
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[6:7], -v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[6:7], null, v[8:9], v[8:9], v[4:5]
v_rcp_f64_e32 v[10:11], v[6:7]
s_waitcnt_depctr 0xfff
v_fma_f64 v[12:13], -v[6:7], v[10:11], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
v_fma_f64 v[12:13], -v[6:7], v[10:11], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
v_div_scale_f64 v[12:13], vcc_lo, v[4:5], v[8:9], v[4:5]
v_mul_f64 v[14:15], v[12:13], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], -v[6:7], v[14:15], v[12:13]
v_div_fmas_f64 v[6:7], v[6:7], v[10:11], v[14:15]
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f64 v[4:5], v[6:7], v[8:9], v[4:5]
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s12
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 s4, s4, exec_lo
s_and_b32 s12, s13, exec_lo
s_and_b32 s5, s5, exec_lo
s_or_b32 s4, s4, s12
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s18, s4
s_cbranch_execz .LBB0_36
s_clause 0x1
s_load_b64 s[14:15], s[0:1], 0x0
s_load_b64 s[12:13], s[0:1], 0x28
s_add_i32 s17, s9, -1
s_mov_b32 s4, -1
v_cmp_eq_u32_e64 s3, s17, v2
s_mov_b32 s21, 0
s_mov_b32 s22, 0
s_mov_b32 s19, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s23, s2, s3
s_xor_b32 s24, s23, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s16, s24
s_cbranch_execz .LBB0_15
s_add_i32 s4, s8, -1
v_cmp_ne_u32_e32 vcc_lo, 0, v3
v_cmp_ne_u32_e64 s4, s4, v3
s_mov_b32 s20, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s19, vcc_lo, s4
s_mov_b32 s4, 0
s_and_saveexec_b32 s22, s19
s_xor_b32 s19, exec_lo, s22
s_and_b32 s4, s24, exec_lo
s_and_b32 s20, s23, exec_lo
s_or_saveexec_b32 s19, s19
s_mov_b32 s22, s5
s_xor_b32 exec_lo, exec_lo, s19
s_cbranch_execz .LBB0_14
v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v4, s8, v0
s_waitcnt lgkmcnt(0)
v_add_f64 v[8:9], s[12:13], s[12:13]
s_or_b32 s22, s5, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 3, v[4:5]
v_subrev_nc_u32_e32 v4, s8, v0
v_lshlrev_b64 v[4:5], 3, v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v6, vcc_lo, s14, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s15, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s14, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s15, v5, vcc_lo
s_clause 0x1
global_load_b64 v[6:7], v[6:7], off
global_load_b64 v[4:5], v[4:5], off
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[6:7], -v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[6:7], null, v[8:9], v[8:9], v[4:5]
v_rcp_f64_e32 v[10:11], v[6:7]
s_waitcnt_depctr 0xfff
v_fma_f64 v[12:13], -v[6:7], v[10:11], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
v_fma_f64 v[12:13], -v[6:7], v[10:11], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
v_div_scale_f64 v[12:13], vcc_lo, v[4:5], v[8:9], v[4:5]
v_mul_f64 v[14:15], v[12:13], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], -v[6:7], v[14:15], v[12:13]
v_div_fmas_f64 v[6:7], v[6:7], v[10:11], v[14:15]
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f64 v[4:5], v[6:7], v[8:9], v[4:5]
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s19
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s19, s5, exec_lo
s_and_b32 s22, s22, exec_lo
s_or_b32 s19, s19, s22
s_and_b32 s22, s4, exec_lo
s_or_not1_b32 s4, s20, exec_lo
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s16
s_and_saveexec_b32 s20, s4
s_add_i32 s16, s8, -1
v_cmp_eq_u32_e32 vcc_lo, 0, v3
v_cmp_eq_u32_e64 s4, s16, v3
s_mov_b32 s21, exec_lo
s_and_b32 s24, vcc_lo, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_or_b32 s23, vcc_lo, s4
s_and_b32 s25, s4, exec_lo
s_xor_b32 s23, s23, -1
s_and_not1_b32 s4, s22, exec_lo
s_and_b32 s22, s23, exec_lo
s_or_b32 s22, s4, s22
s_or_b32 exec_lo, exec_lo, s20
s_and_saveexec_b32 s4, s22
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s20, exec_lo, s4
s_cbranch_execz .LBB0_19
v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v4, 1, v0
s_waitcnt lgkmcnt(0)
v_add_f64 v[12:13], s[6:7], s[6:7]
s_or_b32 s19, s19, exec_lo
s_and_not1_b32 s21, s21, exec_lo
v_lshlrev_b64 v[6:7], 3, v[4:5]
v_add_nc_u32_e32 v4, -1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[8:9], 3, v[4:5]
v_add_nc_u32_e32 v4, s8, v0
v_add_co_u32 v6, vcc_lo, s10, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[10:11], 3, v[4:5]
v_subrev_nc_u32_e32 v4, s8, v0
v_add_co_u32 v8, vcc_lo, s10, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s11, v9, vcc_lo
v_lshlrev_b64 v[4:5], 3, v[4:5]
v_add_co_u32 v10, vcc_lo, s14, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s15, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s14, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s15, v5, vcc_lo
s_clause 0x1
global_load_b64 v[6:7], v[6:7], off
global_load_b64 v[8:9], v[8:9], off
s_clause 0x1
global_load_b64 v[10:11], v[10:11], off
global_load_b64 v[4:5], v[4:5], off
s_waitcnt vmcnt(2)
v_add_f64 v[6:7], v[6:7], -v[8:9]
v_add_f64 v[8:9], s[12:13], s[12:13]
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[10:11], -v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_scale_f64 v[10:11], null, v[12:13], v[12:13], v[6:7]
v_div_scale_f64 v[14:15], null, v[8:9], v[8:9], v[4:5]
v_div_scale_f64 v[24:25], vcc_lo, v[6:7], v[12:13], v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f64_e32 v[16:17], v[10:11]
v_rcp_f64_e32 v[18:19], v[14:15]
s_waitcnt_depctr 0xfff
v_fma_f64 v[20:21], -v[10:11], v[16:17], 1.0
v_fma_f64 v[22:23], -v[14:15], v[18:19], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
v_fma_f64 v[18:19], v[18:19], v[22:23], v[18:19]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[20:21], -v[10:11], v[16:17], 1.0
v_fma_f64 v[22:23], -v[14:15], v[18:19], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
v_div_scale_f64 v[20:21], s4, v[4:5], v[8:9], v[4:5]
v_fma_f64 v[18:19], v[18:19], v[22:23], v[18:19]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[22:23], v[24:25], v[16:17]
v_mul_f64 v[26:27], v[20:21], v[18:19]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[10:11], -v[10:11], v[22:23], v[24:25]
v_fma_f64 v[14:15], -v[14:15], v[26:27], v[20:21]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[10:11], v[10:11], v[16:17], v[22:23]
s_mov_b32 vcc_lo, s4
v_div_fmas_f64 v[14:15], v[14:15], v[18:19], v[26:27]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f64 v[6:7], v[10:11], v[12:13], v[6:7]
v_div_fixup_f64 v[4:5], v[14:15], v[8:9], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[6:7], v[4:5]
v_mul_f64 v[4:5], v[4:5], 0.5
.LBB0_19:
s_or_b32 exec_lo, exec_lo, s20
s_and_saveexec_b32 s20, s21
s_cbranch_execz .LBB0_35
v_or_b32_e32 v1, v2, v3
s_mov_b32 s22, s19
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ne_u32_e32 0, v1
s_xor_b32 s21, exec_lo, s4
s_cbranch_execz .LBB0_32
s_and_b32 s2, s2, s25
s_mov_b32 s23, s19
s_xor_b32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_xor_b32 s22, exec_lo, s4
s_cbranch_execz .LBB0_29
s_and_b32 s2, s3, s24
s_mov_b32 s24, s19
s_xor_b32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_xor_b32 s23, exec_lo, s4
s_cbranch_execz .LBB0_26
s_and_b32 s3, s3, s25
s_mov_b32 s2, s19
s_and_saveexec_b32 s4, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s24, exec_lo, s4
s_cbranch_execz .LBB0_25
s_mul_i32 s4, s17, s8
s_mov_b32 s3, 0
s_add_i32 s2, s4, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[26:27], s[2:3], 3
s_waitcnt lgkmcnt(0)
s_add_u32 s28, s10, s26
s_addc_u32 s29, s11, s27
s_add_i32 s2, s4, -2
s_mul_i32 s4, s9, s8
s_lshl_b64 s[30:31], s[2:3], 3
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s34, s10, s30
s_addc_u32 s35, s11, s31
s_add_i32 s2, s4, -2
s_clause 0x1
s_load_b64 s[28:29], s[28:29], 0x0
s_load_b64 s[34:35], s[34:35], 0x0
s_lshl_b64 s[36:37], s[2:3], 3
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s38, s14, s36
s_addc_u32 s39, s15, s37
s_add_u32 s30, s14, s30
s_addc_u32 s31, s15, s31
s_clause 0x1
s_load_b64 s[38:39], s[38:39], 0x0
s_load_b64 s[30:31], s[30:31], 0x0
s_add_i32 s2, s4, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 3
s_waitcnt lgkmcnt(0)
v_add_f64 v[1:2], s[28:29], -s[34:35]
s_add_u32 s28, s14, s2
s_addc_u32 s29, s15, s3
s_add_u32 s26, s14, s26
s_addc_u32 s27, s15, s27
s_add_u32 s2, s10, s2
s_addc_u32 s3, s11, s3
v_add_f64 v[3:4], s[38:39], -s[30:31]
s_clause 0x1
s_load_b64 s[28:29], s[28:29], 0x0
s_load_b64 s[26:27], s[26:27], 0x0
s_add_u32 s30, s10, s36
s_addc_u32 s31, s11, s37
s_clause 0x1
s_load_b64 s[2:3], s[2:3], 0x0
s_load_b64 s[30:31], s[30:31], 0x0
s_waitcnt lgkmcnt(0)
v_add_f64 v[5:6], s[28:29], -s[26:27]
v_add_f64 v[9:10], s[2:3], -s[30:31]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_div_scale_f64 v[7:8], null, s[6:7], s[6:7], v[1:2]
v_div_scale_f64 v[11:12], null, s[12:13], s[12:13], v[3:4]
v_div_scale_f64 v[33:34], s2, v[3:4], s[12:13], v[3:4]
v_div_scale_f64 v[13:14], null, s[12:13], s[12:13], v[5:6]
v_div_scale_f64 v[17:18], null, s[6:7], s[6:7], v[9:10]
v_rcp_f64_e32 v[15:16], v[7:8]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f64_e32 v[19:20], v[11:12]
v_rcp_f64_e32 v[21:22], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(TRANS32_DEP_3)
v_rcp_f64_e32 v[25:26], v[17:18]
v_fma_f64 v[23:24], -v[7:8], v[15:16], 1.0
v_fma_f64 v[27:28], -v[11:12], v[19:20], 1.0
s_waitcnt_depctr 0xfff
v_fma_f64 v[29:30], -v[13:14], v[21:22], 1.0
v_fma_f64 v[15:16], v[15:16], v[23:24], v[15:16]
v_fma_f64 v[23:24], -v[17:18], v[25:26], 1.0
v_fma_f64 v[19:20], v[19:20], v[27:28], v[19:20]
s_delay_alu instid0(VALU_DEP_4)
v_fma_f64 v[21:22], v[21:22], v[29:30], v[21:22]
v_div_scale_f64 v[29:30], vcc_lo, v[1:2], s[6:7], v[1:2]
v_fma_f64 v[27:28], -v[7:8], v[15:16], 1.0
v_fma_f64 v[23:24], v[25:26], v[23:24], v[25:26]
v_fma_f64 v[25:26], -v[11:12], v[19:20], 1.0
v_fma_f64 v[31:32], -v[13:14], v[21:22], 1.0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[15:16], v[15:16], v[27:28], v[15:16]
v_fma_f64 v[27:28], -v[17:18], v[23:24], 1.0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[19:20], v[19:20], v[25:26], v[19:20]
v_fma_f64 v[21:22], v[21:22], v[31:32], v[21:22]
v_div_scale_f64 v[31:32], s3, v[5:6], s[12:13], v[5:6]
v_mul_f64 v[25:26], v[29:30], v[15:16]
v_fma_f64 v[23:24], v[23:24], v[27:28], v[23:24]
v_div_scale_f64 v[27:28], s4, v[9:10], s[6:7], v[9:10]
v_mul_f64 v[35:36], v[33:34], v[19:20]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_fma_f64 v[7:8], -v[7:8], v[25:26], v[29:30]
v_mul_f64 v[29:30], v[31:32], v[21:22]
v_mul_f64 v[37:38], v[27:28], v[23:24]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[11:12], -v[11:12], v[35:36], v[33:34]
v_div_fmas_f64 v[7:8], v[7:8], v[15:16], v[25:26]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_fma_f64 v[13:14], -v[13:14], v[29:30], v[31:32]
s_mov_b32 vcc_lo, s2
v_fma_f64 v[15:16], -v[17:18], v[37:38], v[27:28]
s_or_b32 s2, s19, exec_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_div_fmas_f64 v[11:12], v[11:12], v[19:20], v[35:36]
s_mov_b32 vcc_lo, s3
v_div_fixup_f64 v[1:2], v[7:8], s[6:7], v[1:2]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_div_fmas_f64 v[7:8], v[13:14], v[21:22], v[29:30]
s_mov_b32 vcc_lo, s4
v_div_fmas_f64 v[13:14], v[15:16], v[23:24], v[37:38]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fixup_f64 v[3:4], v[11:12], s[12:13], v[3:4]
v_div_fixup_f64 v[5:6], v[7:8], s[12:13], v[5:6]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fixup_f64 v[7:8], v[13:14], s[6:7], v[9:10]
v_add_f64 v[1:2], v[1:2], v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[3:4], v[5:6], v[7:8]
v_ldexp_f64 v[1:2], -v[1:2], -2
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[4:5], v[3:4], 0x3fe80000, v[1:2]
.LBB0_25:
s_or_b32 exec_lo, exec_lo, s24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s3, s19, exec_lo
s_and_b32 s2, s2, exec_lo
s_or_b32 s24, s3, s2
.LBB0_26:
s_and_not1_saveexec_b32 s23, s23
s_cbranch_execz .LBB0_28
s_add_i32 s2, s9, -2
s_mov_b32 s27, 0
s_mul_i32 s2, s2, s8
s_mov_b32 s3, s27
s_add_i32 s26, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[28:29], s[26:27], 3
s_mul_i32 s26, s17, s8
s_waitcnt lgkmcnt(0)
s_add_u32 s30, s10, s28
s_addc_u32 s31, s11, s29
s_lshl_b64 s[2:3], s[2:3], 3
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s34, s10, s2
s_addc_u32 s35, s11, s3
s_lshl_b64 s[36:37], s[26:27], 3
s_clause 0x1
s_load_b64 s[30:31], s[30:31], 0x0
s_load_b64 s[34:35], s[34:35], 0x0
s_add_u32 s38, s14, s36
s_addc_u32 s39, s15, s37
s_add_u32 s2, s14, s2
s_addc_u32 s3, s15, s3
s_add_u32 s28, s14, s28
s_addc_u32 s29, s15, s29
s_clause 0x2
s_load_b64 s[38:39], s[38:39], 0x0
s_load_b64 s[2:3], s[2:3], 0x0
s_load_b64 s[28:29], s[28:29], 0x0
s_add_i32 s26, s26, 1
s_waitcnt lgkmcnt(0)
v_add_f64 v[1:2], s[30:31], -s[34:35]
v_add_f64 v[3:4], s[38:39], -s[2:3]
v_add_f64 v[5:6], s[38:39], -s[28:29]
s_lshl_b64 s[2:3], s[26:27], 3
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s2, s10, s2
s_addc_u32 s3, s11, s3
s_add_u32 s26, s10, s36
s_addc_u32 s27, s11, s37
s_clause 0x1
s_load_b64 s[2:3], s[2:3], 0x0
s_load_b64 s[26:27], s[26:27], 0x0
s_or_b32 s24, s24, exec_lo
s_waitcnt lgkmcnt(0)
v_add_f64 v[7:8], s[2:3], -s[26:27]
s_delay_alu instid0(VALU_DEP_4)
v_div_scale_f64 v[9:10], null, s[6:7], s[6:7], v[1:2]
v_div_scale_f64 v[33:34], vcc_lo, v[1:2], s[6:7], v[1:2]
v_div_scale_f64 v[11:12], null, s[12:13], s[12:13], v[3:4]
v_div_scale_f64 v[13:14], null, s[12:13], s[12:13], v[5:6]
v_div_scale_f64 v[15:16], null, s[6:7], s[6:7], v[7:8]
v_rcp_f64_e32 v[17:18], v[9:10]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f64_e32 v[19:20], v[11:12]
v_rcp_f64_e32 v[21:22], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(TRANS32_DEP_3)
v_rcp_f64_e32 v[23:24], v[15:16]
v_fma_f64 v[25:26], -v[9:10], v[17:18], 1.0
v_fma_f64 v[27:28], -v[11:12], v[19:20], 1.0
s_waitcnt_depctr 0xfff
v_fma_f64 v[29:30], -v[13:14], v[21:22], 1.0
v_fma_f64 v[31:32], -v[15:16], v[23:24], 1.0
v_fma_f64 v[17:18], v[17:18], v[25:26], v[17:18]
v_fma_f64 v[19:20], v[19:20], v[27:28], v[19:20]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[21:22], v[21:22], v[29:30], v[21:22]
v_fma_f64 v[23:24], v[23:24], v[31:32], v[23:24]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[25:26], -v[9:10], v[17:18], 1.0
v_fma_f64 v[27:28], -v[11:12], v[19:20], 1.0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[29:30], -v[13:14], v[21:22], 1.0
v_fma_f64 v[31:32], -v[15:16], v[23:24], 1.0
s_delay_alu instid0(VALU_DEP_4)
v_fma_f64 v[17:18], v[17:18], v[25:26], v[17:18]
v_div_scale_f64 v[25:26], s2, v[3:4], s[12:13], v[3:4]
v_fma_f64 v[19:20], v[19:20], v[27:28], v[19:20]
v_div_scale_f64 v[27:28], s3, v[5:6], s[12:13], v[5:6]
v_fma_f64 v[21:22], v[21:22], v[29:30], v[21:22]
v_div_scale_f64 v[29:30], s4, v[7:8], s[6:7], v[7:8]
v_fma_f64 v[23:24], v[23:24], v[31:32], v[23:24]
v_mul_f64 v[31:32], v[33:34], v[17:18]
v_mul_f64 v[35:36], v[25:26], v[19:20]
v_mul_f64 v[37:38], v[27:28], v[21:22]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_f64 v[39:40], v[29:30], v[23:24]
v_fma_f64 v[9:10], -v[9:10], v[31:32], v[33:34]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[11:12], -v[11:12], v[35:36], v[25:26]
v_fma_f64 v[13:14], -v[13:14], v[37:38], v[27:28]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[15:16], -v[15:16], v[39:40], v[29:30]
v_div_fmas_f64 v[9:10], v[9:10], v[17:18], v[31:32]
s_mov_b32 vcc_lo, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_div_fmas_f64 v[11:12], v[11:12], v[19:20], v[35:36]
s_mov_b32 vcc_lo, s3
v_div_fmas_f64 v[13:14], v[13:14], v[21:22], v[37:38]
s_mov_b32 vcc_lo, s4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_div_fixup_f64 v[1:2], v[9:10], s[6:7], v[1:2]
v_div_fmas_f64 v[9:10], v[15:16], v[23:24], v[39:40]
v_div_fixup_f64 v[3:4], v[11:12], s[12:13], v[3:4]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fixup_f64 v[5:6], v[13:14], s[12:13], v[5:6]
v_div_fixup_f64 v[7:8], v[9:10], s[6:7], v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[1:2], v[1:2], v[5:6]
v_add_f64 v[3:4], v[3:4], v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[1:2], -v[1:2], -2
v_fma_f64 v[4:5], v[3:4], 0x3fe80000, v[1:2]
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s23
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s19, exec_lo
s_and_b32 s3, s24, exec_lo
s_or_b32 s23, s2, s3
.LBB0_29:
s_and_not1_saveexec_b32 s9, s22
s_cbranch_execz .LBB0_31
s_mov_b32 s17, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[16:17], 3
s_waitcnt lgkmcnt(0)
s_add_u32 s24, s10, s2
s_addc_u32 s25, s11, s3
s_add_i32 s16, s8, -2
s_lshl_b64 s[26:27], s[16:17], 3
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s28, s10, s26
s_addc_u32 s29, s11, s27
s_lshl_b32 s4, s8, 1
s_clause 0x1
s_load_b64 s[24:25], s[24:25], 0x0
s_load_b64 s[28:29], s[28:29], 0x0
s_add_i32 s16, s4, -2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[30:31], s[16:17], 3
s_add_u32 s34, s14, s30
s_addc_u32 s35, s15, s31
s_add_u32 s26, s14, s26
s_addc_u32 s27, s15, s27
s_add_i32 s16, s4, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[16:17], s[16:17], 3
s_add_u32 s36, s14, s16
s_addc_u32 s37, s15, s17
s_add_u32 s2, s14, s2
s_addc_u32 s3, s15, s3
s_add_u32 s16, s10, s16
s_addc_u32 s17, s11, s17
s_clause 0x3
s_load_b64 s[34:35], s[34:35], 0x0
s_load_b64 s[26:27], s[26:27], 0x0
s_load_b64 s[36:37], s[36:37], 0x0
s_load_b64 s[2:3], s[2:3], 0x0
s_add_u32 s30, s10, s30
s_addc_u32 s31, s11, s31
s_clause 0x1
s_load_b64 s[16:17], s[16:17], 0x0
s_load_b64 s[30:31], s[30:31], 0x0
s_waitcnt lgkmcnt(0)
v_add_f64 v[1:2], s[24:25], -s[28:29]
s_or_b32 s23, s23, exec_lo
v_add_f64 v[3:4], s[34:35], -s[26:27]
v_add_f64 v[5:6], s[36:37], -s[2:3]
v_add_f64 v[7:8], s[16:17], -s[30:31]
s_delay_alu instid0(VALU_DEP_4)
v_div_scale_f64 v[9:10], null, s[6:7], s[6:7], v[1:2]
v_div_scale_f64 v[33:34], vcc_lo, v[1:2], s[6:7], v[1:2]
v_div_scale_f64 v[11:12], null, s[12:13], s[12:13], v[3:4]
v_div_scale_f64 v[13:14], null, s[12:13], s[12:13], v[5:6]
v_div_scale_f64 v[15:16], null, s[6:7], s[6:7], v[7:8]
v_rcp_f64_e32 v[17:18], v[9:10]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f64_e32 v[19:20], v[11:12]
v_rcp_f64_e32 v[21:22], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(TRANS32_DEP_3)
v_rcp_f64_e32 v[23:24], v[15:16]
v_fma_f64 v[25:26], -v[9:10], v[17:18], 1.0
v_fma_f64 v[27:28], -v[11:12], v[19:20], 1.0
s_waitcnt_depctr 0xfff
v_fma_f64 v[29:30], -v[13:14], v[21:22], 1.0
v_fma_f64 v[31:32], -v[15:16], v[23:24], 1.0
v_fma_f64 v[17:18], v[17:18], v[25:26], v[17:18]
v_fma_f64 v[19:20], v[19:20], v[27:28], v[19:20]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[21:22], v[21:22], v[29:30], v[21:22]
v_fma_f64 v[23:24], v[23:24], v[31:32], v[23:24]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[25:26], -v[9:10], v[17:18], 1.0
v_fma_f64 v[27:28], -v[11:12], v[19:20], 1.0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[29:30], -v[13:14], v[21:22], 1.0
v_fma_f64 v[31:32], -v[15:16], v[23:24], 1.0
s_delay_alu instid0(VALU_DEP_4)
v_fma_f64 v[17:18], v[17:18], v[25:26], v[17:18]
v_div_scale_f64 v[25:26], s2, v[3:4], s[12:13], v[3:4]
v_fma_f64 v[19:20], v[19:20], v[27:28], v[19:20]
v_div_scale_f64 v[27:28], s3, v[5:6], s[12:13], v[5:6]
v_fma_f64 v[21:22], v[21:22], v[29:30], v[21:22]
v_div_scale_f64 v[29:30], s4, v[7:8], s[6:7], v[7:8]
v_fma_f64 v[23:24], v[23:24], v[31:32], v[23:24]
v_mul_f64 v[31:32], v[33:34], v[17:18]
v_mul_f64 v[35:36], v[25:26], v[19:20]
v_mul_f64 v[37:38], v[27:28], v[21:22]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_f64 v[39:40], v[29:30], v[23:24]
v_fma_f64 v[9:10], -v[9:10], v[31:32], v[33:34]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[11:12], -v[11:12], v[35:36], v[25:26]
v_fma_f64 v[13:14], -v[13:14], v[37:38], v[27:28]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[15:16], -v[15:16], v[39:40], v[29:30]
v_div_fmas_f64 v[9:10], v[9:10], v[17:18], v[31:32]
s_mov_b32 vcc_lo, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_div_fmas_f64 v[11:12], v[11:12], v[19:20], v[35:36]
s_mov_b32 vcc_lo, s3
v_div_fmas_f64 v[13:14], v[13:14], v[21:22], v[37:38]
s_mov_b32 vcc_lo, s4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_div_fmas_f64 v[15:16], v[15:16], v[23:24], v[39:40]
v_div_fixup_f64 v[1:2], v[9:10], s[6:7], v[1:2]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_div_fixup_f64 v[3:4], v[11:12], s[12:13], v[3:4]
v_div_fixup_f64 v[5:6], v[13:14], s[12:13], v[5:6]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f64 v[7:8], v[15:16], s[6:7], v[7:8]
v_add_f64 v[1:2], v[1:2], v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[3:4], v[3:4], v[7:8]
v_ldexp_f64 v[3:4], -v[3:4], -2
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[4:5], v[1:2], 0x3fe80000, v[3:4]
.LBB0_31:
s_or_b32 exec_lo, exec_lo, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s19, exec_lo
s_and_b32 s3, s23, exec_lo
s_or_b32 s22, s2, s3
.LBB0_32:
s_and_not1_saveexec_b32 s16, s21
s_cbranch_execz .LBB0_34
s_mov_b32 s9, 0
s_waitcnt lgkmcnt(0)
s_load_b128 s[24:27], s[10:11], 0x0
s_lshl_b64 s[2:3], s[8:9], 3
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s28, s14, s2
s_addc_u32 s29, s15, s3
s_add_i32 s8, s8, 1
s_clause 0x1
s_load_b64 s[34:35], s[28:29], 0x0
s_load_b128 s[28:31], s[14:15], 0x0
s_lshl_b64 s[8:9], s[8:9], 3
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s14, s14, s8
s_addc_u32 s15, s15, s9
s_add_u32 s8, s10, s8
s_addc_u32 s9, s11, s9
s_load_b64 s[14:15], s[14:15], 0x0
s_add_u32 s2, s10, s2
s_addc_u32 s3, s11, s3
s_clause 0x1
s_load_b64 s[8:9], s[8:9], 0x0
s_load_b64 s[2:3], s[2:3], 0x0
s_or_b32 s22, s22, exec_lo
s_waitcnt lgkmcnt(0)
v_add_f64 v[1:2], s[26:27], -s[24:25]
v_add_f64 v[3:4], s[34:35], -s[28:29]
v_add_f64 v[5:6], s[14:15], -s[30:31]
v_add_f64 v[7:8], s[8:9], -s[2:3]
s_delay_alu instid0(VALU_DEP_4)
v_div_scale_f64 v[9:10], null, s[6:7], s[6:7], v[1:2]
v_div_scale_f64 v[33:34], vcc_lo, v[1:2], s[6:7], v[1:2]
v_div_scale_f64 v[11:12], null, s[12:13], s[12:13], v[3:4]
v_div_scale_f64 v[13:14], null, s[12:13], s[12:13], v[5:6]
v_div_scale_f64 v[15:16], null, s[6:7], s[6:7], v[7:8]
v_rcp_f64_e32 v[17:18], v[9:10]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f64_e32 v[19:20], v[11:12]
v_rcp_f64_e32 v[21:22], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(TRANS32_DEP_3)
v_rcp_f64_e32 v[23:24], v[15:16]
v_fma_f64 v[25:26], -v[9:10], v[17:18], 1.0
v_fma_f64 v[27:28], -v[11:12], v[19:20], 1.0
s_waitcnt_depctr 0xfff
v_fma_f64 v[29:30], -v[13:14], v[21:22], 1.0
v_fma_f64 v[31:32], -v[15:16], v[23:24], 1.0
v_fma_f64 v[17:18], v[17:18], v[25:26], v[17:18]
v_fma_f64 v[19:20], v[19:20], v[27:28], v[19:20]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[21:22], v[21:22], v[29:30], v[21:22]
v_fma_f64 v[23:24], v[23:24], v[31:32], v[23:24]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[25:26], -v[9:10], v[17:18], 1.0
v_fma_f64 v[27:28], -v[11:12], v[19:20], 1.0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[29:30], -v[13:14], v[21:22], 1.0
v_fma_f64 v[31:32], -v[15:16], v[23:24], 1.0
s_delay_alu instid0(VALU_DEP_4)
v_fma_f64 v[17:18], v[17:18], v[25:26], v[17:18]
v_div_scale_f64 v[25:26], s2, v[3:4], s[12:13], v[3:4]
v_fma_f64 v[19:20], v[19:20], v[27:28], v[19:20]
v_div_scale_f64 v[27:28], s3, v[5:6], s[12:13], v[5:6]
v_fma_f64 v[21:22], v[21:22], v[29:30], v[21:22]
v_div_scale_f64 v[29:30], s4, v[7:8], s[6:7], v[7:8]
v_fma_f64 v[23:24], v[23:24], v[31:32], v[23:24]
v_mul_f64 v[31:32], v[33:34], v[17:18]
v_mul_f64 v[35:36], v[25:26], v[19:20]
v_mul_f64 v[37:38], v[27:28], v[21:22]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_f64 v[39:40], v[29:30], v[23:24]
v_fma_f64 v[9:10], -v[9:10], v[31:32], v[33:34]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[11:12], -v[11:12], v[35:36], v[25:26]
v_fma_f64 v[13:14], -v[13:14], v[37:38], v[27:28]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[15:16], -v[15:16], v[39:40], v[29:30]
v_div_fmas_f64 v[9:10], v[9:10], v[17:18], v[31:32]
s_mov_b32 vcc_lo, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_div_fmas_f64 v[11:12], v[11:12], v[19:20], v[35:36]
s_mov_b32 vcc_lo, s3
v_div_fmas_f64 v[13:14], v[13:14], v[21:22], v[37:38]
s_mov_b32 vcc_lo, s4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_div_fmas_f64 v[15:16], v[15:16], v[23:24], v[39:40]
v_div_fixup_f64 v[1:2], v[9:10], s[6:7], v[1:2]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_div_fixup_f64 v[3:4], v[11:12], s[12:13], v[3:4]
v_div_fixup_f64 v[5:6], v[13:14], s[12:13], v[5:6]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fixup_f64 v[7:8], v[15:16], s[6:7], v[7:8]
v_add_f64 v[1:2], v[1:2], v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[5:6], v[7:8]
v_ldexp_f64 v[3:4], -v[5:6], -2
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[4:5], v[1:2], 0x3fe80000, v[3:4]
.LBB0_34:
s_or_b32 exec_lo, exec_lo, s16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s19, exec_lo
s_and_b32 s3, s22, exec_lo
s_or_b32 s19, s2, s3
.LBB0_35:
s_or_b32 exec_lo, exec_lo, s20
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s5, exec_lo
s_and_b32 s3, s19, exec_lo
s_or_b32 s5, s2, s3
.LBB0_36:
s_or_b32 exec_lo, exec_lo, s18
s_and_saveexec_b32 s2, s5
s_cbranch_execz .LBB0_38
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[4:5], off
.LBB0_38:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24update_mixed_derivativesPdS_S_jjddj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 52
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 41
.amdhsa_next_free_sgpr 40
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24update_mixed_derivativesPdS_S_jjddj, .Lfunc_end0-_Z24update_mixed_derivativesPdS_S_jjddj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 52
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24update_mixed_derivativesPdS_S_jjddj
.private_segment_fixed_size: 0
.sgpr_count: 42
.sgpr_spill_count: 0
.symbol: _Z24update_mixed_derivativesPdS_S_jjddj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 41
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void update_mixed_derivatives(double *temppsix, double *temppsiy, double *temppsixy, unsigned int nx, unsigned int ny, double dx, double dy, unsigned int TileSize)
{
unsigned int bx = blockIdx.x;
unsigned int by = blockIdx.y;
unsigned int tx = threadIdx.x;
unsigned int ty = threadIdx.y;
unsigned int index_x = bx * TileSize + tx;
unsigned int index_y = by * TileSize + ty;
unsigned int indexToWrite = index_y * nx + index_x;
if ((index_y == 0 || index_y == ny - 1) && (index_x != 0 && index_x != nx - 1))
temppsixy[indexToWrite] = (temppsiy[indexToWrite+1] - temppsiy[indexToWrite-1])/(2 * dx);
else
if ((index_y != 0 && index_y != ny - 1) && (index_x == 0 || index_x == nx - 1))
temppsixy[indexToWrite] = (temppsix[indexToWrite + nx] - temppsix[indexToWrite - nx])/(2 * dy);
else
if((index_y == 0 || index_y == ny - 1) && (index_x == 0 || index_x == nx - 1)){
if(index_y == 0 && index_x == 0){
double d1 = (temppsiy[1] - temppsiy[0])/dx;
double d2 = (temppsix[nx] - temppsix[0])/dy;
double d3 = (temppsix[nx+1] - temppsix[1])/dy;
double d4 = (temppsiy[nx+1] - temppsiy[nx])/dx;
temppsixy[indexToWrite] = 0.75 * (d1 + d2) - 0.25 * (d3 + d4);
}
else if(index_y == 0 && index_x == nx-1){
double d1 = (temppsiy[nx-1] - temppsiy[nx-2])/dx;
double d2 = (temppsix[nx+nx-2] - temppsix[nx-2])/dy;
double d3 = (temppsix[nx+nx-1] - temppsix[nx-1])/dy;
double d4 = (temppsiy[nx+nx-1] - temppsiy[nx+nx-2])/dx;
temppsixy[indexToWrite] = 0.75 * (d1 + d3) - 0.25 * (d2 + d4);
}
else if(index_y == ny-1 && index_x == 0){
double d1 = (temppsiy[nx *(ny-2) + 1] - temppsiy[nx *(ny-2)])/dx;
double d2 = (temppsix[nx *(ny-1)] - temppsix[nx *(ny-2)])/dy;
double d3 = (temppsix[nx *(ny-1)] - temppsix[nx *(ny-2) + 1])/dy;
double d4 = (temppsiy[nx *(ny-1) + 1] - temppsiy[nx *(ny-1)])/dx;
temppsixy[indexToWrite] = 0.75 * (d2 + d4) - 0.25 * (d3 + d1);
}
else if(index_y == ny-1 && index_x == nx-1){
double d1 = (temppsiy[nx *(ny-2) + nx - 1] - temppsiy[nx *(ny-2) + nx - 2])/dx;
double d2 = (temppsix[nx *(ny-1) + nx - 2] - temppsix[nx *(ny-2) + nx - 2])/dy;
double d3 = (temppsix[nx *(ny-1) + nx - 1] - temppsix[nx *(ny-2) + nx - 1])/dy;
double d4 = (temppsiy[nx *(ny-1) + nx - 1] - temppsiy[nx *(ny-1) + nx - 2])/dx;
temppsixy[indexToWrite] = 0.75 * (d3 + d4) - 0.25 * (d1 + d2);
}
}
else{
double dxy1 = (temppsiy[indexToWrite+1] - temppsiy[indexToWrite-1])/(2 * dx);
double dxy2 = (temppsix[indexToWrite + nx] - temppsix[indexToWrite - nx])/(2 * dy);
temppsixy[indexToWrite] = (dxy1 + dxy2)/2.0;
}
} | .text
.file "update_mixed_derivatives.hip"
.globl _Z39__device_stub__update_mixed_derivativesPdS_S_jjddj # -- Begin function _Z39__device_stub__update_mixed_derivativesPdS_S_jjddj
.p2align 4, 0x90
.type _Z39__device_stub__update_mixed_derivativesPdS_S_jjddj,@function
_Z39__device_stub__update_mixed_derivativesPdS_S_jjddj: # @_Z39__device_stub__update_mixed_derivativesPdS_S_jjddj
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movsd %xmm0, 80(%rsp)
movsd %xmm1, 72(%rsp)
movl %r9d, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rax
movq %rax, 152(%rsp)
leaq 72(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z24update_mixed_derivativesPdS_S_jjddj, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z39__device_stub__update_mixed_derivativesPdS_S_jjddj, .Lfunc_end0-_Z39__device_stub__update_mixed_derivativesPdS_S_jjddj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24update_mixed_derivativesPdS_S_jjddj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24update_mixed_derivativesPdS_S_jjddj,@object # @_Z24update_mixed_derivativesPdS_S_jjddj
.section .rodata,"a",@progbits
.globl _Z24update_mixed_derivativesPdS_S_jjddj
.p2align 3, 0x0
_Z24update_mixed_derivativesPdS_S_jjddj:
.quad _Z39__device_stub__update_mixed_derivativesPdS_S_jjddj
.size _Z24update_mixed_derivativesPdS_S_jjddj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24update_mixed_derivativesPdS_S_jjddj"
.size .L__unnamed_1, 40
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__update_mixed_derivativesPdS_S_jjddj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24update_mixed_derivativesPdS_S_jjddj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00137321_00000000-6_update_mixed_derivatives.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z53__device_stub__Z24update_mixed_derivativesPdS_S_jjddjPdS_S_jjddj
.type _Z53__device_stub__Z24update_mixed_derivativesPdS_S_jjddjPdS_S_jjddj, @function
_Z53__device_stub__Z24update_mixed_derivativesPdS_S_jjddjPdS_S_jjddj:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movl %ecx, 36(%rsp)
movl %r8d, 32(%rsp)
movsd %xmm0, 24(%rsp)
movsd %xmm1, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 12(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z24update_mixed_derivativesPdS_S_jjddj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z53__device_stub__Z24update_mixed_derivativesPdS_S_jjddjPdS_S_jjddj, .-_Z53__device_stub__Z24update_mixed_derivativesPdS_S_jjddjPdS_S_jjddj
.globl _Z24update_mixed_derivativesPdS_S_jjddj
.type _Z24update_mixed_derivativesPdS_S_jjddj, @function
_Z24update_mixed_derivativesPdS_S_jjddj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z24update_mixed_derivativesPdS_S_jjddjPdS_S_jjddj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z24update_mixed_derivativesPdS_S_jjddj, .-_Z24update_mixed_derivativesPdS_S_jjddj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24update_mixed_derivativesPdS_S_jjddj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24update_mixed_derivativesPdS_S_jjddj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "update_mixed_derivatives.hip"
.globl _Z39__device_stub__update_mixed_derivativesPdS_S_jjddj # -- Begin function _Z39__device_stub__update_mixed_derivativesPdS_S_jjddj
.p2align 4, 0x90
.type _Z39__device_stub__update_mixed_derivativesPdS_S_jjddj,@function
_Z39__device_stub__update_mixed_derivativesPdS_S_jjddj: # @_Z39__device_stub__update_mixed_derivativesPdS_S_jjddj
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movsd %xmm0, 80(%rsp)
movsd %xmm1, 72(%rsp)
movl %r9d, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rax
movq %rax, 152(%rsp)
leaq 72(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z24update_mixed_derivativesPdS_S_jjddj, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z39__device_stub__update_mixed_derivativesPdS_S_jjddj, .Lfunc_end0-_Z39__device_stub__update_mixed_derivativesPdS_S_jjddj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24update_mixed_derivativesPdS_S_jjddj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24update_mixed_derivativesPdS_S_jjddj,@object # @_Z24update_mixed_derivativesPdS_S_jjddj
.section .rodata,"a",@progbits
.globl _Z24update_mixed_derivativesPdS_S_jjddj
.p2align 3, 0x0
_Z24update_mixed_derivativesPdS_S_jjddj:
.quad _Z39__device_stub__update_mixed_derivativesPdS_S_jjddj
.size _Z24update_mixed_derivativesPdS_S_jjddj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24update_mixed_derivativesPdS_S_jjddj"
.size .L__unnamed_1, 40
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__update_mixed_derivativesPdS_S_jjddj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24update_mixed_derivativesPdS_S_jjddj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | extern "C"
__device__
float saxpy_dev(float a, float x, float y)
{
return a * x + y;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C"
__device__
float saxpy_dev(float a, float x, float y)
{
return a * x + y;
} | .file "tmpxft_001ae96f_00000000-6_saxpy_cuda_device.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl saxpy_dev
.type saxpy_dev, @function
saxpy_dev:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size saxpy_dev, .-saxpy_dev
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C"
__device__
float saxpy_dev(float a, float x, float y)
{
return a * x + y;
} | #include <hip/hip_runtime.h>
extern "C"
__device__
float saxpy_dev(float a, float x, float y)
{
return a * x + y;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C"
__device__
float saxpy_dev(float a, float x, float y)
{
return a * x + y;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C"
__device__
float saxpy_dev(float a, float x, float y)
{
return a * x + y;
} | .text
.file "saxpy_cuda_device.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001ae96f_00000000-6_saxpy_cuda_device.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl saxpy_dev
.type saxpy_dev, @function
saxpy_dev:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size saxpy_dev, .-saxpy_dev
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "saxpy_cuda_device.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
Jaitirth Jacob - 13CO125 Vidit Bhargava - 13CO151
*/
#include <stdio.h>
int main()
{
int count;
cudaGetDeviceCount(&count);
printf("Device Queries:\n");
printf("There are %d CUDA devices.\n", count);
for (int i = 0; i < count; ++i)
{
printf("\nCUDA Device #%d\n", i);
cudaDeviceProp devProp;
cudaGetDeviceProperties(&devProp, i);
printf("\tDevice Identification: %s\n", devProp.name);
printf("\tGlobal memory: %u\n", devProp.totalGlobalMem);
printf("\tShared memory per block: %u\n", devProp.sharedMemPerBlock);
printf("\tNumber of registers per block: %d\n", devProp.regsPerBlock);
printf("\tNumber of thread in warp: %d\n", devProp.warpSize);
printf("\tMaximum threads per block: %d\n", devProp.maxThreadsPerBlock);
for (int i = 0; i < 3; ++i)
printf("\tMaximum dimension %d of block: %d\n", i, devProp.maxThreadsDim[i]);
for (int i = 0; i < 3; ++i)
printf("\tMaximum dimension %d of grid: %d\n", i, devProp.maxGridSize[i]);
printf("\tAvailable constant memory: %u\n", devProp.totalConstMem);
printf("\tMajor revision number: %d\n", devProp.major);
printf("\tMinor revision number: %d\n", devProp.minor);
printf("\tNumber of multiprocessors: %d\n", devProp.multiProcessorCount);
printf("\tClock rate: %d\n", devProp.clockRate);
}
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
Jaitirth Jacob - 13CO125 Vidit Bhargava - 13CO151
*/
#include <stdio.h>
int main()
{
int count;
cudaGetDeviceCount(&count);
printf("Device Queries:\n");
printf("There are %d CUDA devices.\n", count);
for (int i = 0; i < count; ++i)
{
printf("\nCUDA Device #%d\n", i);
cudaDeviceProp devProp;
cudaGetDeviceProperties(&devProp, i);
printf("\tDevice Identification: %s\n", devProp.name);
printf("\tGlobal memory: %u\n", devProp.totalGlobalMem);
printf("\tShared memory per block: %u\n", devProp.sharedMemPerBlock);
printf("\tNumber of registers per block: %d\n", devProp.regsPerBlock);
printf("\tNumber of thread in warp: %d\n", devProp.warpSize);
printf("\tMaximum threads per block: %d\n", devProp.maxThreadsPerBlock);
for (int i = 0; i < 3; ++i)
printf("\tMaximum dimension %d of block: %d\n", i, devProp.maxThreadsDim[i]);
for (int i = 0; i < 3; ++i)
printf("\tMaximum dimension %d of grid: %d\n", i, devProp.maxGridSize[i]);
printf("\tAvailable constant memory: %u\n", devProp.totalConstMem);
printf("\tMajor revision number: %d\n", devProp.major);
printf("\tMinor revision number: %d\n", devProp.minor);
printf("\tNumber of multiprocessors: %d\n", devProp.multiProcessorCount);
printf("\tClock rate: %d\n", devProp.clockRate);
}
return 0;
} | .file "tmpxft_000ad6e1_00000000-6_q2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Device Queries:\n"
.LC1:
.string "There are %d CUDA devices.\n"
.LC2:
.string "\nCUDA Device #%d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "\tDevice Identification: %s\n"
.align 8
.LC4:
.string "\tGlobal memory: %u\n"
.align 8
.LC5:
.string "\tShared memory per block: %u\n"
.align 8
.LC6:
.string "\tNumber of registers per block: %d\n"
.align 8
.LC7:
.string "\tNumber of thread in warp: %d\n"
.align 8
.LC8:
.string "\tMaximum threads per block: %d\n"
.align 8
.LC9:
.string "\tMaximum dimension %d of block: %d\n"
.align 8
.LC10:
.string "\tMaximum dimension %d of grid: %d\n"
.align 8
.LC11:
.string "\tAvailable constant memory: %u\n"
.align 8
.LC12:
.string "\tMajor revision number: %d\n"
.align 8
.LC13:
.string "\tMinor revision number: %d\n"
.align 8
.LC14:
.string "\tNumber of multiprocessors: %d\n"
.align 8
.LC15:
.string "\tClock rate: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1064, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 12(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 12(%rsp)
jle .L4
movl $0, %r12d
leaq .LC2(%rip), %r14
leaq 16(%rsp), %rbp
leaq .LC3(%rip), %r13
jmp .L7
.L13:
movq 368(%rsp), %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 376(%rsp), %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 380(%rsp), %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 404(%rsp), %edx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 364(%rsp), %edx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r12d
cmpl %r12d, 12(%rsp)
jle .L4
.L7:
movl %r12d, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbp, %rdx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 304(%rsp), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 312(%rsp), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 320(%rsp), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 324(%rsp), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC9(%rip), %r15
.L5:
movl 324(%rbp,%rbx,4), %ecx
movl %ebx, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $3, %rbx
jne .L5
movl $0, %ebx
leaq .LC10(%rip), %r15
.L6:
movl 336(%rbp,%rbx,4), %ecx
movl %ebx, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $3, %rbx
jne .L6
jmp .L13
.L4:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L14
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
Jaitirth Jacob - 13CO125 Vidit Bhargava - 13CO151
*/
#include <stdio.h>
int main()
{
int count;
cudaGetDeviceCount(&count);
printf("Device Queries:\n");
printf("There are %d CUDA devices.\n", count);
for (int i = 0; i < count; ++i)
{
printf("\nCUDA Device #%d\n", i);
cudaDeviceProp devProp;
cudaGetDeviceProperties(&devProp, i);
printf("\tDevice Identification: %s\n", devProp.name);
printf("\tGlobal memory: %u\n", devProp.totalGlobalMem);
printf("\tShared memory per block: %u\n", devProp.sharedMemPerBlock);
printf("\tNumber of registers per block: %d\n", devProp.regsPerBlock);
printf("\tNumber of thread in warp: %d\n", devProp.warpSize);
printf("\tMaximum threads per block: %d\n", devProp.maxThreadsPerBlock);
for (int i = 0; i < 3; ++i)
printf("\tMaximum dimension %d of block: %d\n", i, devProp.maxThreadsDim[i]);
for (int i = 0; i < 3; ++i)
printf("\tMaximum dimension %d of grid: %d\n", i, devProp.maxGridSize[i]);
printf("\tAvailable constant memory: %u\n", devProp.totalConstMem);
printf("\tMajor revision number: %d\n", devProp.major);
printf("\tMinor revision number: %d\n", devProp.minor);
printf("\tNumber of multiprocessors: %d\n", devProp.multiProcessorCount);
printf("\tClock rate: %d\n", devProp.clockRate);
}
return 0;
} | /*
Jaitirth Jacob - 13CO125 Vidit Bhargava - 13CO151
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
int main()
{
int count;
hipGetDeviceCount(&count);
printf("Device Queries:\n");
printf("There are %d CUDA devices.\n", count);
for (int i = 0; i < count; ++i)
{
printf("\nCUDA Device #%d\n", i);
hipDeviceProp_t devProp;
hipGetDeviceProperties(&devProp, i);
printf("\tDevice Identification: %s\n", devProp.name);
printf("\tGlobal memory: %u\n", devProp.totalGlobalMem);
printf("\tShared memory per block: %u\n", devProp.sharedMemPerBlock);
printf("\tNumber of registers per block: %d\n", devProp.regsPerBlock);
printf("\tNumber of thread in warp: %d\n", devProp.warpSize);
printf("\tMaximum threads per block: %d\n", devProp.maxThreadsPerBlock);
for (int i = 0; i < 3; ++i)
printf("\tMaximum dimension %d of block: %d\n", i, devProp.maxThreadsDim[i]);
for (int i = 0; i < 3; ++i)
printf("\tMaximum dimension %d of grid: %d\n", i, devProp.maxGridSize[i]);
printf("\tAvailable constant memory: %u\n", devProp.totalConstMem);
printf("\tMajor revision number: %d\n", devProp.major);
printf("\tMinor revision number: %d\n", devProp.minor);
printf("\tNumber of multiprocessors: %d\n", devProp.multiProcessorCount);
printf("\tClock rate: %d\n", devProp.clockRate);
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
Jaitirth Jacob - 13CO125 Vidit Bhargava - 13CO151
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
int main()
{
int count;
hipGetDeviceCount(&count);
printf("Device Queries:\n");
printf("There are %d CUDA devices.\n", count);
for (int i = 0; i < count; ++i)
{
printf("\nCUDA Device #%d\n", i);
hipDeviceProp_t devProp;
hipGetDeviceProperties(&devProp, i);
printf("\tDevice Identification: %s\n", devProp.name);
printf("\tGlobal memory: %u\n", devProp.totalGlobalMem);
printf("\tShared memory per block: %u\n", devProp.sharedMemPerBlock);
printf("\tNumber of registers per block: %d\n", devProp.regsPerBlock);
printf("\tNumber of thread in warp: %d\n", devProp.warpSize);
printf("\tMaximum threads per block: %d\n", devProp.maxThreadsPerBlock);
for (int i = 0; i < 3; ++i)
printf("\tMaximum dimension %d of block: %d\n", i, devProp.maxThreadsDim[i]);
for (int i = 0; i < 3; ++i)
printf("\tMaximum dimension %d of grid: %d\n", i, devProp.maxGridSize[i]);
printf("\tAvailable constant memory: %u\n", devProp.totalConstMem);
printf("\tMajor revision number: %d\n", devProp.major);
printf("\tMinor revision number: %d\n", devProp.minor);
printf("\tNumber of multiprocessors: %d\n", devProp.multiProcessorCount);
printf("\tClock rate: %d\n", devProp.clockRate);
}
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
Jaitirth Jacob - 13CO125 Vidit Bhargava - 13CO151
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
int main()
{
int count;
hipGetDeviceCount(&count);
printf("Device Queries:\n");
printf("There are %d CUDA devices.\n", count);
for (int i = 0; i < count; ++i)
{
printf("\nCUDA Device #%d\n", i);
hipDeviceProp_t devProp;
hipGetDeviceProperties(&devProp, i);
printf("\tDevice Identification: %s\n", devProp.name);
printf("\tGlobal memory: %u\n", devProp.totalGlobalMem);
printf("\tShared memory per block: %u\n", devProp.sharedMemPerBlock);
printf("\tNumber of registers per block: %d\n", devProp.regsPerBlock);
printf("\tNumber of thread in warp: %d\n", devProp.warpSize);
printf("\tMaximum threads per block: %d\n", devProp.maxThreadsPerBlock);
for (int i = 0; i < 3; ++i)
printf("\tMaximum dimension %d of block: %d\n", i, devProp.maxThreadsDim[i]);
for (int i = 0; i < 3; ++i)
printf("\tMaximum dimension %d of grid: %d\n", i, devProp.maxGridSize[i]);
printf("\tAvailable constant memory: %u\n", devProp.totalConstMem);
printf("\tMajor revision number: %d\n", devProp.major);
printf("\tMinor revision number: %d\n", devProp.minor);
printf("\tNumber of multiprocessors: %d\n", devProp.multiProcessorCount);
printf("\tClock rate: %d\n", devProp.clockRate);
}
return 0;
} | .text
.file "q2.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
movl $.Lstr, %edi
callq puts@PLT
movl 12(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
cmpl $0, 12(%rsp)
jle .LBB0_7
# %bb.1: # %.lr.ph
leaq 16(%rsp), %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_2: # =>This Loop Header: Depth=1
# Child Loop BB0_3 Depth 2
# Child Loop BB0_5 Depth 2
movl $.L.str.2, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.3, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movq 304(%rsp), %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movq 312(%rsp), %rsi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl 320(%rsp), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movl 324(%rsp), %esi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl 336(%rsp), %esi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_3: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movl 340(%rsp,%r14,4), %edx
movl $.L.str.9, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
incq %r14
cmpq $3, %r14
jne .LBB0_3
# %bb.4: # %.preheader.preheader
# in Loop: Header=BB0_2 Depth=1
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_5: # %.preheader
# Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movl 352(%rsp,%r14,4), %edx
movl $.L.str.10, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
incq %r14
cmpq $3, %r14
jne .LBB0_5
# %bb.6: # in Loop: Header=BB0_2 Depth=1
movq 368(%rsp), %rsi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movl 376(%rsp), %esi
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
movl 380(%rsp), %esi
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
movl 404(%rsp), %esi
movl $.L.str.14, %edi
xorl %eax, %eax
callq printf
movl 364(%rsp), %esi
movl $.L.str.15, %edi
xorl %eax, %eax
callq printf
incl %ebp
cmpl 12(%rsp), %ebp
jl .LBB0_2
.LBB0_7: # %._crit_edge
xorl %eax, %eax
addq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "There are %d CUDA devices.\n"
.size .L.str.1, 28
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\nCUDA Device #%d\n"
.size .L.str.2, 18
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\tDevice Identification: %s\n"
.size .L.str.3, 37
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\tGlobal memory: %u\n"
.size .L.str.4, 37
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\tShared memory per block: %u\n"
.size .L.str.5, 37
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\tNumber of registers per block: %d\n"
.size .L.str.6, 37
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\tNumber of thread in warp: %d\n"
.size .L.str.7, 37
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "\tMaximum threads per block: %d\n"
.size .L.str.8, 37
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "\tMaximum dimension %d of block: %d\n"
.size .L.str.9, 37
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "\tMaximum dimension %d of grid: %d\n"
.size .L.str.10, 37
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "\tAvailable constant memory: %u\n"
.size .L.str.11, 37
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "\tMajor revision number: %d\n"
.size .L.str.12, 37
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "\tMinor revision number: %d\n"
.size .L.str.13, 37
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "\tNumber of multiprocessors: %d\n"
.size .L.str.14, 37
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "\tClock rate: %d\n"
.size .L.str.15, 37
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Device Queries:"
.size .Lstr, 16
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ad6e1_00000000-6_q2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Device Queries:\n"
.LC1:
.string "There are %d CUDA devices.\n"
.LC2:
.string "\nCUDA Device #%d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "\tDevice Identification: %s\n"
.align 8
.LC4:
.string "\tGlobal memory: %u\n"
.align 8
.LC5:
.string "\tShared memory per block: %u\n"
.align 8
.LC6:
.string "\tNumber of registers per block: %d\n"
.align 8
.LC7:
.string "\tNumber of thread in warp: %d\n"
.align 8
.LC8:
.string "\tMaximum threads per block: %d\n"
.align 8
.LC9:
.string "\tMaximum dimension %d of block: %d\n"
.align 8
.LC10:
.string "\tMaximum dimension %d of grid: %d\n"
.align 8
.LC11:
.string "\tAvailable constant memory: %u\n"
.align 8
.LC12:
.string "\tMajor revision number: %d\n"
.align 8
.LC13:
.string "\tMinor revision number: %d\n"
.align 8
.LC14:
.string "\tNumber of multiprocessors: %d\n"
.align 8
.LC15:
.string "\tClock rate: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1064, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 12(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 12(%rsp)
jle .L4
movl $0, %r12d
leaq .LC2(%rip), %r14
leaq 16(%rsp), %rbp
leaq .LC3(%rip), %r13
jmp .L7
.L13:
movq 368(%rsp), %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 376(%rsp), %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 380(%rsp), %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 404(%rsp), %edx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 364(%rsp), %edx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r12d
cmpl %r12d, 12(%rsp)
jle .L4
.L7:
movl %r12d, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbp, %rdx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 304(%rsp), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 312(%rsp), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 320(%rsp), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 324(%rsp), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC9(%rip), %r15
.L5:
movl 324(%rbp,%rbx,4), %ecx
movl %ebx, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $3, %rbx
jne .L5
movl $0, %ebx
leaq .LC10(%rip), %r15
.L6:
movl 336(%rbp,%rbx,4), %ecx
movl %ebx, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $3, %rbx
jne .L6
jmp .L13
.L4:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L14
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "q2.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
movl $.Lstr, %edi
callq puts@PLT
movl 12(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
cmpl $0, 12(%rsp)
jle .LBB0_7
# %bb.1: # %.lr.ph
leaq 16(%rsp), %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_2: # =>This Loop Header: Depth=1
# Child Loop BB0_3 Depth 2
# Child Loop BB0_5 Depth 2
movl $.L.str.2, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.3, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movq 304(%rsp), %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movq 312(%rsp), %rsi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl 320(%rsp), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movl 324(%rsp), %esi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl 336(%rsp), %esi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_3: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movl 340(%rsp,%r14,4), %edx
movl $.L.str.9, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
incq %r14
cmpq $3, %r14
jne .LBB0_3
# %bb.4: # %.preheader.preheader
# in Loop: Header=BB0_2 Depth=1
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_5: # %.preheader
# Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movl 352(%rsp,%r14,4), %edx
movl $.L.str.10, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
incq %r14
cmpq $3, %r14
jne .LBB0_5
# %bb.6: # in Loop: Header=BB0_2 Depth=1
movq 368(%rsp), %rsi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movl 376(%rsp), %esi
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
movl 380(%rsp), %esi
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
movl 404(%rsp), %esi
movl $.L.str.14, %edi
xorl %eax, %eax
callq printf
movl 364(%rsp), %esi
movl $.L.str.15, %edi
xorl %eax, %eax
callq printf
incl %ebp
cmpl 12(%rsp), %ebp
jl .LBB0_2
.LBB0_7: # %._crit_edge
xorl %eax, %eax
addq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "There are %d CUDA devices.\n"
.size .L.str.1, 28
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\nCUDA Device #%d\n"
.size .L.str.2, 18
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\tDevice Identification: %s\n"
.size .L.str.3, 37
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\tGlobal memory: %u\n"
.size .L.str.4, 37
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\tShared memory per block: %u\n"
.size .L.str.5, 37
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\tNumber of registers per block: %d\n"
.size .L.str.6, 37
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\tNumber of thread in warp: %d\n"
.size .L.str.7, 37
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "\tMaximum threads per block: %d\n"
.size .L.str.8, 37
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "\tMaximum dimension %d of block: %d\n"
.size .L.str.9, 37
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "\tMaximum dimension %d of grid: %d\n"
.size .L.str.10, 37
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "\tAvailable constant memory: %u\n"
.size .L.str.11, 37
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "\tMajor revision number: %d\n"
.size .L.str.12, 37
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "\tMinor revision number: %d\n"
.size .L.str.13, 37
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "\tNumber of multiprocessors: %d\n"
.size .L.str.14, 37
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "\tClock rate: %d\n"
.size .L.str.15, 37
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Device Queries:"
.size .Lstr, 16
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* Copyright 1993-2010 NVIDIA Corporation. All rights reserved.
*
* NVIDIA Corporation and its licensors retain all intellectual property and
* proprietary rights in and to this software and related documentation.
* Any use, reproduction, disclosure, or distribution of this software
* and related documentation without an express license agreement from
* NVIDIA Corporation is strictly prohibited.
*
* Please refer to the applicable NVIDIA end user license agreement (EULA)
* associated with this source code for terms and conditions that govern
* your use of this NVIDIA software.
*
*/
#include "stdio.h"
#define N 10
__global__
void add11( int *a, int *b, int *c ) {
int i = 0;
while (i < N) {
c[i] = a[i] + b[i];
i += 1;
}
}
__global__
void addn1( int *a, int *b, int *c ) {
int i = blockIdx.x;
c[i] = a[i] + b[i];
}
__global__
void add1n( int *a, int *b, int *c ) {
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
__global__
void add( int *a, int *b, int *c ) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < N; i += stride)
c[i] = a[i] + b[i];
}
int main( void ) {
int *a, *b, *c;
cudaMallocManaged(&a, N*sizeof(int));
cudaMallocManaged(&b, N*sizeof(int));
cudaMallocManaged(&c, N*sizeof(int));
for (int i=0; i<N; i++) {
a[i] = -i;
b[i] = i * i;
}
add11<<<1, 1>>>(a, b, c);
cudaDeviceSynchronize();
printf("1, 1\n");
for (int i=0; i<N; i++) {
printf( "%d + %d = %d\n", a[i], b[i], c[i] );
}
add1n<<<1, N>>>(a, b, c);
cudaDeviceSynchronize();
printf("1, N\n");
for (int i=0; i<N; i++) {
printf( "%d + %d = %d\n", a[i], b[i], c[i] );
}
addn1<<<N, 1>>>(a, b, c);
cudaDeviceSynchronize();
printf("N, 1\n");
for (int i=0; i<N; i++) {
printf( "%d + %d = %d\n", a[i], b[i], c[i] );
}
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
add<<<numBlocks, blockSize>>>(a, b, c);
cudaDeviceSynchronize();
printf("<<<...>>>\n");
for (int i=0; i<N; i++) {
printf( "%d + %d = %d\n", a[i], b[i], c[i] );
}
cudaFree(a);
cudaFree(b);
cudaFree(c);
return 0;
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GT.AND P0, PT, R3, 0x9, PT ; /* 0x000000090300780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x310 ; /* 0x0000028000007945 */
/* 0x000fe60003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R2, R0 ; /* 0x0000000000027306 */
/* 0x000e220000209000 */
/*00b0*/ IADD3 R7, RZ, -R0, RZ ; /* 0x80000000ff077210 */
/* 0x000fe40007ffe0ff */
/*00c0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fca0003f45070 */
/*00d0*/ MUFU.RCP R2, R2 ; /* 0x0000000200027308 */
/* 0x001e240000001000 */
/*00e0*/ IADD3 R4, R2, 0xffffffe, RZ ; /* 0x0ffffffe02047810 */
/* 0x001fcc0007ffe0ff */
/*00f0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0100*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0110*/ IMAD R7, R7, R5, RZ ; /* 0x0000000507077224 */
/* 0x002fc800078e02ff */
/*0120*/ IMAD.HI.U32 R6, R5, R7, R4 ; /* 0x0000000705067227 */
/* 0x000fe200078e0004 */
/*0130*/ IADD3 R5, -R3, 0x9, RZ ; /* 0x0000000903057810 */
/* 0x000fca0007ffe1ff */
/*0140*/ IMAD.HI.U32 R6, R6, R5, RZ ; /* 0x0000000506067227 */
/* 0x000fca00078e00ff */
/*0150*/ IADD3 R2, -R6, RZ, RZ ; /* 0x000000ff06027210 */
/* 0x000fca0007ffe1ff */
/*0160*/ IMAD R5, R0, R2, R5 ; /* 0x0000000200057224 */
/* 0x000fca00078e0205 */
/*0170*/ ISETP.GE.U32.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f06070 */
/*0180*/ @P0 IADD3 R5, -R0, R5, RZ ; /* 0x0000000500050210 */
/* 0x000fe40007ffe1ff */
/*0190*/ @P0 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106060810 */
/* 0x000fe40007ffe0ff */
/*01a0*/ ISETP.GE.U32.AND P1, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f26070 */
/*01b0*/ @P1 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106061810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ @!P2 LOP3.LUT R6, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff06a212 */
/* 0x000fc800078e33ff */
/*01d0*/ IADD3 R2, R6.reuse, 0x1, RZ ; /* 0x0000000106027810 */
/* 0x040fe40007ffe0ff */
/*01e0*/ ISETP.GE.U32.AND P1, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe40003f26070 */
/*01f0*/ LOP3.LUT P0, R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fda000780c0ff */
/*0200*/ @!P0 BRA 0x300 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0210*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fc800078e00ff */
/*0220*/ IMAD.WIDE R4, R3, R8, c[0x0][0x170] ; /* 0x00005c0003047625 */
/* 0x000fc800078e0208 */
/*0230*/ IMAD.WIDE R6, R3, R8, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fc800078e0208 */
/*0240*/ IMAD.WIDE R8, R3, R8, c[0x0][0x160] ; /* 0x0000580003087625 */
/* 0x000fc800078e0208 */
/*0250*/ LDG.E R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x0000a8000c1e1900 */
/*0260*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0002a2000c1e1900 */
/*0270*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*0280*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0290*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*02a0*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x001fc800078e0206 */
/*02b0*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x002fe200078e0208 */
/*02c0*/ IADD3 R11, R10, R11, RZ ; /* 0x0000000b0a0b7210 */
/* 0x004fca0007ffe0ff */
/*02d0*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0001e4000c101904 */
/*02e0*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x001fe200078e0204 */
/*02f0*/ @P0 BRA 0x250 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0300*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0310*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0320*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fd400000001ff */
/*0330*/ IMAD.WIDE R6, R3, R8, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fc800078e0208 */
/*0340*/ IMAD.WIDE R4, R3.reuse, R8.reuse, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x0c0fe200078e0208 */
/*0350*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea8000c1e1900 */
/*0360*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x001ea2000c1e1900 */
/*0370*/ IMAD.WIDE R8, R3, R8, c[0x0][0x170] ; /* 0x00005c0003087625 */
/* 0x000fc800078e0208 */
/*0380*/ IMAD.WIDE R12, R0, 0x4, R6 ; /* 0x00000004000c7825 */
/* 0x000fc800078e0206 */
/*0390*/ IMAD.IADD R19, R2, 0x1, R11 ; /* 0x0000000102137824 */
/* 0x004fe400078e020b */
/*03a0*/ IMAD.WIDE R10, R0, 0x4, R4 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0204 */
/*03b0*/ STG.E [R8.64], R19 ; /* 0x0000001308007986 */
/* 0x0001e8000c101904 */
/*03c0*/ LDG.E R2, [R12.64] ; /* 0x000000040c027981 */
/* 0x000ea8000c1e1900 */
/*03d0*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x000ea2000c1e1900 */
/*03e0*/ IMAD.WIDE R14, R0, 0x4, R8 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0208 */
/*03f0*/ IMAD.WIDE R6, R0, 0x4, R12 ; /* 0x0000000400067825 */
/* 0x000fc800078e020c */
/*0400*/ IMAD.WIDE R4, R0, 0x4, R10 ; /* 0x0000000400047825 */
/* 0x000fe200078e020a */
/*0410*/ IADD3 R21, R2, R17, RZ ; /* 0x0000001102157210 */
/* 0x004fca0007ffe0ff */
/*0420*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0003e8000c101904 */
/*0430*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea8000c1e1900 */
/*0440*/ LDG.E R23, [R4.64] ; /* 0x0000000404177981 */
/* 0x000ea2000c1e1900 */
/*0450*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc800078e020e */
/*0460*/ IMAD.WIDE R12, R0, 0x4, R6 ; /* 0x00000004000c7825 */
/* 0x000fc800078e0206 */
/*0470*/ IMAD.WIDE R8, R0, 0x4, R4 ; /* 0x0000000400087825 */
/* 0x001fe200078e0204 */
/*0480*/ IADD3 R23, R2, R23, RZ ; /* 0x0000001702177210 */
/* 0x004fca0007ffe0ff */
/*0490*/ STG.E [R16.64], R23 ; /* 0x0000001710007986 */
/* 0x0001e8000c101904 */
/*04a0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000e68000c1e1900 */
/*04b0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000e62000c1e1900 */
/*04c0*/ IMAD.WIDE R10, R0.reuse, 0x4, R16 ; /* 0x00000004000a7825 */
/* 0x040fe200078e0210 */
/*04d0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*04e0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*04f0*/ ISETP.GE.AND P0, PT, R3, 0xa, PT ; /* 0x0000000a0300780c */
/* 0x000fe40003f06270 */
/*0500*/ IADD3 R15, R12, R9, RZ ; /* 0x000000090c0f7210 */
/* 0x002fca0007ffe0ff */
/*0510*/ STG.E [R10.64], R15 ; /* 0x0000000f0a007986 */
/* 0x0001ec000c101904 */
/*0520*/ @!P0 BRA 0x320 ; /* 0xfffffdf000008947 */
/* 0x000fea000383ffff */
/*0530*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0540*/ BRA 0x540; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z5add1nPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z5addn1PiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z5add11PiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R6, c[0x0][0x160] ; /* 0x0000580000067a02 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff077624 */
/* 0x000fe200078e00ff */
/*0030*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0060*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea2000c1e1900 */
/*0080*/ MOV R2, c[0x0][0x170] ; /* 0x00005c0000027a02 */
/* 0x000fe20000000f00 */
/*0090*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fe200078e00ff */
/*00a0*/ IADD3 R9, R0, R9, RZ ; /* 0x0000000900097210 */
/* 0x004fca0007ffe0ff */
/*00b0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*00c0*/ LDG.E R0, [R6.64+0x4] ; /* 0x0000040406007981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R11, [R4.64+0x4] ; /* 0x00000404040b7981 */
/* 0x000ea4000c1e1900 */
/*00e0*/ IMAD.IADD R11, R0, 0x1, R11 ; /* 0x00000001000b7824 */
/* 0x004fca00078e020b */
/*00f0*/ STG.E [R2.64+0x4], R11 ; /* 0x0000040b02007986 */
/* 0x0003e8000c101904 */
/*0100*/ LDG.E R0, [R6.64+0x8] ; /* 0x0000080406007981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R13, [R4.64+0x8] ; /* 0x00000804040d7981 */
/* 0x000ea4000c1e1900 */
/*0120*/ IADD3 R13, R0, R13, RZ ; /* 0x0000000d000d7210 */
/* 0x004fca0007ffe0ff */
/*0130*/ STG.E [R2.64+0x8], R13 ; /* 0x0000080d02007986 */
/* 0x0005e8000c101904 */
/*0140*/ LDG.E R0, [R6.64+0xc] ; /* 0x00000c0406007981 */
/* 0x000ee8000c1e1900 */
/*0150*/ LDG.E R15, [R4.64+0xc] ; /* 0x00000c04040f7981 */
/* 0x000ee4000c1e1900 */
/*0160*/ IMAD.IADD R15, R0, 0x1, R15 ; /* 0x00000001000f7824 */
/* 0x008fca00078e020f */
/*0170*/ STG.E [R2.64+0xc], R15 ; /* 0x00000c0f02007986 */
/* 0x0007e8000c101904 */
/*0180*/ LDG.E R0, [R6.64+0x10] ; /* 0x0000100406007981 */
/* 0x000f28000c1e1900 */
/*0190*/ LDG.E R9, [R4.64+0x10] ; /* 0x0000100404097981 */
/* 0x001f24000c1e1900 */
/*01a0*/ IADD3 R9, R0, R9, RZ ; /* 0x0000000900097210 */
/* 0x010fca0007ffe0ff */
/*01b0*/ STG.E [R2.64+0x10], R9 ; /* 0x0000100902007986 */
/* 0x0001e8000c101904 */
/*01c0*/ LDG.E R0, [R6.64+0x14] ; /* 0x0000140406007981 */
/* 0x000f28000c1e1900 */
/*01d0*/ LDG.E R11, [R4.64+0x14] ; /* 0x00001404040b7981 */
/* 0x002f24000c1e1900 */
/*01e0*/ IMAD.IADD R11, R0, 0x1, R11 ; /* 0x00000001000b7824 */
/* 0x010fca00078e020b */
/*01f0*/ STG.E [R2.64+0x14], R11 ; /* 0x0000140b02007986 */
/* 0x0003e8000c101904 */
/*0200*/ LDG.E R0, [R6.64+0x18] ; /* 0x0000180406007981 */
/* 0x000f28000c1e1900 */
/*0210*/ LDG.E R13, [R4.64+0x18] ; /* 0x00001804040d7981 */
/* 0x004f24000c1e1900 */
/*0220*/ IADD3 R13, R0, R13, RZ ; /* 0x0000000d000d7210 */
/* 0x010fca0007ffe0ff */
/*0230*/ STG.E [R2.64+0x18], R13 ; /* 0x0000180d02007986 */
/* 0x000fe8000c101904 */
/*0240*/ LDG.E R0, [R6.64+0x1c] ; /* 0x00001c0406007981 */
/* 0x000ea8000c1e1900 */
/*0250*/ LDG.E R15, [R4.64+0x1c] ; /* 0x00001c04040f7981 */
/* 0x008ea4000c1e1900 */
/*0260*/ IMAD.IADD R15, R0, 0x1, R15 ; /* 0x00000001000f7824 */
/* 0x004fca00078e020f */
/*0270*/ STG.E [R2.64+0x1c], R15 ; /* 0x00001c0f02007986 */
/* 0x000fe8000c101904 */
/*0280*/ LDG.E R0, [R6.64+0x20] ; /* 0x0000200406007981 */
/* 0x000ea8000c1e1900 */
/*0290*/ LDG.E R9, [R4.64+0x20] ; /* 0x0000200404097981 */
/* 0x001ea4000c1e1900 */
/*02a0*/ IADD3 R9, R0, R9, RZ ; /* 0x0000000900097210 */
/* 0x004fca0007ffe0ff */
/*02b0*/ STG.E [R2.64+0x20], R9 ; /* 0x0000200902007986 */
/* 0x000fe8000c101904 */
/*02c0*/ LDG.E R0, [R6.64+0x24] ; /* 0x0000240406007981 */
/* 0x000ea8000c1e1900 */
/*02d0*/ LDG.E R11, [R4.64+0x24] ; /* 0x00002404040b7981 */
/* 0x002ea4000c1e1900 */
/*02e0*/ IMAD.IADD R11, R0, 0x1, R11 ; /* 0x00000001000b7824 */
/* 0x004fca00078e020b */
/*02f0*/ STG.E [R2.64+0x24], R11 ; /* 0x0000240b02007986 */
/* 0x000fe2000c101904 */
/*0300*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0310*/ BRA 0x310; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* Copyright 1993-2010 NVIDIA Corporation. All rights reserved.
*
* NVIDIA Corporation and its licensors retain all intellectual property and
* proprietary rights in and to this software and related documentation.
* Any use, reproduction, disclosure, or distribution of this software
* and related documentation without an express license agreement from
* NVIDIA Corporation is strictly prohibited.
*
* Please refer to the applicable NVIDIA end user license agreement (EULA)
* associated with this source code for terms and conditions that govern
* your use of this NVIDIA software.
*
*/
#include "stdio.h"
#define N 10
__global__
void add11( int *a, int *b, int *c ) {
int i = 0;
while (i < N) {
c[i] = a[i] + b[i];
i += 1;
}
}
__global__
void addn1( int *a, int *b, int *c ) {
int i = blockIdx.x;
c[i] = a[i] + b[i];
}
__global__
void add1n( int *a, int *b, int *c ) {
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
__global__
void add( int *a, int *b, int *c ) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < N; i += stride)
c[i] = a[i] + b[i];
}
int main( void ) {
int *a, *b, *c;
cudaMallocManaged(&a, N*sizeof(int));
cudaMallocManaged(&b, N*sizeof(int));
cudaMallocManaged(&c, N*sizeof(int));
for (int i=0; i<N; i++) {
a[i] = -i;
b[i] = i * i;
}
add11<<<1, 1>>>(a, b, c);
cudaDeviceSynchronize();
printf("1, 1\n");
for (int i=0; i<N; i++) {
printf( "%d + %d = %d\n", a[i], b[i], c[i] );
}
add1n<<<1, N>>>(a, b, c);
cudaDeviceSynchronize();
printf("1, N\n");
for (int i=0; i<N; i++) {
printf( "%d + %d = %d\n", a[i], b[i], c[i] );
}
addn1<<<N, 1>>>(a, b, c);
cudaDeviceSynchronize();
printf("N, 1\n");
for (int i=0; i<N; i++) {
printf( "%d + %d = %d\n", a[i], b[i], c[i] );
}
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
add<<<numBlocks, blockSize>>>(a, b, c);
cudaDeviceSynchronize();
printf("<<<...>>>\n");
for (int i=0; i<N; i++) {
printf( "%d + %d = %d\n", a[i], b[i], c[i] );
}
cudaFree(a);
cudaFree(b);
cudaFree(c);
return 0;
} | .file "tmpxft_00047e5e_00000000-6_add_loop_cpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z5add11PiS_S_PiS_S_
.type _Z28__device_stub__Z5add11PiS_S_PiS_S_, @function
_Z28__device_stub__Z5add11PiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5add11PiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z5add11PiS_S_PiS_S_, .-_Z28__device_stub__Z5add11PiS_S_PiS_S_
.globl _Z5add11PiS_S_
.type _Z5add11PiS_S_, @function
_Z5add11PiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z5add11PiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5add11PiS_S_, .-_Z5add11PiS_S_
.globl _Z28__device_stub__Z5addn1PiS_S_PiS_S_
.type _Z28__device_stub__Z5addn1PiS_S_PiS_S_, @function
_Z28__device_stub__Z5addn1PiS_S_PiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5addn1PiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z28__device_stub__Z5addn1PiS_S_PiS_S_, .-_Z28__device_stub__Z5addn1PiS_S_PiS_S_
.globl _Z5addn1PiS_S_
.type _Z5addn1PiS_S_, @function
_Z5addn1PiS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z5addn1PiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z5addn1PiS_S_, .-_Z5addn1PiS_S_
.globl _Z28__device_stub__Z5add1nPiS_S_PiS_S_
.type _Z28__device_stub__Z5add1nPiS_S_PiS_S_, @function
_Z28__device_stub__Z5add1nPiS_S_PiS_S_:
.LFB2086:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5add1nPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z28__device_stub__Z5add1nPiS_S_PiS_S_, .-_Z28__device_stub__Z5add1nPiS_S_PiS_S_
.globl _Z5add1nPiS_S_
.type _Z5add1nPiS_S_, @function
_Z5add1nPiS_S_:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z5add1nPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z5add1nPiS_S_, .-_Z5add1nPiS_S_
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2088:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "1, 1\n"
.LC1:
.string "%d + %d = %d\n"
.LC2:
.string "1, N\n"
.LC3:
.string "N, 1\n"
.LC4:
.string "<<<...>>>\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $40, %esi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $40, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $40, %esi
call cudaMallocManaged@PLT
movl $0, %eax
.L36:
movl %eax, %ecx
negl %ecx
movq 8(%rsp), %rdx
movl %ecx, (%rdx,%rax,4)
movl %eax, %ecx
imull %eax, %ecx
movq 16(%rsp), %rdx
movl %ecx, (%rdx,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L36
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L37:
call cudaDeviceSynchronize@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC1(%rip), %rbp
.L38:
movq 16(%rsp), %rax
movl (%rax,%rbx), %ecx
movq 8(%rsp), %rax
movl (%rax,%rbx), %edx
movq 24(%rsp), %rax
movl (%rax,%rbx), %r8d
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $40, %rbx
jne .L38
movl $10, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L53
.L39:
call cudaDeviceSynchronize@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC1(%rip), %rbp
.L40:
movq 16(%rsp), %rax
movl (%rax,%rbx), %ecx
movq 8(%rsp), %rax
movl (%rax,%rbx), %edx
movq 24(%rsp), %rax
movl (%rax,%rbx), %r8d
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $40, %rbx
jne .L40
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $10, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L54
.L41:
call cudaDeviceSynchronize@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC1(%rip), %rbp
.L42:
movq 16(%rsp), %rax
movl (%rax,%rbx), %ecx
movq 8(%rsp), %rax
movl (%rax,%rbx), %edx
movq 24(%rsp), %rax
movl (%rax,%rbx), %r8d
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $40, %rbx
jne .L42
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L55
.L43:
call cudaDeviceSynchronize@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC1(%rip), %rbp
.L44:
movq 16(%rsp), %rax
movl (%rax,%rbx), %ecx
movq 8(%rsp), %rax
movl (%rax,%rbx), %edx
movq 24(%rsp), %rax
movl (%rax,%rbx), %r8d
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $40, %rbx
jne .L44
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L56
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z28__device_stub__Z5add11PiS_S_PiS_S_
jmp .L37
.L53:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z28__device_stub__Z5add1nPiS_S_PiS_S_
jmp .L39
.L54:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z28__device_stub__Z5addn1PiS_S_PiS_S_
jmp .L41
.L55:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L43
.L56:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z3addPiS_S_"
.LC6:
.string "_Z5add1nPiS_S_"
.LC7:
.string "_Z5addn1PiS_S_"
.LC8:
.string "_Z5add11PiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z5add1nPiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z5addn1PiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z5add11PiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Copyright 1993-2010 NVIDIA Corporation. All rights reserved.
*
* NVIDIA Corporation and its licensors retain all intellectual property and
* proprietary rights in and to this software and related documentation.
* Any use, reproduction, disclosure, or distribution of this software
* and related documentation without an express license agreement from
* NVIDIA Corporation is strictly prohibited.
*
* Please refer to the applicable NVIDIA end user license agreement (EULA)
* associated with this source code for terms and conditions that govern
* your use of this NVIDIA software.
*
*/
#include "stdio.h"
#define N 10
__global__
void add11( int *a, int *b, int *c ) {
int i = 0;
while (i < N) {
c[i] = a[i] + b[i];
i += 1;
}
}
__global__
void addn1( int *a, int *b, int *c ) {
int i = blockIdx.x;
c[i] = a[i] + b[i];
}
__global__
void add1n( int *a, int *b, int *c ) {
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
__global__
void add( int *a, int *b, int *c ) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < N; i += stride)
c[i] = a[i] + b[i];
}
int main( void ) {
int *a, *b, *c;
cudaMallocManaged(&a, N*sizeof(int));
cudaMallocManaged(&b, N*sizeof(int));
cudaMallocManaged(&c, N*sizeof(int));
for (int i=0; i<N; i++) {
a[i] = -i;
b[i] = i * i;
}
add11<<<1, 1>>>(a, b, c);
cudaDeviceSynchronize();
printf("1, 1\n");
for (int i=0; i<N; i++) {
printf( "%d + %d = %d\n", a[i], b[i], c[i] );
}
add1n<<<1, N>>>(a, b, c);
cudaDeviceSynchronize();
printf("1, N\n");
for (int i=0; i<N; i++) {
printf( "%d + %d = %d\n", a[i], b[i], c[i] );
}
addn1<<<N, 1>>>(a, b, c);
cudaDeviceSynchronize();
printf("N, 1\n");
for (int i=0; i<N; i++) {
printf( "%d + %d = %d\n", a[i], b[i], c[i] );
}
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
add<<<numBlocks, blockSize>>>(a, b, c);
cudaDeviceSynchronize();
printf("<<<...>>>\n");
for (int i=0; i<N; i++) {
printf( "%d + %d = %d\n", a[i], b[i], c[i] );
}
cudaFree(a);
cudaFree(b);
cudaFree(c);
return 0;
} | /*
* Copyright 1993-2010 NVIDIA Corporation. All rights reserved.
*
* NVIDIA Corporation and its licensors retain all intellectual property and
* proprietary rights in and to this software and related documentation.
* Any use, reproduction, disclosure, or distribution of this software
* and related documentation without an express license agreement from
* NVIDIA Corporation is strictly prohibited.
*
* Please refer to the applicable NVIDIA end user license agreement (EULA)
* associated with this source code for terms and conditions that govern
* your use of this NVIDIA software.
*
*/
#include <hip/hip_runtime.h>
#include "stdio.h"
#define N 10
__global__
void add11( int *a, int *b, int *c ) {
int i = 0;
while (i < N) {
c[i] = a[i] + b[i];
i += 1;
}
}
__global__
void addn1( int *a, int *b, int *c ) {
int i = blockIdx.x;
c[i] = a[i] + b[i];
}
__global__
void add1n( int *a, int *b, int *c ) {
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
__global__
void add( int *a, int *b, int *c ) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < N; i += stride)
c[i] = a[i] + b[i];
}
int main( void ) {
int *a, *b, *c;
hipMallocManaged(&a, N*sizeof(int));
hipMallocManaged(&b, N*sizeof(int));
hipMallocManaged(&c, N*sizeof(int));
for (int i=0; i<N; i++) {
a[i] = -i;
b[i] = i * i;
}
add11<<<1, 1>>>(a, b, c);
hipDeviceSynchronize();
printf("1, 1\n");
for (int i=0; i<N; i++) {
printf( "%d + %d = %d\n", a[i], b[i], c[i] );
}
add1n<<<1, N>>>(a, b, c);
hipDeviceSynchronize();
printf("1, N\n");
for (int i=0; i<N; i++) {
printf( "%d + %d = %d\n", a[i], b[i], c[i] );
}
addn1<<<N, 1>>>(a, b, c);
hipDeviceSynchronize();
printf("N, 1\n");
for (int i=0; i<N; i++) {
printf( "%d + %d = %d\n", a[i], b[i], c[i] );
}
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
add<<<numBlocks, blockSize>>>(a, b, c);
hipDeviceSynchronize();
printf("<<<...>>>\n");
for (int i=0; i<N; i++) {
printf( "%d + %d = %d\n", a[i], b[i], c[i] );
}
hipFree(a);
hipFree(b);
hipFree(c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* Copyright 1993-2010 NVIDIA Corporation. All rights reserved.
*
* NVIDIA Corporation and its licensors retain all intellectual property and
* proprietary rights in and to this software and related documentation.
* Any use, reproduction, disclosure, or distribution of this software
* and related documentation without an express license agreement from
* NVIDIA Corporation is strictly prohibited.
*
* Please refer to the applicable NVIDIA end user license agreement (EULA)
* associated with this source code for terms and conditions that govern
* your use of this NVIDIA software.
*
*/
#include <hip/hip_runtime.h>
#include "stdio.h"
#define N 10
__global__
void add11( int *a, int *b, int *c ) {
int i = 0;
while (i < N) {
c[i] = a[i] + b[i];
i += 1;
}
}
__global__
void addn1( int *a, int *b, int *c ) {
int i = blockIdx.x;
c[i] = a[i] + b[i];
}
__global__
void add1n( int *a, int *b, int *c ) {
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
__global__
void add( int *a, int *b, int *c ) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < N; i += stride)
c[i] = a[i] + b[i];
}
int main( void ) {
int *a, *b, *c;
hipMallocManaged(&a, N*sizeof(int));
hipMallocManaged(&b, N*sizeof(int));
hipMallocManaged(&c, N*sizeof(int));
for (int i=0; i<N; i++) {
a[i] = -i;
b[i] = i * i;
}
add11<<<1, 1>>>(a, b, c);
hipDeviceSynchronize();
printf("1, 1\n");
for (int i=0; i<N; i++) {
printf( "%d + %d = %d\n", a[i], b[i], c[i] );
}
add1n<<<1, N>>>(a, b, c);
hipDeviceSynchronize();
printf("1, N\n");
for (int i=0; i<N; i++) {
printf( "%d + %d = %d\n", a[i], b[i], c[i] );
}
addn1<<<N, 1>>>(a, b, c);
hipDeviceSynchronize();
printf("N, 1\n");
for (int i=0; i<N; i++) {
printf( "%d + %d = %d\n", a[i], b[i], c[i] );
}
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
add<<<numBlocks, blockSize>>>(a, b, c);
hipDeviceSynchronize();
printf("<<<...>>>\n");
for (int i=0; i<N; i++) {
printf( "%d + %d = %d\n", a[i], b[i], c[i] );
}
hipFree(a);
hipFree(b);
hipFree(c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5add11PiS_S_
.globl _Z5add11PiS_S_
.p2align 8
.type _Z5add11PiS_S_,@function
_Z5add11PiS_S_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v0, 0
s_mov_b64 s[2:3], 0
.p2align 6
.LBB0_1:
s_waitcnt lgkmcnt(0)
s_add_u32 s8, s4, s2
s_addc_u32 s9, s5, s3
s_add_u32 s10, s6, s2
s_addc_u32 s11, s7, s3
s_clause 0x1
global_load_b32 v1, v0, s[8:9]
global_load_b32 v2, v0, s[10:11]
s_add_u32 s8, s0, s2
s_addc_u32 s9, s1, s3
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_lg_u32 s2, 40
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[8:9]
s_cbranch_scc1 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5add11PiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 12
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5add11PiS_S_, .Lfunc_end0-_Z5add11PiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z5addn1PiS_S_
.globl _Z5addn1PiS_S_
.p2align 8
.type _Z5addn1PiS_S_,@function
_Z5addn1PiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5addn1PiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z5addn1PiS_S_, .Lfunc_end1-_Z5addn1PiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z5add1nPiS_S_
.globl _Z5add1nPiS_S_
.p2align 8
.type _Z5add1nPiS_S_,@function
_Z5add1nPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5add1nPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z5add1nPiS_S_, .Lfunc_end2-_Z5add1nPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_load_b32 s4, s[0:1], 0x24
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 10, v1
s_cbranch_execz .LBB3_3
s_load_b32 s9, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s9, s8
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[8:9], 2
.p2align 6
.LBB3_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_add_nc_u32_e32 v1, s8, v1
global_load_b32 v0, v[4:5], off
global_load_b32 v6, v[6:7], off
v_add_co_u32 v4, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s10
v_cmp_lt_i32_e64 s0, 9, v1
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2)
s_or_b32 s1, s0, s1
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v6, v0
global_store_b32 v[4:5], v0, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB3_2
.LBB3_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z3addPiS_S_, .Lfunc_end3-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5add11PiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z5add11PiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5addn1PiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z5addn1PiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5add1nPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z5add1nPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* Copyright 1993-2010 NVIDIA Corporation. All rights reserved.
*
* NVIDIA Corporation and its licensors retain all intellectual property and
* proprietary rights in and to this software and related documentation.
* Any use, reproduction, disclosure, or distribution of this software
* and related documentation without an express license agreement from
* NVIDIA Corporation is strictly prohibited.
*
* Please refer to the applicable NVIDIA end user license agreement (EULA)
* associated with this source code for terms and conditions that govern
* your use of this NVIDIA software.
*
*/
#include <hip/hip_runtime.h>
#include "stdio.h"
#define N 10
__global__
void add11( int *a, int *b, int *c ) {
int i = 0;
while (i < N) {
c[i] = a[i] + b[i];
i += 1;
}
}
__global__
void addn1( int *a, int *b, int *c ) {
int i = blockIdx.x;
c[i] = a[i] + b[i];
}
__global__
void add1n( int *a, int *b, int *c ) {
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
__global__
void add( int *a, int *b, int *c ) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < N; i += stride)
c[i] = a[i] + b[i];
}
int main( void ) {
int *a, *b, *c;
hipMallocManaged(&a, N*sizeof(int));
hipMallocManaged(&b, N*sizeof(int));
hipMallocManaged(&c, N*sizeof(int));
for (int i=0; i<N; i++) {
a[i] = -i;
b[i] = i * i;
}
add11<<<1, 1>>>(a, b, c);
hipDeviceSynchronize();
printf("1, 1\n");
for (int i=0; i<N; i++) {
printf( "%d + %d = %d\n", a[i], b[i], c[i] );
}
add1n<<<1, N>>>(a, b, c);
hipDeviceSynchronize();
printf("1, N\n");
for (int i=0; i<N; i++) {
printf( "%d + %d = %d\n", a[i], b[i], c[i] );
}
addn1<<<N, 1>>>(a, b, c);
hipDeviceSynchronize();
printf("N, 1\n");
for (int i=0; i<N; i++) {
printf( "%d + %d = %d\n", a[i], b[i], c[i] );
}
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
add<<<numBlocks, blockSize>>>(a, b, c);
hipDeviceSynchronize();
printf("<<<...>>>\n");
for (int i=0; i<N; i++) {
printf( "%d + %d = %d\n", a[i], b[i], c[i] );
}
hipFree(a);
hipFree(b);
hipFree(c);
return 0;
} | .text
.file "add_loop_cpu.hip"
.globl _Z20__device_stub__add11PiS_S_ # -- Begin function _Z20__device_stub__add11PiS_S_
.p2align 4, 0x90
.type _Z20__device_stub__add11PiS_S_,@function
_Z20__device_stub__add11PiS_S_: # @_Z20__device_stub__add11PiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5add11PiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z20__device_stub__add11PiS_S_, .Lfunc_end0-_Z20__device_stub__add11PiS_S_
.cfi_endproc
# -- End function
.globl _Z20__device_stub__addn1PiS_S_ # -- Begin function _Z20__device_stub__addn1PiS_S_
.p2align 4, 0x90
.type _Z20__device_stub__addn1PiS_S_,@function
_Z20__device_stub__addn1PiS_S_: # @_Z20__device_stub__addn1PiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5addn1PiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z20__device_stub__addn1PiS_S_, .Lfunc_end1-_Z20__device_stub__addn1PiS_S_
.cfi_endproc
# -- End function
.globl _Z20__device_stub__add1nPiS_S_ # -- Begin function _Z20__device_stub__add1nPiS_S_
.p2align 4, 0x90
.type _Z20__device_stub__add1nPiS_S_,@function
_Z20__device_stub__add1nPiS_S_: # @_Z20__device_stub__add1nPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5add1nPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z20__device_stub__add1nPiS_S_, .Lfunc_end2-_Z20__device_stub__add1nPiS_S_
.cfi_endproc
# -- End function
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end3-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 8(%rsp), %rdi
movl $40, %esi
movl $1, %edx
callq hipMallocManaged
movq %rsp, %rdi
movl $40, %esi
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movl $40, %esi
movl $1, %edx
callq hipMallocManaged
movq 8(%rsp), %rax
xorl %ecx, %ecx
movq (%rsp), %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB4_1: # =>This Inner Loop Header: Depth=1
movl %ecx, (%rax,%rsi,4)
movl %esi, %edi
imull %esi, %edi
movl %edi, (%rdx,%rsi,4)
incq %rsi
decl %ecx
cmpq $10, %rsi
jne .LBB4_1
# %bb.2:
movabsq $4294967297, %rbx # imm = 0x100000001
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_4
# %bb.3:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5add11PiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_4:
callq hipDeviceSynchronize
movl $.Lstr, %edi
callq puts@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_5: # =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rax
movl (%rax,%r14,4), %esi
movq (%rsp), %rax
movl (%rax,%r14,4), %edx
movq 16(%rsp), %rax
movl (%rax,%r14,4), %ecx
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $10, %r14
jne .LBB4_5
# %bb.6:
leaq 9(%rbx), %r14
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_8
# %bb.7:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5add1nPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_8:
callq hipDeviceSynchronize
movl $.Lstr.1, %edi
callq puts@PLT
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_9: # =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rax
movl (%rax,%r15,4), %esi
movq (%rsp), %rax
movl (%rax,%r15,4), %edx
movq 16(%rsp), %rax
movl (%rax,%r15,4), %ecx
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $10, %r15
jne .LBB4_9
# %bb.10:
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_12
# %bb.11:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5addn1PiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_12:
callq hipDeviceSynchronize
movl $.Lstr.2, %edi
callq puts@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_13: # =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rax
movl (%rax,%r14,4), %esi
movq (%rsp), %rax
movl (%rax,%r14,4), %edx
movq 16(%rsp), %rax
movl (%rax,%r14,4), %ecx
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $10, %r14
jne .LBB4_13
# %bb.14:
leaq 255(%rbx), %rdx
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_16
# %bb.15:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_16:
callq hipDeviceSynchronize
movl $.Lstr.3, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_17: # =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rax
movl (%rax,%rbx,4), %esi
movq (%rsp), %rax
movl (%rax,%rbx,4), %edx
movq 16(%rsp), %rax
movl (%rax,%rbx,4), %ecx
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB4_17
# %bb.18:
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5add11PiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5addn1PiS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5add1nPiS_S_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5add11PiS_S_,@object # @_Z5add11PiS_S_
.section .rodata,"a",@progbits
.globl _Z5add11PiS_S_
.p2align 3, 0x0
_Z5add11PiS_S_:
.quad _Z20__device_stub__add11PiS_S_
.size _Z5add11PiS_S_, 8
.type _Z5addn1PiS_S_,@object # @_Z5addn1PiS_S_
.globl _Z5addn1PiS_S_
.p2align 3, 0x0
_Z5addn1PiS_S_:
.quad _Z20__device_stub__addn1PiS_S_
.size _Z5addn1PiS_S_, 8
.type _Z5add1nPiS_S_,@object # @_Z5add1nPiS_S_
.globl _Z5add1nPiS_S_
.p2align 3, 0x0
_Z5add1nPiS_S_:
.quad _Z20__device_stub__add1nPiS_S_
.size _Z5add1nPiS_S_, 8
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d + %d = %d\n"
.size .L.str.1, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5add11PiS_S_"
.size .L__unnamed_1, 15
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z5addn1PiS_S_"
.size .L__unnamed_2, 15
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z5add1nPiS_S_"
.size .L__unnamed_3, 15
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_4, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "1, 1"
.size .Lstr, 5
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "1, N"
.size .Lstr.1, 5
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "N, 1"
.size .Lstr.2, 5
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "<<<...>>>"
.size .Lstr.3, 10
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__add11PiS_S_
.addrsig_sym _Z20__device_stub__addn1PiS_S_
.addrsig_sym _Z20__device_stub__add1nPiS_S_
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5add11PiS_S_
.addrsig_sym _Z5addn1PiS_S_
.addrsig_sym _Z5add1nPiS_S_
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GT.AND P0, PT, R3, 0x9, PT ; /* 0x000000090300780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x310 ; /* 0x0000028000007945 */
/* 0x000fe60003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R2, R0 ; /* 0x0000000000027306 */
/* 0x000e220000209000 */
/*00b0*/ IADD3 R7, RZ, -R0, RZ ; /* 0x80000000ff077210 */
/* 0x000fe40007ffe0ff */
/*00c0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fca0003f45070 */
/*00d0*/ MUFU.RCP R2, R2 ; /* 0x0000000200027308 */
/* 0x001e240000001000 */
/*00e0*/ IADD3 R4, R2, 0xffffffe, RZ ; /* 0x0ffffffe02047810 */
/* 0x001fcc0007ffe0ff */
/*00f0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0100*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0110*/ IMAD R7, R7, R5, RZ ; /* 0x0000000507077224 */
/* 0x002fc800078e02ff */
/*0120*/ IMAD.HI.U32 R6, R5, R7, R4 ; /* 0x0000000705067227 */
/* 0x000fe200078e0004 */
/*0130*/ IADD3 R5, -R3, 0x9, RZ ; /* 0x0000000903057810 */
/* 0x000fca0007ffe1ff */
/*0140*/ IMAD.HI.U32 R6, R6, R5, RZ ; /* 0x0000000506067227 */
/* 0x000fca00078e00ff */
/*0150*/ IADD3 R2, -R6, RZ, RZ ; /* 0x000000ff06027210 */
/* 0x000fca0007ffe1ff */
/*0160*/ IMAD R5, R0, R2, R5 ; /* 0x0000000200057224 */
/* 0x000fca00078e0205 */
/*0170*/ ISETP.GE.U32.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f06070 */
/*0180*/ @P0 IADD3 R5, -R0, R5, RZ ; /* 0x0000000500050210 */
/* 0x000fe40007ffe1ff */
/*0190*/ @P0 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106060810 */
/* 0x000fe40007ffe0ff */
/*01a0*/ ISETP.GE.U32.AND P1, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f26070 */
/*01b0*/ @P1 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106061810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ @!P2 LOP3.LUT R6, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff06a212 */
/* 0x000fc800078e33ff */
/*01d0*/ IADD3 R2, R6.reuse, 0x1, RZ ; /* 0x0000000106027810 */
/* 0x040fe40007ffe0ff */
/*01e0*/ ISETP.GE.U32.AND P1, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe40003f26070 */
/*01f0*/ LOP3.LUT P0, R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fda000780c0ff */
/*0200*/ @!P0 BRA 0x300 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0210*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fc800078e00ff */
/*0220*/ IMAD.WIDE R4, R3, R8, c[0x0][0x170] ; /* 0x00005c0003047625 */
/* 0x000fc800078e0208 */
/*0230*/ IMAD.WIDE R6, R3, R8, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fc800078e0208 */
/*0240*/ IMAD.WIDE R8, R3, R8, c[0x0][0x160] ; /* 0x0000580003087625 */
/* 0x000fc800078e0208 */
/*0250*/ LDG.E R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x0000a8000c1e1900 */
/*0260*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0002a2000c1e1900 */
/*0270*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*0280*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0290*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*02a0*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x001fc800078e0206 */
/*02b0*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x002fe200078e0208 */
/*02c0*/ IADD3 R11, R10, R11, RZ ; /* 0x0000000b0a0b7210 */
/* 0x004fca0007ffe0ff */
/*02d0*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0001e4000c101904 */
/*02e0*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x001fe200078e0204 */
/*02f0*/ @P0 BRA 0x250 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0300*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0310*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0320*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fd400000001ff */
/*0330*/ IMAD.WIDE R6, R3, R8, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fc800078e0208 */
/*0340*/ IMAD.WIDE R4, R3.reuse, R8.reuse, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x0c0fe200078e0208 */
/*0350*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea8000c1e1900 */
/*0360*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x001ea2000c1e1900 */
/*0370*/ IMAD.WIDE R8, R3, R8, c[0x0][0x170] ; /* 0x00005c0003087625 */
/* 0x000fc800078e0208 */
/*0380*/ IMAD.WIDE R12, R0, 0x4, R6 ; /* 0x00000004000c7825 */
/* 0x000fc800078e0206 */
/*0390*/ IMAD.IADD R19, R2, 0x1, R11 ; /* 0x0000000102137824 */
/* 0x004fe400078e020b */
/*03a0*/ IMAD.WIDE R10, R0, 0x4, R4 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0204 */
/*03b0*/ STG.E [R8.64], R19 ; /* 0x0000001308007986 */
/* 0x0001e8000c101904 */
/*03c0*/ LDG.E R2, [R12.64] ; /* 0x000000040c027981 */
/* 0x000ea8000c1e1900 */
/*03d0*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x000ea2000c1e1900 */
/*03e0*/ IMAD.WIDE R14, R0, 0x4, R8 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0208 */
/*03f0*/ IMAD.WIDE R6, R0, 0x4, R12 ; /* 0x0000000400067825 */
/* 0x000fc800078e020c */
/*0400*/ IMAD.WIDE R4, R0, 0x4, R10 ; /* 0x0000000400047825 */
/* 0x000fe200078e020a */
/*0410*/ IADD3 R21, R2, R17, RZ ; /* 0x0000001102157210 */
/* 0x004fca0007ffe0ff */
/*0420*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0003e8000c101904 */
/*0430*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea8000c1e1900 */
/*0440*/ LDG.E R23, [R4.64] ; /* 0x0000000404177981 */
/* 0x000ea2000c1e1900 */
/*0450*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc800078e020e */
/*0460*/ IMAD.WIDE R12, R0, 0x4, R6 ; /* 0x00000004000c7825 */
/* 0x000fc800078e0206 */
/*0470*/ IMAD.WIDE R8, R0, 0x4, R4 ; /* 0x0000000400087825 */
/* 0x001fe200078e0204 */
/*0480*/ IADD3 R23, R2, R23, RZ ; /* 0x0000001702177210 */
/* 0x004fca0007ffe0ff */
/*0490*/ STG.E [R16.64], R23 ; /* 0x0000001710007986 */
/* 0x0001e8000c101904 */
/*04a0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000e68000c1e1900 */
/*04b0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000e62000c1e1900 */
/*04c0*/ IMAD.WIDE R10, R0.reuse, 0x4, R16 ; /* 0x00000004000a7825 */
/* 0x040fe200078e0210 */
/*04d0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*04e0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*04f0*/ ISETP.GE.AND P0, PT, R3, 0xa, PT ; /* 0x0000000a0300780c */
/* 0x000fe40003f06270 */
/*0500*/ IADD3 R15, R12, R9, RZ ; /* 0x000000090c0f7210 */
/* 0x002fca0007ffe0ff */
/*0510*/ STG.E [R10.64], R15 ; /* 0x0000000f0a007986 */
/* 0x0001ec000c101904 */
/*0520*/ @!P0 BRA 0x320 ; /* 0xfffffdf000008947 */
/* 0x000fea000383ffff */
/*0530*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0540*/ BRA 0x540; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z5add1nPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z5addn1PiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z5add11PiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R6, c[0x0][0x160] ; /* 0x0000580000067a02 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff077624 */
/* 0x000fe200078e00ff */
/*0030*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0060*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea2000c1e1900 */
/*0080*/ MOV R2, c[0x0][0x170] ; /* 0x00005c0000027a02 */
/* 0x000fe20000000f00 */
/*0090*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fe200078e00ff */
/*00a0*/ IADD3 R9, R0, R9, RZ ; /* 0x0000000900097210 */
/* 0x004fca0007ffe0ff */
/*00b0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*00c0*/ LDG.E R0, [R6.64+0x4] ; /* 0x0000040406007981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R11, [R4.64+0x4] ; /* 0x00000404040b7981 */
/* 0x000ea4000c1e1900 */
/*00e0*/ IMAD.IADD R11, R0, 0x1, R11 ; /* 0x00000001000b7824 */
/* 0x004fca00078e020b */
/*00f0*/ STG.E [R2.64+0x4], R11 ; /* 0x0000040b02007986 */
/* 0x0003e8000c101904 */
/*0100*/ LDG.E R0, [R6.64+0x8] ; /* 0x0000080406007981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R13, [R4.64+0x8] ; /* 0x00000804040d7981 */
/* 0x000ea4000c1e1900 */
/*0120*/ IADD3 R13, R0, R13, RZ ; /* 0x0000000d000d7210 */
/* 0x004fca0007ffe0ff */
/*0130*/ STG.E [R2.64+0x8], R13 ; /* 0x0000080d02007986 */
/* 0x0005e8000c101904 */
/*0140*/ LDG.E R0, [R6.64+0xc] ; /* 0x00000c0406007981 */
/* 0x000ee8000c1e1900 */
/*0150*/ LDG.E R15, [R4.64+0xc] ; /* 0x00000c04040f7981 */
/* 0x000ee4000c1e1900 */
/*0160*/ IMAD.IADD R15, R0, 0x1, R15 ; /* 0x00000001000f7824 */
/* 0x008fca00078e020f */
/*0170*/ STG.E [R2.64+0xc], R15 ; /* 0x00000c0f02007986 */
/* 0x0007e8000c101904 */
/*0180*/ LDG.E R0, [R6.64+0x10] ; /* 0x0000100406007981 */
/* 0x000f28000c1e1900 */
/*0190*/ LDG.E R9, [R4.64+0x10] ; /* 0x0000100404097981 */
/* 0x001f24000c1e1900 */
/*01a0*/ IADD3 R9, R0, R9, RZ ; /* 0x0000000900097210 */
/* 0x010fca0007ffe0ff */
/*01b0*/ STG.E [R2.64+0x10], R9 ; /* 0x0000100902007986 */
/* 0x0001e8000c101904 */
/*01c0*/ LDG.E R0, [R6.64+0x14] ; /* 0x0000140406007981 */
/* 0x000f28000c1e1900 */
/*01d0*/ LDG.E R11, [R4.64+0x14] ; /* 0x00001404040b7981 */
/* 0x002f24000c1e1900 */
/*01e0*/ IMAD.IADD R11, R0, 0x1, R11 ; /* 0x00000001000b7824 */
/* 0x010fca00078e020b */
/*01f0*/ STG.E [R2.64+0x14], R11 ; /* 0x0000140b02007986 */
/* 0x0003e8000c101904 */
/*0200*/ LDG.E R0, [R6.64+0x18] ; /* 0x0000180406007981 */
/* 0x000f28000c1e1900 */
/*0210*/ LDG.E R13, [R4.64+0x18] ; /* 0x00001804040d7981 */
/* 0x004f24000c1e1900 */
/*0220*/ IADD3 R13, R0, R13, RZ ; /* 0x0000000d000d7210 */
/* 0x010fca0007ffe0ff */
/*0230*/ STG.E [R2.64+0x18], R13 ; /* 0x0000180d02007986 */
/* 0x000fe8000c101904 */
/*0240*/ LDG.E R0, [R6.64+0x1c] ; /* 0x00001c0406007981 */
/* 0x000ea8000c1e1900 */
/*0250*/ LDG.E R15, [R4.64+0x1c] ; /* 0x00001c04040f7981 */
/* 0x008ea4000c1e1900 */
/*0260*/ IMAD.IADD R15, R0, 0x1, R15 ; /* 0x00000001000f7824 */
/* 0x004fca00078e020f */
/*0270*/ STG.E [R2.64+0x1c], R15 ; /* 0x00001c0f02007986 */
/* 0x000fe8000c101904 */
/*0280*/ LDG.E R0, [R6.64+0x20] ; /* 0x0000200406007981 */
/* 0x000ea8000c1e1900 */
/*0290*/ LDG.E R9, [R4.64+0x20] ; /* 0x0000200404097981 */
/* 0x001ea4000c1e1900 */
/*02a0*/ IADD3 R9, R0, R9, RZ ; /* 0x0000000900097210 */
/* 0x004fca0007ffe0ff */
/*02b0*/ STG.E [R2.64+0x20], R9 ; /* 0x0000200902007986 */
/* 0x000fe8000c101904 */
/*02c0*/ LDG.E R0, [R6.64+0x24] ; /* 0x0000240406007981 */
/* 0x000ea8000c1e1900 */
/*02d0*/ LDG.E R11, [R4.64+0x24] ; /* 0x00002404040b7981 */
/* 0x002ea4000c1e1900 */
/*02e0*/ IMAD.IADD R11, R0, 0x1, R11 ; /* 0x00000001000b7824 */
/* 0x004fca00078e020b */
/*02f0*/ STG.E [R2.64+0x24], R11 ; /* 0x0000240b02007986 */
/* 0x000fe2000c101904 */
/*0300*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0310*/ BRA 0x310; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5add11PiS_S_
.globl _Z5add11PiS_S_
.p2align 8
.type _Z5add11PiS_S_,@function
_Z5add11PiS_S_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v0, 0
s_mov_b64 s[2:3], 0
.p2align 6
.LBB0_1:
s_waitcnt lgkmcnt(0)
s_add_u32 s8, s4, s2
s_addc_u32 s9, s5, s3
s_add_u32 s10, s6, s2
s_addc_u32 s11, s7, s3
s_clause 0x1
global_load_b32 v1, v0, s[8:9]
global_load_b32 v2, v0, s[10:11]
s_add_u32 s8, s0, s2
s_addc_u32 s9, s1, s3
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_lg_u32 s2, 40
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[8:9]
s_cbranch_scc1 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5add11PiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 12
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5add11PiS_S_, .Lfunc_end0-_Z5add11PiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z5addn1PiS_S_
.globl _Z5addn1PiS_S_
.p2align 8
.type _Z5addn1PiS_S_,@function
_Z5addn1PiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5addn1PiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z5addn1PiS_S_, .Lfunc_end1-_Z5addn1PiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z5add1nPiS_S_
.globl _Z5add1nPiS_S_
.p2align 8
.type _Z5add1nPiS_S_,@function
_Z5add1nPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5add1nPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z5add1nPiS_S_, .Lfunc_end2-_Z5add1nPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_load_b32 s4, s[0:1], 0x24
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 10, v1
s_cbranch_execz .LBB3_3
s_load_b32 s9, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s9, s8
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[8:9], 2
.p2align 6
.LBB3_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_add_nc_u32_e32 v1, s8, v1
global_load_b32 v0, v[4:5], off
global_load_b32 v6, v[6:7], off
v_add_co_u32 v4, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s10
v_cmp_lt_i32_e64 s0, 9, v1
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2)
s_or_b32 s1, s0, s1
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v6, v0
global_store_b32 v[4:5], v0, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB3_2
.LBB3_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z3addPiS_S_, .Lfunc_end3-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5add11PiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z5add11PiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5addn1PiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z5addn1PiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5add1nPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z5add1nPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00047e5e_00000000-6_add_loop_cpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z5add11PiS_S_PiS_S_
.type _Z28__device_stub__Z5add11PiS_S_PiS_S_, @function
_Z28__device_stub__Z5add11PiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5add11PiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z5add11PiS_S_PiS_S_, .-_Z28__device_stub__Z5add11PiS_S_PiS_S_
.globl _Z5add11PiS_S_
.type _Z5add11PiS_S_, @function
_Z5add11PiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z5add11PiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5add11PiS_S_, .-_Z5add11PiS_S_
.globl _Z28__device_stub__Z5addn1PiS_S_PiS_S_
.type _Z28__device_stub__Z5addn1PiS_S_PiS_S_, @function
_Z28__device_stub__Z5addn1PiS_S_PiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5addn1PiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z28__device_stub__Z5addn1PiS_S_PiS_S_, .-_Z28__device_stub__Z5addn1PiS_S_PiS_S_
.globl _Z5addn1PiS_S_
.type _Z5addn1PiS_S_, @function
_Z5addn1PiS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z5addn1PiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z5addn1PiS_S_, .-_Z5addn1PiS_S_
.globl _Z28__device_stub__Z5add1nPiS_S_PiS_S_
.type _Z28__device_stub__Z5add1nPiS_S_PiS_S_, @function
_Z28__device_stub__Z5add1nPiS_S_PiS_S_:
.LFB2086:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5add1nPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z28__device_stub__Z5add1nPiS_S_PiS_S_, .-_Z28__device_stub__Z5add1nPiS_S_PiS_S_
.globl _Z5add1nPiS_S_
.type _Z5add1nPiS_S_, @function
_Z5add1nPiS_S_:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z5add1nPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z5add1nPiS_S_, .-_Z5add1nPiS_S_
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2088:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "1, 1\n"
.LC1:
.string "%d + %d = %d\n"
.LC2:
.string "1, N\n"
.LC3:
.string "N, 1\n"
.LC4:
.string "<<<...>>>\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $40, %esi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $40, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $40, %esi
call cudaMallocManaged@PLT
movl $0, %eax
.L36:
movl %eax, %ecx
negl %ecx
movq 8(%rsp), %rdx
movl %ecx, (%rdx,%rax,4)
movl %eax, %ecx
imull %eax, %ecx
movq 16(%rsp), %rdx
movl %ecx, (%rdx,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L36
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L37:
call cudaDeviceSynchronize@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC1(%rip), %rbp
.L38:
movq 16(%rsp), %rax
movl (%rax,%rbx), %ecx
movq 8(%rsp), %rax
movl (%rax,%rbx), %edx
movq 24(%rsp), %rax
movl (%rax,%rbx), %r8d
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $40, %rbx
jne .L38
movl $10, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L53
.L39:
call cudaDeviceSynchronize@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC1(%rip), %rbp
.L40:
movq 16(%rsp), %rax
movl (%rax,%rbx), %ecx
movq 8(%rsp), %rax
movl (%rax,%rbx), %edx
movq 24(%rsp), %rax
movl (%rax,%rbx), %r8d
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $40, %rbx
jne .L40
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $10, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L54
.L41:
call cudaDeviceSynchronize@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC1(%rip), %rbp
.L42:
movq 16(%rsp), %rax
movl (%rax,%rbx), %ecx
movq 8(%rsp), %rax
movl (%rax,%rbx), %edx
movq 24(%rsp), %rax
movl (%rax,%rbx), %r8d
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $40, %rbx
jne .L42
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L55
.L43:
call cudaDeviceSynchronize@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC1(%rip), %rbp
.L44:
movq 16(%rsp), %rax
movl (%rax,%rbx), %ecx
movq 8(%rsp), %rax
movl (%rax,%rbx), %edx
movq 24(%rsp), %rax
movl (%rax,%rbx), %r8d
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $40, %rbx
jne .L44
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L56
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z28__device_stub__Z5add11PiS_S_PiS_S_
jmp .L37
.L53:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z28__device_stub__Z5add1nPiS_S_PiS_S_
jmp .L39
.L54:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z28__device_stub__Z5addn1PiS_S_PiS_S_
jmp .L41
.L55:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L43
.L56:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z3addPiS_S_"
.LC6:
.string "_Z5add1nPiS_S_"
.LC7:
.string "_Z5addn1PiS_S_"
.LC8:
.string "_Z5add11PiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z5add1nPiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z5addn1PiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z5add11PiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add_loop_cpu.hip"
.globl _Z20__device_stub__add11PiS_S_ # -- Begin function _Z20__device_stub__add11PiS_S_
.p2align 4, 0x90
.type _Z20__device_stub__add11PiS_S_,@function
_Z20__device_stub__add11PiS_S_: # @_Z20__device_stub__add11PiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5add11PiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z20__device_stub__add11PiS_S_, .Lfunc_end0-_Z20__device_stub__add11PiS_S_
.cfi_endproc
# -- End function
.globl _Z20__device_stub__addn1PiS_S_ # -- Begin function _Z20__device_stub__addn1PiS_S_
.p2align 4, 0x90
.type _Z20__device_stub__addn1PiS_S_,@function
_Z20__device_stub__addn1PiS_S_: # @_Z20__device_stub__addn1PiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5addn1PiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z20__device_stub__addn1PiS_S_, .Lfunc_end1-_Z20__device_stub__addn1PiS_S_
.cfi_endproc
# -- End function
.globl _Z20__device_stub__add1nPiS_S_ # -- Begin function _Z20__device_stub__add1nPiS_S_
.p2align 4, 0x90
.type _Z20__device_stub__add1nPiS_S_,@function
_Z20__device_stub__add1nPiS_S_: # @_Z20__device_stub__add1nPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5add1nPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z20__device_stub__add1nPiS_S_, .Lfunc_end2-_Z20__device_stub__add1nPiS_S_
.cfi_endproc
# -- End function
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end3-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 8(%rsp), %rdi
movl $40, %esi
movl $1, %edx
callq hipMallocManaged
movq %rsp, %rdi
movl $40, %esi
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movl $40, %esi
movl $1, %edx
callq hipMallocManaged
movq 8(%rsp), %rax
xorl %ecx, %ecx
movq (%rsp), %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB4_1: # =>This Inner Loop Header: Depth=1
movl %ecx, (%rax,%rsi,4)
movl %esi, %edi
imull %esi, %edi
movl %edi, (%rdx,%rsi,4)
incq %rsi
decl %ecx
cmpq $10, %rsi
jne .LBB4_1
# %bb.2:
movabsq $4294967297, %rbx # imm = 0x100000001
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_4
# %bb.3:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5add11PiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_4:
callq hipDeviceSynchronize
movl $.Lstr, %edi
callq puts@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_5: # =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rax
movl (%rax,%r14,4), %esi
movq (%rsp), %rax
movl (%rax,%r14,4), %edx
movq 16(%rsp), %rax
movl (%rax,%r14,4), %ecx
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $10, %r14
jne .LBB4_5
# %bb.6:
leaq 9(%rbx), %r14
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_8
# %bb.7:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5add1nPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_8:
callq hipDeviceSynchronize
movl $.Lstr.1, %edi
callq puts@PLT
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_9: # =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rax
movl (%rax,%r15,4), %esi
movq (%rsp), %rax
movl (%rax,%r15,4), %edx
movq 16(%rsp), %rax
movl (%rax,%r15,4), %ecx
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $10, %r15
jne .LBB4_9
# %bb.10:
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_12
# %bb.11:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5addn1PiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_12:
callq hipDeviceSynchronize
movl $.Lstr.2, %edi
callq puts@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_13: # =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rax
movl (%rax,%r14,4), %esi
movq (%rsp), %rax
movl (%rax,%r14,4), %edx
movq 16(%rsp), %rax
movl (%rax,%r14,4), %ecx
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $10, %r14
jne .LBB4_13
# %bb.14:
leaq 255(%rbx), %rdx
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_16
# %bb.15:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_16:
callq hipDeviceSynchronize
movl $.Lstr.3, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_17: # =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rax
movl (%rax,%rbx,4), %esi
movq (%rsp), %rax
movl (%rax,%rbx,4), %edx
movq 16(%rsp), %rax
movl (%rax,%rbx,4), %ecx
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB4_17
# %bb.18:
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5add11PiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5addn1PiS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5add1nPiS_S_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5add11PiS_S_,@object # @_Z5add11PiS_S_
.section .rodata,"a",@progbits
.globl _Z5add11PiS_S_
.p2align 3, 0x0
_Z5add11PiS_S_:
.quad _Z20__device_stub__add11PiS_S_
.size _Z5add11PiS_S_, 8
.type _Z5addn1PiS_S_,@object # @_Z5addn1PiS_S_
.globl _Z5addn1PiS_S_
.p2align 3, 0x0
_Z5addn1PiS_S_:
.quad _Z20__device_stub__addn1PiS_S_
.size _Z5addn1PiS_S_, 8
.type _Z5add1nPiS_S_,@object # @_Z5add1nPiS_S_
.globl _Z5add1nPiS_S_
.p2align 3, 0x0
_Z5add1nPiS_S_:
.quad _Z20__device_stub__add1nPiS_S_
.size _Z5add1nPiS_S_, 8
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d + %d = %d\n"
.size .L.str.1, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5add11PiS_S_"
.size .L__unnamed_1, 15
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z5addn1PiS_S_"
.size .L__unnamed_2, 15
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z5add1nPiS_S_"
.size .L__unnamed_3, 15
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_4, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "1, 1"
.size .Lstr, 5
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "1, N"
.size .Lstr.1, 5
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "N, 1"
.size .Lstr.2, 5
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "<<<...>>>"
.size .Lstr.3, 10
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__add11PiS_S_
.addrsig_sym _Z20__device_stub__addn1PiS_S_
.addrsig_sym _Z20__device_stub__add1nPiS_S_
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5add11PiS_S_
.addrsig_sym _Z5addn1PiS_S_
.addrsig_sym _Z5add1nPiS_S_
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //
// include files
//
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#define BLOCK_NUM (1024 * 32)
#define THREAD_NUM 32
#define N (BLOCK_NUM * THREAD_NUM)
static void cuda_checker(cudaError_t err, const char *file, int line ) {
if (err != cudaSuccess) {
printf("%s in %s at line %d\n", cudaGetErrorString(err), file, line);
exit(EXIT_FAILURE);
}
}
#define CUDA_CHECK(err) (cuda_checker(err, __FILE__, __LINE__ ))
//
// kernel code
//
__global__ void add(int *a, int *b, int *c) {
int tid = threadIdx.x + blockIdx.x * blockDim.x; // handle the data at this index
if (tid < N) {
if(tid % 2 == 0) {
c[tid] = a[tid] + b[tid];
} else {
c[tid] = a[tid] - b[tid];
}
}
}
//
// host code
//
int main(int argc, const char **argv) {
int *a, *b, *c;
a = (int*) malloc(sizeof(int) * N);
b = (int*) malloc(sizeof(int) * N);
c = (int*) malloc(sizeof(int) * N);
int *dev_a, *dev_b, *dev_c;
for(int i = 0; i < N; i++) {
a[i] = -i;
b[i] = i * i;
}
CUDA_CHECK( cudaMalloc((void**)&dev_a, N * sizeof(int)) );
CUDA_CHECK( cudaMalloc((void**)&dev_b, N * sizeof(int)) );
CUDA_CHECK( cudaMalloc((void**)&dev_c, N * sizeof(int)) );
CUDA_CHECK( cudaMemcpy(dev_a, a, N * sizeof(int), cudaMemcpyHostToDevice) );
CUDA_CHECK( cudaMemcpy(dev_b, b, N * sizeof(int), cudaMemcpyHostToDevice) );
float time;
cudaEvent_t start, stop;
CUDA_CHECK(cudaEventCreate(&start));
CUDA_CHECK(cudaEventCreate(&stop));
CUDA_CHECK(cudaEventRecord(start, 0));
add<<<BLOCK_NUM, THREAD_NUM>>>(dev_a, dev_b, dev_c);
CUDA_CHECK( cudaMemcpy(c, dev_c, N * sizeof(int), cudaMemcpyDeviceToHost) );
CUDA_CHECK(cudaEventRecord(stop, 0));
CUDA_CHECK(cudaEventSynchronize(stop));
CUDA_CHECK(cudaEventElapsedTime(&time, start, stop));
printf("Time to generate: %3.1f ms \n", time);
// for( int i = 0; i < N; i++ ){
// int cpu_value = 0;
// if (i % 2 == 0) {
// a[i]+b[i];
// } else {
// a[i]-b[i];
// }
// printf( "cpu: %d, gpu: %d\n", cpu_value, c[i]);
// }
CUDA_CHECK( cudaFree(dev_a) );
CUDA_CHECK( cudaFree(dev_b) );
CUDA_CHECK( cudaFree(dev_c) );
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R6, 0xfffff, PT ; /* 0x000fffff0600780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ LOP3.LUT R0, R6.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000106007812 */
/* 0x040fe200078ec0ff */
/*00d0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc600078e0207 */
/*00e0*/ ISETP.NE.U32.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f05070 */
/*00f0*/ @!P0 IADD3 R9, R2, -R5, RZ ; /* 0x8000000502098210 */
/* 0x004fca0007ffe0ff */
/*0100*/ @!P0 STG.E [R6.64], R9 ; /* 0x0000000906008986 */
/* 0x0001e2000c101904 */
/*0110*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0120*/ IADD3 R5, R2, R5, RZ ; /* 0x0000000502057210 */
/* 0x000fca0007ffe0ff */
/*0130*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //
// include files
//
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#define BLOCK_NUM (1024 * 32)
#define THREAD_NUM 32
#define N (BLOCK_NUM * THREAD_NUM)
static void cuda_checker(cudaError_t err, const char *file, int line ) {
if (err != cudaSuccess) {
printf("%s in %s at line %d\n", cudaGetErrorString(err), file, line);
exit(EXIT_FAILURE);
}
}
#define CUDA_CHECK(err) (cuda_checker(err, __FILE__, __LINE__ ))
//
// kernel code
//
__global__ void add(int *a, int *b, int *c) {
int tid = threadIdx.x + blockIdx.x * blockDim.x; // handle the data at this index
if (tid < N) {
if(tid % 2 == 0) {
c[tid] = a[tid] + b[tid];
} else {
c[tid] = a[tid] - b[tid];
}
}
}
//
// host code
//
int main(int argc, const char **argv) {
int *a, *b, *c;
a = (int*) malloc(sizeof(int) * N);
b = (int*) malloc(sizeof(int) * N);
c = (int*) malloc(sizeof(int) * N);
int *dev_a, *dev_b, *dev_c;
for(int i = 0; i < N; i++) {
a[i] = -i;
b[i] = i * i;
}
CUDA_CHECK( cudaMalloc((void**)&dev_a, N * sizeof(int)) );
CUDA_CHECK( cudaMalloc((void**)&dev_b, N * sizeof(int)) );
CUDA_CHECK( cudaMalloc((void**)&dev_c, N * sizeof(int)) );
CUDA_CHECK( cudaMemcpy(dev_a, a, N * sizeof(int), cudaMemcpyHostToDevice) );
CUDA_CHECK( cudaMemcpy(dev_b, b, N * sizeof(int), cudaMemcpyHostToDevice) );
float time;
cudaEvent_t start, stop;
CUDA_CHECK(cudaEventCreate(&start));
CUDA_CHECK(cudaEventCreate(&stop));
CUDA_CHECK(cudaEventRecord(start, 0));
add<<<BLOCK_NUM, THREAD_NUM>>>(dev_a, dev_b, dev_c);
CUDA_CHECK( cudaMemcpy(c, dev_c, N * sizeof(int), cudaMemcpyDeviceToHost) );
CUDA_CHECK(cudaEventRecord(stop, 0));
CUDA_CHECK(cudaEventSynchronize(stop));
CUDA_CHECK(cudaEventElapsedTime(&time, start, stop));
printf("Time to generate: %3.1f ms \n", time);
// for( int i = 0; i < N; i++ ){
// int cpu_value = 0;
// if (i % 2 == 0) {
// a[i]+b[i];
// } else {
// a[i]-b[i];
// }
// printf( "cpu: %d, gpu: %d\n", cpu_value, c[i]);
// }
CUDA_CHECK( cudaFree(dev_a) );
CUDA_CHECK( cudaFree(dev_b) );
CUDA_CHECK( cudaFree(dev_c) );
cudaDeviceReset();
return 0;
} | .file "tmpxft_0007eff2_00000000-6_prac4a.cudafe1.cpp"
.text
#APP
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s in %s at line %d\n"
#NO_APP
.text
.type _ZL12cuda_checker9cudaErrorPKci, @function
_ZL12cuda_checker9cudaErrorPKci:
.LFB2057:
.cfi_startproc
testl %edi, %edi
jne .L6
ret
.L6:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbx
movl %edx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rdx
movl %ebp, %r8d
movq %rbx, %rcx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _ZL12cuda_checker9cudaErrorPKci, .-_ZL12cuda_checker9cudaErrorPKci
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/jizhuoran/COMP3231_Tutorial/master/tutorial4/prac4a.cu"
.section .rodata.str1.1
.LC2:
.string "Time to generate: %3.1f ms \n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movl $4194304, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %eax
.L18:
movl %eax, %edx
negl %edx
movl %edx, 0(%rbp,%rax,4)
movl %eax, %edx
imull %eax, %edx
movl %edx, (%rbx,%rax,4)
addq $1, %rax
cmpq $1048576, %rax
jne .L18
leaq 8(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $63, %edx
leaq .LC1(%rip), %r13
movq %r13, %rsi
call _ZL12cuda_checker9cudaErrorPKci
leaq 16(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $64, %edx
movq %r13, %rsi
call _ZL12cuda_checker9cudaErrorPKci
leaq 24(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $65, %edx
movq %r13, %rsi
call _ZL12cuda_checker9cudaErrorPKci
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $67, %edx
movq %r13, %rsi
call _ZL12cuda_checker9cudaErrorPKci
movl $1, %ecx
movl $4194304, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $68, %edx
movq %r13, %rsi
call _ZL12cuda_checker9cudaErrorPKci
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
movl $74, %edx
movq %r13, %rsi
call _ZL12cuda_checker9cudaErrorPKci
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
movl $75, %edx
movq %r13, %rsi
call _ZL12cuda_checker9cudaErrorPKci
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %edi
movl $76, %edx
movq %r13, %rsi
call _ZL12cuda_checker9cudaErrorPKci
movl $32, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $32768, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movl $2, %ecx
movl $4194304, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $81, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _ZL12cuda_checker9cudaErrorPKci
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %edi
movl $83, %edx
movq %rbx, %rsi
call _ZL12cuda_checker9cudaErrorPKci
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movl %eax, %edi
movl $84, %edx
movq %rbx, %rsi
call _ZL12cuda_checker9cudaErrorPKci
leaq 60(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl %eax, %edi
movl $85, %edx
movq %rbx, %rsi
call _ZL12cuda_checker9cudaErrorPKci
pxor %xmm0, %xmm0
cvtss2sd 60(%rsp), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $101, %edx
movq %rbx, %rsi
call _ZL12cuda_checker9cudaErrorPKci
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $102, %edx
movq %rbx, %rsi
call _ZL12cuda_checker9cudaErrorPKci
movq 24(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $103, %edx
movq %rbx, %rsi
call _ZL12cuda_checker9cudaErrorPKci
call cudaDeviceReset@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //
// include files
//
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#define BLOCK_NUM (1024 * 32)
#define THREAD_NUM 32
#define N (BLOCK_NUM * THREAD_NUM)
static void cuda_checker(cudaError_t err, const char *file, int line ) {
if (err != cudaSuccess) {
printf("%s in %s at line %d\n", cudaGetErrorString(err), file, line);
exit(EXIT_FAILURE);
}
}
#define CUDA_CHECK(err) (cuda_checker(err, __FILE__, __LINE__ ))
//
// kernel code
//
__global__ void add(int *a, int *b, int *c) {
int tid = threadIdx.x + blockIdx.x * blockDim.x; // handle the data at this index
if (tid < N) {
if(tid % 2 == 0) {
c[tid] = a[tid] + b[tid];
} else {
c[tid] = a[tid] - b[tid];
}
}
}
//
// host code
//
int main(int argc, const char **argv) {
int *a, *b, *c;
a = (int*) malloc(sizeof(int) * N);
b = (int*) malloc(sizeof(int) * N);
c = (int*) malloc(sizeof(int) * N);
int *dev_a, *dev_b, *dev_c;
for(int i = 0; i < N; i++) {
a[i] = -i;
b[i] = i * i;
}
CUDA_CHECK( cudaMalloc((void**)&dev_a, N * sizeof(int)) );
CUDA_CHECK( cudaMalloc((void**)&dev_b, N * sizeof(int)) );
CUDA_CHECK( cudaMalloc((void**)&dev_c, N * sizeof(int)) );
CUDA_CHECK( cudaMemcpy(dev_a, a, N * sizeof(int), cudaMemcpyHostToDevice) );
CUDA_CHECK( cudaMemcpy(dev_b, b, N * sizeof(int), cudaMemcpyHostToDevice) );
float time;
cudaEvent_t start, stop;
CUDA_CHECK(cudaEventCreate(&start));
CUDA_CHECK(cudaEventCreate(&stop));
CUDA_CHECK(cudaEventRecord(start, 0));
add<<<BLOCK_NUM, THREAD_NUM>>>(dev_a, dev_b, dev_c);
CUDA_CHECK( cudaMemcpy(c, dev_c, N * sizeof(int), cudaMemcpyDeviceToHost) );
CUDA_CHECK(cudaEventRecord(stop, 0));
CUDA_CHECK(cudaEventSynchronize(stop));
CUDA_CHECK(cudaEventElapsedTime(&time, start, stop));
printf("Time to generate: %3.1f ms \n", time);
// for( int i = 0; i < N; i++ ){
// int cpu_value = 0;
// if (i % 2 == 0) {
// a[i]+b[i];
// } else {
// a[i]-b[i];
// }
// printf( "cpu: %d, gpu: %d\n", cpu_value, c[i]);
// }
CUDA_CHECK( cudaFree(dev_a) );
CUDA_CHECK( cudaFree(dev_b) );
CUDA_CHECK( cudaFree(dev_c) );
cudaDeviceReset();
return 0;
} | //
// include files
//
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#define BLOCK_NUM (1024 * 32)
#define THREAD_NUM 32
#define N (BLOCK_NUM * THREAD_NUM)
static void cuda_checker(hipError_t err, const char *file, int line ) {
if (err != hipSuccess) {
printf("%s in %s at line %d\n", hipGetErrorString(err), file, line);
exit(EXIT_FAILURE);
}
}
#define CUDA_CHECK(err) (cuda_checker(err, __FILE__, __LINE__ ))
//
// kernel code
//
__global__ void add(int *a, int *b, int *c) {
int tid = threadIdx.x + blockIdx.x * blockDim.x; // handle the data at this index
if (tid < N) {
if(tid % 2 == 0) {
c[tid] = a[tid] + b[tid];
} else {
c[tid] = a[tid] - b[tid];
}
}
}
//
// host code
//
int main(int argc, const char **argv) {
int *a, *b, *c;
a = (int*) malloc(sizeof(int) * N);
b = (int*) malloc(sizeof(int) * N);
c = (int*) malloc(sizeof(int) * N);
int *dev_a, *dev_b, *dev_c;
for(int i = 0; i < N; i++) {
a[i] = -i;
b[i] = i * i;
}
CUDA_CHECK( hipMalloc((void**)&dev_a, N * sizeof(int)) );
CUDA_CHECK( hipMalloc((void**)&dev_b, N * sizeof(int)) );
CUDA_CHECK( hipMalloc((void**)&dev_c, N * sizeof(int)) );
CUDA_CHECK( hipMemcpy(dev_a, a, N * sizeof(int), hipMemcpyHostToDevice) );
CUDA_CHECK( hipMemcpy(dev_b, b, N * sizeof(int), hipMemcpyHostToDevice) );
float time;
hipEvent_t start, stop;
CUDA_CHECK(hipEventCreate(&start));
CUDA_CHECK(hipEventCreate(&stop));
CUDA_CHECK(hipEventRecord(start, 0));
add<<<BLOCK_NUM, THREAD_NUM>>>(dev_a, dev_b, dev_c);
CUDA_CHECK( hipMemcpy(c, dev_c, N * sizeof(int), hipMemcpyDeviceToHost) );
CUDA_CHECK(hipEventRecord(stop, 0));
CUDA_CHECK(hipEventSynchronize(stop));
CUDA_CHECK(hipEventElapsedTime(&time, start, stop));
printf("Time to generate: %3.1f ms \n", time);
// for( int i = 0; i < N; i++ ){
// int cpu_value = 0;
// if (i % 2 == 0) {
// a[i]+b[i];
// } else {
// a[i]-b[i];
// }
// printf( "cpu: %d, gpu: %d\n", cpu_value, c[i]);
// }
CUDA_CHECK( hipFree(dev_a) );
CUDA_CHECK( hipFree(dev_b) );
CUDA_CHECK( hipFree(dev_c) );
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //
// include files
//
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#define BLOCK_NUM (1024 * 32)
#define THREAD_NUM 32
#define N (BLOCK_NUM * THREAD_NUM)
static void cuda_checker(hipError_t err, const char *file, int line ) {
if (err != hipSuccess) {
printf("%s in %s at line %d\n", hipGetErrorString(err), file, line);
exit(EXIT_FAILURE);
}
}
#define CUDA_CHECK(err) (cuda_checker(err, __FILE__, __LINE__ ))
//
// kernel code
//
__global__ void add(int *a, int *b, int *c) {
int tid = threadIdx.x + blockIdx.x * blockDim.x; // handle the data at this index
if (tid < N) {
if(tid % 2 == 0) {
c[tid] = a[tid] + b[tid];
} else {
c[tid] = a[tid] - b[tid];
}
}
}
//
// host code
//
int main(int argc, const char **argv) {
int *a, *b, *c;
a = (int*) malloc(sizeof(int) * N);
b = (int*) malloc(sizeof(int) * N);
c = (int*) malloc(sizeof(int) * N);
int *dev_a, *dev_b, *dev_c;
for(int i = 0; i < N; i++) {
a[i] = -i;
b[i] = i * i;
}
CUDA_CHECK( hipMalloc((void**)&dev_a, N * sizeof(int)) );
CUDA_CHECK( hipMalloc((void**)&dev_b, N * sizeof(int)) );
CUDA_CHECK( hipMalloc((void**)&dev_c, N * sizeof(int)) );
CUDA_CHECK( hipMemcpy(dev_a, a, N * sizeof(int), hipMemcpyHostToDevice) );
CUDA_CHECK( hipMemcpy(dev_b, b, N * sizeof(int), hipMemcpyHostToDevice) );
float time;
hipEvent_t start, stop;
CUDA_CHECK(hipEventCreate(&start));
CUDA_CHECK(hipEventCreate(&stop));
CUDA_CHECK(hipEventRecord(start, 0));
add<<<BLOCK_NUM, THREAD_NUM>>>(dev_a, dev_b, dev_c);
CUDA_CHECK( hipMemcpy(c, dev_c, N * sizeof(int), hipMemcpyDeviceToHost) );
CUDA_CHECK(hipEventRecord(stop, 0));
CUDA_CHECK(hipEventSynchronize(stop));
CUDA_CHECK(hipEventElapsedTime(&time, start, stop));
printf("Time to generate: %3.1f ms \n", time);
// for( int i = 0; i < N; i++ ){
// int cpu_value = 0;
// if (i % 2 == 0) {
// a[i]+b[i];
// } else {
// a[i]-b[i];
// }
// printf( "cpu: %d, gpu: %d\n", cpu_value, c[i]);
// }
CUDA_CHECK( hipFree(dev_a) );
CUDA_CHECK( hipFree(dev_b) );
CUDA_CHECK( hipFree(dev_c) );
hipDeviceReset();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x100000, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_and_b32_e32 v1, 1, v1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
global_load_b32 v0, v[4:5], off
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v1
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(1)
v_sub_nc_u32_e32 v5, 0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v5, v5, v0, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v4, v5
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //
// include files
//
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#define BLOCK_NUM (1024 * 32)
#define THREAD_NUM 32
#define N (BLOCK_NUM * THREAD_NUM)
static void cuda_checker(hipError_t err, const char *file, int line ) {
if (err != hipSuccess) {
printf("%s in %s at line %d\n", hipGetErrorString(err), file, line);
exit(EXIT_FAILURE);
}
}
#define CUDA_CHECK(err) (cuda_checker(err, __FILE__, __LINE__ ))
//
// kernel code
//
__global__ void add(int *a, int *b, int *c) {
int tid = threadIdx.x + blockIdx.x * blockDim.x; // handle the data at this index
if (tid < N) {
if(tid % 2 == 0) {
c[tid] = a[tid] + b[tid];
} else {
c[tid] = a[tid] - b[tid];
}
}
}
//
// host code
//
int main(int argc, const char **argv) {
int *a, *b, *c;
a = (int*) malloc(sizeof(int) * N);
b = (int*) malloc(sizeof(int) * N);
c = (int*) malloc(sizeof(int) * N);
int *dev_a, *dev_b, *dev_c;
for(int i = 0; i < N; i++) {
a[i] = -i;
b[i] = i * i;
}
CUDA_CHECK( hipMalloc((void**)&dev_a, N * sizeof(int)) );
CUDA_CHECK( hipMalloc((void**)&dev_b, N * sizeof(int)) );
CUDA_CHECK( hipMalloc((void**)&dev_c, N * sizeof(int)) );
CUDA_CHECK( hipMemcpy(dev_a, a, N * sizeof(int), hipMemcpyHostToDevice) );
CUDA_CHECK( hipMemcpy(dev_b, b, N * sizeof(int), hipMemcpyHostToDevice) );
float time;
hipEvent_t start, stop;
CUDA_CHECK(hipEventCreate(&start));
CUDA_CHECK(hipEventCreate(&stop));
CUDA_CHECK(hipEventRecord(start, 0));
add<<<BLOCK_NUM, THREAD_NUM>>>(dev_a, dev_b, dev_c);
CUDA_CHECK( hipMemcpy(c, dev_c, N * sizeof(int), hipMemcpyDeviceToHost) );
CUDA_CHECK(hipEventRecord(stop, 0));
CUDA_CHECK(hipEventSynchronize(stop));
CUDA_CHECK(hipEventElapsedTime(&time, start, stop));
printf("Time to generate: %3.1f ms \n", time);
// for( int i = 0; i < N; i++ ){
// int cpu_value = 0;
// if (i % 2 == 0) {
// a[i]+b[i];
// } else {
// a[i]-b[i];
// }
// printf( "cpu: %d, gpu: %d\n", cpu_value, c[i]);
// }
CUDA_CHECK( hipFree(dev_a) );
CUDA_CHECK( hipFree(dev_b) );
CUDA_CHECK( hipFree(dev_c) );
hipDeviceReset();
return 0;
} | .text
.file "prac4a.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r15
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%r15,%rcx,4)
movl %ecx, %edx
imull %ecx, %edx
movl %edx, (%r14,%rcx,4)
incq %rcx
decl %eax
cmpq $1048576, %rcx # imm = 0x100000
jne .LBB1_1
# %bb.2:
leaq 32(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
jne .LBB1_3
# %bb.5: # %_ZL12cuda_checker10hipError_tPKci.exit
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
jne .LBB1_6
# %bb.7: # %_ZL12cuda_checker10hipError_tPKci.exit14
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
jne .LBB1_8
# %bb.9: # %_ZL12cuda_checker10hipError_tPKci.exit16
movq 32(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_10
# %bb.11: # %_ZL12cuda_checker10hipError_tPKci.exit18
movq 24(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_12
# %bb.13: # %_ZL12cuda_checker10hipError_tPKci.exit20
leaq 40(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB1_14
# %bb.15: # %_ZL12cuda_checker10hipError_tPKci.exit22
leaq 8(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB1_16
# %bb.17: # %_ZL12cuda_checker10hipError_tPKci.exit24
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB1_18
# %bb.19: # %_ZL12cuda_checker10hipError_tPKci.exit26
movabsq $4294967328, %rdx # imm = 0x100000020
leaq 32736(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_21
# %bb.20:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
leaq 136(%rsp), %rax
movq %rax, 48(%rsp)
leaq 128(%rsp), %rax
movq %rax, 56(%rsp)
leaq 120(%rsp), %rax
movq %rax, 64(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_21:
movq 16(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_22
# %bb.23: # %_ZL12cuda_checker10hipError_tPKci.exit28
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB1_24
# %bb.25: # %_ZL12cuda_checker10hipError_tPKci.exit30
movq 8(%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
jne .LBB1_26
# %bb.27: # %_ZL12cuda_checker10hipError_tPKci.exit32
movq 40(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
testl %eax, %eax
jne .LBB1_28
# %bb.29: # %_ZL12cuda_checker10hipError_tPKci.exit34
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_30
# %bb.31: # %_ZL12cuda_checker10hipError_tPKci.exit36
movq 24(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_32
# %bb.33: # %_ZL12cuda_checker10hipError_tPKci.exit38
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_34
# %bb.35: # %_ZL12cuda_checker10hipError_tPKci.exit40
callq hipDeviceReset
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_3:
.cfi_def_cfa_offset 176
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $65, %ecx
jmp .LBB1_4
.LBB1_6:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $66, %ecx
jmp .LBB1_4
.LBB1_8:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $67, %ecx
jmp .LBB1_4
.LBB1_10:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $69, %ecx
jmp .LBB1_4
.LBB1_12:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $70, %ecx
jmp .LBB1_4
.LBB1_14:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $76, %ecx
jmp .LBB1_4
.LBB1_16:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $77, %ecx
jmp .LBB1_4
.LBB1_18:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $78, %ecx
jmp .LBB1_4
.LBB1_22:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $83, %ecx
jmp .LBB1_4
.LBB1_24:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $85, %ecx
jmp .LBB1_4
.LBB1_26:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $86, %ecx
jmp .LBB1_4
.LBB1_28:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $87, %ecx
jmp .LBB1_4
.LBB1_30:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $103, %ecx
jmp .LBB1_4
.LBB1_32:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $104, %ecx
jmp .LBB1_4
.LBB1_34:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $105, %ecx
.LBB1_4:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/jizhuoran/COMP3231_Tutorial/master/tutorial4/prac4a.hip"
.size .L.str, 113
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Time to generate: %3.1f ms \n"
.size .L.str.1, 30
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%s in %s at line %d\n"
.size .L.str.2, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R6, 0xfffff, PT ; /* 0x000fffff0600780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ LOP3.LUT R0, R6.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000106007812 */
/* 0x040fe200078ec0ff */
/*00d0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc600078e0207 */
/*00e0*/ ISETP.NE.U32.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f05070 */
/*00f0*/ @!P0 IADD3 R9, R2, -R5, RZ ; /* 0x8000000502098210 */
/* 0x004fca0007ffe0ff */
/*0100*/ @!P0 STG.E [R6.64], R9 ; /* 0x0000000906008986 */
/* 0x0001e2000c101904 */
/*0110*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0120*/ IADD3 R5, R2, R5, RZ ; /* 0x0000000502057210 */
/* 0x000fca0007ffe0ff */
/*0130*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x100000, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_and_b32_e32 v1, 1, v1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
global_load_b32 v0, v[4:5], off
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v1
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(1)
v_sub_nc_u32_e32 v5, 0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v5, v5, v0, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v4, v5
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007eff2_00000000-6_prac4a.cudafe1.cpp"
.text
#APP
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s in %s at line %d\n"
#NO_APP
.text
.type _ZL12cuda_checker9cudaErrorPKci, @function
_ZL12cuda_checker9cudaErrorPKci:
.LFB2057:
.cfi_startproc
testl %edi, %edi
jne .L6
ret
.L6:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbx
movl %edx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rdx
movl %ebp, %r8d
movq %rbx, %rcx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _ZL12cuda_checker9cudaErrorPKci, .-_ZL12cuda_checker9cudaErrorPKci
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/jizhuoran/COMP3231_Tutorial/master/tutorial4/prac4a.cu"
.section .rodata.str1.1
.LC2:
.string "Time to generate: %3.1f ms \n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movl $4194304, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %eax
.L18:
movl %eax, %edx
negl %edx
movl %edx, 0(%rbp,%rax,4)
movl %eax, %edx
imull %eax, %edx
movl %edx, (%rbx,%rax,4)
addq $1, %rax
cmpq $1048576, %rax
jne .L18
leaq 8(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $63, %edx
leaq .LC1(%rip), %r13
movq %r13, %rsi
call _ZL12cuda_checker9cudaErrorPKci
leaq 16(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $64, %edx
movq %r13, %rsi
call _ZL12cuda_checker9cudaErrorPKci
leaq 24(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $65, %edx
movq %r13, %rsi
call _ZL12cuda_checker9cudaErrorPKci
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $67, %edx
movq %r13, %rsi
call _ZL12cuda_checker9cudaErrorPKci
movl $1, %ecx
movl $4194304, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $68, %edx
movq %r13, %rsi
call _ZL12cuda_checker9cudaErrorPKci
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
movl $74, %edx
movq %r13, %rsi
call _ZL12cuda_checker9cudaErrorPKci
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
movl $75, %edx
movq %r13, %rsi
call _ZL12cuda_checker9cudaErrorPKci
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %edi
movl $76, %edx
movq %r13, %rsi
call _ZL12cuda_checker9cudaErrorPKci
movl $32, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $32768, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movl $2, %ecx
movl $4194304, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $81, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _ZL12cuda_checker9cudaErrorPKci
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %edi
movl $83, %edx
movq %rbx, %rsi
call _ZL12cuda_checker9cudaErrorPKci
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movl %eax, %edi
movl $84, %edx
movq %rbx, %rsi
call _ZL12cuda_checker9cudaErrorPKci
leaq 60(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl %eax, %edi
movl $85, %edx
movq %rbx, %rsi
call _ZL12cuda_checker9cudaErrorPKci
pxor %xmm0, %xmm0
cvtss2sd 60(%rsp), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $101, %edx
movq %rbx, %rsi
call _ZL12cuda_checker9cudaErrorPKci
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $102, %edx
movq %rbx, %rsi
call _ZL12cuda_checker9cudaErrorPKci
movq 24(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $103, %edx
movq %rbx, %rsi
call _ZL12cuda_checker9cudaErrorPKci
call cudaDeviceReset@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "prac4a.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r15
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%r15,%rcx,4)
movl %ecx, %edx
imull %ecx, %edx
movl %edx, (%r14,%rcx,4)
incq %rcx
decl %eax
cmpq $1048576, %rcx # imm = 0x100000
jne .LBB1_1
# %bb.2:
leaq 32(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
jne .LBB1_3
# %bb.5: # %_ZL12cuda_checker10hipError_tPKci.exit
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
jne .LBB1_6
# %bb.7: # %_ZL12cuda_checker10hipError_tPKci.exit14
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
jne .LBB1_8
# %bb.9: # %_ZL12cuda_checker10hipError_tPKci.exit16
movq 32(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_10
# %bb.11: # %_ZL12cuda_checker10hipError_tPKci.exit18
movq 24(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_12
# %bb.13: # %_ZL12cuda_checker10hipError_tPKci.exit20
leaq 40(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB1_14
# %bb.15: # %_ZL12cuda_checker10hipError_tPKci.exit22
leaq 8(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB1_16
# %bb.17: # %_ZL12cuda_checker10hipError_tPKci.exit24
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB1_18
# %bb.19: # %_ZL12cuda_checker10hipError_tPKci.exit26
movabsq $4294967328, %rdx # imm = 0x100000020
leaq 32736(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_21
# %bb.20:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
leaq 136(%rsp), %rax
movq %rax, 48(%rsp)
leaq 128(%rsp), %rax
movq %rax, 56(%rsp)
leaq 120(%rsp), %rax
movq %rax, 64(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_21:
movq 16(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_22
# %bb.23: # %_ZL12cuda_checker10hipError_tPKci.exit28
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB1_24
# %bb.25: # %_ZL12cuda_checker10hipError_tPKci.exit30
movq 8(%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
jne .LBB1_26
# %bb.27: # %_ZL12cuda_checker10hipError_tPKci.exit32
movq 40(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
testl %eax, %eax
jne .LBB1_28
# %bb.29: # %_ZL12cuda_checker10hipError_tPKci.exit34
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_30
# %bb.31: # %_ZL12cuda_checker10hipError_tPKci.exit36
movq 24(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_32
# %bb.33: # %_ZL12cuda_checker10hipError_tPKci.exit38
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_34
# %bb.35: # %_ZL12cuda_checker10hipError_tPKci.exit40
callq hipDeviceReset
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_3:
.cfi_def_cfa_offset 176
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $65, %ecx
jmp .LBB1_4
.LBB1_6:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $66, %ecx
jmp .LBB1_4
.LBB1_8:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $67, %ecx
jmp .LBB1_4
.LBB1_10:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $69, %ecx
jmp .LBB1_4
.LBB1_12:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $70, %ecx
jmp .LBB1_4
.LBB1_14:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $76, %ecx
jmp .LBB1_4
.LBB1_16:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $77, %ecx
jmp .LBB1_4
.LBB1_18:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $78, %ecx
jmp .LBB1_4
.LBB1_22:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $83, %ecx
jmp .LBB1_4
.LBB1_24:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $85, %ecx
jmp .LBB1_4
.LBB1_26:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $86, %ecx
jmp .LBB1_4
.LBB1_28:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $87, %ecx
jmp .LBB1_4
.LBB1_30:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $103, %ecx
jmp .LBB1_4
.LBB1_32:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $104, %ecx
jmp .LBB1_4
.LBB1_34:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $105, %ecx
.LBB1_4:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/jizhuoran/COMP3231_Tutorial/master/tutorial4/prac4a.hip"
.size .L.str, 113
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Time to generate: %3.1f ms \n"
.size .L.str.1, 30
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%s in %s at line %d\n"
.size .L.str.2, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void update_e( int Ny, int Nz, float *Ex, float *Ey, float *Ez, float *Hx, float *Hy, float *Hz, float *CEx, float *CEy, float *CEz ) {
int tk = threadIdx.x;
int idx = blockIdx.x*blockDim.x + tk;
int Nyz = Ny*Nz;
//int fidx = idx + idx/(Nz-1) + Nyz + Nz + 1;
int fidx = idx + idx/(Nz-1) + idx/( (Nz-1)*(Ny-1) )*(Nz-1) + Nyz + Nz + 1;
extern __shared__ float hs[];
float* hx = (float*) hs;
float* hy = (float*) &hx[blockDim.x+1];
float* hz = (float*) &hy[blockDim.x+1];
hx[tk] = Hx[fidx];
hy[tk] = Hy[fidx];
hz[tk] = Hz[fidx];
if ( tk==blockDim.x-1 ) {
hx[tk+1] = Hx[fidx+1];
hy[tk+1] = Hy[fidx+1];
}
__syncthreads();
Ex[fidx] += CEx[fidx]*( Hz[fidx+Nz] - hz[tk] - hy[tk+1] + hy[tk] );
Ey[fidx] += CEy[fidx]*( hx[tk+1] - hx[tk] - Hz[fidx+Nyz] + hz[tk] );
Ez[fidx] += CEz[fidx]*( Hy[fidx+Nyz] - hy[tk] - Hx[fidx+Nz] + hx[tk] );
}
__global__ void update_h( int Ny, int Nz, float *Ex, float *Ey, float *Ez, float *Hx, float *Hy, float *Hz ) {
int tk = threadIdx.x;
int idx = blockIdx.x*blockDim.x + tk;
int Nyz = Ny*Nz;
//int fidx = idx + idx/(Nz-1) + Nyz + Nz + 1;
int fidx = idx + idx/(Nz-1) + idx/( (Nz-1)*(Ny-1) )*(Nz-1) + Nyz + Nz + 1;
extern __shared__ float es[];
float* ex = (float*) es;
float* ey = (float*) &ex[blockDim.x+1];
float* ez = (float*) &ey[blockDim.x+1];
ex[tk+1] = Ex[fidx];
ey[tk+1] = Ey[fidx];
ez[tk] = Ez[fidx];
if ( tk==0 ) {
ex[0] = Ex[fidx-1];
ey[0] = Ey[fidx-1];
}
__syncthreads();
Hx[fidx] -= 0.5*( ez[tk] - Ez[fidx-Nz] - ey[tk+1] + ey[tk] );
Hy[fidx] -= 0.5*( ex[tk+1] - ex[tk] - ez[tk] + Ez[fidx-Nyz] );
Hz[fidx] -= 0.5*( ey[tk+1] - Ey[fidx-Nyz] - ex[tk+1] + Ex[fidx-Nz] );
} | code for sm_80
Function : _Z8update_hiiPfS_S_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff047624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000002500 */
/*0040*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe4000fffe03f */
/*0050*/ IADD3 R2, R4, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x000fe20007ffe0ff */
/*0060*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0080*/ IABS R8, R2.reuse ; /* 0x0000000200087213 */
/* 0x080fe20000000000 */
/*0090*/ IMAD R3, R2, UR4, RZ ; /* 0x0000000402037c24 */
/* 0x000fe2000f8e02ff */
/*00a0*/ IABS R14, R2 ; /* 0x00000002000e7213 */
/* 0x000fc40000000000 */
/*00b0*/ I2F.RP R12, R8 ; /* 0x00000008000c7306 */
/* 0x000e620000209400 */
/*00c0*/ ISETP.NE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f25270 */
/*00d0*/ IABS R5, R3 ; /* 0x0000000300057213 */
/* 0x000fe20000000000 */
/*00e0*/ IMAD.MOV R14, RZ, RZ, -R14 ; /* 0x000000ffff0e7224 */
/* 0x000fc800078e0a0e */
/*00f0*/ I2F.RP R13, R5 ; /* 0x00000005000d7306 */
/* 0x000eb00000209400 */
/*0100*/ MUFU.RCP R12, R12 ; /* 0x0000000c000c7308 */
/* 0x002e620000001000 */
/*0110*/ IMAD R9, R9, c[0x0][0x0], R0 ; /* 0x0000000009097a24 */
/* 0x001fce00078e0200 */
/*0120*/ MUFU.RCP R13, R13 ; /* 0x0000000d000d7308 */
/* 0x004e220000001000 */
/*0130*/ IADD3 R10, R12, 0xffffffe, RZ ; /* 0x0ffffffe0c0a7810 */
/* 0x002fe40007ffe0ff */
/*0140*/ IABS R12, R9 ; /* 0x00000009000c7213 */
/* 0x000fca0000000000 */
/*0150*/ F2I.FTZ.U32.TRUNC.NTZ R11, R10 ; /* 0x0000000a000b7305 */
/* 0x0002a2000021f000 */
/*0160*/ IADD3 R6, R13, 0xffffffe, RZ ; /* 0x0ffffffe0d067810 */
/* 0x001fce0007ffe0ff */
/*0170*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x0000e2000021f000 */
/*0180*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x002fe200078e00ff */
/*0190*/ IADD3 R15, RZ, -R11, RZ ; /* 0x8000000bff0f7210 */
/* 0x004fe20007ffe0ff */
/*01a0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fc800078e00ff */
/*01b0*/ IMAD R13, R15, R8, RZ ; /* 0x000000080f0d7224 */
/* 0x000fe400078e02ff */
/*01c0*/ IMAD.MOV R16, RZ, RZ, -R7 ; /* 0x000000ffff107224 */
/* 0x008fe400078e0a07 */
/*01d0*/ IMAD.HI.U32 R10, R11, R13, R10 ; /* 0x0000000d0b0a7227 */
/* 0x000fe200078e000a */
/*01e0*/ MOV R11, R12 ; /* 0x0000000c000b7202 */
/* 0x000fe40000000f00 */
/*01f0*/ IABS R12, R3 ; /* 0x00000003000c7213 */
/* 0x000fe20000000000 */
/*0200*/ IMAD R13, R16, R5, RZ ; /* 0x00000005100d7224 */
/* 0x000fe400078e02ff */
/*0210*/ IMAD.HI.U32 R10, R10, R11, RZ ; /* 0x0000000b0a0a7227 */
/* 0x000fc800078e00ff */
/*0220*/ IMAD.HI.U32 R6, R7, R13, R6 ; /* 0x0000000d07067227 */
/* 0x000fe200078e0006 */
/*0230*/ MOV R7, R14 ; /* 0x0000000e00077202 */
/* 0x000fc60000000f00 */
/*0240*/ IMAD.MOV R12, RZ, RZ, -R12 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0a0c */
/*0250*/ IMAD R7, R10, R7, R11 ; /* 0x000000070a077224 */
/* 0x000fe400078e020b */
/*0260*/ IMAD.HI.U32 R6, R6, R11, RZ ; /* 0x0000000b06067227 */
/* 0x000fc600078e00ff */
/*0270*/ ISETP.GT.U32.AND P0, PT, R8, R7, PT ; /* 0x000000070800720c */
/* 0x000fe20003f04070 */
/*0280*/ IMAD R12, R6, R12, R11 ; /* 0x0000000c060c7224 */
/* 0x000fca00078e020b */
/*0290*/ ISETP.GT.U32.AND P4, PT, R5, R12, PT ; /* 0x0000000c0500720c */
/* 0x000fce0003f84070 */
/*02a0*/ @!P0 IMAD.IADD R7, R7, 0x1, -R8 ; /* 0x0000000107078824 */
/* 0x000fe200078e0a08 */
/*02b0*/ @!P0 IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a8810 */
/* 0x000fc80007ffe0ff */
/*02c0*/ ISETP.GE.U32.AND P5, PT, R7, R8, PT ; /* 0x000000080700720c */
/* 0x000fe40003fa6070 */
/*02d0*/ @!P4 IADD3 R12, R12, -R5.reuse, RZ ; /* 0x800000050c0cc210 */
/* 0x080fe40007ffe0ff */
/*02e0*/ LOP3.LUT R7, R9.reuse, R2, RZ, 0x3c, !PT ; /* 0x0000000209077212 */
/* 0x040fe400078e3cff */
/*02f0*/ ISETP.GE.U32.AND P3, PT, R12, R5, PT ; /* 0x000000050c00720c */
/* 0x000fe40003f66070 */
/*0300*/ LOP3.LUT R5, R9, R3, RZ, 0x3c, !PT ; /* 0x0000000309057212 */
/* 0x000fe400078e3cff */
/*0310*/ ISETP.GE.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc40003f46270 */
/*0320*/ ISETP.GE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f06270 */
/*0330*/ @!P4 IADD3 R6, R6, 0x1, RZ ; /* 0x000000010606c810 */
/* 0x000fe40007ffe0ff */
/*0340*/ ISETP.NE.AND P4, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe40003f85270 */
/*0350*/ @P5 IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a5810 */
/* 0x000fe40007ffe0ff */
/*0360*/ IADD3 R9, R9, c[0x0][0x164], RZ ; /* 0x0000590009097a10 */
/* 0x000fe40007ffe0ff */
/*0370*/ @P3 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106063810 */
/* 0x000fe20007ffe0ff */
/*0380*/ @!P2 IMAD.MOV R10, RZ, RZ, -R10 ; /* 0x000000ffff0aa224 */
/* 0x000fe200078e0a0a */
/*0390*/ @!P1 LOP3.LUT R10, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff0a9212 */
/* 0x000fe200078e33ff */
/*03a0*/ IMAD R9, R4, c[0x0][0x160], R9 ; /* 0x0000580004097a24 */
/* 0x000fc400078e0209 */
/*03b0*/ @!P0 IMAD.MOV R6, RZ, RZ, -R6 ; /* 0x000000ffff068224 */
/* 0x000fe200078e0a06 */
/*03c0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*03d0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe200078e00ff */
/*03e0*/ IADD3 R9, R10, R9, RZ ; /* 0x000000090a097210 */
/* 0x000fe40007ffe0ff */
/*03f0*/ @!P4 LOP3.LUT R6, RZ, R3, RZ, 0x33, !PT ; /* 0x00000003ff06c212 */
/* 0x000fca00078e33ff */
/*0400*/ IMAD R13, R2, R6, R9 ; /* 0x00000006020d7224 */
/* 0x000fc800078e0209 */
/*0410*/ IMAD.WIDE R8, R13.reuse, R4, c[0x0][0x168] ; /* 0x00005a000d087625 */
/* 0x040fe200078e0204 */
/*0420*/ IADD3 R7, R13, 0x1, RZ ; /* 0x000000010d077810 */
/* 0x000fc60007ffe0ff */
/*0430*/ IMAD.WIDE R12, R13, R4.reuse, c[0x0][0x170] ; /* 0x00005c000d0c7625 */
/* 0x080fe200078e0204 */
/*0440*/ LDG.E R11, [R8.64+0x4] ; /* 0x00000406080b7981 */
/* 0x0000a6000c1e1900 */
/*0450*/ IMAD.WIDE R2, R7, R4, c[0x0][0x178] ; /* 0x00005e0007027625 */
/* 0x000fe200078e0204 */
/*0460*/ LDG.E R6, [R12.64+0x4] ; /* 0x000004060c067981 */
/* 0x000ee8000c1e1900 */
/*0470*/ LDG.E R16, [R2.64] ; /* 0x0000000602107981 */
/* 0x000328000c1e1900 */
/*0480*/ @!P0 LDG.E R17, [R8.64] ; /* 0x0000000608118981 */
/* 0x000168000c1e1900 */
/*0490*/ @!P0 LDG.E R18, [R12.64] ; /* 0x000000060c128981 */
/* 0x000f62000c1e1900 */
/*04a0*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*04b0*/ IMAD.SHL.U32 R5, R0, 0x4, RZ ; /* 0x0000000400057824 */
/* 0x000fe200078e00ff */
/*04c0*/ USHF.L.U32 UR4, UR4, 0x2, URZ ; /* 0x0000000204047899 */
/* 0x000fe2000800063f */
/*04d0*/ SHF.R.S32.HI R14, RZ, 0x1f, R7 ; /* 0x0000001fff0e7819 */
/* 0x000fc80000011407 */
/*04e0*/ SHF.L.U64.HI R8, R7, 0x2, R14 ; /* 0x0000000207087819 */
/* 0x001fe4000001020e */
/*04f0*/ MOV R10, UR4 ; /* 0x00000004000a7c02 */
/* 0x000fc80008000f00 */
/*0500*/ IADD3 R19, R10, 0x4, R5 ; /* 0x000000040a137810 */
/* 0x000fe20007ffe005 */
/*0510*/ IMAD.SHL.U32 R10, R7.reuse, 0x4, RZ ; /* 0x00000004070a7824 */
/* 0x040fe200078e00ff */
/*0520*/ IADD3 R5, R7, -c[0x0][0x164], RZ ; /* 0x8000590007057a10 */
/* 0x000fc80007ffe0ff */
/*0530*/ IADD3 R2, P1, R10, c[0x0][0x180], RZ ; /* 0x000060000a027a10 */
/* 0x002fe20007f3e0ff */
/*0540*/ IMAD.WIDE R14, R5, R4, c[0x0][0x178] ; /* 0x00005e00050e7625 */
/* 0x000fc600078e0204 */
/*0550*/ IADD3.X R3, R8, c[0x0][0x184], RZ, P1, !PT ; /* 0x0000610008037a10 */
/* 0x000fe20000ffe4ff */
/*0560*/ STS [R0.X4+0x4], R11 ; /* 0x0000040b00007388 */
/* 0x004fe80000004800 */
/*0570*/ STS [R19+0x4], R6 ; /* 0x0000040613007388 */
/* 0x008fe80000000800 */
/*0580*/ STS [R19+UR4+0x4], R16 ; /* 0x0000041013007988 */
/* 0x010fe80008000804 */
/*0590*/ @!P0 STS [RZ], R17 ; /* 0x00000011ff008388 */
/* 0x020fe80000000800 */
/*05a0*/ @!P0 STS [UR4+0x4], R18 ; /* 0x00000412ff008988 */
/* 0x000fe80008000804 */
/*05b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*05c0*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000ea8000c1e1900 */
/*05d0*/ LDG.E R12, [R2.64] ; /* 0x00000006020c7981 */
/* 0x000ee8000c1e1900 */
/*05e0*/ LDS R11, [R19+UR4+0x4] ; /* 0x00000404130b7984 */
/* 0x000ea80008000800 */
/*05f0*/ LDS R9, [R19+0x4] ; /* 0x0000040013097984 */
/* 0x000e280000000800 */
/*0600*/ LDS R21, [R19] ; /* 0x0000000013157984 */
/* 0x000e680000000800 */
/*0610*/ LDS R19, [R0.X4] ; /* 0x0000000000137984 */
/* 0x000fe20000004800 */
/*0620*/ FADD R6, -R14, R11 ; /* 0x0000000b0e067221 */
/* 0x004fe20000000100 */
/*0630*/ IADD3 R14, RZ, -c[0x0][0x164], RZ ; /* 0x80005900ff0e7a10 */
/* 0x000fc60007ffe0ff */
/*0640*/ FADD R6, R6, -R9 ; /* 0x8000000906067221 */
/* 0x001fe20000000000 */
/*0650*/ F2F.F64.F32 R12, R12 ; /* 0x0000000c000c7310 */
/* 0x008fe60000201800 */
/*0660*/ FADD R21, R6, R21 ; /* 0x0000001506157221 */
/* 0x002fe20000000000 */
/*0670*/ IADD3 R6, P0, R10, c[0x0][0x188], RZ ; /* 0x000062000a067a10 */
/* 0x000fc80007f1e0ff */
/*0680*/ F2F.F64.F32 R16, R21 ; /* 0x0000001500107310 */
/* 0x000e240000201800 */
/*0690*/ DFMA R16, R16, -0.5, R12 ; /* 0xbfe000001010782b */
/* 0x001064000000000c */
/*06a0*/ IMAD R13, R14, c[0x0][0x160], R7 ; /* 0x000058000e0d7a24 */
/* 0x001fe200078e0207 */
/*06b0*/ IADD3.X R7, R8, c[0x0][0x18c], RZ, P0, !PT ; /* 0x0000630008077a10 */
/* 0x000fe200007fe4ff */
/*06c0*/ LDS R12, [R0.X4+0x4] ; /* 0x00000400000c7984 */
/* 0x000e240000004800 */
/*06d0*/ F2F.F32.F64 R23, R16 ; /* 0x0000001000177310 */
/* 0x002e620000301000 */
/*06e0*/ IMAD.WIDE R14, R13, R4, c[0x0][0x178] ; /* 0x00005e000d0e7625 */
/* 0x000fe200078e0204 */
/*06f0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0023ea000c101906 */
/*0700*/ LDG.E R15, [R14.64] ; /* 0x000000060e0f7981 */
/* 0x000ea8000c1e1900 */
/*0710*/ LDG.E R18, [R6.64] ; /* 0x0000000606127981 */
/* 0x000ee2000c1e1900 */
/*0720*/ FADD R16, -R19, R12 ; /* 0x0000000c13107221 */
/* 0x001fc80000000100 */
/*0730*/ FADD R16, -R11, R16 ; /* 0x000000100b107221 */
/* 0x000fe40000000100 */
/*0740*/ IMAD.WIDE R2, R13, R4, c[0x0][0x170] ; /* 0x00005c000d027625 */
/* 0x002fe200078e0204 */
/*0750*/ IADD3 R10, P0, R10, c[0x0][0x190], RZ ; /* 0x000064000a0a7a10 */
/* 0x000fc60007f1e0ff */
/*0760*/ IMAD.WIDE R4, R5, R4, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fe200078e0204 */
/*0770*/ IADD3.X R11, R8, c[0x0][0x194], RZ, P0, !PT ; /* 0x00006500080b7a10 */
/* 0x000fc600007fe4ff */
/*0780*/ FADD R20, R16, R15 ; /* 0x0000000f10147221 */
/* 0x004fe20000000000 */
/*0790*/ F2F.F64.F32 R18, R18 ; /* 0x0000001200127310 */
/* 0x008ff00000201800 */
/*07a0*/ F2F.F64.F32 R16, R20 ; /* 0x0000001400107310 */
/* 0x000e240000201800 */
/*07b0*/ DFMA R16, R16, -0.5, R18 ; /* 0xbfe000001010782b */
/* 0x001e140000000012 */
/*07c0*/ F2F.F32.F64 R17, R16 ; /* 0x0000001000117310 */
/* 0x001e240000301000 */
/*07d0*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x001fe8000c101906 */
/*07e0*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea8000c1e1900 */
/*07f0*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ee8000c1e1900 */
/*0800*/ LDG.E R14, [R10.64] ; /* 0x000000060a0e7981 */
/* 0x000f22000c1e1900 */
/*0810*/ FADD R9, R9, -R2 ; /* 0x8000000209097221 */
/* 0x004fc80000000000 */
/*0820*/ FADD R9, -R12, R9 ; /* 0x000000090c097221 */
/* 0x000fc80000000100 */
/*0830*/ FADD R0, R9, R4 ; /* 0x0000000409007221 */
/* 0x008fe20000000000 */
/*0840*/ F2F.F64.F32 R14, R14 ; /* 0x0000000e000e7310 */
/* 0x010ff00000201800 */
/*0850*/ F2F.F64.F32 R8, R0 ; /* 0x0000000000087310 */
/* 0x000e240000201800 */
/*0860*/ DFMA R8, R8, -0.5, R14 ; /* 0xbfe000000808782b */
/* 0x001e14000000000e */
/*0870*/ F2F.F32.F64 R9, R8 ; /* 0x0000000800097310 */
/* 0x001e240000301000 */
/*0880*/ STG.E [R10.64], R9 ; /* 0x000000090a007986 */
/* 0x001fe2000c101906 */
/*0890*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08a0*/ BRA 0x8a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8update_eiiPfS_S_S_S_S_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R7, c[0x0][0x164] ; /* 0x0000590000077a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000002500 */
/*0040*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*0050*/ IADD3 R2, R7, -0x1, RZ ; /* 0xffffffff07027810 */
/* 0x000fe40007ffe0ff */
/*0060*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0070*/ IABS R8, R2 ; /* 0x0000000200087213 */
/* 0x000fe20000000000 */
/*0080*/ IMAD R3, R2.reuse, UR4, RZ ; /* 0x0000000402037c24 */
/* 0x040fe2000f8e02ff */
/*0090*/ ISETP.NE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f25270 */
/*00a0*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*00b0*/ I2F.RP R12, R8 ; /* 0x00000008000c7306 */
/* 0x000e620000209400 */
/*00c0*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*00d0*/ IABS R6, R3 ; /* 0x0000000300067213 */
/* 0x000fcc0000000000 */
/*00e0*/ I2F.RP R13, R6 ; /* 0x00000006000d7306 */
/* 0x000eb00000209400 */
/*00f0*/ MUFU.RCP R12, R12 ; /* 0x0000000c000c7308 */
/* 0x002e620000001000 */
/*0100*/ IMAD R9, R9, c[0x0][0x0], R0 ; /* 0x0000000009097a24 */
/* 0x001fce00078e0200 */
/*0110*/ MUFU.RCP R13, R13 ; /* 0x0000000d000d7308 */
/* 0x004e220000001000 */
/*0120*/ IADD3 R10, R12, 0xffffffe, RZ ; /* 0x0ffffffe0c0a7810 */
/* 0x002fe40007ffe0ff */
/*0130*/ IABS R12, R9 ; /* 0x00000009000c7213 */
/* 0x000fca0000000000 */
/*0140*/ F2I.FTZ.U32.TRUNC.NTZ R11, R10 ; /* 0x0000000a000b7305 */
/* 0x0002a2000021f000 */
/*0150*/ IADD3 R4, R13, 0xffffffe, RZ ; /* 0x0ffffffe0d047810 */
/* 0x001fce0007ffe0ff */
/*0160*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x0000e2000021f000 */
/*0170*/ HFMA2.MMA R10, -RZ, RZ, 0, 0 ; /* 0x00000000ff0a7435 */
/* 0x002fe200000001ff */
/*0180*/ IADD3 R15, RZ, -R11, RZ ; /* 0x8000000bff0f7210 */
/* 0x004fe20007ffe0ff */
/*0190*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fc800078e00ff */
/*01a0*/ IMAD R13, R15, R8, RZ ; /* 0x000000080f0d7224 */
/* 0x000fe200078e02ff */
/*01b0*/ IADD3 R14, RZ, -R5, RZ ; /* 0x80000005ff0e7210 */
/* 0x008fc60007ffe0ff */
/*01c0*/ IMAD.HI.U32 R10, R11, R13, R10 ; /* 0x0000000d0b0a7227 */
/* 0x000fe200078e000a */
/*01d0*/ MOV R11, R12 ; /* 0x0000000c000b7202 */
/* 0x000fe40000000f00 */
/*01e0*/ MOV R15, R14 ; /* 0x0000000e000f7202 */
/* 0x000fe40000000f00 */
/*01f0*/ IABS R14, R2 ; /* 0x00000002000e7213 */
/* 0x000fe20000000000 */
/*0200*/ IMAD.HI.U32 R10, R10, R11, RZ ; /* 0x0000000b0a0a7227 */
/* 0x000fe200078e00ff */
/*0210*/ IABS R12, R3 ; /* 0x00000003000c7213 */
/* 0x000fe40000000000 */
/*0220*/ IADD3 R14, RZ, -R14, RZ ; /* 0x8000000eff0e7210 */
/* 0x000fe20007ffe0ff */
/*0230*/ IMAD R13, R15, R6, RZ ; /* 0x000000060f0d7224 */
/* 0x000fe200078e02ff */
/*0240*/ IADD3 R12, RZ, -R12, RZ ; /* 0x8000000cff0c7210 */
/* 0x000fc60007ffe0ff */
/*0250*/ IMAD.HI.U32 R4, R5, R13, R4 ; /* 0x0000000d05047227 */
/* 0x000fe200078e0004 */
/*0260*/ MOV R5, R14 ; /* 0x0000000e00057202 */
/* 0x000fca0000000f00 */
/*0270*/ IMAD R5, R10, R5, R11 ; /* 0x000000050a057224 */
/* 0x000fe400078e020b */
/*0280*/ IMAD.HI.U32 R4, R4, R11, RZ ; /* 0x0000000b04047227 */
/* 0x000fc600078e00ff */
/*0290*/ ISETP.GT.U32.AND P0, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x000fe20003f04070 */
/*02a0*/ IMAD R11, R4, R12, R11 ; /* 0x0000000c040b7224 */
/* 0x000fca00078e020b */
/*02b0*/ ISETP.GT.U32.AND P4, PT, R6, R11, PT ; /* 0x0000000b0600720c */
/* 0x000fce0003f84070 */
/*02c0*/ @!P0 IADD3 R5, R5, -R8.reuse, RZ ; /* 0x8000000805058210 */
/* 0x080fe40007ffe0ff */
/*02d0*/ @!P0 IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a8810 */
/* 0x000fe40007ffe0ff */
/*02e0*/ ISETP.GE.U32.AND P5, PT, R5, R8, PT ; /* 0x000000080500720c */
/* 0x000fe40003fa6070 */
/*02f0*/ @!P4 IADD3 R11, R11, -R6, RZ ; /* 0x800000060b0bc210 */
/* 0x000fe40007ffe0ff */
/*0300*/ LOP3.LUT R5, R9, R2, RZ, 0x3c, !PT ; /* 0x0000000209057212 */
/* 0x000fe400078e3cff */
/*0310*/ ISETP.GE.U32.AND P3, PT, R11, R6, PT ; /* 0x000000060b00720c */
/* 0x000fc40003f66070 */
/*0320*/ LOP3.LUT R6, R9, R3, RZ, 0x3c, !PT ; /* 0x0000000309067212 */
/* 0x000fe400078e3cff */
/*0330*/ ISETP.GE.AND P2, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f46270 */
/*0340*/ ISETP.GE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f06270 */
/*0350*/ @!P4 IADD3 R4, R4, 0x1, RZ ; /* 0x000000010404c810 */
/* 0x000fe40007ffe0ff */
/*0360*/ ISETP.NE.AND P4, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe40003f85270 */
/*0370*/ @P5 IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a5810 */
/* 0x000fc40007ffe0ff */
/*0380*/ IADD3 R6, R9, c[0x0][0x164], RZ ; /* 0x0000590009067a10 */
/* 0x000fe40007ffe0ff */
/*0390*/ @P3 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104043810 */
/* 0x000fe20007ffe0ff */
/*03a0*/ @!P2 IMAD.MOV R10, RZ, RZ, -R10 ; /* 0x000000ffff0aa224 */
/* 0x000fe200078e0a0a */
/*03b0*/ @!P1 LOP3.LUT R10, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff0a9212 */
/* 0x000fe200078e33ff */
/*03c0*/ IMAD R6, R7, c[0x0][0x160], R6 ; /* 0x0000580007067a24 */
/* 0x000fe200078e0206 */
/*03d0*/ @!P0 IADD3 R4, -R4, RZ, RZ ; /* 0x000000ff04048210 */
/* 0x000fe40007ffe1ff */
/*03e0*/ ISETP.NE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fe2000bf05270 */
/*03f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0400*/ IADD3 R5, R10, R6, RZ ; /* 0x000000060a057210 */
/* 0x000fe20007ffe0ff */
/*0410*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x000fe200000001ff */
/*0420*/ @!P4 LOP3.LUT R4, RZ, R3, RZ, 0x33, !PT ; /* 0x00000003ff04c212 */
/* 0x000fca00078e33ff */
/*0430*/ IMAD R5, R2, R4, R5 ; /* 0x0000000402057224 */
/* 0x000fca00078e0205 */
/*0440*/ IADD3 R9, R5, 0x1, RZ ; /* 0x0000000105097810 */
/* 0x000fca0007ffe0ff */
/*0450*/ IMAD.WIDE R2, R9, R6, c[0x0][0x180] ; /* 0x0000600009027625 */
/* 0x000fc800078e0206 */
/*0460*/ IMAD.WIDE R4, R9.reuse, R6.reuse, c[0x0][0x188] ; /* 0x0000620009047625 */
/* 0x0c0fe200078e0206 */
/*0470*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000ea6000c1e1900 */
/*0480*/ IMAD.WIDE R10, R9, R6, c[0x0][0x190] ; /* 0x00006400090a7625 */
/* 0x000fe200078e0206 */
/*0490*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ee8000c1e1900 */
/*04a0*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f28000c1e1900 */
/*04b0*/ @!P0 LDG.E R21, [R2.64+0x4] ; /* 0x0000040402158981 */
/* 0x000f68000c1e1900 */
/*04c0*/ @!P0 LDG.E R22, [R4.64+0x4] ; /* 0x0000040404168981 */
/* 0x000f62000c1e1900 */
/*04d0*/ SHF.L.U32 R13, R0, 0x2, RZ ; /* 0x00000002000d7819 */
/* 0x000fca00000006ff */
/*04e0*/ IMAD R23, R6, c[0x0][0x0], R13 ; /* 0x0000000006177a24 */
/* 0x000fc800078e020d */
/*04f0*/ IMAD R25, R6, c[0x0][0x0], R23 ; /* 0x0000000006197a24 */
/* 0x000fe400078e0217 */
/*0500*/ IMAD.WIDE R18, R7, 0x4, R10 ; /* 0x0000000407127825 */
/* 0x000fc800078e020a */
/*0510*/ IMAD.WIDE R16, R9, R6, c[0x0][0x198] ; /* 0x0000660009107625 */
/* 0x000fc800078e0206 */
/*0520*/ IMAD.WIDE R12, R9, R6, c[0x0][0x168] ; /* 0x00005a00090c7625 */
/* 0x000fe200078e0206 */
/*0530*/ STS [R0.X4], R15 ; /* 0x0000000f00007388 */
/* 0x004fe80000004800 */
/*0540*/ STS [R23+0x4], R8 ; /* 0x0000040817007388 */
/* 0x008fe80000000800 */
/*0550*/ STS [R25+0x8], R20 ; /* 0x0000081419007388 */
/* 0x010fe80000000800 */
/*0560*/ @!P0 STS [R0.X4+0x4], R21 ; /* 0x0000041500008388 */
/* 0x020fe80000004800 */
/*0570*/ @!P0 STS [R23+0x8], R22 ; /* 0x0000081617008388 */
/* 0x000fe80000000800 */
/*0580*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0590*/ LDG.E R19, [R18.64] ; /* 0x0000000412137981 */
/* 0x000ea8000c1e1900 */
/*05a0*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x0000e8000c1e1900 */
/*05b0*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000ee8000c1e1900 */
/*05c0*/ LDS R14, [R25+0x8] ; /* 0x00000800190e7984 */
/* 0x000ea80000000800 */
/*05d0*/ LDS R24, [R23+0x8] ; /* 0x0000080017187984 */
/* 0x000e680000000800 */
/*05e0*/ LDS R8, [R23+0x4] ; /* 0x0000040017087984 */
/* 0x000f280000000800 */
/*05f0*/ LDS R16, [R0.X4] ; /* 0x0000000000107984 */
/* 0x001fe20000004800 */
/*0600*/ FADD R15, -R14, R19 ; /* 0x000000130e0f7221 */
/* 0x004fc80000000100 */
/*0610*/ FADD R15, R15, -R24 ; /* 0x800000180f0f7221 */
/* 0x002fc80000000000 */
/*0620*/ FADD R20, R15, R8 ; /* 0x000000080f147221 */
/* 0x010fe40000000000 */
/*0630*/ IMAD R15, R7, c[0x0][0x160], RZ ; /* 0x00005800070f7a24 */
/* 0x000fe400078e02ff */
/*0640*/ FFMA R27, R20, R17, R26 ; /* 0x00000011141b7223 */
/* 0x008fe4000000001a */
/*0650*/ IMAD.WIDE R20, R15, 0x4, R10 ; /* 0x000000040f147825 */
/* 0x000fe200078e020a */
/*0660*/ LDS R17, [R0.X4+0x4] ; /* 0x0000040000117984 */
/* 0x000e280000004800 */
/*0670*/ STG.E [R12.64], R27 ; /* 0x0000001b0c007986 */
/* 0x0003e2000c101904 */
/*0680*/ IMAD.WIDE R18, R9, R6, c[0x0][0x1a0] ; /* 0x0000680009127625 */
/* 0x000fc600078e0206 */
/*0690*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ea2000c1e1900 */
/*06a0*/ IMAD.WIDE R10, R9, R6, c[0x0][0x170] ; /* 0x00005c00090a7625 */
/* 0x000fc600078e0206 */
/*06b0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ee8000c1e1900 */
/*06c0*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x000ee2000c1e1900 */
/*06d0*/ IMAD.WIDE R4, R15, 0x4, R4 ; /* 0x000000040f047825 */
/* 0x000fc800078e0204 */
/*06e0*/ IMAD.WIDE R12, R7, 0x4, R2 ; /* 0x00000004070c7825 */
/* 0x002fc800078e0202 */
/*06f0*/ FADD R17, -R16, R17 ; /* 0x0000001110117221 */
/* 0x001fe40000000100 */
/*0700*/ IMAD.WIDE R2, R9, R6, c[0x0][0x1a8] ; /* 0x00006a0009027625 */
/* 0x000fc800078e0206 */
/*0710*/ IMAD.WIDE R6, R9, R6, c[0x0][0x178] ; /* 0x00005e0009067625 */
/* 0x000fc800078e0206 */
/*0720*/ FADD R17, R17, -R20 ; /* 0x8000001411117221 */
/* 0x004fc80000000000 */
/*0730*/ FADD R17, R14, R17 ; /* 0x000000110e117221 */
/* 0x000fc80000000000 */
/*0740*/ FFMA R17, R17, R18, R22 ; /* 0x0000001211117223 */
/* 0x008fca0000000016 */
/*0750*/ STG.E [R10.64], R17 ; /* 0x000000110a007986 */
/* 0x000fe8000c101904 */
/*0760*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0770*/ LDG.E R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000ee8000c1e1900 */
/*0780*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000f28000c1e1900 */
/*0790*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */
/* 0x000f22000c1e1900 */
/*07a0*/ FADD R8, -R8, R5 ; /* 0x0000000508087221 */
/* 0x004fc80000000100 */
/*07b0*/ FADD R9, R8, -R13 ; /* 0x8000000d08097221 */
/* 0x008fc80000000000 */
/*07c0*/ FADD R9, R16, R9 ; /* 0x0000000910097221 */
/* 0x000fc80000000000 */
/*07d0*/ FFMA R9, R9, R2, R0 ; /* 0x0000000209097223 */
/* 0x010fca0000000000 */
/*07e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*07f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0800*/ BRA 0x800; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void update_e( int Ny, int Nz, float *Ex, float *Ey, float *Ez, float *Hx, float *Hy, float *Hz, float *CEx, float *CEy, float *CEz ) {
int tk = threadIdx.x;
int idx = blockIdx.x*blockDim.x + tk;
int Nyz = Ny*Nz;
//int fidx = idx + idx/(Nz-1) + Nyz + Nz + 1;
int fidx = idx + idx/(Nz-1) + idx/( (Nz-1)*(Ny-1) )*(Nz-1) + Nyz + Nz + 1;
extern __shared__ float hs[];
float* hx = (float*) hs;
float* hy = (float*) &hx[blockDim.x+1];
float* hz = (float*) &hy[blockDim.x+1];
hx[tk] = Hx[fidx];
hy[tk] = Hy[fidx];
hz[tk] = Hz[fidx];
if ( tk==blockDim.x-1 ) {
hx[tk+1] = Hx[fidx+1];
hy[tk+1] = Hy[fidx+1];
}
__syncthreads();
Ex[fidx] += CEx[fidx]*( Hz[fidx+Nz] - hz[tk] - hy[tk+1] + hy[tk] );
Ey[fidx] += CEy[fidx]*( hx[tk+1] - hx[tk] - Hz[fidx+Nyz] + hz[tk] );
Ez[fidx] += CEz[fidx]*( Hy[fidx+Nyz] - hy[tk] - Hx[fidx+Nz] + hx[tk] );
}
__global__ void update_h( int Ny, int Nz, float *Ex, float *Ey, float *Ez, float *Hx, float *Hy, float *Hz ) {
int tk = threadIdx.x;
int idx = blockIdx.x*blockDim.x + tk;
int Nyz = Ny*Nz;
//int fidx = idx + idx/(Nz-1) + Nyz + Nz + 1;
int fidx = idx + idx/(Nz-1) + idx/( (Nz-1)*(Ny-1) )*(Nz-1) + Nyz + Nz + 1;
extern __shared__ float es[];
float* ex = (float*) es;
float* ey = (float*) &ex[blockDim.x+1];
float* ez = (float*) &ey[blockDim.x+1];
ex[tk+1] = Ex[fidx];
ey[tk+1] = Ey[fidx];
ez[tk] = Ez[fidx];
if ( tk==0 ) {
ex[0] = Ex[fidx-1];
ey[0] = Ey[fidx-1];
}
__syncthreads();
Hx[fidx] -= 0.5*( ez[tk] - Ez[fidx-Nz] - ey[tk+1] + ey[tk] );
Hy[fidx] -= 0.5*( ex[tk+1] - ex[tk] - ez[tk] + Ez[fidx-Nyz] );
Hz[fidx] -= 0.5*( ey[tk+1] - Ey[fidx-Nyz] - ex[tk+1] + Ex[fidx-Nz] );
} | .file "tmpxft_00041623_00000000-6_non_aligned-Nx+1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z8update_eiiPfS_S_S_S_S_S_S_S_iiPfS_S_S_S_S_S_S_S_
.type _Z45__device_stub__Z8update_eiiPfS_S_S_S_S_S_S_S_iiPfS_S_S_S_S_S_S_S_, @function
_Z45__device_stub__Z8update_eiiPfS_S_S_S_S_S_S_S_iiPfS_S_S_S_S_S_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movl %edi, 76(%rsp)
movl %esi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
movq %r8, 48(%rsp)
movq %r9, 40(%rsp)
movq 256(%rsp), %rax
movq %rax, 32(%rsp)
movq 264(%rsp), %rax
movq %rax, 24(%rsp)
movq 272(%rsp), %rax
movq %rax, 16(%rsp)
movq 280(%rsp), %rax
movq %rax, 8(%rsp)
movq 288(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 76(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rax
movq %rax, 176(%rsp)
leaq 40(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rax
movq %rax, 192(%rsp)
leaq 24(%rsp), %rax
movq %rax, 200(%rsp)
leaq 16(%rsp), %rax
movq %rax, 208(%rsp)
leaq 8(%rsp), %rax
movq %rax, 216(%rsp)
movq %rsp, %rax
movq %rax, 224(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 264
pushq 88(%rsp)
.cfi_def_cfa_offset 272
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z8update_eiiPfS_S_S_S_S_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z8update_eiiPfS_S_S_S_S_S_S_S_iiPfS_S_S_S_S_S_S_S_, .-_Z45__device_stub__Z8update_eiiPfS_S_S_S_S_S_S_S_iiPfS_S_S_S_S_S_S_S_
.globl _Z8update_eiiPfS_S_S_S_S_S_S_S_
.type _Z8update_eiiPfS_S_S_S_S_S_S_S_, @function
_Z8update_eiiPfS_S_S_S_S_S_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 56(%rsp)
.cfi_def_cfa_offset 32
pushq 56(%rsp)
.cfi_def_cfa_offset 40
pushq 56(%rsp)
.cfi_def_cfa_offset 48
pushq 56(%rsp)
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z45__device_stub__Z8update_eiiPfS_S_S_S_S_S_S_S_iiPfS_S_S_S_S_S_S_S_
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8update_eiiPfS_S_S_S_S_S_S_S_, .-_Z8update_eiiPfS_S_S_S_S_S_S_S_
.globl _Z39__device_stub__Z8update_hiiPfS_S_S_S_S_iiPfS_S_S_S_S_
.type _Z39__device_stub__Z8update_hiiPfS_S_S_S_S_iiPfS_S_S_S_S_, @function
_Z39__device_stub__Z8update_hiiPfS_S_S_S_S_iiPfS_S_S_S_S_:
.LFB2053:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edi, 60(%rsp)
movl %esi, 56(%rsp)
movq %rdx, 48(%rsp)
movq %rcx, 40(%rsp)
movq %r8, 32(%rsp)
movq %r9, 24(%rsp)
movq 224(%rsp), %rax
movq %rax, 16(%rsp)
movq 232(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z8update_hiiPfS_S_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z39__device_stub__Z8update_hiiPfS_S_S_S_S_iiPfS_S_S_S_S_, .-_Z39__device_stub__Z8update_hiiPfS_S_S_S_S_iiPfS_S_S_S_S_
.globl _Z8update_hiiPfS_S_S_S_S_
.type _Z8update_hiiPfS_S_S_S_S_, @function
_Z8update_hiiPfS_S_S_S_S_:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 24(%rsp)
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z39__device_stub__Z8update_hiiPfS_S_S_S_S_iiPfS_S_S_S_S_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z8update_hiiPfS_S_S_S_S_, .-_Z8update_hiiPfS_S_S_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8update_hiiPfS_S_S_S_S_"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z8update_eiiPfS_S_S_S_S_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8update_hiiPfS_S_S_S_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z8update_eiiPfS_S_S_S_S_S_S_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void update_e( int Ny, int Nz, float *Ex, float *Ey, float *Ez, float *Hx, float *Hy, float *Hz, float *CEx, float *CEy, float *CEz ) {
int tk = threadIdx.x;
int idx = blockIdx.x*blockDim.x + tk;
int Nyz = Ny*Nz;
//int fidx = idx + idx/(Nz-1) + Nyz + Nz + 1;
int fidx = idx + idx/(Nz-1) + idx/( (Nz-1)*(Ny-1) )*(Nz-1) + Nyz + Nz + 1;
extern __shared__ float hs[];
float* hx = (float*) hs;
float* hy = (float*) &hx[blockDim.x+1];
float* hz = (float*) &hy[blockDim.x+1];
hx[tk] = Hx[fidx];
hy[tk] = Hy[fidx];
hz[tk] = Hz[fidx];
if ( tk==blockDim.x-1 ) {
hx[tk+1] = Hx[fidx+1];
hy[tk+1] = Hy[fidx+1];
}
__syncthreads();
Ex[fidx] += CEx[fidx]*( Hz[fidx+Nz] - hz[tk] - hy[tk+1] + hy[tk] );
Ey[fidx] += CEy[fidx]*( hx[tk+1] - hx[tk] - Hz[fidx+Nyz] + hz[tk] );
Ez[fidx] += CEz[fidx]*( Hy[fidx+Nyz] - hy[tk] - Hx[fidx+Nz] + hx[tk] );
}
__global__ void update_h( int Ny, int Nz, float *Ex, float *Ey, float *Ez, float *Hx, float *Hy, float *Hz ) {
int tk = threadIdx.x;
int idx = blockIdx.x*blockDim.x + tk;
int Nyz = Ny*Nz;
//int fidx = idx + idx/(Nz-1) + Nyz + Nz + 1;
int fidx = idx + idx/(Nz-1) + idx/( (Nz-1)*(Ny-1) )*(Nz-1) + Nyz + Nz + 1;
extern __shared__ float es[];
float* ex = (float*) es;
float* ey = (float*) &ex[blockDim.x+1];
float* ez = (float*) &ey[blockDim.x+1];
ex[tk+1] = Ex[fidx];
ey[tk+1] = Ey[fidx];
ez[tk] = Ez[fidx];
if ( tk==0 ) {
ex[0] = Ex[fidx-1];
ey[0] = Ey[fidx-1];
}
__syncthreads();
Hx[fidx] -= 0.5*( ez[tk] - Ez[fidx-Nz] - ey[tk+1] + ey[tk] );
Hy[fidx] -= 0.5*( ex[tk+1] - ex[tk] - ez[tk] + Ez[fidx-Nyz] );
Hz[fidx] -= 0.5*( ey[tk+1] - Ey[fidx-Nyz] - ex[tk+1] + Ex[fidx-Nz] );
} | #include <hip/hip_runtime.h>
__global__ void update_e( int Ny, int Nz, float *Ex, float *Ey, float *Ez, float *Hx, float *Hy, float *Hz, float *CEx, float *CEy, float *CEz ) {
int tk = threadIdx.x;
int idx = blockIdx.x*blockDim.x + tk;
int Nyz = Ny*Nz;
//int fidx = idx + idx/(Nz-1) + Nyz + Nz + 1;
int fidx = idx + idx/(Nz-1) + idx/( (Nz-1)*(Ny-1) )*(Nz-1) + Nyz + Nz + 1;
extern __shared__ float hs[];
float* hx = (float*) hs;
float* hy = (float*) &hx[blockDim.x+1];
float* hz = (float*) &hy[blockDim.x+1];
hx[tk] = Hx[fidx];
hy[tk] = Hy[fidx];
hz[tk] = Hz[fidx];
if ( tk==blockDim.x-1 ) {
hx[tk+1] = Hx[fidx+1];
hy[tk+1] = Hy[fidx+1];
}
__syncthreads();
Ex[fidx] += CEx[fidx]*( Hz[fidx+Nz] - hz[tk] - hy[tk+1] + hy[tk] );
Ey[fidx] += CEy[fidx]*( hx[tk+1] - hx[tk] - Hz[fidx+Nyz] + hz[tk] );
Ez[fidx] += CEz[fidx]*( Hy[fidx+Nyz] - hy[tk] - Hx[fidx+Nz] + hx[tk] );
}
__global__ void update_h( int Ny, int Nz, float *Ex, float *Ey, float *Ez, float *Hx, float *Hy, float *Hz ) {
int tk = threadIdx.x;
int idx = blockIdx.x*blockDim.x + tk;
int Nyz = Ny*Nz;
//int fidx = idx + idx/(Nz-1) + Nyz + Nz + 1;
int fidx = idx + idx/(Nz-1) + idx/( (Nz-1)*(Ny-1) )*(Nz-1) + Nyz + Nz + 1;
extern __shared__ float es[];
float* ex = (float*) es;
float* ey = (float*) &ex[blockDim.x+1];
float* ez = (float*) &ey[blockDim.x+1];
ex[tk+1] = Ex[fidx];
ey[tk+1] = Ey[fidx];
ez[tk] = Ez[fidx];
if ( tk==0 ) {
ex[0] = Ex[fidx-1];
ey[0] = Ey[fidx-1];
}
__syncthreads();
Hx[fidx] -= 0.5*( ez[tk] - Ez[fidx-Nz] - ey[tk+1] + ey[tk] );
Hy[fidx] -= 0.5*( ex[tk+1] - ex[tk] - ez[tk] + Ez[fidx-Nyz] );
Hz[fidx] -= 0.5*( ey[tk+1] - Ey[fidx-Nyz] - ex[tk+1] + Ex[fidx-Nz] );
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void update_e( int Ny, int Nz, float *Ex, float *Ey, float *Ez, float *Hx, float *Hy, float *Hz, float *CEx, float *CEy, float *CEz ) {
int tk = threadIdx.x;
int idx = blockIdx.x*blockDim.x + tk;
int Nyz = Ny*Nz;
//int fidx = idx + idx/(Nz-1) + Nyz + Nz + 1;
int fidx = idx + idx/(Nz-1) + idx/( (Nz-1)*(Ny-1) )*(Nz-1) + Nyz + Nz + 1;
extern __shared__ float hs[];
float* hx = (float*) hs;
float* hy = (float*) &hx[blockDim.x+1];
float* hz = (float*) &hy[blockDim.x+1];
hx[tk] = Hx[fidx];
hy[tk] = Hy[fidx];
hz[tk] = Hz[fidx];
if ( tk==blockDim.x-1 ) {
hx[tk+1] = Hx[fidx+1];
hy[tk+1] = Hy[fidx+1];
}
__syncthreads();
Ex[fidx] += CEx[fidx]*( Hz[fidx+Nz] - hz[tk] - hy[tk+1] + hy[tk] );
Ey[fidx] += CEy[fidx]*( hx[tk+1] - hx[tk] - Hz[fidx+Nyz] + hz[tk] );
Ez[fidx] += CEz[fidx]*( Hy[fidx+Nyz] - hy[tk] - Hx[fidx+Nz] + hx[tk] );
}
__global__ void update_h( int Ny, int Nz, float *Ex, float *Ey, float *Ez, float *Hx, float *Hy, float *Hz ) {
int tk = threadIdx.x;
int idx = blockIdx.x*blockDim.x + tk;
int Nyz = Ny*Nz;
//int fidx = idx + idx/(Nz-1) + Nyz + Nz + 1;
int fidx = idx + idx/(Nz-1) + idx/( (Nz-1)*(Ny-1) )*(Nz-1) + Nyz + Nz + 1;
extern __shared__ float es[];
float* ex = (float*) es;
float* ey = (float*) &ex[blockDim.x+1];
float* ez = (float*) &ey[blockDim.x+1];
ex[tk+1] = Ex[fidx];
ey[tk+1] = Ey[fidx];
ez[tk] = Ez[fidx];
if ( tk==0 ) {
ex[0] = Ex[fidx-1];
ey[0] = Ey[fidx-1];
}
__syncthreads();
Hx[fidx] -= 0.5*( ez[tk] - Ez[fidx-Nz] - ey[tk+1] + ey[tk] );
Hy[fidx] -= 0.5*( ex[tk+1] - ex[tk] - ez[tk] + Ez[fidx-Nyz] );
Hz[fidx] -= 0.5*( ey[tk+1] - Ey[fidx-Nyz] - ex[tk+1] + Ex[fidx-Nz] );
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8update_eiiPfS_S_S_S_S_S_S_S_
.globl _Z8update_eiiPfS_S_S_S_S_S_S_S_
.p2align 8
.type _Z8update_eiiPfS_S_S_S_S_S_S_S_,@function
_Z8update_eiiPfS_S_S_S_S_S_S_S_:
s_clause 0x2
s_load_b64 s[8:9], s[0:1], 0x0
s_load_b128 s[4:7], s[0:1], 0x20
s_load_b32 s11, s[0:1], 0x5c
s_waitcnt lgkmcnt(0)
s_add_i32 s3, s9, -1
s_add_i32 s2, s8, -1
s_ashr_i32 s12, s3, 31
s_mul_i32 s2, s3, s2
s_and_b32 s11, s11, 0xffff
s_ashr_i32 s10, s2, 31
s_mul_i32 s16, s9, s8
s_add_i32 s2, s2, s10
s_lshl_b32 s8, s11, 2
s_xor_b32 s13, s2, s10
s_add_i32 s2, s3, s12
v_cvt_f32_u32_e32 v1, s13
s_xor_b32 s14, s2, s12
s_sub_i32 s2, 0, s13
v_cvt_f32_u32_e32 v2, s14
s_add_i32 s17, s8, 0
v_rcp_iflag_f32_e32 v1, v1
s_add_i32 s17, s17, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_mul_f32_e32 v3, 0x4f7ffffe, v2
v_cvt_u32_f32_e32 v4, v1
v_mad_u64_u32 v[1:2], null, s15, s11, v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cvt_u32_f32_e32 v2, v3
s_add_i32 s11, s11, -1
v_mul_lo_u32 v3, s2, v4
s_sub_i32 s2, 0, s14
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v5, s2, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v6, 31, v1
v_mul_hi_u32 v3, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v7, v1, v6
v_mul_hi_u32 v5, v2, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_xor_b32_e32 v7, v7, v6
v_add_nc_u32_e32 v3, v4, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v2, v5
v_mul_hi_u32 v3, v7, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v2, v7, v2
v_mul_lo_u32 v4, v3, s13
v_add_nc_u32_e32 v8, 1, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_lo_u32 v5, v2, s14
v_sub_nc_u32_e32 v4, v7, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v5, v7, v5
v_add_nc_u32_e32 v7, 1, v2
v_subrev_nc_u32_e32 v9, s13, v4
v_cmp_le_u32_e32 vcc_lo, s13, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_le_u32_e64 s2, s14, v5
v_cndmask_b32_e32 v4, v4, v9, vcc_lo
v_xor_b32_e32 v9, s10, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v2, v2, v7, s2
v_cndmask_b32_e32 v3, v3, v8, vcc_lo
v_subrev_nc_u32_e32 v8, s14, v5
v_cmp_le_u32_e32 vcc_lo, s13, v4
v_xor_b32_e32 v4, s12, v6
v_cndmask_b32_e64 v5, v5, v8, s2
v_add_nc_u32_e32 v8, 1, v2
v_add_nc_u32_e32 v7, 1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v3, v3, v7, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s14, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_xor_b32_e32 v3, v3, v9
v_cndmask_b32_e32 v2, v2, v8, vcc_lo
v_sub_nc_u32_e32 v3, v3, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v2, v2, v4
v_mul_lo_u32 v3, v3, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v4
s_load_b64 s[2:3], s[0:1], 0x30
v_add3_u32 v2, s16, s9, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v5, v2, v1, v3
v_add_nc_u32_e32 v3, 1, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[1:2], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v8, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v2, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v10, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v11, vcc_lo, s3, v2, vcc_lo
global_load_b32 v6, v[6:7], off
global_load_b32 v9, v[8:9], off
global_load_b32 v10, v[10:11], off
v_lshlrev_b32_e32 v7, 2, v0
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v11, s17, s8, v7
v_add_nc_u32_e32 v4, 0, v7
v_add_nc_u32_e32 v7, s17, v7
s_mov_b32 s8, exec_lo
s_waitcnt vmcnt(2)
ds_store_b32 v4, v6
s_waitcnt vmcnt(1)
ds_store_b32 v7, v9
s_waitcnt vmcnt(0)
ds_store_b32 v11, v10 offset:4
v_add_nc_u32_e32 v8, 4, v11
v_cmpx_eq_u32_e64 s11, v0
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v9, vcc_lo, v5, 8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v6, vcc_lo
v_add_co_u32 v5, vcc_lo, s4, v9
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v10, vcc_lo
v_add_co_u32 v9, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
global_load_b32 v5, v[5:6], off
global_load_b32 v6, v[9:10], off
v_lshl_add_u32 v9, v0, 2, 4
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v10, 0, v9
v_add_nc_u32_e32 v9, s17, v9
s_waitcnt vmcnt(1)
ds_store_b32 v10, v5
s_waitcnt vmcnt(0)
ds_store_b32 v9, v6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s8
v_add_nc_u32_e32 v5, s9, v3
s_clause 0x1
s_load_b128 s[12:15], s[0:1], 0x38
s_load_b128 s[8:11], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_barrier
v_ashrrev_i32_e32 v6, 31, v5
buffer_gl0_inv
v_lshl_add_u32 v0, v0, 2, 4
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v6, vcc_lo
global_load_b32 v13, v[9:10], off
v_add_co_u32 v9, vcc_lo, s12, v1
v_add_co_ci_u32_e32 v10, vcc_lo, s13, v2, vcc_lo
v_add_co_u32 v11, vcc_lo, s8, v1
v_add_co_ci_u32_e32 v12, vcc_lo, s9, v2, vcc_lo
s_clause 0x1
s_load_b64 s[18:19], s[0:1], 0x18
s_load_b64 s[0:1], s[0:1], 0x48
global_load_b32 v9, v[9:10], off
global_load_b32 v10, v[11:12], off
v_add_nc_u32_e32 v14, s17, v0
ds_load_b32 v15, v8
ds_load_b32 v8, v14
ds_load_b32 v14, v7
v_add_nc_u32_e32 v7, s16, v3
s_waitcnt vmcnt(2) lgkmcnt(0)
v_dual_sub_f32 v13, v13, v15 :: v_dual_add_nc_u32 v0, 0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_sub_f32_e32 v3, v13, v8
ds_load_b32 v13, v4
v_add_f32_e32 v16, v3, v14
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v10, v9, v16
v_ashrrev_i32_e32 v8, 31, v7
global_store_b32 v[11:12], v10, off
v_lshlrev_b64 v[3:4], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v4, vcc_lo
global_load_b32 v11, v[7:8], off
v_add_co_u32 v7, vcc_lo, s14, v1
v_add_co_ci_u32_e32 v8, vcc_lo, s15, v2, vcc_lo
v_add_co_u32 v9, vcc_lo, s10, v1
v_add_co_ci_u32_e32 v10, vcc_lo, s11, v2, vcc_lo
global_load_b32 v7, v[7:8], off
global_load_b32 v8, v[9:10], off
ds_load_b32 v0, v0
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
s_waitcnt lgkmcnt(0)
v_sub_f32_e32 v0, v0, v13
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v0, v0, v11
v_add_f32_e32 v0, v15, v0
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v8, v7, v0
global_store_b32 v[9:10], v8, off
global_load_b32 v7, v[3:4], off
global_load_b32 v5, v[5:6], off
v_add_co_u32 v3, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v2, vcc_lo
v_add_co_u32 v0, vcc_lo, s18, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s19, v2, vcc_lo
global_load_b32 v2, v[3:4], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(3)
v_sub_f32_e32 v4, v7, v14
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v4, v4, v5
v_add_f32_e32 v4, v13, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v3, v2, v4
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8update_eiiPfS_S_S_S_S_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 336
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8update_eiiPfS_S_S_S_S_S_S_S_, .Lfunc_end0-_Z8update_eiiPfS_S_S_S_S_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8update_hiiPfS_S_S_S_S_
.globl _Z8update_hiiPfS_S_S_S_S_
.p2align 8
.type _Z8update_hiiPfS_S_S_S_S_,@function
_Z8update_hiiPfS_S_S_S_S_:
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b32 s13, s[0:1], 0x44
s_waitcnt lgkmcnt(0)
s_add_i32 s3, s5, -1
s_add_i32 s2, s4, -1
s_ashr_i32 s14, s3, 31
s_mul_i32 s2, s3, s2
s_and_b32 s13, s13, 0xffff
s_ashr_i32 s12, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s12
s_xor_b32 s16, s2, s12
s_add_i32 s2, s3, s14
v_cvt_f32_u32_e32 v1, s16
s_xor_b32 s17, s2, s14
s_sub_i32 s2, 0, s16
v_cvt_f32_u32_e32 v2, s17
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_mul_f32_e32 v3, 0x4f7ffffe, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cvt_u32_f32_e32 v4, v1
v_mad_u64_u32 v[1:2], null, s15, s13, v[0:1]
v_cvt_u32_f32_e32 v2, v3
s_delay_alu instid0(VALU_DEP_3)
v_mul_lo_u32 v3, s2, v4
s_sub_i32 s2, 0, s17
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v5, s2, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v6, 31, v1
v_mul_hi_u32 v3, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v7, v1, v6
v_mul_hi_u32 v5, v2, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_xor_b32_e32 v7, v7, v6
v_add_nc_u32_e32 v3, v4, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v2, v5
v_mul_hi_u32 v3, v7, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v2, v7, v2
v_mul_lo_u32 v4, v3, s16
v_add_nc_u32_e32 v8, 1, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_lo_u32 v5, v2, s17
v_sub_nc_u32_e32 v4, v7, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v5, v7, v5
v_add_nc_u32_e32 v7, 1, v2
v_subrev_nc_u32_e32 v9, s16, v4
v_cmp_le_u32_e32 vcc_lo, s16, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_le_u32_e64 s2, s17, v5
v_cndmask_b32_e32 v4, v4, v9, vcc_lo
v_xor_b32_e32 v9, s12, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v2, v2, v7, s2
v_cndmask_b32_e32 v3, v3, v8, vcc_lo
v_subrev_nc_u32_e32 v8, s17, v5
v_cmp_le_u32_e32 vcc_lo, s16, v4
v_xor_b32_e32 v4, s14, v6
v_cndmask_b32_e64 v5, v5, v8, s2
v_add_nc_u32_e32 v8, 1, v2
v_add_nc_u32_e32 v7, 1, v3
s_mul_i32 s2, s5, s4
s_lshl_b32 s4, s13, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v3, v7, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s17, v5
v_xor_b32_e32 v3, v3, v9
v_cndmask_b32_e32 v2, v2, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v3, v9
v_xor_b32_e32 v2, v2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v3, v3, s3
v_sub_nc_u32_e32 v2, v2, v4
s_add_i32 s3, s4, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_add_i32 s3, s3, 4
v_add3_u32 v2, s2, s5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v5, v2, v1, v3
v_add_nc_u32_e32 v3, 1, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[1:2], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v2, vcc_lo
v_add_co_u32 v8, vcc_lo, s8, v1
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v2, vcc_lo
v_add_co_u32 v10, vcc_lo, s10, v1
v_add_co_ci_u32_e32 v11, vcc_lo, s11, v2, vcc_lo
global_load_b32 v6, v[6:7], off
global_load_b32 v9, v[8:9], off
global_load_b32 v10, v[10:11], off
v_lshl_add_u32 v8, v0, 2, 4
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v4, 0, v8
v_add_nc_u32_e32 v7, s3, v8
v_add3_u32 v8, s3, s4, v8
s_mov_b32 s4, exec_lo
s_waitcnt vmcnt(2)
ds_store_b32 v4, v6
s_waitcnt vmcnt(1)
ds_store_b32 v7, v9
s_waitcnt vmcnt(0)
ds_store_b32 v8, v10
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_2
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v9, vcc_lo, s6, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v6, vcc_lo
v_add_co_u32 v5, vcc_lo, s8, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
global_load_b32 v9, v[9:10], off
global_load_b32 v5, v[5:6], off
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v10, s3
s_waitcnt vmcnt(1)
ds_store_b32 v6, v9
s_waitcnt vmcnt(0)
ds_store_b32 v10, v5
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s4
v_subrev_nc_u32_e32 v5, s5, v3
s_load_b128 s[12:15], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b32_e32 v0, 2, v0
ds_load_b32 v13, v8
v_subrev_nc_u32_e32 v3, s2, v3
s_load_b64 s[0:1], s[0:1], 0x30
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_nc_u32_e32 v8, s3, v0
v_add_nc_u32_e32 v0, 0, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v9, vcc_lo, s10, v5
v_add_co_ci_u32_e32 v10, vcc_lo, s11, v6, vcc_lo
global_load_b32 v11, v[9:10], off
v_add_co_u32 v9, vcc_lo, s12, v1
v_add_co_ci_u32_e32 v10, vcc_lo, s13, v2, vcc_lo
global_load_b32 v12, v[9:10], off
ds_load_b32 v14, v7
ds_load_b32 v7, v8
ds_load_b32 v15, v4
s_waitcnt vmcnt(1) lgkmcnt(0)
v_sub_f32_e32 v8, v13, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v4, v8, v14
v_add_f32_e32 v4, v4, v7
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[7:8], v12
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[11:12], v4
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], v[11:12], -0.5, v[7:8]
v_cvt_f32_f64_e32 v16, v[7:8]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v7, vcc_lo, s10, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s11, v4, vcc_lo
v_add_co_u32 v11, vcc_lo, s14, v1
v_add_co_ci_u32_e32 v12, vcc_lo, s15, v2, vcc_lo
v_add_co_u32 v3, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
global_store_b32 v[9:10], v16, off
global_load_b32 v7, v[7:8], off
global_load_b32 v8, v[11:12], off
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
v_sub_f32_e32 v0, v15, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_f32_e32 v0, v0, v13
s_waitcnt vmcnt(1)
v_add_f32_e32 v0, v7, v0
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[7:8], v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[9:10], v0
v_fma_f64 v[7:8], v[9:10], -0.5, v[7:8]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v0, v[7:8]
global_store_b32 v[11:12], v0, off
global_load_b32 v7, v[3:4], off
v_add_co_u32 v3, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v6, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
global_load_b32 v3, v[3:4], off
global_load_b32 v4, v[0:1], off
s_waitcnt vmcnt(2)
v_sub_f32_e32 v2, v14, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_f32_e32 v2, v2, v15
s_waitcnt vmcnt(1)
v_add_f32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[4:5], v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[2:3], v2
v_fma_f64 v[2:3], v[2:3], -0.5, v[4:5]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v2, v[2:3]
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8update_hiiPfS_S_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z8update_hiiPfS_S_S_S_S_, .Lfunc_end1-_Z8update_hiiPfS_S_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
- .offset: 80
.size: 4
.value_kind: hidden_block_count_x
- .offset: 84
.size: 4
.value_kind: hidden_block_count_y
- .offset: 88
.size: 4
.value_kind: hidden_block_count_z
- .offset: 92
.size: 2
.value_kind: hidden_group_size_x
- .offset: 94
.size: 2
.value_kind: hidden_group_size_y
- .offset: 96
.size: 2
.value_kind: hidden_group_size_z
- .offset: 98
.size: 2
.value_kind: hidden_remainder_x
- .offset: 100
.size: 2
.value_kind: hidden_remainder_y
- .offset: 102
.size: 2
.value_kind: hidden_remainder_z
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 136
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 144
.size: 2
.value_kind: hidden_grid_dims
- .offset: 200
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 336
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8update_eiiPfS_S_S_S_S_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z8update_eiiPfS_S_S_S_S_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
- .offset: 176
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8update_hiiPfS_S_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z8update_hiiPfS_S_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void update_e( int Ny, int Nz, float *Ex, float *Ey, float *Ez, float *Hx, float *Hy, float *Hz, float *CEx, float *CEy, float *CEz ) {
int tk = threadIdx.x;
int idx = blockIdx.x*blockDim.x + tk;
int Nyz = Ny*Nz;
//int fidx = idx + idx/(Nz-1) + Nyz + Nz + 1;
int fidx = idx + idx/(Nz-1) + idx/( (Nz-1)*(Ny-1) )*(Nz-1) + Nyz + Nz + 1;
extern __shared__ float hs[];
float* hx = (float*) hs;
float* hy = (float*) &hx[blockDim.x+1];
float* hz = (float*) &hy[blockDim.x+1];
hx[tk] = Hx[fidx];
hy[tk] = Hy[fidx];
hz[tk] = Hz[fidx];
if ( tk==blockDim.x-1 ) {
hx[tk+1] = Hx[fidx+1];
hy[tk+1] = Hy[fidx+1];
}
__syncthreads();
Ex[fidx] += CEx[fidx]*( Hz[fidx+Nz] - hz[tk] - hy[tk+1] + hy[tk] );
Ey[fidx] += CEy[fidx]*( hx[tk+1] - hx[tk] - Hz[fidx+Nyz] + hz[tk] );
Ez[fidx] += CEz[fidx]*( Hy[fidx+Nyz] - hy[tk] - Hx[fidx+Nz] + hx[tk] );
}
__global__ void update_h( int Ny, int Nz, float *Ex, float *Ey, float *Ez, float *Hx, float *Hy, float *Hz ) {
int tk = threadIdx.x;
int idx = blockIdx.x*blockDim.x + tk;
int Nyz = Ny*Nz;
//int fidx = idx + idx/(Nz-1) + Nyz + Nz + 1;
int fidx = idx + idx/(Nz-1) + idx/( (Nz-1)*(Ny-1) )*(Nz-1) + Nyz + Nz + 1;
extern __shared__ float es[];
float* ex = (float*) es;
float* ey = (float*) &ex[blockDim.x+1];
float* ez = (float*) &ey[blockDim.x+1];
ex[tk+1] = Ex[fidx];
ey[tk+1] = Ey[fidx];
ez[tk] = Ez[fidx];
if ( tk==0 ) {
ex[0] = Ex[fidx-1];
ey[0] = Ey[fidx-1];
}
__syncthreads();
Hx[fidx] -= 0.5*( ez[tk] - Ez[fidx-Nz] - ey[tk+1] + ey[tk] );
Hy[fidx] -= 0.5*( ex[tk+1] - ex[tk] - ez[tk] + Ez[fidx-Nyz] );
Hz[fidx] -= 0.5*( ey[tk+1] - Ey[fidx-Nyz] - ex[tk+1] + Ex[fidx-Nz] );
} | .text
.file "non_aligned-Nx+1.hip"
.globl _Z23__device_stub__update_eiiPfS_S_S_S_S_S_S_S_ # -- Begin function _Z23__device_stub__update_eiiPfS_S_S_S_S_S_S_S_
.p2align 4, 0x90
.type _Z23__device_stub__update_eiiPfS_S_S_S_S_S_S_S_,@function
_Z23__device_stub__update_eiiPfS_S_S_S_S_S_S_S_: # @_Z23__device_stub__update_eiiPfS_S_S_S_S_S_S_S_
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8update_eiiPfS_S_S_S_S_S_S_S_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z23__device_stub__update_eiiPfS_S_S_S_S_S_S_S_, .Lfunc_end0-_Z23__device_stub__update_eiiPfS_S_S_S_S_S_S_S_
.cfi_endproc
# -- End function
.globl _Z23__device_stub__update_hiiPfS_S_S_S_S_ # -- Begin function _Z23__device_stub__update_hiiPfS_S_S_S_S_
.p2align 4, 0x90
.type _Z23__device_stub__update_hiiPfS_S_S_S_S_,@function
_Z23__device_stub__update_hiiPfS_S_S_S_S_: # @_Z23__device_stub__update_hiiPfS_S_S_S_S_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8update_hiiPfS_S_S_S_S_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end1:
.size _Z23__device_stub__update_hiiPfS_S_S_S_S_, .Lfunc_end1-_Z23__device_stub__update_hiiPfS_S_S_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8update_eiiPfS_S_S_S_S_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8update_hiiPfS_S_S_S_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8update_eiiPfS_S_S_S_S_S_S_S_,@object # @_Z8update_eiiPfS_S_S_S_S_S_S_S_
.section .rodata,"a",@progbits
.globl _Z8update_eiiPfS_S_S_S_S_S_S_S_
.p2align 3, 0x0
_Z8update_eiiPfS_S_S_S_S_S_S_S_:
.quad _Z23__device_stub__update_eiiPfS_S_S_S_S_S_S_S_
.size _Z8update_eiiPfS_S_S_S_S_S_S_S_, 8
.type _Z8update_hiiPfS_S_S_S_S_,@object # @_Z8update_hiiPfS_S_S_S_S_
.globl _Z8update_hiiPfS_S_S_S_S_
.p2align 3, 0x0
_Z8update_hiiPfS_S_S_S_S_:
.quad _Z23__device_stub__update_hiiPfS_S_S_S_S_
.size _Z8update_hiiPfS_S_S_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8update_eiiPfS_S_S_S_S_S_S_S_"
.size .L__unnamed_1, 32
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z8update_hiiPfS_S_S_S_S_"
.size .L__unnamed_2, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__update_eiiPfS_S_S_S_S_S_S_S_
.addrsig_sym _Z23__device_stub__update_hiiPfS_S_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8update_eiiPfS_S_S_S_S_S_S_S_
.addrsig_sym _Z8update_hiiPfS_S_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00041623_00000000-6_non_aligned-Nx+1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z8update_eiiPfS_S_S_S_S_S_S_S_iiPfS_S_S_S_S_S_S_S_
.type _Z45__device_stub__Z8update_eiiPfS_S_S_S_S_S_S_S_iiPfS_S_S_S_S_S_S_S_, @function
_Z45__device_stub__Z8update_eiiPfS_S_S_S_S_S_S_S_iiPfS_S_S_S_S_S_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movl %edi, 76(%rsp)
movl %esi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
movq %r8, 48(%rsp)
movq %r9, 40(%rsp)
movq 256(%rsp), %rax
movq %rax, 32(%rsp)
movq 264(%rsp), %rax
movq %rax, 24(%rsp)
movq 272(%rsp), %rax
movq %rax, 16(%rsp)
movq 280(%rsp), %rax
movq %rax, 8(%rsp)
movq 288(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 76(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rax
movq %rax, 176(%rsp)
leaq 40(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rax
movq %rax, 192(%rsp)
leaq 24(%rsp), %rax
movq %rax, 200(%rsp)
leaq 16(%rsp), %rax
movq %rax, 208(%rsp)
leaq 8(%rsp), %rax
movq %rax, 216(%rsp)
movq %rsp, %rax
movq %rax, 224(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 264
pushq 88(%rsp)
.cfi_def_cfa_offset 272
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z8update_eiiPfS_S_S_S_S_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z8update_eiiPfS_S_S_S_S_S_S_S_iiPfS_S_S_S_S_S_S_S_, .-_Z45__device_stub__Z8update_eiiPfS_S_S_S_S_S_S_S_iiPfS_S_S_S_S_S_S_S_
.globl _Z8update_eiiPfS_S_S_S_S_S_S_S_
.type _Z8update_eiiPfS_S_S_S_S_S_S_S_, @function
_Z8update_eiiPfS_S_S_S_S_S_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 56(%rsp)
.cfi_def_cfa_offset 32
pushq 56(%rsp)
.cfi_def_cfa_offset 40
pushq 56(%rsp)
.cfi_def_cfa_offset 48
pushq 56(%rsp)
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z45__device_stub__Z8update_eiiPfS_S_S_S_S_S_S_S_iiPfS_S_S_S_S_S_S_S_
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8update_eiiPfS_S_S_S_S_S_S_S_, .-_Z8update_eiiPfS_S_S_S_S_S_S_S_
.globl _Z39__device_stub__Z8update_hiiPfS_S_S_S_S_iiPfS_S_S_S_S_
.type _Z39__device_stub__Z8update_hiiPfS_S_S_S_S_iiPfS_S_S_S_S_, @function
_Z39__device_stub__Z8update_hiiPfS_S_S_S_S_iiPfS_S_S_S_S_:
.LFB2053:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edi, 60(%rsp)
movl %esi, 56(%rsp)
movq %rdx, 48(%rsp)
movq %rcx, 40(%rsp)
movq %r8, 32(%rsp)
movq %r9, 24(%rsp)
movq 224(%rsp), %rax
movq %rax, 16(%rsp)
movq 232(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z8update_hiiPfS_S_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z39__device_stub__Z8update_hiiPfS_S_S_S_S_iiPfS_S_S_S_S_, .-_Z39__device_stub__Z8update_hiiPfS_S_S_S_S_iiPfS_S_S_S_S_
.globl _Z8update_hiiPfS_S_S_S_S_
.type _Z8update_hiiPfS_S_S_S_S_, @function
_Z8update_hiiPfS_S_S_S_S_:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 24(%rsp)
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z39__device_stub__Z8update_hiiPfS_S_S_S_S_iiPfS_S_S_S_S_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z8update_hiiPfS_S_S_S_S_, .-_Z8update_hiiPfS_S_S_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8update_hiiPfS_S_S_S_S_"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z8update_eiiPfS_S_S_S_S_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8update_hiiPfS_S_S_S_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z8update_eiiPfS_S_S_S_S_S_S_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "non_aligned-Nx+1.hip"
.globl _Z23__device_stub__update_eiiPfS_S_S_S_S_S_S_S_ # -- Begin function _Z23__device_stub__update_eiiPfS_S_S_S_S_S_S_S_
.p2align 4, 0x90
.type _Z23__device_stub__update_eiiPfS_S_S_S_S_S_S_S_,@function
_Z23__device_stub__update_eiiPfS_S_S_S_S_S_S_S_: # @_Z23__device_stub__update_eiiPfS_S_S_S_S_S_S_S_
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8update_eiiPfS_S_S_S_S_S_S_S_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z23__device_stub__update_eiiPfS_S_S_S_S_S_S_S_, .Lfunc_end0-_Z23__device_stub__update_eiiPfS_S_S_S_S_S_S_S_
.cfi_endproc
# -- End function
.globl _Z23__device_stub__update_hiiPfS_S_S_S_S_ # -- Begin function _Z23__device_stub__update_hiiPfS_S_S_S_S_
.p2align 4, 0x90
.type _Z23__device_stub__update_hiiPfS_S_S_S_S_,@function
_Z23__device_stub__update_hiiPfS_S_S_S_S_: # @_Z23__device_stub__update_hiiPfS_S_S_S_S_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8update_hiiPfS_S_S_S_S_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end1:
.size _Z23__device_stub__update_hiiPfS_S_S_S_S_, .Lfunc_end1-_Z23__device_stub__update_hiiPfS_S_S_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8update_eiiPfS_S_S_S_S_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8update_hiiPfS_S_S_S_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8update_eiiPfS_S_S_S_S_S_S_S_,@object # @_Z8update_eiiPfS_S_S_S_S_S_S_S_
.section .rodata,"a",@progbits
.globl _Z8update_eiiPfS_S_S_S_S_S_S_S_
.p2align 3, 0x0
_Z8update_eiiPfS_S_S_S_S_S_S_S_:
.quad _Z23__device_stub__update_eiiPfS_S_S_S_S_S_S_S_
.size _Z8update_eiiPfS_S_S_S_S_S_S_S_, 8
.type _Z8update_hiiPfS_S_S_S_S_,@object # @_Z8update_hiiPfS_S_S_S_S_
.globl _Z8update_hiiPfS_S_S_S_S_
.p2align 3, 0x0
_Z8update_hiiPfS_S_S_S_S_:
.quad _Z23__device_stub__update_hiiPfS_S_S_S_S_
.size _Z8update_hiiPfS_S_S_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8update_eiiPfS_S_S_S_S_S_S_S_"
.size .L__unnamed_1, 32
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z8update_hiiPfS_S_S_S_S_"
.size .L__unnamed_2, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__update_eiiPfS_S_S_S_S_S_S_S_
.addrsig_sym _Z23__device_stub__update_hiiPfS_S_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8update_eiiPfS_S_S_S_S_S_S_S_
.addrsig_sym _Z8update_hiiPfS_S_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
A multithreaded C-program for MT19937.
Original single threaded C reference coded by Takuji Nishimurar
and Makoto Matsumoto, with initialization improved 2002/1/26.
Multithreaded C implementation coded by Eric Mills.
Before using, initialize the state by using mt19937gi(seed)
or mt19937gai(init_key, key_length) for the global memory versions or
mt19937si(seed) or mt19937sai(init_key, key_length) for all shared
memory versions.
Copyright (C) 1997 - 2002, Makoto Matsumoto and Takuji Nishimura,
All rights reserved.
Multithreaded implementation Copyright (C) 2007, Eric Mills.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. The names of its contributors may not be used to endorse or promote
products derived from this software without specific prior written
permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Any feedback is very welcome.
http://www.math.sci.hiroshima-u.ac.jp/~m-mat/MT/emt.html
email: m-mat @ math.sci.hiroshima-u.ac.jp (remove space)
*/
#define NVG80 /* For Nvidia G80 achitecture where mod is VERY slow */
#ifdef NVG80
#define mod(x, y) ((x) < (y) ? (x) : (x) - (y)) /* Short mod - known input range */
#else
#define mod(x, y) ((x) % (y))
#endif
#ifdef _WIN32
typedef unsigned int uint;
#endif
#define N 624
#define M 397
#define INIT_MULT 1812433253 /* See Knuth TAOCP Vol2. 3rd Ed. P.106 for multiplier. */
#define ARRAY_SEED 19650218 /* Seed for initial setup before incorp array seed */
#define MATRIX_A 0x9908b0df /* Constant vector a */
#define UPPER_MASK 0x80000000 /* Most significant w-r bits */
#define LOWER_MASK 0x7fffffff /* Least significant r bits */
#define TEMPER1 0x9d2c5680
#define TEMPER2 0xefc60000
/* First a global memory implementation that uses 2 global reads and 1 global
* write per result and keeps only 2 words of state in permanent shared memory. */
#define MAX_THREADS 227 /* Set to minimise shared memory allocation (max blockDim.x) */
#define MAX_BLOCKS 256 /* Set to minimise global memory allocation (max gridDim.x) */
__shared__ int mtNext; /* Start of next block of seeds */
__shared__ uint mtNexti; /* Indirect on above to save global read cycle */
__device__ uint g_seeds[MAX_BLOCKS][N];
__constant__ uint mag01[2] = {0, MATRIX_A}; /* 2 way bus conflict for each read */
/* Init by single seed - single threaded as only used once */
__device__ static void
mt19937gi(uint seed)
{
int i;
mtNext = 0;
if (threadIdx.x == 0)
{
g_seeds[blockIdx.x][0] = mtNexti = seed;
for (i = 1; i < N; i++)
{
seed = (INIT_MULT * (seed ^ (seed >> 30)) + i);
g_seeds[blockIdx.x][i] = seed;
}
}
return;
}
/* Init by array - single threaded as only used once, opt to reduce global refs */
__device__ static void
mt19937gai(uint* seeds, uint length)
{
mt19937gi(ARRAY_SEED);
if (threadIdx.x == 0)
{
int i = 1;
int j = 0;
int k;
uint mti; /* g_seeds[i] */
uint mtj; /* g_seeds[i - 1] */
mti = g_seeds[blockIdx.x][0];
for (k = N > length ? N : length; k != 0; k--)
{
mtj = mti;
mti = g_seeds[blockIdx.x][i];
mti = (mti ^ ((mtj ^ (mtj >> 30)) * 1664525)) + seeds[j] + j;
g_seeds[blockIdx.x][i] = mti;
if (++i >= N)
{
g_seeds[blockIdx.x][0] = mti;
i = 1;
}
if (++j >= length)
{
j = 0;
}
}
for (k = N - 1; k != 0; k--)
{
mtj = mti;
mti = g_seeds[blockIdx.x][i];
mti = (mti ^ ((mtj ^ (mtj >> 30)) * 1566083941)) - i;
g_seeds[blockIdx.x][i] = mti;
if (++i >= N)
{
g_seeds[blockIdx.x][0] = mti;
i = 1;
}
}
g_seeds[blockIdx.x][0] = mtNexti = 0x80000000; /* MSB is 1; assuring non-zero initial array */
}
return;
}
/* Return next MT random by increasing thread ID, Good for 1 - 227 threads.
* Note you should wind back MAX_THREADS to your max requirement
* to keep auto allocation of shared mem to a minimum.
* Best as a general purpose library routine. */
__device__ static uint
mt19937g(void)
{
int kk;
uint y;
const int tid = threadIdx.x;
__shared__ uint seed[MAX_THREADS + 1];
kk = mod(mtNext + tid, N);
__syncthreads(); /* Finish with mtNext & g_seeds ready from last call & init */
seed[tid + 1] = g_seeds[blockIdx.x][mod(kk + 1, N)]; /* Sequential but not aligned */
if (tid == blockDim.x - 1)
{
mtNext = kk + 1;
seed[0] = mtNexti;
mtNexti = seed[blockDim.x];
}
__syncthreads(); /* seed[] ready */
y = (seed[tid] & UPPER_MASK) | (seed[tid + 1] & LOWER_MASK);
y = g_seeds[blockIdx.x][kk < N - M ? kk + M : kk + (M - N)] ^ (y >> 1) ^ mag01[y & 1];
g_seeds[blockIdx.x][kk] = y; /* Does not overlap above reads */
y ^= (y >> 11); /* Tempering */
y ^= (y << 7) & TEMPER1;
y ^= (y << 15) & TEMPER2;
y ^= (y >> 18);
return y;
}
/* Generalised global memory version for any number of threads.
* Note only runs up to 227 at a time, rest loop and block till all done.
* Runs fractional warps at each end so not perfect utilisation.
* Uses 228 words of auto allocated shared mem. */
__device__ static uint
mt19937gl(void)
{
int jj;
int kk;
uint y;
int tid; /* Offset thread ID */
__shared__ uint seed[N - M + 1];
kk = mod(mtNext + threadIdx.x, N); /* G80 limited to 512 threads */
__syncthreads(); /* Finish with mtNext & g_seeds set from init */
if (threadIdx.x == blockDim.x - 1)
{
mtNext = kk + 1; /* Modded next call */
}
jj = 0;
do
{
__syncthreads(); /* g_seeds set from last loop */
tid = threadIdx.x - jj;
if (0 <= tid && tid < N - M)
{
seed[tid + 1] = g_seeds[blockIdx.x][mod(kk + 1, N)]; /* Sequential but not aligned */
y = min(N - M, blockDim.x - jj);
if (tid == y - 1) /* Last thread this loop */
{
seed[0] = mtNexti;
mtNexti = seed[y];
}
}
__syncthreads(); /* seed[] ready */
if (0 <= tid && tid < N - M)
{
y = (seed[tid] & UPPER_MASK) | (seed[tid + 1] & LOWER_MASK);
y = g_seeds[blockIdx.x][kk < N - M ? kk + M : kk + (M - N)] ^ (y >> 1) ^ mag01[y & 1];
g_seeds[blockIdx.x][kk] = y; /* Does not overlap reads above */
}
} while ((jj += N - M) < blockDim.x);
y ^= (y >> 11); /* Tempering */
y ^= (y << 7) & TEMPER1;
y ^= (y << 15) & TEMPER2;
y ^= (y >> 18);
return y;
}
/*************************************************************************************
* This is a shared memory implementation that keeps the full 626 words of state
* in shared memory. Faster for heavy random work where you can afford shared mem. */
__shared__ int mtNexts; /* Start of next block of seeds */
__shared__ uint s_seeds[N + 1];
/* Init by single seed - single threaded as only used once */
__device__ static void
mt19937si(uint seed)
{
int i;
if (threadIdx.x == 0)
{
mtNexts = 0;
s_seeds[0] = seed;
for (i = 1; i < N; i++)
{
seed = (INIT_MULT * (seed ^ (seed >> 30)) + i);
s_seeds[i] = seed;
}
}
__syncthreads(); /* Ensure mtNexts set & needed for mt19937w() */
return;
}
/* Init by array - single threaded as only used once */
__device__ static void
mt19937sai(uint* seeds, uint length)
{
mt19937si(ARRAY_SEED);
if (threadIdx.x == 0)
{
int i = 1;
int j = 0;
int k;
for (k = N > length ? N : length; k != 0; k--)
{
s_seeds[i] = (s_seeds[i] ^ ((s_seeds[i - 1] ^ (s_seeds[i - 1] >> 30)) * 1664525)) + seeds[j] + j;
if (++i >= N)
{
s_seeds[0] = s_seeds[N - 1];
i = 1;
}
if (++j >= length)
{
j = 0;
}
}
for (k = N - 1; k != 0; k--)
{
s_seeds[i] = (s_seeds[i] ^ ((s_seeds[i - 1] ^ (s_seeds[i - 1] >> 30)) * 1566083941)) - i;
if (++i >= N)
{
s_seeds[0] = s_seeds[N - 1];
i = 1;
}
}
s_seeds[0] = 0x80000000; /* MSB is 1; assuring non-zero initial array */
}
__syncthreads(); /* Needed for mt19937w() */
return;
}
/* Return next MT random by increasing thread ID for 1-227 threads. */
__device__ static uint
mt19937s(void)
{
int kk;
uint y;
const int tid = threadIdx.x;
kk = mod(mtNexts + tid, N);
__syncthreads(); /* Finished with mtNexts & s_seed[] ready from last run */
if (tid == blockDim.x - 1)
{
mtNexts = kk + 1; /* Will get modded on next call */
}
y = (s_seeds[kk] & UPPER_MASK) | (s_seeds[kk + 1] & LOWER_MASK);
y = s_seeds[kk < N - M ? kk + M : kk + (M - N)] ^ (y >> 1) ^ mag01[y & 1];
//y = s_seeds[kk < N - M ? kk + M : kk + (M - N)] ^ (y >> 1) ^ (y & 1 ? MATRIX_A : 0); // Same speed
__syncthreads(); /* All done before we update */
s_seeds[kk] = y;
if (kk == 0) /* Copy up for next round */
{
s_seeds[N] = y;
}
y ^= (y >> 11); /* Tempering */
y ^= (y << 7) & TEMPER1;
y ^= (y << 15) & TEMPER2;
y ^= (y >> 18);
return y;
}
/* General shared memory version for any number of threads.
* Note only up to 227 threads are run at any one time,
* the rest loop and block till all are done. */
__device__ static uint
mt19937sl(void)
{
int jj;
int kk;
uint y;
int tid; /* Offset thread ID */
kk = mod(mtNexts + threadIdx.x, N); /* G80 limited to 512 threads */
__syncthreads(); /* Finished with mtNexts & s_seed[] ready from init */
if (threadIdx.x == blockDim.x - 1)
{
mtNexts = kk + 1; /* Will get modded on next call */
}
jj = 0;
do
{
__syncthreads(); /* s_seeds[] ready from last loop */
tid = threadIdx.x - jj;
if (0 <= tid && tid < N - M)
{
y = (s_seeds[kk] & UPPER_MASK) | (s_seeds[kk + 1] & LOWER_MASK);
y = s_seeds[kk < N - M ? kk + M : kk + (M - N)] ^ (y >> 1) ^ mag01[y & 1];
}
__syncthreads(); /* All done before we update */
if (0 <= tid && tid < N - M)
{
s_seeds[kk] = y;
if (kk == 0)
{
s_seeds[N] = y;
}
}
} while ((jj += N - M) < blockDim.x);
y ^= (y >> 11); /* Tempering */
y ^= (y << 7) & TEMPER1;
y ^= (y << 15) & TEMPER2;
y ^= (y >> 18);
return y;
}
/***************************************************************************************
* This is an implementation of a full step in 1 call - all 624 results returned at once
* in pairs - 64 bit version. It may be run with 227-312 threads and will drop numbers
* from the sequence if < 312 (not incorrect).
* Original idea for this version was first presented by Brian Budge. */
#define B2 224 /* Size of second block */
__device__ static uint2
mt19937w(const int tid)
{
int kk;
uint y;
uint2 ret;
kk = tid;
/* First 227 */
if (kk < N-M) {
y = (s_seeds[kk]&UPPER_MASK)|(s_seeds[kk+1]&LOWER_MASK);
y = s_seeds[kk+M] ^ (y >> 1) ^ mag01[y & 1];
}
__syncthreads();
if (kk < N-M) {
s_seeds[kk] = y;
if (kk == 0)
{
s_seeds[N] = y;
}
}
kk += N-M;
__syncthreads();
/* Next 224 */
if (kk < N-M + B2) {
y = (s_seeds[kk]&UPPER_MASK)|(s_seeds[kk+1]&LOWER_MASK);
y = s_seeds[kk+(M-N)] ^ (y >> 1) ^ mag01[y & 1];
}
__syncthreads();
if (kk < N-M + B2) {
s_seeds[kk] = y;
}
kk += B2;
__syncthreads();
/* Last 173 */
if (kk < N) {
y = (s_seeds[kk]&UPPER_MASK)|(s_seeds[kk+1]&LOWER_MASK);
y = s_seeds[kk+(M-N)] ^ (y >> 1) ^ mag01[y & 1];
}
__syncthreads();
if (kk < N) {
s_seeds[kk] = y;
}
__syncthreads();
ret.x = s_seeds[2*tid];
ret.x ^= (ret.x >> 11); /* Tempering */
ret.x ^= (ret.x << 7) & TEMPER1;
ret.x ^= (ret.x << 15) & TEMPER2;
ret.x ^= (ret.x >> 18);
ret.y = s_seeds[2*tid+1];
ret.y ^= (ret.y >> 11);
ret.y ^= (ret.y << 7) & TEMPER1;
ret.y ^= (ret.y << 15) & TEMPER2;
ret.y ^= (ret.y >> 18);
return ret;
}
/*******************************************************************************
* For reference this is the original C single threaded source: */
#if 0
static unsigned long mt[N]; /* the array for the state vector */
static int mti=N+1; /* mti==N+1 means mt[N] is not initialized */
/* initializes mt[N] with a seed */
void init_genrand(unsigned long s)
{
mt[0]= s & 0xffffffffUL;
for (mti=1; mti<N; mti++) {
mt[mti] =
(1812433253UL * (mt[mti-1] ^ (mt[mti-1] >> 30)) + mti);
/* See Knuth TAOCP Vol2. 3rd Ed. P.106 for multiplier. */
/* In the previous versions, MSBs of the seed affect */
/* only MSBs of the array mt[]. */
/* 2002/01/09 modified by Makoto Matsumoto */
mt[mti] &= 0xffffffffUL;
/* for >32 bit machines */
}
}
/* initialize by an array with array-length */
/* init_key is the array for initializing keys */
/* key_length is its length */
/* slight change for C++, 2004/2/26 */
void init_by_array(unsigned long init_key[], int key_length)
{
int i, j, k;
init_genrand(19650218UL);
i=1; j=0;
k = (N>key_length ? N : key_length);
for (; k; k--) {
mt[i] = (mt[i] ^ ((mt[i-1] ^ (mt[i-1] >> 30)) * 1664525UL))
+ init_key[j] + j; /* non linear */
mt[i] &= 0xffffffffUL; /* for WORDSIZE > 32 machines */
i++; j++;
if (i>=N) { mt[0] = mt[N-1]; i=1; }
if (j>=key_length) j=0;
}
for (k=N-1; k; k--) {
mt[i] = (mt[i] ^ ((mt[i-1] ^ (mt[i-1] >> 30)) * 1566083941UL))
- i; /* non linear */
mt[i] &= 0xffffffffUL; /* for WORDSIZE > 32 machines */
i++;
if (i>=N) { mt[0] = mt[N-1]; i=1; }
}
mt[0] = 0x80000000UL; /* MSB is 1; assuring non-zero initial array */
}
/* generates a random number on [0,0xffffffff]-interval */
unsigned long genrand_int32(void)
{
unsigned long y;
static unsigned long mag01[2]={0x0UL, MATRIX_A};
/* mag01[x] = x * MATRIX_A for x=0,1 */
if (mti >= N) { /* generate N words at one time */
int kk;
if (mti == N+1) /* if init_genrand() has not been called, */
init_genrand(5489UL); /* a default initial seed is used */
for (kk=0;kk<N-M;kk++) {
y = (mt[kk]&UPPER_MASK)|(mt[kk+1]&LOWER_MASK);
mt[kk] = mt[kk+M] ^ (y >> 1) ^ mag01[y & 0x1UL];
}
for (;kk<N-1;kk++) {
y = (mt[kk]&UPPER_MASK)|(mt[kk+1]&LOWER_MASK);
mt[kk] = mt[kk+(M-N)] ^ (y >> 1) ^ mag01[y & 0x1UL];
}
y = (mt[N-1]&UPPER_MASK)|(mt[0]&LOWER_MASK);
mt[N-1] = mt[M-1] ^ (y >> 1) ^ mag01[y & 0x1UL];
mti = 0;
}
y = mt[mti++];
/* Tempering */
y ^= (y >> 11);
y ^= (y << 7) & 0x9d2c5680UL;
y ^= (y << 15) & 0xefc60000UL;
y ^= (y >> 18);
return y;
}
#endif | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
A multithreaded C-program for MT19937.
Original single threaded C reference coded by Takuji Nishimurar
and Makoto Matsumoto, with initialization improved 2002/1/26.
Multithreaded C implementation coded by Eric Mills.
Before using, initialize the state by using mt19937gi(seed)
or mt19937gai(init_key, key_length) for the global memory versions or
mt19937si(seed) or mt19937sai(init_key, key_length) for all shared
memory versions.
Copyright (C) 1997 - 2002, Makoto Matsumoto and Takuji Nishimura,
All rights reserved.
Multithreaded implementation Copyright (C) 2007, Eric Mills.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. The names of its contributors may not be used to endorse or promote
products derived from this software without specific prior written
permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Any feedback is very welcome.
http://www.math.sci.hiroshima-u.ac.jp/~m-mat/MT/emt.html
email: m-mat @ math.sci.hiroshima-u.ac.jp (remove space)
*/
#define NVG80 /* For Nvidia G80 achitecture where mod is VERY slow */
#ifdef NVG80
#define mod(x, y) ((x) < (y) ? (x) : (x) - (y)) /* Short mod - known input range */
#else
#define mod(x, y) ((x) % (y))
#endif
#ifdef _WIN32
typedef unsigned int uint;
#endif
#define N 624
#define M 397
#define INIT_MULT 1812433253 /* See Knuth TAOCP Vol2. 3rd Ed. P.106 for multiplier. */
#define ARRAY_SEED 19650218 /* Seed for initial setup before incorp array seed */
#define MATRIX_A 0x9908b0df /* Constant vector a */
#define UPPER_MASK 0x80000000 /* Most significant w-r bits */
#define LOWER_MASK 0x7fffffff /* Least significant r bits */
#define TEMPER1 0x9d2c5680
#define TEMPER2 0xefc60000
/* First a global memory implementation that uses 2 global reads and 1 global
* write per result and keeps only 2 words of state in permanent shared memory. */
#define MAX_THREADS 227 /* Set to minimise shared memory allocation (max blockDim.x) */
#define MAX_BLOCKS 256 /* Set to minimise global memory allocation (max gridDim.x) */
__shared__ int mtNext; /* Start of next block of seeds */
__shared__ uint mtNexti; /* Indirect on above to save global read cycle */
__device__ uint g_seeds[MAX_BLOCKS][N];
__constant__ uint mag01[2] = {0, MATRIX_A}; /* 2 way bus conflict for each read */
/* Init by single seed - single threaded as only used once */
__device__ static void
mt19937gi(uint seed)
{
int i;
mtNext = 0;
if (threadIdx.x == 0)
{
g_seeds[blockIdx.x][0] = mtNexti = seed;
for (i = 1; i < N; i++)
{
seed = (INIT_MULT * (seed ^ (seed >> 30)) + i);
g_seeds[blockIdx.x][i] = seed;
}
}
return;
}
/* Init by array - single threaded as only used once, opt to reduce global refs */
__device__ static void
mt19937gai(uint* seeds, uint length)
{
mt19937gi(ARRAY_SEED);
if (threadIdx.x == 0)
{
int i = 1;
int j = 0;
int k;
uint mti; /* g_seeds[i] */
uint mtj; /* g_seeds[i - 1] */
mti = g_seeds[blockIdx.x][0];
for (k = N > length ? N : length; k != 0; k--)
{
mtj = mti;
mti = g_seeds[blockIdx.x][i];
mti = (mti ^ ((mtj ^ (mtj >> 30)) * 1664525)) + seeds[j] + j;
g_seeds[blockIdx.x][i] = mti;
if (++i >= N)
{
g_seeds[blockIdx.x][0] = mti;
i = 1;
}
if (++j >= length)
{
j = 0;
}
}
for (k = N - 1; k != 0; k--)
{
mtj = mti;
mti = g_seeds[blockIdx.x][i];
mti = (mti ^ ((mtj ^ (mtj >> 30)) * 1566083941)) - i;
g_seeds[blockIdx.x][i] = mti;
if (++i >= N)
{
g_seeds[blockIdx.x][0] = mti;
i = 1;
}
}
g_seeds[blockIdx.x][0] = mtNexti = 0x80000000; /* MSB is 1; assuring non-zero initial array */
}
return;
}
/* Return next MT random by increasing thread ID, Good for 1 - 227 threads.
* Note you should wind back MAX_THREADS to your max requirement
* to keep auto allocation of shared mem to a minimum.
* Best as a general purpose library routine. */
__device__ static uint
mt19937g(void)
{
int kk;
uint y;
const int tid = threadIdx.x;
__shared__ uint seed[MAX_THREADS + 1];
kk = mod(mtNext + tid, N);
__syncthreads(); /* Finish with mtNext & g_seeds ready from last call & init */
seed[tid + 1] = g_seeds[blockIdx.x][mod(kk + 1, N)]; /* Sequential but not aligned */
if (tid == blockDim.x - 1)
{
mtNext = kk + 1;
seed[0] = mtNexti;
mtNexti = seed[blockDim.x];
}
__syncthreads(); /* seed[] ready */
y = (seed[tid] & UPPER_MASK) | (seed[tid + 1] & LOWER_MASK);
y = g_seeds[blockIdx.x][kk < N - M ? kk + M : kk + (M - N)] ^ (y >> 1) ^ mag01[y & 1];
g_seeds[blockIdx.x][kk] = y; /* Does not overlap above reads */
y ^= (y >> 11); /* Tempering */
y ^= (y << 7) & TEMPER1;
y ^= (y << 15) & TEMPER2;
y ^= (y >> 18);
return y;
}
/* Generalised global memory version for any number of threads.
* Note only runs up to 227 at a time, rest loop and block till all done.
* Runs fractional warps at each end so not perfect utilisation.
* Uses 228 words of auto allocated shared mem. */
__device__ static uint
mt19937gl(void)
{
int jj;
int kk;
uint y;
int tid; /* Offset thread ID */
__shared__ uint seed[N - M + 1];
kk = mod(mtNext + threadIdx.x, N); /* G80 limited to 512 threads */
__syncthreads(); /* Finish with mtNext & g_seeds set from init */
if (threadIdx.x == blockDim.x - 1)
{
mtNext = kk + 1; /* Modded next call */
}
jj = 0;
do
{
__syncthreads(); /* g_seeds set from last loop */
tid = threadIdx.x - jj;
if (0 <= tid && tid < N - M)
{
seed[tid + 1] = g_seeds[blockIdx.x][mod(kk + 1, N)]; /* Sequential but not aligned */
y = min(N - M, blockDim.x - jj);
if (tid == y - 1) /* Last thread this loop */
{
seed[0] = mtNexti;
mtNexti = seed[y];
}
}
__syncthreads(); /* seed[] ready */
if (0 <= tid && tid < N - M)
{
y = (seed[tid] & UPPER_MASK) | (seed[tid + 1] & LOWER_MASK);
y = g_seeds[blockIdx.x][kk < N - M ? kk + M : kk + (M - N)] ^ (y >> 1) ^ mag01[y & 1];
g_seeds[blockIdx.x][kk] = y; /* Does not overlap reads above */
}
} while ((jj += N - M) < blockDim.x);
y ^= (y >> 11); /* Tempering */
y ^= (y << 7) & TEMPER1;
y ^= (y << 15) & TEMPER2;
y ^= (y >> 18);
return y;
}
/*************************************************************************************
* This is a shared memory implementation that keeps the full 626 words of state
* in shared memory. Faster for heavy random work where you can afford shared mem. */
__shared__ int mtNexts; /* Start of next block of seeds */
__shared__ uint s_seeds[N + 1];
/* Init by single seed - single threaded as only used once */
__device__ static void
mt19937si(uint seed)
{
int i;
if (threadIdx.x == 0)
{
mtNexts = 0;
s_seeds[0] = seed;
for (i = 1; i < N; i++)
{
seed = (INIT_MULT * (seed ^ (seed >> 30)) + i);
s_seeds[i] = seed;
}
}
__syncthreads(); /* Ensure mtNexts set & needed for mt19937w() */
return;
}
/* Init by array - single threaded as only used once */
__device__ static void
mt19937sai(uint* seeds, uint length)
{
mt19937si(ARRAY_SEED);
if (threadIdx.x == 0)
{
int i = 1;
int j = 0;
int k;
for (k = N > length ? N : length; k != 0; k--)
{
s_seeds[i] = (s_seeds[i] ^ ((s_seeds[i - 1] ^ (s_seeds[i - 1] >> 30)) * 1664525)) + seeds[j] + j;
if (++i >= N)
{
s_seeds[0] = s_seeds[N - 1];
i = 1;
}
if (++j >= length)
{
j = 0;
}
}
for (k = N - 1; k != 0; k--)
{
s_seeds[i] = (s_seeds[i] ^ ((s_seeds[i - 1] ^ (s_seeds[i - 1] >> 30)) * 1566083941)) - i;
if (++i >= N)
{
s_seeds[0] = s_seeds[N - 1];
i = 1;
}
}
s_seeds[0] = 0x80000000; /* MSB is 1; assuring non-zero initial array */
}
__syncthreads(); /* Needed for mt19937w() */
return;
}
/* Return next MT random by increasing thread ID for 1-227 threads. */
__device__ static uint
mt19937s(void)
{
int kk;
uint y;
const int tid = threadIdx.x;
kk = mod(mtNexts + tid, N);
__syncthreads(); /* Finished with mtNexts & s_seed[] ready from last run */
if (tid == blockDim.x - 1)
{
mtNexts = kk + 1; /* Will get modded on next call */
}
y = (s_seeds[kk] & UPPER_MASK) | (s_seeds[kk + 1] & LOWER_MASK);
y = s_seeds[kk < N - M ? kk + M : kk + (M - N)] ^ (y >> 1) ^ mag01[y & 1];
//y = s_seeds[kk < N - M ? kk + M : kk + (M - N)] ^ (y >> 1) ^ (y & 1 ? MATRIX_A : 0); // Same speed
__syncthreads(); /* All done before we update */
s_seeds[kk] = y;
if (kk == 0) /* Copy up for next round */
{
s_seeds[N] = y;
}
y ^= (y >> 11); /* Tempering */
y ^= (y << 7) & TEMPER1;
y ^= (y << 15) & TEMPER2;
y ^= (y >> 18);
return y;
}
/* General shared memory version for any number of threads.
* Note only up to 227 threads are run at any one time,
* the rest loop and block till all are done. */
__device__ static uint
mt19937sl(void)
{
int jj;
int kk;
uint y;
int tid; /* Offset thread ID */
kk = mod(mtNexts + threadIdx.x, N); /* G80 limited to 512 threads */
__syncthreads(); /* Finished with mtNexts & s_seed[] ready from init */
if (threadIdx.x == blockDim.x - 1)
{
mtNexts = kk + 1; /* Will get modded on next call */
}
jj = 0;
do
{
__syncthreads(); /* s_seeds[] ready from last loop */
tid = threadIdx.x - jj;
if (0 <= tid && tid < N - M)
{
y = (s_seeds[kk] & UPPER_MASK) | (s_seeds[kk + 1] & LOWER_MASK);
y = s_seeds[kk < N - M ? kk + M : kk + (M - N)] ^ (y >> 1) ^ mag01[y & 1];
}
__syncthreads(); /* All done before we update */
if (0 <= tid && tid < N - M)
{
s_seeds[kk] = y;
if (kk == 0)
{
s_seeds[N] = y;
}
}
} while ((jj += N - M) < blockDim.x);
y ^= (y >> 11); /* Tempering */
y ^= (y << 7) & TEMPER1;
y ^= (y << 15) & TEMPER2;
y ^= (y >> 18);
return y;
}
/***************************************************************************************
* This is an implementation of a full step in 1 call - all 624 results returned at once
* in pairs - 64 bit version. It may be run with 227-312 threads and will drop numbers
* from the sequence if < 312 (not incorrect).
* Original idea for this version was first presented by Brian Budge. */
#define B2 224 /* Size of second block */
__device__ static uint2
mt19937w(const int tid)
{
int kk;
uint y;
uint2 ret;
kk = tid;
/* First 227 */
if (kk < N-M) {
y = (s_seeds[kk]&UPPER_MASK)|(s_seeds[kk+1]&LOWER_MASK);
y = s_seeds[kk+M] ^ (y >> 1) ^ mag01[y & 1];
}
__syncthreads();
if (kk < N-M) {
s_seeds[kk] = y;
if (kk == 0)
{
s_seeds[N] = y;
}
}
kk += N-M;
__syncthreads();
/* Next 224 */
if (kk < N-M + B2) {
y = (s_seeds[kk]&UPPER_MASK)|(s_seeds[kk+1]&LOWER_MASK);
y = s_seeds[kk+(M-N)] ^ (y >> 1) ^ mag01[y & 1];
}
__syncthreads();
if (kk < N-M + B2) {
s_seeds[kk] = y;
}
kk += B2;
__syncthreads();
/* Last 173 */
if (kk < N) {
y = (s_seeds[kk]&UPPER_MASK)|(s_seeds[kk+1]&LOWER_MASK);
y = s_seeds[kk+(M-N)] ^ (y >> 1) ^ mag01[y & 1];
}
__syncthreads();
if (kk < N) {
s_seeds[kk] = y;
}
__syncthreads();
ret.x = s_seeds[2*tid];
ret.x ^= (ret.x >> 11); /* Tempering */
ret.x ^= (ret.x << 7) & TEMPER1;
ret.x ^= (ret.x << 15) & TEMPER2;
ret.x ^= (ret.x >> 18);
ret.y = s_seeds[2*tid+1];
ret.y ^= (ret.y >> 11);
ret.y ^= (ret.y << 7) & TEMPER1;
ret.y ^= (ret.y << 15) & TEMPER2;
ret.y ^= (ret.y >> 18);
return ret;
}
/*******************************************************************************
* For reference this is the original C single threaded source: */
#if 0
static unsigned long mt[N]; /* the array for the state vector */
static int mti=N+1; /* mti==N+1 means mt[N] is not initialized */
/* initializes mt[N] with a seed */
void init_genrand(unsigned long s)
{
mt[0]= s & 0xffffffffUL;
for (mti=1; mti<N; mti++) {
mt[mti] =
(1812433253UL * (mt[mti-1] ^ (mt[mti-1] >> 30)) + mti);
/* See Knuth TAOCP Vol2. 3rd Ed. P.106 for multiplier. */
/* In the previous versions, MSBs of the seed affect */
/* only MSBs of the array mt[]. */
/* 2002/01/09 modified by Makoto Matsumoto */
mt[mti] &= 0xffffffffUL;
/* for >32 bit machines */
}
}
/* initialize by an array with array-length */
/* init_key is the array for initializing keys */
/* key_length is its length */
/* slight change for C++, 2004/2/26 */
void init_by_array(unsigned long init_key[], int key_length)
{
int i, j, k;
init_genrand(19650218UL);
i=1; j=0;
k = (N>key_length ? N : key_length);
for (; k; k--) {
mt[i] = (mt[i] ^ ((mt[i-1] ^ (mt[i-1] >> 30)) * 1664525UL))
+ init_key[j] + j; /* non linear */
mt[i] &= 0xffffffffUL; /* for WORDSIZE > 32 machines */
i++; j++;
if (i>=N) { mt[0] = mt[N-1]; i=1; }
if (j>=key_length) j=0;
}
for (k=N-1; k; k--) {
mt[i] = (mt[i] ^ ((mt[i-1] ^ (mt[i-1] >> 30)) * 1566083941UL))
- i; /* non linear */
mt[i] &= 0xffffffffUL; /* for WORDSIZE > 32 machines */
i++;
if (i>=N) { mt[0] = mt[N-1]; i=1; }
}
mt[0] = 0x80000000UL; /* MSB is 1; assuring non-zero initial array */
}
/* generates a random number on [0,0xffffffff]-interval */
unsigned long genrand_int32(void)
{
unsigned long y;
static unsigned long mag01[2]={0x0UL, MATRIX_A};
/* mag01[x] = x * MATRIX_A for x=0,1 */
if (mti >= N) { /* generate N words at one time */
int kk;
if (mti == N+1) /* if init_genrand() has not been called, */
init_genrand(5489UL); /* a default initial seed is used */
for (kk=0;kk<N-M;kk++) {
y = (mt[kk]&UPPER_MASK)|(mt[kk+1]&LOWER_MASK);
mt[kk] = mt[kk+M] ^ (y >> 1) ^ mag01[y & 0x1UL];
}
for (;kk<N-1;kk++) {
y = (mt[kk]&UPPER_MASK)|(mt[kk+1]&LOWER_MASK);
mt[kk] = mt[kk+(M-N)] ^ (y >> 1) ^ mag01[y & 0x1UL];
}
y = (mt[N-1]&UPPER_MASK)|(mt[0]&LOWER_MASK);
mt[N-1] = mt[M-1] ^ (y >> 1) ^ mag01[y & 0x1UL];
mti = 0;
}
y = mt[mti++];
/* Tempering */
y ^= (y >> 11);
y ^= (y << 7) & 0x9d2c5680UL;
y ^= (y << 15) & 0xefc60000UL;
y ^= (y >> 18);
return y;
}
#endif | .file "tmpxft_00058f8a_00000000-6_mt19937_ref.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2038:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2038:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "g_seeds"
.LC1:
.string "mag01"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2061:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $638976, %r9d
movl $0, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7g_seeds(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5mag01(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL5mag01
.comm _ZL5mag01,8,8
.local _ZL7g_seeds
.comm _ZL7g_seeds,638976,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
A multithreaded C-program for MT19937.
Original single threaded C reference coded by Takuji Nishimurar
and Makoto Matsumoto, with initialization improved 2002/1/26.
Multithreaded C implementation coded by Eric Mills.
Before using, initialize the state by using mt19937gi(seed)
or mt19937gai(init_key, key_length) for the global memory versions or
mt19937si(seed) or mt19937sai(init_key, key_length) for all shared
memory versions.
Copyright (C) 1997 - 2002, Makoto Matsumoto and Takuji Nishimura,
All rights reserved.
Multithreaded implementation Copyright (C) 2007, Eric Mills.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. The names of its contributors may not be used to endorse or promote
products derived from this software without specific prior written
permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Any feedback is very welcome.
http://www.math.sci.hiroshima-u.ac.jp/~m-mat/MT/emt.html
email: m-mat @ math.sci.hiroshima-u.ac.jp (remove space)
*/
#define NVG80 /* For Nvidia G80 achitecture where mod is VERY slow */
#ifdef NVG80
#define mod(x, y) ((x) < (y) ? (x) : (x) - (y)) /* Short mod - known input range */
#else
#define mod(x, y) ((x) % (y))
#endif
#ifdef _WIN32
typedef unsigned int uint;
#endif
#define N 624
#define M 397
#define INIT_MULT 1812433253 /* See Knuth TAOCP Vol2. 3rd Ed. P.106 for multiplier. */
#define ARRAY_SEED 19650218 /* Seed for initial setup before incorp array seed */
#define MATRIX_A 0x9908b0df /* Constant vector a */
#define UPPER_MASK 0x80000000 /* Most significant w-r bits */
#define LOWER_MASK 0x7fffffff /* Least significant r bits */
#define TEMPER1 0x9d2c5680
#define TEMPER2 0xefc60000
/* First a global memory implementation that uses 2 global reads and 1 global
* write per result and keeps only 2 words of state in permanent shared memory. */
#define MAX_THREADS 227 /* Set to minimise shared memory allocation (max blockDim.x) */
#define MAX_BLOCKS 256 /* Set to minimise global memory allocation (max gridDim.x) */
__shared__ int mtNext; /* Start of next block of seeds */
__shared__ uint mtNexti; /* Indirect on above to save global read cycle */
__device__ uint g_seeds[MAX_BLOCKS][N];
__constant__ uint mag01[2] = {0, MATRIX_A}; /* 2 way bus conflict for each read */
/* Init by single seed - single threaded as only used once */
__device__ static void
mt19937gi(uint seed)
{
int i;
mtNext = 0;
if (threadIdx.x == 0)
{
g_seeds[blockIdx.x][0] = mtNexti = seed;
for (i = 1; i < N; i++)
{
seed = (INIT_MULT * (seed ^ (seed >> 30)) + i);
g_seeds[blockIdx.x][i] = seed;
}
}
return;
}
/* Init by array - single threaded as only used once, opt to reduce global refs */
__device__ static void
mt19937gai(uint* seeds, uint length)
{
mt19937gi(ARRAY_SEED);
if (threadIdx.x == 0)
{
int i = 1;
int j = 0;
int k;
uint mti; /* g_seeds[i] */
uint mtj; /* g_seeds[i - 1] */
mti = g_seeds[blockIdx.x][0];
for (k = N > length ? N : length; k != 0; k--)
{
mtj = mti;
mti = g_seeds[blockIdx.x][i];
mti = (mti ^ ((mtj ^ (mtj >> 30)) * 1664525)) + seeds[j] + j;
g_seeds[blockIdx.x][i] = mti;
if (++i >= N)
{
g_seeds[blockIdx.x][0] = mti;
i = 1;
}
if (++j >= length)
{
j = 0;
}
}
for (k = N - 1; k != 0; k--)
{
mtj = mti;
mti = g_seeds[blockIdx.x][i];
mti = (mti ^ ((mtj ^ (mtj >> 30)) * 1566083941)) - i;
g_seeds[blockIdx.x][i] = mti;
if (++i >= N)
{
g_seeds[blockIdx.x][0] = mti;
i = 1;
}
}
g_seeds[blockIdx.x][0] = mtNexti = 0x80000000; /* MSB is 1; assuring non-zero initial array */
}
return;
}
/* Return next MT random by increasing thread ID, Good for 1 - 227 threads.
* Note you should wind back MAX_THREADS to your max requirement
* to keep auto allocation of shared mem to a minimum.
* Best as a general purpose library routine. */
__device__ static uint
mt19937g(void)
{
int kk;
uint y;
const int tid = threadIdx.x;
__shared__ uint seed[MAX_THREADS + 1];
kk = mod(mtNext + tid, N);
__syncthreads(); /* Finish with mtNext & g_seeds ready from last call & init */
seed[tid + 1] = g_seeds[blockIdx.x][mod(kk + 1, N)]; /* Sequential but not aligned */
if (tid == blockDim.x - 1)
{
mtNext = kk + 1;
seed[0] = mtNexti;
mtNexti = seed[blockDim.x];
}
__syncthreads(); /* seed[] ready */
y = (seed[tid] & UPPER_MASK) | (seed[tid + 1] & LOWER_MASK);
y = g_seeds[blockIdx.x][kk < N - M ? kk + M : kk + (M - N)] ^ (y >> 1) ^ mag01[y & 1];
g_seeds[blockIdx.x][kk] = y; /* Does not overlap above reads */
y ^= (y >> 11); /* Tempering */
y ^= (y << 7) & TEMPER1;
y ^= (y << 15) & TEMPER2;
y ^= (y >> 18);
return y;
}
/* Generalised global memory version for any number of threads.
* Note only runs up to 227 at a time, rest loop and block till all done.
* Runs fractional warps at each end so not perfect utilisation.
* Uses 228 words of auto allocated shared mem. */
__device__ static uint
mt19937gl(void)
{
int jj;
int kk;
uint y;
int tid; /* Offset thread ID */
__shared__ uint seed[N - M + 1];
kk = mod(mtNext + threadIdx.x, N); /* G80 limited to 512 threads */
__syncthreads(); /* Finish with mtNext & g_seeds set from init */
if (threadIdx.x == blockDim.x - 1)
{
mtNext = kk + 1; /* Modded next call */
}
jj = 0;
do
{
__syncthreads(); /* g_seeds set from last loop */
tid = threadIdx.x - jj;
if (0 <= tid && tid < N - M)
{
seed[tid + 1] = g_seeds[blockIdx.x][mod(kk + 1, N)]; /* Sequential but not aligned */
y = min(N - M, blockDim.x - jj);
if (tid == y - 1) /* Last thread this loop */
{
seed[0] = mtNexti;
mtNexti = seed[y];
}
}
__syncthreads(); /* seed[] ready */
if (0 <= tid && tid < N - M)
{
y = (seed[tid] & UPPER_MASK) | (seed[tid + 1] & LOWER_MASK);
y = g_seeds[blockIdx.x][kk < N - M ? kk + M : kk + (M - N)] ^ (y >> 1) ^ mag01[y & 1];
g_seeds[blockIdx.x][kk] = y; /* Does not overlap reads above */
}
} while ((jj += N - M) < blockDim.x);
y ^= (y >> 11); /* Tempering */
y ^= (y << 7) & TEMPER1;
y ^= (y << 15) & TEMPER2;
y ^= (y >> 18);
return y;
}
/*************************************************************************************
* This is a shared memory implementation that keeps the full 626 words of state
* in shared memory. Faster for heavy random work where you can afford shared mem. */
__shared__ int mtNexts; /* Start of next block of seeds */
__shared__ uint s_seeds[N + 1];
/* Init by single seed - single threaded as only used once */
__device__ static void
mt19937si(uint seed)
{
int i;
if (threadIdx.x == 0)
{
mtNexts = 0;
s_seeds[0] = seed;
for (i = 1; i < N; i++)
{
seed = (INIT_MULT * (seed ^ (seed >> 30)) + i);
s_seeds[i] = seed;
}
}
__syncthreads(); /* Ensure mtNexts set & needed for mt19937w() */
return;
}
/* Init by array - single threaded as only used once */
__device__ static void
mt19937sai(uint* seeds, uint length)
{
mt19937si(ARRAY_SEED);
if (threadIdx.x == 0)
{
int i = 1;
int j = 0;
int k;
for (k = N > length ? N : length; k != 0; k--)
{
s_seeds[i] = (s_seeds[i] ^ ((s_seeds[i - 1] ^ (s_seeds[i - 1] >> 30)) * 1664525)) + seeds[j] + j;
if (++i >= N)
{
s_seeds[0] = s_seeds[N - 1];
i = 1;
}
if (++j >= length)
{
j = 0;
}
}
for (k = N - 1; k != 0; k--)
{
s_seeds[i] = (s_seeds[i] ^ ((s_seeds[i - 1] ^ (s_seeds[i - 1] >> 30)) * 1566083941)) - i;
if (++i >= N)
{
s_seeds[0] = s_seeds[N - 1];
i = 1;
}
}
s_seeds[0] = 0x80000000; /* MSB is 1; assuring non-zero initial array */
}
__syncthreads(); /* Needed for mt19937w() */
return;
}
/* Return next MT random by increasing thread ID for 1-227 threads. */
__device__ static uint
mt19937s(void)
{
int kk;
uint y;
const int tid = threadIdx.x;
kk = mod(mtNexts + tid, N);
__syncthreads(); /* Finished with mtNexts & s_seed[] ready from last run */
if (tid == blockDim.x - 1)
{
mtNexts = kk + 1; /* Will get modded on next call */
}
y = (s_seeds[kk] & UPPER_MASK) | (s_seeds[kk + 1] & LOWER_MASK);
y = s_seeds[kk < N - M ? kk + M : kk + (M - N)] ^ (y >> 1) ^ mag01[y & 1];
//y = s_seeds[kk < N - M ? kk + M : kk + (M - N)] ^ (y >> 1) ^ (y & 1 ? MATRIX_A : 0); // Same speed
__syncthreads(); /* All done before we update */
s_seeds[kk] = y;
if (kk == 0) /* Copy up for next round */
{
s_seeds[N] = y;
}
y ^= (y >> 11); /* Tempering */
y ^= (y << 7) & TEMPER1;
y ^= (y << 15) & TEMPER2;
y ^= (y >> 18);
return y;
}
/* General shared memory version for any number of threads.
* Note only up to 227 threads are run at any one time,
* the rest loop and block till all are done. */
__device__ static uint
mt19937sl(void)
{
int jj;
int kk;
uint y;
int tid; /* Offset thread ID */
kk = mod(mtNexts + threadIdx.x, N); /* G80 limited to 512 threads */
__syncthreads(); /* Finished with mtNexts & s_seed[] ready from init */
if (threadIdx.x == blockDim.x - 1)
{
mtNexts = kk + 1; /* Will get modded on next call */
}
jj = 0;
do
{
__syncthreads(); /* s_seeds[] ready from last loop */
tid = threadIdx.x - jj;
if (0 <= tid && tid < N - M)
{
y = (s_seeds[kk] & UPPER_MASK) | (s_seeds[kk + 1] & LOWER_MASK);
y = s_seeds[kk < N - M ? kk + M : kk + (M - N)] ^ (y >> 1) ^ mag01[y & 1];
}
__syncthreads(); /* All done before we update */
if (0 <= tid && tid < N - M)
{
s_seeds[kk] = y;
if (kk == 0)
{
s_seeds[N] = y;
}
}
} while ((jj += N - M) < blockDim.x);
y ^= (y >> 11); /* Tempering */
y ^= (y << 7) & TEMPER1;
y ^= (y << 15) & TEMPER2;
y ^= (y >> 18);
return y;
}
/***************************************************************************************
* This is an implementation of a full step in 1 call - all 624 results returned at once
* in pairs - 64 bit version. It may be run with 227-312 threads and will drop numbers
* from the sequence if < 312 (not incorrect).
* Original idea for this version was first presented by Brian Budge. */
#define B2 224 /* Size of second block */
__device__ static uint2
mt19937w(const int tid)
{
int kk;
uint y;
uint2 ret;
kk = tid;
/* First 227 */
if (kk < N-M) {
y = (s_seeds[kk]&UPPER_MASK)|(s_seeds[kk+1]&LOWER_MASK);
y = s_seeds[kk+M] ^ (y >> 1) ^ mag01[y & 1];
}
__syncthreads();
if (kk < N-M) {
s_seeds[kk] = y;
if (kk == 0)
{
s_seeds[N] = y;
}
}
kk += N-M;
__syncthreads();
/* Next 224 */
if (kk < N-M + B2) {
y = (s_seeds[kk]&UPPER_MASK)|(s_seeds[kk+1]&LOWER_MASK);
y = s_seeds[kk+(M-N)] ^ (y >> 1) ^ mag01[y & 1];
}
__syncthreads();
if (kk < N-M + B2) {
s_seeds[kk] = y;
}
kk += B2;
__syncthreads();
/* Last 173 */
if (kk < N) {
y = (s_seeds[kk]&UPPER_MASK)|(s_seeds[kk+1]&LOWER_MASK);
y = s_seeds[kk+(M-N)] ^ (y >> 1) ^ mag01[y & 1];
}
__syncthreads();
if (kk < N) {
s_seeds[kk] = y;
}
__syncthreads();
ret.x = s_seeds[2*tid];
ret.x ^= (ret.x >> 11); /* Tempering */
ret.x ^= (ret.x << 7) & TEMPER1;
ret.x ^= (ret.x << 15) & TEMPER2;
ret.x ^= (ret.x >> 18);
ret.y = s_seeds[2*tid+1];
ret.y ^= (ret.y >> 11);
ret.y ^= (ret.y << 7) & TEMPER1;
ret.y ^= (ret.y << 15) & TEMPER2;
ret.y ^= (ret.y >> 18);
return ret;
}
/*******************************************************************************
* For reference this is the original C single threaded source: */
#if 0
static unsigned long mt[N]; /* the array for the state vector */
static int mti=N+1; /* mti==N+1 means mt[N] is not initialized */
/* initializes mt[N] with a seed */
void init_genrand(unsigned long s)
{
mt[0]= s & 0xffffffffUL;
for (mti=1; mti<N; mti++) {
mt[mti] =
(1812433253UL * (mt[mti-1] ^ (mt[mti-1] >> 30)) + mti);
/* See Knuth TAOCP Vol2. 3rd Ed. P.106 for multiplier. */
/* In the previous versions, MSBs of the seed affect */
/* only MSBs of the array mt[]. */
/* 2002/01/09 modified by Makoto Matsumoto */
mt[mti] &= 0xffffffffUL;
/* for >32 bit machines */
}
}
/* initialize by an array with array-length */
/* init_key is the array for initializing keys */
/* key_length is its length */
/* slight change for C++, 2004/2/26 */
void init_by_array(unsigned long init_key[], int key_length)
{
int i, j, k;
init_genrand(19650218UL);
i=1; j=0;
k = (N>key_length ? N : key_length);
for (; k; k--) {
mt[i] = (mt[i] ^ ((mt[i-1] ^ (mt[i-1] >> 30)) * 1664525UL))
+ init_key[j] + j; /* non linear */
mt[i] &= 0xffffffffUL; /* for WORDSIZE > 32 machines */
i++; j++;
if (i>=N) { mt[0] = mt[N-1]; i=1; }
if (j>=key_length) j=0;
}
for (k=N-1; k; k--) {
mt[i] = (mt[i] ^ ((mt[i-1] ^ (mt[i-1] >> 30)) * 1566083941UL))
- i; /* non linear */
mt[i] &= 0xffffffffUL; /* for WORDSIZE > 32 machines */
i++;
if (i>=N) { mt[0] = mt[N-1]; i=1; }
}
mt[0] = 0x80000000UL; /* MSB is 1; assuring non-zero initial array */
}
/* generates a random number on [0,0xffffffff]-interval */
unsigned long genrand_int32(void)
{
unsigned long y;
static unsigned long mag01[2]={0x0UL, MATRIX_A};
/* mag01[x] = x * MATRIX_A for x=0,1 */
if (mti >= N) { /* generate N words at one time */
int kk;
if (mti == N+1) /* if init_genrand() has not been called, */
init_genrand(5489UL); /* a default initial seed is used */
for (kk=0;kk<N-M;kk++) {
y = (mt[kk]&UPPER_MASK)|(mt[kk+1]&LOWER_MASK);
mt[kk] = mt[kk+M] ^ (y >> 1) ^ mag01[y & 0x1UL];
}
for (;kk<N-1;kk++) {
y = (mt[kk]&UPPER_MASK)|(mt[kk+1]&LOWER_MASK);
mt[kk] = mt[kk+(M-N)] ^ (y >> 1) ^ mag01[y & 0x1UL];
}
y = (mt[N-1]&UPPER_MASK)|(mt[0]&LOWER_MASK);
mt[N-1] = mt[M-1] ^ (y >> 1) ^ mag01[y & 0x1UL];
mti = 0;
}
y = mt[mti++];
/* Tempering */
y ^= (y >> 11);
y ^= (y << 7) & 0x9d2c5680UL;
y ^= (y << 15) & 0xefc60000UL;
y ^= (y >> 18);
return y;
}
#endif | #include <hip/hip_runtime.h>
/*
A multithreaded C-program for MT19937.
Original single threaded C reference coded by Takuji Nishimurar
and Makoto Matsumoto, with initialization improved 2002/1/26.
Multithreaded C implementation coded by Eric Mills.
Before using, initialize the state by using mt19937gi(seed)
or mt19937gai(init_key, key_length) for the global memory versions or
mt19937si(seed) or mt19937sai(init_key, key_length) for all shared
memory versions.
Copyright (C) 1997 - 2002, Makoto Matsumoto and Takuji Nishimura,
All rights reserved.
Multithreaded implementation Copyright (C) 2007, Eric Mills.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. The names of its contributors may not be used to endorse or promote
products derived from this software without specific prior written
permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Any feedback is very welcome.
http://www.math.sci.hiroshima-u.ac.jp/~m-mat/MT/emt.html
email: m-mat @ math.sci.hiroshima-u.ac.jp (remove space)
*/
#define NVG80 /* For Nvidia G80 achitecture where mod is VERY slow */
#ifdef NVG80
#define mod(x, y) ((x) < (y) ? (x) : (x) - (y)) /* Short mod - known input range */
#else
#define mod(x, y) ((x) % (y))
#endif
#ifdef _WIN32
typedef unsigned int uint;
#endif
#define N 624
#define M 397
#define INIT_MULT 1812433253 /* See Knuth TAOCP Vol2. 3rd Ed. P.106 for multiplier. */
#define ARRAY_SEED 19650218 /* Seed for initial setup before incorp array seed */
#define MATRIX_A 0x9908b0df /* Constant vector a */
#define UPPER_MASK 0x80000000 /* Most significant w-r bits */
#define LOWER_MASK 0x7fffffff /* Least significant r bits */
#define TEMPER1 0x9d2c5680
#define TEMPER2 0xefc60000
/* First a global memory implementation that uses 2 global reads and 1 global
* write per result and keeps only 2 words of state in permanent shared memory. */
#define MAX_THREADS 227 /* Set to minimise shared memory allocation (max blockDim.x) */
#define MAX_BLOCKS 256 /* Set to minimise global memory allocation (max gridDim.x) */
__shared__ int mtNext; /* Start of next block of seeds */
__shared__ uint mtNexti; /* Indirect on above to save global read cycle */
__device__ uint g_seeds[MAX_BLOCKS][N];
__constant__ uint mag01[2] = {0, MATRIX_A}; /* 2 way bus conflict for each read */
/* Init by single seed - single threaded as only used once */
__device__ static void
mt19937gi(uint seed)
{
int i;
mtNext = 0;
if (threadIdx.x == 0)
{
g_seeds[blockIdx.x][0] = mtNexti = seed;
for (i = 1; i < N; i++)
{
seed = (INIT_MULT * (seed ^ (seed >> 30)) + i);
g_seeds[blockIdx.x][i] = seed;
}
}
return;
}
/* Init by array - single threaded as only used once, opt to reduce global refs */
__device__ static void
mt19937gai(uint* seeds, uint length)
{
mt19937gi(ARRAY_SEED);
if (threadIdx.x == 0)
{
int i = 1;
int j = 0;
int k;
uint mti; /* g_seeds[i] */
uint mtj; /* g_seeds[i - 1] */
mti = g_seeds[blockIdx.x][0];
for (k = N > length ? N : length; k != 0; k--)
{
mtj = mti;
mti = g_seeds[blockIdx.x][i];
mti = (mti ^ ((mtj ^ (mtj >> 30)) * 1664525)) + seeds[j] + j;
g_seeds[blockIdx.x][i] = mti;
if (++i >= N)
{
g_seeds[blockIdx.x][0] = mti;
i = 1;
}
if (++j >= length)
{
j = 0;
}
}
for (k = N - 1; k != 0; k--)
{
mtj = mti;
mti = g_seeds[blockIdx.x][i];
mti = (mti ^ ((mtj ^ (mtj >> 30)) * 1566083941)) - i;
g_seeds[blockIdx.x][i] = mti;
if (++i >= N)
{
g_seeds[blockIdx.x][0] = mti;
i = 1;
}
}
g_seeds[blockIdx.x][0] = mtNexti = 0x80000000; /* MSB is 1; assuring non-zero initial array */
}
return;
}
/* Return next MT random by increasing thread ID, Good for 1 - 227 threads.
* Note you should wind back MAX_THREADS to your max requirement
* to keep auto allocation of shared mem to a minimum.
* Best as a general purpose library routine. */
__device__ static uint
mt19937g(void)
{
int kk;
uint y;
const int tid = threadIdx.x;
__shared__ uint seed[MAX_THREADS + 1];
kk = mod(mtNext + tid, N);
__syncthreads(); /* Finish with mtNext & g_seeds ready from last call & init */
seed[tid + 1] = g_seeds[blockIdx.x][mod(kk + 1, N)]; /* Sequential but not aligned */
if (tid == blockDim.x - 1)
{
mtNext = kk + 1;
seed[0] = mtNexti;
mtNexti = seed[blockDim.x];
}
__syncthreads(); /* seed[] ready */
y = (seed[tid] & UPPER_MASK) | (seed[tid + 1] & LOWER_MASK);
y = g_seeds[blockIdx.x][kk < N - M ? kk + M : kk + (M - N)] ^ (y >> 1) ^ mag01[y & 1];
g_seeds[blockIdx.x][kk] = y; /* Does not overlap above reads */
y ^= (y >> 11); /* Tempering */
y ^= (y << 7) & TEMPER1;
y ^= (y << 15) & TEMPER2;
y ^= (y >> 18);
return y;
}
/* Generalised global memory version for any number of threads.
* Note only runs up to 227 at a time, rest loop and block till all done.
* Runs fractional warps at each end so not perfect utilisation.
* Uses 228 words of auto allocated shared mem. */
__device__ static uint
mt19937gl(void)
{
int jj;
int kk;
uint y;
int tid; /* Offset thread ID */
__shared__ uint seed[N - M + 1];
kk = mod(mtNext + threadIdx.x, N); /* G80 limited to 512 threads */
__syncthreads(); /* Finish with mtNext & g_seeds set from init */
if (threadIdx.x == blockDim.x - 1)
{
mtNext = kk + 1; /* Modded next call */
}
jj = 0;
do
{
__syncthreads(); /* g_seeds set from last loop */
tid = threadIdx.x - jj;
if (0 <= tid && tid < N - M)
{
seed[tid + 1] = g_seeds[blockIdx.x][mod(kk + 1, N)]; /* Sequential but not aligned */
y = min(N - M, blockDim.x - jj);
if (tid == y - 1) /* Last thread this loop */
{
seed[0] = mtNexti;
mtNexti = seed[y];
}
}
__syncthreads(); /* seed[] ready */
if (0 <= tid && tid < N - M)
{
y = (seed[tid] & UPPER_MASK) | (seed[tid + 1] & LOWER_MASK);
y = g_seeds[blockIdx.x][kk < N - M ? kk + M : kk + (M - N)] ^ (y >> 1) ^ mag01[y & 1];
g_seeds[blockIdx.x][kk] = y; /* Does not overlap reads above */
}
} while ((jj += N - M) < blockDim.x);
y ^= (y >> 11); /* Tempering */
y ^= (y << 7) & TEMPER1;
y ^= (y << 15) & TEMPER2;
y ^= (y >> 18);
return y;
}
/*************************************************************************************
* This is a shared memory implementation that keeps the full 626 words of state
* in shared memory. Faster for heavy random work where you can afford shared mem. */
__shared__ int mtNexts; /* Start of next block of seeds */
__shared__ uint s_seeds[N + 1];
/* Init by single seed - single threaded as only used once */
__device__ static void
mt19937si(uint seed)
{
int i;
if (threadIdx.x == 0)
{
mtNexts = 0;
s_seeds[0] = seed;
for (i = 1; i < N; i++)
{
seed = (INIT_MULT * (seed ^ (seed >> 30)) + i);
s_seeds[i] = seed;
}
}
__syncthreads(); /* Ensure mtNexts set & needed for mt19937w() */
return;
}
/* Init by array - single threaded as only used once */
__device__ static void
mt19937sai(uint* seeds, uint length)
{
mt19937si(ARRAY_SEED);
if (threadIdx.x == 0)
{
int i = 1;
int j = 0;
int k;
for (k = N > length ? N : length; k != 0; k--)
{
s_seeds[i] = (s_seeds[i] ^ ((s_seeds[i - 1] ^ (s_seeds[i - 1] >> 30)) * 1664525)) + seeds[j] + j;
if (++i >= N)
{
s_seeds[0] = s_seeds[N - 1];
i = 1;
}
if (++j >= length)
{
j = 0;
}
}
for (k = N - 1; k != 0; k--)
{
s_seeds[i] = (s_seeds[i] ^ ((s_seeds[i - 1] ^ (s_seeds[i - 1] >> 30)) * 1566083941)) - i;
if (++i >= N)
{
s_seeds[0] = s_seeds[N - 1];
i = 1;
}
}
s_seeds[0] = 0x80000000; /* MSB is 1; assuring non-zero initial array */
}
__syncthreads(); /* Needed for mt19937w() */
return;
}
/* Return next MT random by increasing thread ID for 1-227 threads. */
__device__ static uint
mt19937s(void)
{
int kk;
uint y;
const int tid = threadIdx.x;
kk = mod(mtNexts + tid, N);
__syncthreads(); /* Finished with mtNexts & s_seed[] ready from last run */
if (tid == blockDim.x - 1)
{
mtNexts = kk + 1; /* Will get modded on next call */
}
y = (s_seeds[kk] & UPPER_MASK) | (s_seeds[kk + 1] & LOWER_MASK);
y = s_seeds[kk < N - M ? kk + M : kk + (M - N)] ^ (y >> 1) ^ mag01[y & 1];
//y = s_seeds[kk < N - M ? kk + M : kk + (M - N)] ^ (y >> 1) ^ (y & 1 ? MATRIX_A : 0); // Same speed
__syncthreads(); /* All done before we update */
s_seeds[kk] = y;
if (kk == 0) /* Copy up for next round */
{
s_seeds[N] = y;
}
y ^= (y >> 11); /* Tempering */
y ^= (y << 7) & TEMPER1;
y ^= (y << 15) & TEMPER2;
y ^= (y >> 18);
return y;
}
/* General shared memory version for any number of threads.
* Note only up to 227 threads are run at any one time,
* the rest loop and block till all are done. */
__device__ static uint
mt19937sl(void)
{
int jj;
int kk;
uint y;
int tid; /* Offset thread ID */
kk = mod(mtNexts + threadIdx.x, N); /* G80 limited to 512 threads */
__syncthreads(); /* Finished with mtNexts & s_seed[] ready from init */
if (threadIdx.x == blockDim.x - 1)
{
mtNexts = kk + 1; /* Will get modded on next call */
}
jj = 0;
do
{
__syncthreads(); /* s_seeds[] ready from last loop */
tid = threadIdx.x - jj;
if (0 <= tid && tid < N - M)
{
y = (s_seeds[kk] & UPPER_MASK) | (s_seeds[kk + 1] & LOWER_MASK);
y = s_seeds[kk < N - M ? kk + M : kk + (M - N)] ^ (y >> 1) ^ mag01[y & 1];
}
__syncthreads(); /* All done before we update */
if (0 <= tid && tid < N - M)
{
s_seeds[kk] = y;
if (kk == 0)
{
s_seeds[N] = y;
}
}
} while ((jj += N - M) < blockDim.x);
y ^= (y >> 11); /* Tempering */
y ^= (y << 7) & TEMPER1;
y ^= (y << 15) & TEMPER2;
y ^= (y >> 18);
return y;
}
/***************************************************************************************
* This is an implementation of a full step in 1 call - all 624 results returned at once
* in pairs - 64 bit version. It may be run with 227-312 threads and will drop numbers
* from the sequence if < 312 (not incorrect).
* Original idea for this version was first presented by Brian Budge. */
#define B2 224 /* Size of second block */
__device__ static uint2
mt19937w(const int tid)
{
int kk;
uint y;
uint2 ret;
kk = tid;
/* First 227 */
if (kk < N-M) {
y = (s_seeds[kk]&UPPER_MASK)|(s_seeds[kk+1]&LOWER_MASK);
y = s_seeds[kk+M] ^ (y >> 1) ^ mag01[y & 1];
}
__syncthreads();
if (kk < N-M) {
s_seeds[kk] = y;
if (kk == 0)
{
s_seeds[N] = y;
}
}
kk += N-M;
__syncthreads();
/* Next 224 */
if (kk < N-M + B2) {
y = (s_seeds[kk]&UPPER_MASK)|(s_seeds[kk+1]&LOWER_MASK);
y = s_seeds[kk+(M-N)] ^ (y >> 1) ^ mag01[y & 1];
}
__syncthreads();
if (kk < N-M + B2) {
s_seeds[kk] = y;
}
kk += B2;
__syncthreads();
/* Last 173 */
if (kk < N) {
y = (s_seeds[kk]&UPPER_MASK)|(s_seeds[kk+1]&LOWER_MASK);
y = s_seeds[kk+(M-N)] ^ (y >> 1) ^ mag01[y & 1];
}
__syncthreads();
if (kk < N) {
s_seeds[kk] = y;
}
__syncthreads();
ret.x = s_seeds[2*tid];
ret.x ^= (ret.x >> 11); /* Tempering */
ret.x ^= (ret.x << 7) & TEMPER1;
ret.x ^= (ret.x << 15) & TEMPER2;
ret.x ^= (ret.x >> 18);
ret.y = s_seeds[2*tid+1];
ret.y ^= (ret.y >> 11);
ret.y ^= (ret.y << 7) & TEMPER1;
ret.y ^= (ret.y << 15) & TEMPER2;
ret.y ^= (ret.y >> 18);
return ret;
}
/*******************************************************************************
* For reference this is the original C single threaded source: */
#if 0
static unsigned long mt[N]; /* the array for the state vector */
static int mti=N+1; /* mti==N+1 means mt[N] is not initialized */
/* initializes mt[N] with a seed */
void init_genrand(unsigned long s)
{
mt[0]= s & 0xffffffffUL;
for (mti=1; mti<N; mti++) {
mt[mti] =
(1812433253UL * (mt[mti-1] ^ (mt[mti-1] >> 30)) + mti);
/* See Knuth TAOCP Vol2. 3rd Ed. P.106 for multiplier. */
/* In the previous versions, MSBs of the seed affect */
/* only MSBs of the array mt[]. */
/* 2002/01/09 modified by Makoto Matsumoto */
mt[mti] &= 0xffffffffUL;
/* for >32 bit machines */
}
}
/* initialize by an array with array-length */
/* init_key is the array for initializing keys */
/* key_length is its length */
/* slight change for C++, 2004/2/26 */
void init_by_array(unsigned long init_key[], int key_length)
{
int i, j, k;
init_genrand(19650218UL);
i=1; j=0;
k = (N>key_length ? N : key_length);
for (; k; k--) {
mt[i] = (mt[i] ^ ((mt[i-1] ^ (mt[i-1] >> 30)) * 1664525UL))
+ init_key[j] + j; /* non linear */
mt[i] &= 0xffffffffUL; /* for WORDSIZE > 32 machines */
i++; j++;
if (i>=N) { mt[0] = mt[N-1]; i=1; }
if (j>=key_length) j=0;
}
for (k=N-1; k; k--) {
mt[i] = (mt[i] ^ ((mt[i-1] ^ (mt[i-1] >> 30)) * 1566083941UL))
- i; /* non linear */
mt[i] &= 0xffffffffUL; /* for WORDSIZE > 32 machines */
i++;
if (i>=N) { mt[0] = mt[N-1]; i=1; }
}
mt[0] = 0x80000000UL; /* MSB is 1; assuring non-zero initial array */
}
/* generates a random number on [0,0xffffffff]-interval */
unsigned long genrand_int32(void)
{
unsigned long y;
static unsigned long mag01[2]={0x0UL, MATRIX_A};
/* mag01[x] = x * MATRIX_A for x=0,1 */
if (mti >= N) { /* generate N words at one time */
int kk;
if (mti == N+1) /* if init_genrand() has not been called, */
init_genrand(5489UL); /* a default initial seed is used */
for (kk=0;kk<N-M;kk++) {
y = (mt[kk]&UPPER_MASK)|(mt[kk+1]&LOWER_MASK);
mt[kk] = mt[kk+M] ^ (y >> 1) ^ mag01[y & 0x1UL];
}
for (;kk<N-1;kk++) {
y = (mt[kk]&UPPER_MASK)|(mt[kk+1]&LOWER_MASK);
mt[kk] = mt[kk+(M-N)] ^ (y >> 1) ^ mag01[y & 0x1UL];
}
y = (mt[N-1]&UPPER_MASK)|(mt[0]&LOWER_MASK);
mt[N-1] = mt[M-1] ^ (y >> 1) ^ mag01[y & 0x1UL];
mti = 0;
}
y = mt[mti++];
/* Tempering */
y ^= (y >> 11);
y ^= (y << 7) & 0x9d2c5680UL;
y ^= (y << 15) & 0xefc60000UL;
y ^= (y >> 18);
return y;
}
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/*
A multithreaded C-program for MT19937.
Original single threaded C reference coded by Takuji Nishimurar
and Makoto Matsumoto, with initialization improved 2002/1/26.
Multithreaded C implementation coded by Eric Mills.
Before using, initialize the state by using mt19937gi(seed)
or mt19937gai(init_key, key_length) for the global memory versions or
mt19937si(seed) or mt19937sai(init_key, key_length) for all shared
memory versions.
Copyright (C) 1997 - 2002, Makoto Matsumoto and Takuji Nishimura,
All rights reserved.
Multithreaded implementation Copyright (C) 2007, Eric Mills.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. The names of its contributors may not be used to endorse or promote
products derived from this software without specific prior written
permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Any feedback is very welcome.
http://www.math.sci.hiroshima-u.ac.jp/~m-mat/MT/emt.html
email: m-mat @ math.sci.hiroshima-u.ac.jp (remove space)
*/
#define NVG80 /* For Nvidia G80 achitecture where mod is VERY slow */
#ifdef NVG80
#define mod(x, y) ((x) < (y) ? (x) : (x) - (y)) /* Short mod - known input range */
#else
#define mod(x, y) ((x) % (y))
#endif
#ifdef _WIN32
typedef unsigned int uint;
#endif
#define N 624
#define M 397
#define INIT_MULT 1812433253 /* See Knuth TAOCP Vol2. 3rd Ed. P.106 for multiplier. */
#define ARRAY_SEED 19650218 /* Seed for initial setup before incorp array seed */
#define MATRIX_A 0x9908b0df /* Constant vector a */
#define UPPER_MASK 0x80000000 /* Most significant w-r bits */
#define LOWER_MASK 0x7fffffff /* Least significant r bits */
#define TEMPER1 0x9d2c5680
#define TEMPER2 0xefc60000
/* First a global memory implementation that uses 2 global reads and 1 global
* write per result and keeps only 2 words of state in permanent shared memory. */
#define MAX_THREADS 227 /* Set to minimise shared memory allocation (max blockDim.x) */
#define MAX_BLOCKS 256 /* Set to minimise global memory allocation (max gridDim.x) */
__shared__ int mtNext; /* Start of next block of seeds */
__shared__ uint mtNexti; /* Indirect on above to save global read cycle */
__device__ uint g_seeds[MAX_BLOCKS][N];
__constant__ uint mag01[2] = {0, MATRIX_A}; /* 2 way bus conflict for each read */
/* Init by single seed - single threaded as only used once */
__device__ static void
mt19937gi(uint seed)
{
int i;
mtNext = 0;
if (threadIdx.x == 0)
{
g_seeds[blockIdx.x][0] = mtNexti = seed;
for (i = 1; i < N; i++)
{
seed = (INIT_MULT * (seed ^ (seed >> 30)) + i);
g_seeds[blockIdx.x][i] = seed;
}
}
return;
}
/* Init by array - single threaded as only used once, opt to reduce global refs */
__device__ static void
mt19937gai(uint* seeds, uint length)
{
mt19937gi(ARRAY_SEED);
if (threadIdx.x == 0)
{
int i = 1;
int j = 0;
int k;
uint mti; /* g_seeds[i] */
uint mtj; /* g_seeds[i - 1] */
mti = g_seeds[blockIdx.x][0];
for (k = N > length ? N : length; k != 0; k--)
{
mtj = mti;
mti = g_seeds[blockIdx.x][i];
mti = (mti ^ ((mtj ^ (mtj >> 30)) * 1664525)) + seeds[j] + j;
g_seeds[blockIdx.x][i] = mti;
if (++i >= N)
{
g_seeds[blockIdx.x][0] = mti;
i = 1;
}
if (++j >= length)
{
j = 0;
}
}
for (k = N - 1; k != 0; k--)
{
mtj = mti;
mti = g_seeds[blockIdx.x][i];
mti = (mti ^ ((mtj ^ (mtj >> 30)) * 1566083941)) - i;
g_seeds[blockIdx.x][i] = mti;
if (++i >= N)
{
g_seeds[blockIdx.x][0] = mti;
i = 1;
}
}
g_seeds[blockIdx.x][0] = mtNexti = 0x80000000; /* MSB is 1; assuring non-zero initial array */
}
return;
}
/* Return next MT random by increasing thread ID, Good for 1 - 227 threads.
* Note you should wind back MAX_THREADS to your max requirement
* to keep auto allocation of shared mem to a minimum.
* Best as a general purpose library routine. */
__device__ static uint
mt19937g(void)
{
int kk;
uint y;
const int tid = threadIdx.x;
__shared__ uint seed[MAX_THREADS + 1];
kk = mod(mtNext + tid, N);
__syncthreads(); /* Finish with mtNext & g_seeds ready from last call & init */
seed[tid + 1] = g_seeds[blockIdx.x][mod(kk + 1, N)]; /* Sequential but not aligned */
if (tid == blockDim.x - 1)
{
mtNext = kk + 1;
seed[0] = mtNexti;
mtNexti = seed[blockDim.x];
}
__syncthreads(); /* seed[] ready */
y = (seed[tid] & UPPER_MASK) | (seed[tid + 1] & LOWER_MASK);
y = g_seeds[blockIdx.x][kk < N - M ? kk + M : kk + (M - N)] ^ (y >> 1) ^ mag01[y & 1];
g_seeds[blockIdx.x][kk] = y; /* Does not overlap above reads */
y ^= (y >> 11); /* Tempering */
y ^= (y << 7) & TEMPER1;
y ^= (y << 15) & TEMPER2;
y ^= (y >> 18);
return y;
}
/* Generalised global memory version for any number of threads.
* Note only runs up to 227 at a time, rest loop and block till all done.
* Runs fractional warps at each end so not perfect utilisation.
* Uses 228 words of auto allocated shared mem. */
__device__ static uint
mt19937gl(void)
{
int jj;
int kk;
uint y;
int tid; /* Offset thread ID */
__shared__ uint seed[N - M + 1];
kk = mod(mtNext + threadIdx.x, N); /* G80 limited to 512 threads */
__syncthreads(); /* Finish with mtNext & g_seeds set from init */
if (threadIdx.x == blockDim.x - 1)
{
mtNext = kk + 1; /* Modded next call */
}
jj = 0;
do
{
__syncthreads(); /* g_seeds set from last loop */
tid = threadIdx.x - jj;
if (0 <= tid && tid < N - M)
{
seed[tid + 1] = g_seeds[blockIdx.x][mod(kk + 1, N)]; /* Sequential but not aligned */
y = min(N - M, blockDim.x - jj);
if (tid == y - 1) /* Last thread this loop */
{
seed[0] = mtNexti;
mtNexti = seed[y];
}
}
__syncthreads(); /* seed[] ready */
if (0 <= tid && tid < N - M)
{
y = (seed[tid] & UPPER_MASK) | (seed[tid + 1] & LOWER_MASK);
y = g_seeds[blockIdx.x][kk < N - M ? kk + M : kk + (M - N)] ^ (y >> 1) ^ mag01[y & 1];
g_seeds[blockIdx.x][kk] = y; /* Does not overlap reads above */
}
} while ((jj += N - M) < blockDim.x);
y ^= (y >> 11); /* Tempering */
y ^= (y << 7) & TEMPER1;
y ^= (y << 15) & TEMPER2;
y ^= (y >> 18);
return y;
}
/*************************************************************************************
* This is a shared memory implementation that keeps the full 626 words of state
* in shared memory. Faster for heavy random work where you can afford shared mem. */
__shared__ int mtNexts; /* Start of next block of seeds */
__shared__ uint s_seeds[N + 1];
/* Init by single seed - single threaded as only used once */
__device__ static void
mt19937si(uint seed)
{
int i;
if (threadIdx.x == 0)
{
mtNexts = 0;
s_seeds[0] = seed;
for (i = 1; i < N; i++)
{
seed = (INIT_MULT * (seed ^ (seed >> 30)) + i);
s_seeds[i] = seed;
}
}
__syncthreads(); /* Ensure mtNexts set & needed for mt19937w() */
return;
}
/* Init by array - single threaded as only used once */
__device__ static void
mt19937sai(uint* seeds, uint length)
{
mt19937si(ARRAY_SEED);
if (threadIdx.x == 0)
{
int i = 1;
int j = 0;
int k;
for (k = N > length ? N : length; k != 0; k--)
{
s_seeds[i] = (s_seeds[i] ^ ((s_seeds[i - 1] ^ (s_seeds[i - 1] >> 30)) * 1664525)) + seeds[j] + j;
if (++i >= N)
{
s_seeds[0] = s_seeds[N - 1];
i = 1;
}
if (++j >= length)
{
j = 0;
}
}
for (k = N - 1; k != 0; k--)
{
s_seeds[i] = (s_seeds[i] ^ ((s_seeds[i - 1] ^ (s_seeds[i - 1] >> 30)) * 1566083941)) - i;
if (++i >= N)
{
s_seeds[0] = s_seeds[N - 1];
i = 1;
}
}
s_seeds[0] = 0x80000000; /* MSB is 1; assuring non-zero initial array */
}
__syncthreads(); /* Needed for mt19937w() */
return;
}
/* Return next MT random by increasing thread ID for 1-227 threads. */
__device__ static uint
mt19937s(void)
{
int kk;
uint y;
const int tid = threadIdx.x;
kk = mod(mtNexts + tid, N);
__syncthreads(); /* Finished with mtNexts & s_seed[] ready from last run */
if (tid == blockDim.x - 1)
{
mtNexts = kk + 1; /* Will get modded on next call */
}
y = (s_seeds[kk] & UPPER_MASK) | (s_seeds[kk + 1] & LOWER_MASK);
y = s_seeds[kk < N - M ? kk + M : kk + (M - N)] ^ (y >> 1) ^ mag01[y & 1];
//y = s_seeds[kk < N - M ? kk + M : kk + (M - N)] ^ (y >> 1) ^ (y & 1 ? MATRIX_A : 0); // Same speed
__syncthreads(); /* All done before we update */
s_seeds[kk] = y;
if (kk == 0) /* Copy up for next round */
{
s_seeds[N] = y;
}
y ^= (y >> 11); /* Tempering */
y ^= (y << 7) & TEMPER1;
y ^= (y << 15) & TEMPER2;
y ^= (y >> 18);
return y;
}
/* General shared memory version for any number of threads.
* Note only up to 227 threads are run at any one time,
* the rest loop and block till all are done. */
__device__ static uint
mt19937sl(void)
{
int jj;
int kk;
uint y;
int tid; /* Offset thread ID */
kk = mod(mtNexts + threadIdx.x, N); /* G80 limited to 512 threads */
__syncthreads(); /* Finished with mtNexts & s_seed[] ready from init */
if (threadIdx.x == blockDim.x - 1)
{
mtNexts = kk + 1; /* Will get modded on next call */
}
jj = 0;
do
{
__syncthreads(); /* s_seeds[] ready from last loop */
tid = threadIdx.x - jj;
if (0 <= tid && tid < N - M)
{
y = (s_seeds[kk] & UPPER_MASK) | (s_seeds[kk + 1] & LOWER_MASK);
y = s_seeds[kk < N - M ? kk + M : kk + (M - N)] ^ (y >> 1) ^ mag01[y & 1];
}
__syncthreads(); /* All done before we update */
if (0 <= tid && tid < N - M)
{
s_seeds[kk] = y;
if (kk == 0)
{
s_seeds[N] = y;
}
}
} while ((jj += N - M) < blockDim.x);
y ^= (y >> 11); /* Tempering */
y ^= (y << 7) & TEMPER1;
y ^= (y << 15) & TEMPER2;
y ^= (y >> 18);
return y;
}
/***************************************************************************************
* This is an implementation of a full step in 1 call - all 624 results returned at once
* in pairs - 64 bit version. It may be run with 227-312 threads and will drop numbers
* from the sequence if < 312 (not incorrect).
* Original idea for this version was first presented by Brian Budge. */
#define B2 224 /* Size of second block */
__device__ static uint2
mt19937w(const int tid)
{
int kk;
uint y;
uint2 ret;
kk = tid;
/* First 227 */
if (kk < N-M) {
y = (s_seeds[kk]&UPPER_MASK)|(s_seeds[kk+1]&LOWER_MASK);
y = s_seeds[kk+M] ^ (y >> 1) ^ mag01[y & 1];
}
__syncthreads();
if (kk < N-M) {
s_seeds[kk] = y;
if (kk == 0)
{
s_seeds[N] = y;
}
}
kk += N-M;
__syncthreads();
/* Next 224 */
if (kk < N-M + B2) {
y = (s_seeds[kk]&UPPER_MASK)|(s_seeds[kk+1]&LOWER_MASK);
y = s_seeds[kk+(M-N)] ^ (y >> 1) ^ mag01[y & 1];
}
__syncthreads();
if (kk < N-M + B2) {
s_seeds[kk] = y;
}
kk += B2;
__syncthreads();
/* Last 173 */
if (kk < N) {
y = (s_seeds[kk]&UPPER_MASK)|(s_seeds[kk+1]&LOWER_MASK);
y = s_seeds[kk+(M-N)] ^ (y >> 1) ^ mag01[y & 1];
}
__syncthreads();
if (kk < N) {
s_seeds[kk] = y;
}
__syncthreads();
ret.x = s_seeds[2*tid];
ret.x ^= (ret.x >> 11); /* Tempering */
ret.x ^= (ret.x << 7) & TEMPER1;
ret.x ^= (ret.x << 15) & TEMPER2;
ret.x ^= (ret.x >> 18);
ret.y = s_seeds[2*tid+1];
ret.y ^= (ret.y >> 11);
ret.y ^= (ret.y << 7) & TEMPER1;
ret.y ^= (ret.y << 15) & TEMPER2;
ret.y ^= (ret.y >> 18);
return ret;
}
/*******************************************************************************
* For reference this is the original C single threaded source: */
#if 0
static unsigned long mt[N]; /* the array for the state vector */
static int mti=N+1; /* mti==N+1 means mt[N] is not initialized */
/* initializes mt[N] with a seed */
void init_genrand(unsigned long s)
{
mt[0]= s & 0xffffffffUL;
for (mti=1; mti<N; mti++) {
mt[mti] =
(1812433253UL * (mt[mti-1] ^ (mt[mti-1] >> 30)) + mti);
/* See Knuth TAOCP Vol2. 3rd Ed. P.106 for multiplier. */
/* In the previous versions, MSBs of the seed affect */
/* only MSBs of the array mt[]. */
/* 2002/01/09 modified by Makoto Matsumoto */
mt[mti] &= 0xffffffffUL;
/* for >32 bit machines */
}
}
/* initialize by an array with array-length */
/* init_key is the array for initializing keys */
/* key_length is its length */
/* slight change for C++, 2004/2/26 */
void init_by_array(unsigned long init_key[], int key_length)
{
int i, j, k;
init_genrand(19650218UL);
i=1; j=0;
k = (N>key_length ? N : key_length);
for (; k; k--) {
mt[i] = (mt[i] ^ ((mt[i-1] ^ (mt[i-1] >> 30)) * 1664525UL))
+ init_key[j] + j; /* non linear */
mt[i] &= 0xffffffffUL; /* for WORDSIZE > 32 machines */
i++; j++;
if (i>=N) { mt[0] = mt[N-1]; i=1; }
if (j>=key_length) j=0;
}
for (k=N-1; k; k--) {
mt[i] = (mt[i] ^ ((mt[i-1] ^ (mt[i-1] >> 30)) * 1566083941UL))
- i; /* non linear */
mt[i] &= 0xffffffffUL; /* for WORDSIZE > 32 machines */
i++;
if (i>=N) { mt[0] = mt[N-1]; i=1; }
}
mt[0] = 0x80000000UL; /* MSB is 1; assuring non-zero initial array */
}
/* generates a random number on [0,0xffffffff]-interval */
unsigned long genrand_int32(void)
{
unsigned long y;
static unsigned long mag01[2]={0x0UL, MATRIX_A};
/* mag01[x] = x * MATRIX_A for x=0,1 */
if (mti >= N) { /* generate N words at one time */
int kk;
if (mti == N+1) /* if init_genrand() has not been called, */
init_genrand(5489UL); /* a default initial seed is used */
for (kk=0;kk<N-M;kk++) {
y = (mt[kk]&UPPER_MASK)|(mt[kk+1]&LOWER_MASK);
mt[kk] = mt[kk+M] ^ (y >> 1) ^ mag01[y & 0x1UL];
}
for (;kk<N-1;kk++) {
y = (mt[kk]&UPPER_MASK)|(mt[kk+1]&LOWER_MASK);
mt[kk] = mt[kk+(M-N)] ^ (y >> 1) ^ mag01[y & 0x1UL];
}
y = (mt[N-1]&UPPER_MASK)|(mt[0]&LOWER_MASK);
mt[N-1] = mt[M-1] ^ (y >> 1) ^ mag01[y & 0x1UL];
mti = 0;
}
y = mt[mti++];
/* Tempering */
y ^= (y >> 11);
y ^= (y << 7) & 0x9d2c5680UL;
y ^= (y << 15) & 0xefc60000UL;
y ^= (y >> 18);
return y;
}
#endif | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected g_seeds
.type g_seeds,@object
.section .bss,"aw",@nobits
.globl g_seeds
.p2align 4, 0x0
g_seeds:
.zero 638976
.size g_seeds, 638976
.protected mag01
.type mag01,@object
.data
.globl mag01
.p2align 2, 0x0
mag01:
.long 0
.long 2567483615
.size mag01, 8
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym g_seeds
.addrsig_sym mag01
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*
A multithreaded C-program for MT19937.
Original single threaded C reference coded by Takuji Nishimurar
and Makoto Matsumoto, with initialization improved 2002/1/26.
Multithreaded C implementation coded by Eric Mills.
Before using, initialize the state by using mt19937gi(seed)
or mt19937gai(init_key, key_length) for the global memory versions or
mt19937si(seed) or mt19937sai(init_key, key_length) for all shared
memory versions.
Copyright (C) 1997 - 2002, Makoto Matsumoto and Takuji Nishimura,
All rights reserved.
Multithreaded implementation Copyright (C) 2007, Eric Mills.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. The names of its contributors may not be used to endorse or promote
products derived from this software without specific prior written
permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Any feedback is very welcome.
http://www.math.sci.hiroshima-u.ac.jp/~m-mat/MT/emt.html
email: m-mat @ math.sci.hiroshima-u.ac.jp (remove space)
*/
#define NVG80 /* For Nvidia G80 achitecture where mod is VERY slow */
#ifdef NVG80
#define mod(x, y) ((x) < (y) ? (x) : (x) - (y)) /* Short mod - known input range */
#else
#define mod(x, y) ((x) % (y))
#endif
#ifdef _WIN32
typedef unsigned int uint;
#endif
#define N 624
#define M 397
#define INIT_MULT 1812433253 /* See Knuth TAOCP Vol2. 3rd Ed. P.106 for multiplier. */
#define ARRAY_SEED 19650218 /* Seed for initial setup before incorp array seed */
#define MATRIX_A 0x9908b0df /* Constant vector a */
#define UPPER_MASK 0x80000000 /* Most significant w-r bits */
#define LOWER_MASK 0x7fffffff /* Least significant r bits */
#define TEMPER1 0x9d2c5680
#define TEMPER2 0xefc60000
/* First a global memory implementation that uses 2 global reads and 1 global
* write per result and keeps only 2 words of state in permanent shared memory. */
#define MAX_THREADS 227 /* Set to minimise shared memory allocation (max blockDim.x) */
#define MAX_BLOCKS 256 /* Set to minimise global memory allocation (max gridDim.x) */
__shared__ int mtNext; /* Start of next block of seeds */
__shared__ uint mtNexti; /* Indirect on above to save global read cycle */
__device__ uint g_seeds[MAX_BLOCKS][N];
__constant__ uint mag01[2] = {0, MATRIX_A}; /* 2 way bus conflict for each read */
/* Init by single seed - single threaded as only used once */
__device__ static void
mt19937gi(uint seed)
{
int i;
mtNext = 0;
if (threadIdx.x == 0)
{
g_seeds[blockIdx.x][0] = mtNexti = seed;
for (i = 1; i < N; i++)
{
seed = (INIT_MULT * (seed ^ (seed >> 30)) + i);
g_seeds[blockIdx.x][i] = seed;
}
}
return;
}
/* Init by array - single threaded as only used once, opt to reduce global refs */
__device__ static void
mt19937gai(uint* seeds, uint length)
{
mt19937gi(ARRAY_SEED);
if (threadIdx.x == 0)
{
int i = 1;
int j = 0;
int k;
uint mti; /* g_seeds[i] */
uint mtj; /* g_seeds[i - 1] */
mti = g_seeds[blockIdx.x][0];
for (k = N > length ? N : length; k != 0; k--)
{
mtj = mti;
mti = g_seeds[blockIdx.x][i];
mti = (mti ^ ((mtj ^ (mtj >> 30)) * 1664525)) + seeds[j] + j;
g_seeds[blockIdx.x][i] = mti;
if (++i >= N)
{
g_seeds[blockIdx.x][0] = mti;
i = 1;
}
if (++j >= length)
{
j = 0;
}
}
for (k = N - 1; k != 0; k--)
{
mtj = mti;
mti = g_seeds[blockIdx.x][i];
mti = (mti ^ ((mtj ^ (mtj >> 30)) * 1566083941)) - i;
g_seeds[blockIdx.x][i] = mti;
if (++i >= N)
{
g_seeds[blockIdx.x][0] = mti;
i = 1;
}
}
g_seeds[blockIdx.x][0] = mtNexti = 0x80000000; /* MSB is 1; assuring non-zero initial array */
}
return;
}
/* Return next MT random by increasing thread ID, Good for 1 - 227 threads.
* Note you should wind back MAX_THREADS to your max requirement
* to keep auto allocation of shared mem to a minimum.
* Best as a general purpose library routine. */
__device__ static uint
mt19937g(void)
{
int kk;
uint y;
const int tid = threadIdx.x;
__shared__ uint seed[MAX_THREADS + 1];
kk = mod(mtNext + tid, N);
__syncthreads(); /* Finish with mtNext & g_seeds ready from last call & init */
seed[tid + 1] = g_seeds[blockIdx.x][mod(kk + 1, N)]; /* Sequential but not aligned */
if (tid == blockDim.x - 1)
{
mtNext = kk + 1;
seed[0] = mtNexti;
mtNexti = seed[blockDim.x];
}
__syncthreads(); /* seed[] ready */
y = (seed[tid] & UPPER_MASK) | (seed[tid + 1] & LOWER_MASK);
y = g_seeds[blockIdx.x][kk < N - M ? kk + M : kk + (M - N)] ^ (y >> 1) ^ mag01[y & 1];
g_seeds[blockIdx.x][kk] = y; /* Does not overlap above reads */
y ^= (y >> 11); /* Tempering */
y ^= (y << 7) & TEMPER1;
y ^= (y << 15) & TEMPER2;
y ^= (y >> 18);
return y;
}
/* Generalised global memory version for any number of threads.
* Note only runs up to 227 at a time, rest loop and block till all done.
* Runs fractional warps at each end so not perfect utilisation.
* Uses 228 words of auto allocated shared mem. */
__device__ static uint
mt19937gl(void)
{
int jj;
int kk;
uint y;
int tid; /* Offset thread ID */
__shared__ uint seed[N - M + 1];
kk = mod(mtNext + threadIdx.x, N); /* G80 limited to 512 threads */
__syncthreads(); /* Finish with mtNext & g_seeds set from init */
if (threadIdx.x == blockDim.x - 1)
{
mtNext = kk + 1; /* Modded next call */
}
jj = 0;
do
{
__syncthreads(); /* g_seeds set from last loop */
tid = threadIdx.x - jj;
if (0 <= tid && tid < N - M)
{
seed[tid + 1] = g_seeds[blockIdx.x][mod(kk + 1, N)]; /* Sequential but not aligned */
y = min(N - M, blockDim.x - jj);
if (tid == y - 1) /* Last thread this loop */
{
seed[0] = mtNexti;
mtNexti = seed[y];
}
}
__syncthreads(); /* seed[] ready */
if (0 <= tid && tid < N - M)
{
y = (seed[tid] & UPPER_MASK) | (seed[tid + 1] & LOWER_MASK);
y = g_seeds[blockIdx.x][kk < N - M ? kk + M : kk + (M - N)] ^ (y >> 1) ^ mag01[y & 1];
g_seeds[blockIdx.x][kk] = y; /* Does not overlap reads above */
}
} while ((jj += N - M) < blockDim.x);
y ^= (y >> 11); /* Tempering */
y ^= (y << 7) & TEMPER1;
y ^= (y << 15) & TEMPER2;
y ^= (y >> 18);
return y;
}
/*************************************************************************************
* This is a shared memory implementation that keeps the full 626 words of state
* in shared memory. Faster for heavy random work where you can afford shared mem. */
__shared__ int mtNexts; /* Start of next block of seeds */
__shared__ uint s_seeds[N + 1];
/* Init by single seed - single threaded as only used once */
__device__ static void
mt19937si(uint seed)
{
int i;
if (threadIdx.x == 0)
{
mtNexts = 0;
s_seeds[0] = seed;
for (i = 1; i < N; i++)
{
seed = (INIT_MULT * (seed ^ (seed >> 30)) + i);
s_seeds[i] = seed;
}
}
__syncthreads(); /* Ensure mtNexts set & needed for mt19937w() */
return;
}
/* Init by array - single threaded as only used once */
__device__ static void
mt19937sai(uint* seeds, uint length)
{
mt19937si(ARRAY_SEED);
if (threadIdx.x == 0)
{
int i = 1;
int j = 0;
int k;
for (k = N > length ? N : length; k != 0; k--)
{
s_seeds[i] = (s_seeds[i] ^ ((s_seeds[i - 1] ^ (s_seeds[i - 1] >> 30)) * 1664525)) + seeds[j] + j;
if (++i >= N)
{
s_seeds[0] = s_seeds[N - 1];
i = 1;
}
if (++j >= length)
{
j = 0;
}
}
for (k = N - 1; k != 0; k--)
{
s_seeds[i] = (s_seeds[i] ^ ((s_seeds[i - 1] ^ (s_seeds[i - 1] >> 30)) * 1566083941)) - i;
if (++i >= N)
{
s_seeds[0] = s_seeds[N - 1];
i = 1;
}
}
s_seeds[0] = 0x80000000; /* MSB is 1; assuring non-zero initial array */
}
__syncthreads(); /* Needed for mt19937w() */
return;
}
/* Return next MT random by increasing thread ID for 1-227 threads. */
__device__ static uint
mt19937s(void)
{
int kk;
uint y;
const int tid = threadIdx.x;
kk = mod(mtNexts + tid, N);
__syncthreads(); /* Finished with mtNexts & s_seed[] ready from last run */
if (tid == blockDim.x - 1)
{
mtNexts = kk + 1; /* Will get modded on next call */
}
y = (s_seeds[kk] & UPPER_MASK) | (s_seeds[kk + 1] & LOWER_MASK);
y = s_seeds[kk < N - M ? kk + M : kk + (M - N)] ^ (y >> 1) ^ mag01[y & 1];
//y = s_seeds[kk < N - M ? kk + M : kk + (M - N)] ^ (y >> 1) ^ (y & 1 ? MATRIX_A : 0); // Same speed
__syncthreads(); /* All done before we update */
s_seeds[kk] = y;
if (kk == 0) /* Copy up for next round */
{
s_seeds[N] = y;
}
y ^= (y >> 11); /* Tempering */
y ^= (y << 7) & TEMPER1;
y ^= (y << 15) & TEMPER2;
y ^= (y >> 18);
return y;
}
/* General shared memory version for any number of threads.
* Note only up to 227 threads are run at any one time,
* the rest loop and block till all are done. */
__device__ static uint
mt19937sl(void)
{
int jj;
int kk;
uint y;
int tid; /* Offset thread ID */
kk = mod(mtNexts + threadIdx.x, N); /* G80 limited to 512 threads */
__syncthreads(); /* Finished with mtNexts & s_seed[] ready from init */
if (threadIdx.x == blockDim.x - 1)
{
mtNexts = kk + 1; /* Will get modded on next call */
}
jj = 0;
do
{
__syncthreads(); /* s_seeds[] ready from last loop */
tid = threadIdx.x - jj;
if (0 <= tid && tid < N - M)
{
y = (s_seeds[kk] & UPPER_MASK) | (s_seeds[kk + 1] & LOWER_MASK);
y = s_seeds[kk < N - M ? kk + M : kk + (M - N)] ^ (y >> 1) ^ mag01[y & 1];
}
__syncthreads(); /* All done before we update */
if (0 <= tid && tid < N - M)
{
s_seeds[kk] = y;
if (kk == 0)
{
s_seeds[N] = y;
}
}
} while ((jj += N - M) < blockDim.x);
y ^= (y >> 11); /* Tempering */
y ^= (y << 7) & TEMPER1;
y ^= (y << 15) & TEMPER2;
y ^= (y >> 18);
return y;
}
/***************************************************************************************
* This is an implementation of a full step in 1 call - all 624 results returned at once
* in pairs - 64 bit version. It may be run with 227-312 threads and will drop numbers
* from the sequence if < 312 (not incorrect).
* Original idea for this version was first presented by Brian Budge. */
#define B2 224 /* Size of second block */
__device__ static uint2
mt19937w(const int tid)
{
int kk;
uint y;
uint2 ret;
kk = tid;
/* First 227 */
if (kk < N-M) {
y = (s_seeds[kk]&UPPER_MASK)|(s_seeds[kk+1]&LOWER_MASK);
y = s_seeds[kk+M] ^ (y >> 1) ^ mag01[y & 1];
}
__syncthreads();
if (kk < N-M) {
s_seeds[kk] = y;
if (kk == 0)
{
s_seeds[N] = y;
}
}
kk += N-M;
__syncthreads();
/* Next 224 */
if (kk < N-M + B2) {
y = (s_seeds[kk]&UPPER_MASK)|(s_seeds[kk+1]&LOWER_MASK);
y = s_seeds[kk+(M-N)] ^ (y >> 1) ^ mag01[y & 1];
}
__syncthreads();
if (kk < N-M + B2) {
s_seeds[kk] = y;
}
kk += B2;
__syncthreads();
/* Last 173 */
if (kk < N) {
y = (s_seeds[kk]&UPPER_MASK)|(s_seeds[kk+1]&LOWER_MASK);
y = s_seeds[kk+(M-N)] ^ (y >> 1) ^ mag01[y & 1];
}
__syncthreads();
if (kk < N) {
s_seeds[kk] = y;
}
__syncthreads();
ret.x = s_seeds[2*tid];
ret.x ^= (ret.x >> 11); /* Tempering */
ret.x ^= (ret.x << 7) & TEMPER1;
ret.x ^= (ret.x << 15) & TEMPER2;
ret.x ^= (ret.x >> 18);
ret.y = s_seeds[2*tid+1];
ret.y ^= (ret.y >> 11);
ret.y ^= (ret.y << 7) & TEMPER1;
ret.y ^= (ret.y << 15) & TEMPER2;
ret.y ^= (ret.y >> 18);
return ret;
}
/*******************************************************************************
* For reference this is the original C single threaded source: */
#if 0
static unsigned long mt[N]; /* the array for the state vector */
static int mti=N+1; /* mti==N+1 means mt[N] is not initialized */
/* initializes mt[N] with a seed */
void init_genrand(unsigned long s)
{
mt[0]= s & 0xffffffffUL;
for (mti=1; mti<N; mti++) {
mt[mti] =
(1812433253UL * (mt[mti-1] ^ (mt[mti-1] >> 30)) + mti);
/* See Knuth TAOCP Vol2. 3rd Ed. P.106 for multiplier. */
/* In the previous versions, MSBs of the seed affect */
/* only MSBs of the array mt[]. */
/* 2002/01/09 modified by Makoto Matsumoto */
mt[mti] &= 0xffffffffUL;
/* for >32 bit machines */
}
}
/* initialize by an array with array-length */
/* init_key is the array for initializing keys */
/* key_length is its length */
/* slight change for C++, 2004/2/26 */
void init_by_array(unsigned long init_key[], int key_length)
{
int i, j, k;
init_genrand(19650218UL);
i=1; j=0;
k = (N>key_length ? N : key_length);
for (; k; k--) {
mt[i] = (mt[i] ^ ((mt[i-1] ^ (mt[i-1] >> 30)) * 1664525UL))
+ init_key[j] + j; /* non linear */
mt[i] &= 0xffffffffUL; /* for WORDSIZE > 32 machines */
i++; j++;
if (i>=N) { mt[0] = mt[N-1]; i=1; }
if (j>=key_length) j=0;
}
for (k=N-1; k; k--) {
mt[i] = (mt[i] ^ ((mt[i-1] ^ (mt[i-1] >> 30)) * 1566083941UL))
- i; /* non linear */
mt[i] &= 0xffffffffUL; /* for WORDSIZE > 32 machines */
i++;
if (i>=N) { mt[0] = mt[N-1]; i=1; }
}
mt[0] = 0x80000000UL; /* MSB is 1; assuring non-zero initial array */
}
/* generates a random number on [0,0xffffffff]-interval */
unsigned long genrand_int32(void)
{
unsigned long y;
static unsigned long mag01[2]={0x0UL, MATRIX_A};
/* mag01[x] = x * MATRIX_A for x=0,1 */
if (mti >= N) { /* generate N words at one time */
int kk;
if (mti == N+1) /* if init_genrand() has not been called, */
init_genrand(5489UL); /* a default initial seed is used */
for (kk=0;kk<N-M;kk++) {
y = (mt[kk]&UPPER_MASK)|(mt[kk+1]&LOWER_MASK);
mt[kk] = mt[kk+M] ^ (y >> 1) ^ mag01[y & 0x1UL];
}
for (;kk<N-1;kk++) {
y = (mt[kk]&UPPER_MASK)|(mt[kk+1]&LOWER_MASK);
mt[kk] = mt[kk+(M-N)] ^ (y >> 1) ^ mag01[y & 0x1UL];
}
y = (mt[N-1]&UPPER_MASK)|(mt[0]&LOWER_MASK);
mt[N-1] = mt[M-1] ^ (y >> 1) ^ mag01[y & 0x1UL];
mti = 0;
}
y = mt[mti++];
/* Tempering */
y ^= (y >> 11);
y ^= (y << 7) & 0x9d2c5680UL;
y ^= (y << 15) & 0xefc60000UL;
y ^= (y >> 18);
return y;
}
#endif | .text
.file "mt19937_ref.hip"
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB0_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB0_2:
movq __hip_gpubin_handle(%rip), %rbx
movl $g_seeds, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $638976, %r9d # imm = 0x9C000
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $mag01, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end0:
.size __hip_module_ctor, .Lfunc_end0-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB1_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB1_2:
retq
.Lfunc_end1:
.size __hip_module_dtor, .Lfunc_end1-__hip_module_dtor
.cfi_endproc
# -- End function
.type g_seeds,@object # @g_seeds
.local g_seeds
.comm g_seeds,638976,16
.type mag01,@object # @mag01
.local mag01
.comm mag01,8,4
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "g_seeds"
.size .L__unnamed_1, 8
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "mag01"
.size .L__unnamed_2, 6
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym g_seeds
.addrsig_sym mag01
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected g_seeds
.type g_seeds,@object
.section .bss,"aw",@nobits
.globl g_seeds
.p2align 4, 0x0
g_seeds:
.zero 638976
.size g_seeds, 638976
.protected mag01
.type mag01,@object
.data
.globl mag01
.p2align 2, 0x0
mag01:
.long 0
.long 2567483615
.size mag01, 8
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym g_seeds
.addrsig_sym mag01
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00058f8a_00000000-6_mt19937_ref.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2038:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2038:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "g_seeds"
.LC1:
.string "mag01"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2061:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $638976, %r9d
movl $0, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7g_seeds(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5mag01(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL5mag01
.comm _ZL5mag01,8,8
.local _ZL7g_seeds
.comm _ZL7g_seeds,638976,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mt19937_ref.hip"
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB0_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB0_2:
movq __hip_gpubin_handle(%rip), %rbx
movl $g_seeds, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $638976, %r9d # imm = 0x9C000
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $mag01, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end0:
.size __hip_module_ctor, .Lfunc_end0-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB1_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB1_2:
retq
.Lfunc_end1:
.size __hip_module_dtor, .Lfunc_end1-__hip_module_dtor
.cfi_endproc
# -- End function
.type g_seeds,@object # @g_seeds
.local g_seeds
.comm g_seeds,638976,16
.type mag01,@object # @mag01
.local mag01
.comm mag01,8,4
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "g_seeds"
.size .L__unnamed_1, 8
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "mag01"
.size .L__unnamed_2, 6
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym g_seeds
.addrsig_sym mag01
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
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