system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C"
{
__global__ void binaryentropy_32(const int lengthX, const float *x, const float *y, float *z)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<lengthX)
{
z[i] = x[i]*log(x[i]/y[i])+ (1.0-x[i])*log((1.0-x[i])/(1.0-y[i]));
}
}
} | #include <hip/hip_runtime.h>
extern "C"
{
__global__ void binaryentropy_32(const int lengthX, const float *x, const float *y, float *z)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<lengthX)
{
z[i] = x[i]*log(x[i]/y[i])+ (1.0-x[i])*log((1.0-x[i])/(1.0-y[i]));
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C"
{
__global__ void binaryentropy_32(const int lengthX, const float *x, const float *y, float *z)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<lengthX)
{
z[i] = x[i]*log(x[i]/y[i])+ (1.0-x[i])*log((1.0-x[i])/(1.0-y[i]));
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected binaryentropy_32
.globl binaryentropy_32
.p2align 8
.type binaryentropy_32,@function
binaryentropy_32:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x18
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0x3fe55555
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
s_mov_b32 s5, 0x3fc38538
global_load_b32 v24, v[2:3], off
global_load_b32 v25, v[4:5], off
s_mov_b32 s4, 0x6b47b09a
s_mov_b32 s7, 0x3fc3ab76
s_mov_b32 s6, 0xbf559e2b
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e32 v[2:3], v24
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[4:5], v25
v_div_scale_f32 v14, null, v25, v25, v24
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_rcp_f32_e32 v15, v14
v_add_f64 v[2:3], -v[2:3], 1.0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], -v[4:5], 1.0
v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], v[2:3]
v_div_scale_f64 v[12:13], s0, v[2:3], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[8:9], v[6:7]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[10:11], v[12:13], v[8:9]
v_fma_f64 v[6:7], -v[6:7], v[10:11], v[12:13]
v_fma_f32 v12, -v14, v15, 1.0
v_div_scale_f32 v13, vcc_lo, v24, v25, v24
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v15, v12, v15
v_mul_f32_e32 v12, v13, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v16, -v14, v12, v13
v_fmac_f32_e32 v12, v16, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v13, -v14, v12, v13
v_div_fmas_f32 v26, v13, v15, v12
s_mov_b32 vcc_lo, s0
s_mov_b32 s0, 0x55555555
v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[4:5], v[6:7], v[4:5], v[2:3]
v_frexp_mant_f64_e32 v[6:7], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cmp_gt_f64_e32 vcc_lo, s[0:1], v[6:7]
s_mov_b32 s0, 0x55555780
v_cndmask_b32_e64 v8, 0, 1, vcc_lo
v_ldexp_f64 v[6:7], v[6:7], v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[8:9], v[6:7], 1.0
v_add_f64 v[14:15], v[6:7], -1.0
v_rcp_f64_e32 v[10:11], v[8:9]
v_add_f64 v[16:17], v[8:9], -1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_f64 v[6:7], v[6:7], -v[16:17]
s_waitcnt_depctr 0xfff
v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
v_fma_f64 v[10:11], v[12:13], v[10:11], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
v_fma_f64 v[10:11], v[12:13], v[10:11], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[12:13], v[14:15], v[10:11]
v_mul_f64 v[18:19], v[8:9], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[12:13], v[8:9], -v[18:19]
v_fma_f64 v[6:7], v[12:13], v[6:7], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[8:9], v[18:19], v[6:7]
v_add_f64 v[16:17], v[14:15], -v[8:9]
v_add_f64 v[18:19], v[8:9], -v[18:19]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[14:15], v[14:15], -v[16:17]
v_add_f64 v[6:7], v[18:19], -v[6:7]
v_frexp_exp_i32_f64_e32 v18, v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[8:9], v[14:15], -v[8:9]
v_add_f64 v[6:7], v[6:7], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[6:7], v[16:17], v[6:7]
v_mul_f64 v[6:7], v[10:11], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[8:9], v[12:13], v[6:7]
v_mul_f64 v[10:11], v[8:9], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_fma_f64 v[14:15], v[10:11], s[6:7], s[4:5]
s_mov_b32 s5, 0x3fc7474d
s_mov_b32 s4, 0xd7f4df2e
v_mul_f64 v[16:17], v[8:9], v[10:11]
v_fma_f64 v[14:15], v[10:11], v[14:15], s[4:5]
s_mov_b32 s5, 0x3fcc71c0
s_mov_b32 s4, 0x16291751
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[14:15], v[10:11], v[14:15], s[4:5]
s_mov_b32 s5, 0x3fd24924
s_mov_b32 s4, 0x9b27acf1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[14:15], v[10:11], v[14:15], s[4:5]
s_mov_b32 s5, 0x3fd99999
s_mov_b32 s4, 0x998ef7b6
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[14:15], v[10:11], v[14:15], s[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_fma_f64 v[10:11], v[10:11], v[14:15], s[0:1]
v_ldexp_f64 v[14:15], v[8:9], 1
v_add_f64 v[8:9], v[8:9], -v[12:13]
s_mov_b32 s1, 0x3fe62e42
s_mov_b32 s0, 0xfefa39ef
v_mul_f64 v[10:11], v[16:17], v[10:11]
v_subrev_co_ci_u32_e32 v16, vcc_lo, 0, v18, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[6:7], v[6:7], -v[8:9]
v_cvt_f64_i32_e32 v[16:17], v16
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[12:13], v[14:15], v[10:11]
v_ldexp_f64 v[6:7], v[6:7], 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[18:19], v[16:17], s[0:1]
v_add_f64 v[8:9], v[12:13], -v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fma_f64 v[14:15], v[16:17], s[0:1], -v[18:19]
s_mov_b32 s1, 0x3c7abc9e
s_mov_b32 s0, 0x3b39803f
v_add_f64 v[8:9], v[10:11], -v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[10:11], v[16:17], s[0:1], v[14:15]
v_add_f64 v[6:7], v[6:7], v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[8:9], v[18:19], v[10:11]
v_add_f64 v[14:15], v[12:13], v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[18:19], v[8:9], -v[18:19]
v_add_f64 v[16:17], v[8:9], v[14:15]
v_add_f64 v[12:13], v[14:15], -v[12:13]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[10:11], v[10:11], -v[18:19]
v_add_f64 v[20:21], v[16:17], -v[8:9]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[6:7], v[6:7], -v[12:13]
v_add_f64 v[22:23], v[16:17], -v[20:21]
v_add_f64 v[12:13], v[14:15], -v[20:21]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[14:15], v[10:11], v[6:7]
v_add_f64 v[8:9], v[8:9], -v[22:23]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[8:9], v[12:13], v[8:9]
v_add_f64 v[12:13], v[14:15], -v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[8:9], v[14:15], v[8:9]
v_add_f64 v[14:15], v[14:15], -v[12:13]
v_add_f64 v[6:7], v[6:7], -v[12:13]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[18:19], v[16:17], v[8:9]
v_add_f64 v[10:11], v[10:11], -v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[12:13], v[18:19], -v[16:17]
v_add_f64 v[6:7], v[6:7], v[10:11]
v_div_fixup_f32 v10, v26, v25, v24
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cmp_gt_f32_e32 vcc_lo, 0x800000, v10
v_cndmask_b32_e64 v11, 1.0, 0x4f800000, vcc_lo
v_add_f64 v[8:9], v[8:9], -v[12:13]
v_add_f64 v[6:7], v[6:7], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[6:7], v[18:19], v[6:7]
v_mul_f32_e32 v8, v10, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_log_f32_e32 v8, v8
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v9, 0x3f317217, v8
v_fma_f32 v10, v8, 0x3f317217, -v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v10, v8, 0x3377d1cf, v10
v_add_f32_e32 v9, v9, v10
v_cndmask_b32_e64 v10, 0, 0x41b17218, vcc_lo
v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v8|
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v8, v8, v9, vcc_lo
v_cmp_class_f64_e64 vcc_lo, v[4:5], 0x204
v_dual_cndmask_b32 v7, v7, v5 :: v_dual_cndmask_b32 v6, v6, v4
v_cmp_ngt_f64_e32 vcc_lo, 0, v[4:5]
v_dual_sub_f32 v8, v8, v10 :: v_dual_cndmask_b32 v7, 0x7ff80000, v7
v_cmp_nge_f64_e32 vcc_lo, 0, v[4:5]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v6, 0, v6, vcc_lo
v_cmp_neq_f64_e32 vcc_lo, 0, v[4:5]
v_dual_mul_f32 v8, v24, v8 :: v_dual_cndmask_b32 v7, 0xfff00000, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cvt_f64_f32_e32 v[8:9], v8
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_fma_f64 v[2:3], v[2:3], v[6:7], v[8:9]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v2, v[2:3]
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel binaryentropy_32
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 27
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size binaryentropy_32, .Lfunc_end0-binaryentropy_32
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: binaryentropy_32
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: binaryentropy_32.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 27
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C"
{
__global__ void binaryentropy_32(const int lengthX, const float *x, const float *y, float *z)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<lengthX)
{
z[i] = x[i]*log(x[i]/y[i])+ (1.0-x[i])*log((1.0-x[i])/(1.0-y[i]));
}
}
} | .text
.file "binaryentropy_32.hip"
.globl __device_stub__binaryentropy_32 # -- Begin function __device_stub__binaryentropy_32
.p2align 4, 0x90
.type __device_stub__binaryentropy_32,@function
__device_stub__binaryentropy_32: # @__device_stub__binaryentropy_32
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $binaryentropy_32, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__binaryentropy_32, .Lfunc_end0-__device_stub__binaryentropy_32
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $binaryentropy_32, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type binaryentropy_32,@object # @binaryentropy_32
.section .rodata,"a",@progbits
.globl binaryentropy_32
.p2align 3, 0x0
binaryentropy_32:
.quad __device_stub__binaryentropy_32
.size binaryentropy_32, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "binaryentropy_32"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__binaryentropy_32
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym binaryentropy_32
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009c7e6_00000000-6_binaryentropy_32.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z16binaryentropy_32iPKfS0_PfiPKfS0_Pf
.type _Z43__device_stub__Z16binaryentropy_32iPKfS0_PfiPKfS0_Pf, @function
_Z43__device_stub__Z16binaryentropy_32iPKfS0_PfiPKfS0_Pf:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq binaryentropy_32(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z16binaryentropy_32iPKfS0_PfiPKfS0_Pf, .-_Z43__device_stub__Z16binaryentropy_32iPKfS0_PfiPKfS0_Pf
.globl binaryentropy_32
.type binaryentropy_32, @function
binaryentropy_32:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z16binaryentropy_32iPKfS0_PfiPKfS0_Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size binaryentropy_32, .-binaryentropy_32
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "binaryentropy_32"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq binaryentropy_32(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "binaryentropy_32.hip"
.globl __device_stub__binaryentropy_32 # -- Begin function __device_stub__binaryentropy_32
.p2align 4, 0x90
.type __device_stub__binaryentropy_32,@function
__device_stub__binaryentropy_32: # @__device_stub__binaryentropy_32
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $binaryentropy_32, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__binaryentropy_32, .Lfunc_end0-__device_stub__binaryentropy_32
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $binaryentropy_32, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type binaryentropy_32,@object # @binaryentropy_32
.section .rodata,"a",@progbits
.globl binaryentropy_32
.p2align 3, 0x0
binaryentropy_32:
.quad __device_stub__binaryentropy_32
.size binaryentropy_32, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "binaryentropy_32"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__binaryentropy_32
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym binaryentropy_32
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <cuda_runtime.h>
__global__ void matXvec(int* mat, int* vec, int* prod)
{
//mat[threadIdx.x + blockDim.x * threadIdx.y] = mat[threadIdx.x + blockDim.x * threadIdx.y] * vec[threadIdx.x];
//int ty = threadIdx.y;
//int tx = threadIdx.x;
//atomicAdd(&prod[ty], mat[ty * 32 + tx]);
atomicAdd(&prod[threadIdx.y], vec[threadIdx.x] * mat[threadIdx.y * blockDim.x + threadIdx.x]);
}
int* read_array(const char* filename, int len) {
int *x = (int*) malloc(len * sizeof(int));
FILE *fp = fopen(filename, "r");
for (int i = 0; i < len; i++) {
fscanf(fp, "%d", &x[i]);
}
fclose(fp);
return x;
}
int main(int argc, char *argv[]) {
if (argc != 1) {
printf("Invalid argument Usage: ./problem1");
return -1;
}
const int rowWidth=32;
const int colWidth=16;
int *hA = read_array("inputA.inp",rowWidth*colWidth );
int *hB = read_array("inputB.inp", rowWidth);
int *hC = (int*) malloc(colWidth * sizeof(int));
int *refC = (int*) malloc(colWidth * sizeof(int));
// TODO - allocate host memory for refC (you have to figure out how much)
// The skeleton currently segfaults because refC is accessed without allocation
// TODO do a reference host implementation (Ch) here. ie populate answer in refC
for(int i = 0; i < colWidth; i++)
{
refC[i] = 0;
for(int j = 0; j < rowWidth; j++)
{
refC[i] = refC[i] + hA[j + rowWidth * i] * hB[j];
}
//printf("refC[%d]=%d\n",i, refC[i]);
}
int *dA, *dB, *dC;
// TODO allocate device memory for dA,dB and dC
cudaMalloc((void**)&dA, sizeof(int) * rowWidth * colWidth);
cudaMalloc((void**)&dB, sizeof(int) * rowWidth);
cudaMalloc((void**)&dC, sizeof(int) * colWidth);
// TODO copy data from host to GPU
cudaMemcpy(dA, hA, sizeof(int) * rowWidth * colWidth, cudaMemcpyHostToDevice);
cudaMemcpy(dB, hB, sizeof(int) * rowWidth, cudaMemcpyHostToDevice);
// TODO call your kernel
dim3 threadsPerBlock(rowWidth, colWidth);
matXvec<<<1, threadsPerBlock>>>(dA, dB, dC);
// TODO copyback results
cudaMemcpy(hC, dC, sizeof(int) * colWidth, cudaMemcpyDeviceToHost);
cudaFree(dA);
cudaFree(dB);
cudaFree(dC);
float Error=0;
for(int i=0;i<colWidth;i++)
Error+=(hC[i]-refC[i])*(hC[i]-refC[i]);
printf("%f\n%d",sqrt(Error),hC[colWidth-1]);
free(refC);
free(hB);
free(hA);
return 0;
} | code for sm_80
Function : _Z7matXvecPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e240000002200 */
/*0050*/ IMAD R6, R2, c[0x0][0x0], R5 ; /* 0x0000000002067a24 */
/* 0x001fca00078e0205 */
/*0060*/ IMAD.WIDE.U32 R4, R5, R3, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fc800078e0003 */
/*0070*/ IMAD.WIDE.U32 R6, R6, R3.reuse, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x080fe400078e0003 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fc800078e0003 */
/*00b0*/ IMAD R9, R4, R7, RZ ; /* 0x0000000704097224 */
/* 0x004fca00078e02ff */
/*00c0*/ RED.E.ADD.STRONG.GPU [R2.64], R9 ; /* 0x000000090200798e */
/* 0x000fe2000c10e184 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <cuda_runtime.h>
__global__ void matXvec(int* mat, int* vec, int* prod)
{
//mat[threadIdx.x + blockDim.x * threadIdx.y] = mat[threadIdx.x + blockDim.x * threadIdx.y] * vec[threadIdx.x];
//int ty = threadIdx.y;
//int tx = threadIdx.x;
//atomicAdd(&prod[ty], mat[ty * 32 + tx]);
atomicAdd(&prod[threadIdx.y], vec[threadIdx.x] * mat[threadIdx.y * blockDim.x + threadIdx.x]);
}
int* read_array(const char* filename, int len) {
int *x = (int*) malloc(len * sizeof(int));
FILE *fp = fopen(filename, "r");
for (int i = 0; i < len; i++) {
fscanf(fp, "%d", &x[i]);
}
fclose(fp);
return x;
}
int main(int argc, char *argv[]) {
if (argc != 1) {
printf("Invalid argument Usage: ./problem1");
return -1;
}
const int rowWidth=32;
const int colWidth=16;
int *hA = read_array("inputA.inp",rowWidth*colWidth );
int *hB = read_array("inputB.inp", rowWidth);
int *hC = (int*) malloc(colWidth * sizeof(int));
int *refC = (int*) malloc(colWidth * sizeof(int));
// TODO - allocate host memory for refC (you have to figure out how much)
// The skeleton currently segfaults because refC is accessed without allocation
// TODO do a reference host implementation (Ch) here. ie populate answer in refC
for(int i = 0; i < colWidth; i++)
{
refC[i] = 0;
for(int j = 0; j < rowWidth; j++)
{
refC[i] = refC[i] + hA[j + rowWidth * i] * hB[j];
}
//printf("refC[%d]=%d\n",i, refC[i]);
}
int *dA, *dB, *dC;
// TODO allocate device memory for dA,dB and dC
cudaMalloc((void**)&dA, sizeof(int) * rowWidth * colWidth);
cudaMalloc((void**)&dB, sizeof(int) * rowWidth);
cudaMalloc((void**)&dC, sizeof(int) * colWidth);
// TODO copy data from host to GPU
cudaMemcpy(dA, hA, sizeof(int) * rowWidth * colWidth, cudaMemcpyHostToDevice);
cudaMemcpy(dB, hB, sizeof(int) * rowWidth, cudaMemcpyHostToDevice);
// TODO call your kernel
dim3 threadsPerBlock(rowWidth, colWidth);
matXvec<<<1, threadsPerBlock>>>(dA, dB, dC);
// TODO copyback results
cudaMemcpy(hC, dC, sizeof(int) * colWidth, cudaMemcpyDeviceToHost);
cudaFree(dA);
cudaFree(dB);
cudaFree(dC);
float Error=0;
for(int i=0;i<colWidth;i++)
Error+=(hC[i]-refC[i])*(hC[i]-refC[i]);
printf("%f\n%d",sqrt(Error),hC[colWidth-1]);
free(refC);
free(hB);
free(hA);
return 0;
} | .file "tmpxft_00108a9e_00000000-6_problem1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "%d"
.text
.globl _Z10read_arrayPKci
.type _Z10read_arrayPKci, @function
_Z10read_arrayPKci:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r12
movl %esi, %ebx
movslq %esi, %rbp
salq $2, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r14
leaq .LC0(%rip), %rsi
movq %r12, %rdi
call fopen@PLT
movq %rax, %r12
testl %ebx, %ebx
jle .L4
movq %r14, %rbx
addq %r14, %rbp
leaq .LC1(%rip), %r13
.L5:
movq %rbx, %rdx
movq %r13, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
.L4:
movq %r12, %rdi
call fclose@PLT
movq %r14, %rax
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z10read_arrayPKci, .-_Z10read_arrayPKci
.globl _Z30__device_stub__Z7matXvecPiS_S_PiS_S_
.type _Z30__device_stub__Z7matXvecPiS_S_PiS_S_, @function
_Z30__device_stub__Z7matXvecPiS_S_PiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7matXvecPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z30__device_stub__Z7matXvecPiS_S_PiS_S_, .-_Z30__device_stub__Z7matXvecPiS_S_PiS_S_
.globl _Z7matXvecPiS_S_
.type _Z7matXvecPiS_S_, @function
_Z7matXvecPiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7matXvecPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7matXvecPiS_S_, .-_Z7matXvecPiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Invalid argument Usage: ./problem1"
.section .rodata.str1.1
.LC4:
.string "inputA.inp"
.LC5:
.string "inputB.inp"
.LC6:
.string "%f\n%d"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jne .L33
movl $512, %esi
leaq .LC4(%rip), %rdi
call _Z10read_arrayPKci
movq %rax, %r13
movl $32, %esi
leaq .LC5(%rip), %rdi
call _Z10read_arrayPKci
movq %rax, %rbx
movl $64, %edi
call malloc@PLT
movq %rax, %r12
movl $64, %edi
call malloc@PLT
movq %rax, %rbp
movq %rax, %r8
movq %r13, %rsi
movl $0, %edi
.L20:
movq %r8, %r9
movl $0, %eax
movl $0, %ecx
.L19:
movl (%rsi,%rax), %edx
imull (%rbx,%rax), %edx
addl %edx, %ecx
addq $4, %rax
cmpq $128, %rax
jne .L19
movl %ecx, (%r9)
addq $4, %r8
addl $32, %edi
subq $-128, %rsi
cmpl $512, %edi
jne .L20
leaq 8(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $2048, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $128, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 32(%rsp)
movl $16, 36(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L21:
movl $2, %ecx
movl $64, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movl $0, %edx
pxor %xmm0, %xmm0
.L22:
movl (%r12,%rdx), %eax
subl 0(%rbp,%rdx), %eax
imull %eax, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
addss %xmm1, %xmm0
addq $4, %rdx
cmpq $64, %rdx
jne .L22
movl 60(%r12), %r12d
pxor %xmm1, %xmm1
ucomiss %xmm0, %xmm1
ja .L31
sqrtss %xmm0, %xmm0
.L25:
cvtss2sd %xmm0, %xmm0
movl %r12d, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movl $0, %eax
.L16:
movq 56(%rsp), %rdx
subq %fs:40, %rdx
jne .L35
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
leaq .LC3(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $-1, %eax
jmp .L16
.L34:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z30__device_stub__Z7matXvecPiS_S_PiS_S_
jmp .L21
.L31:
call sqrtf@PLT
jmp .L25
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z7matXvecPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z7matXvecPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <cuda_runtime.h>
__global__ void matXvec(int* mat, int* vec, int* prod)
{
//mat[threadIdx.x + blockDim.x * threadIdx.y] = mat[threadIdx.x + blockDim.x * threadIdx.y] * vec[threadIdx.x];
//int ty = threadIdx.y;
//int tx = threadIdx.x;
//atomicAdd(&prod[ty], mat[ty * 32 + tx]);
atomicAdd(&prod[threadIdx.y], vec[threadIdx.x] * mat[threadIdx.y * blockDim.x + threadIdx.x]);
}
int* read_array(const char* filename, int len) {
int *x = (int*) malloc(len * sizeof(int));
FILE *fp = fopen(filename, "r");
for (int i = 0; i < len; i++) {
fscanf(fp, "%d", &x[i]);
}
fclose(fp);
return x;
}
int main(int argc, char *argv[]) {
if (argc != 1) {
printf("Invalid argument Usage: ./problem1");
return -1;
}
const int rowWidth=32;
const int colWidth=16;
int *hA = read_array("inputA.inp",rowWidth*colWidth );
int *hB = read_array("inputB.inp", rowWidth);
int *hC = (int*) malloc(colWidth * sizeof(int));
int *refC = (int*) malloc(colWidth * sizeof(int));
// TODO - allocate host memory for refC (you have to figure out how much)
// The skeleton currently segfaults because refC is accessed without allocation
// TODO do a reference host implementation (Ch) here. ie populate answer in refC
for(int i = 0; i < colWidth; i++)
{
refC[i] = 0;
for(int j = 0; j < rowWidth; j++)
{
refC[i] = refC[i] + hA[j + rowWidth * i] * hB[j];
}
//printf("refC[%d]=%d\n",i, refC[i]);
}
int *dA, *dB, *dC;
// TODO allocate device memory for dA,dB and dC
cudaMalloc((void**)&dA, sizeof(int) * rowWidth * colWidth);
cudaMalloc((void**)&dB, sizeof(int) * rowWidth);
cudaMalloc((void**)&dC, sizeof(int) * colWidth);
// TODO copy data from host to GPU
cudaMemcpy(dA, hA, sizeof(int) * rowWidth * colWidth, cudaMemcpyHostToDevice);
cudaMemcpy(dB, hB, sizeof(int) * rowWidth, cudaMemcpyHostToDevice);
// TODO call your kernel
dim3 threadsPerBlock(rowWidth, colWidth);
matXvec<<<1, threadsPerBlock>>>(dA, dB, dC);
// TODO copyback results
cudaMemcpy(hC, dC, sizeof(int) * colWidth, cudaMemcpyDeviceToHost);
cudaFree(dA);
cudaFree(dB);
cudaFree(dC);
float Error=0;
for(int i=0;i<colWidth;i++)
Error+=(hC[i]-refC[i])*(hC[i]-refC[i]);
printf("%f\n%d",sqrt(Error),hC[colWidth-1]);
free(refC);
free(hB);
free(hA);
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
__global__ void matXvec(int* mat, int* vec, int* prod)
{
//mat[threadIdx.x + blockDim.x * threadIdx.y] = mat[threadIdx.x + blockDim.x * threadIdx.y] * vec[threadIdx.x];
//int ty = threadIdx.y;
//int tx = threadIdx.x;
//atomicAdd(&prod[ty], mat[ty * 32 + tx]);
atomicAdd(&prod[threadIdx.y], vec[threadIdx.x] * mat[threadIdx.y * blockDim.x + threadIdx.x]);
}
int* read_array(const char* filename, int len) {
int *x = (int*) malloc(len * sizeof(int));
FILE *fp = fopen(filename, "r");
for (int i = 0; i < len; i++) {
fscanf(fp, "%d", &x[i]);
}
fclose(fp);
return x;
}
int main(int argc, char *argv[]) {
if (argc != 1) {
printf("Invalid argument Usage: ./problem1");
return -1;
}
const int rowWidth=32;
const int colWidth=16;
int *hA = read_array("inputA.inp",rowWidth*colWidth );
int *hB = read_array("inputB.inp", rowWidth);
int *hC = (int*) malloc(colWidth * sizeof(int));
int *refC = (int*) malloc(colWidth * sizeof(int));
// TODO - allocate host memory for refC (you have to figure out how much)
// The skeleton currently segfaults because refC is accessed without allocation
// TODO do a reference host implementation (Ch) here. ie populate answer in refC
for(int i = 0; i < colWidth; i++)
{
refC[i] = 0;
for(int j = 0; j < rowWidth; j++)
{
refC[i] = refC[i] + hA[j + rowWidth * i] * hB[j];
}
//printf("refC[%d]=%d\n",i, refC[i]);
}
int *dA, *dB, *dC;
// TODO allocate device memory for dA,dB and dC
hipMalloc((void**)&dA, sizeof(int) * rowWidth * colWidth);
hipMalloc((void**)&dB, sizeof(int) * rowWidth);
hipMalloc((void**)&dC, sizeof(int) * colWidth);
// TODO copy data from host to GPU
hipMemcpy(dA, hA, sizeof(int) * rowWidth * colWidth, hipMemcpyHostToDevice);
hipMemcpy(dB, hB, sizeof(int) * rowWidth, hipMemcpyHostToDevice);
// TODO call your kernel
dim3 threadsPerBlock(rowWidth, colWidth);
matXvec<<<1, threadsPerBlock>>>(dA, dB, dC);
// TODO copyback results
hipMemcpy(hC, dC, sizeof(int) * colWidth, hipMemcpyDeviceToHost);
hipFree(dA);
hipFree(dB);
hipFree(dC);
float Error=0;
for(int i=0;i<colWidth;i++)
Error+=(hC[i]-refC[i])*(hC[i]-refC[i]);
printf("%f\n%d",sqrt(Error),hC[colWidth-1]);
free(refC);
free(hB);
free(hA);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
__global__ void matXvec(int* mat, int* vec, int* prod)
{
//mat[threadIdx.x + blockDim.x * threadIdx.y] = mat[threadIdx.x + blockDim.x * threadIdx.y] * vec[threadIdx.x];
//int ty = threadIdx.y;
//int tx = threadIdx.x;
//atomicAdd(&prod[ty], mat[ty * 32 + tx]);
atomicAdd(&prod[threadIdx.y], vec[threadIdx.x] * mat[threadIdx.y * blockDim.x + threadIdx.x]);
}
int* read_array(const char* filename, int len) {
int *x = (int*) malloc(len * sizeof(int));
FILE *fp = fopen(filename, "r");
for (int i = 0; i < len; i++) {
fscanf(fp, "%d", &x[i]);
}
fclose(fp);
return x;
}
int main(int argc, char *argv[]) {
if (argc != 1) {
printf("Invalid argument Usage: ./problem1");
return -1;
}
const int rowWidth=32;
const int colWidth=16;
int *hA = read_array("inputA.inp",rowWidth*colWidth );
int *hB = read_array("inputB.inp", rowWidth);
int *hC = (int*) malloc(colWidth * sizeof(int));
int *refC = (int*) malloc(colWidth * sizeof(int));
// TODO - allocate host memory for refC (you have to figure out how much)
// The skeleton currently segfaults because refC is accessed without allocation
// TODO do a reference host implementation (Ch) here. ie populate answer in refC
for(int i = 0; i < colWidth; i++)
{
refC[i] = 0;
for(int j = 0; j < rowWidth; j++)
{
refC[i] = refC[i] + hA[j + rowWidth * i] * hB[j];
}
//printf("refC[%d]=%d\n",i, refC[i]);
}
int *dA, *dB, *dC;
// TODO allocate device memory for dA,dB and dC
hipMalloc((void**)&dA, sizeof(int) * rowWidth * colWidth);
hipMalloc((void**)&dB, sizeof(int) * rowWidth);
hipMalloc((void**)&dC, sizeof(int) * colWidth);
// TODO copy data from host to GPU
hipMemcpy(dA, hA, sizeof(int) * rowWidth * colWidth, hipMemcpyHostToDevice);
hipMemcpy(dB, hB, sizeof(int) * rowWidth, hipMemcpyHostToDevice);
// TODO call your kernel
dim3 threadsPerBlock(rowWidth, colWidth);
matXvec<<<1, threadsPerBlock>>>(dA, dB, dC);
// TODO copyback results
hipMemcpy(hC, dC, sizeof(int) * colWidth, hipMemcpyDeviceToHost);
hipFree(dA);
hipFree(dB);
hipFree(dC);
float Error=0;
for(int i=0;i<colWidth;i++)
Error+=(hC[i]-refC[i])*(hC[i]-refC[i]);
printf("%f\n%d",sqrt(Error),hC[colWidth-1]);
free(refC);
free(hB);
free(hA);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7matXvecPiS_S_
.globl _Z7matXvecPiS_S_
.p2align 8
.type _Z7matXvecPiS_S_,@function
_Z7matXvecPiS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b32_e32 v3, 2, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
v_mul_u32_u24_e32 v2, s2, v1
v_lshlrev_b32_e32 v1, 2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_lshl_u32 v0, v2, v0, 2
global_load_b32 v2, v3, s[6:7]
global_load_b32 v0, v0, s[4:5]
s_waitcnt vmcnt(0)
v_mul_lo_u32 v0, v0, v2
global_atomic_add_u32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7matXvecPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7matXvecPiS_S_, .Lfunc_end0-_Z7matXvecPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7matXvecPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z7matXvecPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
__global__ void matXvec(int* mat, int* vec, int* prod)
{
//mat[threadIdx.x + blockDim.x * threadIdx.y] = mat[threadIdx.x + blockDim.x * threadIdx.y] * vec[threadIdx.x];
//int ty = threadIdx.y;
//int tx = threadIdx.x;
//atomicAdd(&prod[ty], mat[ty * 32 + tx]);
atomicAdd(&prod[threadIdx.y], vec[threadIdx.x] * mat[threadIdx.y * blockDim.x + threadIdx.x]);
}
int* read_array(const char* filename, int len) {
int *x = (int*) malloc(len * sizeof(int));
FILE *fp = fopen(filename, "r");
for (int i = 0; i < len; i++) {
fscanf(fp, "%d", &x[i]);
}
fclose(fp);
return x;
}
int main(int argc, char *argv[]) {
if (argc != 1) {
printf("Invalid argument Usage: ./problem1");
return -1;
}
const int rowWidth=32;
const int colWidth=16;
int *hA = read_array("inputA.inp",rowWidth*colWidth );
int *hB = read_array("inputB.inp", rowWidth);
int *hC = (int*) malloc(colWidth * sizeof(int));
int *refC = (int*) malloc(colWidth * sizeof(int));
// TODO - allocate host memory for refC (you have to figure out how much)
// The skeleton currently segfaults because refC is accessed without allocation
// TODO do a reference host implementation (Ch) here. ie populate answer in refC
for(int i = 0; i < colWidth; i++)
{
refC[i] = 0;
for(int j = 0; j < rowWidth; j++)
{
refC[i] = refC[i] + hA[j + rowWidth * i] * hB[j];
}
//printf("refC[%d]=%d\n",i, refC[i]);
}
int *dA, *dB, *dC;
// TODO allocate device memory for dA,dB and dC
hipMalloc((void**)&dA, sizeof(int) * rowWidth * colWidth);
hipMalloc((void**)&dB, sizeof(int) * rowWidth);
hipMalloc((void**)&dC, sizeof(int) * colWidth);
// TODO copy data from host to GPU
hipMemcpy(dA, hA, sizeof(int) * rowWidth * colWidth, hipMemcpyHostToDevice);
hipMemcpy(dB, hB, sizeof(int) * rowWidth, hipMemcpyHostToDevice);
// TODO call your kernel
dim3 threadsPerBlock(rowWidth, colWidth);
matXvec<<<1, threadsPerBlock>>>(dA, dB, dC);
// TODO copyback results
hipMemcpy(hC, dC, sizeof(int) * colWidth, hipMemcpyDeviceToHost);
hipFree(dA);
hipFree(dB);
hipFree(dC);
float Error=0;
for(int i=0;i<colWidth;i++)
Error+=(hC[i]-refC[i])*(hC[i]-refC[i]);
printf("%f\n%d",sqrt(Error),hC[colWidth-1]);
free(refC);
free(hB);
free(hA);
return 0;
} | .text
.file "problem1.hip"
.globl _Z22__device_stub__matXvecPiS_S_ # -- Begin function _Z22__device_stub__matXvecPiS_S_
.p2align 4, 0x90
.type _Z22__device_stub__matXvecPiS_S_,@function
_Z22__device_stub__matXvecPiS_S_: # @_Z22__device_stub__matXvecPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7matXvecPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z22__device_stub__matXvecPiS_S_, .Lfunc_end0-_Z22__device_stub__matXvecPiS_S_
.cfi_endproc
# -- End function
.globl _Z10read_arrayPKci # -- Begin function _Z10read_arrayPKci
.p2align 4, 0x90
.type _Z10read_arrayPKci,@function
_Z10read_arrayPKci: # @_Z10read_arrayPKci
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %r14
movslq %esi, %r15
leaq (,%r15,4), %rdi
callq malloc
movq %rax, %rbx
movl $.L.str, %esi
movq %r14, %rdi
callq fopen
movq %rax, %r14
testl %r15d, %r15d
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r12d
movq %rbx, %r15
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %esi
movq %r14, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
addq $4, %r15
decq %r12
jne .LBB1_2
.LBB1_3: # %._crit_edge
movq %r14, %rdi
callq fclose
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z10read_arrayPKci, .Lfunc_end1-_Z10read_arrayPKci
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
cmpl $1, %edi
jne .LBB2_1
# %bb.2:
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %rbx
movl $.L.str.3, %edi
movl $.L.str, %esi
callq fopen
movq %rax, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
leaq (%rbx,%r15), %rdx
movl $.L.str.1, %esi
movq %r14, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
addq $4, %r15
cmpq $2048, %r15 # imm = 0x800
jne .LBB2_3
# %bb.4: # %_Z10read_arrayPKci.exit
movq %r14, %rdi
callq fclose
movl $128, %edi
callq malloc
movq %rax, %r14
movl $.L.str.4, %edi
movl $.L.str, %esi
callq fopen
movq %rax, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_5: # %.lr.ph.i44
# =>This Inner Loop Header: Depth=1
leaq (%r14,%r12), %rdx
movl $.L.str.1, %esi
movq %r15, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
addq $4, %r12
cmpq $128, %r12
jne .LBB2_5
# %bb.6: # %_Z10read_arrayPKci.exit48
movq %r15, %rdi
callq fclose
movl $64, %edi
callq malloc
movq %rax, %r12
movl $64, %edi
callq malloc
movq %rax, %r15
xorl %eax, %eax
movq %rbx, %rcx
.p2align 4, 0x90
.LBB2_7: # =>This Loop Header: Depth=1
# Child Loop BB2_8 Depth 2
movl $0, (%r15,%rax,4)
xorl %esi, %esi
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_8: # Parent Loop BB2_7 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%rsi,4), %edi
imull (%rcx,%rsi,4), %edi
addl %edi, %edx
incq %rsi
cmpq $32, %rsi
jne .LBB2_8
# %bb.9: # in Loop: Header=BB2_7 Depth=1
movl %edx, (%r15,%rax,4)
incq %rax
subq $-128, %rcx
cmpq $16, %rax
jne .LBB2_7
# %bb.10:
leaq 16(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
leaq 8(%rsp), %rdi
movl $128, %esi
callq hipMalloc
movq %rsp, %rdi
movl $64, %esi
callq hipMalloc
movq 16(%rsp), %rdi
movl $2048, %edx # imm = 0x800
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $128, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $68719476768, %rdx # imm = 0x1000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_12
# %bb.11:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7matXvecPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_12:
movq (%rsp), %rsi
movl $64, %edx
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_13: # =>This Inner Loop Header: Depth=1
movl (%r12,%rax,4), %ecx
subl (%r15,%rax,4), %ecx
imull %ecx, %ecx
xorps %xmm1, %xmm1
cvtsi2ss %ecx, %xmm1
addss %xmm1, %xmm0
incq %rax
cmpq $16, %rax
jne .LBB2_13
# %bb.14:
cvtss2sd %xmm0, %xmm0
xorps %xmm1, %xmm1
ucomisd %xmm1, %xmm0
jb .LBB2_16
# %bb.15:
sqrtsd %xmm0, %xmm0
jmp .LBB2_17
.LBB2_1:
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl $-1, %eax
jmp .LBB2_18
.LBB2_16: # %call.sqrt
callq sqrt
.LBB2_17: # %.split
movl 60(%r12), %esi
movl $.L.str.5, %edi
movb $1, %al
callq printf
movq %r15, %rdi
callq free
movq %r14, %rdi
callq free
movq %rbx, %rdi
callq free
xorl %eax, %eax
.LBB2_18:
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7matXvecPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7matXvecPiS_S_,@object # @_Z7matXvecPiS_S_
.section .rodata,"a",@progbits
.globl _Z7matXvecPiS_S_
.p2align 3, 0x0
_Z7matXvecPiS_S_:
.quad _Z22__device_stub__matXvecPiS_S_
.size _Z7matXvecPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Invalid argument Usage: ./problem1"
.size .L.str.2, 35
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "inputA.inp"
.size .L.str.3, 11
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "inputB.inp"
.size .L.str.4, 11
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%f\n%d"
.size .L.str.5, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7matXvecPiS_S_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__matXvecPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7matXvecPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7matXvecPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e240000002200 */
/*0050*/ IMAD R6, R2, c[0x0][0x0], R5 ; /* 0x0000000002067a24 */
/* 0x001fca00078e0205 */
/*0060*/ IMAD.WIDE.U32 R4, R5, R3, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fc800078e0003 */
/*0070*/ IMAD.WIDE.U32 R6, R6, R3.reuse, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x080fe400078e0003 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fc800078e0003 */
/*00b0*/ IMAD R9, R4, R7, RZ ; /* 0x0000000704097224 */
/* 0x004fca00078e02ff */
/*00c0*/ RED.E.ADD.STRONG.GPU [R2.64], R9 ; /* 0x000000090200798e */
/* 0x000fe2000c10e184 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7matXvecPiS_S_
.globl _Z7matXvecPiS_S_
.p2align 8
.type _Z7matXvecPiS_S_,@function
_Z7matXvecPiS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b32_e32 v3, 2, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
v_mul_u32_u24_e32 v2, s2, v1
v_lshlrev_b32_e32 v1, 2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_lshl_u32 v0, v2, v0, 2
global_load_b32 v2, v3, s[6:7]
global_load_b32 v0, v0, s[4:5]
s_waitcnt vmcnt(0)
v_mul_lo_u32 v0, v0, v2
global_atomic_add_u32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7matXvecPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7matXvecPiS_S_, .Lfunc_end0-_Z7matXvecPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7matXvecPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z7matXvecPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00108a9e_00000000-6_problem1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "%d"
.text
.globl _Z10read_arrayPKci
.type _Z10read_arrayPKci, @function
_Z10read_arrayPKci:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r12
movl %esi, %ebx
movslq %esi, %rbp
salq $2, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r14
leaq .LC0(%rip), %rsi
movq %r12, %rdi
call fopen@PLT
movq %rax, %r12
testl %ebx, %ebx
jle .L4
movq %r14, %rbx
addq %r14, %rbp
leaq .LC1(%rip), %r13
.L5:
movq %rbx, %rdx
movq %r13, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
.L4:
movq %r12, %rdi
call fclose@PLT
movq %r14, %rax
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z10read_arrayPKci, .-_Z10read_arrayPKci
.globl _Z30__device_stub__Z7matXvecPiS_S_PiS_S_
.type _Z30__device_stub__Z7matXvecPiS_S_PiS_S_, @function
_Z30__device_stub__Z7matXvecPiS_S_PiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7matXvecPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z30__device_stub__Z7matXvecPiS_S_PiS_S_, .-_Z30__device_stub__Z7matXvecPiS_S_PiS_S_
.globl _Z7matXvecPiS_S_
.type _Z7matXvecPiS_S_, @function
_Z7matXvecPiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7matXvecPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7matXvecPiS_S_, .-_Z7matXvecPiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Invalid argument Usage: ./problem1"
.section .rodata.str1.1
.LC4:
.string "inputA.inp"
.LC5:
.string "inputB.inp"
.LC6:
.string "%f\n%d"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jne .L33
movl $512, %esi
leaq .LC4(%rip), %rdi
call _Z10read_arrayPKci
movq %rax, %r13
movl $32, %esi
leaq .LC5(%rip), %rdi
call _Z10read_arrayPKci
movq %rax, %rbx
movl $64, %edi
call malloc@PLT
movq %rax, %r12
movl $64, %edi
call malloc@PLT
movq %rax, %rbp
movq %rax, %r8
movq %r13, %rsi
movl $0, %edi
.L20:
movq %r8, %r9
movl $0, %eax
movl $0, %ecx
.L19:
movl (%rsi,%rax), %edx
imull (%rbx,%rax), %edx
addl %edx, %ecx
addq $4, %rax
cmpq $128, %rax
jne .L19
movl %ecx, (%r9)
addq $4, %r8
addl $32, %edi
subq $-128, %rsi
cmpl $512, %edi
jne .L20
leaq 8(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $2048, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $128, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 32(%rsp)
movl $16, 36(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L21:
movl $2, %ecx
movl $64, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movl $0, %edx
pxor %xmm0, %xmm0
.L22:
movl (%r12,%rdx), %eax
subl 0(%rbp,%rdx), %eax
imull %eax, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
addss %xmm1, %xmm0
addq $4, %rdx
cmpq $64, %rdx
jne .L22
movl 60(%r12), %r12d
pxor %xmm1, %xmm1
ucomiss %xmm0, %xmm1
ja .L31
sqrtss %xmm0, %xmm0
.L25:
cvtss2sd %xmm0, %xmm0
movl %r12d, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movl $0, %eax
.L16:
movq 56(%rsp), %rdx
subq %fs:40, %rdx
jne .L35
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
leaq .LC3(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $-1, %eax
jmp .L16
.L34:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z30__device_stub__Z7matXvecPiS_S_PiS_S_
jmp .L21
.L31:
call sqrtf@PLT
jmp .L25
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z7matXvecPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z7matXvecPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "problem1.hip"
.globl _Z22__device_stub__matXvecPiS_S_ # -- Begin function _Z22__device_stub__matXvecPiS_S_
.p2align 4, 0x90
.type _Z22__device_stub__matXvecPiS_S_,@function
_Z22__device_stub__matXvecPiS_S_: # @_Z22__device_stub__matXvecPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7matXvecPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z22__device_stub__matXvecPiS_S_, .Lfunc_end0-_Z22__device_stub__matXvecPiS_S_
.cfi_endproc
# -- End function
.globl _Z10read_arrayPKci # -- Begin function _Z10read_arrayPKci
.p2align 4, 0x90
.type _Z10read_arrayPKci,@function
_Z10read_arrayPKci: # @_Z10read_arrayPKci
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %r14
movslq %esi, %r15
leaq (,%r15,4), %rdi
callq malloc
movq %rax, %rbx
movl $.L.str, %esi
movq %r14, %rdi
callq fopen
movq %rax, %r14
testl %r15d, %r15d
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r12d
movq %rbx, %r15
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %esi
movq %r14, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
addq $4, %r15
decq %r12
jne .LBB1_2
.LBB1_3: # %._crit_edge
movq %r14, %rdi
callq fclose
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z10read_arrayPKci, .Lfunc_end1-_Z10read_arrayPKci
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
cmpl $1, %edi
jne .LBB2_1
# %bb.2:
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %rbx
movl $.L.str.3, %edi
movl $.L.str, %esi
callq fopen
movq %rax, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
leaq (%rbx,%r15), %rdx
movl $.L.str.1, %esi
movq %r14, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
addq $4, %r15
cmpq $2048, %r15 # imm = 0x800
jne .LBB2_3
# %bb.4: # %_Z10read_arrayPKci.exit
movq %r14, %rdi
callq fclose
movl $128, %edi
callq malloc
movq %rax, %r14
movl $.L.str.4, %edi
movl $.L.str, %esi
callq fopen
movq %rax, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_5: # %.lr.ph.i44
# =>This Inner Loop Header: Depth=1
leaq (%r14,%r12), %rdx
movl $.L.str.1, %esi
movq %r15, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
addq $4, %r12
cmpq $128, %r12
jne .LBB2_5
# %bb.6: # %_Z10read_arrayPKci.exit48
movq %r15, %rdi
callq fclose
movl $64, %edi
callq malloc
movq %rax, %r12
movl $64, %edi
callq malloc
movq %rax, %r15
xorl %eax, %eax
movq %rbx, %rcx
.p2align 4, 0x90
.LBB2_7: # =>This Loop Header: Depth=1
# Child Loop BB2_8 Depth 2
movl $0, (%r15,%rax,4)
xorl %esi, %esi
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_8: # Parent Loop BB2_7 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%rsi,4), %edi
imull (%rcx,%rsi,4), %edi
addl %edi, %edx
incq %rsi
cmpq $32, %rsi
jne .LBB2_8
# %bb.9: # in Loop: Header=BB2_7 Depth=1
movl %edx, (%r15,%rax,4)
incq %rax
subq $-128, %rcx
cmpq $16, %rax
jne .LBB2_7
# %bb.10:
leaq 16(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
leaq 8(%rsp), %rdi
movl $128, %esi
callq hipMalloc
movq %rsp, %rdi
movl $64, %esi
callq hipMalloc
movq 16(%rsp), %rdi
movl $2048, %edx # imm = 0x800
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $128, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $68719476768, %rdx # imm = 0x1000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_12
# %bb.11:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7matXvecPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_12:
movq (%rsp), %rsi
movl $64, %edx
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_13: # =>This Inner Loop Header: Depth=1
movl (%r12,%rax,4), %ecx
subl (%r15,%rax,4), %ecx
imull %ecx, %ecx
xorps %xmm1, %xmm1
cvtsi2ss %ecx, %xmm1
addss %xmm1, %xmm0
incq %rax
cmpq $16, %rax
jne .LBB2_13
# %bb.14:
cvtss2sd %xmm0, %xmm0
xorps %xmm1, %xmm1
ucomisd %xmm1, %xmm0
jb .LBB2_16
# %bb.15:
sqrtsd %xmm0, %xmm0
jmp .LBB2_17
.LBB2_1:
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl $-1, %eax
jmp .LBB2_18
.LBB2_16: # %call.sqrt
callq sqrt
.LBB2_17: # %.split
movl 60(%r12), %esi
movl $.L.str.5, %edi
movb $1, %al
callq printf
movq %r15, %rdi
callq free
movq %r14, %rdi
callq free
movq %rbx, %rdi
callq free
xorl %eax, %eax
.LBB2_18:
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7matXvecPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7matXvecPiS_S_,@object # @_Z7matXvecPiS_S_
.section .rodata,"a",@progbits
.globl _Z7matXvecPiS_S_
.p2align 3, 0x0
_Z7matXvecPiS_S_:
.quad _Z22__device_stub__matXvecPiS_S_
.size _Z7matXvecPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Invalid argument Usage: ./problem1"
.size .L.str.2, 35
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "inputA.inp"
.size .L.str.3, 11
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "inputB.inp"
.size .L.str.4, 11
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%f\n%d"
.size .L.str.5, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7matXvecPiS_S_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__matXvecPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7matXvecPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
/*
* Currently, `initializeElementsTo`, if executed in a thread whose
* `i` is calculated to be greater than `N`, will try to access a value
* outside the range of `a`.
*
* Refactor the kernel defintition to prevent our of range accesses.
*/
__global__ void initializeElementsTo(int initialValue, int *a, int N)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i < N) {
a[i] = initialValue;
}
}
int main()
{
/*
* Do not modify `N`.
*/
int N = 1000;
int *a;
size_t size = N * sizeof(int);
cudaMallocManaged(&a, size);
/*
* Assume we have reason to want the number of threads
* fixed at `256`: do not modify `threads_per_block`.
*/
size_t threads_per_block = 256;
/*
* Assign a value to `number_of_blocks` that will
* allow for a working execution configuration given
* the fixed values for `N` and `threads_per_block`.
*/
size_t number_of_blocks = (N + threads_per_block - 1) / threads_per_block;
int initialValue = 6;
initializeElementsTo<<<number_of_blocks, threads_per_block>>>(initialValue, a, N);
cudaDeviceSynchronize();
/*
* Check to make sure all values in `a`, were initialized.
*/
for (int i = 0; i < N; ++i)
{
if(a[i] != initialValue)
{
printf("FAILURE: target value: %d\t a[%d]: %d\n", initialValue, i, a[i]);
exit(1);
}
}
printf("SUCCESS!\n");
cudaFree(a);
} | code for sm_80
Function : _Z20initializeElementsToiPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ MOV R5, c[0x0][0x160] ; /* 0x0000580000057a02 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0090*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*00a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
/*
* Currently, `initializeElementsTo`, if executed in a thread whose
* `i` is calculated to be greater than `N`, will try to access a value
* outside the range of `a`.
*
* Refactor the kernel defintition to prevent our of range accesses.
*/
__global__ void initializeElementsTo(int initialValue, int *a, int N)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i < N) {
a[i] = initialValue;
}
}
int main()
{
/*
* Do not modify `N`.
*/
int N = 1000;
int *a;
size_t size = N * sizeof(int);
cudaMallocManaged(&a, size);
/*
* Assume we have reason to want the number of threads
* fixed at `256`: do not modify `threads_per_block`.
*/
size_t threads_per_block = 256;
/*
* Assign a value to `number_of_blocks` that will
* allow for a working execution configuration given
* the fixed values for `N` and `threads_per_block`.
*/
size_t number_of_blocks = (N + threads_per_block - 1) / threads_per_block;
int initialValue = 6;
initializeElementsTo<<<number_of_blocks, threads_per_block>>>(initialValue, a, N);
cudaDeviceSynchronize();
/*
* Check to make sure all values in `a`, were initialized.
*/
for (int i = 0; i < N; ++i)
{
if(a[i] != initialValue)
{
printf("FAILURE: target value: %d\t a[%d]: %d\n", initialValue, i, a[i]);
exit(1);
}
}
printf("SUCCESS!\n");
cudaFree(a);
} | .file "tmpxft_000ecef6_00000000-6_loop_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z20initializeElementsToiPiiiPii
.type _Z42__device_stub__Z20initializeElementsToiPiiiPii, @function
_Z42__device_stub__Z20initializeElementsToiPiiiPii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z20initializeElementsToiPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z42__device_stub__Z20initializeElementsToiPiiiPii, .-_Z42__device_stub__Z20initializeElementsToiPiiiPii
.globl _Z20initializeElementsToiPii
.type _Z20initializeElementsToiPii, @function
_Z20initializeElementsToiPii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z20initializeElementsToiPiiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z20initializeElementsToiPii, .-_Z20initializeElementsToiPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "FAILURE: target value: %d\t a[%d]: %d\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "SUCCESS!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $4000, %esi
call cudaMallocManaged@PLT
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $4, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L12:
call cudaDeviceSynchronize@PLT
movq 8(%rsp), %rdx
movl $0, %eax
.L14:
movl (%rdx,%rax,4), %r8d
cmpl $6, %r8d
jne .L19
addq $1, %rax
cmpq $1000, %rax
jne .L14
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movl $1000, %edx
movq 8(%rsp), %rsi
movl $6, %edi
call _Z42__device_stub__Z20initializeElementsToiPiiiPii
jmp .L12
.L19:
movl %eax, %ecx
movl $6, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z20initializeElementsToiPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z20initializeElementsToiPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
/*
* Currently, `initializeElementsTo`, if executed in a thread whose
* `i` is calculated to be greater than `N`, will try to access a value
* outside the range of `a`.
*
* Refactor the kernel defintition to prevent our of range accesses.
*/
__global__ void initializeElementsTo(int initialValue, int *a, int N)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i < N) {
a[i] = initialValue;
}
}
int main()
{
/*
* Do not modify `N`.
*/
int N = 1000;
int *a;
size_t size = N * sizeof(int);
cudaMallocManaged(&a, size);
/*
* Assume we have reason to want the number of threads
* fixed at `256`: do not modify `threads_per_block`.
*/
size_t threads_per_block = 256;
/*
* Assign a value to `number_of_blocks` that will
* allow for a working execution configuration given
* the fixed values for `N` and `threads_per_block`.
*/
size_t number_of_blocks = (N + threads_per_block - 1) / threads_per_block;
int initialValue = 6;
initializeElementsTo<<<number_of_blocks, threads_per_block>>>(initialValue, a, N);
cudaDeviceSynchronize();
/*
* Check to make sure all values in `a`, were initialized.
*/
for (int i = 0; i < N; ++i)
{
if(a[i] != initialValue)
{
printf("FAILURE: target value: %d\t a[%d]: %d\n", initialValue, i, a[i]);
exit(1);
}
}
printf("SUCCESS!\n");
cudaFree(a);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
/*
* Currently, `initializeElementsTo`, if executed in a thread whose
* `i` is calculated to be greater than `N`, will try to access a value
* outside the range of `a`.
*
* Refactor the kernel defintition to prevent our of range accesses.
*/
__global__ void initializeElementsTo(int initialValue, int *a, int N)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i < N) {
a[i] = initialValue;
}
}
int main()
{
/*
* Do not modify `N`.
*/
int N = 1000;
int *a;
size_t size = N * sizeof(int);
hipMallocManaged(&a, size);
/*
* Assume we have reason to want the number of threads
* fixed at `256`: do not modify `threads_per_block`.
*/
size_t threads_per_block = 256;
/*
* Assign a value to `number_of_blocks` that will
* allow for a working execution configuration given
* the fixed values for `N` and `threads_per_block`.
*/
size_t number_of_blocks = (N + threads_per_block - 1) / threads_per_block;
int initialValue = 6;
initializeElementsTo<<<number_of_blocks, threads_per_block>>>(initialValue, a, N);
hipDeviceSynchronize();
/*
* Check to make sure all values in `a`, were initialized.
*/
for (int i = 0; i < N; ++i)
{
if(a[i] != initialValue)
{
printf("FAILURE: target value: %d\t a[%d]: %d\n", initialValue, i, a[i]);
exit(1);
}
}
printf("SUCCESS!\n");
hipFree(a);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
/*
* Currently, `initializeElementsTo`, if executed in a thread whose
* `i` is calculated to be greater than `N`, will try to access a value
* outside the range of `a`.
*
* Refactor the kernel defintition to prevent our of range accesses.
*/
__global__ void initializeElementsTo(int initialValue, int *a, int N)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i < N) {
a[i] = initialValue;
}
}
int main()
{
/*
* Do not modify `N`.
*/
int N = 1000;
int *a;
size_t size = N * sizeof(int);
hipMallocManaged(&a, size);
/*
* Assume we have reason to want the number of threads
* fixed at `256`: do not modify `threads_per_block`.
*/
size_t threads_per_block = 256;
/*
* Assign a value to `number_of_blocks` that will
* allow for a working execution configuration given
* the fixed values for `N` and `threads_per_block`.
*/
size_t number_of_blocks = (N + threads_per_block - 1) / threads_per_block;
int initialValue = 6;
initializeElementsTo<<<number_of_blocks, threads_per_block>>>(initialValue, a, N);
hipDeviceSynchronize();
/*
* Check to make sure all values in `a`, were initialized.
*/
for (int i = 0; i < N; ++i)
{
if(a[i] != initialValue)
{
printf("FAILURE: target value: %d\t a[%d]: %d\n", initialValue, i, a[i]);
exit(1);
}
}
printf("SUCCESS!\n");
hipFree(a);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20initializeElementsToiPii
.globl _Z20initializeElementsToiPii
.p2align 8
.type _Z20initializeElementsToiPii,@function
_Z20initializeElementsToiPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b32 s0, s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_mov_b32_e32 v2, s0
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20initializeElementsToiPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20initializeElementsToiPii, .Lfunc_end0-_Z20initializeElementsToiPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20initializeElementsToiPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20initializeElementsToiPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
/*
* Currently, `initializeElementsTo`, if executed in a thread whose
* `i` is calculated to be greater than `N`, will try to access a value
* outside the range of `a`.
*
* Refactor the kernel defintition to prevent our of range accesses.
*/
__global__ void initializeElementsTo(int initialValue, int *a, int N)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i < N) {
a[i] = initialValue;
}
}
int main()
{
/*
* Do not modify `N`.
*/
int N = 1000;
int *a;
size_t size = N * sizeof(int);
hipMallocManaged(&a, size);
/*
* Assume we have reason to want the number of threads
* fixed at `256`: do not modify `threads_per_block`.
*/
size_t threads_per_block = 256;
/*
* Assign a value to `number_of_blocks` that will
* allow for a working execution configuration given
* the fixed values for `N` and `threads_per_block`.
*/
size_t number_of_blocks = (N + threads_per_block - 1) / threads_per_block;
int initialValue = 6;
initializeElementsTo<<<number_of_blocks, threads_per_block>>>(initialValue, a, N);
hipDeviceSynchronize();
/*
* Check to make sure all values in `a`, were initialized.
*/
for (int i = 0; i < N; ++i)
{
if(a[i] != initialValue)
{
printf("FAILURE: target value: %d\t a[%d]: %d\n", initialValue, i, a[i]);
exit(1);
}
}
printf("SUCCESS!\n");
hipFree(a);
} | .text
.file "loop_kernel.hip"
.globl _Z35__device_stub__initializeElementsToiPii # -- Begin function _Z35__device_stub__initializeElementsToiPii
.p2align 4, 0x90
.type _Z35__device_stub__initializeElementsToiPii,@function
_Z35__device_stub__initializeElementsToiPii: # @_Z35__device_stub__initializeElementsToiPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
movl %edx, (%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z20initializeElementsToiPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z35__device_stub__initializeElementsToiPii, .Lfunc_end0-_Z35__device_stub__initializeElementsToiPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
leaq 8(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
movl $1, %edx
callq hipMallocManaged
movabsq $4294967300, %rdi # imm = 0x100000004
leaq 252(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movl $6, 20(%rsp)
movq %rax, 72(%rsp)
movl $1000, 16(%rsp) # imm = 0x3E8
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20initializeElementsToiPii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %edx, %edx
movq 8(%rsp), %rax
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movl (%rax,%rdx,4), %ecx
cmpl $6, %ecx
jne .LBB1_6
# %bb.4: # in Loop: Header=BB1_3 Depth=1
incq %rdx
cmpq $1000, %rdx # imm = 0x3E8
jne .LBB1_3
# %bb.5:
movl $.Lstr, %edi
callq puts@PLT
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.LBB1_6:
.cfi_def_cfa_offset 112
movl $.L.str, %edi
movl $6, %esi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20initializeElementsToiPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20initializeElementsToiPii,@object # @_Z20initializeElementsToiPii
.section .rodata,"a",@progbits
.globl _Z20initializeElementsToiPii
.p2align 3, 0x0
_Z20initializeElementsToiPii:
.quad _Z35__device_stub__initializeElementsToiPii
.size _Z20initializeElementsToiPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "FAILURE: target value: %d\t a[%d]: %d\n"
.size .L.str, 38
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z20initializeElementsToiPii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "SUCCESS!"
.size .Lstr, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__initializeElementsToiPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20initializeElementsToiPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z20initializeElementsToiPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ MOV R5, c[0x0][0x160] ; /* 0x0000580000057a02 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0090*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*00a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20initializeElementsToiPii
.globl _Z20initializeElementsToiPii
.p2align 8
.type _Z20initializeElementsToiPii,@function
_Z20initializeElementsToiPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b32 s0, s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_mov_b32_e32 v2, s0
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20initializeElementsToiPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20initializeElementsToiPii, .Lfunc_end0-_Z20initializeElementsToiPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20initializeElementsToiPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20initializeElementsToiPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ecef6_00000000-6_loop_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z20initializeElementsToiPiiiPii
.type _Z42__device_stub__Z20initializeElementsToiPiiiPii, @function
_Z42__device_stub__Z20initializeElementsToiPiiiPii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z20initializeElementsToiPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z42__device_stub__Z20initializeElementsToiPiiiPii, .-_Z42__device_stub__Z20initializeElementsToiPiiiPii
.globl _Z20initializeElementsToiPii
.type _Z20initializeElementsToiPii, @function
_Z20initializeElementsToiPii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z20initializeElementsToiPiiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z20initializeElementsToiPii, .-_Z20initializeElementsToiPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "FAILURE: target value: %d\t a[%d]: %d\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "SUCCESS!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $4000, %esi
call cudaMallocManaged@PLT
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $4, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L12:
call cudaDeviceSynchronize@PLT
movq 8(%rsp), %rdx
movl $0, %eax
.L14:
movl (%rdx,%rax,4), %r8d
cmpl $6, %r8d
jne .L19
addq $1, %rax
cmpq $1000, %rax
jne .L14
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movl $1000, %edx
movq 8(%rsp), %rsi
movl $6, %edi
call _Z42__device_stub__Z20initializeElementsToiPiiiPii
jmp .L12
.L19:
movl %eax, %ecx
movl $6, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z20initializeElementsToiPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z20initializeElementsToiPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "loop_kernel.hip"
.globl _Z35__device_stub__initializeElementsToiPii # -- Begin function _Z35__device_stub__initializeElementsToiPii
.p2align 4, 0x90
.type _Z35__device_stub__initializeElementsToiPii,@function
_Z35__device_stub__initializeElementsToiPii: # @_Z35__device_stub__initializeElementsToiPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
movl %edx, (%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z20initializeElementsToiPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z35__device_stub__initializeElementsToiPii, .Lfunc_end0-_Z35__device_stub__initializeElementsToiPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
leaq 8(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
movl $1, %edx
callq hipMallocManaged
movabsq $4294967300, %rdi # imm = 0x100000004
leaq 252(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movl $6, 20(%rsp)
movq %rax, 72(%rsp)
movl $1000, 16(%rsp) # imm = 0x3E8
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20initializeElementsToiPii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %edx, %edx
movq 8(%rsp), %rax
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movl (%rax,%rdx,4), %ecx
cmpl $6, %ecx
jne .LBB1_6
# %bb.4: # in Loop: Header=BB1_3 Depth=1
incq %rdx
cmpq $1000, %rdx # imm = 0x3E8
jne .LBB1_3
# %bb.5:
movl $.Lstr, %edi
callq puts@PLT
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.LBB1_6:
.cfi_def_cfa_offset 112
movl $.L.str, %edi
movl $6, %esi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20initializeElementsToiPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20initializeElementsToiPii,@object # @_Z20initializeElementsToiPii
.section .rodata,"a",@progbits
.globl _Z20initializeElementsToiPii
.p2align 3, 0x0
_Z20initializeElementsToiPii:
.quad _Z35__device_stub__initializeElementsToiPii
.size _Z20initializeElementsToiPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "FAILURE: target value: %d\t a[%d]: %d\n"
.size .L.str, 38
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z20initializeElementsToiPii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "SUCCESS!"
.size .Lstr, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__initializeElementsToiPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20initializeElementsToiPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void gpu_stencil37_hack1_cp_cols(double * dst, double * shared_rows, double *shared_cols,double *shared_slices,int n_rows, int n_cols,int n_slices,int tile_x,int tile_y, int tile_z){
#ifdef CUDA_DARTS_DEBUG
if((blockIdx.x==0)&&(blockIdx.y==0)&&(blockIdx.z==0)&&(threadIdx.y==0)&& threadIdx.x==0 && threadIdx.z==0){
printf("copy cols begin\n");
printf("gridDim.x=%d,gridDim.y=%d,gridDim.z=%d\n",gridDim.x,gridDim.y,gridDim.z);
printf("blockDim.x=%d,blockDim.y=%d,blockDim.z=%d\n",blockDim.x,blockDim.y,blockDim.z);
printf("tile_x=%d,tile_y=%d,tile_z=%d\n",tile_x,tile_y,tile_z);
}
#endif
int base_global_slice = tile_z * blockIdx.z;
int base_global_row = blockDim.y * blockIdx.y;
int base_global_col = tile_x * blockIdx.x;
int area_dst = n_rows*n_cols;
int area_shared = gridDim.x*n_rows*2;
#ifdef CUDA_CUDA_DEBUG
if((blockIdx.x==0)&&(blockIdx.y==0)&&(blockIdx.z==0)&&(threadIdx.y==0&&threadIdx.x==0&&threadIdx.z==0)){
printf("area_shared=%d\n",area_shared);
}
#endif
int base_global_idx = base_global_slice*area_dst + base_global_row * n_cols + base_global_col;
int nextCol= base_global_col+1;
bool legalNextCol = (nextCol<n_cols)?1:0;
int ty = threadIdx.y;
bool legalCurRow = (base_global_row + ty)<n_rows;
for(int tz=0;tz<tile_z;++tz){
bool legalCurSlice = (base_global_slice + tz)<n_slices;
int idx_dst =base_global_idx + tz*area_dst + ty*n_cols ;
int idx = (base_global_slice+tz)*area_shared + blockIdx.x*2*n_rows+blockIdx.y*blockDim.y+ty;
if(legalCurRow && legalCurSlice){
shared_cols[idx] = dst[idx_dst];
}
if(legalCurRow && legalCurSlice && legalNextCol){
shared_cols[idx + n_rows] = dst[idx_dst + 1];
}
__syncthreads();
}
__syncthreads();
#ifdef CUDA_CUDA_DEBUG
if(blockIdx.z ==0 && blockIdx.y==0 && blockIdx.x==0 && (threadIdx.x==0)){
// printf("shared_cols: addr:%d, val = %f\n", threadIdx.y,shared_cols[threadIdx.y]);
}
#endif
#ifdef CUDA_DARTS_DEBUG
if((blockIdx.x==0)&&(blockIdx.y==0)&&(blockIdx.z==0)&&(threadIdx.y==0 && threadIdx.x==0 && threadIdx.z==0)){
printf("copy cols end!\n");
}
#endif
} | code for sm_80
Function : _Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x194] ; /* 0x00006500ff027624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 BRA 0xc10 ; /* 0x00000bd000008947 */
/* 0x000fea0003800000 */
/*0040*/ S2UR UR13, SR_CTAID.X ; /* 0x00000000000d79c3 */
/* 0x000e220000002500 */
/*0050*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e620000002600 */
/*0060*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe20007ffe0ff */
/*0070*/ ULDC UR6, c[0x0][0x18c] ; /* 0x0000630000067ab9 */
/* 0x000fe20000000800 */
/*0080*/ LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fe200078ec0ff */
/*0090*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*00a0*/ ISETP.GE.U32.AND P1, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f26070 */
/*00b0*/ ULDC UR5, c[0x0][0x194] ; /* 0x0000650000057ab9 */
/* 0x000fe20000000800 */
/*00c0*/ S2UR UR12, SR_CTAID.Z ; /* 0x00000000000c79c3 */
/* 0x000ea20000002700 */
/*00d0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00e0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*00f0*/ ULDC.64 UR14, c[0x0][0x118] ; /* 0x00004600000e7ab9 */
/* 0x000fc40000000a00 */
/*0100*/ UIMAD UR6, UR13, UR6, URZ ; /* 0x000000060d0672a4 */
/* 0x001fc8000f8e023f */
/*0110*/ UIADD3 UR18, UR6, 0x1, URZ ; /* 0x0000000106127890 */
/* 0x000fe2000fffe03f */
/*0120*/ IMAD R4, R0, c[0x0][0x4], R3 ; /* 0x0000010000047a24 */
/* 0x002fe200078e0203 */
/*0130*/ UIMAD UR5, UR12, UR5, URZ ; /* 0x000000050c0572a4 */
/* 0x004fe2000f8e023f */
/*0140*/ @!P1 BRA 0x960 ; /* 0x0000081000009947 */
/* 0x000fec0003800000 */
/*0150*/ UIADD3 UR19, UR5, 0x3, URZ ; /* 0x0000000305137890 */
/* 0x000fe2000fffe03f */
/*0160*/ IMAD.MOV.U32 R26, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff1a7624 */
/* 0x000fe200078e00ff */
/*0170*/ UIADD3 UR20, UR5, 0x2, URZ ; /* 0x0000000205147890 */
/* 0x000fe2000fffe03f */
/*0180*/ IMAD.U32 R10, RZ, RZ, UR5 ; /* 0x00000005ff0a7e24 */
/* 0x000fe2000f8e00ff */
/*0190*/ ULDC UR8, c[0x0][0xc] ; /* 0x0000030000087ab9 */
/* 0x000fe20000000800 */
/*01a0*/ MOV R9, c[0x0][0x180] ; /* 0x0000600000097a02 */
/* 0x000fe20000000f00 */
/*01b0*/ UIADD3 UR21, UR5, 0x1, URZ ; /* 0x0000000105157890 */
/* 0x000fe2000fffe03f */
/*01c0*/ MOV R5, UR19 ; /* 0x0000001300057c02 */
/* 0x000fe20008000f00 */
/*01d0*/ USHF.L.U32 UR7, UR13, 0x1, URZ ; /* 0x000000010d077899 */
/* 0x000fe2000800063f */
/*01e0*/ MOV R7, UR20 ; /* 0x0000001400077c02 */
/* 0x000fe20008000f00 */
/*01f0*/ UIMAD UR4, UR19, UR8, URZ ; /* 0x00000008130472a4 */
/* 0x000fe2000f8e023f */
/*0200*/ IMAD R11, R10, c[0x0][0x180], R3.reuse ; /* 0x000060000a0b7a24 */
/* 0x100fe200078e0203 */
/*0210*/ UIMAD UR9, UR20, UR8, URZ ; /* 0x00000008140972a4 */
/* 0x000fe2000f8e023f */
/*0220*/ IMAD R5, R5, c[0x0][0x180], R4.reuse ; /* 0x0000600005057a24 */
/* 0x100fe200078e0204 */
/*0230*/ ULDC UR16, c[0x0][0x180] ; /* 0x0000600000107ab9 */
/* 0x000fe20000000800 */
/*0240*/ IMAD R22, R7, c[0x0][0x180], R4.reuse ; /* 0x0000600007167a24 */
/* 0x100fe200078e0204 */
/*0250*/ UIMAD UR11, UR21, UR8, URZ ; /* 0x00000008150b72a4 */
/* 0x000fe2000f8e023f */
/*0260*/ IMAD R26, R5, R26, UR6 ; /* 0x00000006051a7e24 */
/* 0x000fe2000f8e021a */
/*0270*/ UIMAD UR12, UR12, UR8, URZ ; /* 0x000000080c0c72a4 */
/* 0x000fe2000f8e023f */
/*0280*/ IMAD.U32 R23, RZ, RZ, UR21 ; /* 0x00000015ff177e24 */
/* 0x000fe2000f8e00ff */
/*0290*/ ULEA UR8, UR4, UR7, 0x1 ; /* 0x0000000704087291 */
/* 0x000fe2000f8e083f */
/*02a0*/ IMAD R8, R9.reuse, c[0x0][0xc], RZ ; /* 0x0000030009087a24 */
/* 0x040fe200078e02ff */
/*02b0*/ ULEA UR10, UR9, UR7, 0x1 ; /* 0x00000007090a7291 */
/* 0x000fe2000f8e083f */
/*02c0*/ ISETP.GE.AND P1, PT, R4, c[0x0][0x180], PT ; /* 0x0000600004007a0c */
/* 0x000fe20003f26270 */
/*02d0*/ USHF.L.U32 UR22, UR16, 0x1, URZ ; /* 0x0000000110167899 */
/* 0x000fe2000800063f */
/*02e0*/ IADD3 R5, R2, -c[0x0][0x194], RZ ; /* 0x8000650002057a10 */
/* 0x000fe20007ffe0ff */
/*02f0*/ UIADD3 UR8, UR8, 0x1, URZ ; /* 0x0000000108087890 */
/* 0x000fe2000fffe03f */
/*0300*/ MOV R6, R4 ; /* 0x0000000400067202 */
/* 0x000fe20000000f00 */
/*0310*/ UIADD3 UR10, UR10, 0x1, URZ ; /* 0x000000010a0a7890 */
/* 0x000fe2000fffe03f */
/*0320*/ IMAD.U32 R24, RZ, RZ, UR6 ; /* 0x00000006ff187e24 */
/* 0x000fe2000f8e00ff */
/*0330*/ UIADD3 UR4, UR4, UR13, URZ ; /* 0x0000000d04047290 */
/* 0x000fe2000fffe03f */
/*0340*/ IMAD.U32 R12, RZ, RZ, UR22 ; /* 0x00000016ff0c7e24 */
/* 0x000fe2000f8e00ff */
/*0350*/ UIADD3 UR9, UR9, UR13, URZ ; /* 0x0000000d09097290 */
/* 0x000fe2000fffe03f */
/*0360*/ MOV R25, UR8 ; /* 0x0000000800197c02 */
/* 0x000fe20008000f00 */
/*0370*/ ULDC UR17, c[0x0][0x194] ; /* 0x0000650000117ab9 */
/* 0x000fe20000000800 */
/*0380*/ MOV R27, UR10 ; /* 0x0000000a001b7c02 */
/* 0x000fe20008000f00 */
/*0390*/ IMAD R7, R12.reuse, UR4, R3.reuse ; /* 0x000000040c077c24 */
/* 0x140fe2000f8e0203 */
/*03a0*/ ULEA UR7, UR11, UR7, 0x1 ; /* 0x000000070b077291 */
/* 0x000fe2000f8e083f */
/*03b0*/ IMAD R29, R12, UR9, R3 ; /* 0x000000090c1d7c24 */
/* 0x000fe2000f8e0203 */
/*03c0*/ UIMAD UR12, UR12, UR17, UR13 ; /* 0x000000110c0c72a4 */
/* 0x000fe2000f8e020d */
/*03d0*/ IMAD R9, R9, c[0x0][0x184], RZ ; /* 0x0000610009097a24 */
/* 0x000fe200078e02ff */
/*03e0*/ UIADD3 UR11, UR11, UR13, URZ ; /* 0x0000000d0b0b7290 */
/* 0x000fe2000fffe03f */
/*03f0*/ MOV R10, UR19 ; /* 0x00000013000a7c02 */
/* 0x000fe20008000f00 */
/*0400*/ IMAD R11, R0, c[0x0][0x4], R11 ; /* 0x00000100000b7a24 */
/* 0x000fe200078e020b */
/*0410*/ IADD3 R26, R26, 0x1, RZ ; /* 0x000000011a1a7810 */
/* 0x000fe20007ffe0ff */
/*0420*/ IMAD R23, R23, c[0x0][0x180], R4.reuse ; /* 0x0000600017177a24 */
/* 0x100fe200078e0204 */
/*0430*/ ULEA UR17, UR12, 0x1, 0x1 ; /* 0x000000010c117891 */
/* 0x000fe2000f8e083f */
/*0440*/ IMAD R7, R0.reuse, c[0x0][0x4], R7 ; /* 0x0000010000077a24 */
/* 0x040fe200078e0207 */
/*0450*/ UIADD3 UR7, UR7, 0x1, URZ ; /* 0x0000000107077890 */
/* 0x000fe2000fffe03f */
/*0460*/ IMAD R29, R0, c[0x0][0x4], R29 ; /* 0x00000100001d7a24 */
/* 0x000fe200078e021d */
/*0470*/ UIMAD UR11, UR11, UR16, URZ ; /* 0x000000100b0b72a4 */
/* 0x000fe2000f8e023f */
/*0480*/ IMAD R25, R25, c[0x0][0x180], R4.reuse ; /* 0x0000600019197a24 */
/* 0x100fe200078e0204 */
/*0490*/ UIMAD UR12, UR12, UR16, URZ ; /* 0x000000100c0c72a4 */
/* 0x000fe2000f8e023f */
/*04a0*/ IMAD R27, R27, c[0x0][0x180], R4 ; /* 0x000060001b1b7a24 */
/* 0x000fe200078e0204 */
/*04b0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fc40008000000 */
/*04c0*/ UIADD3 UR8, UR5, UR4, URZ ; /* 0x0000000405087290 */
/* 0x000fe2000fffe03f */
/*04d0*/ HFMA2.MMA R28, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff1c7435 */
/* 0x000fe200000001ff */
/*04e0*/ IMAD R13, R11, c[0x0][0x184], R24 ; /* 0x000061000b0d7a24 */
/* 0x001fc800078e0218 */
/*04f0*/ IMAD.U32 R12, RZ, RZ, UR8 ; /* 0x00000008ff0c7e24 */
/* 0x000fca000f8e00ff */
/*0500*/ ISETP.LT.AND P2, PT, R12, c[0x0][0x188], !P1 ; /* 0x000062000c007a0c */
/* 0x000fe20004f41270 */
/*0510*/ IMAD.WIDE R12, R13, R28, c[0x0][0x160] ; /* 0x000058000d0c7625 */
/* 0x000fd800078e021c */
/*0520*/ @P2 LDG.E.64 R14, [R12.64] ; /* 0x0000000e0c0e2981 */
/* 0x000ea2000c1e1b00 */
/*0530*/ MOV R16, UR18 ; /* 0x0000001200107c02 */
/* 0x000fe20008000f00 */
/*0540*/ IMAD.U32 R21, RZ, RZ, UR12 ; /* 0x0000000cff157e24 */
/* 0x000fc6000f8e00ff */
/*0550*/ ISETP.GE.OR P3, PT, R16, c[0x0][0x184], !P2 ; /* 0x0000610010007a0c */
/* 0x000fe40005766670 */
/*0560*/ @P2 LEA R21, R21, R6, 0x1 ; /* 0x0000000615152211 */
/* 0x000fca00078e08ff */
/*0570*/ @P2 IMAD.WIDE R20, R21, R28, c[0x0][0x170] ; /* 0x00005c0015142625 */
/* 0x000fca00078e021c */
/*0580*/ @P2 STG.E.64 [R20.64], R14 ; /* 0x0000000e14002986 */
/* 0x0041e8000c101b0e */
/*0590*/ @!P3 LDG.E.64 R18, [R12.64+0x8] ; /* 0x0000080e0c12b981 */
/* 0x000ea2000c1e1b00 */
/*05a0*/ IMAD.U32 R17, RZ, RZ, UR17 ; /* 0x00000011ff117e24 */
/* 0x000fe2000f8e00ff */
/*05b0*/ UIADD3 UR8, UR21, UR4, URZ ; /* 0x0000000415087290 */
/* 0x000fc6000fffe03f */
/*05c0*/ @!P3 IMAD R17, R17, c[0x0][0x180], R6 ; /* 0x000060001111ba24 */
/* 0x000fc600078e0206 */
/*05d0*/ MOV R16, UR8 ; /* 0x0000000800107c02 */
/* 0x000fe20008000f00 */
/*05e0*/ @!P3 IMAD.WIDE R14, R17, R28, c[0x0][0x170] ; /* 0x00005c00110eb625 */
/* 0x001fc600078e021c */
/*05f0*/ ISETP.LT.AND P2, PT, R16, c[0x0][0x188], !P1 ; /* 0x0000620010007a0c */
/* 0x000fe20004f41270 */
/*0600*/ IMAD R16, R23, c[0x0][0x184], R24 ; /* 0x0000610017107a24 */
/* 0x000fc800078e0218 */
/*0610*/ IMAD.WIDE R16, R16, R28, c[0x0][0x160] ; /* 0x0000580010107625 */
/* 0x000fe200078e021c */
/*0620*/ @!P3 STG.E.64 [R14.64], R18 ; /* 0x000000120e00b986 */
/* 0x0041e8000c101b0e */
/*0630*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0640*/ @P2 LDG.E.64 R12, [R16.64] ; /* 0x0000000e100c2981 */
/* 0x000ea2000c1e1b00 */
/*0650*/ MOV R20, UR18 ; /* 0x0000001200147c02 */
/* 0x000fc40008000f00 */
/*0660*/ MOV R21, UR11 ; /* 0x0000000b00157c02 */
/* 0x000fe40008000f00 */
/*0670*/ ISETP.GE.OR P3, PT, R20, c[0x0][0x184], !P2 ; /* 0x0000610014007a0c */
/* 0x000fc60005766670 */
/*0680*/ @P2 IMAD R21, R21, 0x2, R6 ; /* 0x0000000215152824 */
/* 0x000fc800078e0206 */
/*0690*/ @P2 IMAD.WIDE R20, R21, R28, c[0x0][0x170] ; /* 0x00005c0015142625 */
/* 0x000fe200078e021c */
/*06a0*/ MOV R19, UR7 ; /* 0x0000000700137c02 */
/* 0x001fc80008000f00 */
/*06b0*/ @P2 STG.E.64 [R20.64], R12 ; /* 0x0000000c14002986 */
/* 0x0041e8000c101b0e */
/*06c0*/ @!P3 LDG.E.64 R12, [R16.64+0x8] ; /* 0x0000080e100cb981 */
/* 0x001ea2000c1e1b00 */
/*06d0*/ @!P3 IMAD R19, R19, c[0x0][0x180], R6 ; /* 0x000060001313ba24 */
/* 0x000fe200078e0206 */
/*06e0*/ IADD3 R14, R10, -0x1, RZ ; /* 0xffffffff0a0e7810 */
/* 0x000fe20007ffe0ff */
/*06f0*/ IMAD R15, R22, c[0x0][0x184], R24 ; /* 0x00006100160f7a24 */
/* 0x000fe400078e0218 */
/*0700*/ @!P3 IMAD.WIDE R18, R19, R28, c[0x0][0x170] ; /* 0x00005c001312b625 */
/* 0x000fe200078e021c */
/*0710*/ ISETP.LT.AND P2, PT, R14, c[0x0][0x188], !P1 ; /* 0x000062000e007a0c */
/* 0x000fc60004f41270 */
/*0720*/ IMAD.WIDE R14, R15, R28.reuse, c[0x0][0x160] ; /* 0x000058000f0e7625 */
/* 0x080fe200078e021c */
/*0730*/ @!P3 STG.E.64 [R18.64], R12 ; /* 0x0000000c1200b986 */
/* 0x0041e8000c101b0e */
/*0740*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0750*/ @P2 LDG.E.64 R12, [R14.64] ; /* 0x0000000e0e0c2981 */
/* 0x001ea2000c1e1b00 */
/*0760*/ MOV R16, UR18 ; /* 0x0000001200107c02 */
/* 0x000fe20008000f00 */
/*0770*/ @P2 IMAD.WIDE R20, R29, R28, c[0x0][0x170] ; /* 0x00005c001d142625 */
/* 0x000fc600078e021c */
/*0780*/ ISETP.GE.OR P3, PT, R16, c[0x0][0x184], !P2 ; /* 0x0000610010007a0c */
/* 0x000fe40005766670 */
/*0790*/ @P2 STG.E.64 [R20.64], R12 ; /* 0x0000000c14002986 */
/* 0x0041f6000c101b0e */
/*07a0*/ @!P3 LDG.E.64 R14, [R14.64+0x8] ; /* 0x0000080e0e0eb981 */
/* 0x000ea2000c1e1b00 */
/*07b0*/ @!P3 IMAD.WIDE R16, R27, R28, c[0x0][0x170] ; /* 0x00005c001b10b625 */
/* 0x000fe200078e021c */
/*07c0*/ ISETP.LT.AND P2, PT, R10, c[0x0][0x188], !P1 ; /* 0x000062000a007a0c */
/* 0x000fc40004f41270 */
/*07d0*/ IADD3 R19, R26, -0x1, RZ ; /* 0xffffffff1a137810 */
/* 0x000fca0007ffe0ff */
/*07e0*/ IMAD.WIDE R12, R19, R28, c[0x0][0x160] ; /* 0x00005800130c7625 */
/* 0x001fe200078e021c */
/*07f0*/ @!P3 STG.E.64 [R16.64], R14 ; /* 0x0000000e1000b986 */
/* 0x0041e8000c101b0e */
/*0800*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0810*/ @P2 LDG.E.64 R18, [R12.64] ; /* 0x0000000e0c122981 */
/* 0x000ea2000c1e1b00 */
/*0820*/ IMAD.U32 R16, RZ, RZ, UR18 ; /* 0x00000012ff107e24 */
/* 0x001fc4000f8e00ff */
/*0830*/ @P2 IMAD.WIDE R20, R7, R28, c[0x0][0x170] ; /* 0x00005c0007142625 */
/* 0x000fc600078e021c */
/*0840*/ ISETP.GE.OR P3, PT, R16, c[0x0][0x184], !P2 ; /* 0x0000610010007a0c */
/* 0x000fe20005766670 */
/*0850*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fcc000fffe03f */
/*0860*/ IADD3 R16, R5, UR4, RZ ; /* 0x0000000405107c10 */
/* 0x000fe2000fffe0ff */
/*0870*/ @P2 STG.E.64 [R20.64], R18 ; /* 0x0000001214002986 */
/* 0x0041ea000c101b0e */
/*0880*/ @!P3 LDG.E.64 R12, [R12.64+0x8] ; /* 0x0000080e0c0cb981 */
/* 0x000ea2000c1e1b00 */
/*0890*/ ISETP.NE.AND P2, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe20003f45270 */
/*08a0*/ @!P3 IMAD.WIDE R14, R25, R28, c[0x0][0x170] ; /* 0x00005c00190eb625 */
/* 0x000fe200078e021c */
/*08b0*/ IADD3 R10, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fe40007ffe0ff */
/*08c0*/ LEA R26, R9.reuse, R26, 0x2 ; /* 0x0000001a091a7211 */
/* 0x040fe200078e10ff */
/*08d0*/ IMAD R7, R8.reuse, 0x8, R7 ; /* 0x0000000808077824 */
/* 0x040fe200078e0207 */
/*08e0*/ LEA R24, R9, R24, 0x2 ; /* 0x0000001809187211 */
/* 0x000fe200078e10ff */
/*08f0*/ IMAD R27, R8.reuse, 0x8, R27 ; /* 0x00000008081b7824 */
/* 0x040fe200078e021b */
/*0900*/ LEA R25, R8, R25, 0x3 ; /* 0x0000001908197211 */
/* 0x000fc400078e18ff */
/*0910*/ LEA R29, R8.reuse, R29, 0x3 ; /* 0x0000001d081d7211 */
/* 0x040fe400078e18ff */
/*0920*/ LEA R6, R8, R6, 0x3 ; /* 0x0000000608067211 */
/* 0x000fe200078e18ff */
/*0930*/ @!P3 STG.E.64 [R14.64], R12 ; /* 0x0000000c0e00b986 */
/* 0x0041e8000c101b0e */
/*0940*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0950*/ @P2 BRA 0x4c0 ; /* 0xfffffb6000002947 */
/* 0x000fea000383ffff */
/*0960*/ @!P0 BRA 0xc10 ; /* 0x000002a000008947 */
/* 0x000fea0003800000 */
/*0970*/ UIADD3 UR4, UR5, UR4, URZ ; /* 0x0000000405047290 */
/* 0x000fe2000fffe03f */
/*0980*/ MOV R8, c[0x0][0x184] ; /* 0x0000610000087a02 */
/* 0x000fe20000000f00 */
/*0990*/ ULDC UR7, c[0x0][0x180] ; /* 0x0000600000077ab9 */
/* 0x000fe20000000800 */
/*09a0*/ IADD3 R16, -R2, RZ, RZ ; /* 0x000000ff02107210 */
/* 0x000fe20007ffe1ff */
/*09b0*/ ULDC UR5, c[0x0][0xc] ; /* 0x0000030000057ab9 */
/* 0x000fc40000000800 */
/*09c0*/ UIMAD UR5, UR4, UR5, UR13 ; /* 0x00000005040572a4 */
/* 0x000fe2000f8e020d */
/*09d0*/ IMAD.U32 R7, RZ, RZ, UR4 ; /* 0x00000004ff077e24 */
/* 0x000fc6000f8e00ff */
/*09e0*/ UIMAD UR7, UR5, UR7, URZ ; /* 0x00000007050772a4 */
/* 0x000fe4000f8e023f */
/*09f0*/ ULEA UR5, UR5, 0x1, 0x1 ; /* 0x0000000105057891 */
/* 0x000fc8000f8e083f */
/*0a00*/ MOV R6, UR7 ; /* 0x0000000700067c02 */
/* 0x000fc80008000f00 */
/*0a10*/ LEA R5, R6, R3, 0x1 ; /* 0x0000000306057211 */
/* 0x000fe200078e08ff */
/*0a20*/ IMAD R3, R7, c[0x0][0x180], R4 ; /* 0x0000600007037a24 */
/* 0x000fe200078e0204 */
/*0a30*/ MOV R7, UR5 ; /* 0x0000000500077c02 */
/* 0x000fe20008000f00 */
/*0a40*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff067624 */
/* 0x000fe400078e00ff */
/*0a50*/ IMAD R3, R3, R8, UR6 ; /* 0x0000000603037e24 */
/* 0x000fe4000f8e0208 */
/*0a60*/ IMAD R15, R0, c[0x0][0x4], R5 ; /* 0x00000100000f7a24 */
/* 0x001fe400078e0205 */
/*0a70*/ IMAD R17, R6, c[0x0][0xc], RZ ; /* 0x0000030006117a24 */
/* 0x000fe200078e02ff */
/*0a80*/ IADD3 R5, R3, 0x1, RZ ; /* 0x0000000103057810 */
/* 0x000fe20007ffe0ff */
/*0a90*/ IMAD.U32 R0, RZ, RZ, UR4 ; /* 0x00000004ff007e24 */
/* 0x000fc4000f8e00ff */
/*0aa0*/ IMAD R14, R7, c[0x0][0x180], R4 ; /* 0x00006000070e7a24 */
/* 0x000fc600078e0204 */
/*0ab0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x188], PT ; /* 0x0000620000007a0c */
/* 0x000fe20003f06270 */
/*0ac0*/ HFMA2.MMA R11, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff0b7435 */
/* 0x001fe200000001ff */
/*0ad0*/ IADD3 R12, R5, -0x1, RZ ; /* 0xffffffff050c7810 */
/* 0x000fe40007ffe0ff */
/*0ae0*/ ISETP.LT.AND P0, PT, R4, c[0x0][0x180], !P0 ; /* 0x0000600004007a0c */
/* 0x000fce0004701270 */
/*0af0*/ IMAD.WIDE R12, R12, R11, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x000fcc00078e020b */
/*0b00*/ @P0 LDG.E.64 R2, [R12.64] ; /* 0x0000000e0c020981 */
/* 0x000ea2000c1e1b00 */
/*0b10*/ MOV R6, UR18 ; /* 0x0000001200067c02 */
/* 0x000fc80008000f00 */
/*0b20*/ ISETP.GE.OR P1, PT, R6, c[0x0][0x184], !P0 ; /* 0x0000610006007a0c */
/* 0x000fe20004726670 */
/*0b30*/ @P0 IMAD.WIDE R6, R15, R11, c[0x0][0x170] ; /* 0x00005c000f060625 */
/* 0x000fe200078e020b */
/*0b40*/ IADD3 R16, R16, 0x1, RZ ; /* 0x0000000110107810 */
/* 0x000fc80007ffe0ff */
/*0b50*/ @P0 STG.E.64 [R6.64], R2 ; /* 0x0000000206000986 */
/* 0x0041ee000c101b0e */
/*0b60*/ @!P1 LDG.E.64 R8, [R12.64+0x8] ; /* 0x0000080e0c089981 */
/* 0x000ea2000c1e1b00 */
/*0b70*/ ISETP.NE.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe20003f05270 */
/*0b80*/ @!P1 IMAD.WIDE R10, R14, R11, c[0x0][0x170] ; /* 0x00005c000e0a9625 */
/* 0x000fe200078e020b */
/*0b90*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fc40007ffe0ff */
/*0ba0*/ LEA R15, R17.reuse, R15, 0x1 ; /* 0x0000000f110f7211 */
/* 0x040fe200078e08ff */
/*0bb0*/ IMAD.MOV.U32 R18, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff127624 */
/* 0x000fe200078e00ff */
/*0bc0*/ LEA R14, R17, R14, 0x1 ; /* 0x0000000e110e7211 */
/* 0x000fc600078e08ff */
/*0bd0*/ IMAD R5, R18, c[0x0][0x184], R5 ; /* 0x0000610012057a24 */
/* 0x000fe200078e0205 */
/*0be0*/ @!P1 STG.E.64 [R10.64], R8 ; /* 0x000000080a009986 */
/* 0x0041e8000c101b0e */
/*0bf0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0c00*/ @P0 BRA 0xab0 ; /* 0xfffffea000000947 */
/* 0x000fea000383ffff */
/*0c10*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0c20*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c30*/ BRA 0xc30; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void gpu_stencil37_hack1_cp_cols(double * dst, double * shared_rows, double *shared_cols,double *shared_slices,int n_rows, int n_cols,int n_slices,int tile_x,int tile_y, int tile_z){
#ifdef CUDA_DARTS_DEBUG
if((blockIdx.x==0)&&(blockIdx.y==0)&&(blockIdx.z==0)&&(threadIdx.y==0)&& threadIdx.x==0 && threadIdx.z==0){
printf("copy cols begin\n");
printf("gridDim.x=%d,gridDim.y=%d,gridDim.z=%d\n",gridDim.x,gridDim.y,gridDim.z);
printf("blockDim.x=%d,blockDim.y=%d,blockDim.z=%d\n",blockDim.x,blockDim.y,blockDim.z);
printf("tile_x=%d,tile_y=%d,tile_z=%d\n",tile_x,tile_y,tile_z);
}
#endif
int base_global_slice = tile_z * blockIdx.z;
int base_global_row = blockDim.y * blockIdx.y;
int base_global_col = tile_x * blockIdx.x;
int area_dst = n_rows*n_cols;
int area_shared = gridDim.x*n_rows*2;
#ifdef CUDA_CUDA_DEBUG
if((blockIdx.x==0)&&(blockIdx.y==0)&&(blockIdx.z==0)&&(threadIdx.y==0&&threadIdx.x==0&&threadIdx.z==0)){
printf("area_shared=%d\n",area_shared);
}
#endif
int base_global_idx = base_global_slice*area_dst + base_global_row * n_cols + base_global_col;
int nextCol= base_global_col+1;
bool legalNextCol = (nextCol<n_cols)?1:0;
int ty = threadIdx.y;
bool legalCurRow = (base_global_row + ty)<n_rows;
for(int tz=0;tz<tile_z;++tz){
bool legalCurSlice = (base_global_slice + tz)<n_slices;
int idx_dst =base_global_idx + tz*area_dst + ty*n_cols ;
int idx = (base_global_slice+tz)*area_shared + blockIdx.x*2*n_rows+blockIdx.y*blockDim.y+ty;
if(legalCurRow && legalCurSlice){
shared_cols[idx] = dst[idx_dst];
}
if(legalCurRow && legalCurSlice && legalNextCol){
shared_cols[idx + n_rows] = dst[idx_dst + 1];
}
__syncthreads();
}
__syncthreads();
#ifdef CUDA_CUDA_DEBUG
if(blockIdx.z ==0 && blockIdx.y==0 && blockIdx.x==0 && (threadIdx.x==0)){
// printf("shared_cols: addr:%d, val = %f\n", threadIdx.y,shared_cols[threadIdx.y]);
}
#endif
#ifdef CUDA_DARTS_DEBUG
if((blockIdx.x==0)&&(blockIdx.y==0)&&(blockIdx.z==0)&&(threadIdx.y==0 && threadIdx.x==0 && threadIdx.z==0)){
printf("copy cols end!\n");
}
#endif
} | .file "tmpxft_0014ee9b_00000000-6_gpu_stencil37_hack1_cp_cols.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z59__device_stub__Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiiiPdS_S_S_iiiiii
.type _Z59__device_stub__Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiiiPdS_S_S_iiiiii, @function
_Z59__device_stub__Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiiiPdS_S_S_iiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z59__device_stub__Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiiiPdS_S_S_iiiiii, .-_Z59__device_stub__Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiiiPdS_S_S_iiiiii
.globl _Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii
.type _Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii, @function
_Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z59__device_stub__Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiiiPdS_S_S_iiiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii, .-_Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void gpu_stencil37_hack1_cp_cols(double * dst, double * shared_rows, double *shared_cols,double *shared_slices,int n_rows, int n_cols,int n_slices,int tile_x,int tile_y, int tile_z){
#ifdef CUDA_DARTS_DEBUG
if((blockIdx.x==0)&&(blockIdx.y==0)&&(blockIdx.z==0)&&(threadIdx.y==0)&& threadIdx.x==0 && threadIdx.z==0){
printf("copy cols begin\n");
printf("gridDim.x=%d,gridDim.y=%d,gridDim.z=%d\n",gridDim.x,gridDim.y,gridDim.z);
printf("blockDim.x=%d,blockDim.y=%d,blockDim.z=%d\n",blockDim.x,blockDim.y,blockDim.z);
printf("tile_x=%d,tile_y=%d,tile_z=%d\n",tile_x,tile_y,tile_z);
}
#endif
int base_global_slice = tile_z * blockIdx.z;
int base_global_row = blockDim.y * blockIdx.y;
int base_global_col = tile_x * blockIdx.x;
int area_dst = n_rows*n_cols;
int area_shared = gridDim.x*n_rows*2;
#ifdef CUDA_CUDA_DEBUG
if((blockIdx.x==0)&&(blockIdx.y==0)&&(blockIdx.z==0)&&(threadIdx.y==0&&threadIdx.x==0&&threadIdx.z==0)){
printf("area_shared=%d\n",area_shared);
}
#endif
int base_global_idx = base_global_slice*area_dst + base_global_row * n_cols + base_global_col;
int nextCol= base_global_col+1;
bool legalNextCol = (nextCol<n_cols)?1:0;
int ty = threadIdx.y;
bool legalCurRow = (base_global_row + ty)<n_rows;
for(int tz=0;tz<tile_z;++tz){
bool legalCurSlice = (base_global_slice + tz)<n_slices;
int idx_dst =base_global_idx + tz*area_dst + ty*n_cols ;
int idx = (base_global_slice+tz)*area_shared + blockIdx.x*2*n_rows+blockIdx.y*blockDim.y+ty;
if(legalCurRow && legalCurSlice){
shared_cols[idx] = dst[idx_dst];
}
if(legalCurRow && legalCurSlice && legalNextCol){
shared_cols[idx + n_rows] = dst[idx_dst + 1];
}
__syncthreads();
}
__syncthreads();
#ifdef CUDA_CUDA_DEBUG
if(blockIdx.z ==0 && blockIdx.y==0 && blockIdx.x==0 && (threadIdx.x==0)){
// printf("shared_cols: addr:%d, val = %f\n", threadIdx.y,shared_cols[threadIdx.y]);
}
#endif
#ifdef CUDA_DARTS_DEBUG
if((blockIdx.x==0)&&(blockIdx.y==0)&&(blockIdx.z==0)&&(threadIdx.y==0 && threadIdx.x==0 && threadIdx.z==0)){
printf("copy cols end!\n");
}
#endif
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gpu_stencil37_hack1_cp_cols(double * dst, double * shared_rows, double *shared_cols,double *shared_slices,int n_rows, int n_cols,int n_slices,int tile_x,int tile_y, int tile_z){
#ifdef CUDA_DARTS_DEBUG
if((blockIdx.x==0)&&(blockIdx.y==0)&&(blockIdx.z==0)&&(threadIdx.y==0)&& threadIdx.x==0 && threadIdx.z==0){
printf("copy cols begin\n");
printf("gridDim.x=%d,gridDim.y=%d,gridDim.z=%d\n",gridDim.x,gridDim.y,gridDim.z);
printf("blockDim.x=%d,blockDim.y=%d,blockDim.z=%d\n",blockDim.x,blockDim.y,blockDim.z);
printf("tile_x=%d,tile_y=%d,tile_z=%d\n",tile_x,tile_y,tile_z);
}
#endif
int base_global_slice = tile_z * blockIdx.z;
int base_global_row = blockDim.y * blockIdx.y;
int base_global_col = tile_x * blockIdx.x;
int area_dst = n_rows*n_cols;
int area_shared = gridDim.x*n_rows*2;
#ifdef CUDA_CUDA_DEBUG
if((blockIdx.x==0)&&(blockIdx.y==0)&&(blockIdx.z==0)&&(threadIdx.y==0&&threadIdx.x==0&&threadIdx.z==0)){
printf("area_shared=%d\n",area_shared);
}
#endif
int base_global_idx = base_global_slice*area_dst + base_global_row * n_cols + base_global_col;
int nextCol= base_global_col+1;
bool legalNextCol = (nextCol<n_cols)?1:0;
int ty = threadIdx.y;
bool legalCurRow = (base_global_row + ty)<n_rows;
for(int tz=0;tz<tile_z;++tz){
bool legalCurSlice = (base_global_slice + tz)<n_slices;
int idx_dst =base_global_idx + tz*area_dst + ty*n_cols ;
int idx = (base_global_slice+tz)*area_shared + blockIdx.x*2*n_rows+blockIdx.y*blockDim.y+ty;
if(legalCurRow && legalCurSlice){
shared_cols[idx] = dst[idx_dst];
}
if(legalCurRow && legalCurSlice && legalNextCol){
shared_cols[idx + n_rows] = dst[idx_dst + 1];
}
__syncthreads();
}
__syncthreads();
#ifdef CUDA_CUDA_DEBUG
if(blockIdx.z ==0 && blockIdx.y==0 && blockIdx.x==0 && (threadIdx.x==0)){
// printf("shared_cols: addr:%d, val = %f\n", threadIdx.y,shared_cols[threadIdx.y]);
}
#endif
#ifdef CUDA_DARTS_DEBUG
if((blockIdx.x==0)&&(blockIdx.y==0)&&(blockIdx.z==0)&&(threadIdx.y==0 && threadIdx.x==0 && threadIdx.z==0)){
printf("copy cols end!\n");
}
#endif
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gpu_stencil37_hack1_cp_cols(double * dst, double * shared_rows, double *shared_cols,double *shared_slices,int n_rows, int n_cols,int n_slices,int tile_x,int tile_y, int tile_z){
#ifdef CUDA_DARTS_DEBUG
if((blockIdx.x==0)&&(blockIdx.y==0)&&(blockIdx.z==0)&&(threadIdx.y==0)&& threadIdx.x==0 && threadIdx.z==0){
printf("copy cols begin\n");
printf("gridDim.x=%d,gridDim.y=%d,gridDim.z=%d\n",gridDim.x,gridDim.y,gridDim.z);
printf("blockDim.x=%d,blockDim.y=%d,blockDim.z=%d\n",blockDim.x,blockDim.y,blockDim.z);
printf("tile_x=%d,tile_y=%d,tile_z=%d\n",tile_x,tile_y,tile_z);
}
#endif
int base_global_slice = tile_z * blockIdx.z;
int base_global_row = blockDim.y * blockIdx.y;
int base_global_col = tile_x * blockIdx.x;
int area_dst = n_rows*n_cols;
int area_shared = gridDim.x*n_rows*2;
#ifdef CUDA_CUDA_DEBUG
if((blockIdx.x==0)&&(blockIdx.y==0)&&(blockIdx.z==0)&&(threadIdx.y==0&&threadIdx.x==0&&threadIdx.z==0)){
printf("area_shared=%d\n",area_shared);
}
#endif
int base_global_idx = base_global_slice*area_dst + base_global_row * n_cols + base_global_col;
int nextCol= base_global_col+1;
bool legalNextCol = (nextCol<n_cols)?1:0;
int ty = threadIdx.y;
bool legalCurRow = (base_global_row + ty)<n_rows;
for(int tz=0;tz<tile_z;++tz){
bool legalCurSlice = (base_global_slice + tz)<n_slices;
int idx_dst =base_global_idx + tz*area_dst + ty*n_cols ;
int idx = (base_global_slice+tz)*area_shared + blockIdx.x*2*n_rows+blockIdx.y*blockDim.y+ty;
if(legalCurRow && legalCurSlice){
shared_cols[idx] = dst[idx_dst];
}
if(legalCurRow && legalCurSlice && legalNextCol){
shared_cols[idx + n_rows] = dst[idx_dst + 1];
}
__syncthreads();
}
__syncthreads();
#ifdef CUDA_CUDA_DEBUG
if(blockIdx.z ==0 && blockIdx.y==0 && blockIdx.x==0 && (threadIdx.x==0)){
// printf("shared_cols: addr:%d, val = %f\n", threadIdx.y,shared_cols[threadIdx.y]);
}
#endif
#ifdef CUDA_DARTS_DEBUG
if((blockIdx.x==0)&&(blockIdx.y==0)&&(blockIdx.z==0)&&(threadIdx.y==0 && threadIdx.x==0 && threadIdx.z==0)){
printf("copy cols end!\n");
}
#endif
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii
.globl _Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii
.p2align 8
.type _Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii,@function
_Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii:
s_load_b32 s8, s[0:1], 0x34
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s8, 1
s_cbranch_scc1 .LBB0_6
s_clause 0x4
s_load_b128 s[4:7], s[0:1], 0x20
s_load_b32 s9, s[0:1], 0x44
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s17, s[0:1], 0x38
s_load_b64 s[0:1], s[0:1], 0x10
v_bfe_u32 v2, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_mul_i32 s16, s13, s7
s_lshr_b32 s7, s9, 16
s_add_i32 s9, s16, 1
v_mad_u64_u32 v[0:1], null, s14, s7, v[2:3]
s_mul_i32 s7, s15, s8
s_cmp_lt_i32 s9, s5
s_mul_i32 s12, s7, s17
s_mul_i32 s17, s17, s4
s_cselect_b32 s9, -1, 0
s_add_u32 s10, s2, 8
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s7, s4, v[0:1]
s_addc_u32 s11, s3, 0
s_add_i32 s13, s13, s12
v_cmp_le_i32_e32 vcc_lo, s4, v0
s_lshl_b32 s14, s13, 1
s_mul_i32 s12, s4, s13
s_or_b32 s14, s14, 1
s_delay_alu instid0(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s5, v3, s[16:17]
s_lshl_b32 s12, s12, 1
s_lshl_b32 s13, s17, 1
s_mul_i32 s14, s4, s14
s_mul_i32 s4, s5, s4
s_xor_b32 s5, vcc_lo, -1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s15
v_add_nc_u32_e32 v0, s13, v0
v_add_nc_u32_e32 v1, s4, v1
s_add_i32 s8, s8, -1
s_add_i32 s7, s7, 1
s_cmp_eq_u32 s8, 0
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_6
.LBB0_3:
s_cmp_lt_i32 s7, s6
s_cselect_b32 s15, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s16, s5, s15
s_and_saveexec_b32 s15, s16
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v2, 31, v1
v_add_nc_u32_e32 v6, s12, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 3, v[1:2]
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[6:7], 3, v[6:7]
v_add_co_u32 v4, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s0, v6
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
s_and_not1_b32 vcc_lo, exec_lo, s9
s_waitcnt vmcnt(0)
global_store_b64 v[6:7], v[4:5], off
s_cbranch_vccnz .LBB0_2
v_add_co_u32 v2, vcc_lo, s10, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
v_add_nc_u32_e32 v4, s14, v0
global_load_b64 v[2:3], v[2:3], off
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 3, v[4:5]
v_add_co_u32 v4, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_waitcnt vmcnt(0)
global_store_b64 v[4:5], v[2:3], off
s_branch .LBB0_2
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii, .Lfunc_end0-_Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gpu_stencil37_hack1_cp_cols(double * dst, double * shared_rows, double *shared_cols,double *shared_slices,int n_rows, int n_cols,int n_slices,int tile_x,int tile_y, int tile_z){
#ifdef CUDA_DARTS_DEBUG
if((blockIdx.x==0)&&(blockIdx.y==0)&&(blockIdx.z==0)&&(threadIdx.y==0)&& threadIdx.x==0 && threadIdx.z==0){
printf("copy cols begin\n");
printf("gridDim.x=%d,gridDim.y=%d,gridDim.z=%d\n",gridDim.x,gridDim.y,gridDim.z);
printf("blockDim.x=%d,blockDim.y=%d,blockDim.z=%d\n",blockDim.x,blockDim.y,blockDim.z);
printf("tile_x=%d,tile_y=%d,tile_z=%d\n",tile_x,tile_y,tile_z);
}
#endif
int base_global_slice = tile_z * blockIdx.z;
int base_global_row = blockDim.y * blockIdx.y;
int base_global_col = tile_x * blockIdx.x;
int area_dst = n_rows*n_cols;
int area_shared = gridDim.x*n_rows*2;
#ifdef CUDA_CUDA_DEBUG
if((blockIdx.x==0)&&(blockIdx.y==0)&&(blockIdx.z==0)&&(threadIdx.y==0&&threadIdx.x==0&&threadIdx.z==0)){
printf("area_shared=%d\n",area_shared);
}
#endif
int base_global_idx = base_global_slice*area_dst + base_global_row * n_cols + base_global_col;
int nextCol= base_global_col+1;
bool legalNextCol = (nextCol<n_cols)?1:0;
int ty = threadIdx.y;
bool legalCurRow = (base_global_row + ty)<n_rows;
for(int tz=0;tz<tile_z;++tz){
bool legalCurSlice = (base_global_slice + tz)<n_slices;
int idx_dst =base_global_idx + tz*area_dst + ty*n_cols ;
int idx = (base_global_slice+tz)*area_shared + blockIdx.x*2*n_rows+blockIdx.y*blockDim.y+ty;
if(legalCurRow && legalCurSlice){
shared_cols[idx] = dst[idx_dst];
}
if(legalCurRow && legalCurSlice && legalNextCol){
shared_cols[idx + n_rows] = dst[idx_dst + 1];
}
__syncthreads();
}
__syncthreads();
#ifdef CUDA_CUDA_DEBUG
if(blockIdx.z ==0 && blockIdx.y==0 && blockIdx.x==0 && (threadIdx.x==0)){
// printf("shared_cols: addr:%d, val = %f\n", threadIdx.y,shared_cols[threadIdx.y]);
}
#endif
#ifdef CUDA_DARTS_DEBUG
if((blockIdx.x==0)&&(blockIdx.y==0)&&(blockIdx.z==0)&&(threadIdx.y==0 && threadIdx.x==0 && threadIdx.z==0)){
printf("copy cols end!\n");
}
#endif
} | .text
.file "gpu_stencil37_hack1_cp_cols.hip"
.globl _Z42__device_stub__gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii # -- Begin function _Z42__device_stub__gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii
.p2align 4, 0x90
.type _Z42__device_stub__gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii,@function
_Z42__device_stub__gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii: # @_Z42__device_stub__gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z42__device_stub__gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii, .Lfunc_end0-_Z42__device_stub__gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii,@object # @_Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii
.section .rodata,"a",@progbits
.globl _Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii
.p2align 3, 0x0
_Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii:
.quad _Z42__device_stub__gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii
.size _Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii"
.size .L__unnamed_1, 46
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z42__device_stub__gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x194] ; /* 0x00006500ff027624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 BRA 0xc10 ; /* 0x00000bd000008947 */
/* 0x000fea0003800000 */
/*0040*/ S2UR UR13, SR_CTAID.X ; /* 0x00000000000d79c3 */
/* 0x000e220000002500 */
/*0050*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e620000002600 */
/*0060*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe20007ffe0ff */
/*0070*/ ULDC UR6, c[0x0][0x18c] ; /* 0x0000630000067ab9 */
/* 0x000fe20000000800 */
/*0080*/ LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fe200078ec0ff */
/*0090*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*00a0*/ ISETP.GE.U32.AND P1, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f26070 */
/*00b0*/ ULDC UR5, c[0x0][0x194] ; /* 0x0000650000057ab9 */
/* 0x000fe20000000800 */
/*00c0*/ S2UR UR12, SR_CTAID.Z ; /* 0x00000000000c79c3 */
/* 0x000ea20000002700 */
/*00d0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00e0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*00f0*/ ULDC.64 UR14, c[0x0][0x118] ; /* 0x00004600000e7ab9 */
/* 0x000fc40000000a00 */
/*0100*/ UIMAD UR6, UR13, UR6, URZ ; /* 0x000000060d0672a4 */
/* 0x001fc8000f8e023f */
/*0110*/ UIADD3 UR18, UR6, 0x1, URZ ; /* 0x0000000106127890 */
/* 0x000fe2000fffe03f */
/*0120*/ IMAD R4, R0, c[0x0][0x4], R3 ; /* 0x0000010000047a24 */
/* 0x002fe200078e0203 */
/*0130*/ UIMAD UR5, UR12, UR5, URZ ; /* 0x000000050c0572a4 */
/* 0x004fe2000f8e023f */
/*0140*/ @!P1 BRA 0x960 ; /* 0x0000081000009947 */
/* 0x000fec0003800000 */
/*0150*/ UIADD3 UR19, UR5, 0x3, URZ ; /* 0x0000000305137890 */
/* 0x000fe2000fffe03f */
/*0160*/ IMAD.MOV.U32 R26, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff1a7624 */
/* 0x000fe200078e00ff */
/*0170*/ UIADD3 UR20, UR5, 0x2, URZ ; /* 0x0000000205147890 */
/* 0x000fe2000fffe03f */
/*0180*/ IMAD.U32 R10, RZ, RZ, UR5 ; /* 0x00000005ff0a7e24 */
/* 0x000fe2000f8e00ff */
/*0190*/ ULDC UR8, c[0x0][0xc] ; /* 0x0000030000087ab9 */
/* 0x000fe20000000800 */
/*01a0*/ MOV R9, c[0x0][0x180] ; /* 0x0000600000097a02 */
/* 0x000fe20000000f00 */
/*01b0*/ UIADD3 UR21, UR5, 0x1, URZ ; /* 0x0000000105157890 */
/* 0x000fe2000fffe03f */
/*01c0*/ MOV R5, UR19 ; /* 0x0000001300057c02 */
/* 0x000fe20008000f00 */
/*01d0*/ USHF.L.U32 UR7, UR13, 0x1, URZ ; /* 0x000000010d077899 */
/* 0x000fe2000800063f */
/*01e0*/ MOV R7, UR20 ; /* 0x0000001400077c02 */
/* 0x000fe20008000f00 */
/*01f0*/ UIMAD UR4, UR19, UR8, URZ ; /* 0x00000008130472a4 */
/* 0x000fe2000f8e023f */
/*0200*/ IMAD R11, R10, c[0x0][0x180], R3.reuse ; /* 0x000060000a0b7a24 */
/* 0x100fe200078e0203 */
/*0210*/ UIMAD UR9, UR20, UR8, URZ ; /* 0x00000008140972a4 */
/* 0x000fe2000f8e023f */
/*0220*/ IMAD R5, R5, c[0x0][0x180], R4.reuse ; /* 0x0000600005057a24 */
/* 0x100fe200078e0204 */
/*0230*/ ULDC UR16, c[0x0][0x180] ; /* 0x0000600000107ab9 */
/* 0x000fe20000000800 */
/*0240*/ IMAD R22, R7, c[0x0][0x180], R4.reuse ; /* 0x0000600007167a24 */
/* 0x100fe200078e0204 */
/*0250*/ UIMAD UR11, UR21, UR8, URZ ; /* 0x00000008150b72a4 */
/* 0x000fe2000f8e023f */
/*0260*/ IMAD R26, R5, R26, UR6 ; /* 0x00000006051a7e24 */
/* 0x000fe2000f8e021a */
/*0270*/ UIMAD UR12, UR12, UR8, URZ ; /* 0x000000080c0c72a4 */
/* 0x000fe2000f8e023f */
/*0280*/ IMAD.U32 R23, RZ, RZ, UR21 ; /* 0x00000015ff177e24 */
/* 0x000fe2000f8e00ff */
/*0290*/ ULEA UR8, UR4, UR7, 0x1 ; /* 0x0000000704087291 */
/* 0x000fe2000f8e083f */
/*02a0*/ IMAD R8, R9.reuse, c[0x0][0xc], RZ ; /* 0x0000030009087a24 */
/* 0x040fe200078e02ff */
/*02b0*/ ULEA UR10, UR9, UR7, 0x1 ; /* 0x00000007090a7291 */
/* 0x000fe2000f8e083f */
/*02c0*/ ISETP.GE.AND P1, PT, R4, c[0x0][0x180], PT ; /* 0x0000600004007a0c */
/* 0x000fe20003f26270 */
/*02d0*/ USHF.L.U32 UR22, UR16, 0x1, URZ ; /* 0x0000000110167899 */
/* 0x000fe2000800063f */
/*02e0*/ IADD3 R5, R2, -c[0x0][0x194], RZ ; /* 0x8000650002057a10 */
/* 0x000fe20007ffe0ff */
/*02f0*/ UIADD3 UR8, UR8, 0x1, URZ ; /* 0x0000000108087890 */
/* 0x000fe2000fffe03f */
/*0300*/ MOV R6, R4 ; /* 0x0000000400067202 */
/* 0x000fe20000000f00 */
/*0310*/ UIADD3 UR10, UR10, 0x1, URZ ; /* 0x000000010a0a7890 */
/* 0x000fe2000fffe03f */
/*0320*/ IMAD.U32 R24, RZ, RZ, UR6 ; /* 0x00000006ff187e24 */
/* 0x000fe2000f8e00ff */
/*0330*/ UIADD3 UR4, UR4, UR13, URZ ; /* 0x0000000d04047290 */
/* 0x000fe2000fffe03f */
/*0340*/ IMAD.U32 R12, RZ, RZ, UR22 ; /* 0x00000016ff0c7e24 */
/* 0x000fe2000f8e00ff */
/*0350*/ UIADD3 UR9, UR9, UR13, URZ ; /* 0x0000000d09097290 */
/* 0x000fe2000fffe03f */
/*0360*/ MOV R25, UR8 ; /* 0x0000000800197c02 */
/* 0x000fe20008000f00 */
/*0370*/ ULDC UR17, c[0x0][0x194] ; /* 0x0000650000117ab9 */
/* 0x000fe20000000800 */
/*0380*/ MOV R27, UR10 ; /* 0x0000000a001b7c02 */
/* 0x000fe20008000f00 */
/*0390*/ IMAD R7, R12.reuse, UR4, R3.reuse ; /* 0x000000040c077c24 */
/* 0x140fe2000f8e0203 */
/*03a0*/ ULEA UR7, UR11, UR7, 0x1 ; /* 0x000000070b077291 */
/* 0x000fe2000f8e083f */
/*03b0*/ IMAD R29, R12, UR9, R3 ; /* 0x000000090c1d7c24 */
/* 0x000fe2000f8e0203 */
/*03c0*/ UIMAD UR12, UR12, UR17, UR13 ; /* 0x000000110c0c72a4 */
/* 0x000fe2000f8e020d */
/*03d0*/ IMAD R9, R9, c[0x0][0x184], RZ ; /* 0x0000610009097a24 */
/* 0x000fe200078e02ff */
/*03e0*/ UIADD3 UR11, UR11, UR13, URZ ; /* 0x0000000d0b0b7290 */
/* 0x000fe2000fffe03f */
/*03f0*/ MOV R10, UR19 ; /* 0x00000013000a7c02 */
/* 0x000fe20008000f00 */
/*0400*/ IMAD R11, R0, c[0x0][0x4], R11 ; /* 0x00000100000b7a24 */
/* 0x000fe200078e020b */
/*0410*/ IADD3 R26, R26, 0x1, RZ ; /* 0x000000011a1a7810 */
/* 0x000fe20007ffe0ff */
/*0420*/ IMAD R23, R23, c[0x0][0x180], R4.reuse ; /* 0x0000600017177a24 */
/* 0x100fe200078e0204 */
/*0430*/ ULEA UR17, UR12, 0x1, 0x1 ; /* 0x000000010c117891 */
/* 0x000fe2000f8e083f */
/*0440*/ IMAD R7, R0.reuse, c[0x0][0x4], R7 ; /* 0x0000010000077a24 */
/* 0x040fe200078e0207 */
/*0450*/ UIADD3 UR7, UR7, 0x1, URZ ; /* 0x0000000107077890 */
/* 0x000fe2000fffe03f */
/*0460*/ IMAD R29, R0, c[0x0][0x4], R29 ; /* 0x00000100001d7a24 */
/* 0x000fe200078e021d */
/*0470*/ UIMAD UR11, UR11, UR16, URZ ; /* 0x000000100b0b72a4 */
/* 0x000fe2000f8e023f */
/*0480*/ IMAD R25, R25, c[0x0][0x180], R4.reuse ; /* 0x0000600019197a24 */
/* 0x100fe200078e0204 */
/*0490*/ UIMAD UR12, UR12, UR16, URZ ; /* 0x000000100c0c72a4 */
/* 0x000fe2000f8e023f */
/*04a0*/ IMAD R27, R27, c[0x0][0x180], R4 ; /* 0x000060001b1b7a24 */
/* 0x000fe200078e0204 */
/*04b0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fc40008000000 */
/*04c0*/ UIADD3 UR8, UR5, UR4, URZ ; /* 0x0000000405087290 */
/* 0x000fe2000fffe03f */
/*04d0*/ HFMA2.MMA R28, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff1c7435 */
/* 0x000fe200000001ff */
/*04e0*/ IMAD R13, R11, c[0x0][0x184], R24 ; /* 0x000061000b0d7a24 */
/* 0x001fc800078e0218 */
/*04f0*/ IMAD.U32 R12, RZ, RZ, UR8 ; /* 0x00000008ff0c7e24 */
/* 0x000fca000f8e00ff */
/*0500*/ ISETP.LT.AND P2, PT, R12, c[0x0][0x188], !P1 ; /* 0x000062000c007a0c */
/* 0x000fe20004f41270 */
/*0510*/ IMAD.WIDE R12, R13, R28, c[0x0][0x160] ; /* 0x000058000d0c7625 */
/* 0x000fd800078e021c */
/*0520*/ @P2 LDG.E.64 R14, [R12.64] ; /* 0x0000000e0c0e2981 */
/* 0x000ea2000c1e1b00 */
/*0530*/ MOV R16, UR18 ; /* 0x0000001200107c02 */
/* 0x000fe20008000f00 */
/*0540*/ IMAD.U32 R21, RZ, RZ, UR12 ; /* 0x0000000cff157e24 */
/* 0x000fc6000f8e00ff */
/*0550*/ ISETP.GE.OR P3, PT, R16, c[0x0][0x184], !P2 ; /* 0x0000610010007a0c */
/* 0x000fe40005766670 */
/*0560*/ @P2 LEA R21, R21, R6, 0x1 ; /* 0x0000000615152211 */
/* 0x000fca00078e08ff */
/*0570*/ @P2 IMAD.WIDE R20, R21, R28, c[0x0][0x170] ; /* 0x00005c0015142625 */
/* 0x000fca00078e021c */
/*0580*/ @P2 STG.E.64 [R20.64], R14 ; /* 0x0000000e14002986 */
/* 0x0041e8000c101b0e */
/*0590*/ @!P3 LDG.E.64 R18, [R12.64+0x8] ; /* 0x0000080e0c12b981 */
/* 0x000ea2000c1e1b00 */
/*05a0*/ IMAD.U32 R17, RZ, RZ, UR17 ; /* 0x00000011ff117e24 */
/* 0x000fe2000f8e00ff */
/*05b0*/ UIADD3 UR8, UR21, UR4, URZ ; /* 0x0000000415087290 */
/* 0x000fc6000fffe03f */
/*05c0*/ @!P3 IMAD R17, R17, c[0x0][0x180], R6 ; /* 0x000060001111ba24 */
/* 0x000fc600078e0206 */
/*05d0*/ MOV R16, UR8 ; /* 0x0000000800107c02 */
/* 0x000fe20008000f00 */
/*05e0*/ @!P3 IMAD.WIDE R14, R17, R28, c[0x0][0x170] ; /* 0x00005c00110eb625 */
/* 0x001fc600078e021c */
/*05f0*/ ISETP.LT.AND P2, PT, R16, c[0x0][0x188], !P1 ; /* 0x0000620010007a0c */
/* 0x000fe20004f41270 */
/*0600*/ IMAD R16, R23, c[0x0][0x184], R24 ; /* 0x0000610017107a24 */
/* 0x000fc800078e0218 */
/*0610*/ IMAD.WIDE R16, R16, R28, c[0x0][0x160] ; /* 0x0000580010107625 */
/* 0x000fe200078e021c */
/*0620*/ @!P3 STG.E.64 [R14.64], R18 ; /* 0x000000120e00b986 */
/* 0x0041e8000c101b0e */
/*0630*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0640*/ @P2 LDG.E.64 R12, [R16.64] ; /* 0x0000000e100c2981 */
/* 0x000ea2000c1e1b00 */
/*0650*/ MOV R20, UR18 ; /* 0x0000001200147c02 */
/* 0x000fc40008000f00 */
/*0660*/ MOV R21, UR11 ; /* 0x0000000b00157c02 */
/* 0x000fe40008000f00 */
/*0670*/ ISETP.GE.OR P3, PT, R20, c[0x0][0x184], !P2 ; /* 0x0000610014007a0c */
/* 0x000fc60005766670 */
/*0680*/ @P2 IMAD R21, R21, 0x2, R6 ; /* 0x0000000215152824 */
/* 0x000fc800078e0206 */
/*0690*/ @P2 IMAD.WIDE R20, R21, R28, c[0x0][0x170] ; /* 0x00005c0015142625 */
/* 0x000fe200078e021c */
/*06a0*/ MOV R19, UR7 ; /* 0x0000000700137c02 */
/* 0x001fc80008000f00 */
/*06b0*/ @P2 STG.E.64 [R20.64], R12 ; /* 0x0000000c14002986 */
/* 0x0041e8000c101b0e */
/*06c0*/ @!P3 LDG.E.64 R12, [R16.64+0x8] ; /* 0x0000080e100cb981 */
/* 0x001ea2000c1e1b00 */
/*06d0*/ @!P3 IMAD R19, R19, c[0x0][0x180], R6 ; /* 0x000060001313ba24 */
/* 0x000fe200078e0206 */
/*06e0*/ IADD3 R14, R10, -0x1, RZ ; /* 0xffffffff0a0e7810 */
/* 0x000fe20007ffe0ff */
/*06f0*/ IMAD R15, R22, c[0x0][0x184], R24 ; /* 0x00006100160f7a24 */
/* 0x000fe400078e0218 */
/*0700*/ @!P3 IMAD.WIDE R18, R19, R28, c[0x0][0x170] ; /* 0x00005c001312b625 */
/* 0x000fe200078e021c */
/*0710*/ ISETP.LT.AND P2, PT, R14, c[0x0][0x188], !P1 ; /* 0x000062000e007a0c */
/* 0x000fc60004f41270 */
/*0720*/ IMAD.WIDE R14, R15, R28.reuse, c[0x0][0x160] ; /* 0x000058000f0e7625 */
/* 0x080fe200078e021c */
/*0730*/ @!P3 STG.E.64 [R18.64], R12 ; /* 0x0000000c1200b986 */
/* 0x0041e8000c101b0e */
/*0740*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0750*/ @P2 LDG.E.64 R12, [R14.64] ; /* 0x0000000e0e0c2981 */
/* 0x001ea2000c1e1b00 */
/*0760*/ MOV R16, UR18 ; /* 0x0000001200107c02 */
/* 0x000fe20008000f00 */
/*0770*/ @P2 IMAD.WIDE R20, R29, R28, c[0x0][0x170] ; /* 0x00005c001d142625 */
/* 0x000fc600078e021c */
/*0780*/ ISETP.GE.OR P3, PT, R16, c[0x0][0x184], !P2 ; /* 0x0000610010007a0c */
/* 0x000fe40005766670 */
/*0790*/ @P2 STG.E.64 [R20.64], R12 ; /* 0x0000000c14002986 */
/* 0x0041f6000c101b0e */
/*07a0*/ @!P3 LDG.E.64 R14, [R14.64+0x8] ; /* 0x0000080e0e0eb981 */
/* 0x000ea2000c1e1b00 */
/*07b0*/ @!P3 IMAD.WIDE R16, R27, R28, c[0x0][0x170] ; /* 0x00005c001b10b625 */
/* 0x000fe200078e021c */
/*07c0*/ ISETP.LT.AND P2, PT, R10, c[0x0][0x188], !P1 ; /* 0x000062000a007a0c */
/* 0x000fc40004f41270 */
/*07d0*/ IADD3 R19, R26, -0x1, RZ ; /* 0xffffffff1a137810 */
/* 0x000fca0007ffe0ff */
/*07e0*/ IMAD.WIDE R12, R19, R28, c[0x0][0x160] ; /* 0x00005800130c7625 */
/* 0x001fe200078e021c */
/*07f0*/ @!P3 STG.E.64 [R16.64], R14 ; /* 0x0000000e1000b986 */
/* 0x0041e8000c101b0e */
/*0800*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0810*/ @P2 LDG.E.64 R18, [R12.64] ; /* 0x0000000e0c122981 */
/* 0x000ea2000c1e1b00 */
/*0820*/ IMAD.U32 R16, RZ, RZ, UR18 ; /* 0x00000012ff107e24 */
/* 0x001fc4000f8e00ff */
/*0830*/ @P2 IMAD.WIDE R20, R7, R28, c[0x0][0x170] ; /* 0x00005c0007142625 */
/* 0x000fc600078e021c */
/*0840*/ ISETP.GE.OR P3, PT, R16, c[0x0][0x184], !P2 ; /* 0x0000610010007a0c */
/* 0x000fe20005766670 */
/*0850*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fcc000fffe03f */
/*0860*/ IADD3 R16, R5, UR4, RZ ; /* 0x0000000405107c10 */
/* 0x000fe2000fffe0ff */
/*0870*/ @P2 STG.E.64 [R20.64], R18 ; /* 0x0000001214002986 */
/* 0x0041ea000c101b0e */
/*0880*/ @!P3 LDG.E.64 R12, [R12.64+0x8] ; /* 0x0000080e0c0cb981 */
/* 0x000ea2000c1e1b00 */
/*0890*/ ISETP.NE.AND P2, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe20003f45270 */
/*08a0*/ @!P3 IMAD.WIDE R14, R25, R28, c[0x0][0x170] ; /* 0x00005c00190eb625 */
/* 0x000fe200078e021c */
/*08b0*/ IADD3 R10, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fe40007ffe0ff */
/*08c0*/ LEA R26, R9.reuse, R26, 0x2 ; /* 0x0000001a091a7211 */
/* 0x040fe200078e10ff */
/*08d0*/ IMAD R7, R8.reuse, 0x8, R7 ; /* 0x0000000808077824 */
/* 0x040fe200078e0207 */
/*08e0*/ LEA R24, R9, R24, 0x2 ; /* 0x0000001809187211 */
/* 0x000fe200078e10ff */
/*08f0*/ IMAD R27, R8.reuse, 0x8, R27 ; /* 0x00000008081b7824 */
/* 0x040fe200078e021b */
/*0900*/ LEA R25, R8, R25, 0x3 ; /* 0x0000001908197211 */
/* 0x000fc400078e18ff */
/*0910*/ LEA R29, R8.reuse, R29, 0x3 ; /* 0x0000001d081d7211 */
/* 0x040fe400078e18ff */
/*0920*/ LEA R6, R8, R6, 0x3 ; /* 0x0000000608067211 */
/* 0x000fe200078e18ff */
/*0930*/ @!P3 STG.E.64 [R14.64], R12 ; /* 0x0000000c0e00b986 */
/* 0x0041e8000c101b0e */
/*0940*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0950*/ @P2 BRA 0x4c0 ; /* 0xfffffb6000002947 */
/* 0x000fea000383ffff */
/*0960*/ @!P0 BRA 0xc10 ; /* 0x000002a000008947 */
/* 0x000fea0003800000 */
/*0970*/ UIADD3 UR4, UR5, UR4, URZ ; /* 0x0000000405047290 */
/* 0x000fe2000fffe03f */
/*0980*/ MOV R8, c[0x0][0x184] ; /* 0x0000610000087a02 */
/* 0x000fe20000000f00 */
/*0990*/ ULDC UR7, c[0x0][0x180] ; /* 0x0000600000077ab9 */
/* 0x000fe20000000800 */
/*09a0*/ IADD3 R16, -R2, RZ, RZ ; /* 0x000000ff02107210 */
/* 0x000fe20007ffe1ff */
/*09b0*/ ULDC UR5, c[0x0][0xc] ; /* 0x0000030000057ab9 */
/* 0x000fc40000000800 */
/*09c0*/ UIMAD UR5, UR4, UR5, UR13 ; /* 0x00000005040572a4 */
/* 0x000fe2000f8e020d */
/*09d0*/ IMAD.U32 R7, RZ, RZ, UR4 ; /* 0x00000004ff077e24 */
/* 0x000fc6000f8e00ff */
/*09e0*/ UIMAD UR7, UR5, UR7, URZ ; /* 0x00000007050772a4 */
/* 0x000fe4000f8e023f */
/*09f0*/ ULEA UR5, UR5, 0x1, 0x1 ; /* 0x0000000105057891 */
/* 0x000fc8000f8e083f */
/*0a00*/ MOV R6, UR7 ; /* 0x0000000700067c02 */
/* 0x000fc80008000f00 */
/*0a10*/ LEA R5, R6, R3, 0x1 ; /* 0x0000000306057211 */
/* 0x000fe200078e08ff */
/*0a20*/ IMAD R3, R7, c[0x0][0x180], R4 ; /* 0x0000600007037a24 */
/* 0x000fe200078e0204 */
/*0a30*/ MOV R7, UR5 ; /* 0x0000000500077c02 */
/* 0x000fe20008000f00 */
/*0a40*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff067624 */
/* 0x000fe400078e00ff */
/*0a50*/ IMAD R3, R3, R8, UR6 ; /* 0x0000000603037e24 */
/* 0x000fe4000f8e0208 */
/*0a60*/ IMAD R15, R0, c[0x0][0x4], R5 ; /* 0x00000100000f7a24 */
/* 0x001fe400078e0205 */
/*0a70*/ IMAD R17, R6, c[0x0][0xc], RZ ; /* 0x0000030006117a24 */
/* 0x000fe200078e02ff */
/*0a80*/ IADD3 R5, R3, 0x1, RZ ; /* 0x0000000103057810 */
/* 0x000fe20007ffe0ff */
/*0a90*/ IMAD.U32 R0, RZ, RZ, UR4 ; /* 0x00000004ff007e24 */
/* 0x000fc4000f8e00ff */
/*0aa0*/ IMAD R14, R7, c[0x0][0x180], R4 ; /* 0x00006000070e7a24 */
/* 0x000fc600078e0204 */
/*0ab0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x188], PT ; /* 0x0000620000007a0c */
/* 0x000fe20003f06270 */
/*0ac0*/ HFMA2.MMA R11, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff0b7435 */
/* 0x001fe200000001ff */
/*0ad0*/ IADD3 R12, R5, -0x1, RZ ; /* 0xffffffff050c7810 */
/* 0x000fe40007ffe0ff */
/*0ae0*/ ISETP.LT.AND P0, PT, R4, c[0x0][0x180], !P0 ; /* 0x0000600004007a0c */
/* 0x000fce0004701270 */
/*0af0*/ IMAD.WIDE R12, R12, R11, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x000fcc00078e020b */
/*0b00*/ @P0 LDG.E.64 R2, [R12.64] ; /* 0x0000000e0c020981 */
/* 0x000ea2000c1e1b00 */
/*0b10*/ MOV R6, UR18 ; /* 0x0000001200067c02 */
/* 0x000fc80008000f00 */
/*0b20*/ ISETP.GE.OR P1, PT, R6, c[0x0][0x184], !P0 ; /* 0x0000610006007a0c */
/* 0x000fe20004726670 */
/*0b30*/ @P0 IMAD.WIDE R6, R15, R11, c[0x0][0x170] ; /* 0x00005c000f060625 */
/* 0x000fe200078e020b */
/*0b40*/ IADD3 R16, R16, 0x1, RZ ; /* 0x0000000110107810 */
/* 0x000fc80007ffe0ff */
/*0b50*/ @P0 STG.E.64 [R6.64], R2 ; /* 0x0000000206000986 */
/* 0x0041ee000c101b0e */
/*0b60*/ @!P1 LDG.E.64 R8, [R12.64+0x8] ; /* 0x0000080e0c089981 */
/* 0x000ea2000c1e1b00 */
/*0b70*/ ISETP.NE.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe20003f05270 */
/*0b80*/ @!P1 IMAD.WIDE R10, R14, R11, c[0x0][0x170] ; /* 0x00005c000e0a9625 */
/* 0x000fe200078e020b */
/*0b90*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fc40007ffe0ff */
/*0ba0*/ LEA R15, R17.reuse, R15, 0x1 ; /* 0x0000000f110f7211 */
/* 0x040fe200078e08ff */
/*0bb0*/ IMAD.MOV.U32 R18, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff127624 */
/* 0x000fe200078e00ff */
/*0bc0*/ LEA R14, R17, R14, 0x1 ; /* 0x0000000e110e7211 */
/* 0x000fc600078e08ff */
/*0bd0*/ IMAD R5, R18, c[0x0][0x184], R5 ; /* 0x0000610012057a24 */
/* 0x000fe200078e0205 */
/*0be0*/ @!P1 STG.E.64 [R10.64], R8 ; /* 0x000000080a009986 */
/* 0x0041e8000c101b0e */
/*0bf0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0c00*/ @P0 BRA 0xab0 ; /* 0xfffffea000000947 */
/* 0x000fea000383ffff */
/*0c10*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0c20*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c30*/ BRA 0xc30; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii
.globl _Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii
.p2align 8
.type _Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii,@function
_Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii:
s_load_b32 s8, s[0:1], 0x34
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s8, 1
s_cbranch_scc1 .LBB0_6
s_clause 0x4
s_load_b128 s[4:7], s[0:1], 0x20
s_load_b32 s9, s[0:1], 0x44
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s17, s[0:1], 0x38
s_load_b64 s[0:1], s[0:1], 0x10
v_bfe_u32 v2, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_mul_i32 s16, s13, s7
s_lshr_b32 s7, s9, 16
s_add_i32 s9, s16, 1
v_mad_u64_u32 v[0:1], null, s14, s7, v[2:3]
s_mul_i32 s7, s15, s8
s_cmp_lt_i32 s9, s5
s_mul_i32 s12, s7, s17
s_mul_i32 s17, s17, s4
s_cselect_b32 s9, -1, 0
s_add_u32 s10, s2, 8
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s7, s4, v[0:1]
s_addc_u32 s11, s3, 0
s_add_i32 s13, s13, s12
v_cmp_le_i32_e32 vcc_lo, s4, v0
s_lshl_b32 s14, s13, 1
s_mul_i32 s12, s4, s13
s_or_b32 s14, s14, 1
s_delay_alu instid0(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s5, v3, s[16:17]
s_lshl_b32 s12, s12, 1
s_lshl_b32 s13, s17, 1
s_mul_i32 s14, s4, s14
s_mul_i32 s4, s5, s4
s_xor_b32 s5, vcc_lo, -1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s15
v_add_nc_u32_e32 v0, s13, v0
v_add_nc_u32_e32 v1, s4, v1
s_add_i32 s8, s8, -1
s_add_i32 s7, s7, 1
s_cmp_eq_u32 s8, 0
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_6
.LBB0_3:
s_cmp_lt_i32 s7, s6
s_cselect_b32 s15, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s16, s5, s15
s_and_saveexec_b32 s15, s16
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v2, 31, v1
v_add_nc_u32_e32 v6, s12, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 3, v[1:2]
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[6:7], 3, v[6:7]
v_add_co_u32 v4, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s0, v6
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
s_and_not1_b32 vcc_lo, exec_lo, s9
s_waitcnt vmcnt(0)
global_store_b64 v[6:7], v[4:5], off
s_cbranch_vccnz .LBB0_2
v_add_co_u32 v2, vcc_lo, s10, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
v_add_nc_u32_e32 v4, s14, v0
global_load_b64 v[2:3], v[2:3], off
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 3, v[4:5]
v_add_co_u32 v4, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_waitcnt vmcnt(0)
global_store_b64 v[4:5], v[2:3], off
s_branch .LBB0_2
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii, .Lfunc_end0-_Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014ee9b_00000000-6_gpu_stencil37_hack1_cp_cols.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z59__device_stub__Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiiiPdS_S_S_iiiiii
.type _Z59__device_stub__Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiiiPdS_S_S_iiiiii, @function
_Z59__device_stub__Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiiiPdS_S_S_iiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z59__device_stub__Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiiiPdS_S_S_iiiiii, .-_Z59__device_stub__Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiiiPdS_S_S_iiiiii
.globl _Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii
.type _Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii, @function
_Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z59__device_stub__Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiiiPdS_S_S_iiiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii, .-_Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gpu_stencil37_hack1_cp_cols.hip"
.globl _Z42__device_stub__gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii # -- Begin function _Z42__device_stub__gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii
.p2align 4, 0x90
.type _Z42__device_stub__gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii,@function
_Z42__device_stub__gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii: # @_Z42__device_stub__gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z42__device_stub__gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii, .Lfunc_end0-_Z42__device_stub__gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii,@object # @_Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii
.section .rodata,"a",@progbits
.globl _Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii
.p2align 3, 0x0
_Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii:
.quad _Z42__device_stub__gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii
.size _Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii"
.size .L__unnamed_1, 46
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z42__device_stub__gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z27gpu_stencil37_hack1_cp_colsPdS_S_S_iiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <stdio.h>
void printMatrix(float *matrix, int rows, int columns)
{
for (int i = 0; i < rows; i++) {
for (int j = 0; j < columns; j++)
printf("%g\t", matrix[i * columns + j]);
printf("\n");
}
printf("\n");
}
void Output(float* a, int N)
{
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
fprintf(stdout, "%g\t", a[j + i * N]);
}
fprintf(stdout, "\n");
}
fprintf(stdout, "\n");
}
__global__ void initMatrix_1D(float *matrix)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
matrix[i] = i;
}
__global__ void initMatrix(float *matrix)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
int I = gridDim.x * blockDim.x;
matrix[i + j * I] = (float) (i + j * I);
}
__global__ void transp(float *matrix, float *matrix_t, int N)
{
int x = threadIdx.x + blockDim.x * blockIdx.x;
int y = threadIdx.y + blockDim.y * blockIdx.y;
matrix_t[y * N + x] = matrix[x * N + y];
}
int main(int argc, char *argv[])
{
int N = (argc > 1) ? atoi(argv[1]) : 4;
int size_matrix = N * N;
int block_x = (argc > 2) ? atoi(argv[2]) : 1;
int block_y = block_x;
float *dmatrix1, *hmatrix1;
float *dmatrix2, *hmatrix2;
cudaMalloc((void**) &dmatrix1, size_matrix * sizeof(float));
cudaMalloc((void**) &dmatrix2, size_matrix * sizeof(float));
hmatrix1 = (float*) calloc(size_matrix, sizeof(float));
hmatrix2 = (float*) calloc(size_matrix, sizeof(float));
dim3 dimGrid = dim3(N / block_x, N / block_y, 1);
dim3 dimBlock = dim3(block_x, block_y, 1);
printf("Size matrix(%dx%d): %d\n", N, N, N * N);
printf("gridDim.x = %d gridDim.y = %d\n", dimGrid.x, dimGrid.y);
printf("blockDim.x = %d blockDim.y = %d\n", dimBlock.x, dimBlock.y);
initMatrix<<<dimGrid, dimBlock>>>(dmatrix1);
cudaDeviceSynchronize();
cudaMemcpy(hmatrix1, dmatrix1, size_matrix * sizeof(float), cudaMemcpyDeviceToHost);
Output(hmatrix1, N);
transp<<<dimGrid, dimBlock>>>(dmatrix1, dmatrix2, N);
cudaDeviceSynchronize();
cudaMemcpy(hmatrix2, dmatrix2, size_matrix * sizeof(float), cudaMemcpyDeviceToHost);
Output(hmatrix2, N);
#if 0
float *test_matrix = (float*) calloc(size_matrix, sizeof(float));
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
test_matrix[j * N + i] = hmatrix1[i * N + j];
}
}
Output(test_matrix, N);
free(test_matrix);
#endif
cudaFree(dmatrix1);
cudaFree(dmatrix2);
free(hmatrix1);
free(hmatrix2);
return 0;
} | code for sm_80
Function : _Z6transpPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002200 */
/*0060*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002600 */
/*0070*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fc400078e0200 */
/*0080*/ IMAD R5, R2, c[0x0][0x4], R5 ; /* 0x0000010002057a24 */
/* 0x002fc800078e0205 */
/*0090*/ IMAD R2, R0, c[0x0][0x170], R5 ; /* 0x00005c0000027a24 */
/* 0x000fc800078e0205 */
/*00a0*/ IMAD.WIDE R2, R2, R4, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0204 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD R5, R5, c[0x0][0x170], R0 ; /* 0x00005c0005057a24 */
/* 0x000fc800078e0200 */
/*00d0*/ IMAD.WIDE R4, R5, R4, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e0204 */
/*00e0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10initMatrixPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e280000002600 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000ea20000002100 */
/*0060*/ IMAD R0, R7, c[0x0][0x4], R0 ; /* 0x0000010007007a24 */
/* 0x001fc800078e0200 */
/*0070*/ IMAD R0, R0, c[0x0][0xc], R5 ; /* 0x0000030000007a24 */
/* 0x002fc800078e0205 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x004fe200078e0203 */
/*0090*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fc600000001ff */
/*00a0*/ I2F R5, R0 ; /* 0x0000000000057306 */
/* 0x000e2e0000201400 */
/*00b0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*00c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z13initMatrix_1DPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0040*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fe200078e0200 */
/*0050*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fc600000001ff */
/*0060*/ I2F R5, R0 ; /* 0x0000000000057306 */
/* 0x000e2e0000201400 */
/*0070*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0080*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <stdio.h>
void printMatrix(float *matrix, int rows, int columns)
{
for (int i = 0; i < rows; i++) {
for (int j = 0; j < columns; j++)
printf("%g\t", matrix[i * columns + j]);
printf("\n");
}
printf("\n");
}
void Output(float* a, int N)
{
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
fprintf(stdout, "%g\t", a[j + i * N]);
}
fprintf(stdout, "\n");
}
fprintf(stdout, "\n");
}
__global__ void initMatrix_1D(float *matrix)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
matrix[i] = i;
}
__global__ void initMatrix(float *matrix)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
int I = gridDim.x * blockDim.x;
matrix[i + j * I] = (float) (i + j * I);
}
__global__ void transp(float *matrix, float *matrix_t, int N)
{
int x = threadIdx.x + blockDim.x * blockIdx.x;
int y = threadIdx.y + blockDim.y * blockIdx.y;
matrix_t[y * N + x] = matrix[x * N + y];
}
int main(int argc, char *argv[])
{
int N = (argc > 1) ? atoi(argv[1]) : 4;
int size_matrix = N * N;
int block_x = (argc > 2) ? atoi(argv[2]) : 1;
int block_y = block_x;
float *dmatrix1, *hmatrix1;
float *dmatrix2, *hmatrix2;
cudaMalloc((void**) &dmatrix1, size_matrix * sizeof(float));
cudaMalloc((void**) &dmatrix2, size_matrix * sizeof(float));
hmatrix1 = (float*) calloc(size_matrix, sizeof(float));
hmatrix2 = (float*) calloc(size_matrix, sizeof(float));
dim3 dimGrid = dim3(N / block_x, N / block_y, 1);
dim3 dimBlock = dim3(block_x, block_y, 1);
printf("Size matrix(%dx%d): %d\n", N, N, N * N);
printf("gridDim.x = %d gridDim.y = %d\n", dimGrid.x, dimGrid.y);
printf("blockDim.x = %d blockDim.y = %d\n", dimBlock.x, dimBlock.y);
initMatrix<<<dimGrid, dimBlock>>>(dmatrix1);
cudaDeviceSynchronize();
cudaMemcpy(hmatrix1, dmatrix1, size_matrix * sizeof(float), cudaMemcpyDeviceToHost);
Output(hmatrix1, N);
transp<<<dimGrid, dimBlock>>>(dmatrix1, dmatrix2, N);
cudaDeviceSynchronize();
cudaMemcpy(hmatrix2, dmatrix2, size_matrix * sizeof(float), cudaMemcpyDeviceToHost);
Output(hmatrix2, N);
#if 0
float *test_matrix = (float*) calloc(size_matrix, sizeof(float));
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
test_matrix[j * N + i] = hmatrix1[i * N + j];
}
}
Output(test_matrix, N);
free(test_matrix);
#endif
cudaFree(dmatrix1);
cudaFree(dmatrix2);
free(hmatrix1);
free(hmatrix2);
return 0;
} | .file "tmpxft_0008bb51_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%g\t"
.LC1:
.string "\n"
.text
.globl _Z11printMatrixPfii
.type _Z11printMatrixPfii, @function
_Z11printMatrixPfii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
movl %esi, 12(%rsp)
testl %esi, %esi
jle .L4
movl %edx, %r15d
movl $0, %r14d
movl $0, %r13d
movslq %edx, %rax
movq %rax, 24(%rsp)
leaq .LC0(%rip), %r12
jmp .L5
.L7:
movslq %r14d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 24(%rsp), %rdx
addq %rdx, %rax
leaq (%rcx,%rax,4), %rbp
.L6:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L6
.L8:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addl %r15d, %r14d
cmpl %r13d, 12(%rsp)
je .L4
.L5:
testl %r15d, %r15d
jg .L7
jmp .L8
.L4:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11printMatrixPfii, .-_Z11printMatrixPfii
.globl _Z6OutputPfi
.type _Z6OutputPfi, @function
_Z6OutputPfi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %esi, 12(%rsp)
testl %esi, %esi
jle .L12
movslq %esi, %r14
leaq 0(,%r14,4), %r15
leaq (%rdi,%r15), %rbp
negq %r14
salq $2, %r14
movl $0, %r13d
leaq .LC0(%rip), %r12
.L13:
leaq 0(%rbp,%r14), %rbx
.L14:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L14
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1, %r13d
addq %r15, %rbp
cmpl %r13d, 12(%rsp)
jne .L13
.L12:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z6OutputPfi, .-_Z6OutputPfi
.globl _Z33__device_stub__Z13initMatrix_1DPfPf
.type _Z33__device_stub__Z13initMatrix_1DPfPf, @function
_Z33__device_stub__Z13initMatrix_1DPfPf:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13initMatrix_1DPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z33__device_stub__Z13initMatrix_1DPfPf, .-_Z33__device_stub__Z13initMatrix_1DPfPf
.globl _Z13initMatrix_1DPf
.type _Z13initMatrix_1DPf, @function
_Z13initMatrix_1DPf:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z13initMatrix_1DPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z13initMatrix_1DPf, .-_Z13initMatrix_1DPf
.globl _Z30__device_stub__Z10initMatrixPfPf
.type _Z30__device_stub__Z10initMatrixPfPf, @function
_Z30__device_stub__Z10initMatrixPfPf:
.LFB2086:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10initMatrixPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z30__device_stub__Z10initMatrixPfPf, .-_Z30__device_stub__Z10initMatrixPfPf
.globl _Z10initMatrixPf
.type _Z10initMatrixPf, @function
_Z10initMatrixPf:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10initMatrixPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z10initMatrixPf, .-_Z10initMatrixPf
.globl _Z28__device_stub__Z6transpPfS_iPfS_i
.type _Z28__device_stub__Z6transpPfS_iPfS_i, @function
_Z28__device_stub__Z6transpPfS_iPfS_i:
.LFB2088:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L37
.L33:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6transpPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L33
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z28__device_stub__Z6transpPfS_iPfS_i, .-_Z28__device_stub__Z6transpPfS_iPfS_i
.globl _Z6transpPfS_i
.type _Z6transpPfS_i, @function
_Z6transpPfS_i:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z6transpPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z6transpPfS_i, .-_Z6transpPfS_i
.section .rodata.str1.1
.LC2:
.string "Size matrix(%dx%d): %d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "gridDim.x = %d gridDim.y = %d\n"
.align 8
.LC4:
.string "blockDim.x = %d blockDim.y = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jg .L49
movl $16, 12(%rsp)
movl $4, %ebp
movl $1, %ebx
.L42:
movslq 12(%rsp), %r12
leaq 0(,%r12,4), %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl $4, %esi
movq %r12, %rdi
call calloc@PLT
movq %rax, %r13
movl $4, %esi
movq %r12, %rdi
call calloc@PLT
movq %rax, %r12
movl %ebp, %eax
cltd
idivl %ebx
movl %eax, %r15d
movl $1, 40(%rsp)
movl $1, 52(%rsp)
movl 12(%rsp), %r8d
movl %ebp, %ecx
movl %ebp, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r15d, %ecx
movl %r15d, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %ecx
movl %ebx, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r15d, 32(%rsp)
movl %r15d, 36(%rsp)
movl %ebx, 44(%rsp)
movl %ebx, 48(%rsp)
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L43:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %r14, %rdx
movq 16(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl %ebp, %esi
movq %r13, %rdi
call _Z6OutputPfi
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L51
.L44:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %r14, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl %ebp, %esi
movq %r12, %rdi
call _Z6OutputPfi
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L52
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
movl %edi, %ebx
movq %rsi, %r12
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebp
movl %eax, %edx
imull %eax, %edx
movl %edx, 12(%rsp)
cmpl $2, %ebx
jle .L47
movq 16(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebx
jmp .L42
.L47:
movl $1, %ebx
jmp .L42
.L50:
movq 16(%rsp), %rdi
call _Z30__device_stub__Z10initMatrixPfPf
jmp .L43
.L51:
movl %ebp, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z28__device_stub__Z6transpPfS_iPfS_i
jmp .L44
.L52:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z6transpPfS_i"
.LC6:
.string "_Z10initMatrixPf"
.LC7:
.string "_Z13initMatrix_1DPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z6transpPfS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z10initMatrixPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z13initMatrix_1DPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <stdio.h>
void printMatrix(float *matrix, int rows, int columns)
{
for (int i = 0; i < rows; i++) {
for (int j = 0; j < columns; j++)
printf("%g\t", matrix[i * columns + j]);
printf("\n");
}
printf("\n");
}
void Output(float* a, int N)
{
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
fprintf(stdout, "%g\t", a[j + i * N]);
}
fprintf(stdout, "\n");
}
fprintf(stdout, "\n");
}
__global__ void initMatrix_1D(float *matrix)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
matrix[i] = i;
}
__global__ void initMatrix(float *matrix)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
int I = gridDim.x * blockDim.x;
matrix[i + j * I] = (float) (i + j * I);
}
__global__ void transp(float *matrix, float *matrix_t, int N)
{
int x = threadIdx.x + blockDim.x * blockIdx.x;
int y = threadIdx.y + blockDim.y * blockIdx.y;
matrix_t[y * N + x] = matrix[x * N + y];
}
int main(int argc, char *argv[])
{
int N = (argc > 1) ? atoi(argv[1]) : 4;
int size_matrix = N * N;
int block_x = (argc > 2) ? atoi(argv[2]) : 1;
int block_y = block_x;
float *dmatrix1, *hmatrix1;
float *dmatrix2, *hmatrix2;
cudaMalloc((void**) &dmatrix1, size_matrix * sizeof(float));
cudaMalloc((void**) &dmatrix2, size_matrix * sizeof(float));
hmatrix1 = (float*) calloc(size_matrix, sizeof(float));
hmatrix2 = (float*) calloc(size_matrix, sizeof(float));
dim3 dimGrid = dim3(N / block_x, N / block_y, 1);
dim3 dimBlock = dim3(block_x, block_y, 1);
printf("Size matrix(%dx%d): %d\n", N, N, N * N);
printf("gridDim.x = %d gridDim.y = %d\n", dimGrid.x, dimGrid.y);
printf("blockDim.x = %d blockDim.y = %d\n", dimBlock.x, dimBlock.y);
initMatrix<<<dimGrid, dimBlock>>>(dmatrix1);
cudaDeviceSynchronize();
cudaMemcpy(hmatrix1, dmatrix1, size_matrix * sizeof(float), cudaMemcpyDeviceToHost);
Output(hmatrix1, N);
transp<<<dimGrid, dimBlock>>>(dmatrix1, dmatrix2, N);
cudaDeviceSynchronize();
cudaMemcpy(hmatrix2, dmatrix2, size_matrix * sizeof(float), cudaMemcpyDeviceToHost);
Output(hmatrix2, N);
#if 0
float *test_matrix = (float*) calloc(size_matrix, sizeof(float));
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
test_matrix[j * N + i] = hmatrix1[i * N + j];
}
}
Output(test_matrix, N);
free(test_matrix);
#endif
cudaFree(dmatrix1);
cudaFree(dmatrix2);
free(hmatrix1);
free(hmatrix2);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
void printMatrix(float *matrix, int rows, int columns)
{
for (int i = 0; i < rows; i++) {
for (int j = 0; j < columns; j++)
printf("%g\t", matrix[i * columns + j]);
printf("\n");
}
printf("\n");
}
void Output(float* a, int N)
{
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
fprintf(stdout, "%g\t", a[j + i * N]);
}
fprintf(stdout, "\n");
}
fprintf(stdout, "\n");
}
__global__ void initMatrix_1D(float *matrix)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
matrix[i] = i;
}
__global__ void initMatrix(float *matrix)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
int I = gridDim.x * blockDim.x;
matrix[i + j * I] = (float) (i + j * I);
}
__global__ void transp(float *matrix, float *matrix_t, int N)
{
int x = threadIdx.x + blockDim.x * blockIdx.x;
int y = threadIdx.y + blockDim.y * blockIdx.y;
matrix_t[y * N + x] = matrix[x * N + y];
}
int main(int argc, char *argv[])
{
int N = (argc > 1) ? atoi(argv[1]) : 4;
int size_matrix = N * N;
int block_x = (argc > 2) ? atoi(argv[2]) : 1;
int block_y = block_x;
float *dmatrix1, *hmatrix1;
float *dmatrix2, *hmatrix2;
hipMalloc((void**) &dmatrix1, size_matrix * sizeof(float));
hipMalloc((void**) &dmatrix2, size_matrix * sizeof(float));
hmatrix1 = (float*) calloc(size_matrix, sizeof(float));
hmatrix2 = (float*) calloc(size_matrix, sizeof(float));
dim3 dimGrid = dim3(N / block_x, N / block_y, 1);
dim3 dimBlock = dim3(block_x, block_y, 1);
printf("Size matrix(%dx%d): %d\n", N, N, N * N);
printf("gridDim.x = %d gridDim.y = %d\n", dimGrid.x, dimGrid.y);
printf("blockDim.x = %d blockDim.y = %d\n", dimBlock.x, dimBlock.y);
initMatrix<<<dimGrid, dimBlock>>>(dmatrix1);
hipDeviceSynchronize();
hipMemcpy(hmatrix1, dmatrix1, size_matrix * sizeof(float), hipMemcpyDeviceToHost);
Output(hmatrix1, N);
transp<<<dimGrid, dimBlock>>>(dmatrix1, dmatrix2, N);
hipDeviceSynchronize();
hipMemcpy(hmatrix2, dmatrix2, size_matrix * sizeof(float), hipMemcpyDeviceToHost);
Output(hmatrix2, N);
#if 0
float *test_matrix = (float*) calloc(size_matrix, sizeof(float));
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
test_matrix[j * N + i] = hmatrix1[i * N + j];
}
}
Output(test_matrix, N);
free(test_matrix);
#endif
hipFree(dmatrix1);
hipFree(dmatrix2);
free(hmatrix1);
free(hmatrix2);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
void printMatrix(float *matrix, int rows, int columns)
{
for (int i = 0; i < rows; i++) {
for (int j = 0; j < columns; j++)
printf("%g\t", matrix[i * columns + j]);
printf("\n");
}
printf("\n");
}
void Output(float* a, int N)
{
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
fprintf(stdout, "%g\t", a[j + i * N]);
}
fprintf(stdout, "\n");
}
fprintf(stdout, "\n");
}
__global__ void initMatrix_1D(float *matrix)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
matrix[i] = i;
}
__global__ void initMatrix(float *matrix)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
int I = gridDim.x * blockDim.x;
matrix[i + j * I] = (float) (i + j * I);
}
__global__ void transp(float *matrix, float *matrix_t, int N)
{
int x = threadIdx.x + blockDim.x * blockIdx.x;
int y = threadIdx.y + blockDim.y * blockIdx.y;
matrix_t[y * N + x] = matrix[x * N + y];
}
int main(int argc, char *argv[])
{
int N = (argc > 1) ? atoi(argv[1]) : 4;
int size_matrix = N * N;
int block_x = (argc > 2) ? atoi(argv[2]) : 1;
int block_y = block_x;
float *dmatrix1, *hmatrix1;
float *dmatrix2, *hmatrix2;
hipMalloc((void**) &dmatrix1, size_matrix * sizeof(float));
hipMalloc((void**) &dmatrix2, size_matrix * sizeof(float));
hmatrix1 = (float*) calloc(size_matrix, sizeof(float));
hmatrix2 = (float*) calloc(size_matrix, sizeof(float));
dim3 dimGrid = dim3(N / block_x, N / block_y, 1);
dim3 dimBlock = dim3(block_x, block_y, 1);
printf("Size matrix(%dx%d): %d\n", N, N, N * N);
printf("gridDim.x = %d gridDim.y = %d\n", dimGrid.x, dimGrid.y);
printf("blockDim.x = %d blockDim.y = %d\n", dimBlock.x, dimBlock.y);
initMatrix<<<dimGrid, dimBlock>>>(dmatrix1);
hipDeviceSynchronize();
hipMemcpy(hmatrix1, dmatrix1, size_matrix * sizeof(float), hipMemcpyDeviceToHost);
Output(hmatrix1, N);
transp<<<dimGrid, dimBlock>>>(dmatrix1, dmatrix2, N);
hipDeviceSynchronize();
hipMemcpy(hmatrix2, dmatrix2, size_matrix * sizeof(float), hipMemcpyDeviceToHost);
Output(hmatrix2, N);
#if 0
float *test_matrix = (float*) calloc(size_matrix, sizeof(float));
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
test_matrix[j * N + i] = hmatrix1[i * N + j];
}
}
Output(test_matrix, N);
free(test_matrix);
#endif
hipFree(dmatrix1);
hipFree(dmatrix2);
free(hmatrix1);
free(hmatrix2);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13initMatrix_1DPf
.globl _Z13initMatrix_1DPf
.p2align 8
.type _Z13initMatrix_1DPf,@function
_Z13initMatrix_1DPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
v_cvt_f32_i32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13initMatrix_1DPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13initMatrix_1DPf, .Lfunc_end0-_Z13initMatrix_1DPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10initMatrixPf
.globl _Z10initMatrixPf
.p2align 8
.type _Z10initMatrixPf,@function
_Z10initMatrixPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b32 s3, s[0:1], 0x8
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v2, s3, s[14:15]
v_mad_u64_u32 v[1:2], null, v3, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_cvt_f32_i32_e32 v4, v1
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10initMatrixPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10initMatrixPf, .Lfunc_end1-_Z10initMatrixPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z6transpPfS_i
.globl _Z6transpPfS_i
.p2align 8
.type _Z6transpPfS_i,@function
_Z6transpPfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v2, s4, v[3:4]
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v4, v[0:1], off
v_mad_u64_u32 v[0:1], null, v3, s4, v[2:3]
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6transpPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z6transpPfS_i, .Lfunc_end2-_Z6transpPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13initMatrix_1DPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13initMatrix_1DPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10initMatrixPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10initMatrixPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6transpPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6transpPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
void printMatrix(float *matrix, int rows, int columns)
{
for (int i = 0; i < rows; i++) {
for (int j = 0; j < columns; j++)
printf("%g\t", matrix[i * columns + j]);
printf("\n");
}
printf("\n");
}
void Output(float* a, int N)
{
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
fprintf(stdout, "%g\t", a[j + i * N]);
}
fprintf(stdout, "\n");
}
fprintf(stdout, "\n");
}
__global__ void initMatrix_1D(float *matrix)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
matrix[i] = i;
}
__global__ void initMatrix(float *matrix)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
int I = gridDim.x * blockDim.x;
matrix[i + j * I] = (float) (i + j * I);
}
__global__ void transp(float *matrix, float *matrix_t, int N)
{
int x = threadIdx.x + blockDim.x * blockIdx.x;
int y = threadIdx.y + blockDim.y * blockIdx.y;
matrix_t[y * N + x] = matrix[x * N + y];
}
int main(int argc, char *argv[])
{
int N = (argc > 1) ? atoi(argv[1]) : 4;
int size_matrix = N * N;
int block_x = (argc > 2) ? atoi(argv[2]) : 1;
int block_y = block_x;
float *dmatrix1, *hmatrix1;
float *dmatrix2, *hmatrix2;
hipMalloc((void**) &dmatrix1, size_matrix * sizeof(float));
hipMalloc((void**) &dmatrix2, size_matrix * sizeof(float));
hmatrix1 = (float*) calloc(size_matrix, sizeof(float));
hmatrix2 = (float*) calloc(size_matrix, sizeof(float));
dim3 dimGrid = dim3(N / block_x, N / block_y, 1);
dim3 dimBlock = dim3(block_x, block_y, 1);
printf("Size matrix(%dx%d): %d\n", N, N, N * N);
printf("gridDim.x = %d gridDim.y = %d\n", dimGrid.x, dimGrid.y);
printf("blockDim.x = %d blockDim.y = %d\n", dimBlock.x, dimBlock.y);
initMatrix<<<dimGrid, dimBlock>>>(dmatrix1);
hipDeviceSynchronize();
hipMemcpy(hmatrix1, dmatrix1, size_matrix * sizeof(float), hipMemcpyDeviceToHost);
Output(hmatrix1, N);
transp<<<dimGrid, dimBlock>>>(dmatrix1, dmatrix2, N);
hipDeviceSynchronize();
hipMemcpy(hmatrix2, dmatrix2, size_matrix * sizeof(float), hipMemcpyDeviceToHost);
Output(hmatrix2, N);
#if 0
float *test_matrix = (float*) calloc(size_matrix, sizeof(float));
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
test_matrix[j * N + i] = hmatrix1[i * N + j];
}
}
Output(test_matrix, N);
free(test_matrix);
#endif
hipFree(dmatrix1);
hipFree(dmatrix2);
free(hmatrix1);
free(hmatrix2);
return 0;
} | .text
.file "main.hip"
.globl _Z11printMatrixPfii # -- Begin function _Z11printMatrixPfii
.p2align 4, 0x90
.type _Z11printMatrixPfii,@function
_Z11printMatrixPfii: # @_Z11printMatrixPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, 8(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB0_6
# %bb.1: # %.preheader.lr.ph
movl %edx, %ebx
movl %esi, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %edx, %r12d
xorl %r13d, %r13d
xorl %ebp, %ebp
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_5: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %rbp
addl %ebx, %r13d
cmpq 16(%rsp), %rbp # 8-byte Folded Reload
je .LBB0_6
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
testl %ebx, %ebx
jle .LBB0_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB0_2 Depth=1
movl %r13d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r12
jne .LBB0_4
jmp .LBB0_5
.LBB0_6: # %._crit_edge14
movl $10, %edi
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp putchar@PLT # TAILCALL
.Lfunc_end0:
.size _Z11printMatrixPfii, .Lfunc_end0-_Z11printMatrixPfii
.cfi_endproc
# -- End function
.globl _Z6OutputPfi # -- Begin function _Z6OutputPfi
.p2align 4, 0x90
.type _Z6OutputPfi,@function
_Z6OutputPfi: # @_Z6OutputPfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, (%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB1_5
# %bb.1: # %.preheader.lr.ph
movl %esi, %ebx
movl %esi, %r15d
xorl %r12d, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
movl %r12d, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_3: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movq stdout(%rip), %rdi
movss (%rbp,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %esi
movb $1, %al
callq fprintf
incq %r14
cmpq %r14, %r15
jne .LBB1_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movq stdout(%rip), %rsi
movl $10, %edi
callq fputc@PLT
incq %r13
addl %ebx, %r12d
cmpq %r15, %r13
jne .LBB1_2
.LBB1_5: # %._crit_edge14
movq stdout(%rip), %rsi
movl $10, %edi
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp fputc@PLT # TAILCALL
.Lfunc_end1:
.size _Z6OutputPfi, .Lfunc_end1-_Z6OutputPfi
.cfi_endproc
# -- End function
.globl _Z28__device_stub__initMatrix_1DPf # -- Begin function _Z28__device_stub__initMatrix_1DPf
.p2align 4, 0x90
.type _Z28__device_stub__initMatrix_1DPf,@function
_Z28__device_stub__initMatrix_1DPf: # @_Z28__device_stub__initMatrix_1DPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z13initMatrix_1DPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size _Z28__device_stub__initMatrix_1DPf, .Lfunc_end2-_Z28__device_stub__initMatrix_1DPf
.cfi_endproc
# -- End function
.globl _Z25__device_stub__initMatrixPf # -- Begin function _Z25__device_stub__initMatrixPf
.p2align 4, 0x90
.type _Z25__device_stub__initMatrixPf,@function
_Z25__device_stub__initMatrixPf: # @_Z25__device_stub__initMatrixPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10initMatrixPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end3:
.size _Z25__device_stub__initMatrixPf, .Lfunc_end3-_Z25__device_stub__initMatrixPf
.cfi_endproc
# -- End function
.globl _Z21__device_stub__transpPfS_i # -- Begin function _Z21__device_stub__transpPfS_i
.p2align 4, 0x90
.type _Z21__device_stub__transpPfS_i,@function
_Z21__device_stub__transpPfS_i: # @_Z21__device_stub__transpPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6transpPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end4:
.size _Z21__device_stub__transpPfS_i, .Lfunc_end4-_Z21__device_stub__transpPfS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movl %edi, %ebp
movl $4, %ebx
cmpl $2, %edi
jl .LBB5_2
# %bb.1:
movq 8(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
.LBB5_2:
movl %ebx, %r15d
imull %ebx, %r15d
movl $1, %r12d
cmpl $3, %ebp
jl .LBB5_4
# %bb.3:
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
.LBB5_4:
movl %r15d, (%rsp) # 4-byte Spill
movl %r15d, %r15d
leaq (,%r15,4), %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %r14, 104(%rsp) # 8-byte Spill
movq %r14, %rsi
callq hipMalloc
movl $4, %esi
movq %r15, %rdi
callq calloc
movq %rax, %r14
movl $4, %esi
movq %r15, %rdi
callq calloc
movq %rax, 32(%rsp) # 8-byte Spill
movl %ebx, %eax
cltd
idivl %r12d
movl %eax, %ebp
movq %rbp, %r15
shlq $32, %r15
orq %rbp, %r15
movl %r12d, %eax
movq %rax, %r13
shlq $32, %r13
orq %rax, %r13
movl $.L.str.2, %edi
movl %ebx, %esi
movl %ebx, %edx
movl (%rsp), %ecx # 4-byte Reload
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movl %ebp, %esi
movl %ebp, %edx
xorl %eax, %eax
callq printf
movl $.L.str.4, %edi
movl %r12d, %esi
movl %r12d, %edx
xorl %eax, %eax
callq printf
movq %r15, 152(%rsp) # 8-byte Spill
movq %r15, %rdi
movl $1, %esi
movq %r13, 144(%rsp) # 8-byte Spill
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_6
# %bb.5:
movq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 88(%rsp), %rax
movq %rax, 16(%rsp)
leaq 112(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z10initMatrixPf, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_6:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movq %r14, %rdi
movq 104(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movl %ebx, %r12d
testl %ebx, %ebx
movq %r14, (%rsp) # 8-byte Spill
jle .LBB5_11
# %bb.7: # %.preheader.lr.ph.i
xorl %r13d, %r13d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB5_8: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB5_9 Depth 2
movl %r13d, %eax
leaq (%r14,%rax,4), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB5_9: # Parent Loop BB5_8 Depth=1
# => This Inner Loop Header: Depth=2
movq stdout(%rip), %rdi
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %esi
movb $1, %al
callq fprintf
incq %r15
cmpq %r15, %r12
jne .LBB5_9
# %bb.10: # %._crit_edge.i
# in Loop: Header=BB5_8 Depth=1
movq stdout(%rip), %rsi
movl $10, %edi
callq fputc@PLT
incq %rbp
addl %ebx, %r13d
cmpq %r12, %rbp
movq (%rsp), %r14 # 8-byte Reload
jne .LBB5_8
.LBB5_11: # %_Z6OutputPfi.exit
movq stdout(%rip), %rsi
movl $10, %edi
callq fputc@PLT
movq 152(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movq 144(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_13
# %bb.12:
movq 8(%rsp), %rax
movq 40(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movl %ebx, 84(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 84(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 160(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6transpPfS_i, %edi
pushq 160(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_13:
callq hipDeviceSynchronize
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi # 8-byte Reload
movq 104(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
testl %ebx, %ebx
jle .LBB5_18
# %bb.14: # %.preheader.lr.ph.i53
xorl %r13d, %r13d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB5_15: # %.preheader.i55
# =>This Loop Header: Depth=1
# Child Loop BB5_16 Depth 2
movl %r13d, %eax
movq 32(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB5_16: # Parent Loop BB5_15 Depth=1
# => This Inner Loop Header: Depth=2
movq stdout(%rip), %rdi
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %esi
movb $1, %al
callq fprintf
incq %r15
cmpq %r15, %r12
jne .LBB5_16
# %bb.17: # %._crit_edge.i61
# in Loop: Header=BB5_15 Depth=1
movq stdout(%rip), %rsi
movl $10, %edi
callq fputc@PLT
incq %rbp
addl %ebx, %r13d
cmpq %r12, %rbp
jne .LBB5_15
.LBB5_18: # %_Z6OutputPfi.exit65
movq stdout(%rip), %rsi
movl $10, %edi
callq fputc@PLT
movq 8(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi # 8-byte Reload
callq free
movq 32(%rsp), %rdi # 8-byte Reload
callq free
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13initMatrix_1DPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10initMatrixPf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6transpPfS_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%g\t"
.size .L.str, 4
.type _Z13initMatrix_1DPf,@object # @_Z13initMatrix_1DPf
.section .rodata,"a",@progbits
.globl _Z13initMatrix_1DPf
.p2align 3, 0x0
_Z13initMatrix_1DPf:
.quad _Z28__device_stub__initMatrix_1DPf
.size _Z13initMatrix_1DPf, 8
.type _Z10initMatrixPf,@object # @_Z10initMatrixPf
.globl _Z10initMatrixPf
.p2align 3, 0x0
_Z10initMatrixPf:
.quad _Z25__device_stub__initMatrixPf
.size _Z10initMatrixPf, 8
.type _Z6transpPfS_i,@object # @_Z6transpPfS_i
.globl _Z6transpPfS_i
.p2align 3, 0x0
_Z6transpPfS_i:
.quad _Z21__device_stub__transpPfS_i
.size _Z6transpPfS_i, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Size matrix(%dx%d): %d\n"
.size .L.str.2, 24
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "gridDim.x = %d gridDim.y = %d\n"
.size .L.str.3, 31
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "blockDim.x = %d blockDim.y = %d\n"
.size .L.str.4, 33
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13initMatrix_1DPf"
.size .L__unnamed_1, 20
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10initMatrixPf"
.size .L__unnamed_2, 17
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z6transpPfS_i"
.size .L__unnamed_3, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__initMatrix_1DPf
.addrsig_sym _Z25__device_stub__initMatrixPf
.addrsig_sym _Z21__device_stub__transpPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13initMatrix_1DPf
.addrsig_sym _Z10initMatrixPf
.addrsig_sym _Z6transpPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6transpPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002200 */
/*0060*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002600 */
/*0070*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fc400078e0200 */
/*0080*/ IMAD R5, R2, c[0x0][0x4], R5 ; /* 0x0000010002057a24 */
/* 0x002fc800078e0205 */
/*0090*/ IMAD R2, R0, c[0x0][0x170], R5 ; /* 0x00005c0000027a24 */
/* 0x000fc800078e0205 */
/*00a0*/ IMAD.WIDE R2, R2, R4, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0204 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD R5, R5, c[0x0][0x170], R0 ; /* 0x00005c0005057a24 */
/* 0x000fc800078e0200 */
/*00d0*/ IMAD.WIDE R4, R5, R4, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e0204 */
/*00e0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10initMatrixPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e280000002600 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000ea20000002100 */
/*0060*/ IMAD R0, R7, c[0x0][0x4], R0 ; /* 0x0000010007007a24 */
/* 0x001fc800078e0200 */
/*0070*/ IMAD R0, R0, c[0x0][0xc], R5 ; /* 0x0000030000007a24 */
/* 0x002fc800078e0205 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x004fe200078e0203 */
/*0090*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fc600000001ff */
/*00a0*/ I2F R5, R0 ; /* 0x0000000000057306 */
/* 0x000e2e0000201400 */
/*00b0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*00c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z13initMatrix_1DPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0040*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fe200078e0200 */
/*0050*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fc600000001ff */
/*0060*/ I2F R5, R0 ; /* 0x0000000000057306 */
/* 0x000e2e0000201400 */
/*0070*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0080*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13initMatrix_1DPf
.globl _Z13initMatrix_1DPf
.p2align 8
.type _Z13initMatrix_1DPf,@function
_Z13initMatrix_1DPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
v_cvt_f32_i32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13initMatrix_1DPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13initMatrix_1DPf, .Lfunc_end0-_Z13initMatrix_1DPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10initMatrixPf
.globl _Z10initMatrixPf
.p2align 8
.type _Z10initMatrixPf,@function
_Z10initMatrixPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b32 s3, s[0:1], 0x8
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v2, s3, s[14:15]
v_mad_u64_u32 v[1:2], null, v3, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_cvt_f32_i32_e32 v4, v1
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10initMatrixPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10initMatrixPf, .Lfunc_end1-_Z10initMatrixPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z6transpPfS_i
.globl _Z6transpPfS_i
.p2align 8
.type _Z6transpPfS_i,@function
_Z6transpPfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v2, s4, v[3:4]
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v4, v[0:1], off
v_mad_u64_u32 v[0:1], null, v3, s4, v[2:3]
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6transpPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z6transpPfS_i, .Lfunc_end2-_Z6transpPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13initMatrix_1DPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13initMatrix_1DPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10initMatrixPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10initMatrixPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6transpPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6transpPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0008bb51_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%g\t"
.LC1:
.string "\n"
.text
.globl _Z11printMatrixPfii
.type _Z11printMatrixPfii, @function
_Z11printMatrixPfii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
movl %esi, 12(%rsp)
testl %esi, %esi
jle .L4
movl %edx, %r15d
movl $0, %r14d
movl $0, %r13d
movslq %edx, %rax
movq %rax, 24(%rsp)
leaq .LC0(%rip), %r12
jmp .L5
.L7:
movslq %r14d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 24(%rsp), %rdx
addq %rdx, %rax
leaq (%rcx,%rax,4), %rbp
.L6:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L6
.L8:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addl %r15d, %r14d
cmpl %r13d, 12(%rsp)
je .L4
.L5:
testl %r15d, %r15d
jg .L7
jmp .L8
.L4:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11printMatrixPfii, .-_Z11printMatrixPfii
.globl _Z6OutputPfi
.type _Z6OutputPfi, @function
_Z6OutputPfi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %esi, 12(%rsp)
testl %esi, %esi
jle .L12
movslq %esi, %r14
leaq 0(,%r14,4), %r15
leaq (%rdi,%r15), %rbp
negq %r14
salq $2, %r14
movl $0, %r13d
leaq .LC0(%rip), %r12
.L13:
leaq 0(%rbp,%r14), %rbx
.L14:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L14
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1, %r13d
addq %r15, %rbp
cmpl %r13d, 12(%rsp)
jne .L13
.L12:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z6OutputPfi, .-_Z6OutputPfi
.globl _Z33__device_stub__Z13initMatrix_1DPfPf
.type _Z33__device_stub__Z13initMatrix_1DPfPf, @function
_Z33__device_stub__Z13initMatrix_1DPfPf:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13initMatrix_1DPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z33__device_stub__Z13initMatrix_1DPfPf, .-_Z33__device_stub__Z13initMatrix_1DPfPf
.globl _Z13initMatrix_1DPf
.type _Z13initMatrix_1DPf, @function
_Z13initMatrix_1DPf:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z13initMatrix_1DPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z13initMatrix_1DPf, .-_Z13initMatrix_1DPf
.globl _Z30__device_stub__Z10initMatrixPfPf
.type _Z30__device_stub__Z10initMatrixPfPf, @function
_Z30__device_stub__Z10initMatrixPfPf:
.LFB2086:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10initMatrixPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z30__device_stub__Z10initMatrixPfPf, .-_Z30__device_stub__Z10initMatrixPfPf
.globl _Z10initMatrixPf
.type _Z10initMatrixPf, @function
_Z10initMatrixPf:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10initMatrixPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z10initMatrixPf, .-_Z10initMatrixPf
.globl _Z28__device_stub__Z6transpPfS_iPfS_i
.type _Z28__device_stub__Z6transpPfS_iPfS_i, @function
_Z28__device_stub__Z6transpPfS_iPfS_i:
.LFB2088:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L37
.L33:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6transpPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L33
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z28__device_stub__Z6transpPfS_iPfS_i, .-_Z28__device_stub__Z6transpPfS_iPfS_i
.globl _Z6transpPfS_i
.type _Z6transpPfS_i, @function
_Z6transpPfS_i:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z6transpPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z6transpPfS_i, .-_Z6transpPfS_i
.section .rodata.str1.1
.LC2:
.string "Size matrix(%dx%d): %d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "gridDim.x = %d gridDim.y = %d\n"
.align 8
.LC4:
.string "blockDim.x = %d blockDim.y = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jg .L49
movl $16, 12(%rsp)
movl $4, %ebp
movl $1, %ebx
.L42:
movslq 12(%rsp), %r12
leaq 0(,%r12,4), %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl $4, %esi
movq %r12, %rdi
call calloc@PLT
movq %rax, %r13
movl $4, %esi
movq %r12, %rdi
call calloc@PLT
movq %rax, %r12
movl %ebp, %eax
cltd
idivl %ebx
movl %eax, %r15d
movl $1, 40(%rsp)
movl $1, 52(%rsp)
movl 12(%rsp), %r8d
movl %ebp, %ecx
movl %ebp, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r15d, %ecx
movl %r15d, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %ecx
movl %ebx, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r15d, 32(%rsp)
movl %r15d, 36(%rsp)
movl %ebx, 44(%rsp)
movl %ebx, 48(%rsp)
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L43:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %r14, %rdx
movq 16(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl %ebp, %esi
movq %r13, %rdi
call _Z6OutputPfi
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L51
.L44:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %r14, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl %ebp, %esi
movq %r12, %rdi
call _Z6OutputPfi
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L52
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
movl %edi, %ebx
movq %rsi, %r12
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebp
movl %eax, %edx
imull %eax, %edx
movl %edx, 12(%rsp)
cmpl $2, %ebx
jle .L47
movq 16(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebx
jmp .L42
.L47:
movl $1, %ebx
jmp .L42
.L50:
movq 16(%rsp), %rdi
call _Z30__device_stub__Z10initMatrixPfPf
jmp .L43
.L51:
movl %ebp, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z28__device_stub__Z6transpPfS_iPfS_i
jmp .L44
.L52:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z6transpPfS_i"
.LC6:
.string "_Z10initMatrixPf"
.LC7:
.string "_Z13initMatrix_1DPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z6transpPfS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z10initMatrixPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z13initMatrix_1DPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z11printMatrixPfii # -- Begin function _Z11printMatrixPfii
.p2align 4, 0x90
.type _Z11printMatrixPfii,@function
_Z11printMatrixPfii: # @_Z11printMatrixPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, 8(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB0_6
# %bb.1: # %.preheader.lr.ph
movl %edx, %ebx
movl %esi, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %edx, %r12d
xorl %r13d, %r13d
xorl %ebp, %ebp
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_5: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %rbp
addl %ebx, %r13d
cmpq 16(%rsp), %rbp # 8-byte Folded Reload
je .LBB0_6
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
testl %ebx, %ebx
jle .LBB0_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB0_2 Depth=1
movl %r13d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r12
jne .LBB0_4
jmp .LBB0_5
.LBB0_6: # %._crit_edge14
movl $10, %edi
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp putchar@PLT # TAILCALL
.Lfunc_end0:
.size _Z11printMatrixPfii, .Lfunc_end0-_Z11printMatrixPfii
.cfi_endproc
# -- End function
.globl _Z6OutputPfi # -- Begin function _Z6OutputPfi
.p2align 4, 0x90
.type _Z6OutputPfi,@function
_Z6OutputPfi: # @_Z6OutputPfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, (%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB1_5
# %bb.1: # %.preheader.lr.ph
movl %esi, %ebx
movl %esi, %r15d
xorl %r12d, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
movl %r12d, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_3: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movq stdout(%rip), %rdi
movss (%rbp,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %esi
movb $1, %al
callq fprintf
incq %r14
cmpq %r14, %r15
jne .LBB1_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movq stdout(%rip), %rsi
movl $10, %edi
callq fputc@PLT
incq %r13
addl %ebx, %r12d
cmpq %r15, %r13
jne .LBB1_2
.LBB1_5: # %._crit_edge14
movq stdout(%rip), %rsi
movl $10, %edi
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp fputc@PLT # TAILCALL
.Lfunc_end1:
.size _Z6OutputPfi, .Lfunc_end1-_Z6OutputPfi
.cfi_endproc
# -- End function
.globl _Z28__device_stub__initMatrix_1DPf # -- Begin function _Z28__device_stub__initMatrix_1DPf
.p2align 4, 0x90
.type _Z28__device_stub__initMatrix_1DPf,@function
_Z28__device_stub__initMatrix_1DPf: # @_Z28__device_stub__initMatrix_1DPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z13initMatrix_1DPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size _Z28__device_stub__initMatrix_1DPf, .Lfunc_end2-_Z28__device_stub__initMatrix_1DPf
.cfi_endproc
# -- End function
.globl _Z25__device_stub__initMatrixPf # -- Begin function _Z25__device_stub__initMatrixPf
.p2align 4, 0x90
.type _Z25__device_stub__initMatrixPf,@function
_Z25__device_stub__initMatrixPf: # @_Z25__device_stub__initMatrixPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10initMatrixPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end3:
.size _Z25__device_stub__initMatrixPf, .Lfunc_end3-_Z25__device_stub__initMatrixPf
.cfi_endproc
# -- End function
.globl _Z21__device_stub__transpPfS_i # -- Begin function _Z21__device_stub__transpPfS_i
.p2align 4, 0x90
.type _Z21__device_stub__transpPfS_i,@function
_Z21__device_stub__transpPfS_i: # @_Z21__device_stub__transpPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6transpPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end4:
.size _Z21__device_stub__transpPfS_i, .Lfunc_end4-_Z21__device_stub__transpPfS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movl %edi, %ebp
movl $4, %ebx
cmpl $2, %edi
jl .LBB5_2
# %bb.1:
movq 8(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
.LBB5_2:
movl %ebx, %r15d
imull %ebx, %r15d
movl $1, %r12d
cmpl $3, %ebp
jl .LBB5_4
# %bb.3:
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
.LBB5_4:
movl %r15d, (%rsp) # 4-byte Spill
movl %r15d, %r15d
leaq (,%r15,4), %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %r14, 104(%rsp) # 8-byte Spill
movq %r14, %rsi
callq hipMalloc
movl $4, %esi
movq %r15, %rdi
callq calloc
movq %rax, %r14
movl $4, %esi
movq %r15, %rdi
callq calloc
movq %rax, 32(%rsp) # 8-byte Spill
movl %ebx, %eax
cltd
idivl %r12d
movl %eax, %ebp
movq %rbp, %r15
shlq $32, %r15
orq %rbp, %r15
movl %r12d, %eax
movq %rax, %r13
shlq $32, %r13
orq %rax, %r13
movl $.L.str.2, %edi
movl %ebx, %esi
movl %ebx, %edx
movl (%rsp), %ecx # 4-byte Reload
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movl %ebp, %esi
movl %ebp, %edx
xorl %eax, %eax
callq printf
movl $.L.str.4, %edi
movl %r12d, %esi
movl %r12d, %edx
xorl %eax, %eax
callq printf
movq %r15, 152(%rsp) # 8-byte Spill
movq %r15, %rdi
movl $1, %esi
movq %r13, 144(%rsp) # 8-byte Spill
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_6
# %bb.5:
movq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 88(%rsp), %rax
movq %rax, 16(%rsp)
leaq 112(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z10initMatrixPf, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_6:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movq %r14, %rdi
movq 104(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movl %ebx, %r12d
testl %ebx, %ebx
movq %r14, (%rsp) # 8-byte Spill
jle .LBB5_11
# %bb.7: # %.preheader.lr.ph.i
xorl %r13d, %r13d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB5_8: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB5_9 Depth 2
movl %r13d, %eax
leaq (%r14,%rax,4), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB5_9: # Parent Loop BB5_8 Depth=1
# => This Inner Loop Header: Depth=2
movq stdout(%rip), %rdi
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %esi
movb $1, %al
callq fprintf
incq %r15
cmpq %r15, %r12
jne .LBB5_9
# %bb.10: # %._crit_edge.i
# in Loop: Header=BB5_8 Depth=1
movq stdout(%rip), %rsi
movl $10, %edi
callq fputc@PLT
incq %rbp
addl %ebx, %r13d
cmpq %r12, %rbp
movq (%rsp), %r14 # 8-byte Reload
jne .LBB5_8
.LBB5_11: # %_Z6OutputPfi.exit
movq stdout(%rip), %rsi
movl $10, %edi
callq fputc@PLT
movq 152(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movq 144(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_13
# %bb.12:
movq 8(%rsp), %rax
movq 40(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movl %ebx, 84(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 84(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 160(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6transpPfS_i, %edi
pushq 160(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_13:
callq hipDeviceSynchronize
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi # 8-byte Reload
movq 104(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
testl %ebx, %ebx
jle .LBB5_18
# %bb.14: # %.preheader.lr.ph.i53
xorl %r13d, %r13d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB5_15: # %.preheader.i55
# =>This Loop Header: Depth=1
# Child Loop BB5_16 Depth 2
movl %r13d, %eax
movq 32(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB5_16: # Parent Loop BB5_15 Depth=1
# => This Inner Loop Header: Depth=2
movq stdout(%rip), %rdi
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %esi
movb $1, %al
callq fprintf
incq %r15
cmpq %r15, %r12
jne .LBB5_16
# %bb.17: # %._crit_edge.i61
# in Loop: Header=BB5_15 Depth=1
movq stdout(%rip), %rsi
movl $10, %edi
callq fputc@PLT
incq %rbp
addl %ebx, %r13d
cmpq %r12, %rbp
jne .LBB5_15
.LBB5_18: # %_Z6OutputPfi.exit65
movq stdout(%rip), %rsi
movl $10, %edi
callq fputc@PLT
movq 8(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi # 8-byte Reload
callq free
movq 32(%rsp), %rdi # 8-byte Reload
callq free
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13initMatrix_1DPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10initMatrixPf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6transpPfS_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%g\t"
.size .L.str, 4
.type _Z13initMatrix_1DPf,@object # @_Z13initMatrix_1DPf
.section .rodata,"a",@progbits
.globl _Z13initMatrix_1DPf
.p2align 3, 0x0
_Z13initMatrix_1DPf:
.quad _Z28__device_stub__initMatrix_1DPf
.size _Z13initMatrix_1DPf, 8
.type _Z10initMatrixPf,@object # @_Z10initMatrixPf
.globl _Z10initMatrixPf
.p2align 3, 0x0
_Z10initMatrixPf:
.quad _Z25__device_stub__initMatrixPf
.size _Z10initMatrixPf, 8
.type _Z6transpPfS_i,@object # @_Z6transpPfS_i
.globl _Z6transpPfS_i
.p2align 3, 0x0
_Z6transpPfS_i:
.quad _Z21__device_stub__transpPfS_i
.size _Z6transpPfS_i, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Size matrix(%dx%d): %d\n"
.size .L.str.2, 24
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "gridDim.x = %d gridDim.y = %d\n"
.size .L.str.3, 31
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "blockDim.x = %d blockDim.y = %d\n"
.size .L.str.4, 33
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13initMatrix_1DPf"
.size .L__unnamed_1, 20
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10initMatrixPf"
.size .L__unnamed_2, 17
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z6transpPfS_i"
.size .L__unnamed_3, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__initMatrix_1DPf
.addrsig_sym _Z25__device_stub__initMatrixPf
.addrsig_sym _Z21__device_stub__transpPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13initMatrix_1DPf
.addrsig_sym _Z10initMatrixPf
.addrsig_sym _Z6transpPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/copy.h>
#include <thrust/scan.h>
#include <thrust/execution_policy.h>
int checkResults(float*res, float* cudaRes,int length)
{
int nDiffs=0;
const float smallVal = .3f; // Keeping this extra high as we have repetitive addition and sequence matters
for(int i=0; i<length; i++)
if(fabs(cudaRes[i]-res[i])>smallVal)
{nDiffs++;
//printf("%f %f\n",cudaRes[i],res[i]);
}
return nDiffs;
}
void initializeArray(FILE* fp,float* arr, int nElements)
{
for( int i=0; i<nElements; i++){
int r=fscanf(fp,"%f",&arr[i]);
if(r == EOF){
rewind(fp);
}
arr[i]-=5; // This is to make the data zero mean. Otherwise we reach large numbers and lose precision
}
}
void inclusiveScan_SEQ(float *in, float *out,int length) {
float sum=0.f;
for (int i =0; i < length; i++) {
sum+=in[i];
out[i]=sum;
}
}
int main(int argc, char* argv[]) {
if(argc!=2){
printf("Usage %s N\n",argv[0]);
return 1;
}
int N = atoi(argv[1]);
FILE *fp = fopen("problem1.inp","r");
int size = N * sizeof(float);
float *in = (float *)malloc(size);
float *out = (float *)malloc(size);
float *cuda_out = (float *)malloc(size);
float time = 0.f;
cudaEvent_t startEvent_inc, stopEvent_inc;
cudaEventCreate(&startEvent_inc);
cudaEventCreate(&stopEvent_inc);
initializeArray(fp,in, N);
thrust::host_vector<float> H(N);
for (int i = 0; i < N; i++)
{
H[i] = in[i];
}
cudaEventRecord(startEvent_inc,0); // starting timing for inclusive
thrust::device_vector<float> D = H;
thrust::inclusive_scan(D.begin(), D.end(), D.begin());
thrust::copy(D.begin(), D.end(), cuda_out);
cudaEventRecord(stopEvent_inc,0); //ending timing for inclusive
cudaEventSynchronize(stopEvent_inc);
cudaEventElapsedTime(&time, startEvent_inc, stopEvent_inc);
inclusiveScan_SEQ(in, out, N);
int nDiffs = checkResults(out, cuda_out,N);
if(nDiffs)printf("Test Failed\n"); // This should never print
printf("%d\n%f\n%f\n",N,cuda_out[N-1],time);
//dynamically delete all
return(0);
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/copy.h>
#include <thrust/scan.h>
#include <thrust/execution_policy.h>
int checkResults(float*res, float* cudaRes,int length)
{
int nDiffs=0;
const float smallVal = .3f; // Keeping this extra high as we have repetitive addition and sequence matters
for(int i=0; i<length; i++)
if(fabs(cudaRes[i]-res[i])>smallVal)
{nDiffs++;
//printf("%f %f\n",cudaRes[i],res[i]);
}
return nDiffs;
}
void initializeArray(FILE* fp,float* arr, int nElements)
{
for( int i=0; i<nElements; i++){
int r=fscanf(fp,"%f",&arr[i]);
if(r == EOF){
rewind(fp);
}
arr[i]-=5; // This is to make the data zero mean. Otherwise we reach large numbers and lose precision
}
}
void inclusiveScan_SEQ(float *in, float *out,int length) {
float sum=0.f;
for (int i =0; i < length; i++) {
sum+=in[i];
out[i]=sum;
}
}
int main(int argc, char* argv[]) {
if(argc!=2){
printf("Usage %s N\n",argv[0]);
return 1;
}
int N = atoi(argv[1]);
FILE *fp = fopen("problem1.inp","r");
int size = N * sizeof(float);
float *in = (float *)malloc(size);
float *out = (float *)malloc(size);
float *cuda_out = (float *)malloc(size);
float time = 0.f;
hipEvent_t startEvent_inc, stopEvent_inc;
hipEventCreate(&startEvent_inc);
hipEventCreate(&stopEvent_inc);
initializeArray(fp,in, N);
thrust::host_vector<float> H(N);
for (int i = 0; i < N; i++)
{
H[i] = in[i];
}
hipEventRecord(startEvent_inc,0); // starting timing for inclusive
thrust::device_vector<float> D = H;
thrust::inclusive_scan(D.begin(), D.end(), D.begin());
thrust::copy(D.begin(), D.end(), cuda_out);
hipEventRecord(stopEvent_inc,0); //ending timing for inclusive
hipEventSynchronize(stopEvent_inc);
hipEventElapsedTime(&time, startEvent_inc, stopEvent_inc);
inclusiveScan_SEQ(in, out, N);
int nDiffs = checkResults(out, cuda_out,N);
if(nDiffs)printf("Test Failed\n"); // This should never print
printf("%d\n%f\n%f\n",N,cuda_out[N-1],time);
//dynamically delete all
return(0);
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void naiveKernel(int N, float *input, float *output){
int global_i = blockIdx.x * blockDim.x + threadIdx.x;
if(global_i < N){
for(int i=0;i<N;++i) output[global_i] += input[i];
output[global_i] /= N;
}
return ;
} | code for sm_80
Function : _Z11naiveKerneliPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ; /* 0x0000580003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x160], PT ; /* 0x00005800ff007a0c */
/* 0x000fe20003f01270 */
/*0070*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0090*/ IMAD.WIDE R2, R3, R6, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fd000078e0206 */
/*00a0*/ @!P0 BRA 0x990 ; /* 0x000008e000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff007624 */
/* 0x000fe400078e00ff */
/*00c0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fc600078e00ff */
/*00d0*/ IADD3 R4, R0.reuse, -0x1, RZ ; /* 0xffffffff00047810 */
/* 0x040fe40007ffe0ff */
/*00e0*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe400078ec0ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fda0003f06070 */
/*0100*/ @!P0 BRA 0x8b0 ; /* 0x000007a000008947 */
/* 0x000fea0003800000 */
/*0110*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000162000c1e1900 */
/*0120*/ IADD3 R8, -R0, c[0x0][0x160], RZ ; /* 0x0000580000087a10 */
/* 0x000fe20007ffe1ff */
/*0130*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe400078e00ff */
/*0140*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0150*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f04270 */
/*0160*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fd800078e00ff */
/*0170*/ @!P0 BRA 0x770 ; /* 0x000005f000008947 */
/* 0x001fea0003800000 */
/*0180*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*0190*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01a0*/ @!P1 BRA 0x540 ; /* 0x0000039000009947 */
/* 0x000fea0003800000 */
/*01b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01c0*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea4000c1e1900 */
/*01d0*/ FADD R9, R10, R9 ; /* 0x000000090a097221 */
/* 0x02cfca0000000000 */
/*01e0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*01f0*/ LDG.E R10, [R4.64+0x4] ; /* 0x00000404040a7981 */
/* 0x000ea4000c1e1900 */
/*0200*/ FADD R11, R9, R10 ; /* 0x0000000a090b7221 */
/* 0x004fca0000000000 */
/*0210*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101904 */
/*0220*/ LDG.E R10, [R4.64+0x8] ; /* 0x00000804040a7981 */
/* 0x000ea4000c1e1900 */
/*0230*/ FADD R13, R11, R10 ; /* 0x0000000a0b0d7221 */
/* 0x004fca0000000000 */
/*0240*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*0250*/ LDG.E R10, [R4.64+0xc] ; /* 0x00000c04040a7981 */
/* 0x000ee4000c1e1900 */
/*0260*/ FADD R15, R13, R10 ; /* 0x0000000a0d0f7221 */
/* 0x008fca0000000000 */
/*0270*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0007e8000c101904 */
/*0280*/ LDG.E R10, [R4.64+0x10] ; /* 0x00001004040a7981 */
/* 0x000e24000c1e1900 */
/*0290*/ FADD R9, R15, R10 ; /* 0x0000000a0f097221 */
/* 0x001fca0000000000 */
/*02a0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*02b0*/ LDG.E R10, [R4.64+0x14] ; /* 0x00001404040a7981 */
/* 0x000e64000c1e1900 */
/*02c0*/ FADD R11, R9, R10 ; /* 0x0000000a090b7221 */
/* 0x002fca0000000000 */
/*02d0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101904 */
/*02e0*/ LDG.E R10, [R4.64+0x18] ; /* 0x00001804040a7981 */
/* 0x000ea4000c1e1900 */
/*02f0*/ FADD R13, R11, R10 ; /* 0x0000000a0b0d7221 */
/* 0x004fca0000000000 */
/*0300*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*0310*/ LDG.E R10, [R4.64+0x1c] ; /* 0x00001c04040a7981 */
/* 0x000ee4000c1e1900 */
/*0320*/ FADD R15, R13, R10 ; /* 0x0000000a0d0f7221 */
/* 0x008fca0000000000 */
/*0330*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0007e8000c101904 */
/*0340*/ LDG.E R10, [R4.64+0x20] ; /* 0x00002004040a7981 */
/* 0x000e24000c1e1900 */
/*0350*/ FADD R9, R15, R10 ; /* 0x0000000a0f097221 */
/* 0x001fca0000000000 */
/*0360*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*0370*/ LDG.E R10, [R4.64+0x24] ; /* 0x00002404040a7981 */
/* 0x000e64000c1e1900 */
/*0380*/ FADD R11, R9, R10 ; /* 0x0000000a090b7221 */
/* 0x002fca0000000000 */
/*0390*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101904 */
/*03a0*/ LDG.E R10, [R4.64+0x28] ; /* 0x00002804040a7981 */
/* 0x000ea4000c1e1900 */
/*03b0*/ FADD R13, R11, R10 ; /* 0x0000000a0b0d7221 */
/* 0x004fca0000000000 */
/*03c0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0003e8000c101904 */
/*03d0*/ LDG.E R10, [R4.64+0x2c] ; /* 0x00002c04040a7981 */
/* 0x000ee4000c1e1900 */
/*03e0*/ FADD R15, R13, R10 ; /* 0x0000000a0d0f7221 */
/* 0x008fca0000000000 */
/*03f0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0005e8000c101904 */
/*0400*/ LDG.E R10, [R4.64+0x30] ; /* 0x00003004040a7981 */
/* 0x000ee4000c1e1900 */
/*0410*/ FADD R17, R15, R10 ; /* 0x0000000a0f117221 */
/* 0x008fca0000000000 */
/*0420*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0007e8000c101904 */
/*0430*/ LDG.E R10, [R4.64+0x34] ; /* 0x00003404040a7981 */
/* 0x000e24000c1e1900 */
/*0440*/ FADD R11, R17, R10 ; /* 0x0000000a110b7221 */
/* 0x001fca0000000000 */
/*0450*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0007e8000c101904 */
/*0460*/ LDG.E R10, [R4.64+0x38] ; /* 0x00003804040a7981 */
/* 0x000e64000c1e1900 */
/*0470*/ FADD R13, R11, R10 ; /* 0x0000000a0b0d7221 */
/* 0x002fca0000000000 */
/*0480*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*0490*/ LDG.E R10, [R4.64+0x3c] ; /* 0x00003c04040a7981 */
/* 0x000f22000c1e1900 */
/*04a0*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fe40007ffe0ff */
/*04b0*/ IADD3 R7, R7, 0x10, RZ ; /* 0x0000001007077810 */
/* 0x000fe40007ffe0ff */
/*04c0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe20003f24270 */
/*04d0*/ FADD R9, R13, R10 ; /* 0x0000000a0d097221 */
/* 0x010fe20000000000 */
/*04e0*/ IADD3 R10, P2, R4, 0x40, RZ ; /* 0x00000040040a7810 */
/* 0x000fc80007f5e0ff */
/*04f0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0007e2000c101904 */
/*0500*/ IMAD.X R15, RZ, RZ, R5, P2 ; /* 0x000000ffff0f7224 */
/* 0x004fe400010e0605 */
/*0510*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000a */
/*0520*/ IMAD.MOV.U32 R5, RZ, RZ, R15 ; /* 0x000000ffff057224 */
/* 0x000fe400078e000f */
/*0530*/ @P1 BRA 0x1c0 ; /* 0xfffffc8000001947 */
/* 0x000fea000383ffff */
/*0540*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*0550*/ @!P1 BRA 0x750 ; /* 0x000001f000009947 */
/* 0x000fea0003800000 */
/*0560*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea4000c1e1900 */
/*0570*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x02cfca0000000000 */
/*0580*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*0590*/ LDG.E R10, [R4.64+0x4] ; /* 0x00000404040a7981 */
/* 0x000ea4000c1e1900 */
/*05a0*/ FADD R11, R9, R10 ; /* 0x0000000a090b7221 */
/* 0x004fca0000000000 */
/*05b0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101904 */
/*05c0*/ LDG.E R10, [R4.64+0x8] ; /* 0x00000804040a7981 */
/* 0x000ea4000c1e1900 */
/*05d0*/ FADD R13, R11, R10 ; /* 0x0000000a0b0d7221 */
/* 0x004fca0000000000 */
/*05e0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0003e8000c101904 */
/*05f0*/ LDG.E R10, [R4.64+0xc] ; /* 0x00000c04040a7981 */
/* 0x000ea4000c1e1900 */
/*0600*/ FADD R15, R13, R10 ; /* 0x0000000a0d0f7221 */
/* 0x004fca0000000000 */
/*0610*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0005e8000c101904 */
/*0620*/ LDG.E R10, [R4.64+0x10] ; /* 0x00001004040a7981 */
/* 0x000ee4000c1e1900 */
/*0630*/ FADD R17, R15, R10 ; /* 0x0000000a0f117221 */
/* 0x008fca0000000000 */
/*0640*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0007e8000c101904 */
/*0650*/ LDG.E R10, [R4.64+0x14] ; /* 0x00001404040a7981 */
/* 0x000e24000c1e1900 */
/*0660*/ FADD R11, R17, R10 ; /* 0x0000000a110b7221 */
/* 0x001fca0000000000 */
/*0670*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0007e8000c101904 */
/*0680*/ LDG.E R10, [R4.64+0x18] ; /* 0x00001804040a7981 */
/* 0x000e64000c1e1900 */
/*0690*/ FADD R13, R11, R10 ; /* 0x0000000a0b0d7221 */
/* 0x002fca0000000000 */
/*06a0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*06b0*/ LDG.E R10, [R4.64+0x1c] ; /* 0x00001c04040a7981 */
/* 0x000f22000c1e1900 */
/*06c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*06d0*/ IADD3 R7, R7, 0x8, RZ ; /* 0x0000000807077810 */
/* 0x000fe40007ffe0ff */
/*06e0*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fe20007ffe0ff */
/*06f0*/ FADD R9, R13, R10 ; /* 0x0000000a0d097221 */
/* 0x010fe20000000000 */
/*0700*/ IADD3 R10, P1, R4, 0x20, RZ ; /* 0x00000020040a7810 */
/* 0x000fc80007f3e0ff */
/*0710*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0007e2000c101904 */
/*0720*/ IMAD.X R15, RZ, RZ, R5, P1 ; /* 0x000000ffff0f7224 */
/* 0x004fe200008e0605 */
/*0730*/ MOV R4, R10 ; /* 0x0000000a00047202 */
/* 0x000fc60000000f00 */
/*0740*/ IMAD.MOV.U32 R5, RZ, RZ, R15 ; /* 0x000000ffff057224 */
/* 0x000fe400078e000f */
/*0750*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0000705670 */
/*0760*/ @!P0 BRA 0x8b0 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*0770*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea4000c1e1900 */
/*0780*/ FADD R11, R10, R9 ; /* 0x000000090a0b7221 */
/* 0x02cfca0000000000 */
/*0790*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101904 */
/*07a0*/ LDG.E R10, [R4.64+0x4] ; /* 0x00000404040a7981 */
/* 0x000ea4000c1e1900 */
/*07b0*/ FADD R13, R11, R10 ; /* 0x0000000a0b0d7221 */
/* 0x004fca0000000000 */
/*07c0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0003e8000c101904 */
/*07d0*/ LDG.E R10, [R4.64+0x8] ; /* 0x00000804040a7981 */
/* 0x000ea4000c1e1900 */
/*07e0*/ FADD R15, R13, R10 ; /* 0x0000000a0d0f7221 */
/* 0x004fca0000000000 */
/*07f0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0003e8000c101904 */
/*0800*/ LDG.E R10, [R4.64+0xc] ; /* 0x00000c04040a7981 */
/* 0x000ea2000c1e1900 */
/*0810*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fe40007ffe0ff */
/*0820*/ IADD3 R7, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fe40007ffe0ff */
/*0830*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0840*/ FADD R9, R15, R10 ; /* 0x0000000a0f097221 */
/* 0x004fe20000000000 */
/*0850*/ IADD3 R10, P1, R4, 0x10, RZ ; /* 0x00000010040a7810 */
/* 0x000fc80007f3e0ff */
/*0860*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e2000c101904 */
/*0870*/ IMAD.X R11, RZ, RZ, R5, P1 ; /* 0x000000ffff0b7224 */
/* 0x001fe400008e0605 */
/*0880*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000a */
/*0890*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fe400078e000b */
/*08a0*/ @P0 BRA 0x770 ; /* 0xfffffec000000947 */
/* 0x002fea000383ffff */
/*08b0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*08c0*/ @!P0 BRA 0x990 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*08d0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x028162000c1e1900 */
/*08e0*/ IMAD.WIDE R6, R7, R6, c[0x0][0x168] ; /* 0x00005a0007067625 */
/* 0x000fc800078e0206 */
/*08f0*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0006 */
/*0900*/ IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff057224 */
/* 0x000fca00078e0007 */
/*0910*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0920*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe40007ffe0ff */
/*0930*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe40007f3e0ff */
/*0940*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc60003f05270 */
/*0950*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x000fe400008e0607 */
/*0960*/ FADD R9, R4, R9 ; /* 0x0000000904097221 */
/* 0x026fca0000000000 */
/*0970*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e6000c101904 */
/*0980*/ @P0 BRA 0x8f0 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0990*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea2000c1e1900 */
/*09a0*/ I2F R4, c[0x0][0x160] ; /* 0x0000580000047b06 */
/* 0x000f220000201400 */
/*09b0*/ BSSY B0, 0xa80 ; /* 0x000000c000007945 */
/* 0x000fee0003800000 */
/*09c0*/ MUFU.RCP R5, R4 ; /* 0x0000000400057308 */
/* 0x010f240000001000 */
/*09d0*/ FFMA R0, -R4, R5, 1 ; /* 0x3f80000004007423 */
/* 0x010fc80000000105 */
/*09e0*/ FFMA R0, R5, R0, R5 ; /* 0x0000000005007223 */
/* 0x000fe40000000005 */
/*09f0*/ FCHK P0, R7, R4 ; /* 0x0000000407007302 */
/* 0x004ea40000000000 */
/*0a00*/ FFMA R5, R0, R7, RZ ; /* 0x0000000700057223 */
/* 0x000fc800000000ff */
/*0a10*/ FFMA R6, -R4, R5, R7 ; /* 0x0000000504067223 */
/* 0x000fc80000000107 */
/*0a20*/ FFMA R5, R0, R6, R5 ; /* 0x0000000600057223 */
/* 0x000fe20000000005 */
/*0a30*/ @!P0 BRA 0xa70 ; /* 0x0000003000008947 */
/* 0x004fea0003800000 */
/*0a40*/ MOV R0, 0xa60 ; /* 0x00000a6000007802 */
/* 0x000fe40000000f00 */
/*0a50*/ CALL.REL.NOINC 0xaa0 ; /* 0x0000004000007944 */
/* 0x02bfea0003c00000 */
/*0a60*/ MOV R5, R6 ; /* 0x0000000600057202 */
/* 0x000fe40000000f00 */
/*0a70*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0a80*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0a90*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0aa0*/ SHF.R.U32.HI R6, RZ, 0x17, R4.reuse ; /* 0x00000017ff067819 */
/* 0x100fe20000011604 */
/*0ab0*/ BSSY B1, 0x1100 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0ac0*/ SHF.R.U32.HI R5, RZ, 0x17, R7 ; /* 0x00000017ff057819 */
/* 0x000fe20000011607 */
/*0ad0*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0004 */
/*0ae0*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fe400078ec0ff */
/*0af0*/ LOP3.LUT R11, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff050b7812 */
/* 0x000fe400078ec0ff */
/*0b00*/ IADD3 R10, R6, -0x1, RZ ; /* 0xffffffff060a7810 */
/* 0x000fc40007ffe0ff */
/*0b10*/ IADD3 R12, R11, -0x1, RZ ; /* 0xffffffff0b0c7810 */
/* 0x000fe40007ffe0ff */
/*0b20*/ ISETP.GT.U32.AND P0, PT, R10, 0xfd, PT ; /* 0x000000fd0a00780c */
/* 0x000fc80003f04070 */
/*0b30*/ ISETP.GT.U32.OR P0, PT, R12, 0xfd, P0 ; /* 0x000000fd0c00780c */
/* 0x000fda0000704470 */
/*0b40*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*0b50*/ @!P0 BRA 0xce0 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0b60*/ FSETP.GTU.FTZ.AND P0, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fe20003f1c200 */
/*0b70*/ IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0007 */
/*0b80*/ FSETP.GTU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fc80003f3c200 */
/*0b90*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0ba0*/ @P0 BRA 0x10e0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0bb0*/ LOP3.LUT P0, RZ, R8, 0x7fffffff, R7, 0xc8, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000780c807 */
/*0bc0*/ @!P0 BRA 0x10c0 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0bd0*/ FSETP.NEU.FTZ.AND P2, PT, |R5|.reuse, +INF , PT ; /* 0x7f8000000500780b */
/* 0x040fe40003f5d200 */
/*0be0*/ FSETP.NEU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f3d200 */
/*0bf0*/ FSETP.NEU.FTZ.AND P0, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fd60003f1d200 */
/*0c00*/ @!P1 BRA !P2, 0x10c0 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0c10*/ LOP3.LUT P2, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000784c0ff */
/*0c20*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0c30*/ @P1 BRA 0x10a0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0c40*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000782c0ff */
/*0c50*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0c60*/ @P0 BRA 0x1070 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0c70*/ ISETP.GE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f06270 */
/*0c80*/ ISETP.GE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fd60003f26270 */
/*0c90*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff090224 */
/* 0x000fe400078e00ff */
/*0ca0*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; /* 0xffffffc0ff098424 */
/* 0x000fe400078e00ff */
/*0cb0*/ @!P0 FFMA R7, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f80000005078823 */
/* 0x000fe400000000ff */
/*0cc0*/ @!P1 FFMA R8, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004089823 */
/* 0x000fe200000000ff */
/*0cd0*/ @!P1 IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009099810 */
/* 0x000fe40007ffe0ff */
/*0ce0*/ LEA R5, R6, 0xc0800000, 0x17 ; /* 0xc080000006057811 */
/* 0x000fe200078eb8ff */
/*0cf0*/ BSSY B2, 0x1060 ; /* 0x0000036000027945 */
/* 0x000fe80003800000 */
/*0d00*/ IMAD.IADD R8, R8, 0x1, -R5 ; /* 0x0000000108087824 */
/* 0x000fe200078e0a05 */
/*0d10*/ IADD3 R5, R11, -0x7f, RZ ; /* 0xffffff810b057810 */
/* 0x000fc60007ffe0ff */
/*0d20*/ MUFU.RCP R4, R8 ; /* 0x0000000800047308 */
/* 0x000e220000001000 */
/*0d30*/ FADD.FTZ R10, -R8, -RZ ; /* 0x800000ff080a7221 */
/* 0x000fe20000010100 */
/*0d40*/ IADD3 R6, R5.reuse, 0x7f, -R6 ; /* 0x0000007f05067810 */
/* 0x040fe20007ffe806 */
/*0d50*/ IMAD R7, R5, -0x800000, R7 ; /* 0xff80000005077824 */
/* 0x000fc800078e0207 */
/*0d60*/ IMAD.IADD R6, R6, 0x1, R9 ; /* 0x0000000106067824 */
/* 0x000fe400078e0209 */
/*0d70*/ FFMA R11, R4, R10, 1 ; /* 0x3f800000040b7423 */
/* 0x001fc8000000000a */
/*0d80*/ FFMA R12, R4, R11, R4 ; /* 0x0000000b040c7223 */
/* 0x000fc80000000004 */
/*0d90*/ FFMA R4, R7, R12, RZ ; /* 0x0000000c07047223 */
/* 0x000fc800000000ff */
/*0da0*/ FFMA R11, R10, R4, R7 ; /* 0x000000040a0b7223 */
/* 0x000fc80000000007 */
/*0db0*/ FFMA R11, R12, R11, R4 ; /* 0x0000000b0c0b7223 */
/* 0x000fc80000000004 */
/*0dc0*/ FFMA R10, R10, R11, R7 ; /* 0x0000000b0a0a7223 */
/* 0x000fc80000000007 */
/*0dd0*/ FFMA R4, R12, R10, R11 ; /* 0x0000000a0c047223 */
/* 0x000fca000000000b */
/*0de0*/ SHF.R.U32.HI R5, RZ, 0x17, R4 ; /* 0x00000017ff057819 */
/* 0x000fc80000011604 */
/*0df0*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fc800078ec0ff */
/*0e00*/ IADD3 R9, R5, R6, RZ ; /* 0x0000000605097210 */
/* 0x000fc80007ffe0ff */
/*0e10*/ IADD3 R5, R9, -0x1, RZ ; /* 0xffffffff09057810 */
/* 0x000fc80007ffe0ff */
/*0e20*/ ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f06070 */
/*0e30*/ @!P0 BRA 0x1040 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0e40*/ ISETP.GT.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f04270 */
/*0e50*/ @P0 BRA 0x1010 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0e60*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*0e70*/ @P0 BRA 0x1050 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0e80*/ ISETP.GE.AND P0, PT, R9, -0x18, PT ; /* 0xffffffe80900780c */
/* 0x000fe40003f06270 */
/*0e90*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fd600078ec0ff */
/*0ea0*/ @!P0 BRA 0x1050 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0eb0*/ FFMA.RZ R5, R12.reuse, R10.reuse, R11.reuse ; /* 0x0000000a0c057223 */
/* 0x1c0fe2000000c00b */
/*0ec0*/ IADD3 R8, R9.reuse, 0x20, RZ ; /* 0x0000002009087810 */
/* 0x040fe20007ffe0ff */
/*0ed0*/ FFMA.RM R6, R12.reuse, R10.reuse, R11.reuse ; /* 0x0000000a0c067223 */
/* 0x1c0fe2000000400b */
/*0ee0*/ ISETP.NE.AND P2, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f45270 */
/*0ef0*/ LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05077812 */
/* 0x000fe200078ec0ff */
/*0f00*/ FFMA.RP R5, R12, R10, R11 ; /* 0x0000000a0c057223 */
/* 0x000fe2000000800b */
/*0f10*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f25270 */
/*0f20*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a09 */
/*0f30*/ LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007077812 */
/* 0x000fe400078efcff */
/*0f40*/ FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x000fc40003f1d000 */
/*0f50*/ SHF.L.U32 R8, R7, R8, RZ ; /* 0x0000000807087219 */
/* 0x000fe400000006ff */
/*0f60*/ SEL R6, R9, RZ, P2 ; /* 0x000000ff09067207 */
/* 0x000fe40001000000 */
/*0f70*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*0f80*/ SHF.R.U32.HI R6, RZ, R6, R7 ; /* 0x00000006ff067219 */
/* 0x000fe40000011607 */
/*0f90*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0fa0*/ SHF.R.U32.HI R8, RZ, 0x1, R6 ; /* 0x00000001ff087819 */
/* 0x000fc40000011606 */
/*0fb0*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*0fc0*/ LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef808 */
/*0fd0*/ LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ; /* 0x0000000605057212 */
/* 0x000fca00078ec0ff */
/*0fe0*/ IMAD.IADD R5, R8, 0x1, R5 ; /* 0x0000000108057824 */
/* 0x000fca00078e0205 */
/*0ff0*/ LOP3.LUT R4, R5, R4, RZ, 0xfc, !PT ; /* 0x0000000405047212 */
/* 0x000fe200078efcff */
/*1000*/ BRA 0x1050 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*1010*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fc800078ec0ff */
/*1020*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*1030*/ BRA 0x1050 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*1040*/ IMAD R4, R6, 0x800000, R4 ; /* 0x0080000006047824 */
/* 0x000fe400078e0204 */
/*1050*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*1060*/ BRA 0x10f0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*1070*/ LOP3.LUT R4, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008047812 */
/* 0x000fc800078e4807 */
/*1080*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*1090*/ BRA 0x10f0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*10a0*/ LOP3.LUT R4, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008047812 */
/* 0x000fe200078e4807 */
/*10b0*/ BRA 0x10f0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*10c0*/ MUFU.RSQ R4, -QNAN ; /* 0xffc0000000047908 */
/* 0x000e220000001400 */
/*10d0*/ BRA 0x10f0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*10e0*/ FADD.FTZ R4, R5, R4 ; /* 0x0000000405047221 */
/* 0x000fe40000010000 */
/*10f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*1100*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x001fe400078e0004 */
/*1110*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*1120*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*1130*/ RET.REL.NODEC R4 0x0 ; /* 0xffffeec004007950 */
/* 0x000fea0003c3ffff */
/*1140*/ BRA 0x1140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void naiveKernel(int N, float *input, float *output){
int global_i = blockIdx.x * blockDim.x + threadIdx.x;
if(global_i < N){
for(int i=0;i<N;++i) output[global_i] += input[i];
output[global_i] /= N;
}
return ;
} | .file "tmpxft_0008d779_00000000-6_naiveKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z11naiveKerneliPfS_iPfS_
.type _Z34__device_stub__Z11naiveKerneliPfS_iPfS_, @function
_Z34__device_stub__Z11naiveKerneliPfS_iPfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11naiveKerneliPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z11naiveKerneliPfS_iPfS_, .-_Z34__device_stub__Z11naiveKerneliPfS_iPfS_
.globl _Z11naiveKerneliPfS_
.type _Z11naiveKerneliPfS_, @function
_Z11naiveKerneliPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z11naiveKerneliPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11naiveKerneliPfS_, .-_Z11naiveKerneliPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11naiveKerneliPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11naiveKerneliPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void naiveKernel(int N, float *input, float *output){
int global_i = blockIdx.x * blockDim.x + threadIdx.x;
if(global_i < N){
for(int i=0;i<N;++i) output[global_i] += input[i];
output[global_i] /= N;
}
return ;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void naiveKernel(int N, float *input, float *output){
int global_i = blockIdx.x * blockDim.x + threadIdx.x;
if(global_i < N){
for(int i=0;i<N;++i) output[global_i] += input[i];
output[global_i] /= N;
}
return ;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void naiveKernel(int N, float *input, float *output){
int global_i = blockIdx.x * blockDim.x + threadIdx.x;
if(global_i < N){
for(int i=0;i<N;++i) output[global_i] += input[i];
output[global_i] /= N;
}
return ;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11naiveKerneliPfS_
.globl _Z11naiveKerneliPfS_
.p2align 8
.type _Z11naiveKerneliPfS_,@function
_Z11naiveKerneliPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_5
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x8
v_mov_b32_e32 v5, 0
s_mov_b32 s5, s4
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v0, v[3:4], off
.LBB0_3:
global_load_b32 v6, v5, s[0:1]
s_add_i32 s5, s5, -1
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s5, 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v6, v0
global_store_b32 v[3:4], v0, off
s_cbranch_scc0 .LBB0_3
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_cvt_f32_i32_e32 v3, s4
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v4, null, v3, v3, v2
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, v2, v3, v2
v_mul_f32_e32 v7, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v4, v7, v6
v_fmac_f32_e32 v7, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v7, v6
v_div_fmas_f32 v4, v4, v5, v7
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v2, v4, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11naiveKerneliPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11naiveKerneliPfS_, .Lfunc_end0-_Z11naiveKerneliPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11naiveKerneliPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11naiveKerneliPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void naiveKernel(int N, float *input, float *output){
int global_i = blockIdx.x * blockDim.x + threadIdx.x;
if(global_i < N){
for(int i=0;i<N;++i) output[global_i] += input[i];
output[global_i] /= N;
}
return ;
} | .text
.file "naiveKernel.hip"
.globl _Z26__device_stub__naiveKerneliPfS_ # -- Begin function _Z26__device_stub__naiveKerneliPfS_
.p2align 4, 0x90
.type _Z26__device_stub__naiveKerneliPfS_,@function
_Z26__device_stub__naiveKerneliPfS_: # @_Z26__device_stub__naiveKerneliPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11naiveKerneliPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z26__device_stub__naiveKerneliPfS_, .Lfunc_end0-_Z26__device_stub__naiveKerneliPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11naiveKerneliPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11naiveKerneliPfS_,@object # @_Z11naiveKerneliPfS_
.section .rodata,"a",@progbits
.globl _Z11naiveKerneliPfS_
.p2align 3, 0x0
_Z11naiveKerneliPfS_:
.quad _Z26__device_stub__naiveKerneliPfS_
.size _Z11naiveKerneliPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11naiveKerneliPfS_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__naiveKerneliPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11naiveKerneliPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11naiveKerneliPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ; /* 0x0000580003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x160], PT ; /* 0x00005800ff007a0c */
/* 0x000fe20003f01270 */
/*0070*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0090*/ IMAD.WIDE R2, R3, R6, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fd000078e0206 */
/*00a0*/ @!P0 BRA 0x990 ; /* 0x000008e000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff007624 */
/* 0x000fe400078e00ff */
/*00c0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fc600078e00ff */
/*00d0*/ IADD3 R4, R0.reuse, -0x1, RZ ; /* 0xffffffff00047810 */
/* 0x040fe40007ffe0ff */
/*00e0*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe400078ec0ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fda0003f06070 */
/*0100*/ @!P0 BRA 0x8b0 ; /* 0x000007a000008947 */
/* 0x000fea0003800000 */
/*0110*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000162000c1e1900 */
/*0120*/ IADD3 R8, -R0, c[0x0][0x160], RZ ; /* 0x0000580000087a10 */
/* 0x000fe20007ffe1ff */
/*0130*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe400078e00ff */
/*0140*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0150*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f04270 */
/*0160*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fd800078e00ff */
/*0170*/ @!P0 BRA 0x770 ; /* 0x000005f000008947 */
/* 0x001fea0003800000 */
/*0180*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*0190*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01a0*/ @!P1 BRA 0x540 ; /* 0x0000039000009947 */
/* 0x000fea0003800000 */
/*01b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01c0*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea4000c1e1900 */
/*01d0*/ FADD R9, R10, R9 ; /* 0x000000090a097221 */
/* 0x02cfca0000000000 */
/*01e0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*01f0*/ LDG.E R10, [R4.64+0x4] ; /* 0x00000404040a7981 */
/* 0x000ea4000c1e1900 */
/*0200*/ FADD R11, R9, R10 ; /* 0x0000000a090b7221 */
/* 0x004fca0000000000 */
/*0210*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101904 */
/*0220*/ LDG.E R10, [R4.64+0x8] ; /* 0x00000804040a7981 */
/* 0x000ea4000c1e1900 */
/*0230*/ FADD R13, R11, R10 ; /* 0x0000000a0b0d7221 */
/* 0x004fca0000000000 */
/*0240*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*0250*/ LDG.E R10, [R4.64+0xc] ; /* 0x00000c04040a7981 */
/* 0x000ee4000c1e1900 */
/*0260*/ FADD R15, R13, R10 ; /* 0x0000000a0d0f7221 */
/* 0x008fca0000000000 */
/*0270*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0007e8000c101904 */
/*0280*/ LDG.E R10, [R4.64+0x10] ; /* 0x00001004040a7981 */
/* 0x000e24000c1e1900 */
/*0290*/ FADD R9, R15, R10 ; /* 0x0000000a0f097221 */
/* 0x001fca0000000000 */
/*02a0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*02b0*/ LDG.E R10, [R4.64+0x14] ; /* 0x00001404040a7981 */
/* 0x000e64000c1e1900 */
/*02c0*/ FADD R11, R9, R10 ; /* 0x0000000a090b7221 */
/* 0x002fca0000000000 */
/*02d0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101904 */
/*02e0*/ LDG.E R10, [R4.64+0x18] ; /* 0x00001804040a7981 */
/* 0x000ea4000c1e1900 */
/*02f0*/ FADD R13, R11, R10 ; /* 0x0000000a0b0d7221 */
/* 0x004fca0000000000 */
/*0300*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*0310*/ LDG.E R10, [R4.64+0x1c] ; /* 0x00001c04040a7981 */
/* 0x000ee4000c1e1900 */
/*0320*/ FADD R15, R13, R10 ; /* 0x0000000a0d0f7221 */
/* 0x008fca0000000000 */
/*0330*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0007e8000c101904 */
/*0340*/ LDG.E R10, [R4.64+0x20] ; /* 0x00002004040a7981 */
/* 0x000e24000c1e1900 */
/*0350*/ FADD R9, R15, R10 ; /* 0x0000000a0f097221 */
/* 0x001fca0000000000 */
/*0360*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*0370*/ LDG.E R10, [R4.64+0x24] ; /* 0x00002404040a7981 */
/* 0x000e64000c1e1900 */
/*0380*/ FADD R11, R9, R10 ; /* 0x0000000a090b7221 */
/* 0x002fca0000000000 */
/*0390*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101904 */
/*03a0*/ LDG.E R10, [R4.64+0x28] ; /* 0x00002804040a7981 */
/* 0x000ea4000c1e1900 */
/*03b0*/ FADD R13, R11, R10 ; /* 0x0000000a0b0d7221 */
/* 0x004fca0000000000 */
/*03c0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0003e8000c101904 */
/*03d0*/ LDG.E R10, [R4.64+0x2c] ; /* 0x00002c04040a7981 */
/* 0x000ee4000c1e1900 */
/*03e0*/ FADD R15, R13, R10 ; /* 0x0000000a0d0f7221 */
/* 0x008fca0000000000 */
/*03f0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0005e8000c101904 */
/*0400*/ LDG.E R10, [R4.64+0x30] ; /* 0x00003004040a7981 */
/* 0x000ee4000c1e1900 */
/*0410*/ FADD R17, R15, R10 ; /* 0x0000000a0f117221 */
/* 0x008fca0000000000 */
/*0420*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0007e8000c101904 */
/*0430*/ LDG.E R10, [R4.64+0x34] ; /* 0x00003404040a7981 */
/* 0x000e24000c1e1900 */
/*0440*/ FADD R11, R17, R10 ; /* 0x0000000a110b7221 */
/* 0x001fca0000000000 */
/*0450*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0007e8000c101904 */
/*0460*/ LDG.E R10, [R4.64+0x38] ; /* 0x00003804040a7981 */
/* 0x000e64000c1e1900 */
/*0470*/ FADD R13, R11, R10 ; /* 0x0000000a0b0d7221 */
/* 0x002fca0000000000 */
/*0480*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*0490*/ LDG.E R10, [R4.64+0x3c] ; /* 0x00003c04040a7981 */
/* 0x000f22000c1e1900 */
/*04a0*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fe40007ffe0ff */
/*04b0*/ IADD3 R7, R7, 0x10, RZ ; /* 0x0000001007077810 */
/* 0x000fe40007ffe0ff */
/*04c0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe20003f24270 */
/*04d0*/ FADD R9, R13, R10 ; /* 0x0000000a0d097221 */
/* 0x010fe20000000000 */
/*04e0*/ IADD3 R10, P2, R4, 0x40, RZ ; /* 0x00000040040a7810 */
/* 0x000fc80007f5e0ff */
/*04f0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0007e2000c101904 */
/*0500*/ IMAD.X R15, RZ, RZ, R5, P2 ; /* 0x000000ffff0f7224 */
/* 0x004fe400010e0605 */
/*0510*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000a */
/*0520*/ IMAD.MOV.U32 R5, RZ, RZ, R15 ; /* 0x000000ffff057224 */
/* 0x000fe400078e000f */
/*0530*/ @P1 BRA 0x1c0 ; /* 0xfffffc8000001947 */
/* 0x000fea000383ffff */
/*0540*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*0550*/ @!P1 BRA 0x750 ; /* 0x000001f000009947 */
/* 0x000fea0003800000 */
/*0560*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea4000c1e1900 */
/*0570*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x02cfca0000000000 */
/*0580*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*0590*/ LDG.E R10, [R4.64+0x4] ; /* 0x00000404040a7981 */
/* 0x000ea4000c1e1900 */
/*05a0*/ FADD R11, R9, R10 ; /* 0x0000000a090b7221 */
/* 0x004fca0000000000 */
/*05b0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101904 */
/*05c0*/ LDG.E R10, [R4.64+0x8] ; /* 0x00000804040a7981 */
/* 0x000ea4000c1e1900 */
/*05d0*/ FADD R13, R11, R10 ; /* 0x0000000a0b0d7221 */
/* 0x004fca0000000000 */
/*05e0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0003e8000c101904 */
/*05f0*/ LDG.E R10, [R4.64+0xc] ; /* 0x00000c04040a7981 */
/* 0x000ea4000c1e1900 */
/*0600*/ FADD R15, R13, R10 ; /* 0x0000000a0d0f7221 */
/* 0x004fca0000000000 */
/*0610*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0005e8000c101904 */
/*0620*/ LDG.E R10, [R4.64+0x10] ; /* 0x00001004040a7981 */
/* 0x000ee4000c1e1900 */
/*0630*/ FADD R17, R15, R10 ; /* 0x0000000a0f117221 */
/* 0x008fca0000000000 */
/*0640*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0007e8000c101904 */
/*0650*/ LDG.E R10, [R4.64+0x14] ; /* 0x00001404040a7981 */
/* 0x000e24000c1e1900 */
/*0660*/ FADD R11, R17, R10 ; /* 0x0000000a110b7221 */
/* 0x001fca0000000000 */
/*0670*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0007e8000c101904 */
/*0680*/ LDG.E R10, [R4.64+0x18] ; /* 0x00001804040a7981 */
/* 0x000e64000c1e1900 */
/*0690*/ FADD R13, R11, R10 ; /* 0x0000000a0b0d7221 */
/* 0x002fca0000000000 */
/*06a0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*06b0*/ LDG.E R10, [R4.64+0x1c] ; /* 0x00001c04040a7981 */
/* 0x000f22000c1e1900 */
/*06c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*06d0*/ IADD3 R7, R7, 0x8, RZ ; /* 0x0000000807077810 */
/* 0x000fe40007ffe0ff */
/*06e0*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fe20007ffe0ff */
/*06f0*/ FADD R9, R13, R10 ; /* 0x0000000a0d097221 */
/* 0x010fe20000000000 */
/*0700*/ IADD3 R10, P1, R4, 0x20, RZ ; /* 0x00000020040a7810 */
/* 0x000fc80007f3e0ff */
/*0710*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0007e2000c101904 */
/*0720*/ IMAD.X R15, RZ, RZ, R5, P1 ; /* 0x000000ffff0f7224 */
/* 0x004fe200008e0605 */
/*0730*/ MOV R4, R10 ; /* 0x0000000a00047202 */
/* 0x000fc60000000f00 */
/*0740*/ IMAD.MOV.U32 R5, RZ, RZ, R15 ; /* 0x000000ffff057224 */
/* 0x000fe400078e000f */
/*0750*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0000705670 */
/*0760*/ @!P0 BRA 0x8b0 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*0770*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea4000c1e1900 */
/*0780*/ FADD R11, R10, R9 ; /* 0x000000090a0b7221 */
/* 0x02cfca0000000000 */
/*0790*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101904 */
/*07a0*/ LDG.E R10, [R4.64+0x4] ; /* 0x00000404040a7981 */
/* 0x000ea4000c1e1900 */
/*07b0*/ FADD R13, R11, R10 ; /* 0x0000000a0b0d7221 */
/* 0x004fca0000000000 */
/*07c0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0003e8000c101904 */
/*07d0*/ LDG.E R10, [R4.64+0x8] ; /* 0x00000804040a7981 */
/* 0x000ea4000c1e1900 */
/*07e0*/ FADD R15, R13, R10 ; /* 0x0000000a0d0f7221 */
/* 0x004fca0000000000 */
/*07f0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0003e8000c101904 */
/*0800*/ LDG.E R10, [R4.64+0xc] ; /* 0x00000c04040a7981 */
/* 0x000ea2000c1e1900 */
/*0810*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fe40007ffe0ff */
/*0820*/ IADD3 R7, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fe40007ffe0ff */
/*0830*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0840*/ FADD R9, R15, R10 ; /* 0x0000000a0f097221 */
/* 0x004fe20000000000 */
/*0850*/ IADD3 R10, P1, R4, 0x10, RZ ; /* 0x00000010040a7810 */
/* 0x000fc80007f3e0ff */
/*0860*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e2000c101904 */
/*0870*/ IMAD.X R11, RZ, RZ, R5, P1 ; /* 0x000000ffff0b7224 */
/* 0x001fe400008e0605 */
/*0880*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000a */
/*0890*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fe400078e000b */
/*08a0*/ @P0 BRA 0x770 ; /* 0xfffffec000000947 */
/* 0x002fea000383ffff */
/*08b0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*08c0*/ @!P0 BRA 0x990 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*08d0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x028162000c1e1900 */
/*08e0*/ IMAD.WIDE R6, R7, R6, c[0x0][0x168] ; /* 0x00005a0007067625 */
/* 0x000fc800078e0206 */
/*08f0*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0006 */
/*0900*/ IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff057224 */
/* 0x000fca00078e0007 */
/*0910*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0920*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe40007ffe0ff */
/*0930*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe40007f3e0ff */
/*0940*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc60003f05270 */
/*0950*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x000fe400008e0607 */
/*0960*/ FADD R9, R4, R9 ; /* 0x0000000904097221 */
/* 0x026fca0000000000 */
/*0970*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e6000c101904 */
/*0980*/ @P0 BRA 0x8f0 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0990*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea2000c1e1900 */
/*09a0*/ I2F R4, c[0x0][0x160] ; /* 0x0000580000047b06 */
/* 0x000f220000201400 */
/*09b0*/ BSSY B0, 0xa80 ; /* 0x000000c000007945 */
/* 0x000fee0003800000 */
/*09c0*/ MUFU.RCP R5, R4 ; /* 0x0000000400057308 */
/* 0x010f240000001000 */
/*09d0*/ FFMA R0, -R4, R5, 1 ; /* 0x3f80000004007423 */
/* 0x010fc80000000105 */
/*09e0*/ FFMA R0, R5, R0, R5 ; /* 0x0000000005007223 */
/* 0x000fe40000000005 */
/*09f0*/ FCHK P0, R7, R4 ; /* 0x0000000407007302 */
/* 0x004ea40000000000 */
/*0a00*/ FFMA R5, R0, R7, RZ ; /* 0x0000000700057223 */
/* 0x000fc800000000ff */
/*0a10*/ FFMA R6, -R4, R5, R7 ; /* 0x0000000504067223 */
/* 0x000fc80000000107 */
/*0a20*/ FFMA R5, R0, R6, R5 ; /* 0x0000000600057223 */
/* 0x000fe20000000005 */
/*0a30*/ @!P0 BRA 0xa70 ; /* 0x0000003000008947 */
/* 0x004fea0003800000 */
/*0a40*/ MOV R0, 0xa60 ; /* 0x00000a6000007802 */
/* 0x000fe40000000f00 */
/*0a50*/ CALL.REL.NOINC 0xaa0 ; /* 0x0000004000007944 */
/* 0x02bfea0003c00000 */
/*0a60*/ MOV R5, R6 ; /* 0x0000000600057202 */
/* 0x000fe40000000f00 */
/*0a70*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0a80*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0a90*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0aa0*/ SHF.R.U32.HI R6, RZ, 0x17, R4.reuse ; /* 0x00000017ff067819 */
/* 0x100fe20000011604 */
/*0ab0*/ BSSY B1, 0x1100 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0ac0*/ SHF.R.U32.HI R5, RZ, 0x17, R7 ; /* 0x00000017ff057819 */
/* 0x000fe20000011607 */
/*0ad0*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0004 */
/*0ae0*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fe400078ec0ff */
/*0af0*/ LOP3.LUT R11, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff050b7812 */
/* 0x000fe400078ec0ff */
/*0b00*/ IADD3 R10, R6, -0x1, RZ ; /* 0xffffffff060a7810 */
/* 0x000fc40007ffe0ff */
/*0b10*/ IADD3 R12, R11, -0x1, RZ ; /* 0xffffffff0b0c7810 */
/* 0x000fe40007ffe0ff */
/*0b20*/ ISETP.GT.U32.AND P0, PT, R10, 0xfd, PT ; /* 0x000000fd0a00780c */
/* 0x000fc80003f04070 */
/*0b30*/ ISETP.GT.U32.OR P0, PT, R12, 0xfd, P0 ; /* 0x000000fd0c00780c */
/* 0x000fda0000704470 */
/*0b40*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*0b50*/ @!P0 BRA 0xce0 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0b60*/ FSETP.GTU.FTZ.AND P0, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fe20003f1c200 */
/*0b70*/ IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0007 */
/*0b80*/ FSETP.GTU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fc80003f3c200 */
/*0b90*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0ba0*/ @P0 BRA 0x10e0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0bb0*/ LOP3.LUT P0, RZ, R8, 0x7fffffff, R7, 0xc8, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000780c807 */
/*0bc0*/ @!P0 BRA 0x10c0 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0bd0*/ FSETP.NEU.FTZ.AND P2, PT, |R5|.reuse, +INF , PT ; /* 0x7f8000000500780b */
/* 0x040fe40003f5d200 */
/*0be0*/ FSETP.NEU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f3d200 */
/*0bf0*/ FSETP.NEU.FTZ.AND P0, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fd60003f1d200 */
/*0c00*/ @!P1 BRA !P2, 0x10c0 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0c10*/ LOP3.LUT P2, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000784c0ff */
/*0c20*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0c30*/ @P1 BRA 0x10a0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0c40*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000782c0ff */
/*0c50*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0c60*/ @P0 BRA 0x1070 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0c70*/ ISETP.GE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f06270 */
/*0c80*/ ISETP.GE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fd60003f26270 */
/*0c90*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff090224 */
/* 0x000fe400078e00ff */
/*0ca0*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; /* 0xffffffc0ff098424 */
/* 0x000fe400078e00ff */
/*0cb0*/ @!P0 FFMA R7, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f80000005078823 */
/* 0x000fe400000000ff */
/*0cc0*/ @!P1 FFMA R8, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004089823 */
/* 0x000fe200000000ff */
/*0cd0*/ @!P1 IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009099810 */
/* 0x000fe40007ffe0ff */
/*0ce0*/ LEA R5, R6, 0xc0800000, 0x17 ; /* 0xc080000006057811 */
/* 0x000fe200078eb8ff */
/*0cf0*/ BSSY B2, 0x1060 ; /* 0x0000036000027945 */
/* 0x000fe80003800000 */
/*0d00*/ IMAD.IADD R8, R8, 0x1, -R5 ; /* 0x0000000108087824 */
/* 0x000fe200078e0a05 */
/*0d10*/ IADD3 R5, R11, -0x7f, RZ ; /* 0xffffff810b057810 */
/* 0x000fc60007ffe0ff */
/*0d20*/ MUFU.RCP R4, R8 ; /* 0x0000000800047308 */
/* 0x000e220000001000 */
/*0d30*/ FADD.FTZ R10, -R8, -RZ ; /* 0x800000ff080a7221 */
/* 0x000fe20000010100 */
/*0d40*/ IADD3 R6, R5.reuse, 0x7f, -R6 ; /* 0x0000007f05067810 */
/* 0x040fe20007ffe806 */
/*0d50*/ IMAD R7, R5, -0x800000, R7 ; /* 0xff80000005077824 */
/* 0x000fc800078e0207 */
/*0d60*/ IMAD.IADD R6, R6, 0x1, R9 ; /* 0x0000000106067824 */
/* 0x000fe400078e0209 */
/*0d70*/ FFMA R11, R4, R10, 1 ; /* 0x3f800000040b7423 */
/* 0x001fc8000000000a */
/*0d80*/ FFMA R12, R4, R11, R4 ; /* 0x0000000b040c7223 */
/* 0x000fc80000000004 */
/*0d90*/ FFMA R4, R7, R12, RZ ; /* 0x0000000c07047223 */
/* 0x000fc800000000ff */
/*0da0*/ FFMA R11, R10, R4, R7 ; /* 0x000000040a0b7223 */
/* 0x000fc80000000007 */
/*0db0*/ FFMA R11, R12, R11, R4 ; /* 0x0000000b0c0b7223 */
/* 0x000fc80000000004 */
/*0dc0*/ FFMA R10, R10, R11, R7 ; /* 0x0000000b0a0a7223 */
/* 0x000fc80000000007 */
/*0dd0*/ FFMA R4, R12, R10, R11 ; /* 0x0000000a0c047223 */
/* 0x000fca000000000b */
/*0de0*/ SHF.R.U32.HI R5, RZ, 0x17, R4 ; /* 0x00000017ff057819 */
/* 0x000fc80000011604 */
/*0df0*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fc800078ec0ff */
/*0e00*/ IADD3 R9, R5, R6, RZ ; /* 0x0000000605097210 */
/* 0x000fc80007ffe0ff */
/*0e10*/ IADD3 R5, R9, -0x1, RZ ; /* 0xffffffff09057810 */
/* 0x000fc80007ffe0ff */
/*0e20*/ ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f06070 */
/*0e30*/ @!P0 BRA 0x1040 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0e40*/ ISETP.GT.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f04270 */
/*0e50*/ @P0 BRA 0x1010 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0e60*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*0e70*/ @P0 BRA 0x1050 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0e80*/ ISETP.GE.AND P0, PT, R9, -0x18, PT ; /* 0xffffffe80900780c */
/* 0x000fe40003f06270 */
/*0e90*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fd600078ec0ff */
/*0ea0*/ @!P0 BRA 0x1050 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0eb0*/ FFMA.RZ R5, R12.reuse, R10.reuse, R11.reuse ; /* 0x0000000a0c057223 */
/* 0x1c0fe2000000c00b */
/*0ec0*/ IADD3 R8, R9.reuse, 0x20, RZ ; /* 0x0000002009087810 */
/* 0x040fe20007ffe0ff */
/*0ed0*/ FFMA.RM R6, R12.reuse, R10.reuse, R11.reuse ; /* 0x0000000a0c067223 */
/* 0x1c0fe2000000400b */
/*0ee0*/ ISETP.NE.AND P2, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f45270 */
/*0ef0*/ LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05077812 */
/* 0x000fe200078ec0ff */
/*0f00*/ FFMA.RP R5, R12, R10, R11 ; /* 0x0000000a0c057223 */
/* 0x000fe2000000800b */
/*0f10*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f25270 */
/*0f20*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a09 */
/*0f30*/ LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007077812 */
/* 0x000fe400078efcff */
/*0f40*/ FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x000fc40003f1d000 */
/*0f50*/ SHF.L.U32 R8, R7, R8, RZ ; /* 0x0000000807087219 */
/* 0x000fe400000006ff */
/*0f60*/ SEL R6, R9, RZ, P2 ; /* 0x000000ff09067207 */
/* 0x000fe40001000000 */
/*0f70*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*0f80*/ SHF.R.U32.HI R6, RZ, R6, R7 ; /* 0x00000006ff067219 */
/* 0x000fe40000011607 */
/*0f90*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0fa0*/ SHF.R.U32.HI R8, RZ, 0x1, R6 ; /* 0x00000001ff087819 */
/* 0x000fc40000011606 */
/*0fb0*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*0fc0*/ LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef808 */
/*0fd0*/ LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ; /* 0x0000000605057212 */
/* 0x000fca00078ec0ff */
/*0fe0*/ IMAD.IADD R5, R8, 0x1, R5 ; /* 0x0000000108057824 */
/* 0x000fca00078e0205 */
/*0ff0*/ LOP3.LUT R4, R5, R4, RZ, 0xfc, !PT ; /* 0x0000000405047212 */
/* 0x000fe200078efcff */
/*1000*/ BRA 0x1050 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*1010*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fc800078ec0ff */
/*1020*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*1030*/ BRA 0x1050 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*1040*/ IMAD R4, R6, 0x800000, R4 ; /* 0x0080000006047824 */
/* 0x000fe400078e0204 */
/*1050*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*1060*/ BRA 0x10f0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*1070*/ LOP3.LUT R4, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008047812 */
/* 0x000fc800078e4807 */
/*1080*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*1090*/ BRA 0x10f0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*10a0*/ LOP3.LUT R4, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008047812 */
/* 0x000fe200078e4807 */
/*10b0*/ BRA 0x10f0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*10c0*/ MUFU.RSQ R4, -QNAN ; /* 0xffc0000000047908 */
/* 0x000e220000001400 */
/*10d0*/ BRA 0x10f0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*10e0*/ FADD.FTZ R4, R5, R4 ; /* 0x0000000405047221 */
/* 0x000fe40000010000 */
/*10f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*1100*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x001fe400078e0004 */
/*1110*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*1120*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*1130*/ RET.REL.NODEC R4 0x0 ; /* 0xffffeec004007950 */
/* 0x000fea0003c3ffff */
/*1140*/ BRA 0x1140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11naiveKerneliPfS_
.globl _Z11naiveKerneliPfS_
.p2align 8
.type _Z11naiveKerneliPfS_,@function
_Z11naiveKerneliPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_5
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x8
v_mov_b32_e32 v5, 0
s_mov_b32 s5, s4
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v0, v[3:4], off
.LBB0_3:
global_load_b32 v6, v5, s[0:1]
s_add_i32 s5, s5, -1
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s5, 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v6, v0
global_store_b32 v[3:4], v0, off
s_cbranch_scc0 .LBB0_3
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_cvt_f32_i32_e32 v3, s4
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v4, null, v3, v3, v2
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, v2, v3, v2
v_mul_f32_e32 v7, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v4, v7, v6
v_fmac_f32_e32 v7, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v7, v6
v_div_fmas_f32 v4, v4, v5, v7
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v2, v4, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11naiveKerneliPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11naiveKerneliPfS_, .Lfunc_end0-_Z11naiveKerneliPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11naiveKerneliPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11naiveKerneliPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0008d779_00000000-6_naiveKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z11naiveKerneliPfS_iPfS_
.type _Z34__device_stub__Z11naiveKerneliPfS_iPfS_, @function
_Z34__device_stub__Z11naiveKerneliPfS_iPfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11naiveKerneliPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z11naiveKerneliPfS_iPfS_, .-_Z34__device_stub__Z11naiveKerneliPfS_iPfS_
.globl _Z11naiveKerneliPfS_
.type _Z11naiveKerneliPfS_, @function
_Z11naiveKerneliPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z11naiveKerneliPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11naiveKerneliPfS_, .-_Z11naiveKerneliPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11naiveKerneliPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11naiveKerneliPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "naiveKernel.hip"
.globl _Z26__device_stub__naiveKerneliPfS_ # -- Begin function _Z26__device_stub__naiveKerneliPfS_
.p2align 4, 0x90
.type _Z26__device_stub__naiveKerneliPfS_,@function
_Z26__device_stub__naiveKerneliPfS_: # @_Z26__device_stub__naiveKerneliPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11naiveKerneliPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z26__device_stub__naiveKerneliPfS_, .Lfunc_end0-_Z26__device_stub__naiveKerneliPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11naiveKerneliPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11naiveKerneliPfS_,@object # @_Z11naiveKerneliPfS_
.section .rodata,"a",@progbits
.globl _Z11naiveKerneliPfS_
.p2align 3, 0x0
_Z11naiveKerneliPfS_:
.quad _Z26__device_stub__naiveKerneliPfS_
.size _Z11naiveKerneliPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11naiveKerneliPfS_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__naiveKerneliPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11naiveKerneliPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //
// kernel routine
//
__global__ void VecAdd_kernel(const float* A, const float* B, float* C, int N)
/* Naive kernel */
{
// Uncomment line below and define global index form block and thread indexes
// int i = ;
// Define C[i] below
} | code for sm_80
Function : _Z13VecAdd_kernelPKfS0_Pfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //
// kernel routine
//
__global__ void VecAdd_kernel(const float* A, const float* B, float* C, int N)
/* Naive kernel */
{
// Uncomment line below and define global index form block and thread indexes
// int i = ;
// Define C[i] below
} | .file "tmpxft_0015e0a4_00000000-6_VecAdd_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z13VecAdd_kernelPKfS0_PfiPKfS0_Pfi
.type _Z40__device_stub__Z13VecAdd_kernelPKfS0_PfiPKfS0_Pfi, @function
_Z40__device_stub__Z13VecAdd_kernelPKfS0_PfiPKfS0_Pfi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13VecAdd_kernelPKfS0_Pfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z13VecAdd_kernelPKfS0_PfiPKfS0_Pfi, .-_Z40__device_stub__Z13VecAdd_kernelPKfS0_PfiPKfS0_Pfi
.globl _Z13VecAdd_kernelPKfS0_Pfi
.type _Z13VecAdd_kernelPKfS0_Pfi, @function
_Z13VecAdd_kernelPKfS0_Pfi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z13VecAdd_kernelPKfS0_PfiPKfS0_Pfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13VecAdd_kernelPKfS0_Pfi, .-_Z13VecAdd_kernelPKfS0_Pfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13VecAdd_kernelPKfS0_Pfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13VecAdd_kernelPKfS0_Pfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //
// kernel routine
//
__global__ void VecAdd_kernel(const float* A, const float* B, float* C, int N)
/* Naive kernel */
{
// Uncomment line below and define global index form block and thread indexes
// int i = ;
// Define C[i] below
} | #include <hip/hip_runtime.h>
//
// kernel routine
//
__global__ void VecAdd_kernel(const float* A, const float* B, float* C, int N)
/* Naive kernel */
{
// Uncomment line below and define global index form block and thread indexes
// int i = ;
// Define C[i] below
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
//
// kernel routine
//
__global__ void VecAdd_kernel(const float* A, const float* B, float* C, int N)
/* Naive kernel */
{
// Uncomment line below and define global index form block and thread indexes
// int i = ;
// Define C[i] below
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13VecAdd_kernelPKfS0_Pfi
.globl _Z13VecAdd_kernelPKfS0_Pfi
.p2align 8
.type _Z13VecAdd_kernelPKfS0_Pfi,@function
_Z13VecAdd_kernelPKfS0_Pfi:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13VecAdd_kernelPKfS0_Pfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13VecAdd_kernelPKfS0_Pfi, .Lfunc_end0-_Z13VecAdd_kernelPKfS0_Pfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13VecAdd_kernelPKfS0_Pfi
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z13VecAdd_kernelPKfS0_Pfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
//
// kernel routine
//
__global__ void VecAdd_kernel(const float* A, const float* B, float* C, int N)
/* Naive kernel */
{
// Uncomment line below and define global index form block and thread indexes
// int i = ;
// Define C[i] below
} | .text
.file "VecAdd_kernel.hip"
.globl _Z28__device_stub__VecAdd_kernelPKfS0_Pfi # -- Begin function _Z28__device_stub__VecAdd_kernelPKfS0_Pfi
.p2align 4, 0x90
.type _Z28__device_stub__VecAdd_kernelPKfS0_Pfi,@function
_Z28__device_stub__VecAdd_kernelPKfS0_Pfi: # @_Z28__device_stub__VecAdd_kernelPKfS0_Pfi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13VecAdd_kernelPKfS0_Pfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__VecAdd_kernelPKfS0_Pfi, .Lfunc_end0-_Z28__device_stub__VecAdd_kernelPKfS0_Pfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13VecAdd_kernelPKfS0_Pfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13VecAdd_kernelPKfS0_Pfi,@object # @_Z13VecAdd_kernelPKfS0_Pfi
.section .rodata,"a",@progbits
.globl _Z13VecAdd_kernelPKfS0_Pfi
.p2align 3, 0x0
_Z13VecAdd_kernelPKfS0_Pfi:
.quad _Z28__device_stub__VecAdd_kernelPKfS0_Pfi
.size _Z13VecAdd_kernelPKfS0_Pfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13VecAdd_kernelPKfS0_Pfi"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__VecAdd_kernelPKfS0_Pfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13VecAdd_kernelPKfS0_Pfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13VecAdd_kernelPKfS0_Pfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13VecAdd_kernelPKfS0_Pfi
.globl _Z13VecAdd_kernelPKfS0_Pfi
.p2align 8
.type _Z13VecAdd_kernelPKfS0_Pfi,@function
_Z13VecAdd_kernelPKfS0_Pfi:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13VecAdd_kernelPKfS0_Pfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13VecAdd_kernelPKfS0_Pfi, .Lfunc_end0-_Z13VecAdd_kernelPKfS0_Pfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13VecAdd_kernelPKfS0_Pfi
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z13VecAdd_kernelPKfS0_Pfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0015e0a4_00000000-6_VecAdd_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z13VecAdd_kernelPKfS0_PfiPKfS0_Pfi
.type _Z40__device_stub__Z13VecAdd_kernelPKfS0_PfiPKfS0_Pfi, @function
_Z40__device_stub__Z13VecAdd_kernelPKfS0_PfiPKfS0_Pfi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13VecAdd_kernelPKfS0_Pfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z13VecAdd_kernelPKfS0_PfiPKfS0_Pfi, .-_Z40__device_stub__Z13VecAdd_kernelPKfS0_PfiPKfS0_Pfi
.globl _Z13VecAdd_kernelPKfS0_Pfi
.type _Z13VecAdd_kernelPKfS0_Pfi, @function
_Z13VecAdd_kernelPKfS0_Pfi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z13VecAdd_kernelPKfS0_PfiPKfS0_Pfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13VecAdd_kernelPKfS0_Pfi, .-_Z13VecAdd_kernelPKfS0_Pfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13VecAdd_kernelPKfS0_Pfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13VecAdd_kernelPKfS0_Pfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "VecAdd_kernel.hip"
.globl _Z28__device_stub__VecAdd_kernelPKfS0_Pfi # -- Begin function _Z28__device_stub__VecAdd_kernelPKfS0_Pfi
.p2align 4, 0x90
.type _Z28__device_stub__VecAdd_kernelPKfS0_Pfi,@function
_Z28__device_stub__VecAdd_kernelPKfS0_Pfi: # @_Z28__device_stub__VecAdd_kernelPKfS0_Pfi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13VecAdd_kernelPKfS0_Pfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__VecAdd_kernelPKfS0_Pfi, .Lfunc_end0-_Z28__device_stub__VecAdd_kernelPKfS0_Pfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13VecAdd_kernelPKfS0_Pfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13VecAdd_kernelPKfS0_Pfi,@object # @_Z13VecAdd_kernelPKfS0_Pfi
.section .rodata,"a",@progbits
.globl _Z13VecAdd_kernelPKfS0_Pfi
.p2align 3, 0x0
_Z13VecAdd_kernelPKfS0_Pfi:
.quad _Z28__device_stub__VecAdd_kernelPKfS0_Pfi
.size _Z13VecAdd_kernelPKfS0_Pfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13VecAdd_kernelPKfS0_Pfi"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__VecAdd_kernelPKfS0_Pfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13VecAdd_kernelPKfS0_Pfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "RandomHelper.cuh"
#include <stdio.h>
__global__ void seedRandomizer(curandState** cs, int xDim, int yDim, int r) {
//Gets the thread numbers
int threadX = threadIdx.x + blockIdx.x * blockDim.x;
int threadY = threadIdx.y + blockIdx.y * blockDim.y;
//Gets the stride
int strideX = gridDim.x*blockDim.x;
int strideY = gridDim.y*blockDim.y;
//Loops through the array seeding the randomizer
for (int y = threadY; y < yDim; y += strideY) {
for (int x = threadX; x < xDim; x += strideX) {
//Seeds the randomizer
curand_init(1234, r+y + x * xDim, 0, &cs[y][x]);
}
}
}
curandState** getCS(int statesX, int statesY) {
curandState** cs;
//Allocates the matrix for curandStates
cudaMallocManaged(&cs, statesY * sizeof(curandState*));
for (int y = 0; y < statesY; y++) {
cudaMallocManaged(&cs[y], statesX * sizeof(curandState));
}
return cs;
}
void freeCS(curandState** cs, int statesX, int statesY) {
for (int y = 0; y < statesY; y++) {
cudaFree(&cs[y]);
}
cudaFree(&cs);
} | .file "tmpxft_00114f84_00000000-6_RandomHelper.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2275:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2275:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5getCSii
.type _Z5getCSii, @function
_Z5getCSii:
.LFB2271:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movl %edi, %r12d
movl %esi, %ebx
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movslq %esi, %rbp
salq $3, %rbp
movq %rsp, %rdi
movl $1, %edx
movq %rbp, %rsi
call cudaMallocManaged@PLT
testl %ebx, %ebx
jle .L4
movslq %r12d, %rax
leaq (%rax,%rax,2), %r12
salq $4, %r12
movl $0, %ebx
.L5:
movq %rbx, %rdi
addq (%rsp), %rdi
movl $1, %edx
movq %r12, %rsi
call cudaMallocManaged@PLT
addq $8, %rbx
cmpq %rbx, %rbp
jne .L5
.L4:
movq (%rsp), %rax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L9
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2271:
.size _Z5getCSii, .-_Z5getCSii
.globl _Z6freeCSPP17curandStateXORWOWii
.type _Z6freeCSPP17curandStateXORWOWii, @function
_Z6freeCSPP17curandStateXORWOWii:
.LFB2272:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
movq %rdi, 8(%rsp)
testl %edx, %edx
jle .L11
movslq %edx, %rdx
leaq 0(,%rdx,8), %rbp
movl $0, %ebx
.L12:
movq %rbx, %rdi
addq 8(%rsp), %rdi
call cudaFree@PLT
addq $8, %rbx
cmpq %rbp, %rbx
jne .L12
.L11:
leaq 8(%rsp), %rdi
call cudaFree@PLT
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2272:
.size _Z6freeCSPP17curandStateXORWOWii, .-_Z6freeCSPP17curandStateXORWOWii
.globl _Z56__device_stub__Z14seedRandomizerPP17curandStateXORWOWiiiPP17curandStateXORWOWiii
.type _Z56__device_stub__Z14seedRandomizerPP17curandStateXORWOWiiiPP17curandStateXORWOWiii, @function
_Z56__device_stub__Z14seedRandomizerPP17curandStateXORWOWiiiPP17curandStateXORWOWiii:
.LFB2297:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14seedRandomizerPP17curandStateXORWOWiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2297:
.size _Z56__device_stub__Z14seedRandomizerPP17curandStateXORWOWiiiPP17curandStateXORWOWiii, .-_Z56__device_stub__Z14seedRandomizerPP17curandStateXORWOWiiiPP17curandStateXORWOWiii
.globl _Z14seedRandomizerPP17curandStateXORWOWiii
.type _Z14seedRandomizerPP17curandStateXORWOWiii, @function
_Z14seedRandomizerPP17curandStateXORWOWiii:
.LFB2298:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z56__device_stub__Z14seedRandomizerPP17curandStateXORWOWiiiPP17curandStateXORWOWiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2298:
.size _Z14seedRandomizerPP17curandStateXORWOWiii, .-_Z14seedRandomizerPP17curandStateXORWOWiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z14seedRandomizerPP17curandStateXORWOWiii"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "precalc_xorwow_matrix"
.LC2:
.string "precalc_xorwow_offset_matrix"
.LC3:
.string "mrg32k3aM1"
.LC4:
.string "mrg32k3aM2"
.LC5:
.string "mrg32k3aM1SubSeq"
.LC6:
.string "mrg32k3aM2SubSeq"
.LC7:
.string "mrg32k3aM1Seq"
.LC8:
.string "mrg32k3aM2Seq"
.LC9:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2300:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14seedRandomizerPP17curandStateXORWOWiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2300:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "RandomHelper.cuh"
#include <stdio.h>
__global__ void seedRandomizer(curandState** cs, int xDim, int yDim, int r) {
//Gets the thread numbers
int threadX = threadIdx.x + blockIdx.x * blockDim.x;
int threadY = threadIdx.y + blockIdx.y * blockDim.y;
//Gets the stride
int strideX = gridDim.x*blockDim.x;
int strideY = gridDim.y*blockDim.y;
//Loops through the array seeding the randomizer
for (int y = threadY; y < yDim; y += strideY) {
for (int x = threadX; x < xDim; x += strideX) {
//Seeds the randomizer
curand_init(1234, r+y + x * xDim, 0, &cs[y][x]);
}
}
}
curandState** getCS(int statesX, int statesY) {
curandState** cs;
//Allocates the matrix for curandStates
cudaMallocManaged(&cs, statesY * sizeof(curandState*));
for (int y = 0; y < statesY; y++) {
cudaMallocManaged(&cs[y], statesX * sizeof(curandState));
}
return cs;
}
void freeCS(curandState** cs, int statesX, int statesY) {
for (int y = 0; y < statesY; y++) {
cudaFree(&cs[y]);
}
cudaFree(&cs);
} | #ifndef RANDOMHELPER_CUH
#define RANDOMHELPER_CUH
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
__global__ void seedRandomizer(hiprandState** cs, int xDim, int yDim, int r);
hiprandState** getCS(int statesX, int statesY);
void freeCS(hiprandState** cs, int statesX, int statesY);
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #ifndef RANDOMHELPER_CUH
#define RANDOMHELPER_CUH
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
__global__ void seedRandomizer(hiprandState** cs, int xDim, int yDim, int r);
hiprandState** getCS(int statesX, int statesY);
void freeCS(hiprandState** cs, int statesX, int statesY);
#endif | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #ifndef RANDOMHELPER_CUH
#define RANDOMHELPER_CUH
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
__global__ void seedRandomizer(hiprandState** cs, int xDim, int yDim, int r);
hiprandState** getCS(int statesX, int statesY);
void freeCS(hiprandState** cs, int statesX, int statesY);
#endif | .text
.file "RandomHelper.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00114f84_00000000-6_RandomHelper.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2275:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2275:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5getCSii
.type _Z5getCSii, @function
_Z5getCSii:
.LFB2271:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movl %edi, %r12d
movl %esi, %ebx
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movslq %esi, %rbp
salq $3, %rbp
movq %rsp, %rdi
movl $1, %edx
movq %rbp, %rsi
call cudaMallocManaged@PLT
testl %ebx, %ebx
jle .L4
movslq %r12d, %rax
leaq (%rax,%rax,2), %r12
salq $4, %r12
movl $0, %ebx
.L5:
movq %rbx, %rdi
addq (%rsp), %rdi
movl $1, %edx
movq %r12, %rsi
call cudaMallocManaged@PLT
addq $8, %rbx
cmpq %rbx, %rbp
jne .L5
.L4:
movq (%rsp), %rax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L9
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2271:
.size _Z5getCSii, .-_Z5getCSii
.globl _Z6freeCSPP17curandStateXORWOWii
.type _Z6freeCSPP17curandStateXORWOWii, @function
_Z6freeCSPP17curandStateXORWOWii:
.LFB2272:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
movq %rdi, 8(%rsp)
testl %edx, %edx
jle .L11
movslq %edx, %rdx
leaq 0(,%rdx,8), %rbp
movl $0, %ebx
.L12:
movq %rbx, %rdi
addq 8(%rsp), %rdi
call cudaFree@PLT
addq $8, %rbx
cmpq %rbp, %rbx
jne .L12
.L11:
leaq 8(%rsp), %rdi
call cudaFree@PLT
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2272:
.size _Z6freeCSPP17curandStateXORWOWii, .-_Z6freeCSPP17curandStateXORWOWii
.globl _Z56__device_stub__Z14seedRandomizerPP17curandStateXORWOWiiiPP17curandStateXORWOWiii
.type _Z56__device_stub__Z14seedRandomizerPP17curandStateXORWOWiiiPP17curandStateXORWOWiii, @function
_Z56__device_stub__Z14seedRandomizerPP17curandStateXORWOWiiiPP17curandStateXORWOWiii:
.LFB2297:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14seedRandomizerPP17curandStateXORWOWiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2297:
.size _Z56__device_stub__Z14seedRandomizerPP17curandStateXORWOWiiiPP17curandStateXORWOWiii, .-_Z56__device_stub__Z14seedRandomizerPP17curandStateXORWOWiiiPP17curandStateXORWOWiii
.globl _Z14seedRandomizerPP17curandStateXORWOWiii
.type _Z14seedRandomizerPP17curandStateXORWOWiii, @function
_Z14seedRandomizerPP17curandStateXORWOWiii:
.LFB2298:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z56__device_stub__Z14seedRandomizerPP17curandStateXORWOWiiiPP17curandStateXORWOWiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2298:
.size _Z14seedRandomizerPP17curandStateXORWOWiii, .-_Z14seedRandomizerPP17curandStateXORWOWiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z14seedRandomizerPP17curandStateXORWOWiii"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "precalc_xorwow_matrix"
.LC2:
.string "precalc_xorwow_offset_matrix"
.LC3:
.string "mrg32k3aM1"
.LC4:
.string "mrg32k3aM2"
.LC5:
.string "mrg32k3aM1SubSeq"
.LC6:
.string "mrg32k3aM2SubSeq"
.LC7:
.string "mrg32k3aM1Seq"
.LC8:
.string "mrg32k3aM2Seq"
.LC9:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2300:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14seedRandomizerPP17curandStateXORWOWiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2300:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "RandomHelper.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
__device__ int mandel(float c_re, float c_im, int maxIteration)
{
float z_re = c_re, z_im = c_im;
int i;
for (i = 0; i < maxIteration; ++i)
{
if (z_re * z_re + z_im * z_im > 4.f)
break;
float new_re = z_re * z_re - z_im * z_im;
float new_im = 2.f * z_re * z_im;
z_re = c_re + new_re;
z_im = c_im + new_im;
}
return i;
}
__global__ void mandelKernel(float x1, float y1, float x0, float y0, int* output, int width, int height, int maxIterations, int pitch, int pixels) {
// To avoid error caused by the floating number, use the following pseudo code
// float x = lowerX + thisX * stepX;
// float y = lowerY + thisY * stepY;
int i = (blockIdx.x * blockDim.x + threadIdx.x) * pixels;
int j = blockIdx.y * blockDim.y + threadIdx.y;
// if (i >= width || j >= height) return;
if (i >= width || j >= height) return;
// i -> 1600, j -> 1200
float dx = (x1 - x0) / width;
float dy = (y1 - y0) / height;
float y = y0 + j * dy;
for(int pixel = 0; pixel < pixels; pixel++) {
float x = x0 + (i + pixel) * dx;
int index = (j * pitch + i) + pixel;
output[index] = mandel(x, y, maxIterations);
}
}
// Host front-end function that allocates the memory and launches the GPU kernel
#define N 1600
#define BLOCK_SIZE 64
void hostFE (float x1, float y1, float x0, float y0, int* output, int width, int height, int maxIterations)
{
int *h_img = NULL, *d_img = NULL;
size_t pitch;
// Locate CPU memory and GPU memory
cudaHostAlloc((void**)&h_img, width * height * sizeof(int), cudaHostAllocDefault);
cudaMallocPitch((void**)&d_img, &pitch, (size_t)width * sizeof(int), (size_t)height);
// Copy memory from CPU to GPU
cudaMemcpy2D(d_img, pitch, h_img, width * sizeof(int), width * sizeof(int), height, cudaMemcpyHostToDevice);
//
dim3 blockSize(BLOCK_SIZE, BLOCK_SIZE);
dim3 numBlock(N / BLOCK_SIZE, N / BLOCK_SIZE);
mandelKernel<<<blockSize, numBlock>>>(x1, y1, x0, y0, d_img, width, height, maxIterations, pitch / sizeof(int), 2);
// Sync
cudaDeviceSynchronize();
// // Copy memory from GPU to CPU
cudaMemcpy2D(h_img, width * sizeof(int), d_img, pitch, width * sizeof(int), height, cudaMemcpyDeviceToHost);
// // Copy memory from CPU to CPU(answers)
memcpy(output, h_img, width * height * sizeof(int));
cudaFree(h_img);
cudaFree(d_img);
} | code for sm_80
Function : _Z12mandelKernelffffPiiiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD R0, R0, c[0x0][0x188], RZ ; /* 0x0000620000007a24 */
/* 0x000fe400078e02ff */
/*0070*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x002fc600078e0202 */
/*0080*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc80003f06270 */
/*0090*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x17c], P0 ; /* 0x00005f0005007a0c */
/* 0x000fda0000706670 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ I2F R2, c[0x0][0x17c] ; /* 0x00005f0000027b06 */
/* 0x000e220000201400 */
/*00c0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fc800078e00ff */
/*00d0*/ FADD R3, R3, -c[0x0][0x16c] ; /* 0x80005b0003037621 */
/* 0x000fc60000000000 */
/*00e0*/ MUFU.RCP R7, R2 ; /* 0x0000000200077308 */
/* 0x001e300000001000 */
/*00f0*/ FCHK P0, R3, R2 ; /* 0x0000000203007302 */
/* 0x000e620000000000 */
/*0100*/ FFMA R4, -R2, R7, 1 ; /* 0x3f80000002047423 */
/* 0x001fc80000000107 */
/*0110*/ FFMA R4, R7, R4, R7 ; /* 0x0000000407047223 */
/* 0x000fc80000000007 */
/*0120*/ FFMA R7, R3, R4, RZ ; /* 0x0000000403077223 */
/* 0x000fc800000000ff */
/*0130*/ FFMA R6, -R2, R7, R3 ; /* 0x0000000702067223 */
/* 0x000fc80000000103 */
/*0140*/ FFMA R4, R4, R6, R7 ; /* 0x0000000604047223 */
/* 0x000fe20000000007 */
/*0150*/ @!P0 BRA 0x1b0 ; /* 0x0000005000008947 */
/* 0x002fea0003800000 */
/*0160*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0003 */
/*0170*/ MOV R4, 0x1a0 ; /* 0x000001a000047802 */
/* 0x000fe20000000f00 */
/*0180*/ IMAD.MOV.U32 R10, RZ, RZ, R2 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0002 */
/*0190*/ CALL.REL.NOINC 0xa60 ; /* 0x000008c000007944 */
/* 0x000fea0003c00000 */
/*01a0*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0008 */
/*01b0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff067624 */
/* 0x000fe200078e00ff */
/*01c0*/ I2F R3, R5 ; /* 0x0000000500037306 */
/* 0x0000680000201400 */
/*01d0*/ ISETP.GE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fda0003f06270 */
/*01e0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*01f0*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x180], PT ; /* 0x00006000ff007a0c */
/* 0x003fe20003f01270 */
/*0200*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0210*/ FFMA R3, R3, R4, c[0x0][0x16c] ; /* 0x00005b0003037623 */
/* 0x000fe40000000004 */
/*0220*/ IMAD R2, R5, c[0x0][0x184], R0 ; /* 0x0000610005027a24 */
/* 0x000fd200078e0200 */
/*0230*/ @P0 BRA 0x790 ; /* 0x0000055000000947 */
/* 0x000fea0003800000 */
/*0240*/ IADD3 R3, R6.reuse, -0x1, RZ ; /* 0xffffffff06037810 */
/* 0x040fe20007ffe0ff */
/*0250*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0260*/ LOP3.LUT R4, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306047812 */
/* 0x000fe400078ec0ff */
/*0270*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fda0003f06070 */
/*0280*/ @!P0 BRA 0x6a0 ; /* 0x0000041000008947 */
/* 0x000fea0003800000 */
/*0290*/ IADD3 R6, -R4, c[0x0][0x188], RZ ; /* 0x0000620004067a10 */
/* 0x000fe20007ffe1ff */
/*02a0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*02b0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*02c0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f04270 */
/*02d0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fd800078e0203 */
/*02e0*/ @!P0 BRA 0x5e0 ; /* 0x000002f000008947 */
/* 0x000fea0003800000 */
/*02f0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0300*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0310*/ @!P1 BRA 0x4b0 ; /* 0x0000019000009947 */
/* 0x000fea0003800000 */
/*0320*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0330*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fe20007ffe0ff */
/*0340*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe2000fffe03f */
/*0350*/ IADD3 R7, P2, R2, 0x40, RZ ; /* 0x0000004002077810 */
/* 0x000fe20007f5e0ff */
/*0360*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101906 */
/*0370*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fc60003f24270 */
/*0380*/ IMAD.X R8, RZ, RZ, R3, P2 ; /* 0x000000ffff087224 */
/* 0x000fe200010e0603 */
/*0390*/ STG.E [R2.64+0x4], RZ ; /* 0x000004ff02007986 */
/* 0x000fe8000c101906 */
/*03a0*/ STG.E [R2.64+0x8], RZ ; /* 0x000008ff02007986 */
/* 0x000fe8000c101906 */
/*03b0*/ STG.E [R2.64+0xc], RZ ; /* 0x00000cff02007986 */
/* 0x000fe8000c101906 */
/*03c0*/ STG.E [R2.64+0x10], RZ ; /* 0x000010ff02007986 */
/* 0x000fe8000c101906 */
/*03d0*/ STG.E [R2.64+0x14], RZ ; /* 0x000014ff02007986 */
/* 0x000fe8000c101906 */
/*03e0*/ STG.E [R2.64+0x18], RZ ; /* 0x000018ff02007986 */
/* 0x000fe8000c101906 */
/*03f0*/ STG.E [R2.64+0x1c], RZ ; /* 0x00001cff02007986 */
/* 0x000fe8000c101906 */
/*0400*/ STG.E [R2.64+0x20], RZ ; /* 0x000020ff02007986 */
/* 0x000fe8000c101906 */
/*0410*/ STG.E [R2.64+0x24], RZ ; /* 0x000024ff02007986 */
/* 0x000fe8000c101906 */
/*0420*/ STG.E [R2.64+0x28], RZ ; /* 0x000028ff02007986 */
/* 0x000fe8000c101906 */
/*0430*/ STG.E [R2.64+0x2c], RZ ; /* 0x00002cff02007986 */
/* 0x000fe8000c101906 */
/*0440*/ STG.E [R2.64+0x30], RZ ; /* 0x000030ff02007986 */
/* 0x000fe8000c101906 */
/*0450*/ STG.E [R2.64+0x34], RZ ; /* 0x000034ff02007986 */
/* 0x000fe8000c101906 */
/*0460*/ STG.E [R2.64+0x38], RZ ; /* 0x000038ff02007986 */
/* 0x000fe8000c101906 */
/*0470*/ STG.E [R2.64+0x3c], RZ ; /* 0x00003cff02007986 */
/* 0x0001e4000c101906 */
/*0480*/ IMAD.MOV.U32 R2, RZ, RZ, R7 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0007 */
/*0490*/ IMAD.MOV.U32 R3, RZ, RZ, R8 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0008 */
/*04a0*/ @P1 BRA 0x330 ; /* 0xfffffe8000001947 */
/* 0x000fea000383ffff */
/*04b0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*04c0*/ @!P1 BRA 0x5c0 ; /* 0x000000f000009947 */
/* 0x000fea0003800000 */
/*04d0*/ IADD3 R7, P1, R2, 0x20, RZ ; /* 0x0000002002077810 */
/* 0x000fe20007f3e0ff */
/*04e0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101906 */
/*04f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0500*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0510*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0520*/ IMAD.X R8, RZ, RZ, R3, P1 ; /* 0x000000ffff087224 */
/* 0x000fe200008e0603 */
/*0530*/ STG.E [R2.64+0x4], RZ ; /* 0x000004ff02007986 */
/* 0x000fe8000c101906 */
/*0540*/ STG.E [R2.64+0x8], RZ ; /* 0x000008ff02007986 */
/* 0x000fe8000c101906 */
/*0550*/ STG.E [R2.64+0xc], RZ ; /* 0x00000cff02007986 */
/* 0x000fe8000c101906 */
/*0560*/ STG.E [R2.64+0x10], RZ ; /* 0x000010ff02007986 */
/* 0x000fe8000c101906 */
/*0570*/ STG.E [R2.64+0x14], RZ ; /* 0x000014ff02007986 */
/* 0x000fe8000c101906 */
/*0580*/ STG.E [R2.64+0x18], RZ ; /* 0x000018ff02007986 */
/* 0x000fe8000c101906 */
/*0590*/ STG.E [R2.64+0x1c], RZ ; /* 0x00001cff02007986 */
/* 0x0001e4000c101906 */
/*05a0*/ IMAD.MOV.U32 R2, RZ, RZ, R7 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0007 */
/*05b0*/ IMAD.MOV.U32 R3, RZ, RZ, R8 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0008 */
/*05c0*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*05d0*/ @!P0 BRA 0x6a0 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*05e0*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fe20007ffe0ff */
/*05f0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0600*/ IADD3 R7, P1, R2, 0x10, RZ ; /* 0x0000001002077810 */
/* 0x000fe20007f3e0ff */
/*0610*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101906 */
/*0620*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc60003f05270 */
/*0630*/ IMAD.X R8, RZ, RZ, R3, P1 ; /* 0x000000ffff087224 */
/* 0x000fe200008e0603 */
/*0640*/ STG.E [R2.64+0x4], RZ ; /* 0x000004ff02007986 */
/* 0x000fe8000c101906 */
/*0650*/ STG.E [R2.64+0x8], RZ ; /* 0x000008ff02007986 */
/* 0x000fe8000c101906 */
/*0660*/ STG.E [R2.64+0xc], RZ ; /* 0x00000cff02007986 */
/* 0x0001e4000c101906 */
/*0670*/ IMAD.MOV.U32 R2, RZ, RZ, R7 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0007 */
/*0680*/ IMAD.MOV.U32 R3, RZ, RZ, R8 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0008 */
/*0690*/ @P0 BRA 0x5e0 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*06a0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*06b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*06c0*/ IADD3 R0, R0, UR4, RZ ; /* 0x0000000400007c10 */
/* 0x000fe2000fffe0ff */
/*06d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*06e0*/ IMAD R0, R5, c[0x0][0x184], R0 ; /* 0x0000610005007a24 */
/* 0x000fc800078e0200 */
/*06f0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fc800078e0203 */
/*0700*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe20007ffe0ff */
/*0710*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e2000c101906 */
/*0720*/ IADD3 R0, P1, R2, 0x4, RZ ; /* 0x0000000402007810 */
/* 0x000fe40007f3e0ff */
/*0730*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*0740*/ IMAD.X R5, RZ, RZ, R3, P1 ; /* 0x000000ffff057224 */
/* 0x000fd400008e0603 */
/*0750*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0760*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x001fe400078e0000 */
/*0770*/ IMAD.MOV.U32 R3, RZ, RZ, R5 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0005 */
/*0780*/ BRA 0x700 ; /* 0xffffff7000007947 */
/* 0x000fea000383ffff */
/*0790*/ I2F R5, c[0x0][0x178] ; /* 0x00005e0000057b06 */
/* 0x000e220000201400 */
/*07a0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff047624 */
/* 0x000fc800078e00ff */
/*07b0*/ FADD R4, R4, -c[0x0][0x168] ; /* 0x80005a0004047621 */
/* 0x000fc60000000000 */
/*07c0*/ MUFU.RCP R6, R5 ; /* 0x0000000500067308 */
/* 0x001e300000001000 */
/*07d0*/ FCHK P0, R4, R5 ; /* 0x0000000504007302 */
/* 0x000e620000000000 */
/*07e0*/ FFMA R7, -R5, R6, 1 ; /* 0x3f80000005077423 */
/* 0x001fc80000000106 */
/*07f0*/ FFMA R7, R6, R7, R6 ; /* 0x0000000706077223 */
/* 0x000fc80000000006 */
/*0800*/ FFMA R6, R4, R7, RZ ; /* 0x0000000704067223 */
/* 0x000fc800000000ff */
/*0810*/ FFMA R8, -R5, R6, R4 ; /* 0x0000000605087223 */
/* 0x000fc80000000104 */
/*0820*/ FFMA R6, R7, R8, R6 ; /* 0x0000000807067223 */
/* 0x000fe20000000006 */
/*0830*/ @!P0 BRA 0x890 ; /* 0x0000005000008947 */
/* 0x002fea0003800000 */
/*0840*/ IMAD.MOV.U32 R9, RZ, RZ, R4 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0004 */
/*0850*/ MOV R4, 0x880 ; /* 0x0000088000047802 */
/* 0x000fe20000000f00 */
/*0860*/ IMAD.MOV.U32 R10, RZ, RZ, R5 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0005 */
/*0870*/ CALL.REL.NOINC 0xa60 ; /* 0x000001e000007944 */
/* 0x000fea0003c00000 */
/*0880*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0008 */
/*0890*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fca00078e00ff */
/*08a0*/ IMAD.IADD R4, R0, 0x1, R7.reuse ; /* 0x0000000100047824 */
/* 0x101fe200078e0207 */
/*08b0*/ BSSY B0, 0xa10 ; /* 0x0000015000007945 */
/* 0x000fe20003800000 */
/*08c0*/ IMAD.IADD R11, R2, 0x1, R7 ; /* 0x00000001020b7824 */
/* 0x000fe200078e0207 */
/*08d0*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe20007ffe0ff */
/*08e0*/ I2F R5, R4 ; /* 0x0000000400057306 */
/* 0x000e220000201400 */
/*08f0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe400078e00ff */
/*0900*/ ISETP.GE.AND P1, PT, R7, c[0x0][0x188], PT ; /* 0x0000620007007a0c */
/* 0x000fe20003f26270 */
/*0910*/ IMAD.MOV.U32 R8, RZ, RZ, R3 ; /* 0x000000ffff087224 */
/* 0x000fc400078e0003 */
/*0920*/ FFMA R10, R5, R6, c[0x0][0x168] ; /* 0x00005a00050a7623 */
/* 0x001fc80000000006 */
/*0930*/ IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff057224 */
/* 0x000fe400078e000a */
/*0940*/ FMUL R12, R8, R8 ; /* 0x00000008080c7220 */
/* 0x000fe40000400000 */
/*0950*/ FMUL R13, R5, R5 ; /* 0x00000005050d7220 */
/* 0x000fc80000400000 */
/*0960*/ FADD R4, R12, R13 ; /* 0x0000000d0c047221 */
/* 0x000fca0000000000 */
/*0970*/ FSETP.GT.AND P0, PT, R4, 4, PT ; /* 0x408000000400780b */
/* 0x000fda0003f04000 */
/*0980*/ @P0 BRA 0xa00 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0990*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fe20007ffe0ff */
/*09a0*/ FADD R4, R5, R5 ; /* 0x0000000505047221 */
/* 0x000fe40000000000 */
/*09b0*/ FADD R5, -R12, R13 ; /* 0x0000000d0c057221 */
/* 0x000fe20000000100 */
/*09c0*/ ISETP.GE.AND P0, PT, R9, c[0x0][0x180], PT ; /* 0x0000600009007a0c */
/* 0x000fe20003f06270 */
/*09d0*/ FFMA R8, R4, R8, R3 ; /* 0x0000000804087223 */
/* 0x000fe40000000003 */
/*09e0*/ FADD R5, R10, R5 ; /* 0x000000050a057221 */
/* 0x000fd40000000000 */
/*09f0*/ @!P0 BRA 0x940 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0a00*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0a10*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*0a20*/ IMAD.WIDE R4, R11, R4, c[0x0][0x170] ; /* 0x00005c000b047625 */
/* 0x000fca00078e0204 */
/*0a30*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e2000c101906 */
/*0a40*/ @!P1 BRA 0x8a0 ; /* 0xfffffe5000009947 */
/* 0x000fea000383ffff */
/*0a50*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a60*/ SHF.R.U32.HI R7, RZ, 0x17, R10.reuse ; /* 0x00000017ff077819 */
/* 0x100fe4000001160a */
/*0a70*/ SHF.R.U32.HI R6, RZ, 0x17, R9.reuse ; /* 0x00000017ff067819 */
/* 0x100fe40000011609 */
/*0a80*/ LOP3.LUT R14, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff070e7812 */
/* 0x000fe200078ec0ff */
/*0a90*/ IMAD.MOV.U32 R7, RZ, RZ, R10 ; /* 0x000000ffff077224 */
/* 0x000fe200078e000a */
/*0aa0*/ LOP3.LUT R12, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff060c7812 */
/* 0x000fe200078ec0ff */
/*0ab0*/ IMAD.MOV.U32 R6, RZ, RZ, R9 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0009 */
/*0ac0*/ IADD3 R13, R14, -0x1, RZ ; /* 0xffffffff0e0d7810 */
/* 0x000fe40007ffe0ff */
/*0ad0*/ IADD3 R11, R12, -0x1, RZ ; /* 0xffffffff0c0b7810 */
/* 0x000fc40007ffe0ff */
/*0ae0*/ ISETP.GT.U32.AND P0, PT, R13, 0xfd, PT ; /* 0x000000fd0d00780c */
/* 0x000fc80003f04070 */
/*0af0*/ ISETP.GT.U32.OR P0, PT, R11, 0xfd, P0 ; /* 0x000000fd0b00780c */
/* 0x000fda0000704470 */
/*0b00*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff088224 */
/* 0x000fe200078e00ff */
/*0b10*/ @!P0 BRA 0xc90 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0b20*/ FSETP.GTU.FTZ.AND P0, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fe40003f1c200 */
/*0b30*/ FSETP.GTU.FTZ.AND P1, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fc80003f3c200 */
/*0b40*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0b50*/ @P0 BRA 0x1070 ; /* 0x0000051000000947 */
/* 0x000fea0003800000 */
/*0b60*/ LOP3.LUT P0, RZ, R7, 0x7fffffff, R6, 0xc8, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fda000780c806 */
/*0b70*/ @!P0 BRA 0x1050 ; /* 0x000004d000008947 */
/* 0x000fea0003800000 */
/*0b80*/ FSETP.NEU.FTZ.AND P2, PT, |R9|.reuse, +INF , PT ; /* 0x7f8000000900780b */
/* 0x040fe40003f5d200 */
/*0b90*/ FSETP.NEU.FTZ.AND P1, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fe40003f3d200 */
/*0ba0*/ FSETP.NEU.FTZ.AND P0, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fd60003f1d200 */
/*0bb0*/ @!P1 BRA !P2, 0x1050 ; /* 0x0000049000009947 */
/* 0x000fea0005000000 */
/*0bc0*/ LOP3.LUT P2, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fc8000784c0ff */
/*0bd0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0be0*/ @P1 BRA 0x1030 ; /* 0x0000044000001947 */
/* 0x000fea0003800000 */
/*0bf0*/ LOP3.LUT P1, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000782c0ff */
/*0c00*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0c10*/ @P0 BRA 0x1000 ; /* 0x000003e000000947 */
/* 0x000fea0003800000 */
/*0c20*/ ISETP.GE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f06270 */
/*0c30*/ ISETP.GE.AND P1, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fd60003f26270 */
/*0c40*/ @P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff080224 */
/* 0x000fe400078e00ff */
/*0c50*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, -0x40 ; /* 0xffffffc0ff088424 */
/* 0x000fe400078e00ff */
/*0c60*/ @!P0 FFMA R6, R9, 1.84467440737095516160e+19, RZ ; /* 0x5f80000009068823 */
/* 0x000fe400000000ff */
/*0c70*/ @!P1 FFMA R7, R10, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000a079823 */
/* 0x000fe200000000ff */
/*0c80*/ @!P1 IADD3 R8, R8, 0x40, RZ ; /* 0x0000004008089810 */
/* 0x000fe40007ffe0ff */
/*0c90*/ LEA R10, R14, 0xc0800000, 0x17 ; /* 0xc08000000e0a7811 */
/* 0x000fca00078eb8ff */
/*0ca0*/ IMAD.IADD R10, R7, 0x1, -R10 ; /* 0x00000001070a7824 */
/* 0x000fe200078e0a0a */
/*0cb0*/ IADD3 R7, R12, -0x7f, RZ ; /* 0xffffff810c077810 */
/* 0x000fc60007ffe0ff */
/*0cc0*/ MUFU.RCP R9, R10 ; /* 0x0000000a00097308 */
/* 0x000e220000001000 */
/*0cd0*/ FADD.FTZ R11, -R10, -RZ ; /* 0x800000ff0a0b7221 */
/* 0x000fe40000010100 */
/*0ce0*/ IMAD R6, R7, -0x800000, R6 ; /* 0xff80000007067824 */
/* 0x000fe400078e0206 */
/*0cf0*/ FFMA R12, R9, R11, 1 ; /* 0x3f800000090c7423 */
/* 0x001fc8000000000b */
/*0d00*/ FFMA R13, R9, R12, R9 ; /* 0x0000000c090d7223 */
/* 0x000fc80000000009 */
/*0d10*/ FFMA R9, R6, R13, RZ ; /* 0x0000000d06097223 */
/* 0x000fc800000000ff */
/*0d20*/ FFMA R12, R11, R9, R6 ; /* 0x000000090b0c7223 */
/* 0x000fc80000000006 */
/*0d30*/ FFMA R12, R13, R12, R9 ; /* 0x0000000c0d0c7223 */
/* 0x000fe20000000009 */
/*0d40*/ IADD3 R9, R7, 0x7f, -R14 ; /* 0x0000007f07097810 */
/* 0x000fc60007ffe80e */
/*0d50*/ FFMA R11, R11, R12, R6 ; /* 0x0000000c0b0b7223 */
/* 0x000fe40000000006 */
/*0d60*/ IMAD.IADD R9, R9, 0x1, R8 ; /* 0x0000000109097824 */
/* 0x000fe400078e0208 */
/*0d70*/ FFMA R6, R13, R11, R12 ; /* 0x0000000b0d067223 */
/* 0x000fca000000000c */
/*0d80*/ SHF.R.U32.HI R7, RZ, 0x17, R6 ; /* 0x00000017ff077819 */
/* 0x000fc80000011606 */
/*0d90*/ LOP3.LUT R7, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07077812 */
/* 0x000fca00078ec0ff */
/*0da0*/ IMAD.IADD R14, R7, 0x1, R9 ; /* 0x00000001070e7824 */
/* 0x000fca00078e0209 */
/*0db0*/ IADD3 R7, R14, -0x1, RZ ; /* 0xffffffff0e077810 */
/* 0x000fc80007ffe0ff */
/*0dc0*/ ISETP.GE.U32.AND P0, PT, R7, 0xfe, PT ; /* 0x000000fe0700780c */
/* 0x000fda0003f06070 */
/*0dd0*/ @!P0 BRA 0xfe0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0de0*/ ISETP.GT.AND P0, PT, R14, 0xfe, PT ; /* 0x000000fe0e00780c */
/* 0x000fda0003f04270 */
/*0df0*/ @P0 BRA 0xfb0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0e00*/ ISETP.GE.AND P0, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fda0003f06270 */
/*0e10*/ @P0 BRA 0x1080 ; /* 0x0000026000000947 */
/* 0x000fea0003800000 */
/*0e20*/ ISETP.GE.AND P0, PT, R14, -0x18, PT ; /* 0xffffffe80e00780c */
/* 0x000fe40003f06270 */
/*0e30*/ LOP3.LUT R6, R6, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000006067812 */
/* 0x000fd600078ec0ff */
/*0e40*/ @!P0 BRA 0x1080 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*0e50*/ FFMA.RZ R7, R13.reuse, R11.reuse, R12.reuse ; /* 0x0000000b0d077223 */
/* 0x1c0fe2000000c00c */
/*0e60*/ IADD3 R10, R14.reuse, 0x20, RZ ; /* 0x000000200e0a7810 */
/* 0x040fe20007ffe0ff */
/*0e70*/ FFMA.RM R8, R13, R11.reuse, R12.reuse ; /* 0x0000000b0d087223 */
/* 0x180fe2000000400c */
/*0e80*/ ISETP.NE.AND P2, PT, R14.reuse, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x040fe40003f45270 */
/*0e90*/ LOP3.LUT R9, R7, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff07097812 */
/* 0x000fe200078ec0ff */
/*0ea0*/ FFMA.RP R7, R13, R11, R12 ; /* 0x0000000b0d077223 */
/* 0x000fe2000000800c */
/*0eb0*/ ISETP.NE.AND P1, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe20003f25270 */
/*0ec0*/ IMAD.MOV R11, RZ, RZ, -R14 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0a0e */
/*0ed0*/ LOP3.LUT R9, R9, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000009097812 */
/* 0x000fe400078efcff */
/*0ee0*/ FSETP.NEU.FTZ.AND P0, PT, R7, R8, PT ; /* 0x000000080700720b */
/* 0x000fc40003f1d000 */
/*0ef0*/ SHF.L.U32 R10, R9, R10, RZ ; /* 0x0000000a090a7219 */
/* 0x000fe400000006ff */
/*0f00*/ SEL R8, R11, RZ, P2 ; /* 0x000000ff0b087207 */
/* 0x000fe40001000000 */
/*0f10*/ ISETP.NE.AND P1, PT, R10, RZ, P1 ; /* 0x000000ff0a00720c */
/* 0x000fe40000f25270 */
/*0f20*/ SHF.R.U32.HI R8, RZ, R8, R9 ; /* 0x00000008ff087219 */
/* 0x000fe40000011609 */
/*0f30*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0f40*/ SHF.R.U32.HI R10, RZ, 0x1, R8 ; /* 0x00000001ff0a7819 */
/* 0x000fc40000011608 */
/*0f50*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fc80004000000 */
/*0f60*/ LOP3.LUT R7, R7, 0x1, R10, 0xf8, !PT ; /* 0x0000000107077812 */
/* 0x000fc800078ef80a */
/*0f70*/ LOP3.LUT R7, R7, R8, RZ, 0xc0, !PT ; /* 0x0000000807077212 */
/* 0x000fca00078ec0ff */
/*0f80*/ IMAD.IADD R7, R10, 0x1, R7 ; /* 0x000000010a077824 */
/* 0x000fca00078e0207 */
/*0f90*/ LOP3.LUT R6, R7, R6, RZ, 0xfc, !PT ; /* 0x0000000607067212 */
/* 0x000fe200078efcff */
/*0fa0*/ BRA 0x1080 ; /* 0x000000d000007947 */
/* 0x000fea0003800000 */
/*0fb0*/ LOP3.LUT R6, R6, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000006067812 */
/* 0x000fc800078ec0ff */
/*0fc0*/ LOP3.LUT R6, R6, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000006067812 */
/* 0x000fe200078efcff */
/*0fd0*/ BRA 0x1080 ; /* 0x000000a000007947 */
/* 0x000fea0003800000 */
/*0fe0*/ IMAD R6, R9, 0x800000, R6 ; /* 0x0080000009067824 */
/* 0x000fe200078e0206 */
/*0ff0*/ BRA 0x1080 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*1000*/ LOP3.LUT R6, R7, 0x80000000, R6, 0x48, !PT ; /* 0x8000000007067812 */
/* 0x000fc800078e4806 */
/*1010*/ LOP3.LUT R6, R6, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000006067812 */
/* 0x000fe200078efcff */
/*1020*/ BRA 0x1080 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*1030*/ LOP3.LUT R6, R7, 0x80000000, R6, 0x48, !PT ; /* 0x8000000007067812 */
/* 0x000fe200078e4806 */
/*1040*/ BRA 0x1080 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*1050*/ MUFU.RSQ R6, -QNAN ; /* 0xffc0000000067908 */
/* 0x000e220000001400 */
/*1060*/ BRA 0x1080 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*1070*/ FADD.FTZ R6, R9, R10 ; /* 0x0000000a09067221 */
/* 0x000fc80000010000 */
/*1080*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x001fe400078e0006 */
/*1090*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0004 */
/*10a0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fc800078e00ff */
/*10b0*/ RET.REL.NODEC R6 0x0 ; /* 0xffffef4006007950 */
/* 0x000fea0003c3ffff */
/*10c0*/ BRA 0x10c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
__device__ int mandel(float c_re, float c_im, int maxIteration)
{
float z_re = c_re, z_im = c_im;
int i;
for (i = 0; i < maxIteration; ++i)
{
if (z_re * z_re + z_im * z_im > 4.f)
break;
float new_re = z_re * z_re - z_im * z_im;
float new_im = 2.f * z_re * z_im;
z_re = c_re + new_re;
z_im = c_im + new_im;
}
return i;
}
__global__ void mandelKernel(float x1, float y1, float x0, float y0, int* output, int width, int height, int maxIterations, int pitch, int pixels) {
// To avoid error caused by the floating number, use the following pseudo code
// float x = lowerX + thisX * stepX;
// float y = lowerY + thisY * stepY;
int i = (blockIdx.x * blockDim.x + threadIdx.x) * pixels;
int j = blockIdx.y * blockDim.y + threadIdx.y;
// if (i >= width || j >= height) return;
if (i >= width || j >= height) return;
// i -> 1600, j -> 1200
float dx = (x1 - x0) / width;
float dy = (y1 - y0) / height;
float y = y0 + j * dy;
for(int pixel = 0; pixel < pixels; pixel++) {
float x = x0 + (i + pixel) * dx;
int index = (j * pitch + i) + pixel;
output[index] = mandel(x, y, maxIterations);
}
}
// Host front-end function that allocates the memory and launches the GPU kernel
#define N 1600
#define BLOCK_SIZE 64
void hostFE (float x1, float y1, float x0, float y0, int* output, int width, int height, int maxIterations)
{
int *h_img = NULL, *d_img = NULL;
size_t pitch;
// Locate CPU memory and GPU memory
cudaHostAlloc((void**)&h_img, width * height * sizeof(int), cudaHostAllocDefault);
cudaMallocPitch((void**)&d_img, &pitch, (size_t)width * sizeof(int), (size_t)height);
// Copy memory from CPU to GPU
cudaMemcpy2D(d_img, pitch, h_img, width * sizeof(int), width * sizeof(int), height, cudaMemcpyHostToDevice);
//
dim3 blockSize(BLOCK_SIZE, BLOCK_SIZE);
dim3 numBlock(N / BLOCK_SIZE, N / BLOCK_SIZE);
mandelKernel<<<blockSize, numBlock>>>(x1, y1, x0, y0, d_img, width, height, maxIterations, pitch / sizeof(int), 2);
// Sync
cudaDeviceSynchronize();
// // Copy memory from GPU to CPU
cudaMemcpy2D(h_img, width * sizeof(int), d_img, pitch, width * sizeof(int), height, cudaMemcpyDeviceToHost);
// // Copy memory from CPU to CPU(answers)
memcpy(output, h_img, width * height * sizeof(int));
cudaFree(h_img);
cudaFree(d_img);
} | .file "tmpxft_0009f5e8_00000000-6_kernel3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6mandelffi
.type _Z6mandelffi, @function
_Z6mandelffi:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z6mandelffi, .-_Z6mandelffi
.globl _Z41__device_stub__Z12mandelKernelffffPiiiiiiffffPiiiiii
.type _Z41__device_stub__Z12mandelKernelffffPiiiiiiffffPiiiiii, @function
_Z41__device_stub__Z12mandelKernelffffPiiiiiiffffPiiiiii:
.LFB2083:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movss %xmm0, 44(%rsp)
movss %xmm1, 40(%rsp)
movss %xmm2, 36(%rsp)
movss %xmm3, 32(%rsp)
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 4(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12mandelKernelffffPiiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z41__device_stub__Z12mandelKernelffffPiiiiiiffffPiiiiii, .-_Z41__device_stub__Z12mandelKernelffffPiiiiiiffffPiiiiii
.globl _Z12mandelKernelffffPiiiiii
.type _Z12mandelKernelffffPiiiiii, @function
_Z12mandelKernelffffPiiiiii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z12mandelKernelffffPiiiiiiffffPiiiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z12mandelKernelffffPiiiiii, .-_Z12mandelKernelffffPiiiiii
.globl _Z6hostFEffffPiiii
.type _Z6hostFEffffPiiii, @function
_Z6hostFEffffPiiii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movss %xmm0, 12(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm2, 20(%rsp)
movss %xmm3, 24(%rsp)
movq %rdi, %r14
movl %esi, %r12d
movl %edx, %r13d
movl %ecx, 28(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq $0, 40(%rsp)
movq $0, 48(%rsp)
movl %esi, %ebp
imull %edx, %ebp
movslq %ebp, %rbp
salq $2, %rbp
leaq 40(%rsp), %rdi
movl $0, %edx
movq %rbp, %rsi
call cudaHostAlloc@PLT
movslq %r13d, %r15
movslq %r12d, %rbx
salq $2, %rbx
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdi
movq %r15, %rcx
movq %rbx, %rdx
call cudaMallocPitch@PLT
subq $8, %rsp
.cfi_def_cfa_offset 168
pushq $1
.cfi_def_cfa_offset 176
movq %r15, %r9
movq %rbx, %r8
movq %rbx, %rcx
movq 56(%rsp), %rdx
movq 72(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy2D@PLT
movl $64, 80(%rsp)
movl $64, 84(%rsp)
movl $25, 92(%rsp)
movl $25, 96(%rsp)
addq $16, %rsp
.cfi_def_cfa_offset 160
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L14:
call cudaDeviceSynchronize@PLT
subq $8, %rsp
.cfi_def_cfa_offset 168
pushq $2
.cfi_def_cfa_offset 176
movq %r15, %r9
movq %rbx, %r8
movq 72(%rsp), %rcx
movq 64(%rsp), %rdx
movq %rbx, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy2D@PLT
movq 56(%rsp), %rbx
movq %rbp, %rdx
movq %rbx, %rsi
movq %r14, %rdi
call memcpy@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
movq %rbx, %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 56(%rsp), %r8
shrq $2, %r8
movl $2, %r9d
movl 28(%rsp), %ecx
movl %r13d, %edx
movl %r12d, %esi
movq 48(%rsp), %rdi
movss 24(%rsp), %xmm3
movss 20(%rsp), %xmm2
movss 16(%rsp), %xmm1
movss 12(%rsp), %xmm0
call _Z41__device_stub__Z12mandelKernelffffPiiiiiiffffPiiiiii
jmp .L14
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z6hostFEffffPiiii, .-_Z6hostFEffffPiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12mandelKernelffffPiiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12mandelKernelffffPiiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
__device__ int mandel(float c_re, float c_im, int maxIteration)
{
float z_re = c_re, z_im = c_im;
int i;
for (i = 0; i < maxIteration; ++i)
{
if (z_re * z_re + z_im * z_im > 4.f)
break;
float new_re = z_re * z_re - z_im * z_im;
float new_im = 2.f * z_re * z_im;
z_re = c_re + new_re;
z_im = c_im + new_im;
}
return i;
}
__global__ void mandelKernel(float x1, float y1, float x0, float y0, int* output, int width, int height, int maxIterations, int pitch, int pixels) {
// To avoid error caused by the floating number, use the following pseudo code
// float x = lowerX + thisX * stepX;
// float y = lowerY + thisY * stepY;
int i = (blockIdx.x * blockDim.x + threadIdx.x) * pixels;
int j = blockIdx.y * blockDim.y + threadIdx.y;
// if (i >= width || j >= height) return;
if (i >= width || j >= height) return;
// i -> 1600, j -> 1200
float dx = (x1 - x0) / width;
float dy = (y1 - y0) / height;
float y = y0 + j * dy;
for(int pixel = 0; pixel < pixels; pixel++) {
float x = x0 + (i + pixel) * dx;
int index = (j * pitch + i) + pixel;
output[index] = mandel(x, y, maxIterations);
}
}
// Host front-end function that allocates the memory and launches the GPU kernel
#define N 1600
#define BLOCK_SIZE 64
void hostFE (float x1, float y1, float x0, float y0, int* output, int width, int height, int maxIterations)
{
int *h_img = NULL, *d_img = NULL;
size_t pitch;
// Locate CPU memory and GPU memory
cudaHostAlloc((void**)&h_img, width * height * sizeof(int), cudaHostAllocDefault);
cudaMallocPitch((void**)&d_img, &pitch, (size_t)width * sizeof(int), (size_t)height);
// Copy memory from CPU to GPU
cudaMemcpy2D(d_img, pitch, h_img, width * sizeof(int), width * sizeof(int), height, cudaMemcpyHostToDevice);
//
dim3 blockSize(BLOCK_SIZE, BLOCK_SIZE);
dim3 numBlock(N / BLOCK_SIZE, N / BLOCK_SIZE);
mandelKernel<<<blockSize, numBlock>>>(x1, y1, x0, y0, d_img, width, height, maxIterations, pitch / sizeof(int), 2);
// Sync
cudaDeviceSynchronize();
// // Copy memory from GPU to CPU
cudaMemcpy2D(h_img, width * sizeof(int), d_img, pitch, width * sizeof(int), height, cudaMemcpyDeviceToHost);
// // Copy memory from CPU to CPU(answers)
memcpy(output, h_img, width * height * sizeof(int));
cudaFree(h_img);
cudaFree(d_img);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__device__ int mandel(float c_re, float c_im, int maxIteration)
{
float z_re = c_re, z_im = c_im;
int i;
for (i = 0; i < maxIteration; ++i)
{
if (z_re * z_re + z_im * z_im > 4.f)
break;
float new_re = z_re * z_re - z_im * z_im;
float new_im = 2.f * z_re * z_im;
z_re = c_re + new_re;
z_im = c_im + new_im;
}
return i;
}
__global__ void mandelKernel(float x1, float y1, float x0, float y0, int* output, int width, int height, int maxIterations, int pitch, int pixels) {
// To avoid error caused by the floating number, use the following pseudo code
// float x = lowerX + thisX * stepX;
// float y = lowerY + thisY * stepY;
int i = (blockIdx.x * blockDim.x + threadIdx.x) * pixels;
int j = blockIdx.y * blockDim.y + threadIdx.y;
// if (i >= width || j >= height) return;
if (i >= width || j >= height) return;
// i -> 1600, j -> 1200
float dx = (x1 - x0) / width;
float dy = (y1 - y0) / height;
float y = y0 + j * dy;
for(int pixel = 0; pixel < pixels; pixel++) {
float x = x0 + (i + pixel) * dx;
int index = (j * pitch + i) + pixel;
output[index] = mandel(x, y, maxIterations);
}
}
// Host front-end function that allocates the memory and launches the GPU kernel
#define N 1600
#define BLOCK_SIZE 64
void hostFE (float x1, float y1, float x0, float y0, int* output, int width, int height, int maxIterations)
{
int *h_img = NULL, *d_img = NULL;
size_t pitch;
// Locate CPU memory and GPU memory
hipHostAlloc((void**)&h_img, width * height * sizeof(int), hipHostMallocDefault);
hipMallocPitch((void**)&d_img, &pitch, (size_t)width * sizeof(int), (size_t)height);
// Copy memory from CPU to GPU
hipMemcpy2D(d_img, pitch, h_img, width * sizeof(int), width * sizeof(int), height, hipMemcpyHostToDevice);
//
dim3 blockSize(BLOCK_SIZE, BLOCK_SIZE);
dim3 numBlock(N / BLOCK_SIZE, N / BLOCK_SIZE);
mandelKernel<<<blockSize, numBlock>>>(x1, y1, x0, y0, d_img, width, height, maxIterations, pitch / sizeof(int), 2);
// Sync
hipDeviceSynchronize();
// // Copy memory from GPU to CPU
hipMemcpy2D(h_img, width * sizeof(int), d_img, pitch, width * sizeof(int), height, hipMemcpyDeviceToHost);
// // Copy memory from CPU to CPU(answers)
memcpy(output, h_img, width * height * sizeof(int));
hipFree(h_img);
hipFree(d_img);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__device__ int mandel(float c_re, float c_im, int maxIteration)
{
float z_re = c_re, z_im = c_im;
int i;
for (i = 0; i < maxIteration; ++i)
{
if (z_re * z_re + z_im * z_im > 4.f)
break;
float new_re = z_re * z_re - z_im * z_im;
float new_im = 2.f * z_re * z_im;
z_re = c_re + new_re;
z_im = c_im + new_im;
}
return i;
}
__global__ void mandelKernel(float x1, float y1, float x0, float y0, int* output, int width, int height, int maxIterations, int pitch, int pixels) {
// To avoid error caused by the floating number, use the following pseudo code
// float x = lowerX + thisX * stepX;
// float y = lowerY + thisY * stepY;
int i = (blockIdx.x * blockDim.x + threadIdx.x) * pixels;
int j = blockIdx.y * blockDim.y + threadIdx.y;
// if (i >= width || j >= height) return;
if (i >= width || j >= height) return;
// i -> 1600, j -> 1200
float dx = (x1 - x0) / width;
float dy = (y1 - y0) / height;
float y = y0 + j * dy;
for(int pixel = 0; pixel < pixels; pixel++) {
float x = x0 + (i + pixel) * dx;
int index = (j * pitch + i) + pixel;
output[index] = mandel(x, y, maxIterations);
}
}
// Host front-end function that allocates the memory and launches the GPU kernel
#define N 1600
#define BLOCK_SIZE 64
void hostFE (float x1, float y1, float x0, float y0, int* output, int width, int height, int maxIterations)
{
int *h_img = NULL, *d_img = NULL;
size_t pitch;
// Locate CPU memory and GPU memory
hipHostAlloc((void**)&h_img, width * height * sizeof(int), hipHostMallocDefault);
hipMallocPitch((void**)&d_img, &pitch, (size_t)width * sizeof(int), (size_t)height);
// Copy memory from CPU to GPU
hipMemcpy2D(d_img, pitch, h_img, width * sizeof(int), width * sizeof(int), height, hipMemcpyHostToDevice);
//
dim3 blockSize(BLOCK_SIZE, BLOCK_SIZE);
dim3 numBlock(N / BLOCK_SIZE, N / BLOCK_SIZE);
mandelKernel<<<blockSize, numBlock>>>(x1, y1, x0, y0, d_img, width, height, maxIterations, pitch / sizeof(int), 2);
// Sync
hipDeviceSynchronize();
// // Copy memory from GPU to CPU
hipMemcpy2D(h_img, width * sizeof(int), d_img, pitch, width * sizeof(int), height, hipMemcpyDeviceToHost);
// // Copy memory from CPU to CPU(answers)
memcpy(output, h_img, width * height * sizeof(int));
hipFree(h_img);
hipFree(d_img);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12mandelKernelffffPiiiiii
.globl _Z12mandelKernelffffPiiiiii
.p2align 8
.type _Z12mandelKernelffffPiiiiii,@function
_Z12mandelKernelffffPiiiiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s3, s[0:1], 0x28
v_and_b32_e32 v1, 0x3ff, v0
s_load_b64 s[8:9], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s4, v[1:2]
v_bfe_u32 v1, v0, 10, 10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v0, v2, s3
v_mad_u64_u32 v[3:4], null, s15, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s8, v0
v_cmp_gt_i32_e64 s2, s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_11
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_11
s_clause 0x1
s_load_b64 s[10:11], s[0:1], 0x0
s_load_b128 s[4:7], s[0:1], 0x8
v_cvt_f32_i32_e32 v4, s8
v_cvt_f32_i32_e32 v1, s9
s_load_b64 s[0:1], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
v_sub_f32_e64 v5, s10, s4
v_sub_f32_e64 v2, s11, s5
s_cmp_gt_i32 s0, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_scale_f32 v6, null, v4, v4, v5
v_div_scale_f32 v7, null, v1, v1, v2
v_div_scale_f32 v12, vcc_lo, v5, v4, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v8, v6
v_rcp_f32_e32 v9, v7
s_waitcnt_depctr 0xfff
v_fma_f32 v10, -v6, v8, 1.0
v_fma_f32 v11, -v7, v9, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_fmac_f32 v8, v10, v8 :: v_dual_fmac_f32 v9, v11, v9
v_div_scale_f32 v10, s2, v2, v1, v2
v_mul_f32_e32 v11, v12, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v13, v10, v9
v_fma_f32 v14, -v6, v11, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v15, -v7, v13, v10
v_fmac_f32_e32 v11, v14, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v13, v15, v9
v_fma_f32 v6, -v6, v11, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v7, -v7, v13, v10
v_div_fmas_f32 v6, v6, v8, v11
s_mov_b32 vcc_lo, s2
v_cvt_f32_i32_e32 v8, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_div_fmas_f32 v7, v7, v9, v13
s_mov_b32 s2, 0
v_div_fixup_f32 v7, v7, v1, v2
v_mad_u64_u32 v[1:2], null, v3, s1, v[0:1]
v_div_fixup_f32 v2, v6, v4, v5
s_cselect_b32 s1, -1, 0
s_delay_alu instid0(VALU_DEP_3)
v_fma_f32 v3, v7, v8, s5
s_branch .LBB0_5
.LBB0_3:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s5
.LBB0_4:
v_add_nc_u32_e32 v4, s2, v1
s_add_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s2, s3
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_u32 v4, vcc_lo, s6, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
global_store_b32 v[4:5], v6, off
s_cbranch_scc0 .LBB0_11
.LBB0_5:
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_dual_mov_b32 v5, v3 :: v_dual_add_nc_u32 v4, s2, v0
s_mov_b32 s5, 0
s_mov_b32 s8, 0
v_cvt_f32_i32_e32 v4, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, v2, v4, s4
v_mov_b32_e32 v7, v4
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_8
.p2align 6
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s10, exec_lo, s9
s_or_b32 s5, s10, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execz .LBB0_3
.LBB0_8:
v_mul_f32_e32 v8, v5, v5
s_or_b32 s9, s9, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, v7, v7, v8
v_cmp_nlt_f32_e32 vcc_lo, 4.0, v6
v_mov_b32_e32 v6, s8
s_and_saveexec_b32 s10, vcc_lo
s_cbranch_execz .LBB0_7
v_mul_f32_e32 v6, v7, v7
v_add_f32_e32 v7, v7, v7
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s0, s8
v_sub_f32_e32 v8, v6, v8
s_cselect_b32 s11, -1, 0
v_mov_b32_e32 v6, s0
v_fma_f32 v5, v5, v7, v3
s_and_not1_b32 s9, s9, exec_lo
v_add_f32_e32 v7, v4, v8
s_and_b32 s11, s11, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s9, s9, s11
s_branch .LBB0_7
.LBB0_10:
v_mov_b32_e32 v6, 0
s_branch .LBB0_4
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12mandelKernelffffPiiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12mandelKernelffffPiiiiii, .Lfunc_end0-_Z12mandelKernelffffPiiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12mandelKernelffffPiiiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12mandelKernelffffPiiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__device__ int mandel(float c_re, float c_im, int maxIteration)
{
float z_re = c_re, z_im = c_im;
int i;
for (i = 0; i < maxIteration; ++i)
{
if (z_re * z_re + z_im * z_im > 4.f)
break;
float new_re = z_re * z_re - z_im * z_im;
float new_im = 2.f * z_re * z_im;
z_re = c_re + new_re;
z_im = c_im + new_im;
}
return i;
}
__global__ void mandelKernel(float x1, float y1, float x0, float y0, int* output, int width, int height, int maxIterations, int pitch, int pixels) {
// To avoid error caused by the floating number, use the following pseudo code
// float x = lowerX + thisX * stepX;
// float y = lowerY + thisY * stepY;
int i = (blockIdx.x * blockDim.x + threadIdx.x) * pixels;
int j = blockIdx.y * blockDim.y + threadIdx.y;
// if (i >= width || j >= height) return;
if (i >= width || j >= height) return;
// i -> 1600, j -> 1200
float dx = (x1 - x0) / width;
float dy = (y1 - y0) / height;
float y = y0 + j * dy;
for(int pixel = 0; pixel < pixels; pixel++) {
float x = x0 + (i + pixel) * dx;
int index = (j * pitch + i) + pixel;
output[index] = mandel(x, y, maxIterations);
}
}
// Host front-end function that allocates the memory and launches the GPU kernel
#define N 1600
#define BLOCK_SIZE 64
void hostFE (float x1, float y1, float x0, float y0, int* output, int width, int height, int maxIterations)
{
int *h_img = NULL, *d_img = NULL;
size_t pitch;
// Locate CPU memory and GPU memory
hipHostAlloc((void**)&h_img, width * height * sizeof(int), hipHostMallocDefault);
hipMallocPitch((void**)&d_img, &pitch, (size_t)width * sizeof(int), (size_t)height);
// Copy memory from CPU to GPU
hipMemcpy2D(d_img, pitch, h_img, width * sizeof(int), width * sizeof(int), height, hipMemcpyHostToDevice);
//
dim3 blockSize(BLOCK_SIZE, BLOCK_SIZE);
dim3 numBlock(N / BLOCK_SIZE, N / BLOCK_SIZE);
mandelKernel<<<blockSize, numBlock>>>(x1, y1, x0, y0, d_img, width, height, maxIterations, pitch / sizeof(int), 2);
// Sync
hipDeviceSynchronize();
// // Copy memory from GPU to CPU
hipMemcpy2D(h_img, width * sizeof(int), d_img, pitch, width * sizeof(int), height, hipMemcpyDeviceToHost);
// // Copy memory from CPU to CPU(answers)
memcpy(output, h_img, width * height * sizeof(int));
hipFree(h_img);
hipFree(d_img);
} | .text
.file "kernel3.hip"
.globl _Z27__device_stub__mandelKernelffffPiiiiii # -- Begin function _Z27__device_stub__mandelKernelffffPiiiiii
.p2align 4, 0x90
.type _Z27__device_stub__mandelKernelffffPiiiiii,@function
_Z27__device_stub__mandelKernelffffPiiiiii: # @_Z27__device_stub__mandelKernelffffPiiiiii
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movss %xmm0, 36(%rsp)
movss %xmm1, 32(%rsp)
movss %xmm2, 28(%rsp)
movss %xmm3, 24(%rsp)
movq %rdi, 88(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
leaq 36(%rsp), %rax
movq %rax, 96(%rsp)
leaq 32(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
leaq 4(%rsp), %rax
movq %rax, 168(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12mandelKernelffffPiiiiii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z27__device_stub__mandelKernelffffPiiiiii, .Lfunc_end0-_Z27__device_stub__mandelKernelffffPiiiiii
.cfi_endproc
# -- End function
.globl _Z6hostFEffffPiiii # -- Begin function _Z6hostFEffffPiiii
.p2align 4, 0x90
.type _Z6hostFEffffPiiii,@function
_Z6hostFEffffPiiii: # @_Z6hostFEffffPiiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movl %edx, %r13d
movl %esi, %ebx
movq %rdi, 96(%rsp) # 8-byte Spill
movss %xmm3, 56(%rsp) # 4-byte Spill
movss %xmm2, 52(%rsp) # 4-byte Spill
movss %xmm1, 48(%rsp) # 4-byte Spill
movss %xmm0, 44(%rsp) # 4-byte Spill
movq $0, 24(%rsp)
movq $0, 16(%rsp)
movl %edx, %eax
imull %esi, %eax
movslq %eax, %r14
shlq $2, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
xorl %edx, %edx
callq hipHostAlloc
movslq %ebx, %r15
shlq $2, %r15
movslq %r13d, %r12
leaq 16(%rsp), %rdi
leaq 32(%rsp), %rsi
movq %r15, %rdx
movq %r12, %rcx
callq hipMallocPitch
movq 16(%rsp), %rdi
movq 32(%rsp), %rsi
movq 24(%rsp), %rdx
movl $1, (%rsp)
movq %r15, %rcx
movq %r15, %r8
movq %r12, %r9
callq hipMemcpy2D
movabsq $274877907008, %rdi # imm = 0x4000000040
movabsq $107374182425, %rdx # imm = 0x1900000019
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 32(%rsp), %rcx
shrq $2, %rcx
movss 44(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 92(%rsp)
movss 48(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 88(%rsp)
movss 52(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 84(%rsp)
movss 56(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 80(%rsp)
movq %rax, 152(%rsp)
movl %ebx, 76(%rsp)
movl %r13d, 72(%rsp)
movl %ebp, 68(%rsp)
movl %ecx, 64(%rsp)
movl $2, 60(%rsp)
leaq 92(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rax
movq %rax, 168(%rsp)
leaq 84(%rsp), %rax
movq %rax, 176(%rsp)
leaq 80(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 76(%rsp), %rax
movq %rax, 200(%rsp)
leaq 72(%rsp), %rax
movq %rax, 208(%rsp)
leaq 68(%rsp), %rax
movq %rax, 216(%rsp)
leaq 64(%rsp), %rax
movq %rax, 224(%rsp)
leaq 60(%rsp), %rax
movq %rax, 232(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rax
movq 104(%rsp), %rdi
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
movq %rdi, 8(%rsp)
movq %rax, (%rsp)
leaq 160(%rsp), %r9
movl $_Z12mandelKernelffffPiiiiii, %edi
callq hipLaunchKernel
.LBB1_2:
callq hipDeviceSynchronize
movq 24(%rsp), %rdi
movq 16(%rsp), %rdx
movq 32(%rsp), %rcx
movl $2, (%rsp)
movq %r15, %rsi
movq %r15, %r8
movq %r12, %r9
callq hipMemcpy2D
movq 24(%rsp), %rbx
movq 96(%rsp), %rdi # 8-byte Reload
movq %rbx, %rsi
movq %r14, %rdx
callq memcpy@PLT
movq %rbx, %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z6hostFEffffPiiii, .Lfunc_end1-_Z6hostFEffffPiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12mandelKernelffffPiiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12mandelKernelffffPiiiiii,@object # @_Z12mandelKernelffffPiiiiii
.section .rodata,"a",@progbits
.globl _Z12mandelKernelffffPiiiiii
.p2align 3, 0x0
_Z12mandelKernelffffPiiiiii:
.quad _Z27__device_stub__mandelKernelffffPiiiiii
.size _Z12mandelKernelffffPiiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12mandelKernelffffPiiiiii"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__mandelKernelffffPiiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12mandelKernelffffPiiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12mandelKernelffffPiiiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD R0, R0, c[0x0][0x188], RZ ; /* 0x0000620000007a24 */
/* 0x000fe400078e02ff */
/*0070*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x002fc600078e0202 */
/*0080*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc80003f06270 */
/*0090*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x17c], P0 ; /* 0x00005f0005007a0c */
/* 0x000fda0000706670 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ I2F R2, c[0x0][0x17c] ; /* 0x00005f0000027b06 */
/* 0x000e220000201400 */
/*00c0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fc800078e00ff */
/*00d0*/ FADD R3, R3, -c[0x0][0x16c] ; /* 0x80005b0003037621 */
/* 0x000fc60000000000 */
/*00e0*/ MUFU.RCP R7, R2 ; /* 0x0000000200077308 */
/* 0x001e300000001000 */
/*00f0*/ FCHK P0, R3, R2 ; /* 0x0000000203007302 */
/* 0x000e620000000000 */
/*0100*/ FFMA R4, -R2, R7, 1 ; /* 0x3f80000002047423 */
/* 0x001fc80000000107 */
/*0110*/ FFMA R4, R7, R4, R7 ; /* 0x0000000407047223 */
/* 0x000fc80000000007 */
/*0120*/ FFMA R7, R3, R4, RZ ; /* 0x0000000403077223 */
/* 0x000fc800000000ff */
/*0130*/ FFMA R6, -R2, R7, R3 ; /* 0x0000000702067223 */
/* 0x000fc80000000103 */
/*0140*/ FFMA R4, R4, R6, R7 ; /* 0x0000000604047223 */
/* 0x000fe20000000007 */
/*0150*/ @!P0 BRA 0x1b0 ; /* 0x0000005000008947 */
/* 0x002fea0003800000 */
/*0160*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0003 */
/*0170*/ MOV R4, 0x1a0 ; /* 0x000001a000047802 */
/* 0x000fe20000000f00 */
/*0180*/ IMAD.MOV.U32 R10, RZ, RZ, R2 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0002 */
/*0190*/ CALL.REL.NOINC 0xa60 ; /* 0x000008c000007944 */
/* 0x000fea0003c00000 */
/*01a0*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0008 */
/*01b0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff067624 */
/* 0x000fe200078e00ff */
/*01c0*/ I2F R3, R5 ; /* 0x0000000500037306 */
/* 0x0000680000201400 */
/*01d0*/ ISETP.GE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fda0003f06270 */
/*01e0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*01f0*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x180], PT ; /* 0x00006000ff007a0c */
/* 0x003fe20003f01270 */
/*0200*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0210*/ FFMA R3, R3, R4, c[0x0][0x16c] ; /* 0x00005b0003037623 */
/* 0x000fe40000000004 */
/*0220*/ IMAD R2, R5, c[0x0][0x184], R0 ; /* 0x0000610005027a24 */
/* 0x000fd200078e0200 */
/*0230*/ @P0 BRA 0x790 ; /* 0x0000055000000947 */
/* 0x000fea0003800000 */
/*0240*/ IADD3 R3, R6.reuse, -0x1, RZ ; /* 0xffffffff06037810 */
/* 0x040fe20007ffe0ff */
/*0250*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0260*/ LOP3.LUT R4, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306047812 */
/* 0x000fe400078ec0ff */
/*0270*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fda0003f06070 */
/*0280*/ @!P0 BRA 0x6a0 ; /* 0x0000041000008947 */
/* 0x000fea0003800000 */
/*0290*/ IADD3 R6, -R4, c[0x0][0x188], RZ ; /* 0x0000620004067a10 */
/* 0x000fe20007ffe1ff */
/*02a0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*02b0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*02c0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f04270 */
/*02d0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fd800078e0203 */
/*02e0*/ @!P0 BRA 0x5e0 ; /* 0x000002f000008947 */
/* 0x000fea0003800000 */
/*02f0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0300*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0310*/ @!P1 BRA 0x4b0 ; /* 0x0000019000009947 */
/* 0x000fea0003800000 */
/*0320*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0330*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fe20007ffe0ff */
/*0340*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe2000fffe03f */
/*0350*/ IADD3 R7, P2, R2, 0x40, RZ ; /* 0x0000004002077810 */
/* 0x000fe20007f5e0ff */
/*0360*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101906 */
/*0370*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fc60003f24270 */
/*0380*/ IMAD.X R8, RZ, RZ, R3, P2 ; /* 0x000000ffff087224 */
/* 0x000fe200010e0603 */
/*0390*/ STG.E [R2.64+0x4], RZ ; /* 0x000004ff02007986 */
/* 0x000fe8000c101906 */
/*03a0*/ STG.E [R2.64+0x8], RZ ; /* 0x000008ff02007986 */
/* 0x000fe8000c101906 */
/*03b0*/ STG.E [R2.64+0xc], RZ ; /* 0x00000cff02007986 */
/* 0x000fe8000c101906 */
/*03c0*/ STG.E [R2.64+0x10], RZ ; /* 0x000010ff02007986 */
/* 0x000fe8000c101906 */
/*03d0*/ STG.E [R2.64+0x14], RZ ; /* 0x000014ff02007986 */
/* 0x000fe8000c101906 */
/*03e0*/ STG.E [R2.64+0x18], RZ ; /* 0x000018ff02007986 */
/* 0x000fe8000c101906 */
/*03f0*/ STG.E [R2.64+0x1c], RZ ; /* 0x00001cff02007986 */
/* 0x000fe8000c101906 */
/*0400*/ STG.E [R2.64+0x20], RZ ; /* 0x000020ff02007986 */
/* 0x000fe8000c101906 */
/*0410*/ STG.E [R2.64+0x24], RZ ; /* 0x000024ff02007986 */
/* 0x000fe8000c101906 */
/*0420*/ STG.E [R2.64+0x28], RZ ; /* 0x000028ff02007986 */
/* 0x000fe8000c101906 */
/*0430*/ STG.E [R2.64+0x2c], RZ ; /* 0x00002cff02007986 */
/* 0x000fe8000c101906 */
/*0440*/ STG.E [R2.64+0x30], RZ ; /* 0x000030ff02007986 */
/* 0x000fe8000c101906 */
/*0450*/ STG.E [R2.64+0x34], RZ ; /* 0x000034ff02007986 */
/* 0x000fe8000c101906 */
/*0460*/ STG.E [R2.64+0x38], RZ ; /* 0x000038ff02007986 */
/* 0x000fe8000c101906 */
/*0470*/ STG.E [R2.64+0x3c], RZ ; /* 0x00003cff02007986 */
/* 0x0001e4000c101906 */
/*0480*/ IMAD.MOV.U32 R2, RZ, RZ, R7 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0007 */
/*0490*/ IMAD.MOV.U32 R3, RZ, RZ, R8 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0008 */
/*04a0*/ @P1 BRA 0x330 ; /* 0xfffffe8000001947 */
/* 0x000fea000383ffff */
/*04b0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*04c0*/ @!P1 BRA 0x5c0 ; /* 0x000000f000009947 */
/* 0x000fea0003800000 */
/*04d0*/ IADD3 R7, P1, R2, 0x20, RZ ; /* 0x0000002002077810 */
/* 0x000fe20007f3e0ff */
/*04e0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101906 */
/*04f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0500*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0510*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0520*/ IMAD.X R8, RZ, RZ, R3, P1 ; /* 0x000000ffff087224 */
/* 0x000fe200008e0603 */
/*0530*/ STG.E [R2.64+0x4], RZ ; /* 0x000004ff02007986 */
/* 0x000fe8000c101906 */
/*0540*/ STG.E [R2.64+0x8], RZ ; /* 0x000008ff02007986 */
/* 0x000fe8000c101906 */
/*0550*/ STG.E [R2.64+0xc], RZ ; /* 0x00000cff02007986 */
/* 0x000fe8000c101906 */
/*0560*/ STG.E [R2.64+0x10], RZ ; /* 0x000010ff02007986 */
/* 0x000fe8000c101906 */
/*0570*/ STG.E [R2.64+0x14], RZ ; /* 0x000014ff02007986 */
/* 0x000fe8000c101906 */
/*0580*/ STG.E [R2.64+0x18], RZ ; /* 0x000018ff02007986 */
/* 0x000fe8000c101906 */
/*0590*/ STG.E [R2.64+0x1c], RZ ; /* 0x00001cff02007986 */
/* 0x0001e4000c101906 */
/*05a0*/ IMAD.MOV.U32 R2, RZ, RZ, R7 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0007 */
/*05b0*/ IMAD.MOV.U32 R3, RZ, RZ, R8 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0008 */
/*05c0*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*05d0*/ @!P0 BRA 0x6a0 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*05e0*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fe20007ffe0ff */
/*05f0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0600*/ IADD3 R7, P1, R2, 0x10, RZ ; /* 0x0000001002077810 */
/* 0x000fe20007f3e0ff */
/*0610*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101906 */
/*0620*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc60003f05270 */
/*0630*/ IMAD.X R8, RZ, RZ, R3, P1 ; /* 0x000000ffff087224 */
/* 0x000fe200008e0603 */
/*0640*/ STG.E [R2.64+0x4], RZ ; /* 0x000004ff02007986 */
/* 0x000fe8000c101906 */
/*0650*/ STG.E [R2.64+0x8], RZ ; /* 0x000008ff02007986 */
/* 0x000fe8000c101906 */
/*0660*/ STG.E [R2.64+0xc], RZ ; /* 0x00000cff02007986 */
/* 0x0001e4000c101906 */
/*0670*/ IMAD.MOV.U32 R2, RZ, RZ, R7 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0007 */
/*0680*/ IMAD.MOV.U32 R3, RZ, RZ, R8 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0008 */
/*0690*/ @P0 BRA 0x5e0 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*06a0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*06b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*06c0*/ IADD3 R0, R0, UR4, RZ ; /* 0x0000000400007c10 */
/* 0x000fe2000fffe0ff */
/*06d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*06e0*/ IMAD R0, R5, c[0x0][0x184], R0 ; /* 0x0000610005007a24 */
/* 0x000fc800078e0200 */
/*06f0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fc800078e0203 */
/*0700*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe20007ffe0ff */
/*0710*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e2000c101906 */
/*0720*/ IADD3 R0, P1, R2, 0x4, RZ ; /* 0x0000000402007810 */
/* 0x000fe40007f3e0ff */
/*0730*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*0740*/ IMAD.X R5, RZ, RZ, R3, P1 ; /* 0x000000ffff057224 */
/* 0x000fd400008e0603 */
/*0750*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0760*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x001fe400078e0000 */
/*0770*/ IMAD.MOV.U32 R3, RZ, RZ, R5 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0005 */
/*0780*/ BRA 0x700 ; /* 0xffffff7000007947 */
/* 0x000fea000383ffff */
/*0790*/ I2F R5, c[0x0][0x178] ; /* 0x00005e0000057b06 */
/* 0x000e220000201400 */
/*07a0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff047624 */
/* 0x000fc800078e00ff */
/*07b0*/ FADD R4, R4, -c[0x0][0x168] ; /* 0x80005a0004047621 */
/* 0x000fc60000000000 */
/*07c0*/ MUFU.RCP R6, R5 ; /* 0x0000000500067308 */
/* 0x001e300000001000 */
/*07d0*/ FCHK P0, R4, R5 ; /* 0x0000000504007302 */
/* 0x000e620000000000 */
/*07e0*/ FFMA R7, -R5, R6, 1 ; /* 0x3f80000005077423 */
/* 0x001fc80000000106 */
/*07f0*/ FFMA R7, R6, R7, R6 ; /* 0x0000000706077223 */
/* 0x000fc80000000006 */
/*0800*/ FFMA R6, R4, R7, RZ ; /* 0x0000000704067223 */
/* 0x000fc800000000ff */
/*0810*/ FFMA R8, -R5, R6, R4 ; /* 0x0000000605087223 */
/* 0x000fc80000000104 */
/*0820*/ FFMA R6, R7, R8, R6 ; /* 0x0000000807067223 */
/* 0x000fe20000000006 */
/*0830*/ @!P0 BRA 0x890 ; /* 0x0000005000008947 */
/* 0x002fea0003800000 */
/*0840*/ IMAD.MOV.U32 R9, RZ, RZ, R4 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0004 */
/*0850*/ MOV R4, 0x880 ; /* 0x0000088000047802 */
/* 0x000fe20000000f00 */
/*0860*/ IMAD.MOV.U32 R10, RZ, RZ, R5 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0005 */
/*0870*/ CALL.REL.NOINC 0xa60 ; /* 0x000001e000007944 */
/* 0x000fea0003c00000 */
/*0880*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0008 */
/*0890*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fca00078e00ff */
/*08a0*/ IMAD.IADD R4, R0, 0x1, R7.reuse ; /* 0x0000000100047824 */
/* 0x101fe200078e0207 */
/*08b0*/ BSSY B0, 0xa10 ; /* 0x0000015000007945 */
/* 0x000fe20003800000 */
/*08c0*/ IMAD.IADD R11, R2, 0x1, R7 ; /* 0x00000001020b7824 */
/* 0x000fe200078e0207 */
/*08d0*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe20007ffe0ff */
/*08e0*/ I2F R5, R4 ; /* 0x0000000400057306 */
/* 0x000e220000201400 */
/*08f0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe400078e00ff */
/*0900*/ ISETP.GE.AND P1, PT, R7, c[0x0][0x188], PT ; /* 0x0000620007007a0c */
/* 0x000fe20003f26270 */
/*0910*/ IMAD.MOV.U32 R8, RZ, RZ, R3 ; /* 0x000000ffff087224 */
/* 0x000fc400078e0003 */
/*0920*/ FFMA R10, R5, R6, c[0x0][0x168] ; /* 0x00005a00050a7623 */
/* 0x001fc80000000006 */
/*0930*/ IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff057224 */
/* 0x000fe400078e000a */
/*0940*/ FMUL R12, R8, R8 ; /* 0x00000008080c7220 */
/* 0x000fe40000400000 */
/*0950*/ FMUL R13, R5, R5 ; /* 0x00000005050d7220 */
/* 0x000fc80000400000 */
/*0960*/ FADD R4, R12, R13 ; /* 0x0000000d0c047221 */
/* 0x000fca0000000000 */
/*0970*/ FSETP.GT.AND P0, PT, R4, 4, PT ; /* 0x408000000400780b */
/* 0x000fda0003f04000 */
/*0980*/ @P0 BRA 0xa00 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0990*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fe20007ffe0ff */
/*09a0*/ FADD R4, R5, R5 ; /* 0x0000000505047221 */
/* 0x000fe40000000000 */
/*09b0*/ FADD R5, -R12, R13 ; /* 0x0000000d0c057221 */
/* 0x000fe20000000100 */
/*09c0*/ ISETP.GE.AND P0, PT, R9, c[0x0][0x180], PT ; /* 0x0000600009007a0c */
/* 0x000fe20003f06270 */
/*09d0*/ FFMA R8, R4, R8, R3 ; /* 0x0000000804087223 */
/* 0x000fe40000000003 */
/*09e0*/ FADD R5, R10, R5 ; /* 0x000000050a057221 */
/* 0x000fd40000000000 */
/*09f0*/ @!P0 BRA 0x940 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0a00*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0a10*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*0a20*/ IMAD.WIDE R4, R11, R4, c[0x0][0x170] ; /* 0x00005c000b047625 */
/* 0x000fca00078e0204 */
/*0a30*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e2000c101906 */
/*0a40*/ @!P1 BRA 0x8a0 ; /* 0xfffffe5000009947 */
/* 0x000fea000383ffff */
/*0a50*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a60*/ SHF.R.U32.HI R7, RZ, 0x17, R10.reuse ; /* 0x00000017ff077819 */
/* 0x100fe4000001160a */
/*0a70*/ SHF.R.U32.HI R6, RZ, 0x17, R9.reuse ; /* 0x00000017ff067819 */
/* 0x100fe40000011609 */
/*0a80*/ LOP3.LUT R14, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff070e7812 */
/* 0x000fe200078ec0ff */
/*0a90*/ IMAD.MOV.U32 R7, RZ, RZ, R10 ; /* 0x000000ffff077224 */
/* 0x000fe200078e000a */
/*0aa0*/ LOP3.LUT R12, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff060c7812 */
/* 0x000fe200078ec0ff */
/*0ab0*/ IMAD.MOV.U32 R6, RZ, RZ, R9 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0009 */
/*0ac0*/ IADD3 R13, R14, -0x1, RZ ; /* 0xffffffff0e0d7810 */
/* 0x000fe40007ffe0ff */
/*0ad0*/ IADD3 R11, R12, -0x1, RZ ; /* 0xffffffff0c0b7810 */
/* 0x000fc40007ffe0ff */
/*0ae0*/ ISETP.GT.U32.AND P0, PT, R13, 0xfd, PT ; /* 0x000000fd0d00780c */
/* 0x000fc80003f04070 */
/*0af0*/ ISETP.GT.U32.OR P0, PT, R11, 0xfd, P0 ; /* 0x000000fd0b00780c */
/* 0x000fda0000704470 */
/*0b00*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff088224 */
/* 0x000fe200078e00ff */
/*0b10*/ @!P0 BRA 0xc90 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0b20*/ FSETP.GTU.FTZ.AND P0, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fe40003f1c200 */
/*0b30*/ FSETP.GTU.FTZ.AND P1, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fc80003f3c200 */
/*0b40*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0b50*/ @P0 BRA 0x1070 ; /* 0x0000051000000947 */
/* 0x000fea0003800000 */
/*0b60*/ LOP3.LUT P0, RZ, R7, 0x7fffffff, R6, 0xc8, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fda000780c806 */
/*0b70*/ @!P0 BRA 0x1050 ; /* 0x000004d000008947 */
/* 0x000fea0003800000 */
/*0b80*/ FSETP.NEU.FTZ.AND P2, PT, |R9|.reuse, +INF , PT ; /* 0x7f8000000900780b */
/* 0x040fe40003f5d200 */
/*0b90*/ FSETP.NEU.FTZ.AND P1, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fe40003f3d200 */
/*0ba0*/ FSETP.NEU.FTZ.AND P0, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fd60003f1d200 */
/*0bb0*/ @!P1 BRA !P2, 0x1050 ; /* 0x0000049000009947 */
/* 0x000fea0005000000 */
/*0bc0*/ LOP3.LUT P2, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fc8000784c0ff */
/*0bd0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0be0*/ @P1 BRA 0x1030 ; /* 0x0000044000001947 */
/* 0x000fea0003800000 */
/*0bf0*/ LOP3.LUT P1, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000782c0ff */
/*0c00*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0c10*/ @P0 BRA 0x1000 ; /* 0x000003e000000947 */
/* 0x000fea0003800000 */
/*0c20*/ ISETP.GE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f06270 */
/*0c30*/ ISETP.GE.AND P1, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fd60003f26270 */
/*0c40*/ @P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff080224 */
/* 0x000fe400078e00ff */
/*0c50*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, -0x40 ; /* 0xffffffc0ff088424 */
/* 0x000fe400078e00ff */
/*0c60*/ @!P0 FFMA R6, R9, 1.84467440737095516160e+19, RZ ; /* 0x5f80000009068823 */
/* 0x000fe400000000ff */
/*0c70*/ @!P1 FFMA R7, R10, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000a079823 */
/* 0x000fe200000000ff */
/*0c80*/ @!P1 IADD3 R8, R8, 0x40, RZ ; /* 0x0000004008089810 */
/* 0x000fe40007ffe0ff */
/*0c90*/ LEA R10, R14, 0xc0800000, 0x17 ; /* 0xc08000000e0a7811 */
/* 0x000fca00078eb8ff */
/*0ca0*/ IMAD.IADD R10, R7, 0x1, -R10 ; /* 0x00000001070a7824 */
/* 0x000fe200078e0a0a */
/*0cb0*/ IADD3 R7, R12, -0x7f, RZ ; /* 0xffffff810c077810 */
/* 0x000fc60007ffe0ff */
/*0cc0*/ MUFU.RCP R9, R10 ; /* 0x0000000a00097308 */
/* 0x000e220000001000 */
/*0cd0*/ FADD.FTZ R11, -R10, -RZ ; /* 0x800000ff0a0b7221 */
/* 0x000fe40000010100 */
/*0ce0*/ IMAD R6, R7, -0x800000, R6 ; /* 0xff80000007067824 */
/* 0x000fe400078e0206 */
/*0cf0*/ FFMA R12, R9, R11, 1 ; /* 0x3f800000090c7423 */
/* 0x001fc8000000000b */
/*0d00*/ FFMA R13, R9, R12, R9 ; /* 0x0000000c090d7223 */
/* 0x000fc80000000009 */
/*0d10*/ FFMA R9, R6, R13, RZ ; /* 0x0000000d06097223 */
/* 0x000fc800000000ff */
/*0d20*/ FFMA R12, R11, R9, R6 ; /* 0x000000090b0c7223 */
/* 0x000fc80000000006 */
/*0d30*/ FFMA R12, R13, R12, R9 ; /* 0x0000000c0d0c7223 */
/* 0x000fe20000000009 */
/*0d40*/ IADD3 R9, R7, 0x7f, -R14 ; /* 0x0000007f07097810 */
/* 0x000fc60007ffe80e */
/*0d50*/ FFMA R11, R11, R12, R6 ; /* 0x0000000c0b0b7223 */
/* 0x000fe40000000006 */
/*0d60*/ IMAD.IADD R9, R9, 0x1, R8 ; /* 0x0000000109097824 */
/* 0x000fe400078e0208 */
/*0d70*/ FFMA R6, R13, R11, R12 ; /* 0x0000000b0d067223 */
/* 0x000fca000000000c */
/*0d80*/ SHF.R.U32.HI R7, RZ, 0x17, R6 ; /* 0x00000017ff077819 */
/* 0x000fc80000011606 */
/*0d90*/ LOP3.LUT R7, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07077812 */
/* 0x000fca00078ec0ff */
/*0da0*/ IMAD.IADD R14, R7, 0x1, R9 ; /* 0x00000001070e7824 */
/* 0x000fca00078e0209 */
/*0db0*/ IADD3 R7, R14, -0x1, RZ ; /* 0xffffffff0e077810 */
/* 0x000fc80007ffe0ff */
/*0dc0*/ ISETP.GE.U32.AND P0, PT, R7, 0xfe, PT ; /* 0x000000fe0700780c */
/* 0x000fda0003f06070 */
/*0dd0*/ @!P0 BRA 0xfe0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0de0*/ ISETP.GT.AND P0, PT, R14, 0xfe, PT ; /* 0x000000fe0e00780c */
/* 0x000fda0003f04270 */
/*0df0*/ @P0 BRA 0xfb0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0e00*/ ISETP.GE.AND P0, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fda0003f06270 */
/*0e10*/ @P0 BRA 0x1080 ; /* 0x0000026000000947 */
/* 0x000fea0003800000 */
/*0e20*/ ISETP.GE.AND P0, PT, R14, -0x18, PT ; /* 0xffffffe80e00780c */
/* 0x000fe40003f06270 */
/*0e30*/ LOP3.LUT R6, R6, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000006067812 */
/* 0x000fd600078ec0ff */
/*0e40*/ @!P0 BRA 0x1080 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*0e50*/ FFMA.RZ R7, R13.reuse, R11.reuse, R12.reuse ; /* 0x0000000b0d077223 */
/* 0x1c0fe2000000c00c */
/*0e60*/ IADD3 R10, R14.reuse, 0x20, RZ ; /* 0x000000200e0a7810 */
/* 0x040fe20007ffe0ff */
/*0e70*/ FFMA.RM R8, R13, R11.reuse, R12.reuse ; /* 0x0000000b0d087223 */
/* 0x180fe2000000400c */
/*0e80*/ ISETP.NE.AND P2, PT, R14.reuse, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x040fe40003f45270 */
/*0e90*/ LOP3.LUT R9, R7, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff07097812 */
/* 0x000fe200078ec0ff */
/*0ea0*/ FFMA.RP R7, R13, R11, R12 ; /* 0x0000000b0d077223 */
/* 0x000fe2000000800c */
/*0eb0*/ ISETP.NE.AND P1, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe20003f25270 */
/*0ec0*/ IMAD.MOV R11, RZ, RZ, -R14 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0a0e */
/*0ed0*/ LOP3.LUT R9, R9, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000009097812 */
/* 0x000fe400078efcff */
/*0ee0*/ FSETP.NEU.FTZ.AND P0, PT, R7, R8, PT ; /* 0x000000080700720b */
/* 0x000fc40003f1d000 */
/*0ef0*/ SHF.L.U32 R10, R9, R10, RZ ; /* 0x0000000a090a7219 */
/* 0x000fe400000006ff */
/*0f00*/ SEL R8, R11, RZ, P2 ; /* 0x000000ff0b087207 */
/* 0x000fe40001000000 */
/*0f10*/ ISETP.NE.AND P1, PT, R10, RZ, P1 ; /* 0x000000ff0a00720c */
/* 0x000fe40000f25270 */
/*0f20*/ SHF.R.U32.HI R8, RZ, R8, R9 ; /* 0x00000008ff087219 */
/* 0x000fe40000011609 */
/*0f30*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0f40*/ SHF.R.U32.HI R10, RZ, 0x1, R8 ; /* 0x00000001ff0a7819 */
/* 0x000fc40000011608 */
/*0f50*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fc80004000000 */
/*0f60*/ LOP3.LUT R7, R7, 0x1, R10, 0xf8, !PT ; /* 0x0000000107077812 */
/* 0x000fc800078ef80a */
/*0f70*/ LOP3.LUT R7, R7, R8, RZ, 0xc0, !PT ; /* 0x0000000807077212 */
/* 0x000fca00078ec0ff */
/*0f80*/ IMAD.IADD R7, R10, 0x1, R7 ; /* 0x000000010a077824 */
/* 0x000fca00078e0207 */
/*0f90*/ LOP3.LUT R6, R7, R6, RZ, 0xfc, !PT ; /* 0x0000000607067212 */
/* 0x000fe200078efcff */
/*0fa0*/ BRA 0x1080 ; /* 0x000000d000007947 */
/* 0x000fea0003800000 */
/*0fb0*/ LOP3.LUT R6, R6, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000006067812 */
/* 0x000fc800078ec0ff */
/*0fc0*/ LOP3.LUT R6, R6, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000006067812 */
/* 0x000fe200078efcff */
/*0fd0*/ BRA 0x1080 ; /* 0x000000a000007947 */
/* 0x000fea0003800000 */
/*0fe0*/ IMAD R6, R9, 0x800000, R6 ; /* 0x0080000009067824 */
/* 0x000fe200078e0206 */
/*0ff0*/ BRA 0x1080 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*1000*/ LOP3.LUT R6, R7, 0x80000000, R6, 0x48, !PT ; /* 0x8000000007067812 */
/* 0x000fc800078e4806 */
/*1010*/ LOP3.LUT R6, R6, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000006067812 */
/* 0x000fe200078efcff */
/*1020*/ BRA 0x1080 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*1030*/ LOP3.LUT R6, R7, 0x80000000, R6, 0x48, !PT ; /* 0x8000000007067812 */
/* 0x000fe200078e4806 */
/*1040*/ BRA 0x1080 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*1050*/ MUFU.RSQ R6, -QNAN ; /* 0xffc0000000067908 */
/* 0x000e220000001400 */
/*1060*/ BRA 0x1080 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*1070*/ FADD.FTZ R6, R9, R10 ; /* 0x0000000a09067221 */
/* 0x000fc80000010000 */
/*1080*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x001fe400078e0006 */
/*1090*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0004 */
/*10a0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fc800078e00ff */
/*10b0*/ RET.REL.NODEC R6 0x0 ; /* 0xffffef4006007950 */
/* 0x000fea0003c3ffff */
/*10c0*/ BRA 0x10c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12mandelKernelffffPiiiiii
.globl _Z12mandelKernelffffPiiiiii
.p2align 8
.type _Z12mandelKernelffffPiiiiii,@function
_Z12mandelKernelffffPiiiiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s3, s[0:1], 0x28
v_and_b32_e32 v1, 0x3ff, v0
s_load_b64 s[8:9], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s4, v[1:2]
v_bfe_u32 v1, v0, 10, 10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v0, v2, s3
v_mad_u64_u32 v[3:4], null, s15, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s8, v0
v_cmp_gt_i32_e64 s2, s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_11
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_11
s_clause 0x1
s_load_b64 s[10:11], s[0:1], 0x0
s_load_b128 s[4:7], s[0:1], 0x8
v_cvt_f32_i32_e32 v4, s8
v_cvt_f32_i32_e32 v1, s9
s_load_b64 s[0:1], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
v_sub_f32_e64 v5, s10, s4
v_sub_f32_e64 v2, s11, s5
s_cmp_gt_i32 s0, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_scale_f32 v6, null, v4, v4, v5
v_div_scale_f32 v7, null, v1, v1, v2
v_div_scale_f32 v12, vcc_lo, v5, v4, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v8, v6
v_rcp_f32_e32 v9, v7
s_waitcnt_depctr 0xfff
v_fma_f32 v10, -v6, v8, 1.0
v_fma_f32 v11, -v7, v9, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_fmac_f32 v8, v10, v8 :: v_dual_fmac_f32 v9, v11, v9
v_div_scale_f32 v10, s2, v2, v1, v2
v_mul_f32_e32 v11, v12, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v13, v10, v9
v_fma_f32 v14, -v6, v11, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v15, -v7, v13, v10
v_fmac_f32_e32 v11, v14, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v13, v15, v9
v_fma_f32 v6, -v6, v11, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v7, -v7, v13, v10
v_div_fmas_f32 v6, v6, v8, v11
s_mov_b32 vcc_lo, s2
v_cvt_f32_i32_e32 v8, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_div_fmas_f32 v7, v7, v9, v13
s_mov_b32 s2, 0
v_div_fixup_f32 v7, v7, v1, v2
v_mad_u64_u32 v[1:2], null, v3, s1, v[0:1]
v_div_fixup_f32 v2, v6, v4, v5
s_cselect_b32 s1, -1, 0
s_delay_alu instid0(VALU_DEP_3)
v_fma_f32 v3, v7, v8, s5
s_branch .LBB0_5
.LBB0_3:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s5
.LBB0_4:
v_add_nc_u32_e32 v4, s2, v1
s_add_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s2, s3
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_u32 v4, vcc_lo, s6, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
global_store_b32 v[4:5], v6, off
s_cbranch_scc0 .LBB0_11
.LBB0_5:
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_dual_mov_b32 v5, v3 :: v_dual_add_nc_u32 v4, s2, v0
s_mov_b32 s5, 0
s_mov_b32 s8, 0
v_cvt_f32_i32_e32 v4, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, v2, v4, s4
v_mov_b32_e32 v7, v4
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_8
.p2align 6
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s10, exec_lo, s9
s_or_b32 s5, s10, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execz .LBB0_3
.LBB0_8:
v_mul_f32_e32 v8, v5, v5
s_or_b32 s9, s9, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, v7, v7, v8
v_cmp_nlt_f32_e32 vcc_lo, 4.0, v6
v_mov_b32_e32 v6, s8
s_and_saveexec_b32 s10, vcc_lo
s_cbranch_execz .LBB0_7
v_mul_f32_e32 v6, v7, v7
v_add_f32_e32 v7, v7, v7
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s0, s8
v_sub_f32_e32 v8, v6, v8
s_cselect_b32 s11, -1, 0
v_mov_b32_e32 v6, s0
v_fma_f32 v5, v5, v7, v3
s_and_not1_b32 s9, s9, exec_lo
v_add_f32_e32 v7, v4, v8
s_and_b32 s11, s11, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s9, s9, s11
s_branch .LBB0_7
.LBB0_10:
v_mov_b32_e32 v6, 0
s_branch .LBB0_4
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12mandelKernelffffPiiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12mandelKernelffffPiiiiii, .Lfunc_end0-_Z12mandelKernelffffPiiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12mandelKernelffffPiiiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12mandelKernelffffPiiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009f5e8_00000000-6_kernel3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6mandelffi
.type _Z6mandelffi, @function
_Z6mandelffi:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z6mandelffi, .-_Z6mandelffi
.globl _Z41__device_stub__Z12mandelKernelffffPiiiiiiffffPiiiiii
.type _Z41__device_stub__Z12mandelKernelffffPiiiiiiffffPiiiiii, @function
_Z41__device_stub__Z12mandelKernelffffPiiiiiiffffPiiiiii:
.LFB2083:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movss %xmm0, 44(%rsp)
movss %xmm1, 40(%rsp)
movss %xmm2, 36(%rsp)
movss %xmm3, 32(%rsp)
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 4(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12mandelKernelffffPiiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z41__device_stub__Z12mandelKernelffffPiiiiiiffffPiiiiii, .-_Z41__device_stub__Z12mandelKernelffffPiiiiiiffffPiiiiii
.globl _Z12mandelKernelffffPiiiiii
.type _Z12mandelKernelffffPiiiiii, @function
_Z12mandelKernelffffPiiiiii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z12mandelKernelffffPiiiiiiffffPiiiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z12mandelKernelffffPiiiiii, .-_Z12mandelKernelffffPiiiiii
.globl _Z6hostFEffffPiiii
.type _Z6hostFEffffPiiii, @function
_Z6hostFEffffPiiii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movss %xmm0, 12(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm2, 20(%rsp)
movss %xmm3, 24(%rsp)
movq %rdi, %r14
movl %esi, %r12d
movl %edx, %r13d
movl %ecx, 28(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq $0, 40(%rsp)
movq $0, 48(%rsp)
movl %esi, %ebp
imull %edx, %ebp
movslq %ebp, %rbp
salq $2, %rbp
leaq 40(%rsp), %rdi
movl $0, %edx
movq %rbp, %rsi
call cudaHostAlloc@PLT
movslq %r13d, %r15
movslq %r12d, %rbx
salq $2, %rbx
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdi
movq %r15, %rcx
movq %rbx, %rdx
call cudaMallocPitch@PLT
subq $8, %rsp
.cfi_def_cfa_offset 168
pushq $1
.cfi_def_cfa_offset 176
movq %r15, %r9
movq %rbx, %r8
movq %rbx, %rcx
movq 56(%rsp), %rdx
movq 72(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy2D@PLT
movl $64, 80(%rsp)
movl $64, 84(%rsp)
movl $25, 92(%rsp)
movl $25, 96(%rsp)
addq $16, %rsp
.cfi_def_cfa_offset 160
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L14:
call cudaDeviceSynchronize@PLT
subq $8, %rsp
.cfi_def_cfa_offset 168
pushq $2
.cfi_def_cfa_offset 176
movq %r15, %r9
movq %rbx, %r8
movq 72(%rsp), %rcx
movq 64(%rsp), %rdx
movq %rbx, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy2D@PLT
movq 56(%rsp), %rbx
movq %rbp, %rdx
movq %rbx, %rsi
movq %r14, %rdi
call memcpy@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
movq %rbx, %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 56(%rsp), %r8
shrq $2, %r8
movl $2, %r9d
movl 28(%rsp), %ecx
movl %r13d, %edx
movl %r12d, %esi
movq 48(%rsp), %rdi
movss 24(%rsp), %xmm3
movss 20(%rsp), %xmm2
movss 16(%rsp), %xmm1
movss 12(%rsp), %xmm0
call _Z41__device_stub__Z12mandelKernelffffPiiiiiiffffPiiiiii
jmp .L14
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z6hostFEffffPiiii, .-_Z6hostFEffffPiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12mandelKernelffffPiiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12mandelKernelffffPiiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel3.hip"
.globl _Z27__device_stub__mandelKernelffffPiiiiii # -- Begin function _Z27__device_stub__mandelKernelffffPiiiiii
.p2align 4, 0x90
.type _Z27__device_stub__mandelKernelffffPiiiiii,@function
_Z27__device_stub__mandelKernelffffPiiiiii: # @_Z27__device_stub__mandelKernelffffPiiiiii
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movss %xmm0, 36(%rsp)
movss %xmm1, 32(%rsp)
movss %xmm2, 28(%rsp)
movss %xmm3, 24(%rsp)
movq %rdi, 88(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
leaq 36(%rsp), %rax
movq %rax, 96(%rsp)
leaq 32(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
leaq 4(%rsp), %rax
movq %rax, 168(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12mandelKernelffffPiiiiii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z27__device_stub__mandelKernelffffPiiiiii, .Lfunc_end0-_Z27__device_stub__mandelKernelffffPiiiiii
.cfi_endproc
# -- End function
.globl _Z6hostFEffffPiiii # -- Begin function _Z6hostFEffffPiiii
.p2align 4, 0x90
.type _Z6hostFEffffPiiii,@function
_Z6hostFEffffPiiii: # @_Z6hostFEffffPiiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movl %edx, %r13d
movl %esi, %ebx
movq %rdi, 96(%rsp) # 8-byte Spill
movss %xmm3, 56(%rsp) # 4-byte Spill
movss %xmm2, 52(%rsp) # 4-byte Spill
movss %xmm1, 48(%rsp) # 4-byte Spill
movss %xmm0, 44(%rsp) # 4-byte Spill
movq $0, 24(%rsp)
movq $0, 16(%rsp)
movl %edx, %eax
imull %esi, %eax
movslq %eax, %r14
shlq $2, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
xorl %edx, %edx
callq hipHostAlloc
movslq %ebx, %r15
shlq $2, %r15
movslq %r13d, %r12
leaq 16(%rsp), %rdi
leaq 32(%rsp), %rsi
movq %r15, %rdx
movq %r12, %rcx
callq hipMallocPitch
movq 16(%rsp), %rdi
movq 32(%rsp), %rsi
movq 24(%rsp), %rdx
movl $1, (%rsp)
movq %r15, %rcx
movq %r15, %r8
movq %r12, %r9
callq hipMemcpy2D
movabsq $274877907008, %rdi # imm = 0x4000000040
movabsq $107374182425, %rdx # imm = 0x1900000019
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 32(%rsp), %rcx
shrq $2, %rcx
movss 44(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 92(%rsp)
movss 48(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 88(%rsp)
movss 52(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 84(%rsp)
movss 56(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 80(%rsp)
movq %rax, 152(%rsp)
movl %ebx, 76(%rsp)
movl %r13d, 72(%rsp)
movl %ebp, 68(%rsp)
movl %ecx, 64(%rsp)
movl $2, 60(%rsp)
leaq 92(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rax
movq %rax, 168(%rsp)
leaq 84(%rsp), %rax
movq %rax, 176(%rsp)
leaq 80(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 76(%rsp), %rax
movq %rax, 200(%rsp)
leaq 72(%rsp), %rax
movq %rax, 208(%rsp)
leaq 68(%rsp), %rax
movq %rax, 216(%rsp)
leaq 64(%rsp), %rax
movq %rax, 224(%rsp)
leaq 60(%rsp), %rax
movq %rax, 232(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rax
movq 104(%rsp), %rdi
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
movq %rdi, 8(%rsp)
movq %rax, (%rsp)
leaq 160(%rsp), %r9
movl $_Z12mandelKernelffffPiiiiii, %edi
callq hipLaunchKernel
.LBB1_2:
callq hipDeviceSynchronize
movq 24(%rsp), %rdi
movq 16(%rsp), %rdx
movq 32(%rsp), %rcx
movl $2, (%rsp)
movq %r15, %rsi
movq %r15, %r8
movq %r12, %r9
callq hipMemcpy2D
movq 24(%rsp), %rbx
movq 96(%rsp), %rdi # 8-byte Reload
movq %rbx, %rsi
movq %r14, %rdx
callq memcpy@PLT
movq %rbx, %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z6hostFEffffPiiii, .Lfunc_end1-_Z6hostFEffffPiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12mandelKernelffffPiiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12mandelKernelffffPiiiiii,@object # @_Z12mandelKernelffffPiiiiii
.section .rodata,"a",@progbits
.globl _Z12mandelKernelffffPiiiiii
.p2align 3, 0x0
_Z12mandelKernelffffPiiiiii:
.quad _Z27__device_stub__mandelKernelffffPiiiiii
.size _Z12mandelKernelffffPiiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12mandelKernelffffPiiiiii"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__mandelKernelffffPiiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12mandelKernelffffPiiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void kernel_mult_vector_by_number(double *vec, double alpha, int numElements)
{
int iam = threadIdx.x;
int bid = blockIdx.x;
int threads_in_block = blockDim.x;
int gid = bid*threads_in_block + iam;
if (gid < numElements){
vec[gid] *= alpha;
}
} | code for sm_80
Function : _Z28kernel_mult_vector_by_numberPddi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1b00 */
/*00a0*/ DMUL R4, R4, c[0x0][0x168] ; /* 0x00005a0004047a28 */
/* 0x004e0e0000000000 */
/*00b0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x001fe2000c101b04 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kernel_mult_vector_by_number(double *vec, double alpha, int numElements)
{
int iam = threadIdx.x;
int bid = blockIdx.x;
int threads_in_block = blockDim.x;
int gid = bid*threads_in_block + iam;
if (gid < numElements){
vec[gid] *= alpha;
}
} | .file "tmpxft_000c7dac_00000000-6_kernel_mult_vector_by_number.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z28kernel_mult_vector_by_numberPddiPddi
.type _Z50__device_stub__Z28kernel_mult_vector_by_numberPddiPddi, @function
_Z50__device_stub__Z28kernel_mult_vector_by_numberPddiPddi:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movsd %xmm0, 16(%rsp)
movl %esi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z28kernel_mult_vector_by_numberPddi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z28kernel_mult_vector_by_numberPddiPddi, .-_Z50__device_stub__Z28kernel_mult_vector_by_numberPddiPddi
.globl _Z28kernel_mult_vector_by_numberPddi
.type _Z28kernel_mult_vector_by_numberPddi, @function
_Z28kernel_mult_vector_by_numberPddi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z28kernel_mult_vector_by_numberPddiPddi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z28kernel_mult_vector_by_numberPddi, .-_Z28kernel_mult_vector_by_numberPddi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z28kernel_mult_vector_by_numberPddi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z28kernel_mult_vector_by_numberPddi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kernel_mult_vector_by_number(double *vec, double alpha, int numElements)
{
int iam = threadIdx.x;
int bid = blockIdx.x;
int threads_in_block = blockDim.x;
int gid = bid*threads_in_block + iam;
if (gid < numElements){
vec[gid] *= alpha;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_mult_vector_by_number(double *vec, double alpha, int numElements)
{
int iam = threadIdx.x;
int bid = blockIdx.x;
int threads_in_block = blockDim.x;
int gid = bid*threads_in_block + iam;
if (gid < numElements){
vec[gid] *= alpha;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_mult_vector_by_number(double *vec, double alpha, int numElements)
{
int iam = threadIdx.x;
int bid = blockIdx.x;
int threads_in_block = blockDim.x;
int gid = bid*threads_in_block + iam;
if (gid < numElements){
vec[gid] *= alpha;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z28kernel_mult_vector_by_numberPddi
.globl _Z28kernel_mult_vector_by_numberPddi
.p2align 8
.type _Z28kernel_mult_vector_by_numberPddi,@function
_Z28kernel_mult_vector_by_numberPddi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[2:3], v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f64 v[2:3], v[2:3], s[2:3]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z28kernel_mult_vector_by_numberPddi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z28kernel_mult_vector_by_numberPddi, .Lfunc_end0-_Z28kernel_mult_vector_by_numberPddi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z28kernel_mult_vector_by_numberPddi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z28kernel_mult_vector_by_numberPddi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_mult_vector_by_number(double *vec, double alpha, int numElements)
{
int iam = threadIdx.x;
int bid = blockIdx.x;
int threads_in_block = blockDim.x;
int gid = bid*threads_in_block + iam;
if (gid < numElements){
vec[gid] *= alpha;
}
} | .text
.file "kernel_mult_vector_by_number.hip"
.globl _Z43__device_stub__kernel_mult_vector_by_numberPddi # -- Begin function _Z43__device_stub__kernel_mult_vector_by_numberPddi
.p2align 4, 0x90
.type _Z43__device_stub__kernel_mult_vector_by_numberPddi,@function
_Z43__device_stub__kernel_mult_vector_by_numberPddi: # @_Z43__device_stub__kernel_mult_vector_by_numberPddi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movsd %xmm0, 64(%rsp)
movl %esi, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z28kernel_mult_vector_by_numberPddi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z43__device_stub__kernel_mult_vector_by_numberPddi, .Lfunc_end0-_Z43__device_stub__kernel_mult_vector_by_numberPddi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z28kernel_mult_vector_by_numberPddi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z28kernel_mult_vector_by_numberPddi,@object # @_Z28kernel_mult_vector_by_numberPddi
.section .rodata,"a",@progbits
.globl _Z28kernel_mult_vector_by_numberPddi
.p2align 3, 0x0
_Z28kernel_mult_vector_by_numberPddi:
.quad _Z43__device_stub__kernel_mult_vector_by_numberPddi
.size _Z28kernel_mult_vector_by_numberPddi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z28kernel_mult_vector_by_numberPddi"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z43__device_stub__kernel_mult_vector_by_numberPddi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z28kernel_mult_vector_by_numberPddi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z28kernel_mult_vector_by_numberPddi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1b00 */
/*00a0*/ DMUL R4, R4, c[0x0][0x168] ; /* 0x00005a0004047a28 */
/* 0x004e0e0000000000 */
/*00b0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x001fe2000c101b04 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z28kernel_mult_vector_by_numberPddi
.globl _Z28kernel_mult_vector_by_numberPddi
.p2align 8
.type _Z28kernel_mult_vector_by_numberPddi,@function
_Z28kernel_mult_vector_by_numberPddi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[2:3], v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f64 v[2:3], v[2:3], s[2:3]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z28kernel_mult_vector_by_numberPddi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z28kernel_mult_vector_by_numberPddi, .Lfunc_end0-_Z28kernel_mult_vector_by_numberPddi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z28kernel_mult_vector_by_numberPddi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z28kernel_mult_vector_by_numberPddi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c7dac_00000000-6_kernel_mult_vector_by_number.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z28kernel_mult_vector_by_numberPddiPddi
.type _Z50__device_stub__Z28kernel_mult_vector_by_numberPddiPddi, @function
_Z50__device_stub__Z28kernel_mult_vector_by_numberPddiPddi:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movsd %xmm0, 16(%rsp)
movl %esi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z28kernel_mult_vector_by_numberPddi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z28kernel_mult_vector_by_numberPddiPddi, .-_Z50__device_stub__Z28kernel_mult_vector_by_numberPddiPddi
.globl _Z28kernel_mult_vector_by_numberPddi
.type _Z28kernel_mult_vector_by_numberPddi, @function
_Z28kernel_mult_vector_by_numberPddi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z28kernel_mult_vector_by_numberPddiPddi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z28kernel_mult_vector_by_numberPddi, .-_Z28kernel_mult_vector_by_numberPddi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z28kernel_mult_vector_by_numberPddi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z28kernel_mult_vector_by_numberPddi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel_mult_vector_by_number.hip"
.globl _Z43__device_stub__kernel_mult_vector_by_numberPddi # -- Begin function _Z43__device_stub__kernel_mult_vector_by_numberPddi
.p2align 4, 0x90
.type _Z43__device_stub__kernel_mult_vector_by_numberPddi,@function
_Z43__device_stub__kernel_mult_vector_by_numberPddi: # @_Z43__device_stub__kernel_mult_vector_by_numberPddi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movsd %xmm0, 64(%rsp)
movl %esi, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z28kernel_mult_vector_by_numberPddi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z43__device_stub__kernel_mult_vector_by_numberPddi, .Lfunc_end0-_Z43__device_stub__kernel_mult_vector_by_numberPddi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z28kernel_mult_vector_by_numberPddi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z28kernel_mult_vector_by_numberPddi,@object # @_Z28kernel_mult_vector_by_numberPddi
.section .rodata,"a",@progbits
.globl _Z28kernel_mult_vector_by_numberPddi
.p2align 3, 0x0
_Z28kernel_mult_vector_by_numberPddi:
.quad _Z43__device_stub__kernel_mult_vector_by_numberPddi
.size _Z28kernel_mult_vector_by_numberPddi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z28kernel_mult_vector_by_numberPddi"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z43__device_stub__kernel_mult_vector_by_numberPddi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z28kernel_mult_vector_by_numberPddi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void add(std::size_t n, const float *x, float *y) {
std::size_t index = blockIdx.x * blockDim.x + threadIdx.x;
std::size_t stride = blockDim.x * gridDim.x;
for (auto i = index; i < n; i += stride) y[i] = x[i] + y[i];
} | code for sm_80
Function : _Z3addmPKfPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x164], PT, P0 ; /* 0x00005900ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0000 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff087624 */
/* 0x000fe400078e00ff */
/*00b0*/ IMAD.SHL.U32 R4, R6.reuse, 0x4, RZ ; /* 0x0000000406047824 */
/* 0x040fe200078e00ff */
/*00c0*/ SHF.L.U64.HI R0, R6, 0x2, R9 ; /* 0x0000000206007819 */
/* 0x000fc80000010209 */
/*00d0*/ IADD3 R2, P0, R4.reuse, c[0x0][0x170], RZ ; /* 0x00005c0004027a10 */
/* 0x041fe40007f1e0ff */
/*00e0*/ IADD3 R4, P1, R4, c[0x0][0x168], RZ ; /* 0x00005a0004047a10 */
/* 0x000fe40007f3e0ff */
/*00f0*/ IADD3.X R3, R0.reuse, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0000037a10 */
/* 0x040fe400007fe4ff */
/*0100*/ IADD3.X R5, R0, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0000057a10 */
/* 0x000fc60000ffe4ff */
/*0110*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*0120*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0130*/ IMAD R11, R8, c[0x0][0xc], RZ ; /* 0x00000300080b7a24 */
/* 0x000fca00078e02ff */
/*0140*/ IADD3 R6, P0, R11, R6, RZ ; /* 0x000000060b067210 */
/* 0x000fca0007f1e0ff */
/*0150*/ IMAD.X R9, RZ, RZ, R9, P0 ; /* 0x000000ffff097224 */
/* 0x000fe200000e0609 */
/*0160*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */
/* 0x000fc80003f06070 */
/*0170*/ ISETP.GE.U32.AND.EX P0, PT, R9, c[0x0][0x164], PT, P0 ; /* 0x0000590009007a0c */
/* 0x000fe20003f06100 */
/*0180*/ FADD R7, R0, R5 ; /* 0x0000000500077221 */
/* 0x004fca0000000000 */
/*0190*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001ee000c101904 */
/*01a0*/ @!P0 BRA 0xb0 ; /* 0xffffff0000008947 */
/* 0x000fea000383ffff */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void add(std::size_t n, const float *x, float *y) {
std::size_t index = blockIdx.x * blockDim.x + threadIdx.x;
std::size_t stride = blockDim.x * gridDim.x;
for (auto i = index; i < n; i += stride) y[i] = x[i] + y[i];
} | .file "tmpxft_00111158_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addmPKfPfmPKfPf
.type _Z26__device_stub__Z3addmPKfPfmPKfPf, @function
_Z26__device_stub__Z3addmPKfPfmPKfPf:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addmPKfPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z3addmPKfPfmPKfPf, .-_Z26__device_stub__Z3addmPKfPfmPKfPf
.globl _Z3addmPKfPf
.type _Z3addmPKfPf, @function
_Z3addmPKfPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addmPKfPfmPKfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3addmPKfPf, .-_Z3addmPKfPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addmPKfPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addmPKfPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void add(std::size_t n, const float *x, float *y) {
std::size_t index = blockIdx.x * blockDim.x + threadIdx.x;
std::size_t stride = blockDim.x * gridDim.x;
for (auto i = index; i < n; i += stride) y[i] = x[i] + y[i];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void add(std::size_t n, const float *x, float *y) {
std::size_t index = blockIdx.x * blockDim.x + threadIdx.x;
std::size_t stride = blockDim.x * gridDim.x;
for (auto i = index; i < n; i += stride) y[i] = x[i] + y[i];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void add(std::size_t n, const float *x, float *y) {
std::size_t index = blockIdx.x * blockDim.x + threadIdx.x;
std::size_t stride = blockDim.x * gridDim.x;
for (auto i = index; i < n; i += stride) y[i] = x[i] + y[i];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addmPKfPf
.globl _Z3addmPKfPf
.p2align 8
.type _Z3addmPKfPf,@function
_Z3addmPKfPf:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x0
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s6, 0xffff
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_3
s_load_b32 s10, s[4:5], 0x0
s_load_b128 s[4:7], s[0:1], 0x8
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_mov_b32 s9, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mov_b32 s1, s9
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s10, s8
s_lshl_b64 s[10:11], s[8:9], 2
.p2align 6
.LBB0_2:
v_add_co_u32 v5, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v1, vcc_lo, v1, s8
global_load_b32 v0, v[5:6], off
global_load_b32 v5, v[7:8], off
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
v_add_co_u32 v3, s0, v3, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v4, s0, s11, v4, s0
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[1:2]
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v5
global_store_b32 v[7:8], v0, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addmPKfPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addmPKfPf, .Lfunc_end0-_Z3addmPKfPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addmPKfPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addmPKfPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void add(std::size_t n, const float *x, float *y) {
std::size_t index = blockIdx.x * blockDim.x + threadIdx.x;
std::size_t stride = blockDim.x * gridDim.x;
for (auto i = index; i < n; i += stride) y[i] = x[i] + y[i];
} | .text
.file "add.hip"
.globl _Z18__device_stub__addmPKfPf # -- Begin function _Z18__device_stub__addmPKfPf
.p2align 4, 0x90
.type _Z18__device_stub__addmPKfPf,@function
_Z18__device_stub__addmPKfPf: # @_Z18__device_stub__addmPKfPf
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addmPKfPf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addmPKfPf, .Lfunc_end0-_Z18__device_stub__addmPKfPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addmPKfPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addmPKfPf,@object # @_Z3addmPKfPf
.section .rodata,"a",@progbits
.globl _Z3addmPKfPf
.p2align 3, 0x0
_Z3addmPKfPf:
.quad _Z18__device_stub__addmPKfPf
.size _Z3addmPKfPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addmPKfPf"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addmPKfPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addmPKfPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addmPKfPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x164], PT, P0 ; /* 0x00005900ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0000 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff087624 */
/* 0x000fe400078e00ff */
/*00b0*/ IMAD.SHL.U32 R4, R6.reuse, 0x4, RZ ; /* 0x0000000406047824 */
/* 0x040fe200078e00ff */
/*00c0*/ SHF.L.U64.HI R0, R6, 0x2, R9 ; /* 0x0000000206007819 */
/* 0x000fc80000010209 */
/*00d0*/ IADD3 R2, P0, R4.reuse, c[0x0][0x170], RZ ; /* 0x00005c0004027a10 */
/* 0x041fe40007f1e0ff */
/*00e0*/ IADD3 R4, P1, R4, c[0x0][0x168], RZ ; /* 0x00005a0004047a10 */
/* 0x000fe40007f3e0ff */
/*00f0*/ IADD3.X R3, R0.reuse, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0000037a10 */
/* 0x040fe400007fe4ff */
/*0100*/ IADD3.X R5, R0, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0000057a10 */
/* 0x000fc60000ffe4ff */
/*0110*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*0120*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0130*/ IMAD R11, R8, c[0x0][0xc], RZ ; /* 0x00000300080b7a24 */
/* 0x000fca00078e02ff */
/*0140*/ IADD3 R6, P0, R11, R6, RZ ; /* 0x000000060b067210 */
/* 0x000fca0007f1e0ff */
/*0150*/ IMAD.X R9, RZ, RZ, R9, P0 ; /* 0x000000ffff097224 */
/* 0x000fe200000e0609 */
/*0160*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */
/* 0x000fc80003f06070 */
/*0170*/ ISETP.GE.U32.AND.EX P0, PT, R9, c[0x0][0x164], PT, P0 ; /* 0x0000590009007a0c */
/* 0x000fe20003f06100 */
/*0180*/ FADD R7, R0, R5 ; /* 0x0000000500077221 */
/* 0x004fca0000000000 */
/*0190*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001ee000c101904 */
/*01a0*/ @!P0 BRA 0xb0 ; /* 0xffffff0000008947 */
/* 0x000fea000383ffff */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addmPKfPf
.globl _Z3addmPKfPf
.p2align 8
.type _Z3addmPKfPf,@function
_Z3addmPKfPf:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x0
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s6, 0xffff
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_3
s_load_b32 s10, s[4:5], 0x0
s_load_b128 s[4:7], s[0:1], 0x8
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_mov_b32 s9, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mov_b32 s1, s9
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s10, s8
s_lshl_b64 s[10:11], s[8:9], 2
.p2align 6
.LBB0_2:
v_add_co_u32 v5, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v1, vcc_lo, v1, s8
global_load_b32 v0, v[5:6], off
global_load_b32 v5, v[7:8], off
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
v_add_co_u32 v3, s0, v3, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v4, s0, s11, v4, s0
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[1:2]
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v5
global_store_b32 v[7:8], v0, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addmPKfPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addmPKfPf, .Lfunc_end0-_Z3addmPKfPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addmPKfPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addmPKfPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00111158_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addmPKfPfmPKfPf
.type _Z26__device_stub__Z3addmPKfPfmPKfPf, @function
_Z26__device_stub__Z3addmPKfPfmPKfPf:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addmPKfPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z3addmPKfPfmPKfPf, .-_Z26__device_stub__Z3addmPKfPfmPKfPf
.globl _Z3addmPKfPf
.type _Z3addmPKfPf, @function
_Z3addmPKfPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addmPKfPfmPKfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3addmPKfPf, .-_Z3addmPKfPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addmPKfPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addmPKfPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add.hip"
.globl _Z18__device_stub__addmPKfPf # -- Begin function _Z18__device_stub__addmPKfPf
.p2align 4, 0x90
.type _Z18__device_stub__addmPKfPf,@function
_Z18__device_stub__addmPKfPf: # @_Z18__device_stub__addmPKfPf
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addmPKfPf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addmPKfPf, .Lfunc_end0-_Z18__device_stub__addmPKfPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addmPKfPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addmPKfPf,@object # @_Z3addmPKfPf
.section .rodata,"a",@progbits
.globl _Z3addmPKfPf
.p2align 3, 0x0
_Z3addmPKfPf:
.quad _Z18__device_stub__addmPKfPf
.size _Z3addmPKfPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addmPKfPf"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addmPKfPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addmPKfPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void StarThetaKernel (double *Qbase, double *Rmed, int nrad, int nsec, double *dq, double dt)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;
double dxtheta, invdxtheta, dqp, dqm;
if (i<nrad && j<nsec){
if (i<nrad){
dxtheta = 2.0*PI/(double)nsec*Rmed[i];
invdxtheta = 1.0/dxtheta;
}
dqm = (Qbase[i*nsec + j] - Qbase[i*nsec + ((j-1)+nsec)%nsec]);
dqp = (Qbase[i*nsec + (j+1)%nsec] - Qbase[i*nsec + j]);
if (dqp * dqm > 0.0)
dq[i*nsec + j] = dqp*dqm/(dqp+dqm)*invdxtheta;
else
dq[i*nsec + j] = 0.0;
}
} | code for sm_80
Function : _Z15StarThetaKernelPdS_iiS_d
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R2, c[0x0][0x4], R5 ; /* 0x0000010002007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IABS R8, c[0x0][0x174] ; /* 0x00005d0000087a13 */
/* 0x000fe20000000000 */
/*00b0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x8 ; /* 0x00000008ff0b7424 */
/* 0x000fe200078e00ff */
/*00c0*/ IADD3 R2, R3.reuse, c[0x0][0x174], RZ ; /* 0x00005d0003027a10 */
/* 0x040fe20007ffe0ff */
/*00d0*/ IMAD R12, R0, c[0x0][0x174], R3 ; /* 0x00005d00000c7a24 */
/* 0x000fe200078e0203 */
/*00e0*/ I2F.RP R6, R8 ; /* 0x0000000800067306 */
/* 0x000e220000209400 */
/*00f0*/ IADD3 R7, R3, 0x1, RZ ; /* 0x0000000103077810 */
/* 0x000fe20007ffe0ff */
/*0100*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0110*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*0120*/ IABS R10, R7 ; /* 0x00000007000a7213 */
/* 0x000fc60000000000 */
/*0130*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0140*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fe40007ffe0ff */
/*0150*/ IABS R6, R2 ; /* 0x0000000200067213 */
/* 0x000fc80000000000 */
/*0160*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0170*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0180*/ IMAD.MOV R9, RZ, RZ, -R5 ; /* 0x000000ffff097224 */
/* 0x002fc800078e0a05 */
/*0190*/ IMAD R9, R9, R8, RZ ; /* 0x0000000809097224 */
/* 0x000fc800078e02ff */
/*01a0*/ IMAD.HI.U32 R5, R5, R9, R4 ; /* 0x0000000905057227 */
/* 0x000fcc00078e0004 */
/*01b0*/ IMAD.HI.U32 R4, R5, R6, RZ ; /* 0x0000000605047227 */
/* 0x000fc800078e00ff */
/*01c0*/ IMAD.HI.U32 R5, R5, R10, RZ ; /* 0x0000000a05057227 */
/* 0x000fc800078e00ff */
/*01d0*/ IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0a05 */
/*01e0*/ IMAD.MOV R9, RZ, RZ, -R4 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0a04 */
/*01f0*/ IMAD R5, R8.reuse, R5, R10 ; /* 0x0000000508057224 */
/* 0x040fe400078e020a */
/*0200*/ IMAD R4, R8, R9, R6 ; /* 0x0000000908047224 */
/* 0x000fc600078e0206 */
/*0210*/ ISETP.GT.U32.AND P1, PT, R8.reuse, R5, PT ; /* 0x000000050800720c */
/* 0x040fe40003f24070 */
/*0220*/ ISETP.GT.U32.AND P0, PT, R8, R4, PT ; /* 0x000000040800720c */
/* 0x000fd60003f04070 */
/*0230*/ @!P1 IMAD.IADD R5, R5, 0x1, -R8.reuse ; /* 0x0000000105059824 */
/* 0x100fe200078e0a08 */
/*0240*/ ISETP.GE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f26270 */
/*0250*/ @!P0 IMAD.IADD R4, R4, 0x1, -R8 ; /* 0x0000000104048824 */
/* 0x000fe200078e0a08 */
/*0260*/ ISETP.GE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f06270 */
/*0270*/ ISETP.GT.U32.AND P3, PT, R8.reuse, R5, PT ; /* 0x000000050800720c */
/* 0x040fe40003f64070 */
/*0280*/ ISETP.GT.U32.AND P2, PT, R8, R4, PT ; /* 0x000000040800720c */
/* 0x000fd60003f44070 */
/*0290*/ @!P3 IMAD.IADD R5, R5, 0x1, -R8.reuse ; /* 0x000000010505b824 */
/* 0x100fe400078e0a08 */
/*02a0*/ @!P2 IMAD.IADD R4, R4, 0x1, -R8 ; /* 0x000000010404a824 */
/* 0x000fe200078e0a08 */
/*02b0*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x174], PT ; /* 0x00005d00ff007a0c */
/* 0x000fe20003f45270 */
/*02c0*/ IMAD.MOV.U32 R2, RZ, RZ, R5 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0005 */
/*02d0*/ LOP3.LUT R5, RZ, c[0x0][0x174], RZ, 0x33, !PT ; /* 0x00005d00ff057a12 */
/* 0x000fe200078e33ff */
/*02e0*/ @!P0 IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff048224 */
/* 0x000fe400078e0a04 */
/*02f0*/ @!P1 IMAD.MOV R2, RZ, RZ, -R2 ; /* 0x000000ffff029224 */
/* 0x000fc600078e0a02 */
/*0300*/ SEL R7, R5.reuse, R4, !P2 ; /* 0x0000000405077207 */
/* 0x040fe40005000000 */
/*0310*/ SEL R5, R5, R2, !P2 ; /* 0x0000000205057207 */
/* 0x000fe20005000000 */
/*0320*/ IMAD.WIDE R2, R12, R11, c[0x0][0x160] ; /* 0x000058000c027625 */
/* 0x000fc800078e020b */
/*0330*/ IMAD R4, R0.reuse, c[0x0][0x174], R7 ; /* 0x00005d0000047a24 */
/* 0x040fe400078e0207 */
/*0340*/ IMAD R6, R0, c[0x0][0x174], R5 ; /* 0x00005d0000067a24 */
/* 0x000fe200078e0205 */
/*0350*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*0360*/ IMAD.WIDE R4, R4, R11, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e020b */
/*0370*/ IMAD.WIDE R6, R6, R11.reuse, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x080fe400078e020b */
/*0380*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*0390*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1b00 */
/*03a0*/ IMAD.WIDE R12, R12, R11, c[0x0][0x178] ; /* 0x00005e000c0c7625 */
/* 0x000fe200078e020b */
/*03b0*/ DADD R18, -R4, R2 ; /* 0x0000000004127229 */
/* 0x004fc80000000102 */
/*03c0*/ DADD R16, -R2, R6 ; /* 0x0000000002107229 */
/* 0x008e0c0000000106 */
/*03d0*/ DMUL R14, R18, R16 ; /* 0x00000010120e7228 */
/* 0x001e0c0000000000 */
/*03e0*/ DSETP.GT.AND P0, PT, R14, RZ, PT ; /* 0x000000ff0e00722a */
/* 0x001e1c0003f04000 */
/*03f0*/ @!P0 STG.E.64 [R12.64], RZ ; /* 0x000000ff0c008986 */
/* 0x0011e2000c101b04 */
/*0400*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0410*/ IMAD.WIDE R10, R0, R11, c[0x0][0x168] ; /* 0x00005a00000a7625 */
/* 0x000fcc00078e020b */
/*0420*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f62000c1e1b00 */
/*0430*/ I2F.F64 R2, c[0x0][0x174] ; /* 0x00005d0000027b12 */
/* 0x000e620000201c00 */
/*0440*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fce00078e00ff */
/*0450*/ MUFU.RCP64H R5, R3 ; /* 0x0000000300057308 */
/* 0x002e640000001800 */
/*0460*/ DFMA R6, -R2, R4, 1 ; /* 0x3ff000000206742b */
/* 0x002e4c0000000104 */
/*0470*/ DFMA R6, R6, R6, R6 ; /* 0x000000060606722b */
/* 0x002e4c0000000006 */
/*0480*/ DFMA R6, R4, R6, R4 ; /* 0x000000060406722b */
/* 0x002e4c0000000004 */
/*0490*/ DFMA R4, -R2, R6, 1 ; /* 0x3ff000000204742b */
/* 0x002e4c0000000106 */
/*04a0*/ DFMA R4, R6, R4, R6 ; /* 0x000000040604722b */
/* 0x002e4c0000000006 */
/*04b0*/ DMUL R6, R4, c[0x2][0x0] ; /* 0x0080000004067a28 */
/* 0x002e4c0000000000 */
/*04c0*/ DFMA R8, -R2, R6, c[0x2][0x0] ; /* 0x008000000208762b */
/* 0x002e4c0000000106 */
/*04d0*/ DFMA R4, R4, R8, R6 ; /* 0x000000080404722b */
/* 0x002e540000000006 */
/*04e0*/ FFMA R0, RZ, R3, R5 ; /* 0x00000003ff007223 */
/* 0x002fca0000000005 */
/*04f0*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*0500*/ @P0 BRA 0x570 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*0510*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0002 */
/*0520*/ MOV R0, 0x570 ; /* 0x0000057000007802 */
/* 0x000fe20000000f00 */
/*0530*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0003 */
/*0540*/ IMAD.MOV.U32 R8, RZ, RZ, 0x54442d18 ; /* 0x54442d18ff087424 */
/* 0x000fe400078e00ff */
/*0550*/ IMAD.MOV.U32 R9, RZ, RZ, 0x401921fb ; /* 0x401921fbff097424 */
/* 0x000fe400078e00ff */
/*0560*/ CALL.REL.NOINC 0xb00 ; /* 0x0000059000007944 */
/* 0x021fea0003c00000 */
/*0570*/ DMUL R6, R10, R4 ; /* 0x000000040a067228 */
/* 0x020e620000000000 */
/*0580*/ BSSY B0, 0x670 ; /* 0x000000e000007945 */
/* 0x000fea0003800000 */
/*0590*/ MUFU.RCP64H R3, R7 ; /* 0x0000000700037308 */
/* 0x002e680000001800 */
/*05a0*/ IADD3 R2, R7, 0x300402, RZ ; /* 0x0030040207027810 */
/* 0x000fc80007ffe0ff */
/*05b0*/ FSETP.GEU.AND P0, PT, |R2|, 5.8789094863358348022e-39, PT ; /* 0x004004020200780b */
/* 0x000fe40003f0e200 */
/*05c0*/ DFMA R4, -R6, R2, 1 ; /* 0x3ff000000604742b */
/* 0x002e4c0000000102 */
/*05d0*/ DFMA R4, R4, R4, R4 ; /* 0x000000040404722b */
/* 0x002e4c0000000004 */
/*05e0*/ DFMA R4, R2, R4, R2 ; /* 0x000000040204722b */
/* 0x002e4c0000000002 */
/*05f0*/ DFMA R10, -R6, R4, 1 ; /* 0x3ff00000060a742b */
/* 0x002e4c0000000104 */
/*0600*/ DFMA R10, R4, R10, R4 ; /* 0x0000000a040a722b */
/* 0x0022a20000000004 */
/*0610*/ @P0 BRA 0x660 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0620*/ LOP3.LUT R0, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07007812 */
/* 0x000fc800078ec0ff */
/*0630*/ IADD3 R9, R0, -0x100000, RZ ; /* 0xfff0000000097810 */
/* 0x000fe40007ffe0ff */
/*0640*/ MOV R0, 0x660 ; /* 0x0000066000007802 */
/* 0x000fe40000000f00 */
/*0650*/ CALL.REL.NOINC 0x830 ; /* 0x000001d000007944 */
/* 0x007fea0003c00000 */
/*0660*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0670*/ DADD R16, R18, R16 ; /* 0x0000000012107229 */
/* 0x000ee20000000010 */
/*0680*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fe200078e00ff */
/*0690*/ FSETP.GEU.AND P1, PT, |R15|, 6.5827683646048100446e-37, PT ; /* 0x036000000f00780b */
/* 0x000fe20003f2e200 */
/*06a0*/ BSSY B0, 0x800 ; /* 0x0000015000007945 */
/* 0x000fe60003800000 */
/*06b0*/ MUFU.RCP64H R3, R17 ; /* 0x0000001100037308 */
/* 0x008ee40000001800 */
/*06c0*/ DFMA R4, -R16, R2, 1 ; /* 0x3ff000001004742b */
/* 0x00ae4c0000000102 */
/*06d0*/ DFMA R4, R4, R4, R4 ; /* 0x000000040404722b */
/* 0x002e4c0000000004 */
/*06e0*/ DFMA R4, R2, R4, R2 ; /* 0x000000040204722b */
/* 0x002e4c0000000002 */
/*06f0*/ DFMA R2, -R16, R4, 1 ; /* 0x3ff000001002742b */
/* 0x002e4c0000000104 */
/*0700*/ DFMA R2, R4, R2, R4 ; /* 0x000000020402722b */
/* 0x002e4c0000000004 */
/*0710*/ DMUL R4, R14, R2 ; /* 0x000000020e047228 */
/* 0x002e4c0000000000 */
/*0720*/ DFMA R6, -R16, R4, R14 ; /* 0x000000041006722b */
/* 0x002e4c000000010e */
/*0730*/ DFMA R2, R2, R6, R4 ; /* 0x000000060202722b */
/* 0x002e540000000004 */
/*0740*/ FFMA R0, RZ, R17, R3 ; /* 0x00000011ff007223 */
/* 0x002fca0000000003 */
/*0750*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*0760*/ @P0 BRA P1, 0x7f0 ; /* 0x0000008000000947 */
/* 0x000fea0000800000 */
/*0770*/ IMAD.MOV.U32 R8, RZ, RZ, R14 ; /* 0x000000ffff087224 */
/* 0x000fe200078e000e */
/*0780*/ MOV R0, 0x7d0 ; /* 0x000007d000007802 */
/* 0x000fe20000000f00 */
/*0790*/ IMAD.MOV.U32 R9, RZ, RZ, R15 ; /* 0x000000ffff097224 */
/* 0x000fe400078e000f */
/*07a0*/ IMAD.MOV.U32 R6, RZ, RZ, R16 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0010 */
/*07b0*/ IMAD.MOV.U32 R5, RZ, RZ, R17 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0011 */
/*07c0*/ CALL.REL.NOINC 0xb00 ; /* 0x0000033000007944 */
/* 0x005fea0003c00000 */
/*07d0*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0004 */
/*07e0*/ IMAD.MOV.U32 R3, RZ, RZ, R5 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0005 */
/*07f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0800*/ DMUL R10, R2, R10 ; /* 0x0000000a020a7228 */
/* 0x004e4e0000000000 */
/*0810*/ STG.E.64 [R12.64], R10 ; /* 0x0000000a0c007986 */
/* 0x002fe2000c101b04 */
/*0820*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0830*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0006 */
/*0840*/ BSSY B1, 0xab0 ; /* 0x0000026000017945 */
/* 0x000fe20003800000 */
/*0850*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fcc00078e0007 */
/*0860*/ DSETP.GTU.AND P0, PT, |R2|, +INF , PT ; /* 0x7ff000000200742a */
/* 0x000e1c0003f0c200 */
/*0870*/ @P0 BRA 0xa80 ; /* 0x0000020000000947 */
/* 0x001fea0003800000 */
/*0880*/ LOP3.LUT R6, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07067812 */
/* 0x000fc800078ec0ff */
/*0890*/ IADD3 R4, R6, -0x1, RZ ; /* 0xffffffff06047810 */
/* 0x000fc80007ffe0ff */
/*08a0*/ ISETP.GE.U32.AND P0, PT, R4, 0x7fefffff, PT ; /* 0x7fefffff0400780c */
/* 0x000fda0003f06070 */
/*08b0*/ @P0 LOP3.LUT R5, R3, 0x7ff00000, RZ, 0x3c, !PT ; /* 0x7ff0000003050812 */
/* 0x000fe200078e3cff */
/*08c0*/ @P0 IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff040224 */
/* 0x000fe200078e00ff */
/*08d0*/ @P0 BRA 0xaa0 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*08e0*/ ISETP.GE.U32.AND P0, PT, R6, 0x1000001, PT ; /* 0x010000010600780c */
/* 0x000fda0003f06070 */
/*08f0*/ @!P0 BRA 0x9e0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0900*/ IADD3 R5, R3, -0x3fe00000, RZ ; /* 0xc020000003057810 */
/* 0x000fe20007ffe0ff */
/*0910*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0002 */
/*0920*/ IMAD.MOV.U32 R6, RZ, RZ, R9 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0009 */
/*0930*/ MUFU.RCP64H R7, R5 ; /* 0x0000000500077308 */
/* 0x000e2a0000001800 */
/*0940*/ DFMA R8, -R4, R6, 1 ; /* 0x3ff000000408742b */
/* 0x001e0c0000000106 */
/*0950*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*0960*/ DFMA R8, R6, R8, R6 ; /* 0x000000080608722b */
/* 0x001e0c0000000006 */
/*0970*/ DFMA R6, -R4, R8, 1 ; /* 0x3ff000000406742b */
/* 0x001e0c0000000108 */
/*0980*/ DFMA R6, R8, R6, R8 ; /* 0x000000060806722b */
/* 0x001e0c0000000008 */
/*0990*/ DMUL R6, R6, 2.2250738585072013831e-308 ; /* 0x0010000006067828 */
/* 0x001e0c0000000000 */
/*09a0*/ DFMA R2, -R2, R6, 1 ; /* 0x3ff000000202742b */
/* 0x001e0c0000000106 */
/*09b0*/ DFMA R2, R2, R2, R2 ; /* 0x000000020202722b */
/* 0x001e0c0000000002 */
/*09c0*/ DFMA R4, R6, R2, R6 ; /* 0x000000020604722b */
/* 0x0010620000000006 */
/*09d0*/ BRA 0xaa0 ; /* 0x000000c000007947 */
/* 0x000fea0003800000 */
/*09e0*/ DMUL R2, R2, 8.11296384146066816958e+31 ; /* 0x4690000002027828 */
/* 0x000e220000000000 */
/*09f0*/ IMAD.MOV.U32 R4, RZ, RZ, R9 ; /* 0x000000ffff047224 */
/* 0x000fca00078e0009 */
/*0a00*/ MUFU.RCP64H R5, R3 ; /* 0x0000000300057308 */
/* 0x001e240000001800 */
/*0a10*/ DFMA R6, -R2, R4, 1 ; /* 0x3ff000000206742b */
/* 0x001e0c0000000104 */
/*0a20*/ DFMA R6, R6, R6, R6 ; /* 0x000000060606722b */
/* 0x001e0c0000000006 */
/*0a30*/ DFMA R6, R4, R6, R4 ; /* 0x000000060406722b */
/* 0x001e0c0000000004 */
/*0a40*/ DFMA R4, -R2, R6, 1 ; /* 0x3ff000000204742b */
/* 0x001e0c0000000106 */
/*0a50*/ DFMA R4, R6, R4, R6 ; /* 0x000000040604722b */
/* 0x001e0c0000000006 */
/*0a60*/ DMUL R4, R4, 8.11296384146066816958e+31 ; /* 0x4690000004047828 */
/* 0x001e220000000000 */
/*0a70*/ BRA 0xaa0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0a80*/ LOP3.LUT R5, R3, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000003057812 */
/* 0x000fe200078efcff */
/*0a90*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0002 */
/*0aa0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0ab0*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x001fe400078e0000 */
/*0ac0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fe400078e00ff */
/*0ad0*/ IMAD.MOV.U32 R10, RZ, RZ, R4 ; /* 0x000000ffff0a7224 */
/* 0x002fe400078e0004 */
/*0ae0*/ IMAD.MOV.U32 R11, RZ, RZ, R5 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0005 */
/*0af0*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff50002007950 */
/* 0x000fec0003c3ffff */
/*0b00*/ FSETP.GEU.AND P2, PT, |R9|, 1.469367938527859385e-39, PT ; /* 0x001000000900780b */
/* 0x000fe20003f4e200 */
/*0b10*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0006 */
/*0b20*/ FSETP.GEU.AND P0, PT, |R5|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000500780b */
/* 0x040fe20003f0e200 */
/*0b30*/ IMAD.MOV.U32 R20, RZ, RZ, R8 ; /* 0x000000ffff147224 */
/* 0x000fe200078e0008 */
/*0b40*/ LOP3.LUT R7, R5, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff05077812 */
/* 0x000fe200078ec0ff */
/*0b50*/ IMAD.MOV.U32 R22, RZ, RZ, 0x1 ; /* 0x00000001ff167424 */
/* 0x000fe200078e00ff */
/*0b60*/ LOP3.LUT R2, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009027812 */
/* 0x000fe200078ec0ff */
/*0b70*/ BSSY B1, 0x1090 ; /* 0x0000051000017945 */
/* 0x000fe20003800000 */
/*0b80*/ LOP3.LUT R7, R7, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000007077812 */
/* 0x000fc400078efcff */
/*0b90*/ LOP3.LUT R29, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000051d7812 */
/* 0x000fc600078ec0ff */
/*0ba0*/ @!P2 LOP3.LUT R3, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000503a812 */
/* 0x000fe200078ec0ff */
/*0bb0*/ @!P2 IMAD.MOV.U32 R24, RZ, RZ, RZ ; /* 0x000000ffff18a224 */
/* 0x000fe200078e00ff */
/*0bc0*/ @!P0 DMUL R6, R4, 8.98846567431157953865e+307 ; /* 0x7fe0000004068828 */
/* 0x000e220000000000 */
/*0bd0*/ ISETP.GE.U32.AND P1, PT, R2.reuse, R29, PT ; /* 0x0000001d0200720c */
/* 0x040fe40003f26070 */
/*0be0*/ @!P2 ISETP.GE.U32.AND P3, PT, R2, R3, PT ; /* 0x000000030200a20c */
/* 0x000fe20003f66070 */
/*0bf0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff037424 */
/* 0x000fe400078e00ff */
/*0c00*/ MUFU.RCP64H R23, R7 ; /* 0x0000000700177308 */
/* 0x001e260000001800 */
/*0c10*/ @!P2 SEL R25, R3, 0x63400000, !P3 ; /* 0x634000000319a807 */
/* 0x000fc40005800000 */
/*0c20*/ SEL R21, R3, 0x63400000, !P1 ; /* 0x6340000003157807 */
/* 0x000fe40004800000 */
/*0c30*/ @!P2 LOP3.LUT R25, R25, 0x80000000, R9.reuse, 0xf8, !PT ; /* 0x800000001919a812 */
/* 0x100fe400078ef809 */
/*0c40*/ LOP3.LUT R21, R21, 0x800fffff, R9, 0xf8, !PT ; /* 0x800fffff15157812 */
/* 0x000fe400078ef809 */
/*0c50*/ @!P2 LOP3.LUT R25, R25, 0x100000, RZ, 0xfc, !PT ; /* 0x001000001919a812 */
/* 0x000fe400078efcff */
/*0c60*/ @!P0 LOP3.LUT R29, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000071d8812 */
/* 0x000fc800078ec0ff */
/*0c70*/ @!P2 DFMA R20, R20, 2, -R24 ; /* 0x400000001414a82b */
/* 0x000fc80000000818 */
/*0c80*/ DFMA R24, R22, -R6, 1 ; /* 0x3ff000001618742b */
/* 0x001e0c0000000806 */
/*0c90*/ DFMA R24, R24, R24, R24 ; /* 0x000000181818722b */
/* 0x001e0c0000000018 */
/*0ca0*/ DFMA R24, R22, R24, R22 ; /* 0x000000181618722b */
/* 0x001e0c0000000016 */
/*0cb0*/ DFMA R22, R24, -R6, 1 ; /* 0x3ff000001816742b */
/* 0x001e0c0000000806 */
/*0cc0*/ DFMA R22, R24, R22, R24 ; /* 0x000000161816722b */
/* 0x001e0c0000000018 */
/*0cd0*/ DMUL R24, R22, R20 ; /* 0x0000001416187228 */
/* 0x001e0c0000000000 */
/*0ce0*/ DFMA R26, R24, -R6, R20 ; /* 0x80000006181a722b */
/* 0x001e0c0000000014 */
/*0cf0*/ DFMA R26, R22, R26, R24 ; /* 0x0000001a161a722b */
/* 0x0010640000000018 */
/*0d00*/ IMAD.MOV.U32 R22, RZ, RZ, R2 ; /* 0x000000ffff167224 */
/* 0x001fe200078e0002 */
/*0d10*/ @!P2 LOP3.LUT R22, R21, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000001516a812 */
/* 0x000fc800078ec0ff */
/*0d20*/ IADD3 R23, R22, -0x1, RZ ; /* 0xffffffff16177810 */
/* 0x000fc80007ffe0ff */
/*0d30*/ ISETP.GT.U32.AND P0, PT, R23, 0x7feffffe, PT ; /* 0x7feffffe1700780c */
/* 0x000fe40003f04070 */
/*0d40*/ IADD3 R23, R29, -0x1, RZ ; /* 0xffffffff1d177810 */
/* 0x000fc80007ffe0ff */
/*0d50*/ ISETP.GT.U32.OR P0, PT, R23, 0x7feffffe, P0 ; /* 0x7feffffe1700780c */
/* 0x000fda0000704470 */
/*0d60*/ @P0 BRA 0xf30 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0d70*/ LOP3.LUT R9, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005097812 */
/* 0x002fc800078ec0ff */
/*0d80*/ ISETP.GE.U32.AND P0, PT, R2.reuse, R9, PT ; /* 0x000000090200720c */
/* 0x040fe20003f06070 */
/*0d90*/ IMAD.IADD R8, R2, 0x1, -R9 ; /* 0x0000000102087824 */
/* 0x000fc600078e0a09 */
/*0da0*/ SEL R3, R3, 0x63400000, !P0 ; /* 0x6340000003037807 */
/* 0x000fe40004000000 */
/*0db0*/ IMNMX R8, R8, -0x46a00000, !PT ; /* 0xb960000008087817 */
/* 0x000fc80007800200 */
/*0dc0*/ IMNMX R8, R8, 0x46a00000, PT ; /* 0x46a0000008087817 */
/* 0x000fca0003800200 */
/*0dd0*/ IMAD.IADD R22, R8, 0x1, -R3 ; /* 0x0000000108167824 */
/* 0x000fe400078e0a03 */
/*0de0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fc600078e00ff */
/*0df0*/ IADD3 R9, R22, 0x7fe00000, RZ ; /* 0x7fe0000016097810 */
/* 0x000fcc0007ffe0ff */
/*0e00*/ DMUL R2, R26, R8 ; /* 0x000000081a027228 */
/* 0x000e140000000000 */
/*0e10*/ FSETP.GTU.AND P0, PT, |R3|, 1.469367938527859385e-39, PT ; /* 0x001000000300780b */
/* 0x001fda0003f0c200 */
/*0e20*/ @P0 BRA 0x1080 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0e30*/ DFMA R6, R26, -R6, R20 ; /* 0x800000061a06722b */
/* 0x000e220000000014 */
/*0e40*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fd200078e00ff */
/*0e50*/ FSETP.NEU.AND P0, PT, R7.reuse, RZ, PT ; /* 0x000000ff0700720b */
/* 0x041fe40003f0d000 */
/*0e60*/ LOP3.LUT R5, R7, 0x80000000, R5, 0x48, !PT ; /* 0x8000000007057812 */
/* 0x000fc800078e4805 */
/*0e70*/ LOP3.LUT R9, R5, R9, RZ, 0xfc, !PT ; /* 0x0000000905097212 */
/* 0x000fce00078efcff */
/*0e80*/ @!P0 BRA 0x1080 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0e90*/ IMAD.MOV R7, RZ, RZ, -R22 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0a16 */
/*0ea0*/ DMUL.RP R8, R26, R8 ; /* 0x000000081a087228 */
/* 0x000e220000008000 */
/*0eb0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fcc00078e00ff */
/*0ec0*/ DFMA R6, R2, -R6, R26 ; /* 0x800000060206722b */
/* 0x000e46000000001a */
/*0ed0*/ LOP3.LUT R5, R9, R5, RZ, 0x3c, !PT ; /* 0x0000000509057212 */
/* 0x001fc600078e3cff */
/*0ee0*/ IADD3 R6, -R22, -0x43300000, RZ ; /* 0xbcd0000016067810 */
/* 0x002fc80007ffe1ff */
/*0ef0*/ FSETP.NEU.AND P0, PT, |R7|, R6, PT ; /* 0x000000060700720b */
/* 0x000fc80003f0d200 */
/*0f00*/ FSEL R2, R8, R2, !P0 ; /* 0x0000000208027208 */
/* 0x000fe40004000000 */
/*0f10*/ FSEL R3, R5, R3, !P0 ; /* 0x0000000305037208 */
/* 0x000fe20004000000 */
/*0f20*/ BRA 0x1080 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0f30*/ DSETP.NAN.AND P0, PT, R8, R8, PT ; /* 0x000000080800722a */
/* 0x002e1c0003f08000 */
/*0f40*/ @P0 BRA 0x1060 ; /* 0x0000011000000947 */
/* 0x001fea0003800000 */
/*0f50*/ DSETP.NAN.AND P0, PT, R4, R4, PT ; /* 0x000000040400722a */
/* 0x000e1c0003f08000 */
/*0f60*/ @P0 BRA 0x1030 ; /* 0x000000c000000947 */
/* 0x001fea0003800000 */
/*0f70*/ ISETP.NE.AND P0, PT, R22, R29, PT ; /* 0x0000001d1600720c */
/* 0x000fe20003f05270 */
/*0f80*/ IMAD.MOV.U32 R2, RZ, RZ, 0x0 ; /* 0x00000000ff027424 */
/* 0x000fe400078e00ff */
/*0f90*/ IMAD.MOV.U32 R3, RZ, RZ, -0x80000 ; /* 0xfff80000ff037424 */
/* 0x000fd400078e00ff */
/*0fa0*/ @!P0 BRA 0x1080 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0fb0*/ ISETP.NE.AND P0, PT, R22, 0x7ff00000, PT ; /* 0x7ff000001600780c */
/* 0x000fe40003f05270 */
/*0fc0*/ LOP3.LUT R3, R9, 0x80000000, R5, 0x48, !PT ; /* 0x8000000009037812 */
/* 0x000fe400078e4805 */
/*0fd0*/ ISETP.EQ.OR P0, PT, R29, RZ, !P0 ; /* 0x000000ff1d00720c */
/* 0x000fda0004702670 */
/*0fe0*/ @P0 LOP3.LUT R4, R3, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000003040812 */
/* 0x000fe200078efcff */
/*0ff0*/ @!P0 IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff028224 */
/* 0x000fe400078e00ff */
/*1000*/ @P0 IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff020224 */
/* 0x000fe400078e00ff */
/*1010*/ @P0 IMAD.MOV.U32 R3, RZ, RZ, R4 ; /* 0x000000ffff030224 */
/* 0x000fe200078e0004 */
/*1020*/ BRA 0x1080 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*1030*/ LOP3.LUT R3, R5, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000005037812 */
/* 0x000fe200078efcff */
/*1040*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0004 */
/*1050*/ BRA 0x1080 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*1060*/ LOP3.LUT R3, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000009037812 */
/* 0x000fe200078efcff */
/*1070*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0008 */
/*1080*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*1090*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0002 */
/*10a0*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x000fc400078e0003 */
/*10b0*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0000 */
/*10c0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*10d0*/ RET.REL.NODEC R2 0x0 ; /* 0xffffef2002007950 */
/* 0x000fea0003c3ffff */
/*10e0*/ BRA 0x10e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void StarThetaKernel (double *Qbase, double *Rmed, int nrad, int nsec, double *dq, double dt)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;
double dxtheta, invdxtheta, dqp, dqm;
if (i<nrad && j<nsec){
if (i<nrad){
dxtheta = 2.0*PI/(double)nsec*Rmed[i];
invdxtheta = 1.0/dxtheta;
}
dqm = (Qbase[i*nsec + j] - Qbase[i*nsec + ((j-1)+nsec)%nsec]);
dqp = (Qbase[i*nsec + (j+1)%nsec] - Qbase[i*nsec + j]);
if (dqp * dqm > 0.0)
dq[i*nsec + j] = dqp*dqm/(dqp+dqm)*invdxtheta;
else
dq[i*nsec + j] = 0.0;
}
} | .file "tmpxft_000818b4_00000000-6_StarThetaKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z15StarThetaKernelPdS_iiS_dPdS_iiS_d
.type _Z42__device_stub__Z15StarThetaKernelPdS_iiS_dPdS_iiS_d, @function
_Z42__device_stub__Z15StarThetaKernelPdS_iiS_dPdS_iiS_d:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movq %r8, 16(%rsp)
movsd %xmm0, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15StarThetaKernelPdS_iiS_d(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z15StarThetaKernelPdS_iiS_dPdS_iiS_d, .-_Z42__device_stub__Z15StarThetaKernelPdS_iiS_dPdS_iiS_d
.globl _Z15StarThetaKernelPdS_iiS_d
.type _Z15StarThetaKernelPdS_iiS_d, @function
_Z15StarThetaKernelPdS_iiS_d:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z15StarThetaKernelPdS_iiS_dPdS_iiS_d
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15StarThetaKernelPdS_iiS_d, .-_Z15StarThetaKernelPdS_iiS_d
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15StarThetaKernelPdS_iiS_d"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15StarThetaKernelPdS_iiS_d(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void StarThetaKernel (double *Qbase, double *Rmed, int nrad, int nsec, double *dq, double dt)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;
double dxtheta, invdxtheta, dqp, dqm;
if (i<nrad && j<nsec){
if (i<nrad){
dxtheta = 2.0*PI/(double)nsec*Rmed[i];
invdxtheta = 1.0/dxtheta;
}
dqm = (Qbase[i*nsec + j] - Qbase[i*nsec + ((j-1)+nsec)%nsec]);
dqp = (Qbase[i*nsec + (j+1)%nsec] - Qbase[i*nsec + j]);
if (dqp * dqm > 0.0)
dq[i*nsec + j] = dqp*dqm/(dqp+dqm)*invdxtheta;
else
dq[i*nsec + j] = 0.0;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void StarThetaKernel (double *Qbase, double *Rmed, int nrad, int nsec, double *dq, double dt)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;
double dxtheta, invdxtheta, dqp, dqm;
if (i<nrad && j<nsec){
if (i<nrad){
dxtheta = 2.0*PI/(double)nsec*Rmed[i];
invdxtheta = 1.0/dxtheta;
}
dqm = (Qbase[i*nsec + j] - Qbase[i*nsec + ((j-1)+nsec)%nsec]);
dqp = (Qbase[i*nsec + (j+1)%nsec] - Qbase[i*nsec + j]);
if (dqp * dqm > 0.0)
dq[i*nsec + j] = dqp*dqm/(dqp+dqm)*invdxtheta;
else
dq[i*nsec + j] = 0.0;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void StarThetaKernel (double *Qbase, double *Rmed, int nrad, int nsec, double *dq, double dt)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;
double dxtheta, invdxtheta, dqp, dqm;
if (i<nrad && j<nsec){
if (i<nrad){
dxtheta = 2.0*PI/(double)nsec*Rmed[i];
invdxtheta = 1.0/dxtheta;
}
dqm = (Qbase[i*nsec + j] - Qbase[i*nsec + ((j-1)+nsec)%nsec]);
dqp = (Qbase[i*nsec + (j+1)%nsec] - Qbase[i*nsec + j]);
if (dqp * dqm > 0.0)
dq[i*nsec + j] = dqp*dqm/(dqp+dqm)*invdxtheta;
else
dq[i*nsec + j] = 0.0;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15StarThetaKernelPdS_iiS_d
.globl _Z15StarThetaKernelPdS_iiS_d
.p2align 8
.type _Z15StarThetaKernelPdS_iiS_d,@function
_Z15StarThetaKernelPdS_iiS_d:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x10
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s5, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
v_cmp_gt_i32_e64 s2, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_4
s_ashr_i32 s2, s3, 31
v_add3_u32 v3, s3, -1, v1
s_add_i32 s4, s3, s2
v_mul_lo_u32 v8, v0, s3
s_xor_b32 s2, s4, s2
v_add_nc_u32_e32 v5, 1, v1
v_cvt_f32_u32_e32 v2, s2
s_sub_i32 s4, 0, s2
v_ashrrev_i32_e32 v6, 31, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v7, 31, v5
v_rcp_iflag_f32_e32 v2, v2
v_add_nc_u32_e32 v1, v8, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v3, v3, v6
v_add_nc_u32_e32 v5, v5, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_xor_b32_e32 v3, v3, v6
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, s4, v2
s_load_b64 s[4:5], s[0:1], 0x0
v_mul_hi_u32 v4, v2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v2, v4
v_xor_b32_e32 v4, v5, v7
v_mul_hi_u32 v5, v3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v2, v4, v2
v_mul_lo_u32 v5, v5, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v2, s2
v_sub_nc_u32_e32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v4, v2
v_subrev_nc_u32_e32 v4, s2, v3
v_cmp_le_u32_e32 vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v5, s2, v2
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_subrev_nc_u32_e32 v4, s2, v3
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_subrev_nc_u32_e32 v5, s2, v2
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_xor_b32_e32 v3, v3, v6
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v3, v6
v_xor_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, v3, v8
v_sub_nc_u32_e32 v5, v2, v7
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v6, v5, v8
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[2:3], 3, v[1:2]
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[4:5], 3, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v8, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[6:7], 3, v[6:7]
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
s_clause 0x2
global_load_b64 v[8:9], v[8:9], off
global_load_b64 v[4:5], v[4:5], off
global_load_b64 v[10:11], v[6:7], off
s_mov_b32 s4, exec_lo
s_waitcnt vmcnt(1)
v_add_f64 v[6:7], v[8:9], -v[4:5]
s_waitcnt vmcnt(0)
v_add_f64 v[8:9], v[10:11], -v[8:9]
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[4:5], v[6:7], v[8:9]
v_cmpx_lt_f64_e32 0, v[4:5]
s_cbranch_execz .LBB0_3
v_cvt_f64_i32_e32 v[10:11], s3
s_mov_b32 s3, 0x401921fb
s_mov_b32 s2, 0x54442d18
s_load_b64 s[6:7], s[0:1], 0x8
v_ashrrev_i32_e32 v1, 31, v0
v_add_f64 v[6:7], v[6:7], v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b64 v[0:1], v[0:1], off
v_div_scale_f64 v[12:13], null, v[10:11], v[10:11], s[2:3]
v_div_scale_f64 v[18:19], vcc_lo, s[2:3], v[10:11], s[2:3]
v_rcp_f64_e32 v[14:15], v[12:13]
s_waitcnt_depctr 0xfff
v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
v_mul_f64 v[16:17], v[18:19], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], -v[12:13], v[16:17], v[18:19]
v_div_fmas_f64 v[12:13], v[12:13], v[14:15], v[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[10:11], v[12:13], v[10:11], s[2:3]
s_waitcnt vmcnt(0)
v_mul_f64 v[0:1], v[10:11], v[0:1]
v_div_scale_f64 v[10:11], null, v[6:7], v[6:7], v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_scale_f64 v[8:9], null, v[0:1], v[0:1], 1.0
v_rcp_f64_e32 v[14:15], v[10:11]
v_div_scale_f64 v[20:21], vcc_lo, 1.0, v[0:1], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_rcp_f64_e32 v[12:13], v[8:9]
s_waitcnt_depctr 0xfff
v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
v_div_scale_f64 v[16:17], s2, v[4:5], v[6:7], v[4:5]
v_mul_f64 v[18:19], v[20:21], v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[22:23], v[16:17], v[14:15]
v_fma_f64 v[8:9], -v[8:9], v[18:19], v[20:21]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[10:11], -v[10:11], v[22:23], v[16:17]
v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[18:19]
s_mov_b32 vcc_lo, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[22:23]
v_div_fixup_f64 v[0:1], v[8:9], v[0:1], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[4:5], v[10:11], v[6:7], v[4:5]
v_mul_f64 v[10:11], v[4:5], v[0:1]
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s4
s_load_b64 s[0:1], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_b64 v[0:1], v[10:11], off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15StarThetaKernelPdS_iiS_d
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 24
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15StarThetaKernelPdS_iiS_d, .Lfunc_end0-_Z15StarThetaKernelPdS_iiS_d
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15StarThetaKernelPdS_iiS_d
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15StarThetaKernelPdS_iiS_d.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 24
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void StarThetaKernel (double *Qbase, double *Rmed, int nrad, int nsec, double *dq, double dt)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;
double dxtheta, invdxtheta, dqp, dqm;
if (i<nrad && j<nsec){
if (i<nrad){
dxtheta = 2.0*PI/(double)nsec*Rmed[i];
invdxtheta = 1.0/dxtheta;
}
dqm = (Qbase[i*nsec + j] - Qbase[i*nsec + ((j-1)+nsec)%nsec]);
dqp = (Qbase[i*nsec + (j+1)%nsec] - Qbase[i*nsec + j]);
if (dqp * dqm > 0.0)
dq[i*nsec + j] = dqp*dqm/(dqp+dqm)*invdxtheta;
else
dq[i*nsec + j] = 0.0;
}
} | .text
.file "StarThetaKernel.hip"
.globl _Z30__device_stub__StarThetaKernelPdS_iiS_d # -- Begin function _Z30__device_stub__StarThetaKernelPdS_iiS_d
.p2align 4, 0x90
.type _Z30__device_stub__StarThetaKernelPdS_iiS_d,@function
_Z30__device_stub__StarThetaKernelPdS_iiS_d: # @_Z30__device_stub__StarThetaKernelPdS_iiS_d
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %r8, 72(%rsp)
movsd %xmm0, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15StarThetaKernelPdS_iiS_d, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z30__device_stub__StarThetaKernelPdS_iiS_d, .Lfunc_end0-_Z30__device_stub__StarThetaKernelPdS_iiS_d
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15StarThetaKernelPdS_iiS_d, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15StarThetaKernelPdS_iiS_d,@object # @_Z15StarThetaKernelPdS_iiS_d
.section .rodata,"a",@progbits
.globl _Z15StarThetaKernelPdS_iiS_d
.p2align 3, 0x0
_Z15StarThetaKernelPdS_iiS_d:
.quad _Z30__device_stub__StarThetaKernelPdS_iiS_d
.size _Z15StarThetaKernelPdS_iiS_d, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15StarThetaKernelPdS_iiS_d"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__StarThetaKernelPdS_iiS_d
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15StarThetaKernelPdS_iiS_d
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000818b4_00000000-6_StarThetaKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z15StarThetaKernelPdS_iiS_dPdS_iiS_d
.type _Z42__device_stub__Z15StarThetaKernelPdS_iiS_dPdS_iiS_d, @function
_Z42__device_stub__Z15StarThetaKernelPdS_iiS_dPdS_iiS_d:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movq %r8, 16(%rsp)
movsd %xmm0, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15StarThetaKernelPdS_iiS_d(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z15StarThetaKernelPdS_iiS_dPdS_iiS_d, .-_Z42__device_stub__Z15StarThetaKernelPdS_iiS_dPdS_iiS_d
.globl _Z15StarThetaKernelPdS_iiS_d
.type _Z15StarThetaKernelPdS_iiS_d, @function
_Z15StarThetaKernelPdS_iiS_d:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z15StarThetaKernelPdS_iiS_dPdS_iiS_d
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15StarThetaKernelPdS_iiS_d, .-_Z15StarThetaKernelPdS_iiS_d
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15StarThetaKernelPdS_iiS_d"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15StarThetaKernelPdS_iiS_d(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "StarThetaKernel.hip"
.globl _Z30__device_stub__StarThetaKernelPdS_iiS_d # -- Begin function _Z30__device_stub__StarThetaKernelPdS_iiS_d
.p2align 4, 0x90
.type _Z30__device_stub__StarThetaKernelPdS_iiS_d,@function
_Z30__device_stub__StarThetaKernelPdS_iiS_d: # @_Z30__device_stub__StarThetaKernelPdS_iiS_d
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %r8, 72(%rsp)
movsd %xmm0, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15StarThetaKernelPdS_iiS_d, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z30__device_stub__StarThetaKernelPdS_iiS_d, .Lfunc_end0-_Z30__device_stub__StarThetaKernelPdS_iiS_d
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15StarThetaKernelPdS_iiS_d, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15StarThetaKernelPdS_iiS_d,@object # @_Z15StarThetaKernelPdS_iiS_d
.section .rodata,"a",@progbits
.globl _Z15StarThetaKernelPdS_iiS_d
.p2align 3, 0x0
_Z15StarThetaKernelPdS_iiS_d:
.quad _Z30__device_stub__StarThetaKernelPdS_iiS_d
.size _Z15StarThetaKernelPdS_iiS_d, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15StarThetaKernelPdS_iiS_d"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__StarThetaKernelPdS_iiS_d
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15StarThetaKernelPdS_iiS_d
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <sys/times.h>
#include <unistd.h>
__global__ void calcInterval (double * data, const long cntSteps, const long cntThreads, const double step)
{
double x;
double sum=0.0;
int idThread=blockDim.x * blockIdx.x + threadIdx.x;;
long cntStepsPerThread = cntSteps / cntThreads;
long localmax = (idThread+1)*cntStepsPerThread;
if (idThread==cntThreads-1) localmax=cntSteps;
for (long i = idThread*cntStepsPerThread; i < localmax; i ++)
{
x = (i + .5)*step;
sum = sum + 4.0/(1.+ x*x);
}
data[idThread]=sum;
}
int main(int argc, char** argv)
{
const unsigned long cntSteps=500000000; /* default # of rectangles */
double step = 1./static_cast<double>(cntSteps);
const double PI25DT = 3.141592653589793238462643;
double pi=0.;
const int cntThreads=256;
const int cntBlocks=256;
const long cntThreadsTotal=cntThreads*cntBlocks;
std::cout << "\ncomputing on GPU (" << cntThreadsTotal << ") threads " << std::endl;
clock_t clockStart, clockStop;
tms tmsStart, tmsStop;
clockStart = times(&tmsStart);
double * gpuValues = NULL;
cudaMalloc((void**) &gpuValues,cntThreadsTotal*sizeof(double));
calcInterval<<<cntBlocks,cntThreads>>>(gpuValues,cntSteps,cntThreadsTotal,step);
double * cpuValues = new double[cntThreadsTotal];
cudaMemcpy (cpuValues, gpuValues, cntThreadsTotal * sizeof(double), cudaMemcpyDeviceToHost);
cudaFree (gpuValues);
for (long i=0; i<cntThreadsTotal; i++)
{
pi+=cpuValues[i]*step;
}
delete[] cpuValues;
clockStop = times(&tmsStop);
std::cout << "The value of PI is " << pi << " Error is " << fabs(pi - PI25DT) << std::endl;
std::cout << "The time to calculate PI was " ;
double secs= (clockStop - clockStart)/static_cast<double>(sysconf(_SC_CLK_TCK));
std::cout << secs << " seconds\n" << std::endl;
return 0;
} | .file "tmpxft_001231b5_00000000-6_6_cuda.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3685:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3685:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z12calcIntervalPdlldPdlld
.type _Z35__device_stub__Z12calcIntervalPdlldPdlld, @function
_Z35__device_stub__Z12calcIntervalPdlldPdlld:
.LFB3707:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movsd %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12calcIntervalPdlld(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3707:
.size _Z35__device_stub__Z12calcIntervalPdlldPdlld, .-_Z35__device_stub__Z12calcIntervalPdlldPdlld
.globl _Z12calcIntervalPdlld
.type _Z12calcIntervalPdlld, @function
_Z12calcIntervalPdlld:
.LFB3708:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z12calcIntervalPdlldPdlld
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3708:
.size _Z12calcIntervalPdlld, .-_Z12calcIntervalPdlld
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\ncomputing on GPU ("
.LC2:
.string ") threads "
.LC4:
.string "The value of PI is "
.LC5:
.string " Error is "
.LC8:
.string "The time to calculate PI was "
.LC9:
.string " seconds\n"
.text
.globl main
.type main, @function
main:
.LFB3682:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
addq $-128, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $65536, %esi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 48(%rsp), %rdi
call times@PLT
movq %rax, %rbp
movq $0, 24(%rsp)
leaq 24(%rsp), %rdi
movl $524288, %esi
call cudaMalloc@PLT
movl $256, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $256, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
movl $524288, %edi
call _Znam@PLT
movq %rax, %rbx
movl $2, %ecx
movl $524288, %edx
movq 24(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rax
leaq 524288(%rbx), %rdx
movq $0x000000000, 8(%rsp)
movsd .LC3(%rip), %xmm1
.L13:
movapd %xmm1, %xmm0
mulsd (%rax), %xmm0
addsd 8(%rsp), %xmm0
movsd %xmm0, 8(%rsp)
addq $8, %rax
cmpq %rdx, %rax
jne .L13
movq %rbx, %rdi
call _ZdaPv@PLT
leaq 80(%rsp), %rdi
call times@PLT
movq %rax, %rbx
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %r12
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 8(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 8(%rsp), %xmm0
subsd .LC6(%rip), %xmm0
andpd .LC7(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC8(%rip), %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
subq %rbp, %rbx
pxor %xmm3, %xmm3
cvtsi2sdq %rbx, %xmm3
movq %xmm3, %rbx
movl $2, %edi
call sysconf@PLT
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
movq %rbx, %xmm0
divsd %xmm1, %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC9(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
subq $-128, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movsd .LC3(%rip), %xmm0
movl $65536, %edx
movl $500000000, %esi
movq 24(%rsp), %rdi
call _Z35__device_stub__Z12calcIntervalPdlldPdlld
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3682:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z12calcIntervalPdlld"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3710:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z12calcIntervalPdlld(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3710:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long -400107883
.long 1042361867
.align 8
.LC6:
.long 1413754136
.long 1074340347
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC7:
.long -1
.long 2147483647
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <sys/times.h>
#include <unistd.h>
__global__ void calcInterval (double * data, const long cntSteps, const long cntThreads, const double step)
{
double x;
double sum=0.0;
int idThread=blockDim.x * blockIdx.x + threadIdx.x;;
long cntStepsPerThread = cntSteps / cntThreads;
long localmax = (idThread+1)*cntStepsPerThread;
if (idThread==cntThreads-1) localmax=cntSteps;
for (long i = idThread*cntStepsPerThread; i < localmax; i ++)
{
x = (i + .5)*step;
sum = sum + 4.0/(1.+ x*x);
}
data[idThread]=sum;
}
int main(int argc, char** argv)
{
const unsigned long cntSteps=500000000; /* default # of rectangles */
double step = 1./static_cast<double>(cntSteps);
const double PI25DT = 3.141592653589793238462643;
double pi=0.;
const int cntThreads=256;
const int cntBlocks=256;
const long cntThreadsTotal=cntThreads*cntBlocks;
std::cout << "\ncomputing on GPU (" << cntThreadsTotal << ") threads " << std::endl;
clock_t clockStart, clockStop;
tms tmsStart, tmsStop;
clockStart = times(&tmsStart);
double * gpuValues = NULL;
cudaMalloc((void**) &gpuValues,cntThreadsTotal*sizeof(double));
calcInterval<<<cntBlocks,cntThreads>>>(gpuValues,cntSteps,cntThreadsTotal,step);
double * cpuValues = new double[cntThreadsTotal];
cudaMemcpy (cpuValues, gpuValues, cntThreadsTotal * sizeof(double), cudaMemcpyDeviceToHost);
cudaFree (gpuValues);
for (long i=0; i<cntThreadsTotal; i++)
{
pi+=cpuValues[i]*step;
}
delete[] cpuValues;
clockStop = times(&tmsStop);
std::cout << "The value of PI is " << pi << " Error is " << fabs(pi - PI25DT) << std::endl;
std::cout << "The time to calculate PI was " ;
double secs= (clockStop - clockStart)/static_cast<double>(sysconf(_SC_CLK_TCK));
std::cout << secs << " seconds\n" << std::endl;
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <sys/times.h>
#include <unistd.h>
__global__ void calcInterval (double * data, const long cntSteps, const long cntThreads, const double step)
{
double x;
double sum=0.0;
int idThread=blockDim.x * blockIdx.x + threadIdx.x;;
long cntStepsPerThread = cntSteps / cntThreads;
long localmax = (idThread+1)*cntStepsPerThread;
if (idThread==cntThreads-1) localmax=cntSteps;
for (long i = idThread*cntStepsPerThread; i < localmax; i ++)
{
x = (i + .5)*step;
sum = sum + 4.0/(1.+ x*x);
}
data[idThread]=sum;
}
int main(int argc, char** argv)
{
const unsigned long cntSteps=500000000; /* default # of rectangles */
double step = 1./static_cast<double>(cntSteps);
const double PI25DT = 3.141592653589793238462643;
double pi=0.;
const int cntThreads=256;
const int cntBlocks=256;
const long cntThreadsTotal=cntThreads*cntBlocks;
std::cout << "\ncomputing on GPU (" << cntThreadsTotal << ") threads " << std::endl;
clock_t clockStart, clockStop;
tms tmsStart, tmsStop;
clockStart = times(&tmsStart);
double * gpuValues = NULL;
hipMalloc((void**) &gpuValues,cntThreadsTotal*sizeof(double));
calcInterval<<<cntBlocks,cntThreads>>>(gpuValues,cntSteps,cntThreadsTotal,step);
double * cpuValues = new double[cntThreadsTotal];
hipMemcpy (cpuValues, gpuValues, cntThreadsTotal * sizeof(double), hipMemcpyDeviceToHost);
hipFree (gpuValues);
for (long i=0; i<cntThreadsTotal; i++)
{
pi+=cpuValues[i]*step;
}
delete[] cpuValues;
clockStop = times(&tmsStop);
std::cout << "The value of PI is " << pi << " Error is " << fabs(pi - PI25DT) << std::endl;
std::cout << "The time to calculate PI was " ;
double secs= (clockStop - clockStart)/static_cast<double>(sysconf(_SC_CLK_TCK));
std::cout << secs << " seconds\n" << std::endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <sys/times.h>
#include <unistd.h>
__global__ void calcInterval (double * data, const long cntSteps, const long cntThreads, const double step)
{
double x;
double sum=0.0;
int idThread=blockDim.x * blockIdx.x + threadIdx.x;;
long cntStepsPerThread = cntSteps / cntThreads;
long localmax = (idThread+1)*cntStepsPerThread;
if (idThread==cntThreads-1) localmax=cntSteps;
for (long i = idThread*cntStepsPerThread; i < localmax; i ++)
{
x = (i + .5)*step;
sum = sum + 4.0/(1.+ x*x);
}
data[idThread]=sum;
}
int main(int argc, char** argv)
{
const unsigned long cntSteps=500000000; /* default # of rectangles */
double step = 1./static_cast<double>(cntSteps);
const double PI25DT = 3.141592653589793238462643;
double pi=0.;
const int cntThreads=256;
const int cntBlocks=256;
const long cntThreadsTotal=cntThreads*cntBlocks;
std::cout << "\ncomputing on GPU (" << cntThreadsTotal << ") threads " << std::endl;
clock_t clockStart, clockStop;
tms tmsStart, tmsStop;
clockStart = times(&tmsStart);
double * gpuValues = NULL;
hipMalloc((void**) &gpuValues,cntThreadsTotal*sizeof(double));
calcInterval<<<cntBlocks,cntThreads>>>(gpuValues,cntSteps,cntThreadsTotal,step);
double * cpuValues = new double[cntThreadsTotal];
hipMemcpy (cpuValues, gpuValues, cntThreadsTotal * sizeof(double), hipMemcpyDeviceToHost);
hipFree (gpuValues);
for (long i=0; i<cntThreadsTotal; i++)
{
pi+=cpuValues[i]*step;
}
delete[] cpuValues;
clockStop = times(&tmsStop);
std::cout << "The value of PI is " << pi << " Error is " << fabs(pi - PI25DT) << std::endl;
std::cout << "The time to calculate PI was " ;
double secs= (clockStop - clockStart)/static_cast<double>(sysconf(_SC_CLK_TCK));
std::cout << secs << " seconds\n" << std::endl;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12calcIntervalPdlld
.globl _Z12calcIntervalPdlld
.p2align 8
.type _Z12calcIntervalPdlld,@function
_Z12calcIntervalPdlld:
s_load_b128 s[4:7], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_or_b64 s[8:9], s[4:5], s[6:7]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u64 s[8:9], 0
s_cbranch_scc0 .LBB0_2
s_ashr_i32 s10, s7, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_u32 s2, s6, s10
s_mov_b32 s11, s10
s_addc_u32 s3, s7, s10
s_xor_b64 s[2:3], s[2:3], s[10:11]
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s2
v_cvt_f32_u32_e32 v2, s3
s_sub_u32 s13, 0, s2
s_subb_u32 s14, 0, s3
v_fmamk_f32 v1, v2, 0x4f800000, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x5f7ffffc, v1
v_mul_f32_e32 v2, 0x2f800000, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_trunc_f32_e32 v2, v2
v_fmamk_f32 v1, v2, 0xcf800000, v1
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v1, v1
v_readfirstlane_b32 s9, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_readfirstlane_b32 s12, v1
s_mul_i32 s16, s13, s9
s_delay_alu instid0(VALU_DEP_1)
s_mul_hi_u32 s18, s13, s12
s_mul_i32 s17, s14, s12
s_add_i32 s16, s18, s16
s_mul_i32 s19, s13, s12
s_add_i32 s16, s16, s17
s_mul_hi_u32 s18, s12, s19
s_mul_hi_u32 s20, s9, s19
s_mul_i32 s17, s9, s19
s_mul_hi_u32 s19, s12, s16
s_mul_i32 s12, s12, s16
s_mul_hi_u32 s21, s9, s16
s_add_u32 s12, s18, s12
s_addc_u32 s18, 0, s19
s_add_u32 s12, s12, s17
s_mul_i32 s16, s9, s16
s_addc_u32 s12, s18, s20
s_addc_u32 s17, s21, 0
s_add_u32 s12, s12, s16
s_addc_u32 s16, 0, s17
v_add_co_u32 v1, s12, v1, s12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s12, 0
s_addc_u32 s9, s9, s16
v_readfirstlane_b32 s12, v1
s_mul_i32 s16, s13, s9
s_delay_alu instid0(VALU_DEP_1)
s_mul_hi_u32 s17, s13, s12
s_mul_i32 s14, s14, s12
s_add_i32 s16, s17, s16
s_mul_i32 s13, s13, s12
s_add_i32 s16, s16, s14
s_mul_hi_u32 s17, s9, s13
s_mul_i32 s18, s9, s13
s_mul_hi_u32 s13, s12, s13
s_mul_hi_u32 s19, s12, s16
s_mul_i32 s12, s12, s16
s_mul_hi_u32 s14, s9, s16
s_add_u32 s12, s13, s12
s_addc_u32 s13, 0, s19
s_add_u32 s12, s12, s18
s_mul_i32 s16, s9, s16
s_addc_u32 s12, s13, s17
s_addc_u32 s13, s14, 0
s_add_u32 s12, s12, s16
s_addc_u32 s13, 0, s13
v_add_co_u32 v1, s12, v1, s12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s12, 0
s_addc_u32 s9, s9, s13
s_ashr_i32 s12, s5, 31
v_readfirstlane_b32 s14, v1
s_add_u32 s16, s4, s12
s_mov_b32 s13, s12
s_addc_u32 s17, s5, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b64 s[16:17], s[16:17], s[12:13]
s_mul_i32 s19, s16, s9
s_mul_hi_u32 s20, s16, s14
s_mul_hi_u32 s18, s16, s9
s_mul_hi_u32 s22, s17, s14
s_mul_i32 s14, s17, s14
s_add_u32 s19, s20, s19
s_addc_u32 s18, 0, s18
s_mul_hi_u32 s21, s17, s9
s_add_u32 s14, s19, s14
s_mul_i32 s9, s17, s9
s_addc_u32 s14, s18, s22
s_addc_u32 s18, s21, 0
s_add_u32 s9, s14, s9
s_addc_u32 s14, 0, s18
s_mul_i32 s21, s2, s9
s_mul_hi_u32 s18, s2, s9
s_mul_i32 s20, s2, s14
v_sub_co_u32 v1, s16, s16, s21
s_mul_i32 s19, s3, s9
s_add_i32 s18, s18, s20
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_add_i32 s18, s18, s19
v_sub_co_u32 v2, s20, v1, s2
s_sub_i32 s19, s17, s18
s_cmp_lg_u32 s16, 0
s_subb_u32 s19, s19, s3
s_cmp_lg_u32 s20, 0
v_cmp_le_u32_e32 vcc_lo, s2, v2
s_subb_u32 s19, s19, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_u32 s19, s3
v_cndmask_b32_e64 v2, 0, -1, vcc_lo
s_cselect_b32 s20, -1, 0
s_cmp_eq_u32 s19, s3
s_cselect_b32 vcc_lo, -1, 0
s_add_u32 s19, s9, 1
v_cndmask_b32_e32 v2, s20, v2, vcc_lo
s_addc_u32 s20, s14, 0
s_add_u32 s21, s9, 2
s_addc_u32 s22, s14, 0
v_mov_b32_e32 v3, s21
s_cmp_lg_u32 s16, 0
v_cmp_le_u32_e32 vcc_lo, s2, v1
s_subb_u32 s2, s17, s18
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_u32 s2, s3
v_cndmask_b32_e64 v1, 0, -1, vcc_lo
s_cselect_b32 s16, -1, 0
s_cmp_eq_u32 s2, s3
v_cmp_ne_u32_e32 vcc_lo, 0, v2
s_cselect_b32 s2, -1, 0
v_mov_b32_e32 v2, s22
v_cndmask_b32_e64 v1, s16, v1, s2
s_xor_b64 s[2:3], s[12:13], s[10:11]
v_cndmask_b32_e32 v3, s19, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v2, s20, v2, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v1, s14, v2, vcc_lo
v_cndmask_b32_e32 v2, s9, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v1, s3, v1
v_xor_b32_e32 v2, s2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_co_u32 v5, vcc_lo, v2, s2
v_subrev_co_ci_u32_e32 v6, vcc_lo, s3, v1, vcc_lo
s_branch .LBB0_3
.LBB0_2:
s_mov_b32 s8, -1
.LBB0_3:
s_load_b32 s2, s[0:1], 0x2c
s_and_not1_b32 vcc_lo, exec_lo, s8
s_cbranch_vccnz .LBB0_5
v_cvt_f32_u32_e32 v1, s6
s_sub_i32 s8, 0, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s3, v1
s_mul_i32 s8, s8, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s8, s3, s8
s_add_i32 s3, s3, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s3, s4, s3
s_mul_i32 s8, s3, s6
s_add_i32 s9, s3, 1
s_sub_i32 s8, s4, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s10, s8, s6
s_cmp_ge_u32 s8, s6
s_cselect_b32 s3, s9, s3
s_cselect_b32 s8, s10, s8
s_add_i32 s10, s3, 1
s_cmp_ge_u32 s8, s6
s_mov_b32 s9, 0
s_cselect_b32 s8, s10, s3
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, s8 :: v_dual_mov_b32 v6, s9
.LBB0_5:
s_waitcnt lgkmcnt(0)
s_and_b32 s2, 0xffff, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_add_u32 s2, s6, -1
s_addc_u32 s3, s7, -1
v_add_nc_u32_e32 v0, 1, v1
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v3, 31, v0
v_mul_lo_u32 v9, v6, v0
v_mad_u64_u32 v[7:8], null, v5, v0, 0
v_mul_lo_u32 v6, v6, v1
v_mul_lo_u32 v0, v5, v3
v_mad_u64_u32 v[3:4], null, v5, v1, 0
v_mul_lo_u32 v5, v5, v2
v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[1:2]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add3_u32 v0, v8, v0, v9
v_cndmask_b32_e64 v7, v7, s4, vcc_lo
v_add3_u32 v4, v4, v5, v6
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v8, v0, s5, vcc_lo
v_mov_b32_e32 v6, 0
s_mov_b32 s4, exec_lo
v_cmpx_lt_i64_e64 v[3:4], v[7:8]
s_cbranch_execz .LBB0_9
s_load_b64 s[2:3], s[0:1], 0x18
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v6, 0
s_mov_b32 s5, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_7:
v_cvt_f64_i32_e32 v[9:10], v4
v_cvt_f64_u32_e32 v[11:12], v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[9:10], v[9:10], 32
v_add_f64 v[9:10], v[9:10], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[9:10], v[9:10], 0.5
s_waitcnt lgkmcnt(0)
v_mul_f64 v[9:10], v[9:10], s[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], v[9:10], v[9:10], 1.0
v_div_scale_f64 v[11:12], null, v[9:10], v[9:10], 4.0
v_div_scale_f64 v[17:18], vcc_lo, 4.0, v[9:10], 4.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[13:14], v[11:12]
s_waitcnt_depctr 0xfff
v_fma_f64 v[15:16], -v[11:12], v[13:14], 1.0
v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[15:16], -v[11:12], v[13:14], 1.0
v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[15:16], v[17:18], v[13:14]
v_fma_f64 v[11:12], -v[11:12], v[15:16], v[17:18]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[11:12], v[11:12], v[13:14], v[15:16]
v_add_co_u32 v3, vcc_lo, v3, 1
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
v_cmp_ge_i64_e32 vcc_lo, v[3:4], v[7:8]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[9:10], v[11:12], v[9:10], 4.0
v_add_f64 v[5:6], v[5:6], v[9:10]
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_7
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s5
.LBB0_9:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s4
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[5:6], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12calcIntervalPdlld
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 19
.amdhsa_next_free_sgpr 23
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12calcIntervalPdlld, .Lfunc_end0-_Z12calcIntervalPdlld
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12calcIntervalPdlld
.private_segment_fixed_size: 0
.sgpr_count: 25
.sgpr_spill_count: 0
.symbol: _Z12calcIntervalPdlld.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 19
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <sys/times.h>
#include <unistd.h>
__global__ void calcInterval (double * data, const long cntSteps, const long cntThreads, const double step)
{
double x;
double sum=0.0;
int idThread=blockDim.x * blockIdx.x + threadIdx.x;;
long cntStepsPerThread = cntSteps / cntThreads;
long localmax = (idThread+1)*cntStepsPerThread;
if (idThread==cntThreads-1) localmax=cntSteps;
for (long i = idThread*cntStepsPerThread; i < localmax; i ++)
{
x = (i + .5)*step;
sum = sum + 4.0/(1.+ x*x);
}
data[idThread]=sum;
}
int main(int argc, char** argv)
{
const unsigned long cntSteps=500000000; /* default # of rectangles */
double step = 1./static_cast<double>(cntSteps);
const double PI25DT = 3.141592653589793238462643;
double pi=0.;
const int cntThreads=256;
const int cntBlocks=256;
const long cntThreadsTotal=cntThreads*cntBlocks;
std::cout << "\ncomputing on GPU (" << cntThreadsTotal << ") threads " << std::endl;
clock_t clockStart, clockStop;
tms tmsStart, tmsStop;
clockStart = times(&tmsStart);
double * gpuValues = NULL;
hipMalloc((void**) &gpuValues,cntThreadsTotal*sizeof(double));
calcInterval<<<cntBlocks,cntThreads>>>(gpuValues,cntSteps,cntThreadsTotal,step);
double * cpuValues = new double[cntThreadsTotal];
hipMemcpy (cpuValues, gpuValues, cntThreadsTotal * sizeof(double), hipMemcpyDeviceToHost);
hipFree (gpuValues);
for (long i=0; i<cntThreadsTotal; i++)
{
pi+=cpuValues[i]*step;
}
delete[] cpuValues;
clockStop = times(&tmsStop);
std::cout << "The value of PI is " << pi << " Error is " << fabs(pi - PI25DT) << std::endl;
std::cout << "The time to calculate PI was " ;
double secs= (clockStop - clockStart)/static_cast<double>(sysconf(_SC_CLK_TCK));
std::cout << secs << " seconds\n" << std::endl;
return 0;
} | .text
.file "6_cuda.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z27__device_stub__calcIntervalPdlld # -- Begin function _Z27__device_stub__calcIntervalPdlld
.p2align 4, 0x90
.type _Z27__device_stub__calcIntervalPdlld,@function
_Z27__device_stub__calcIntervalPdlld: # @_Z27__device_stub__calcIntervalPdlld
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movsd %xmm0, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12calcIntervalPdlld, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__calcIntervalPdlld, .Lfunc_end0-_Z27__device_stub__calcIntervalPdlld
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3e212e0be826d695 # double 2.0000000000000001E-9
.LCPI1_1:
.quad 0xc00921fb54442d18 # double -3.1415926535897931
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_2:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $184, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $65536, %esi # imm = 0x10000
callq _ZNSo9_M_insertIlEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $10, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB1_17
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB1_3
# %bb.2:
movzbl 67(%r14), %eax
jmp .LBB1_4
.LBB1_3:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 152(%rsp), %rdi
callq times
movq %rax, %rbx
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $524288, %esi # imm = 0x80000
callq hipMalloc
movabsq $4294967552, %rdi # imm = 0x100000100
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 8(%rsp), %rax
movq %rax, 104(%rsp)
movq $500000000, 96(%rsp) # imm = 0x1DCD6500
movq $65536, 88(%rsp) # imm = 0x10000
movabsq $4476910133257361045, %rax # imm = 0x3E212E0BE826D695
movq %rax, 80(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z12calcIntervalPdlld, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movl $524288, %edi # imm = 0x80000
callq _Znam
movq %rax, %r14
movq 8(%rsp), %rsi
movl $524288, %edx # imm = 0x80000
movq %rax, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
xorpd %xmm2, %xmm2
xorl %eax, %eax
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movsd (%r14,%rax,8), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm0, %xmm1
addsd %xmm1, %xmm2
incq %rax
cmpq $65536, %rax # imm = 0x10000
jne .LBB1_7
# %bb.8:
movq %r14, %rdi
movapd %xmm2, 16(%rsp) # 16-byte Spill
callq _ZdaPv
leaq 112(%rsp), %rdi
callq times
movq %rax, %r14
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movaps 16(%rsp), %xmm0 # 16-byte Reload
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str.3, %esi
movl $10, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movapd 16(%rsp), %xmm0 # 16-byte Reload
addsd .LCPI1_1(%rip), %xmm0
andpd .LCPI1_2(%rip), %xmm0
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB1_17
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i17
cmpb $0, 56(%r15)
je .LBB1_11
# %bb.10:
movzbl 67(%r15), %ecx
jmp .LBB1_12
.LBB1_11:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB1_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit20
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $29, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %rbx, %r14
xorps %xmm0, %xmm0
cvtsi2sd %r14, %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
movl $2, %edi
callq sysconf
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd %xmm1, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.5, %esi
movl $9, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB1_17
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i22
cmpb $0, 56(%r14)
je .LBB1_15
# %bb.14:
movzbl 67(%r14), %eax
jmp .LBB1_16
.LBB1_15:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit25
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_17:
.cfi_def_cfa_offset 224
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12calcIntervalPdlld, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12calcIntervalPdlld,@object # @_Z12calcIntervalPdlld
.section .rodata,"a",@progbits
.globl _Z12calcIntervalPdlld
.p2align 3, 0x0
_Z12calcIntervalPdlld:
.quad _Z27__device_stub__calcIntervalPdlld
.size _Z12calcIntervalPdlld, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\ncomputing on GPU ("
.size .L.str, 20
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz ") threads "
.size .L.str.1, 11
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "The value of PI is "
.size .L.str.2, 20
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " Error is "
.size .L.str.3, 11
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "The time to calculate PI was "
.size .L.str.4, 30
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " seconds\n"
.size .L.str.5, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12calcIntervalPdlld"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__calcIntervalPdlld
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12calcIntervalPdlld
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001231b5_00000000-6_6_cuda.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3685:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3685:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z12calcIntervalPdlldPdlld
.type _Z35__device_stub__Z12calcIntervalPdlldPdlld, @function
_Z35__device_stub__Z12calcIntervalPdlldPdlld:
.LFB3707:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movsd %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12calcIntervalPdlld(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3707:
.size _Z35__device_stub__Z12calcIntervalPdlldPdlld, .-_Z35__device_stub__Z12calcIntervalPdlldPdlld
.globl _Z12calcIntervalPdlld
.type _Z12calcIntervalPdlld, @function
_Z12calcIntervalPdlld:
.LFB3708:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z12calcIntervalPdlldPdlld
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3708:
.size _Z12calcIntervalPdlld, .-_Z12calcIntervalPdlld
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\ncomputing on GPU ("
.LC2:
.string ") threads "
.LC4:
.string "The value of PI is "
.LC5:
.string " Error is "
.LC8:
.string "The time to calculate PI was "
.LC9:
.string " seconds\n"
.text
.globl main
.type main, @function
main:
.LFB3682:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
addq $-128, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $65536, %esi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 48(%rsp), %rdi
call times@PLT
movq %rax, %rbp
movq $0, 24(%rsp)
leaq 24(%rsp), %rdi
movl $524288, %esi
call cudaMalloc@PLT
movl $256, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $256, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
movl $524288, %edi
call _Znam@PLT
movq %rax, %rbx
movl $2, %ecx
movl $524288, %edx
movq 24(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rax
leaq 524288(%rbx), %rdx
movq $0x000000000, 8(%rsp)
movsd .LC3(%rip), %xmm1
.L13:
movapd %xmm1, %xmm0
mulsd (%rax), %xmm0
addsd 8(%rsp), %xmm0
movsd %xmm0, 8(%rsp)
addq $8, %rax
cmpq %rdx, %rax
jne .L13
movq %rbx, %rdi
call _ZdaPv@PLT
leaq 80(%rsp), %rdi
call times@PLT
movq %rax, %rbx
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %r12
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 8(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 8(%rsp), %xmm0
subsd .LC6(%rip), %xmm0
andpd .LC7(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC8(%rip), %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
subq %rbp, %rbx
pxor %xmm3, %xmm3
cvtsi2sdq %rbx, %xmm3
movq %xmm3, %rbx
movl $2, %edi
call sysconf@PLT
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
movq %rbx, %xmm0
divsd %xmm1, %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC9(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
subq $-128, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movsd .LC3(%rip), %xmm0
movl $65536, %edx
movl $500000000, %esi
movq 24(%rsp), %rdi
call _Z35__device_stub__Z12calcIntervalPdlldPdlld
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3682:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z12calcIntervalPdlld"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3710:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z12calcIntervalPdlld(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3710:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long -400107883
.long 1042361867
.align 8
.LC6:
.long 1413754136
.long 1074340347
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC7:
.long -1
.long 2147483647
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "6_cuda.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z27__device_stub__calcIntervalPdlld # -- Begin function _Z27__device_stub__calcIntervalPdlld
.p2align 4, 0x90
.type _Z27__device_stub__calcIntervalPdlld,@function
_Z27__device_stub__calcIntervalPdlld: # @_Z27__device_stub__calcIntervalPdlld
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movsd %xmm0, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12calcIntervalPdlld, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__calcIntervalPdlld, .Lfunc_end0-_Z27__device_stub__calcIntervalPdlld
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3e212e0be826d695 # double 2.0000000000000001E-9
.LCPI1_1:
.quad 0xc00921fb54442d18 # double -3.1415926535897931
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_2:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $184, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $65536, %esi # imm = 0x10000
callq _ZNSo9_M_insertIlEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $10, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB1_17
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB1_3
# %bb.2:
movzbl 67(%r14), %eax
jmp .LBB1_4
.LBB1_3:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 152(%rsp), %rdi
callq times
movq %rax, %rbx
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $524288, %esi # imm = 0x80000
callq hipMalloc
movabsq $4294967552, %rdi # imm = 0x100000100
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 8(%rsp), %rax
movq %rax, 104(%rsp)
movq $500000000, 96(%rsp) # imm = 0x1DCD6500
movq $65536, 88(%rsp) # imm = 0x10000
movabsq $4476910133257361045, %rax # imm = 0x3E212E0BE826D695
movq %rax, 80(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z12calcIntervalPdlld, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movl $524288, %edi # imm = 0x80000
callq _Znam
movq %rax, %r14
movq 8(%rsp), %rsi
movl $524288, %edx # imm = 0x80000
movq %rax, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
xorpd %xmm2, %xmm2
xorl %eax, %eax
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movsd (%r14,%rax,8), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm0, %xmm1
addsd %xmm1, %xmm2
incq %rax
cmpq $65536, %rax # imm = 0x10000
jne .LBB1_7
# %bb.8:
movq %r14, %rdi
movapd %xmm2, 16(%rsp) # 16-byte Spill
callq _ZdaPv
leaq 112(%rsp), %rdi
callq times
movq %rax, %r14
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movaps 16(%rsp), %xmm0 # 16-byte Reload
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str.3, %esi
movl $10, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movapd 16(%rsp), %xmm0 # 16-byte Reload
addsd .LCPI1_1(%rip), %xmm0
andpd .LCPI1_2(%rip), %xmm0
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB1_17
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i17
cmpb $0, 56(%r15)
je .LBB1_11
# %bb.10:
movzbl 67(%r15), %ecx
jmp .LBB1_12
.LBB1_11:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB1_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit20
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $29, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %rbx, %r14
xorps %xmm0, %xmm0
cvtsi2sd %r14, %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
movl $2, %edi
callq sysconf
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd %xmm1, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.5, %esi
movl $9, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB1_17
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i22
cmpb $0, 56(%r14)
je .LBB1_15
# %bb.14:
movzbl 67(%r14), %eax
jmp .LBB1_16
.LBB1_15:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit25
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_17:
.cfi_def_cfa_offset 224
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12calcIntervalPdlld, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12calcIntervalPdlld,@object # @_Z12calcIntervalPdlld
.section .rodata,"a",@progbits
.globl _Z12calcIntervalPdlld
.p2align 3, 0x0
_Z12calcIntervalPdlld:
.quad _Z27__device_stub__calcIntervalPdlld
.size _Z12calcIntervalPdlld, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\ncomputing on GPU ("
.size .L.str, 20
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz ") threads "
.size .L.str.1, 11
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "The value of PI is "
.size .L.str.2, 20
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " Error is "
.size .L.str.3, 11
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "The time to calculate PI was "
.size .L.str.4, 30
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " seconds\n"
.size .L.str.5, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12calcIntervalPdlld"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__calcIntervalPdlld
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12calcIntervalPdlld
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <stdio.h>
#define TILE_WIDTH 2
__global__ void matMulKernel(float* d_N, float* d_M, float* d_P, int Width){
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
// Identify the row and column of the d_P element to work on
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
float Pvalue = 0;
// Loop over the d_M and d_N tiles required to compute d_P element
for (int m = 0; m < Width/TILE_WIDTH; ++m) {// Coolaborative loading of d_M and d_N tiles into shared memory
Mds[ty][tx] = d_M[Row*Width + m*TILE_WIDTH + tx];
Nds[ty][tx] = d_N[(m*TILE_WIDTH + ty)*Width + Col];
__syncthreads();
for (int k = 0; k < TILE_WIDTH; ++k) {
Pvalue += Mds[ty][k] * Nds[k][tx];
}
__syncthreads();
}
d_P[Row*Width + Col] = Pvalue;
}
void matMul(float* A, float* B, float* C, int width)
{
int size = width * width * sizeof(float);
static float *d_A, *d_B, *d_C;
cudaMalloc((void **) &d_A, size);
cudaMemcpy(d_A, A, size, cudaMemcpyHostToDevice);
cudaMalloc((void **) &d_B, size);
cudaMemcpy(d_B, B, size, cudaMemcpyHostToDevice);
cudaMalloc((void **) &d_C, size);
dim3 dimGrid(2, 2, 1);
dim3 dimBlock(2, 2, 1);
matMulKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C, width);
cudaMemcpy(C, d_C, size, cudaMemcpyDeviceToHost);
printf("\nA: \n");
for (int i = 0; i < 4; i++) {
for (int j = 0; j < 4; j++){
printf("%2.0f ", A[i + j*width]);
}
printf("\n");
}
printf("\nB: \n");
for (int i = 0; i < 4; i++) {
for (int j = 0; j < 4; j++){
printf("%2.0f ", B[i + j*width]);
}
printf("\n");
}
printf("\n-------------------------------------");
printf("\nC: \n");
for (int i = 0; i < 4; i++) {
for (int j = 0; j < 4; j++){
printf("%2.0f ", C[i + j*width]);
}
printf("\n");
}
printf("\n-------------------------------------\n");
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
}
int main() {
int width = 4;
static float h_A[16];
static float h_B[16];
static float h_C[16];
for (int i = 0; i < width; i++) {
for (int j = 0; j < width; j++) {
h_A[i + j*width] = (i+j)%2;
h_B[i + j*width] = (i+j)%3;
}
}
matMul(h_A, h_B, h_C, width);
} | code for sm_80
Function : _Z12matMulKernelPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0020*/ MOV R14, c[0x0][0x178] ; /* 0x00005e00000e7a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R14, 0x2, PT ; /* 0x000000020e00780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R12, SR_CTAID.X ; /* 0x00000000000c7919 */
/* 0x000e680000002500 */
/*0080*/ S2R R13, SR_TID.X ; /* 0x00000000000d7919 */
/* 0x000ea20000002100 */
/*0090*/ LEA R16, R3, R0, 0x1 ; /* 0x0000000003107211 */
/* 0x001fca00078e08ff */
/*00a0*/ @!P0 BRA 0x730 ; /* 0x0000068000008947 */
/* 0x000fea0003800000 */
/*00b0*/ LEA.HI R2, R14, c[0x0][0x178], RZ, 0x1 ; /* 0x00005e000e027a11 */
/* 0x000fe200078f08ff */
/*00c0*/ HFMA2.MMA R19, -RZ, RZ, 0, 0 ; /* 0x00000000ff137435 */
/* 0x000fe200000001ff */
/*00d0*/ SHF.L.U32 R18, R0, 0x3, RZ ; /* 0x0000000300127819 */
/* 0x000fe200000006ff */
/*00e0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*00f0*/ SHF.R.S32.HI R22, RZ, 0x1, R2 ; /* 0x00000001ff167819 */
/* 0x000fe40000011402 */
/*0100*/ SHF.L.U32 R21, R14, 0x1, RZ ; /* 0x000000010e157819 */
/* 0x000fe200000006ff */
/*0110*/ IMAD R18, R13, 0x4, R18 ; /* 0x000000040d127824 */
/* 0x004fe200078e0212 */
/*0120*/ IADD3 R2, R22.reuse, -0x1, RZ ; /* 0xffffffff16027810 */
/* 0x040fe40007ffe0ff */
/*0130*/ LOP3.LUT R17, R22, 0x3, RZ, 0xc0, !PT ; /* 0x0000000316117812 */
/* 0x000fc400078ec0ff */
/*0140*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0150*/ ISETP.NE.AND P0, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fd60003f05270 */
/*0160*/ @!P1 BRA 0x560 ; /* 0x000003f000009947 */
/* 0x000fea0003800000 */
/*0170*/ MOV R20, 0x4 ; /* 0x0000000400147802 */
/* 0x000fe20000000f00 */
/*0180*/ IMAD R15, R0, c[0x0][0x178], R13.reuse ; /* 0x00005e00000f7a24 */
/* 0x100fe200078e020d */
/*0190*/ IADD3 R22, -R22, R17, RZ ; /* 0x0000001116167210 */
/* 0x000fe20007ffe1ff */
/*01a0*/ IMAD R3, R16, c[0x0][0x178], R13 ; /* 0x00005e0010037a24 */
/* 0x000fe200078e020d */
/*01b0*/ MOV R19, RZ ; /* 0x000000ff00137202 */
/* 0x000fe20000000f00 */
/*01c0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*01d0*/ LEA R15, R12, R15, 0x1 ; /* 0x0000000f0c0f7211 */
/* 0x002fe200078e08ff */
/*01e0*/ IMAD.WIDE R2, R3, R20, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fc800078e0214 */
/*01f0*/ IMAD.WIDE R4, R15, R20, c[0x0][0x160] ; /* 0x000058000f047625 */
/* 0x000fe200078e0214 */
/*0200*/ LDG.E R23, [R2.64] ; /* 0x0000000402177981 */
/* 0x000ea8000c1e1900 */
/*0210*/ LDG.E R25, [R4.64] ; /* 0x0000000404197981 */
/* 0x000ee2000c1e1900 */
/*0220*/ IMAD.WIDE R10, R21, 0x4, R4 ; /* 0x00000004150a7825 */
/* 0x000fc600078e0204 */
/*0230*/ STS [R18], R23 ; /* 0x0000001712007388 */
/* 0x004fe80000000800 */
/*0240*/ STS [R18+0x10], R25 ; /* 0x0000101912007388 */
/* 0x008fe80000000800 */
/*0250*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0260*/ LDS R8, [R13.X4+0x10] ; /* 0x000010000d087984 */
/* 0x000fe80000004800 */
/*0270*/ LDS R26, [R13.X4+0x18] ; /* 0x000018000d1a7984 */
/* 0x000fe80000004800 */
/*0280*/ LDS.64 R6, [R0.X8] ; /* 0x0000000000067984 */
/* 0x000e280000008a00 */
/*0290*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02a0*/ LDG.E R29, [R2.64+0x8] ; /* 0x00000804021d7981 */
/* 0x000ea8000c1e1900 */
/*02b0*/ LDG.E R28, [R10.64] ; /* 0x000000040a1c7981 */
/* 0x000ee2000c1e1900 */
/*02c0*/ FFMA R6, R8, R6, R9 ; /* 0x0000000608067223 */
/* 0x001fc40000000009 */
/*02d0*/ IMAD.WIDE R8, R21, 0x4, R10 ; /* 0x0000000415087825 */
/* 0x000fe200078e020a */
/*02e0*/ STS [R18], R29 ; /* 0x0000001d12007388 */
/* 0x004fe80000000800 */
/*02f0*/ STS [R18+0x10], R28 ; /* 0x0000101c12007388 */
/* 0x008fe80000000800 */
/*0300*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0310*/ LDS R23, [R13.X4+0x10] ; /* 0x000010000d177984 */
/* 0x000fe80000004800 */
/*0320*/ LDS R24, [R13.X4+0x18] ; /* 0x000018000d187984 */
/* 0x000fe80000004800 */
/*0330*/ LDS.64 R4, [R0.X8] ; /* 0x0000000000047984 */
/* 0x000e280000008a00 */
/*0340*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0350*/ LDG.E R25, [R2.64+0x10] ; /* 0x0000100402197981 */
/* 0x000ea8000c1e1900 */
/*0360*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x000ee2000c1e1900 */
/*0370*/ FFMA R27, R26, R7, R6 ; /* 0x000000071a1b7223 */
/* 0x000fc60000000006 */
/*0380*/ STS [R18], R25 ; /* 0x0000001912007388 */
/* 0x004fe80000000800 */
/*0390*/ STS [R18+0x10], R11 ; /* 0x0000100b12007388 */
/* 0x0083e80000000800 */
/*03a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*03b0*/ IMAD.WIDE R10, R21, 0x4, R8 ; /* 0x00000004150a7825 */
/* 0x002fca00078e0208 */
/*03c0*/ LDS R25, [R13.X4+0x10] ; /* 0x000010000d197984 */
/* 0x000fe80000004800 */
/*03d0*/ LDS R26, [R13.X4+0x18] ; /* 0x000018000d1a7984 */
/* 0x000fe80000004800 */
/*03e0*/ LDS.64 R6, [R0.X8] ; /* 0x0000000000067984 */
/* 0x000e680000008a00 */
/*03f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0400*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea8000c1e1900 */
/*0410*/ LDG.E R29, [R2.64+0x18] ; /* 0x00001804021d7981 */
/* 0x000722000c1e1900 */
/*0420*/ FFMA R27, R23, R4, R27 ; /* 0x00000004171b7223 */
/* 0x001fe2000000001b */
/*0430*/ IADD3 R19, R19, 0x4, RZ ; /* 0x0000000413137810 */
/* 0x000fc40007ffe0ff */
/*0440*/ LEA R15, R14, R15, 0x3 ; /* 0x0000000f0e0f7211 */
/* 0x000fe200078e18ff */
/*0450*/ FFMA R5, R24, R5, R27 ; /* 0x0000000518057223 */
/* 0x000fc8000000001b */
/*0460*/ FFMA R5, R25, R6, R5 ; /* 0x0000000619057223 */
/* 0x002fe20000000005 */
/*0470*/ IADD3 R2, P2, R2, 0x20, RZ ; /* 0x0000002002027810 */
/* 0x008fe20007f5e0ff */
/*0480*/ IMAD.IADD R6, R22, 0x1, R19 ; /* 0x0000000116067824 */
/* 0x000fe400078e0213 */
/*0490*/ FFMA R5, R26, R7, R5 ; /* 0x000000071a057223 */
/* 0x000fe20000000005 */
/*04a0*/ IADD3.X R3, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff037210 */
/* 0x000fe400017fe4ff */
/*04b0*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f25270 */
/*04c0*/ STS [R18+0x10], R10 ; /* 0x0000100a12007388 */
/* 0x004fe80000000800 */
/*04d0*/ STS [R18], R29 ; /* 0x0000001d12007388 */
/* 0x010fe80000000800 */
/*04e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04f0*/ LDS R23, [R13.X4+0x10] ; /* 0x000010000d177984 */
/* 0x000fe80000004800 */
/*0500*/ LDS.64 R8, [R0.X8] ; /* 0x0000000000087984 */
/* 0x000e280000008a00 */
/*0510*/ LDS R4, [R13.X4+0x18] ; /* 0x000018000d047984 */
/* 0x000e620000004800 */
/*0520*/ FFMA R5, R23, R8, R5 ; /* 0x0000000817057223 */
/* 0x001fc80000000005 */
/*0530*/ FFMA R9, R4, R9, R5 ; /* 0x0000000904097223 */
/* 0x002fe20000000005 */
/*0540*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0550*/ @P1 BRA 0x1f0 ; /* 0xfffffc9000001947 */
/* 0x000fea000383ffff */
/*0560*/ @!P0 BRA 0x730 ; /* 0x000001c000008947 */
/* 0x000fea0003800000 */
/*0570*/ IMAD R6, R16, c[0x0][0x178], R13 ; /* 0x00005e0010067a24 */
/* 0x000fe200078e020d */
/*0580*/ MOV R4, 0x4 ; /* 0x0000000400047802 */
/* 0x000fe20000000f00 */
/*0590*/ IMAD R2, R19, 0x2, R0 ; /* 0x0000000213027824 */
/* 0x000fc600078e0200 */
/*05a0*/ LEA R3, R19, R6, 0x1 ; /* 0x0000000613037211 */
/* 0x000fe200078e08ff */
/*05b0*/ IMAD R5, R2, c[0x0][0x178], R13 ; /* 0x00005e0002057a24 */
/* 0x000fc800078e020d */
/*05c0*/ IMAD.WIDE R2, R3, R4, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fc800078e0204 */
/*05d0*/ IMAD R5, R12, 0x2, R5 ; /* 0x000000020c057824 */
/* 0x002fe200078e0205 */
/*05e0*/ MOV R6, R2 ; /* 0x0000000200067202 */
/* 0x000fe40000000f00 */
/*05f0*/ MOV R15, R3 ; /* 0x00000003000f7202 */
/* 0x000fe20000000f00 */
/*0600*/ IMAD.WIDE R2, R5, R4, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fc800078e0204 */
/*0610*/ IMAD.MOV.U32 R7, RZ, RZ, R15 ; /* 0x000000ffff077224 */
/* 0x000fe200078e000f */
/*0620*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x0000aa000c1e1900 */
/*0630*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x0002e2000c1e1900 */
/*0640*/ IADD3 R17, R17, -0x1, RZ ; /* 0xffffffff11117810 */
/* 0x000fc80007ffe0ff */
/*0650*/ ISETP.NE.AND P0, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fe20003f05270 */
/*0660*/ IMAD.WIDE R2, R21, 0x4, R2 ; /* 0x0000000415027825 */
/* 0x001fe200078e0202 */
/*0670*/ IADD3 R6, P1, R6, 0x8, RZ ; /* 0x0000000806067810 */
/* 0x002fc80007f3e0ff */
/*0680*/ IADD3.X R15, RZ, R15, RZ, P1, !PT ; /* 0x0000000fff0f7210 */
/* 0x000fe20000ffe4ff */
/*0690*/ STS [R18+0x10], R11 ; /* 0x0000100b12007388 */
/* 0x004fe80000000800 */
/*06a0*/ STS [R18], R7 ; /* 0x0000000712007388 */
/* 0x008fe80000000800 */
/*06b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*06c0*/ LDS R8, [R13.X4+0x10] ; /* 0x000010000d087984 */
/* 0x000fe80000004800 */
/*06d0*/ LDS.64 R4, [R0.X8] ; /* 0x0000000000047984 */
/* 0x000e280000008a00 */
/*06e0*/ LDS R10, [R13.X4+0x18] ; /* 0x000018000d0a7984 */
/* 0x000e620000004800 */
/*06f0*/ FFMA R4, R8, R4, R9 ; /* 0x0000000408047223 */
/* 0x001fc80000000009 */
/*0700*/ FFMA R9, R10, R5, R4 ; /* 0x000000050a097223 */
/* 0x002fe20000000004 */
/*0710*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0720*/ @P0 BRA 0x610 ; /* 0xfffffee000000947 */
/* 0x000fea000383ffff */
/*0730*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0740*/ LEA R13, R12, R13, 0x1 ; /* 0x0000000d0c0d7211 */
/* 0x006fca00078e08ff */
/*0750*/ IMAD R2, R16, c[0x0][0x178], R13 ; /* 0x00005e0010027a24 */
/* 0x000fc800078e020d */
/*0760*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0770*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*0780*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0790*/ BRA 0x790; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <stdio.h>
#define TILE_WIDTH 2
__global__ void matMulKernel(float* d_N, float* d_M, float* d_P, int Width){
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
// Identify the row and column of the d_P element to work on
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
float Pvalue = 0;
// Loop over the d_M and d_N tiles required to compute d_P element
for (int m = 0; m < Width/TILE_WIDTH; ++m) {// Coolaborative loading of d_M and d_N tiles into shared memory
Mds[ty][tx] = d_M[Row*Width + m*TILE_WIDTH + tx];
Nds[ty][tx] = d_N[(m*TILE_WIDTH + ty)*Width + Col];
__syncthreads();
for (int k = 0; k < TILE_WIDTH; ++k) {
Pvalue += Mds[ty][k] * Nds[k][tx];
}
__syncthreads();
}
d_P[Row*Width + Col] = Pvalue;
}
void matMul(float* A, float* B, float* C, int width)
{
int size = width * width * sizeof(float);
static float *d_A, *d_B, *d_C;
cudaMalloc((void **) &d_A, size);
cudaMemcpy(d_A, A, size, cudaMemcpyHostToDevice);
cudaMalloc((void **) &d_B, size);
cudaMemcpy(d_B, B, size, cudaMemcpyHostToDevice);
cudaMalloc((void **) &d_C, size);
dim3 dimGrid(2, 2, 1);
dim3 dimBlock(2, 2, 1);
matMulKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C, width);
cudaMemcpy(C, d_C, size, cudaMemcpyDeviceToHost);
printf("\nA: \n");
for (int i = 0; i < 4; i++) {
for (int j = 0; j < 4; j++){
printf("%2.0f ", A[i + j*width]);
}
printf("\n");
}
printf("\nB: \n");
for (int i = 0; i < 4; i++) {
for (int j = 0; j < 4; j++){
printf("%2.0f ", B[i + j*width]);
}
printf("\n");
}
printf("\n-------------------------------------");
printf("\nC: \n");
for (int i = 0; i < 4; i++) {
for (int j = 0; j < 4; j++){
printf("%2.0f ", C[i + j*width]);
}
printf("\n");
}
printf("\n-------------------------------------\n");
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
}
int main() {
int width = 4;
static float h_A[16];
static float h_B[16];
static float h_C[16];
for (int i = 0; i < width; i++) {
for (int j = 0; j < width; j++) {
h_A[i + j*width] = (i+j)%2;
h_B[i + j*width] = (i+j)%3;
}
}
matMul(h_A, h_B, h_C, width);
} | .file "tmpxft_0016c1d0_00000000-6_matMulTile.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z12matMulKernelPfS_S_iPfS_S_i
.type _Z37__device_stub__Z12matMulKernelPfS_S_iPfS_S_i, @function
_Z37__device_stub__Z12matMulKernelPfS_S_iPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12matMulKernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z37__device_stub__Z12matMulKernelPfS_S_iPfS_S_i, .-_Z37__device_stub__Z12matMulKernelPfS_S_iPfS_S_i
.globl _Z12matMulKernelPfS_S_i
.type _Z12matMulKernelPfS_S_i, @function
_Z12matMulKernelPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12matMulKernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z12matMulKernelPfS_S_i, .-_Z12matMulKernelPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\nA: \n"
.LC1:
.string "%2.0f "
.LC2:
.string "\n"
.LC3:
.string "\nB: \n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "\n-------------------------------------"
.section .rodata.str1.1
.LC5:
.string "\nC: \n"
.section .rodata.str1.8
.align 8
.LC6:
.string "\n-------------------------------------\n"
.text
.globl _Z6matMulPfS_S_i
.type _Z6matMulPfS_S_i, @function
_Z6matMulPfS_S_i:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r15
movq %rsi, %r14
movq %rsi, 8(%rsp)
movq %rdx, (%rsp)
movl %ecx, %ebx
movl %ecx, %ebp
imull %ecx, %ebp
sall $2, %ebp
movslq %ebp, %rbp
movq %rbp, %rsi
leaq _ZZ6matMulPfS_S_iE3d_A(%rip), %rdi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r15, %rsi
movq _ZZ6matMulPfS_S_iE3d_A(%rip), %rdi
call cudaMemcpy@PLT
movq %rbp, %rsi
leaq _ZZ6matMulPfS_S_iE3d_B(%rip), %rdi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r14, %rsi
movq _ZZ6matMulPfS_S_iE3d_B(%rip), %rdi
call cudaMemcpy@PLT
movq %rbp, %rsi
leaq _ZZ6matMulPfS_S_iE3d_C(%rip), %rdi
call cudaMalloc@PLT
movl $2, 24(%rsp)
movl $2, 28(%rsp)
movl $2, 36(%rsp)
movl $2, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L12:
movl $2, %ecx
movq %rbp, %rdx
movq _ZZ6matMulPfS_S_iE3d_C(%rip), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %ebx, %rbx
salq $2, %rbx
movl $0, %r14d
leaq .LC1(%rip), %r13
.L13:
leaq (%r15,%r14,4), %r12
movl $4, %ebp
.L14:
pxor %xmm0, %xmm0
cvtss2sd (%r12), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq %rbx, %r12
subl $1, %ebp
jne .L14
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %r14
cmpq $4, %r14
jne .L13
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r14d
leaq .LC1(%rip), %r13
leaq .LC2(%rip), %r15
.L16:
movq 8(%rsp), %rax
leaq (%rax,%r14,4), %r12
movl $4, %ebp
.L17:
pxor %xmm0, %xmm0
cvtss2sd (%r12), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq %rbx, %r12
subl $1, %ebp
jne .L17
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %r14
cmpq $4, %r14
jne .L16
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r14d
leaq .LC1(%rip), %r13
leaq .LC2(%rip), %r15
.L19:
movq (%rsp), %rax
leaq (%rax,%r14,4), %r12
movl $4, %ebp
.L20:
pxor %xmm0, %xmm0
cvtss2sd (%r12), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq %rbx, %r12
subl $1, %ebp
jne .L20
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %r14
cmpq $4, %r14
jne .L19
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq _ZZ6matMulPfS_S_iE3d_A(%rip), %rdi
call cudaFree@PLT
movq _ZZ6matMulPfS_S_iE3d_B(%rip), %rdi
call cudaFree@PLT
movq _ZZ6matMulPfS_S_iE3d_C(%rip), %rdi
call cudaFree@PLT
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movl %ebx, %ecx
movq _ZZ6matMulPfS_S_iE3d_C(%rip), %rdx
movq _ZZ6matMulPfS_S_iE3d_B(%rip), %rsi
movq _ZZ6matMulPfS_S_iE3d_A(%rip), %rdi
call _Z37__device_stub__Z12matMulKernelPfS_S_iPfS_S_i
jmp .L12
.cfi_endproc
.LFE2057:
.size _Z6matMulPfS_S_i, .-_Z6matMulPfS_S_i
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZZ4mainE3h_A(%rip), %r8
leaq _ZZ4mainE3h_B(%rip), %rdi
movl $0, %r9d
.L28:
movl %r9d, %edx
movl $0, %ecx
.L29:
movl %edx, %r10d
sarl $31, %r10d
movl %edx, %esi
shrl $31, %esi
leal (%rdx,%rsi), %eax
andl $1, %eax
subl %esi, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%r8,%rcx)
movslq %edx, %rax
imulq $1431655766, %rax, %rax
shrq $32, %rax
subl %r10d, %eax
leal (%rax,%rax,2), %esi
movl %edx, %eax
subl %esi, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rdi,%rcx)
addl $1, %edx
addq $16, %rcx
cmpq $64, %rcx
jne .L29
addl $1, %r9d
addq $4, %r8
addq $4, %rdi
cmpl $4, %r9d
jne .L28
movl $4, %ecx
leaq _ZZ4mainE3h_C(%rip), %rdx
leaq _ZZ4mainE3h_B(%rip), %rsi
leaq _ZZ4mainE3h_A(%rip), %rdi
call _Z6matMulPfS_S_i
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z12matMulKernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z12matMulKernelPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZZ4mainE3h_C
.comm _ZZ4mainE3h_C,64,32
.local _ZZ4mainE3h_B
.comm _ZZ4mainE3h_B,64,32
.local _ZZ4mainE3h_A
.comm _ZZ4mainE3h_A,64,32
.local _ZZ6matMulPfS_S_iE3d_C
.comm _ZZ6matMulPfS_S_iE3d_C,8,8
.local _ZZ6matMulPfS_S_iE3d_B
.comm _ZZ6matMulPfS_S_iE3d_B,8,8
.local _ZZ6matMulPfS_S_iE3d_A
.comm _ZZ6matMulPfS_S_iE3d_A,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <stdio.h>
#define TILE_WIDTH 2
__global__ void matMulKernel(float* d_N, float* d_M, float* d_P, int Width){
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
// Identify the row and column of the d_P element to work on
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
float Pvalue = 0;
// Loop over the d_M and d_N tiles required to compute d_P element
for (int m = 0; m < Width/TILE_WIDTH; ++m) {// Coolaborative loading of d_M and d_N tiles into shared memory
Mds[ty][tx] = d_M[Row*Width + m*TILE_WIDTH + tx];
Nds[ty][tx] = d_N[(m*TILE_WIDTH + ty)*Width + Col];
__syncthreads();
for (int k = 0; k < TILE_WIDTH; ++k) {
Pvalue += Mds[ty][k] * Nds[k][tx];
}
__syncthreads();
}
d_P[Row*Width + Col] = Pvalue;
}
void matMul(float* A, float* B, float* C, int width)
{
int size = width * width * sizeof(float);
static float *d_A, *d_B, *d_C;
cudaMalloc((void **) &d_A, size);
cudaMemcpy(d_A, A, size, cudaMemcpyHostToDevice);
cudaMalloc((void **) &d_B, size);
cudaMemcpy(d_B, B, size, cudaMemcpyHostToDevice);
cudaMalloc((void **) &d_C, size);
dim3 dimGrid(2, 2, 1);
dim3 dimBlock(2, 2, 1);
matMulKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C, width);
cudaMemcpy(C, d_C, size, cudaMemcpyDeviceToHost);
printf("\nA: \n");
for (int i = 0; i < 4; i++) {
for (int j = 0; j < 4; j++){
printf("%2.0f ", A[i + j*width]);
}
printf("\n");
}
printf("\nB: \n");
for (int i = 0; i < 4; i++) {
for (int j = 0; j < 4; j++){
printf("%2.0f ", B[i + j*width]);
}
printf("\n");
}
printf("\n-------------------------------------");
printf("\nC: \n");
for (int i = 0; i < 4; i++) {
for (int j = 0; j < 4; j++){
printf("%2.0f ", C[i + j*width]);
}
printf("\n");
}
printf("\n-------------------------------------\n");
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
}
int main() {
int width = 4;
static float h_A[16];
static float h_B[16];
static float h_C[16];
for (int i = 0; i < width; i++) {
for (int j = 0; j < width; j++) {
h_A[i + j*width] = (i+j)%2;
h_B[i + j*width] = (i+j)%3;
}
}
matMul(h_A, h_B, h_C, width);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define TILE_WIDTH 2
__global__ void matMulKernel(float* d_N, float* d_M, float* d_P, int Width){
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
// Identify the row and column of the d_P element to work on
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
float Pvalue = 0;
// Loop over the d_M and d_N tiles required to compute d_P element
for (int m = 0; m < Width/TILE_WIDTH; ++m) {// Coolaborative loading of d_M and d_N tiles into shared memory
Mds[ty][tx] = d_M[Row*Width + m*TILE_WIDTH + tx];
Nds[ty][tx] = d_N[(m*TILE_WIDTH + ty)*Width + Col];
__syncthreads();
for (int k = 0; k < TILE_WIDTH; ++k) {
Pvalue += Mds[ty][k] * Nds[k][tx];
}
__syncthreads();
}
d_P[Row*Width + Col] = Pvalue;
}
void matMul(float* A, float* B, float* C, int width)
{
int size = width * width * sizeof(float);
static float *d_A, *d_B, *d_C;
hipMalloc((void **) &d_A, size);
hipMemcpy(d_A, A, size, hipMemcpyHostToDevice);
hipMalloc((void **) &d_B, size);
hipMemcpy(d_B, B, size, hipMemcpyHostToDevice);
hipMalloc((void **) &d_C, size);
dim3 dimGrid(2, 2, 1);
dim3 dimBlock(2, 2, 1);
matMulKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C, width);
hipMemcpy(C, d_C, size, hipMemcpyDeviceToHost);
printf("\nA: \n");
for (int i = 0; i < 4; i++) {
for (int j = 0; j < 4; j++){
printf("%2.0f ", A[i + j*width]);
}
printf("\n");
}
printf("\nB: \n");
for (int i = 0; i < 4; i++) {
for (int j = 0; j < 4; j++){
printf("%2.0f ", B[i + j*width]);
}
printf("\n");
}
printf("\n-------------------------------------");
printf("\nC: \n");
for (int i = 0; i < 4; i++) {
for (int j = 0; j < 4; j++){
printf("%2.0f ", C[i + j*width]);
}
printf("\n");
}
printf("\n-------------------------------------\n");
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
}
int main() {
int width = 4;
static float h_A[16];
static float h_B[16];
static float h_C[16];
for (int i = 0; i < width; i++) {
for (int j = 0; j < width; j++) {
h_A[i + j*width] = (i+j)%2;
h_B[i + j*width] = (i+j)%3;
}
}
matMul(h_A, h_B, h_C, width);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define TILE_WIDTH 2
__global__ void matMulKernel(float* d_N, float* d_M, float* d_P, int Width){
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
// Identify the row and column of the d_P element to work on
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
float Pvalue = 0;
// Loop over the d_M and d_N tiles required to compute d_P element
for (int m = 0; m < Width/TILE_WIDTH; ++m) {// Coolaborative loading of d_M and d_N tiles into shared memory
Mds[ty][tx] = d_M[Row*Width + m*TILE_WIDTH + tx];
Nds[ty][tx] = d_N[(m*TILE_WIDTH + ty)*Width + Col];
__syncthreads();
for (int k = 0; k < TILE_WIDTH; ++k) {
Pvalue += Mds[ty][k] * Nds[k][tx];
}
__syncthreads();
}
d_P[Row*Width + Col] = Pvalue;
}
void matMul(float* A, float* B, float* C, int width)
{
int size = width * width * sizeof(float);
static float *d_A, *d_B, *d_C;
hipMalloc((void **) &d_A, size);
hipMemcpy(d_A, A, size, hipMemcpyHostToDevice);
hipMalloc((void **) &d_B, size);
hipMemcpy(d_B, B, size, hipMemcpyHostToDevice);
hipMalloc((void **) &d_C, size);
dim3 dimGrid(2, 2, 1);
dim3 dimBlock(2, 2, 1);
matMulKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C, width);
hipMemcpy(C, d_C, size, hipMemcpyDeviceToHost);
printf("\nA: \n");
for (int i = 0; i < 4; i++) {
for (int j = 0; j < 4; j++){
printf("%2.0f ", A[i + j*width]);
}
printf("\n");
}
printf("\nB: \n");
for (int i = 0; i < 4; i++) {
for (int j = 0; j < 4; j++){
printf("%2.0f ", B[i + j*width]);
}
printf("\n");
}
printf("\n-------------------------------------");
printf("\nC: \n");
for (int i = 0; i < 4; i++) {
for (int j = 0; j < 4; j++){
printf("%2.0f ", C[i + j*width]);
}
printf("\n");
}
printf("\n-------------------------------------\n");
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
}
int main() {
int width = 4;
static float h_A[16];
static float h_B[16];
static float h_C[16];
for (int i = 0; i < width; i++) {
for (int j = 0; j < width; j++) {
h_A[i + j*width] = (i+j)%2;
h_B[i + j*width] = (i+j)%3;
}
}
matMul(h_A, h_B, h_C, width);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12matMulKernelPfS_S_i
.globl _Z12matMulKernelPfS_S_i
.p2align 8
.type _Z12matMulKernelPfS_S_i,@function
_Z12matMulKernelPfS_S_i:
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v5, v0, 10, 10
v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v3, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v4, s15, 1, v5
v_lshl_add_u32 v0, s14, 1, v3
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 2
s_cbranch_scc1 .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v8, 2, v3
v_lshlrev_b32_e32 v6, 3, v5
v_mad_u64_u32 v[1:2], null, v4, s2, v[3:4]
s_lshr_b32 s3, s2, 31
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v7, 16, v8
v_add_nc_u32_e32 v3, v6, v8
s_add_i32 s3, s2, s3
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v8, v7, v6
s_ashr_i32 s3, s3, 1
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
s_lshl_b32 s9, s8, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v10, s9, v5
v_add_nc_u32_e32 v9, s9, v1
s_mov_b32 s9, 0
v_mad_u64_u32 v[11:12], null, v10, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v12, 31, v11
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, vcc_lo, s6, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v11, vcc_lo, s4, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
global_load_b32 v10, v[9:10], off
global_load_b32 v11, v[11:12], off
v_mov_b32_e32 v9, v7
s_waitcnt vmcnt(1)
ds_store_b32 v3, v10
s_waitcnt vmcnt(0)
ds_store_b32 v8, v11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
v_add_nc_u32_e32 v10, s9, v6
s_add_i32 s9, s9, 4
ds_load_b32 v11, v9
ds_load_b32 v10, v10
v_add_nc_u32_e32 v9, 8, v9
s_cmp_lg_u32 s9, 4
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, v10, v11
s_cbranch_scc0 .LBB0_3
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, s3
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[5:6], null, v4, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[0:1], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12matMulKernelPfS_S_i
.amdhsa_group_segment_fixed_size 32
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12matMulKernelPfS_S_i, .Lfunc_end0-_Z12matMulKernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 32
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12matMulKernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12matMulKernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define TILE_WIDTH 2
__global__ void matMulKernel(float* d_N, float* d_M, float* d_P, int Width){
__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x; int by = blockIdx.y;
int tx = threadIdx.x; int ty = threadIdx.y;
// Identify the row and column of the d_P element to work on
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
float Pvalue = 0;
// Loop over the d_M and d_N tiles required to compute d_P element
for (int m = 0; m < Width/TILE_WIDTH; ++m) {// Coolaborative loading of d_M and d_N tiles into shared memory
Mds[ty][tx] = d_M[Row*Width + m*TILE_WIDTH + tx];
Nds[ty][tx] = d_N[(m*TILE_WIDTH + ty)*Width + Col];
__syncthreads();
for (int k = 0; k < TILE_WIDTH; ++k) {
Pvalue += Mds[ty][k] * Nds[k][tx];
}
__syncthreads();
}
d_P[Row*Width + Col] = Pvalue;
}
void matMul(float* A, float* B, float* C, int width)
{
int size = width * width * sizeof(float);
static float *d_A, *d_B, *d_C;
hipMalloc((void **) &d_A, size);
hipMemcpy(d_A, A, size, hipMemcpyHostToDevice);
hipMalloc((void **) &d_B, size);
hipMemcpy(d_B, B, size, hipMemcpyHostToDevice);
hipMalloc((void **) &d_C, size);
dim3 dimGrid(2, 2, 1);
dim3 dimBlock(2, 2, 1);
matMulKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C, width);
hipMemcpy(C, d_C, size, hipMemcpyDeviceToHost);
printf("\nA: \n");
for (int i = 0; i < 4; i++) {
for (int j = 0; j < 4; j++){
printf("%2.0f ", A[i + j*width]);
}
printf("\n");
}
printf("\nB: \n");
for (int i = 0; i < 4; i++) {
for (int j = 0; j < 4; j++){
printf("%2.0f ", B[i + j*width]);
}
printf("\n");
}
printf("\n-------------------------------------");
printf("\nC: \n");
for (int i = 0; i < 4; i++) {
for (int j = 0; j < 4; j++){
printf("%2.0f ", C[i + j*width]);
}
printf("\n");
}
printf("\n-------------------------------------\n");
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
}
int main() {
int width = 4;
static float h_A[16];
static float h_B[16];
static float h_C[16];
for (int i = 0; i < width; i++) {
for (int j = 0; j < width; j++) {
h_A[i + j*width] = (i+j)%2;
h_B[i + j*width] = (i+j)%3;
}
}
matMul(h_A, h_B, h_C, width);
} | .text
.file "matMulTile.hip"
.globl _Z27__device_stub__matMulKernelPfS_S_i # -- Begin function _Z27__device_stub__matMulKernelPfS_S_i
.p2align 4, 0x90
.type _Z27__device_stub__matMulKernelPfS_S_i,@function
_Z27__device_stub__matMulKernelPfS_S_i: # @_Z27__device_stub__matMulKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12matMulKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__matMulKernelPfS_S_i, .Lfunc_end0-_Z27__device_stub__matMulKernelPfS_S_i
.cfi_endproc
# -- End function
.globl _Z6matMulPfS_S_i # -- Begin function _Z6matMulPfS_S_i
.p2align 4, 0x90
.type _Z6matMulPfS_S_i,@function
_Z6matMulPfS_S_i: # @_Z6matMulPfS_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movq %rdx, %r15
movq %rsi, %r14
movq %rdi, %rbx
movl %ecx, %eax
imull %ecx, %eax
shll $2, %eax
movslq %eax, %r12
movl $_ZZ6matMulPfS_S_iE3d_A, %edi
movq %r12, %rsi
callq hipMalloc
movq _ZZ6matMulPfS_S_iE3d_A(%rip), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movl $_ZZ6matMulPfS_S_iE3d_B, %edi
movq %r12, %rsi
callq hipMalloc
movq _ZZ6matMulPfS_S_iE3d_B(%rip), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movl $_ZZ6matMulPfS_S_iE3d_C, %edi
movq %r12, %rsi
callq hipMalloc
movabsq $8589934594, %rdi # imm = 0x200000002
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq _ZZ6matMulPfS_S_iE3d_A(%rip), %rax
movq _ZZ6matMulPfS_S_iE3d_B(%rip), %rcx
movq _ZZ6matMulPfS_S_iE3d_C(%rip), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ebp, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12matMulKernelPfS_S_i, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq _ZZ6matMulPfS_S_iE3d_C(%rip), %rsi
movq %r15, 16(%rsp) # 8-byte Spill
movq %r15, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
movslq %ebp, %r12
shlq $2, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_3: # %.preheader54
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
movl $4, %ebp
movq %rbx, %r15
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_3 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r15), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
addq %r12, %r15
decq %rbp
jne .LBB1_4
# %bb.5: # in Loop: Header=BB1_3 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
addq $4, %rbx
cmpq $4, %r13
jne .LBB1_3
# %bb.6:
movl $.Lstr.1, %edi
callq puts@PLT
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_7: # %.preheader53
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
movl $4, %r13d
movq %r14, %rbx
.p2align 4, 0x90
.LBB1_8: # Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
addq %r12, %rbx
decq %r13
jne .LBB1_8
# %bb.9: # in Loop: Header=BB1_7 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addq $4, %r14
cmpq $4, %r15
jne .LBB1_7
# %bb.10:
xorl %r14d, %r14d
movl $.Lstr.3, %edi
xorl %eax, %eax
callq printf
movl $.Lstr.2, %edi
callq puts@PLT
movq 16(%rsp), %r13 # 8-byte Reload
.p2align 4, 0x90
.LBB1_11: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_12 Depth 2
movl $4, %r15d
movq %r13, %rbx
.p2align 4, 0x90
.LBB1_12: # Parent Loop BB1_11 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
addq %r12, %rbx
decq %r15
jne .LBB1_12
# %bb.13: # in Loop: Header=BB1_11 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $4, %r13
cmpq $4, %r14
jne .LBB1_11
# %bb.14:
movl $.Lstr.3, %edi
callq puts@PLT
movq _ZZ6matMulPfS_S_iE3d_A(%rip), %rdi
callq hipFree
movq _ZZ6matMulPfS_S_iE3d_B(%rip), %rdi
callq hipFree
movq _ZZ6matMulPfS_S_iE3d_C(%rip), %rdi
callq hipFree
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z6matMulPfS_S_i, .Lfunc_end1-_Z6matMulPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
xorl %eax, %eax
movl $2863311531, %ecx # imm = 0xAAAAAAAB
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
movq $-64, %rsi
movl %edx, %edi
.p2align 4, 0x90
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movl %edi, %r8d
imulq %rcx, %r8
shrq $33, %r8
leal (%r8,%r8,2), %r8d
movl %edi, %r9d
andl $1, %r9d
xorps %xmm0, %xmm0
cvtsi2ss %r9d, %xmm0
movl %edi, %r9d
subl %r8d, %r9d
xorps %xmm1, %xmm1
cvtsi2ss %r9d, %xmm1
movss %xmm0, _ZZ4mainE3h_A+64(%rax,%rsi)
movss %xmm1, _ZZ4mainE3h_B+64(%rax,%rsi)
incl %edi
addq $16, %rsi
jne .LBB2_2
# %bb.3: # in Loop: Header=BB2_1 Depth=1
incq %rdx
addq $4, %rax
cmpq $4, %rdx
jne .LBB2_1
# %bb.4:
pushq %rax
.cfi_def_cfa_offset 16
movl $_ZZ4mainE3h_A, %edi
movl $_ZZ4mainE3h_B, %esi
movl $_ZZ4mainE3h_C, %edx
movl $4, %ecx
callq _Z6matMulPfS_S_i
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12matMulKernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12matMulKernelPfS_S_i,@object # @_Z12matMulKernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z12matMulKernelPfS_S_i
.p2align 3, 0x0
_Z12matMulKernelPfS_S_i:
.quad _Z27__device_stub__matMulKernelPfS_S_i
.size _Z12matMulKernelPfS_S_i, 8
.type _ZZ6matMulPfS_S_iE3d_A,@object # @_ZZ6matMulPfS_S_iE3d_A
.local _ZZ6matMulPfS_S_iE3d_A
.comm _ZZ6matMulPfS_S_iE3d_A,8,8
.type _ZZ6matMulPfS_S_iE3d_B,@object # @_ZZ6matMulPfS_S_iE3d_B
.local _ZZ6matMulPfS_S_iE3d_B
.comm _ZZ6matMulPfS_S_iE3d_B,8,8
.type _ZZ6matMulPfS_S_iE3d_C,@object # @_ZZ6matMulPfS_S_iE3d_C
.local _ZZ6matMulPfS_S_iE3d_C
.comm _ZZ6matMulPfS_S_iE3d_C,8,8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%2.0f "
.size .L.str.1, 7
.type _ZZ4mainE3h_A,@object # @_ZZ4mainE3h_A
.local _ZZ4mainE3h_A
.comm _ZZ4mainE3h_A,64,16
.type _ZZ4mainE3h_B,@object # @_ZZ4mainE3h_B
.local _ZZ4mainE3h_B
.comm _ZZ4mainE3h_B,64,16
.type _ZZ4mainE3h_C,@object # @_ZZ4mainE3h_C
.local _ZZ4mainE3h_C
.comm _ZZ4mainE3h_C,64,16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12matMulKernelPfS_S_i"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nA: "
.size .Lstr, 5
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\nB: "
.size .Lstr.1, 5
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\nC: "
.size .Lstr.2, 5
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "\n-------------------------------------"
.size .Lstr.3, 39
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__matMulKernelPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12matMulKernelPfS_S_i
.addrsig_sym _ZZ6matMulPfS_S_iE3d_A
.addrsig_sym _ZZ6matMulPfS_S_iE3d_B
.addrsig_sym _ZZ6matMulPfS_S_iE3d_C
.addrsig_sym _ZZ4mainE3h_A
.addrsig_sym _ZZ4mainE3h_B
.addrsig_sym _ZZ4mainE3h_C
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12matMulKernelPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0020*/ MOV R14, c[0x0][0x178] ; /* 0x00005e00000e7a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R14, 0x2, PT ; /* 0x000000020e00780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R12, SR_CTAID.X ; /* 0x00000000000c7919 */
/* 0x000e680000002500 */
/*0080*/ S2R R13, SR_TID.X ; /* 0x00000000000d7919 */
/* 0x000ea20000002100 */
/*0090*/ LEA R16, R3, R0, 0x1 ; /* 0x0000000003107211 */
/* 0x001fca00078e08ff */
/*00a0*/ @!P0 BRA 0x730 ; /* 0x0000068000008947 */
/* 0x000fea0003800000 */
/*00b0*/ LEA.HI R2, R14, c[0x0][0x178], RZ, 0x1 ; /* 0x00005e000e027a11 */
/* 0x000fe200078f08ff */
/*00c0*/ HFMA2.MMA R19, -RZ, RZ, 0, 0 ; /* 0x00000000ff137435 */
/* 0x000fe200000001ff */
/*00d0*/ SHF.L.U32 R18, R0, 0x3, RZ ; /* 0x0000000300127819 */
/* 0x000fe200000006ff */
/*00e0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*00f0*/ SHF.R.S32.HI R22, RZ, 0x1, R2 ; /* 0x00000001ff167819 */
/* 0x000fe40000011402 */
/*0100*/ SHF.L.U32 R21, R14, 0x1, RZ ; /* 0x000000010e157819 */
/* 0x000fe200000006ff */
/*0110*/ IMAD R18, R13, 0x4, R18 ; /* 0x000000040d127824 */
/* 0x004fe200078e0212 */
/*0120*/ IADD3 R2, R22.reuse, -0x1, RZ ; /* 0xffffffff16027810 */
/* 0x040fe40007ffe0ff */
/*0130*/ LOP3.LUT R17, R22, 0x3, RZ, 0xc0, !PT ; /* 0x0000000316117812 */
/* 0x000fc400078ec0ff */
/*0140*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0150*/ ISETP.NE.AND P0, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fd60003f05270 */
/*0160*/ @!P1 BRA 0x560 ; /* 0x000003f000009947 */
/* 0x000fea0003800000 */
/*0170*/ MOV R20, 0x4 ; /* 0x0000000400147802 */
/* 0x000fe20000000f00 */
/*0180*/ IMAD R15, R0, c[0x0][0x178], R13.reuse ; /* 0x00005e00000f7a24 */
/* 0x100fe200078e020d */
/*0190*/ IADD3 R22, -R22, R17, RZ ; /* 0x0000001116167210 */
/* 0x000fe20007ffe1ff */
/*01a0*/ IMAD R3, R16, c[0x0][0x178], R13 ; /* 0x00005e0010037a24 */
/* 0x000fe200078e020d */
/*01b0*/ MOV R19, RZ ; /* 0x000000ff00137202 */
/* 0x000fe20000000f00 */
/*01c0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*01d0*/ LEA R15, R12, R15, 0x1 ; /* 0x0000000f0c0f7211 */
/* 0x002fe200078e08ff */
/*01e0*/ IMAD.WIDE R2, R3, R20, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fc800078e0214 */
/*01f0*/ IMAD.WIDE R4, R15, R20, c[0x0][0x160] ; /* 0x000058000f047625 */
/* 0x000fe200078e0214 */
/*0200*/ LDG.E R23, [R2.64] ; /* 0x0000000402177981 */
/* 0x000ea8000c1e1900 */
/*0210*/ LDG.E R25, [R4.64] ; /* 0x0000000404197981 */
/* 0x000ee2000c1e1900 */
/*0220*/ IMAD.WIDE R10, R21, 0x4, R4 ; /* 0x00000004150a7825 */
/* 0x000fc600078e0204 */
/*0230*/ STS [R18], R23 ; /* 0x0000001712007388 */
/* 0x004fe80000000800 */
/*0240*/ STS [R18+0x10], R25 ; /* 0x0000101912007388 */
/* 0x008fe80000000800 */
/*0250*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0260*/ LDS R8, [R13.X4+0x10] ; /* 0x000010000d087984 */
/* 0x000fe80000004800 */
/*0270*/ LDS R26, [R13.X4+0x18] ; /* 0x000018000d1a7984 */
/* 0x000fe80000004800 */
/*0280*/ LDS.64 R6, [R0.X8] ; /* 0x0000000000067984 */
/* 0x000e280000008a00 */
/*0290*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02a0*/ LDG.E R29, [R2.64+0x8] ; /* 0x00000804021d7981 */
/* 0x000ea8000c1e1900 */
/*02b0*/ LDG.E R28, [R10.64] ; /* 0x000000040a1c7981 */
/* 0x000ee2000c1e1900 */
/*02c0*/ FFMA R6, R8, R6, R9 ; /* 0x0000000608067223 */
/* 0x001fc40000000009 */
/*02d0*/ IMAD.WIDE R8, R21, 0x4, R10 ; /* 0x0000000415087825 */
/* 0x000fe200078e020a */
/*02e0*/ STS [R18], R29 ; /* 0x0000001d12007388 */
/* 0x004fe80000000800 */
/*02f0*/ STS [R18+0x10], R28 ; /* 0x0000101c12007388 */
/* 0x008fe80000000800 */
/*0300*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0310*/ LDS R23, [R13.X4+0x10] ; /* 0x000010000d177984 */
/* 0x000fe80000004800 */
/*0320*/ LDS R24, [R13.X4+0x18] ; /* 0x000018000d187984 */
/* 0x000fe80000004800 */
/*0330*/ LDS.64 R4, [R0.X8] ; /* 0x0000000000047984 */
/* 0x000e280000008a00 */
/*0340*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0350*/ LDG.E R25, [R2.64+0x10] ; /* 0x0000100402197981 */
/* 0x000ea8000c1e1900 */
/*0360*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x000ee2000c1e1900 */
/*0370*/ FFMA R27, R26, R7, R6 ; /* 0x000000071a1b7223 */
/* 0x000fc60000000006 */
/*0380*/ STS [R18], R25 ; /* 0x0000001912007388 */
/* 0x004fe80000000800 */
/*0390*/ STS [R18+0x10], R11 ; /* 0x0000100b12007388 */
/* 0x0083e80000000800 */
/*03a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*03b0*/ IMAD.WIDE R10, R21, 0x4, R8 ; /* 0x00000004150a7825 */
/* 0x002fca00078e0208 */
/*03c0*/ LDS R25, [R13.X4+0x10] ; /* 0x000010000d197984 */
/* 0x000fe80000004800 */
/*03d0*/ LDS R26, [R13.X4+0x18] ; /* 0x000018000d1a7984 */
/* 0x000fe80000004800 */
/*03e0*/ LDS.64 R6, [R0.X8] ; /* 0x0000000000067984 */
/* 0x000e680000008a00 */
/*03f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0400*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea8000c1e1900 */
/*0410*/ LDG.E R29, [R2.64+0x18] ; /* 0x00001804021d7981 */
/* 0x000722000c1e1900 */
/*0420*/ FFMA R27, R23, R4, R27 ; /* 0x00000004171b7223 */
/* 0x001fe2000000001b */
/*0430*/ IADD3 R19, R19, 0x4, RZ ; /* 0x0000000413137810 */
/* 0x000fc40007ffe0ff */
/*0440*/ LEA R15, R14, R15, 0x3 ; /* 0x0000000f0e0f7211 */
/* 0x000fe200078e18ff */
/*0450*/ FFMA R5, R24, R5, R27 ; /* 0x0000000518057223 */
/* 0x000fc8000000001b */
/*0460*/ FFMA R5, R25, R6, R5 ; /* 0x0000000619057223 */
/* 0x002fe20000000005 */
/*0470*/ IADD3 R2, P2, R2, 0x20, RZ ; /* 0x0000002002027810 */
/* 0x008fe20007f5e0ff */
/*0480*/ IMAD.IADD R6, R22, 0x1, R19 ; /* 0x0000000116067824 */
/* 0x000fe400078e0213 */
/*0490*/ FFMA R5, R26, R7, R5 ; /* 0x000000071a057223 */
/* 0x000fe20000000005 */
/*04a0*/ IADD3.X R3, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff037210 */
/* 0x000fe400017fe4ff */
/*04b0*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f25270 */
/*04c0*/ STS [R18+0x10], R10 ; /* 0x0000100a12007388 */
/* 0x004fe80000000800 */
/*04d0*/ STS [R18], R29 ; /* 0x0000001d12007388 */
/* 0x010fe80000000800 */
/*04e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04f0*/ LDS R23, [R13.X4+0x10] ; /* 0x000010000d177984 */
/* 0x000fe80000004800 */
/*0500*/ LDS.64 R8, [R0.X8] ; /* 0x0000000000087984 */
/* 0x000e280000008a00 */
/*0510*/ LDS R4, [R13.X4+0x18] ; /* 0x000018000d047984 */
/* 0x000e620000004800 */
/*0520*/ FFMA R5, R23, R8, R5 ; /* 0x0000000817057223 */
/* 0x001fc80000000005 */
/*0530*/ FFMA R9, R4, R9, R5 ; /* 0x0000000904097223 */
/* 0x002fe20000000005 */
/*0540*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0550*/ @P1 BRA 0x1f0 ; /* 0xfffffc9000001947 */
/* 0x000fea000383ffff */
/*0560*/ @!P0 BRA 0x730 ; /* 0x000001c000008947 */
/* 0x000fea0003800000 */
/*0570*/ IMAD R6, R16, c[0x0][0x178], R13 ; /* 0x00005e0010067a24 */
/* 0x000fe200078e020d */
/*0580*/ MOV R4, 0x4 ; /* 0x0000000400047802 */
/* 0x000fe20000000f00 */
/*0590*/ IMAD R2, R19, 0x2, R0 ; /* 0x0000000213027824 */
/* 0x000fc600078e0200 */
/*05a0*/ LEA R3, R19, R6, 0x1 ; /* 0x0000000613037211 */
/* 0x000fe200078e08ff */
/*05b0*/ IMAD R5, R2, c[0x0][0x178], R13 ; /* 0x00005e0002057a24 */
/* 0x000fc800078e020d */
/*05c0*/ IMAD.WIDE R2, R3, R4, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fc800078e0204 */
/*05d0*/ IMAD R5, R12, 0x2, R5 ; /* 0x000000020c057824 */
/* 0x002fe200078e0205 */
/*05e0*/ MOV R6, R2 ; /* 0x0000000200067202 */
/* 0x000fe40000000f00 */
/*05f0*/ MOV R15, R3 ; /* 0x00000003000f7202 */
/* 0x000fe20000000f00 */
/*0600*/ IMAD.WIDE R2, R5, R4, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fc800078e0204 */
/*0610*/ IMAD.MOV.U32 R7, RZ, RZ, R15 ; /* 0x000000ffff077224 */
/* 0x000fe200078e000f */
/*0620*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x0000aa000c1e1900 */
/*0630*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x0002e2000c1e1900 */
/*0640*/ IADD3 R17, R17, -0x1, RZ ; /* 0xffffffff11117810 */
/* 0x000fc80007ffe0ff */
/*0650*/ ISETP.NE.AND P0, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fe20003f05270 */
/*0660*/ IMAD.WIDE R2, R21, 0x4, R2 ; /* 0x0000000415027825 */
/* 0x001fe200078e0202 */
/*0670*/ IADD3 R6, P1, R6, 0x8, RZ ; /* 0x0000000806067810 */
/* 0x002fc80007f3e0ff */
/*0680*/ IADD3.X R15, RZ, R15, RZ, P1, !PT ; /* 0x0000000fff0f7210 */
/* 0x000fe20000ffe4ff */
/*0690*/ STS [R18+0x10], R11 ; /* 0x0000100b12007388 */
/* 0x004fe80000000800 */
/*06a0*/ STS [R18], R7 ; /* 0x0000000712007388 */
/* 0x008fe80000000800 */
/*06b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*06c0*/ LDS R8, [R13.X4+0x10] ; /* 0x000010000d087984 */
/* 0x000fe80000004800 */
/*06d0*/ LDS.64 R4, [R0.X8] ; /* 0x0000000000047984 */
/* 0x000e280000008a00 */
/*06e0*/ LDS R10, [R13.X4+0x18] ; /* 0x000018000d0a7984 */
/* 0x000e620000004800 */
/*06f0*/ FFMA R4, R8, R4, R9 ; /* 0x0000000408047223 */
/* 0x001fc80000000009 */
/*0700*/ FFMA R9, R10, R5, R4 ; /* 0x000000050a097223 */
/* 0x002fe20000000004 */
/*0710*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0720*/ @P0 BRA 0x610 ; /* 0xfffffee000000947 */
/* 0x000fea000383ffff */
/*0730*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0740*/ LEA R13, R12, R13, 0x1 ; /* 0x0000000d0c0d7211 */
/* 0x006fca00078e08ff */
/*0750*/ IMAD R2, R16, c[0x0][0x178], R13 ; /* 0x00005e0010027a24 */
/* 0x000fc800078e020d */
/*0760*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0770*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*0780*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0790*/ BRA 0x790; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12matMulKernelPfS_S_i
.globl _Z12matMulKernelPfS_S_i
.p2align 8
.type _Z12matMulKernelPfS_S_i,@function
_Z12matMulKernelPfS_S_i:
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v5, v0, 10, 10
v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v3, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v4, s15, 1, v5
v_lshl_add_u32 v0, s14, 1, v3
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 2
s_cbranch_scc1 .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v8, 2, v3
v_lshlrev_b32_e32 v6, 3, v5
v_mad_u64_u32 v[1:2], null, v4, s2, v[3:4]
s_lshr_b32 s3, s2, 31
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v7, 16, v8
v_add_nc_u32_e32 v3, v6, v8
s_add_i32 s3, s2, s3
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v8, v7, v6
s_ashr_i32 s3, s3, 1
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
s_lshl_b32 s9, s8, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v10, s9, v5
v_add_nc_u32_e32 v9, s9, v1
s_mov_b32 s9, 0
v_mad_u64_u32 v[11:12], null, v10, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v12, 31, v11
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, vcc_lo, s6, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v11, vcc_lo, s4, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
global_load_b32 v10, v[9:10], off
global_load_b32 v11, v[11:12], off
v_mov_b32_e32 v9, v7
s_waitcnt vmcnt(1)
ds_store_b32 v3, v10
s_waitcnt vmcnt(0)
ds_store_b32 v8, v11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
v_add_nc_u32_e32 v10, s9, v6
s_add_i32 s9, s9, 4
ds_load_b32 v11, v9
ds_load_b32 v10, v10
v_add_nc_u32_e32 v9, 8, v9
s_cmp_lg_u32 s9, 4
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, v10, v11
s_cbranch_scc0 .LBB0_3
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, s3
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[5:6], null, v4, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[0:1], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12matMulKernelPfS_S_i
.amdhsa_group_segment_fixed_size 32
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12matMulKernelPfS_S_i, .Lfunc_end0-_Z12matMulKernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 32
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12matMulKernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12matMulKernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016c1d0_00000000-6_matMulTile.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z12matMulKernelPfS_S_iPfS_S_i
.type _Z37__device_stub__Z12matMulKernelPfS_S_iPfS_S_i, @function
_Z37__device_stub__Z12matMulKernelPfS_S_iPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12matMulKernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z37__device_stub__Z12matMulKernelPfS_S_iPfS_S_i, .-_Z37__device_stub__Z12matMulKernelPfS_S_iPfS_S_i
.globl _Z12matMulKernelPfS_S_i
.type _Z12matMulKernelPfS_S_i, @function
_Z12matMulKernelPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12matMulKernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z12matMulKernelPfS_S_i, .-_Z12matMulKernelPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\nA: \n"
.LC1:
.string "%2.0f "
.LC2:
.string "\n"
.LC3:
.string "\nB: \n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "\n-------------------------------------"
.section .rodata.str1.1
.LC5:
.string "\nC: \n"
.section .rodata.str1.8
.align 8
.LC6:
.string "\n-------------------------------------\n"
.text
.globl _Z6matMulPfS_S_i
.type _Z6matMulPfS_S_i, @function
_Z6matMulPfS_S_i:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r15
movq %rsi, %r14
movq %rsi, 8(%rsp)
movq %rdx, (%rsp)
movl %ecx, %ebx
movl %ecx, %ebp
imull %ecx, %ebp
sall $2, %ebp
movslq %ebp, %rbp
movq %rbp, %rsi
leaq _ZZ6matMulPfS_S_iE3d_A(%rip), %rdi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r15, %rsi
movq _ZZ6matMulPfS_S_iE3d_A(%rip), %rdi
call cudaMemcpy@PLT
movq %rbp, %rsi
leaq _ZZ6matMulPfS_S_iE3d_B(%rip), %rdi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r14, %rsi
movq _ZZ6matMulPfS_S_iE3d_B(%rip), %rdi
call cudaMemcpy@PLT
movq %rbp, %rsi
leaq _ZZ6matMulPfS_S_iE3d_C(%rip), %rdi
call cudaMalloc@PLT
movl $2, 24(%rsp)
movl $2, 28(%rsp)
movl $2, 36(%rsp)
movl $2, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L12:
movl $2, %ecx
movq %rbp, %rdx
movq _ZZ6matMulPfS_S_iE3d_C(%rip), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %ebx, %rbx
salq $2, %rbx
movl $0, %r14d
leaq .LC1(%rip), %r13
.L13:
leaq (%r15,%r14,4), %r12
movl $4, %ebp
.L14:
pxor %xmm0, %xmm0
cvtss2sd (%r12), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq %rbx, %r12
subl $1, %ebp
jne .L14
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %r14
cmpq $4, %r14
jne .L13
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r14d
leaq .LC1(%rip), %r13
leaq .LC2(%rip), %r15
.L16:
movq 8(%rsp), %rax
leaq (%rax,%r14,4), %r12
movl $4, %ebp
.L17:
pxor %xmm0, %xmm0
cvtss2sd (%r12), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq %rbx, %r12
subl $1, %ebp
jne .L17
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %r14
cmpq $4, %r14
jne .L16
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r14d
leaq .LC1(%rip), %r13
leaq .LC2(%rip), %r15
.L19:
movq (%rsp), %rax
leaq (%rax,%r14,4), %r12
movl $4, %ebp
.L20:
pxor %xmm0, %xmm0
cvtss2sd (%r12), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq %rbx, %r12
subl $1, %ebp
jne .L20
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %r14
cmpq $4, %r14
jne .L19
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq _ZZ6matMulPfS_S_iE3d_A(%rip), %rdi
call cudaFree@PLT
movq _ZZ6matMulPfS_S_iE3d_B(%rip), %rdi
call cudaFree@PLT
movq _ZZ6matMulPfS_S_iE3d_C(%rip), %rdi
call cudaFree@PLT
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movl %ebx, %ecx
movq _ZZ6matMulPfS_S_iE3d_C(%rip), %rdx
movq _ZZ6matMulPfS_S_iE3d_B(%rip), %rsi
movq _ZZ6matMulPfS_S_iE3d_A(%rip), %rdi
call _Z37__device_stub__Z12matMulKernelPfS_S_iPfS_S_i
jmp .L12
.cfi_endproc
.LFE2057:
.size _Z6matMulPfS_S_i, .-_Z6matMulPfS_S_i
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZZ4mainE3h_A(%rip), %r8
leaq _ZZ4mainE3h_B(%rip), %rdi
movl $0, %r9d
.L28:
movl %r9d, %edx
movl $0, %ecx
.L29:
movl %edx, %r10d
sarl $31, %r10d
movl %edx, %esi
shrl $31, %esi
leal (%rdx,%rsi), %eax
andl $1, %eax
subl %esi, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%r8,%rcx)
movslq %edx, %rax
imulq $1431655766, %rax, %rax
shrq $32, %rax
subl %r10d, %eax
leal (%rax,%rax,2), %esi
movl %edx, %eax
subl %esi, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rdi,%rcx)
addl $1, %edx
addq $16, %rcx
cmpq $64, %rcx
jne .L29
addl $1, %r9d
addq $4, %r8
addq $4, %rdi
cmpl $4, %r9d
jne .L28
movl $4, %ecx
leaq _ZZ4mainE3h_C(%rip), %rdx
leaq _ZZ4mainE3h_B(%rip), %rsi
leaq _ZZ4mainE3h_A(%rip), %rdi
call _Z6matMulPfS_S_i
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z12matMulKernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z12matMulKernelPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZZ4mainE3h_C
.comm _ZZ4mainE3h_C,64,32
.local _ZZ4mainE3h_B
.comm _ZZ4mainE3h_B,64,32
.local _ZZ4mainE3h_A
.comm _ZZ4mainE3h_A,64,32
.local _ZZ6matMulPfS_S_iE3d_C
.comm _ZZ6matMulPfS_S_iE3d_C,8,8
.local _ZZ6matMulPfS_S_iE3d_B
.comm _ZZ6matMulPfS_S_iE3d_B,8,8
.local _ZZ6matMulPfS_S_iE3d_A
.comm _ZZ6matMulPfS_S_iE3d_A,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matMulTile.hip"
.globl _Z27__device_stub__matMulKernelPfS_S_i # -- Begin function _Z27__device_stub__matMulKernelPfS_S_i
.p2align 4, 0x90
.type _Z27__device_stub__matMulKernelPfS_S_i,@function
_Z27__device_stub__matMulKernelPfS_S_i: # @_Z27__device_stub__matMulKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12matMulKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__matMulKernelPfS_S_i, .Lfunc_end0-_Z27__device_stub__matMulKernelPfS_S_i
.cfi_endproc
# -- End function
.globl _Z6matMulPfS_S_i # -- Begin function _Z6matMulPfS_S_i
.p2align 4, 0x90
.type _Z6matMulPfS_S_i,@function
_Z6matMulPfS_S_i: # @_Z6matMulPfS_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movq %rdx, %r15
movq %rsi, %r14
movq %rdi, %rbx
movl %ecx, %eax
imull %ecx, %eax
shll $2, %eax
movslq %eax, %r12
movl $_ZZ6matMulPfS_S_iE3d_A, %edi
movq %r12, %rsi
callq hipMalloc
movq _ZZ6matMulPfS_S_iE3d_A(%rip), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movl $_ZZ6matMulPfS_S_iE3d_B, %edi
movq %r12, %rsi
callq hipMalloc
movq _ZZ6matMulPfS_S_iE3d_B(%rip), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movl $_ZZ6matMulPfS_S_iE3d_C, %edi
movq %r12, %rsi
callq hipMalloc
movabsq $8589934594, %rdi # imm = 0x200000002
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq _ZZ6matMulPfS_S_iE3d_A(%rip), %rax
movq _ZZ6matMulPfS_S_iE3d_B(%rip), %rcx
movq _ZZ6matMulPfS_S_iE3d_C(%rip), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ebp, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12matMulKernelPfS_S_i, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq _ZZ6matMulPfS_S_iE3d_C(%rip), %rsi
movq %r15, 16(%rsp) # 8-byte Spill
movq %r15, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
movslq %ebp, %r12
shlq $2, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_3: # %.preheader54
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
movl $4, %ebp
movq %rbx, %r15
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_3 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r15), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
addq %r12, %r15
decq %rbp
jne .LBB1_4
# %bb.5: # in Loop: Header=BB1_3 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
addq $4, %rbx
cmpq $4, %r13
jne .LBB1_3
# %bb.6:
movl $.Lstr.1, %edi
callq puts@PLT
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_7: # %.preheader53
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
movl $4, %r13d
movq %r14, %rbx
.p2align 4, 0x90
.LBB1_8: # Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
addq %r12, %rbx
decq %r13
jne .LBB1_8
# %bb.9: # in Loop: Header=BB1_7 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addq $4, %r14
cmpq $4, %r15
jne .LBB1_7
# %bb.10:
xorl %r14d, %r14d
movl $.Lstr.3, %edi
xorl %eax, %eax
callq printf
movl $.Lstr.2, %edi
callq puts@PLT
movq 16(%rsp), %r13 # 8-byte Reload
.p2align 4, 0x90
.LBB1_11: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_12 Depth 2
movl $4, %r15d
movq %r13, %rbx
.p2align 4, 0x90
.LBB1_12: # Parent Loop BB1_11 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
addq %r12, %rbx
decq %r15
jne .LBB1_12
# %bb.13: # in Loop: Header=BB1_11 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $4, %r13
cmpq $4, %r14
jne .LBB1_11
# %bb.14:
movl $.Lstr.3, %edi
callq puts@PLT
movq _ZZ6matMulPfS_S_iE3d_A(%rip), %rdi
callq hipFree
movq _ZZ6matMulPfS_S_iE3d_B(%rip), %rdi
callq hipFree
movq _ZZ6matMulPfS_S_iE3d_C(%rip), %rdi
callq hipFree
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z6matMulPfS_S_i, .Lfunc_end1-_Z6matMulPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
xorl %eax, %eax
movl $2863311531, %ecx # imm = 0xAAAAAAAB
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
movq $-64, %rsi
movl %edx, %edi
.p2align 4, 0x90
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movl %edi, %r8d
imulq %rcx, %r8
shrq $33, %r8
leal (%r8,%r8,2), %r8d
movl %edi, %r9d
andl $1, %r9d
xorps %xmm0, %xmm0
cvtsi2ss %r9d, %xmm0
movl %edi, %r9d
subl %r8d, %r9d
xorps %xmm1, %xmm1
cvtsi2ss %r9d, %xmm1
movss %xmm0, _ZZ4mainE3h_A+64(%rax,%rsi)
movss %xmm1, _ZZ4mainE3h_B+64(%rax,%rsi)
incl %edi
addq $16, %rsi
jne .LBB2_2
# %bb.3: # in Loop: Header=BB2_1 Depth=1
incq %rdx
addq $4, %rax
cmpq $4, %rdx
jne .LBB2_1
# %bb.4:
pushq %rax
.cfi_def_cfa_offset 16
movl $_ZZ4mainE3h_A, %edi
movl $_ZZ4mainE3h_B, %esi
movl $_ZZ4mainE3h_C, %edx
movl $4, %ecx
callq _Z6matMulPfS_S_i
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12matMulKernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12matMulKernelPfS_S_i,@object # @_Z12matMulKernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z12matMulKernelPfS_S_i
.p2align 3, 0x0
_Z12matMulKernelPfS_S_i:
.quad _Z27__device_stub__matMulKernelPfS_S_i
.size _Z12matMulKernelPfS_S_i, 8
.type _ZZ6matMulPfS_S_iE3d_A,@object # @_ZZ6matMulPfS_S_iE3d_A
.local _ZZ6matMulPfS_S_iE3d_A
.comm _ZZ6matMulPfS_S_iE3d_A,8,8
.type _ZZ6matMulPfS_S_iE3d_B,@object # @_ZZ6matMulPfS_S_iE3d_B
.local _ZZ6matMulPfS_S_iE3d_B
.comm _ZZ6matMulPfS_S_iE3d_B,8,8
.type _ZZ6matMulPfS_S_iE3d_C,@object # @_ZZ6matMulPfS_S_iE3d_C
.local _ZZ6matMulPfS_S_iE3d_C
.comm _ZZ6matMulPfS_S_iE3d_C,8,8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%2.0f "
.size .L.str.1, 7
.type _ZZ4mainE3h_A,@object # @_ZZ4mainE3h_A
.local _ZZ4mainE3h_A
.comm _ZZ4mainE3h_A,64,16
.type _ZZ4mainE3h_B,@object # @_ZZ4mainE3h_B
.local _ZZ4mainE3h_B
.comm _ZZ4mainE3h_B,64,16
.type _ZZ4mainE3h_C,@object # @_ZZ4mainE3h_C
.local _ZZ4mainE3h_C
.comm _ZZ4mainE3h_C,64,16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12matMulKernelPfS_S_i"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nA: "
.size .Lstr, 5
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\nB: "
.size .Lstr.1, 5
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\nC: "
.size .Lstr.2, 5
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "\n-------------------------------------"
.size .Lstr.3, 39
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__matMulKernelPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12matMulKernelPfS_S_i
.addrsig_sym _ZZ6matMulPfS_S_iE3d_A
.addrsig_sym _ZZ6matMulPfS_S_iE3d_B
.addrsig_sym _ZZ6matMulPfS_S_iE3d_C
.addrsig_sym _ZZ4mainE3h_A
.addrsig_sym _ZZ4mainE3h_B
.addrsig_sym _ZZ4mainE3h_C
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
// adds array elements in a loop like normal
void addArrays(int* a, int* b, int* c, int count) {
for (int i = 0; i < count; i++) {
c[i] = a[i] + b[i];
}
}
// simulates adding each element in a separate thread indexed by `i`
void addArraysThread(int* a, int* b, int* c, int i) {
c[i] = a[i] + b[i];
}
// CUDA-compatible "kernel" (aka function) prepended with `__global__`
// notice thread number/ID not needed to be passed in as argument
__global__ void addArraysCUDA(int* a, int* b, int* c) {
int i = threadIdx.x; // thread index available "globally"
c[i] = a[i] + b[i];
}
int main() {
const int count = 5;
const int size = count * sizeof(int);
// the `h` prepending each variable shows that it is memory that sits on the "host" (CPU)
int ha[] = {1,2,3,4,5};
int hb[] = {10,20,30,40,50};
int hc[count];
// memory that sits on the "device" (GPU)
int *da, *db, *dc;
// allocate memory (on device?) using `cudaMalloc`
cudaMalloc(&da, size); // if `da` is already a pointer, why use `&da` to get address?
cudaMalloc(&db, size);
cudaMalloc(&dc, size);
// copy memory from host to device
// cudaMemcpy(*dest, *src, size_t size, kind) // the "kind" says whether you're copying from host -> device or vice versa
cudaMemcpy(da, ha, size, cudaMemcpyKind::cudaMemcpyHostToDevice);
cudaMemcpy(db, hb, size, cudaMemcpyKind::cudaMemcpyHostToDevice);
// addArrays(a, b, c, count); // this does the computation all at once
// for (int i=0; i < count; i++) { // simulates different threads (not actually parallel)
// addArraysThread(a, b, c, i);
// }
// this is how you call CUDA kernels??
addArraysCUDA<<<1, count>>>(da, db, dc); // 1 block with `count` threads
// copy memory from device back to host
cudaMemcpy(hc, dc, size, cudaMemcpyKind::cudaMemcpyDeviceToHost);
// print results
for (int i=0; i < count; i++) {
printf("%d ", hc[i]);
}
printf("\n");
} | code for sm_80
Function : _Z13addArraysCUDAPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
// adds array elements in a loop like normal
void addArrays(int* a, int* b, int* c, int count) {
for (int i = 0; i < count; i++) {
c[i] = a[i] + b[i];
}
}
// simulates adding each element in a separate thread indexed by `i`
void addArraysThread(int* a, int* b, int* c, int i) {
c[i] = a[i] + b[i];
}
// CUDA-compatible "kernel" (aka function) prepended with `__global__`
// notice thread number/ID not needed to be passed in as argument
__global__ void addArraysCUDA(int* a, int* b, int* c) {
int i = threadIdx.x; // thread index available "globally"
c[i] = a[i] + b[i];
}
int main() {
const int count = 5;
const int size = count * sizeof(int);
// the `h` prepending each variable shows that it is memory that sits on the "host" (CPU)
int ha[] = {1,2,3,4,5};
int hb[] = {10,20,30,40,50};
int hc[count];
// memory that sits on the "device" (GPU)
int *da, *db, *dc;
// allocate memory (on device?) using `cudaMalloc`
cudaMalloc(&da, size); // if `da` is already a pointer, why use `&da` to get address?
cudaMalloc(&db, size);
cudaMalloc(&dc, size);
// copy memory from host to device
// cudaMemcpy(*dest, *src, size_t size, kind) // the "kind" says whether you're copying from host -> device or vice versa
cudaMemcpy(da, ha, size, cudaMemcpyKind::cudaMemcpyHostToDevice);
cudaMemcpy(db, hb, size, cudaMemcpyKind::cudaMemcpyHostToDevice);
// addArrays(a, b, c, count); // this does the computation all at once
// for (int i=0; i < count; i++) { // simulates different threads (not actually parallel)
// addArraysThread(a, b, c, i);
// }
// this is how you call CUDA kernels??
addArraysCUDA<<<1, count>>>(da, db, dc); // 1 block with `count` threads
// copy memory from device back to host
cudaMemcpy(hc, dc, size, cudaMemcpyKind::cudaMemcpyDeviceToHost);
// print results
for (int i=0; i < count; i++) {
printf("%d ", hc[i]);
}
printf("\n");
} | .file "tmpxft_000cbd5e_00000000-6_hello_world.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9addArraysPiS_S_i
.type _Z9addArraysPiS_S_i, @function
_Z9addArraysPiS_S_i:
.LFB2057:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L3
movslq %ecx, %rcx
leaq 0(,%rcx,4), %r8
movl $0, %eax
.L5:
movl (%rsi,%rax), %ecx
addl (%rdi,%rax), %ecx
movl %ecx, (%rdx,%rax)
addq $4, %rax
cmpq %r8, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z9addArraysPiS_S_i, .-_Z9addArraysPiS_S_i
.globl _Z15addArraysThreadPiS_S_i
.type _Z15addArraysThreadPiS_S_i, @function
_Z15addArraysThreadPiS_S_i:
.LFB2058:
.cfi_startproc
endbr64
movslq %ecx, %rcx
movl (%rsi,%rcx,4), %eax
addl (%rdi,%rcx,4), %eax
movl %eax, (%rdx,%rcx,4)
ret
.cfi_endproc
.LFE2058:
.size _Z15addArraysThreadPiS_S_i, .-_Z15addArraysThreadPiS_S_i
.globl _Z37__device_stub__Z13addArraysCUDAPiS_S_PiS_S_
.type _Z37__device_stub__Z13addArraysCUDAPiS_S_PiS_S_, @function
_Z37__device_stub__Z13addArraysCUDAPiS_S_PiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13addArraysCUDAPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z37__device_stub__Z13addArraysCUDAPiS_S_PiS_S_, .-_Z37__device_stub__Z13addArraysCUDAPiS_S_PiS_S_
.globl _Z13addArraysCUDAPiS_S_
.type _Z13addArraysCUDAPiS_S_, @function
_Z13addArraysCUDAPiS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13addArraysCUDAPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z13addArraysCUDAPiS_S_, .-_Z13addArraysCUDAPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $144, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $1, 48(%rsp)
movl $2, 52(%rsp)
movl $3, 56(%rsp)
movl $4, 60(%rsp)
movl $5, 64(%rsp)
movl $10, 80(%rsp)
movl $20, 84(%rsp)
movl $30, 88(%rsp)
movl $40, 92(%rsp)
movl $50, 96(%rsp)
movq %rsp, %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $20, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $20, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $5, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L17:
leaq 112(%rsp), %rbx
movl $2, %ecx
movl $20, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 132(%rsp), %r12
leaq .LC0(%rip), %rbp
.L18:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L18
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L23
movl $0, %eax
addq $144, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z37__device_stub__Z13addArraysCUDAPiS_S_PiS_S_
jmp .L17
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z13addArraysCUDAPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z13addArraysCUDAPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
// adds array elements in a loop like normal
void addArrays(int* a, int* b, int* c, int count) {
for (int i = 0; i < count; i++) {
c[i] = a[i] + b[i];
}
}
// simulates adding each element in a separate thread indexed by `i`
void addArraysThread(int* a, int* b, int* c, int i) {
c[i] = a[i] + b[i];
}
// CUDA-compatible "kernel" (aka function) prepended with `__global__`
// notice thread number/ID not needed to be passed in as argument
__global__ void addArraysCUDA(int* a, int* b, int* c) {
int i = threadIdx.x; // thread index available "globally"
c[i] = a[i] + b[i];
}
int main() {
const int count = 5;
const int size = count * sizeof(int);
// the `h` prepending each variable shows that it is memory that sits on the "host" (CPU)
int ha[] = {1,2,3,4,5};
int hb[] = {10,20,30,40,50};
int hc[count];
// memory that sits on the "device" (GPU)
int *da, *db, *dc;
// allocate memory (on device?) using `cudaMalloc`
cudaMalloc(&da, size); // if `da` is already a pointer, why use `&da` to get address?
cudaMalloc(&db, size);
cudaMalloc(&dc, size);
// copy memory from host to device
// cudaMemcpy(*dest, *src, size_t size, kind) // the "kind" says whether you're copying from host -> device or vice versa
cudaMemcpy(da, ha, size, cudaMemcpyKind::cudaMemcpyHostToDevice);
cudaMemcpy(db, hb, size, cudaMemcpyKind::cudaMemcpyHostToDevice);
// addArrays(a, b, c, count); // this does the computation all at once
// for (int i=0; i < count; i++) { // simulates different threads (not actually parallel)
// addArraysThread(a, b, c, i);
// }
// this is how you call CUDA kernels??
addArraysCUDA<<<1, count>>>(da, db, dc); // 1 block with `count` threads
// copy memory from device back to host
cudaMemcpy(hc, dc, size, cudaMemcpyKind::cudaMemcpyDeviceToHost);
// print results
for (int i=0; i < count; i++) {
printf("%d ", hc[i]);
}
printf("\n");
} | #include "hip/hip_runtime.h"
#include <stdio.h>
// adds array elements in a loop like normal
void addArrays(int* a, int* b, int* c, int count) {
for (int i = 0; i < count; i++) {
c[i] = a[i] + b[i];
}
}
// simulates adding each element in a separate thread indexed by `i`
void addArraysThread(int* a, int* b, int* c, int i) {
c[i] = a[i] + b[i];
}
// CUDA-compatible "kernel" (aka function) prepended with `__global__`
// notice thread number/ID not needed to be passed in as argument
__global__ void addArraysCUDA(int* a, int* b, int* c) {
int i = threadIdx.x; // thread index available "globally"
c[i] = a[i] + b[i];
}
int main() {
const int count = 5;
const int size = count * sizeof(int);
// the `h` prepending each variable shows that it is memory that sits on the "host" (CPU)
int ha[] = {1,2,3,4,5};
int hb[] = {10,20,30,40,50};
int hc[count];
// memory that sits on the "device" (GPU)
int *da, *db, *dc;
// allocate memory (on device?) using `cudaMalloc`
hipMalloc(&da, size); // if `da` is already a pointer, why use `&da` to get address?
hipMalloc(&db, size);
hipMalloc(&dc, size);
// copy memory from host to device
// cudaMemcpy(*dest, *src, size_t size, kind) // the "kind" says whether you're copying from host -> device or vice versa
hipMemcpy(da, ha, size, hipMemcpyKind::hipMemcpyHostToDevice);
hipMemcpy(db, hb, size, hipMemcpyKind::hipMemcpyHostToDevice);
// addArrays(a, b, c, count); // this does the computation all at once
// for (int i=0; i < count; i++) { // simulates different threads (not actually parallel)
// addArraysThread(a, b, c, i);
// }
// this is how you call CUDA kernels??
addArraysCUDA<<<1, count>>>(da, db, dc); // 1 block with `count` threads
// copy memory from device back to host
hipMemcpy(hc, dc, size, hipMemcpyKind::hipMemcpyDeviceToHost);
// print results
for (int i=0; i < count; i++) {
printf("%d ", hc[i]);
}
printf("\n");
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
// adds array elements in a loop like normal
void addArrays(int* a, int* b, int* c, int count) {
for (int i = 0; i < count; i++) {
c[i] = a[i] + b[i];
}
}
// simulates adding each element in a separate thread indexed by `i`
void addArraysThread(int* a, int* b, int* c, int i) {
c[i] = a[i] + b[i];
}
// CUDA-compatible "kernel" (aka function) prepended with `__global__`
// notice thread number/ID not needed to be passed in as argument
__global__ void addArraysCUDA(int* a, int* b, int* c) {
int i = threadIdx.x; // thread index available "globally"
c[i] = a[i] + b[i];
}
int main() {
const int count = 5;
const int size = count * sizeof(int);
// the `h` prepending each variable shows that it is memory that sits on the "host" (CPU)
int ha[] = {1,2,3,4,5};
int hb[] = {10,20,30,40,50};
int hc[count];
// memory that sits on the "device" (GPU)
int *da, *db, *dc;
// allocate memory (on device?) using `cudaMalloc`
hipMalloc(&da, size); // if `da` is already a pointer, why use `&da` to get address?
hipMalloc(&db, size);
hipMalloc(&dc, size);
// copy memory from host to device
// cudaMemcpy(*dest, *src, size_t size, kind) // the "kind" says whether you're copying from host -> device or vice versa
hipMemcpy(da, ha, size, hipMemcpyKind::hipMemcpyHostToDevice);
hipMemcpy(db, hb, size, hipMemcpyKind::hipMemcpyHostToDevice);
// addArrays(a, b, c, count); // this does the computation all at once
// for (int i=0; i < count; i++) { // simulates different threads (not actually parallel)
// addArraysThread(a, b, c, i);
// }
// this is how you call CUDA kernels??
addArraysCUDA<<<1, count>>>(da, db, dc); // 1 block with `count` threads
// copy memory from device back to host
hipMemcpy(hc, dc, size, hipMemcpyKind::hipMemcpyDeviceToHost);
// print results
for (int i=0; i < count; i++) {
printf("%d ", hc[i]);
}
printf("\n");
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13addArraysCUDAPiS_S_
.globl _Z13addArraysCUDAPiS_S_
.p2align 8
.type _Z13addArraysCUDAPiS_S_,@function
_Z13addArraysCUDAPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13addArraysCUDAPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13addArraysCUDAPiS_S_, .Lfunc_end0-_Z13addArraysCUDAPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13addArraysCUDAPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z13addArraysCUDAPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
// adds array elements in a loop like normal
void addArrays(int* a, int* b, int* c, int count) {
for (int i = 0; i < count; i++) {
c[i] = a[i] + b[i];
}
}
// simulates adding each element in a separate thread indexed by `i`
void addArraysThread(int* a, int* b, int* c, int i) {
c[i] = a[i] + b[i];
}
// CUDA-compatible "kernel" (aka function) prepended with `__global__`
// notice thread number/ID not needed to be passed in as argument
__global__ void addArraysCUDA(int* a, int* b, int* c) {
int i = threadIdx.x; // thread index available "globally"
c[i] = a[i] + b[i];
}
int main() {
const int count = 5;
const int size = count * sizeof(int);
// the `h` prepending each variable shows that it is memory that sits on the "host" (CPU)
int ha[] = {1,2,3,4,5};
int hb[] = {10,20,30,40,50};
int hc[count];
// memory that sits on the "device" (GPU)
int *da, *db, *dc;
// allocate memory (on device?) using `cudaMalloc`
hipMalloc(&da, size); // if `da` is already a pointer, why use `&da` to get address?
hipMalloc(&db, size);
hipMalloc(&dc, size);
// copy memory from host to device
// cudaMemcpy(*dest, *src, size_t size, kind) // the "kind" says whether you're copying from host -> device or vice versa
hipMemcpy(da, ha, size, hipMemcpyKind::hipMemcpyHostToDevice);
hipMemcpy(db, hb, size, hipMemcpyKind::hipMemcpyHostToDevice);
// addArrays(a, b, c, count); // this does the computation all at once
// for (int i=0; i < count; i++) { // simulates different threads (not actually parallel)
// addArraysThread(a, b, c, i);
// }
// this is how you call CUDA kernels??
addArraysCUDA<<<1, count>>>(da, db, dc); // 1 block with `count` threads
// copy memory from device back to host
hipMemcpy(hc, dc, size, hipMemcpyKind::hipMemcpyDeviceToHost);
// print results
for (int i=0; i < count; i++) {
printf("%d ", hc[i]);
}
printf("\n");
} | .text
.file "hello_world.hip"
.globl _Z9addArraysPiS_S_i # -- Begin function _Z9addArraysPiS_S_i
.p2align 4, 0x90
.type _Z9addArraysPiS_S_i,@function
_Z9addArraysPiS_S_i: # @_Z9addArraysPiS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %ecx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rsi,%rcx,4), %r8d
addl (%rdi,%rcx,4), %r8d
movl %r8d, (%rdx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z9addArraysPiS_S_i, .Lfunc_end0-_Z9addArraysPiS_S_i
.cfi_endproc
# -- End function
.globl _Z15addArraysThreadPiS_S_i # -- Begin function _Z15addArraysThreadPiS_S_i
.p2align 4, 0x90
.type _Z15addArraysThreadPiS_S_i,@function
_Z15addArraysThreadPiS_S_i: # @_Z15addArraysThreadPiS_S_i
.cfi_startproc
# %bb.0:
movslq %ecx, %rax
movl (%rsi,%rax,4), %ecx
addl (%rdi,%rax,4), %ecx
movl %ecx, (%rdx,%rax,4)
retq
.Lfunc_end1:
.size _Z15addArraysThreadPiS_S_i, .Lfunc_end1-_Z15addArraysThreadPiS_S_i
.cfi_endproc
# -- End function
.globl _Z28__device_stub__addArraysCUDAPiS_S_ # -- Begin function _Z28__device_stub__addArraysCUDAPiS_S_
.p2align 4, 0x90
.type _Z28__device_stub__addArraysCUDAPiS_S_,@function
_Z28__device_stub__addArraysCUDAPiS_S_: # @_Z28__device_stub__addArraysCUDAPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13addArraysCUDAPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z28__device_stub__addArraysCUDAPiS_S_, .Lfunc_end2-_Z28__device_stub__addArraysCUDAPiS_S_
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI3_0:
.long 1 # 0x1
.long 2 # 0x2
.long 3 # 0x3
.long 4 # 0x4
.LCPI3_1:
.long 10 # 0xa
.long 20 # 0x14
.long 30 # 0x1e
.long 40 # 0x28
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $192, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -16
movaps .LCPI3_0(%rip), %xmm0 # xmm0 = [1,2,3,4]
movaps %xmm0, 160(%rsp)
movl $5, 176(%rsp)
movaps .LCPI3_1(%rip), %xmm0 # xmm0 = [10,20,30,40]
movaps %xmm0, 128(%rsp)
movl $50, 144(%rsp)
leaq 24(%rsp), %rdi
movl $20, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $20, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $20, %esi
callq hipMalloc
movq 24(%rsp), %rdi
leaq 160(%rsp), %rsi
movl $20, %edx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 128(%rsp), %rsi
movl $20, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 4(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
leaq 120(%rsp), %rax
movq %rax, 32(%rsp)
leaq 112(%rsp), %rax
movq %rax, 40(%rsp)
leaq 104(%rsp), %rax
movq %rax, 48(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z13addArraysCUDAPiS_S_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
movq 8(%rsp), %rsi
leaq 32(%rsp), %rdi
movl $20, %edx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_3: # =>This Inner Loop Header: Depth=1
movl 32(%rsp,%rbx,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $5, %rbx
jne .LBB3_3
# %bb.4:
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $192, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13addArraysCUDAPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13addArraysCUDAPiS_S_,@object # @_Z13addArraysCUDAPiS_S_
.section .rodata,"a",@progbits
.globl _Z13addArraysCUDAPiS_S_
.p2align 3, 0x0
_Z13addArraysCUDAPiS_S_:
.quad _Z28__device_stub__addArraysCUDAPiS_S_
.size _Z13addArraysCUDAPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13addArraysCUDAPiS_S_"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__addArraysCUDAPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13addArraysCUDAPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13addArraysCUDAPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13addArraysCUDAPiS_S_
.globl _Z13addArraysCUDAPiS_S_
.p2align 8
.type _Z13addArraysCUDAPiS_S_,@function
_Z13addArraysCUDAPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13addArraysCUDAPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13addArraysCUDAPiS_S_, .Lfunc_end0-_Z13addArraysCUDAPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13addArraysCUDAPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z13addArraysCUDAPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000cbd5e_00000000-6_hello_world.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9addArraysPiS_S_i
.type _Z9addArraysPiS_S_i, @function
_Z9addArraysPiS_S_i:
.LFB2057:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L3
movslq %ecx, %rcx
leaq 0(,%rcx,4), %r8
movl $0, %eax
.L5:
movl (%rsi,%rax), %ecx
addl (%rdi,%rax), %ecx
movl %ecx, (%rdx,%rax)
addq $4, %rax
cmpq %r8, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z9addArraysPiS_S_i, .-_Z9addArraysPiS_S_i
.globl _Z15addArraysThreadPiS_S_i
.type _Z15addArraysThreadPiS_S_i, @function
_Z15addArraysThreadPiS_S_i:
.LFB2058:
.cfi_startproc
endbr64
movslq %ecx, %rcx
movl (%rsi,%rcx,4), %eax
addl (%rdi,%rcx,4), %eax
movl %eax, (%rdx,%rcx,4)
ret
.cfi_endproc
.LFE2058:
.size _Z15addArraysThreadPiS_S_i, .-_Z15addArraysThreadPiS_S_i
.globl _Z37__device_stub__Z13addArraysCUDAPiS_S_PiS_S_
.type _Z37__device_stub__Z13addArraysCUDAPiS_S_PiS_S_, @function
_Z37__device_stub__Z13addArraysCUDAPiS_S_PiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13addArraysCUDAPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z37__device_stub__Z13addArraysCUDAPiS_S_PiS_S_, .-_Z37__device_stub__Z13addArraysCUDAPiS_S_PiS_S_
.globl _Z13addArraysCUDAPiS_S_
.type _Z13addArraysCUDAPiS_S_, @function
_Z13addArraysCUDAPiS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13addArraysCUDAPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z13addArraysCUDAPiS_S_, .-_Z13addArraysCUDAPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $144, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $1, 48(%rsp)
movl $2, 52(%rsp)
movl $3, 56(%rsp)
movl $4, 60(%rsp)
movl $5, 64(%rsp)
movl $10, 80(%rsp)
movl $20, 84(%rsp)
movl $30, 88(%rsp)
movl $40, 92(%rsp)
movl $50, 96(%rsp)
movq %rsp, %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $20, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $20, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $5, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L17:
leaq 112(%rsp), %rbx
movl $2, %ecx
movl $20, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 132(%rsp), %r12
leaq .LC0(%rip), %rbp
.L18:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L18
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L23
movl $0, %eax
addq $144, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z37__device_stub__Z13addArraysCUDAPiS_S_PiS_S_
jmp .L17
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z13addArraysCUDAPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z13addArraysCUDAPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hello_world.hip"
.globl _Z9addArraysPiS_S_i # -- Begin function _Z9addArraysPiS_S_i
.p2align 4, 0x90
.type _Z9addArraysPiS_S_i,@function
_Z9addArraysPiS_S_i: # @_Z9addArraysPiS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %ecx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rsi,%rcx,4), %r8d
addl (%rdi,%rcx,4), %r8d
movl %r8d, (%rdx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z9addArraysPiS_S_i, .Lfunc_end0-_Z9addArraysPiS_S_i
.cfi_endproc
# -- End function
.globl _Z15addArraysThreadPiS_S_i # -- Begin function _Z15addArraysThreadPiS_S_i
.p2align 4, 0x90
.type _Z15addArraysThreadPiS_S_i,@function
_Z15addArraysThreadPiS_S_i: # @_Z15addArraysThreadPiS_S_i
.cfi_startproc
# %bb.0:
movslq %ecx, %rax
movl (%rsi,%rax,4), %ecx
addl (%rdi,%rax,4), %ecx
movl %ecx, (%rdx,%rax,4)
retq
.Lfunc_end1:
.size _Z15addArraysThreadPiS_S_i, .Lfunc_end1-_Z15addArraysThreadPiS_S_i
.cfi_endproc
# -- End function
.globl _Z28__device_stub__addArraysCUDAPiS_S_ # -- Begin function _Z28__device_stub__addArraysCUDAPiS_S_
.p2align 4, 0x90
.type _Z28__device_stub__addArraysCUDAPiS_S_,@function
_Z28__device_stub__addArraysCUDAPiS_S_: # @_Z28__device_stub__addArraysCUDAPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13addArraysCUDAPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z28__device_stub__addArraysCUDAPiS_S_, .Lfunc_end2-_Z28__device_stub__addArraysCUDAPiS_S_
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI3_0:
.long 1 # 0x1
.long 2 # 0x2
.long 3 # 0x3
.long 4 # 0x4
.LCPI3_1:
.long 10 # 0xa
.long 20 # 0x14
.long 30 # 0x1e
.long 40 # 0x28
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $192, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -16
movaps .LCPI3_0(%rip), %xmm0 # xmm0 = [1,2,3,4]
movaps %xmm0, 160(%rsp)
movl $5, 176(%rsp)
movaps .LCPI3_1(%rip), %xmm0 # xmm0 = [10,20,30,40]
movaps %xmm0, 128(%rsp)
movl $50, 144(%rsp)
leaq 24(%rsp), %rdi
movl $20, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $20, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $20, %esi
callq hipMalloc
movq 24(%rsp), %rdi
leaq 160(%rsp), %rsi
movl $20, %edx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 128(%rsp), %rsi
movl $20, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 4(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
leaq 120(%rsp), %rax
movq %rax, 32(%rsp)
leaq 112(%rsp), %rax
movq %rax, 40(%rsp)
leaq 104(%rsp), %rax
movq %rax, 48(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z13addArraysCUDAPiS_S_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
movq 8(%rsp), %rsi
leaq 32(%rsp), %rdi
movl $20, %edx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_3: # =>This Inner Loop Header: Depth=1
movl 32(%rsp,%rbx,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $5, %rbx
jne .LBB3_3
# %bb.4:
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $192, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13addArraysCUDAPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13addArraysCUDAPiS_S_,@object # @_Z13addArraysCUDAPiS_S_
.section .rodata,"a",@progbits
.globl _Z13addArraysCUDAPiS_S_
.p2align 3, 0x0
_Z13addArraysCUDAPiS_S_:
.quad _Z28__device_stub__addArraysCUDAPiS_S_
.size _Z13addArraysCUDAPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13addArraysCUDAPiS_S_"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__addArraysCUDAPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13addArraysCUDAPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <math.h>
#include <time.h>
#include <unistd.h>
#include <cuda_runtime_api.h>
#include <errno.h>
#include <unistd.h>
/******************************************************************************
* This program takes an initial estimate of m and c and finds the associated
* rms error. It is then as a base to generate and evaluate 8 new estimates,
* which are steps in different directions in m-c space. The best estimate is
* then used as the base for another iteration of "generate and evaluate". This
* continues until none of the new estimates are better than the base. This is
* a gradient search for a minimum in mc-space.
*
* To compile:
* nvcc -o linearcuda_bishal linear_bishal_cuda.cu -lm
*
* To run:
* ./linearcuda_bishal
*
* Dr Kevan Buckley, University of Wolverhampton, 2018
*****************************************************************************/
typedef struct point_t{
double x;
double y;
}point_t;
int n_data = 1000;
__device__ int d_n_data =1000;
point_t data[] = {
{67.50,117.63},{65.33,126.07},{82.95,145.73},{76.19,113.32},
{87.53,145.91},{73.30,132.50},{76.57,134.90},{68.72,115.55},
{73.32,140.31},{78.84,143.44},{71.68,120.91},{92.42,138.04},
{76.05,128.45},{34.36,75.04},{91.02,154.71},{98.33,178.86},
{75.34,134.84},{84.94,143.54},{34.55,73.14},{22.78,36.84},
{11.34,37.95},{77.02,121.28},{20.48,54.11},{85.81,158.12},
{98.14,169.75},{61.93,126.98},{44.68,77.35},{38.15,83.43},
{30.16,67.27},{76.68,133.30},{86.62,141.45},{60.09,116.95},
{26.91,70.86},{ 9.10,37.19},{11.23,36.15},{26.50,59.09},
{41.44,93.35},{67.47,131.65},{89.46,161.35},{19.81,38.73},
{51.34,93.22},{97.28,174.58},{33.38,68.25},{19.98,40.87},
{44.04,85.03},{70.68,125.28},{84.78,128.46},{63.73,98.19},
{16.48,31.39},{91.67,169.18},{13.59,31.83},{69.96,133.01},
{15.59,53.61},{53.87,116.25},{57.95,119.53},{88.77,156.53},
{ 4.54,19.19},{60.18,111.69},{76.51,143.61},{21.62,54.08},
{53.82,107.72},{28.55,79.61},{51.32,89.52},{60.46,135.12},
{68.14,124.70},{13.20,32.38},{94.61,160.20},{57.63,99.17},
{80.81,143.84},{92.81,143.31},{91.60,164.46},{13.32,40.64},
{93.33,174.11},{50.18,102.21},{ 0.11,28.39},{69.56,119.09},
{55.02,110.04},{74.47,146.21},{91.14,163.71},{65.21,125.47},
{58.83,100.80},{10.02,46.51},{94.36,158.71},{51.22,103.94},
{ 9.25,34.11},{12.64,44.32},{50.24,104.77},{15.73,37.63},
{53.03,101.19},{30.42,72.53},{47.90,90.79},{25.89,68.64},
{75.24,126.35},{80.87,133.87},{ 5.86,31.16},{62.88,112.89},
{81.94,145.67},{51.81,88.24},{82.74,122.52},{80.97,139.14},
{ 0.28, 1.97},{62.20,111.18},{55.95,100.36},{29.17,61.74},
{71.13,120.95},{11.42,42.50},{38.60,70.96},{47.24,88.20},
{ 4.25,26.16},{13.53,50.16},{23.30,64.38},{96.18,162.57},
{97.45,167.05},{86.09,139.37},{19.61,40.67},{75.10,137.54},
{61.73,124.08},{ 7.59,27.78},{ 5.53,13.80},{59.76,116.05},
{19.08,55.39},{41.68,74.96},{16.33,42.42},{96.25,161.59},
{69.83,121.89},{ 5.65,37.87},{42.46,86.94},{79.37,151.11},
{48.34,97.43},{57.96,111.54},{22.31,63.95},{ 6.03,14.45},
{38.59,72.82},{91.91,166.06},{77.34,149.68},{20.95,49.40},
{18.24,44.16},{46.33,85.77},{87.69,162.06},{ 5.63,33.09},
{25.64,62.39},{78.37,129.15},{90.63,162.90},{59.07,108.46},
{ 3.73, 9.62},{73.31,127.30},{85.44,148.06},{62.86,111.04},
{27.61,66.72},{97.81,162.18},{76.86,141.77},{65.90,142.09},
{89.34,144.60},{ 9.42,48.00},{51.54,104.84},{11.47,42.53},
{42.31,79.72},{62.70,111.95},{15.81,44.71},{51.03,101.97},
{50.54,98.74},{84.62,138.28},{95.25,169.94},{ 3.97,31.21},
{10.63, 9.82},{ 1.47,32.91},{67.16,129.22},{10.14,26.05},
{52.42,103.57},{41.93,90.91},{96.18,166.50},{ 0.25,16.19},
{20.73,49.87},{34.86,70.58},{39.49,83.99},{93.26,153.09},
{89.43,147.70},{46.72,90.16},{30.27,50.94},{ 7.73,40.77},
{47.24,89.70},{60.71,110.70},{10.25,35.87},{87.93,176.16},
{81.83,132.92},{47.52,95.67},{ 8.22,30.97},{ 0.16,19.43},
{ 7.67,39.19},{25.22,46.59},{37.39,94.24},{23.87,54.68},
{53.00,94.78},{55.12,113.11},{ 0.39,17.41},{12.25,42.86},
{24.12,67.60},{40.49,92.29},{52.77,87.06},{12.23,46.57},
{67.85,125.89},{42.67,89.64},{34.42,61.02},{ 1.94,18.44},
{53.40,111.16},{89.61,164.56},{ 3.82, 3.73},{96.24,158.21},
{77.04,135.04},{97.05,148.24},{26.71,51.44},{95.02,163.28},
{34.29,61.81},{ 1.62,21.43},{67.74,107.75},{98.19,159.80},
{17.62,54.87},{85.72,146.11},{23.67,53.85},{49.02,101.01},
{93.66,161.56},{44.72,86.99},{72.81,113.39},{60.91,112.51},
{24.17,61.50},{49.89,89.80},{ 8.97,45.83},{26.67,59.28},
{62.50,111.35},{11.07,25.58},{37.01,63.82},{18.94,46.54},
{61.63,108.22},{28.93,50.01},{55.36,99.90},{92.64,173.42},
{28.57,52.10},{ 9.61,30.76},{19.82,52.09},{47.92,90.78},
{28.85,70.65},{33.80,38.50},{29.53,66.71},{42.50,89.01},
{34.95,92.60},{83.24,150.06},{94.97,158.22},{63.79,123.66},
{94.60,157.04},{79.72,136.29},{63.38,116.51},{16.22,41.53},
{40.06,65.75},{54.36,89.16},{65.52,130.07},{19.95,52.07},
{78.01,121.11},{32.30,71.77},{84.85,139.15},{50.25,98.61},
{72.77,124.69},{59.41,100.91},{89.09,168.89},{76.82,142.52},
{26.18,56.42},{10.95,52.42},{62.40,111.33},{62.71,102.03},
{ 2.35,13.42},{ 7.19,41.90},{62.53,123.58},{15.54,52.27},
{ 0.80,20.28},{ 5.30,26.03},{13.01,57.51},{19.16,35.04},
{59.74,133.37},{33.93,83.73},{ 4.54,17.74},{18.61,48.23},
{72.71,133.09},{51.18,90.42},{51.26,104.57},{58.02,83.55},
{68.78,148.00},{29.56,70.05},{10.44,22.10},{90.96,154.32},
{13.82,28.56},{88.00,150.89},{51.69,92.07},{54.30,90.90},
{57.44,101.77},{80.12,149.10},{10.78,39.64},{11.95,64.56},
{97.71,178.99},{37.08,69.88},{ 0.47,17.14},{65.62,109.62},
{99.78,179.04},{81.77,158.12},{11.90,33.54},{85.24,151.30},
{49.38,78.83},{63.79,114.06},{32.79,57.50},{31.96,88.52},
{84.21,144.62},{49.77,102.25},{49.55,88.18},{ 8.26,38.38},
{47.36,90.74},{97.88,170.49},{44.11,78.79},{38.23,88.99},
{40.69,69.98},{ 7.36,36.33},{56.85,111.52},{13.64,36.87},
{53.35,116.88},{72.47,124.76},{46.64,107.91},{94.73,151.85},
{66.61,117.51},{12.35,61.26},{79.14,159.92},{79.02,140.10},
{45.42,94.75},{16.54,29.85},{91.82,153.33},{28.86,55.11},
{50.75,79.96},{10.11,36.95},{32.04,68.39},{71.95,131.62},
{57.09,109.51},{10.91,27.38},{62.49,115.05},{20.30,46.80},
{93.11,159.57},{71.85,130.18},{53.28,108.81},{55.38,111.22},
{85.54,151.96},{22.64,52.50},{56.67,98.37},{ 0.97,21.47},
{72.50,138.03},{26.98,45.21},{96.25,167.19},{16.31,40.83},
{58.79,87.57},{47.38,89.11},{90.04,157.08},{32.23,62.24},
{11.57,34.79},{23.99,51.20},{64.23,105.49},{72.15,107.38},
{37.45,77.37},{73.55,128.18},{36.90,78.88},{45.26,95.74},
{37.99,74.96},{63.67,123.99},{68.51,129.23},{13.85,35.04},
{59.04,93.67},{54.42,102.56},{89.89,148.97},{76.40,139.33},
{15.26,37.71},{61.79,114.18},{31.03,61.43},{96.81,157.36},
{41.43,93.08},{59.88,107.00},{75.72,122.81},{47.51,113.65},
{39.71,81.28},{73.15,145.81},{13.27,27.44},{73.94,130.58},
{48.11,95.15},{91.97,147.09},{29.24,56.59},{88.10,143.34},
{83.07,136.67},{ 1.60,25.57},{83.37,132.98},{32.81,81.72},
{32.76,61.42},{26.69,62.44},{34.24,70.93},{75.68,125.27},
{96.68,165.04},{95.66,168.80},{79.86,144.53},{74.34,121.30},
{57.43,94.75},{56.67,79.08},{54.07,88.83},{99.94,171.14},
{66.96,110.58},{77.27,141.31},{68.77,120.16},{27.42,77.06},
{ 3.47,33.83},{22.31,49.66},{56.78,101.75},{96.06,157.01},
{ 1.29,25.47},{ 2.97,42.15},{66.51,105.60},{37.81,72.23},
{ 3.07,33.29},{37.37,92.70},{ 7.52,32.65},{43.43,75.38},
{63.53,120.10},{55.30,106.01},{65.04,118.04},{ 5.91,21.90},
{65.28,121.06},{29.55,51.16},{41.39,88.10},{35.63,81.24},
{86.27,136.99},{15.92,72.35},{75.93,120.09},{91.92,160.74},
{97.55,169.39},{70.19,117.49},{16.28,38.79},{44.36,81.43},
{87.91,149.02},{ 3.52,38.16},{59.12,120.72},{ 1.90, 0.73},
{83.31,156.42},{44.25,74.81},{36.88,57.45},{80.37,157.35},
{66.99,138.80},{79.54,145.55},{18.33,45.70},{64.15,122.52},
{34.89,69.76},{46.89,93.34},{14.47,48.95},{ 4.47,11.21},
{42.32,86.99},{31.84,63.03},{33.34,81.26},{ 4.88,25.36},
{79.82,133.64},{40.63,100.56},{63.46,121.03},{96.80,151.04},
{92.72,156.50},{90.13,156.67},{87.25,150.80},{63.02,122.96},
{17.30,47.83},{24.10,53.74},{55.24,105.56},{49.54,106.29},
{50.18,92.64},{28.50,73.07},{75.82,141.86},{43.76,88.26},
{33.55,61.23},{66.59,98.81},{25.78,64.50},{ 5.19,31.93},
{32.05,72.33},{61.50,119.08},{39.73,91.92},{80.39,146.69},
{73.53,149.32},{40.57,62.81},{91.25,166.56},{63.33,112.85},
{ 1.32,13.80},{87.01,143.92},{84.90,132.20},{36.73,88.35},
{81.82,127.95},{77.33,143.68},{ 4.44,17.14},{71.90,134.73},
{59.09,106.07},{83.32,145.03},{56.43,87.15},{55.72,118.37},
{35.02,93.87},{76.13,111.18},{43.98,75.47},{92.99,165.88},
{31.66,59.37},{28.52,59.74},{82.09,144.05},{26.09,49.24},
{70.97,117.20},{ 7.68,37.90},{70.42,123.06},{40.47,82.04},
{73.52,133.29},{21.29,62.15},{74.56,121.04},{76.26,137.21},
{10.29,56.09},{28.54,78.38},{21.19,63.67},{40.37,88.01},
{ 9.97,60.42},{59.83,106.32},{36.88,81.58},{64.00,122.44},
{44.79,60.82},{25.61,52.42},{32.59,72.08},{65.16,118.02},
{13.14,39.55},{75.40,123.94},{45.15,97.24},{53.90,113.09},
{75.55,129.32},{ 0.43,21.46},{52.76,92.05},{90.01,148.61},
{26.95,57.55},{30.46,68.83},{39.15,81.42},{58.32,98.73},
{70.37,115.08},{ 5.94,21.53},{ 3.43,33.83},{32.38,68.35},
{59.53,111.46},{37.94,108.20},{24.71,63.30},{96.93,166.78},
{87.47,146.91},{33.94,100.63},{76.73,141.16},{31.78,71.95},
{85.03,155.23},{ 2.52,39.44},{44.84,95.65},{77.68,131.95},
{41.72,86.46},{18.32,57.93},{69.89,120.19},{54.70,86.01},
{54.99,104.64},{48.59,95.15},{24.36,53.97},{51.98,96.80},
{60.23,100.55},{59.09,85.63},{33.81,67.74},{12.22,41.13},
{26.38,65.33},{ 7.09,30.43},{24.85,50.55},{99.52,170.23},
{84.73,129.42},{39.71,92.69},{57.91,105.37},{33.52,75.23},
{33.93,65.91},{27.34,52.79},{58.75,104.12},{60.52,110.72},
{ 2.81,12.48},{ 8.02,27.71},{64.73,120.96},{82.03,159.82},
{22.60,38.52},{24.08,61.92},{66.05,102.86},{19.42,49.76},
{48.04,97.54},{46.20,96.45},{ 1.17,17.39},{63.69,129.79},
{29.84,75.40},{26.53,45.12},{95.19,149.02},{90.77,157.73},
{41.81,86.87},{74.43,110.80},{49.39,97.73},{22.62,49.26},
{ 4.87,18.08},{19.41,58.94},{42.62,107.88},{77.24,159.90},
{80.67,133.41},{44.37,89.30},{51.39,91.86},{25.27,57.14},
{10.84,16.20},{99.73,182.30},{85.08,167.49},{16.49,38.24},
{48.48,98.37},{30.56,50.30},{45.38,97.80},{33.13,73.18},
{39.58,86.47},{56.27,115.05},{18.85,48.41},{51.63,99.71},
{ 7.00,29.08},{32.17,71.87},{44.00,94.70},{ 3.73,38.62},
{72.17,111.87},{29.35,54.28},{50.13,94.46},{91.52,170.01},
{40.05,72.34},{46.87,67.83},{76.24,138.98},{26.75,63.90},
{63.87,105.49},{13.12,23.17},{12.58,53.66},{ 8.20,43.82},
{14.36,32.76},{32.84,51.21},{11.45,24.07},{93.59,140.71},
{58.09,85.90},{52.69,102.77},{38.38,85.50},{98.36,158.74},
{74.87,125.72},{32.47,73.67},{55.48,122.80},{42.12,87.03},
{75.24,144.54},{71.66,134.49},{34.01,66.08},{58.69,105.94},
{35.47,72.45},{51.46,100.28},{87.79,150.58},{10.86,27.33},
{68.38,133.79},{38.57,86.54},{64.01,109.90},{17.09,63.00},
{ 9.34,35.52},{66.20,127.61},{22.82,52.08},{79.23,148.39},
{19.50,45.48},{ 4.76,14.25},{ 0.11,24.33},{55.86,91.16},
{43.58,90.07},{14.59,50.39},{39.88,99.03},{41.04,85.30},
{87.44,169.74},{55.54,98.60},{ 2.07, 1.75},{29.04,64.38},
{41.45,92.95},{73.41,124.41},{78.49,152.32},{33.64,87.75},
{67.48,139.43},{87.13,144.84},{59.65,100.97},{45.11,87.31},
{76.40,139.82},{62.21,124.75},{78.60,163.67},{20.57,49.21},
{80.06,138.88},{60.51,108.48},{ 2.05,29.92},{11.23,23.36},
{10.61,39.17},{30.63,63.71},{ 5.13,41.33},{74.37,123.26},
{14.03,38.39},{ 6.31,36.58},{ 9.16,36.90},{75.16,138.63},
{88.12,149.50},{ 1.78,31.54},{28.88,64.20},{79.20,136.08},
{27.98,48.89},{89.12,158.04},{ 9.51,11.76},{10.45,40.24},
{22.73,61.87},{73.97,124.05},{ 7.09,10.69},{11.73,32.78},
{90.67,166.68},{88.17,167.73},{97.82,164.53},{63.81,103.31},
{74.11,137.22},{71.03,119.75},{43.78,85.30},{84.66,148.37},
{12.33,30.33},{83.29,138.56},{21.34,71.07},{40.14,68.00},
{73.05,119.85},{ 7.44,29.55},{89.02,151.86},{17.24,61.99},
{41.66,73.47},{50.62,99.48},{60.53,111.85},{12.70,17.62},
{66.84,110.12},{52.27,89.56},{98.72,178.46},{79.92,113.48},
{23.55,43.25},{38.26,96.94},{56.52,118.31},{53.04,96.75},
{35.73,72.29},{60.43,109.43},{77.67,137.73},{45.78,98.97},
{32.36,67.11},{23.89,68.74},{24.53,45.00},{97.28,162.74},
{27.73,50.67},{90.85,165.35},{93.94,153.83},{ 6.63,43.74},
{93.38,150.59},{43.87,77.99},{49.91,86.07},{82.99,151.00},
{ 7.00,40.39},{46.17,89.39},{28.87,66.05},{72.85,141.73},
{27.21,58.82},{42.02,79.42},{95.29,149.89},{ 7.03,21.47},
{80.55,133.93},{75.29,147.77},{32.44,69.31},{29.14,61.10},
{94.21,157.98},{48.51,115.01},{ 9.76,32.67},{ 6.69,20.71},
{14.30,44.18},{98.57,173.85},{ 4.01,24.74},{34.46,60.56},
{19.21,46.64},{89.60,166.71},{27.93,53.40},{22.10,65.12},
{20.30,42.75},{95.02,166.30},{76.91,138.66},{ 0.28,32.32},
{62.29,108.93},{18.53,44.52},{58.50,118.40},{79.87,133.47},
{ 1.06,31.67},{43.28,75.77},{34.13,84.84},{71.34,142.31},
{94.14,172.56},{18.77,37.09},{ 3.58,15.15},{34.71,49.88},
{15.87,25.31},{40.55,70.94},{63.57,116.94},{33.01,78.49},
{12.21,36.69},{83.80,139.29},{15.41,38.32},{23.53,70.10},
{19.25,53.57},{32.17,40.06},{80.00,133.35},{15.29,51.71},
{43.63,81.51},{70.07,126.99},{44.69,85.99},{89.03,158.09},
{36.23,60.18},{ 2.37, 1.33},{28.27,71.44},{37.81,80.29},
{74.61,114.15},{32.45,63.47},{76.90,145.43},{45.78,89.56},
{43.76,90.34},{72.40,121.11},{80.03,158.07},{89.76,159.97},
{ 0.79,30.07},{74.50,132.38},{46.19,76.00},{98.40,166.43},
{83.71,152.87},{69.45,138.18},{20.09,57.62},{10.82,44.42},
{94.90,161.52},{56.24,105.19},{25.80,45.99},{78.59,144.32},
{41.90,95.14},{88.38,158.28},{72.22,136.40},{98.04,151.63},
{ 3.44,35.78},{18.58,59.71},{58.74,112.02},{43.90,84.81},
{59.96,131.25},{55.08,113.52},{11.76,36.25},{75.05,134.27},
{18.62,45.25},{49.76,101.82},{80.57,154.63},{93.50,167.65},
{70.39,126.65},{53.57,107.27},{36.88,59.79},{10.52,25.86},
{64.89,100.31},{35.21,90.41},{ 6.23,33.90},{93.30,143.70},
{63.45,129.25},{10.07,36.79},{28.01,58.59},{59.22,100.12},
{46.14,75.11},{51.65,78.56},{42.40,66.31},{99.08,164.34},
{ 8.14,35.13},{61.88,118.50},{39.24,88.28},{37.84,82.29},
{77.53,154.65},{ 3.52,12.20},{94.10,150.41},{52.95,90.29},
{33.45,63.79},{59.77,97.17},{37.34,66.25},{62.51,101.43},
{58.38,123.37},{85.57,146.57},{59.50,110.36},{64.77,113.77},
{52.31,86.72},{74.08,119.62},{20.13,55.40},{70.01,137.11},
{73.03,141.72},{72.90,116.95},{ 9.77,18.64},{77.91,120.62},
{35.13,81.81},{94.76,163.60},{84.97,153.65},{50.99,97.73},
{76.95,139.73},{95.14,165.88},{53.85,91.54},{11.67,32.28},
{74.95,128.36},{62.48,122.55},{52.39,104.02},{84.64,137.02},
{60.79,90.69},{10.88,42.09},{89.36,155.24},{42.14,99.07},
{10.47,24.63},{81.53,125.43},{83.23,156.18},{21.79,42.60},
{22.12,42.96},{84.10,145.52},{ 7.28,19.37},{45.70,87.18},
{68.93,116.49},{44.33,92.72},{83.48,164.04},{36.29,59.75},
{56.87,105.36},{10.77,32.58},{37.26,72.49},{81.52,151.25},
{20.22,51.77},{ 0.53,13.54},{70.22,141.70},{86.98,153.36},
{86.88,155.08},{95.61,163.24},{10.92,46.94},{52.02,86.13},
{79.54,145.77},{45.72,80.50},{23.64,54.82},{40.59,76.38},
{10.51,24.25},{88.39,154.46},{96.15,153.89},{52.43,104.17},
{56.14,93.00},{14.86,52.67},{17.22,45.09},{65.58,106.79},
{37.27,49.60},{21.86,54.55},{30.77,65.57},{18.91,46.54},
{99.20,188.44},{64.15,127.79},{53.69,114.35},{80.75,129.07},
{20.46,42.99},{43.95,89.80},{11.86,34.56},{76.24,137.26},
{60.32,123.89},{13.10,47.27},{ 3.21,27.37},{56.46,123.20},
{28.08,60.38},{62.73,112.94},{56.62,118.19},{ 7.11,21.06},
{35.00,74.47},{99.39,182.65},{31.10,63.43},{18.34,55.60},
{63.21,119.43},{96.73,152.88},{85.87,131.41},{85.13,150.34},
{58.50,106.92},{ 9.39,25.13},{32.07,64.76},{70.15,104.89},
{85.64,126.01},{ 5.71,31.30},{10.14,34.51},{55.14,97.21},
{40.93,71.15},{91.84,166.86},{11.77,33.90},{58.69,95.90},
{32.25,88.75},{79.19,149.50},{38.70,81.86},{23.71,55.47},
{58.19,95.57},{60.07,101.54},{20.08,56.31},{ 5.15,21.22},
{63.36,118.68},{58.66,97.64},{99.72,167.67},{55.95,108.87},
{83.51,155.14},{20.52,56.46},{62.20,126.56},{62.36,108.09},
{25.79,51.49},{10.73,31.13},{40.02,89.61},{ 0.96,19.08}
};
double residual_error(double r, double a, double m, double c) {
double e = (m * r) + c - a;
return e * e;
}
__device__ double d_residual_error(double r, double a, double m, double c) {
double e = (m * r) + c - a;
return e * e;
}
double rms_error(double m, double c) {
int i;
double mean;
double error_sum = 0;
for(i=0; i<n_data; i++) {
error_sum += residual_error(data[i].x, data[i].y, m, c);
}
mean = error_sum / n_data;
return sqrt(mean);
}
__global__ void d_rms_error(double *m, double *c,double *error_sum_arr,point_t *d_data) {
int i = threadIdx.x + blockIdx.x *blockDim.x;
error_sum_arr[i] = d_residual_error(d_data[i].x,d_data[i].y, *m, *c);
}
int time_difference(struct timespec *start, struct timespec *finish, long long int *difference)
{
long long int ds = finish->tv_sec - start->tv_sec;
long long int dn = finish->tv_nsec - start->tv_nsec;
if(dn < 0){
ds--;
dn += 1000000000;
}
*difference = ds * 1000000000 + dn;
return !(*difference > 0);
}
int main(){
int i;
double bm = 1.3;
double bc = 10;
double be;
double dm[8];
double dc[8];
double e[8];
double step = 0.01;
double best_error = 999999999;
int best_error_i;
int minimum_found = 0;
double om[] = {0,1,1, 1, 0,-1,-1,-1};
double oc[] = {1,1,0,-1,-1,-1, 0, 1};
struct timespec start, finish;
long long int time_elapsed;
clock_gettime(CLOCK_MONOTONIC, &start);
cudaError_t error;
double *d_dm;
double *d_dc;
double *d_error_sum_arr;
point_t *d_data;
be= rms_error(bm,bc);
error=cudaMalloc(&d_dm,(sizeof(double) * 8));
if(error){
fprintf(stderr,"cudaMalloc on d_dm returned %d %s\n",error,
cudaGetErrorString(error));
exit(1);
}
error=cudaMalloc(&d_dc,(sizeof(double) * 8));
if(error){
fprintf(stderr,"cudaMalloc on d_dc returned %d %s\n",error,
cudaGetErrorString(error));
exit(1);
}
error=cudaMalloc(&d_error_sum_arr,(sizeof(double) * 1000));
if(error){
fprintf(stderr,"cudaMalloc on d_error_sum_arr returned %d %s\n",error, //371
cudaGetErrorString(error));
exit(1);
}
error=cudaMalloc(&d_data,sizeof(data)); //376
if(error){
fprintf(stderr,"cudaMalloc on d_data returned %d %s\n",error,
cudaGetErrorString(error));
exit(1);
}
while(!minimum_found) {
for(i=0;i<8;i++) {
dm[i] = bm + (om[i] * step);
dc[i]= bc + (oc[i] * step);
}
error = cudaMemcpy(d_dm,dm,(sizeof(double)*8), cudaMemcpyHostToDevice);
if(error){
fprintf(stderr,"cudaMemcpy to d_dm returned %d %s\n",error,
cudaGetErrorString(error));
}
error = cudaMemcpy(d_dc,dc,(sizeof(double)*8), cudaMemcpyHostToDevice);
if(error){
fprintf(stderr,"cudaMemcpy to d_dc returned %d %s\n",error,
cudaGetErrorString(error));
}
error = cudaMemcpy(d_data, data,sizeof(data), cudaMemcpyHostToDevice); //401
if(error){
fprintf(stderr,"cudaMemcpy to d_data returned %d %s\n",error,
cudaGetErrorString(error));
}
for(i=0;i<8;i++){
double h_error_sum_arr[1000];
double error_sum_total;
double error_sum_mean;
d_rms_error <<<100,10>>>(&d_dm[i],&d_dc[i],d_error_sum_arr,d_data);
cudaDeviceSynchronize();
error =cudaMemcpy(&h_error_sum_arr,d_error_sum_arr,(sizeof(double) *1000),
cudaMemcpyDeviceToHost);
if(error){
fprintf(stderr,"cudaMemcpy to error_sum returned %d %s\n",error,
cudaGetErrorString(error));
}
for(int j=0;j<n_data;j++){
error_sum_total+= h_error_sum_arr[j];
}
error_sum_mean = error_sum_total / n_data;
e[i] =sqrt(error_sum_mean);
if(e[i] < best_error){
best_error = e[i];
error_sum_total +=h_error_sum_arr[i];
}
error_sum_mean = error_sum_total /n_data;//431
e[i] = sqrt(error_sum_mean); //432
if(e[i]<best_error){ //434
best_error = e[i];
best_error_i = i;
}
error_sum_total = 0; //438
}
if(best_error <be){
be=best_error;
bm =dm[best_error_i];
bc= dc[best_error_i];
}else {
minimum_found = 1;
}
}
error = cudaFree(d_dm);
if(error){
fprintf(stderr,"cudaFree on d_dm returned %d %s\n",error,
cudaGetErrorString(error)); //453
exit(1);
}
error = cudaFree(d_dc);
if(error){
fprintf(stderr,"cudaFree on d_dc returned %d %s\n",error,
cudaGetErrorString(error));
exit(1);
}
error = cudaFree(d_data);
if(error){
fprintf(stderr,"cudaFree on d_data returned %d %s\n",error,
cudaGetErrorString(error));
exit(1);
}
error = cudaFree(d_error_sum_arr);
if(error){
fprintf(stderr,"cudaFree on d_error_sum_arr returned %d %s\n",error,
cudaGetErrorString(error));
exit(1);
}
printf("minimum m,c is %lf,%lf with error %lf\n", bm, bc, be);
clock_gettime(CLOCK_MONOTONIC, &finish);
time_difference(&start, &finish, &time_elapsed);
printf("Time elapsed was %lldns or %0.9lfs\n", time_elapsed,
(time_elapsed/1.0e9));
return 0;
}
; | code for sm_80
Function : _Z11d_rms_errorPdS_S_P7point_t
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff057435 */
/* 0x000fe200000001ff */
/*0030*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff087624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R9, c[0x0][0x164] ; /* 0x0000590000097a02 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0060*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff0a7624 */
/* 0x000fe200078e00ff */
/*0070*/ MOV R11, c[0x0][0x16c] ; /* 0x00005b00000b7a02 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0090*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1b00 */
/*00a0*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea2000c1e1b00 */
/*00b0*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fc800078e0200 */
/*00c0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fca00078e0205 */
/*00d0*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea8000c1e1b00 */
/*00e0*/ LDG.E.64 R6, [R2.64+0x8] ; /* 0x0000080402067981 */
/* 0x000ee2000c1e1b00 */
/*00f0*/ DFMA R4, R4, R8, R10 ; /* 0x000000080404722b */
/* 0x004ecc000000000a */
/*0100*/ DADD R4, -R6, R4 ; /* 0x0000000006047229 */
/* 0x0080640000000104 */
/*0110*/ MOV R7, 0x8 ; /* 0x0000000800077802 */
/* 0x001fc80000000f00 */
/*0120*/ DMUL R4, R4, R4 ; /* 0x0000000404047228 */
/* 0x002e220000000000 */
/*0130*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fcc00078e0207 */
/*0140*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x001fe2000c101b04 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <time.h>
#include <unistd.h>
#include <hip/hip_runtime_api.h>
#include <errno.h>
#include <unistd.h>
/******************************************************************************
* This program takes an initial estimate of m and c and finds the associated
* rms error. It is then as a base to generate and evaluate 8 new estimates,
* which are steps in different directions in m-c space. The best estimate is
* then used as the base for another iteration of "generate and evaluate". This
* continues until none of the new estimates are better than the base. This is
* a gradient search for a minimum in mc-space.
*
* To compile:
* nvcc -o linearcuda_bishal linear_bishal_cuda.cu -lm
*
* To run:
* ./linearcuda_bishal
*
* Dr Kevan Buckley, University of Wolverhampton, 2018
*****************************************************************************/
typedef struct point_t{
double x;
double y;
}point_t;
int n_data = 1000;
__device__ int d_n_data =1000;
point_t data[] = {
{67.50,117.63},{65.33,126.07},{82.95,145.73},{76.19,113.32},
{87.53,145.91},{73.30,132.50},{76.57,134.90},{68.72,115.55},
{73.32,140.31},{78.84,143.44},{71.68,120.91},{92.42,138.04},
{76.05,128.45},{34.36,75.04},{91.02,154.71},{98.33,178.86},
{75.34,134.84},{84.94,143.54},{34.55,73.14},{22.78,36.84},
{11.34,37.95},{77.02,121.28},{20.48,54.11},{85.81,158.12},
{98.14,169.75},{61.93,126.98},{44.68,77.35},{38.15,83.43},
{30.16,67.27},{76.68,133.30},{86.62,141.45},{60.09,116.95},
{26.91,70.86},{ 9.10,37.19},{11.23,36.15},{26.50,59.09},
{41.44,93.35},{67.47,131.65},{89.46,161.35},{19.81,38.73},
{51.34,93.22},{97.28,174.58},{33.38,68.25},{19.98,40.87},
{44.04,85.03},{70.68,125.28},{84.78,128.46},{63.73,98.19},
{16.48,31.39},{91.67,169.18},{13.59,31.83},{69.96,133.01},
{15.59,53.61},{53.87,116.25},{57.95,119.53},{88.77,156.53},
{ 4.54,19.19},{60.18,111.69},{76.51,143.61},{21.62,54.08},
{53.82,107.72},{28.55,79.61},{51.32,89.52},{60.46,135.12},
{68.14,124.70},{13.20,32.38},{94.61,160.20},{57.63,99.17},
{80.81,143.84},{92.81,143.31},{91.60,164.46},{13.32,40.64},
{93.33,174.11},{50.18,102.21},{ 0.11,28.39},{69.56,119.09},
{55.02,110.04},{74.47,146.21},{91.14,163.71},{65.21,125.47},
{58.83,100.80},{10.02,46.51},{94.36,158.71},{51.22,103.94},
{ 9.25,34.11},{12.64,44.32},{50.24,104.77},{15.73,37.63},
{53.03,101.19},{30.42,72.53},{47.90,90.79},{25.89,68.64},
{75.24,126.35},{80.87,133.87},{ 5.86,31.16},{62.88,112.89},
{81.94,145.67},{51.81,88.24},{82.74,122.52},{80.97,139.14},
{ 0.28, 1.97},{62.20,111.18},{55.95,100.36},{29.17,61.74},
{71.13,120.95},{11.42,42.50},{38.60,70.96},{47.24,88.20},
{ 4.25,26.16},{13.53,50.16},{23.30,64.38},{96.18,162.57},
{97.45,167.05},{86.09,139.37},{19.61,40.67},{75.10,137.54},
{61.73,124.08},{ 7.59,27.78},{ 5.53,13.80},{59.76,116.05},
{19.08,55.39},{41.68,74.96},{16.33,42.42},{96.25,161.59},
{69.83,121.89},{ 5.65,37.87},{42.46,86.94},{79.37,151.11},
{48.34,97.43},{57.96,111.54},{22.31,63.95},{ 6.03,14.45},
{38.59,72.82},{91.91,166.06},{77.34,149.68},{20.95,49.40},
{18.24,44.16},{46.33,85.77},{87.69,162.06},{ 5.63,33.09},
{25.64,62.39},{78.37,129.15},{90.63,162.90},{59.07,108.46},
{ 3.73, 9.62},{73.31,127.30},{85.44,148.06},{62.86,111.04},
{27.61,66.72},{97.81,162.18},{76.86,141.77},{65.90,142.09},
{89.34,144.60},{ 9.42,48.00},{51.54,104.84},{11.47,42.53},
{42.31,79.72},{62.70,111.95},{15.81,44.71},{51.03,101.97},
{50.54,98.74},{84.62,138.28},{95.25,169.94},{ 3.97,31.21},
{10.63, 9.82},{ 1.47,32.91},{67.16,129.22},{10.14,26.05},
{52.42,103.57},{41.93,90.91},{96.18,166.50},{ 0.25,16.19},
{20.73,49.87},{34.86,70.58},{39.49,83.99},{93.26,153.09},
{89.43,147.70},{46.72,90.16},{30.27,50.94},{ 7.73,40.77},
{47.24,89.70},{60.71,110.70},{10.25,35.87},{87.93,176.16},
{81.83,132.92},{47.52,95.67},{ 8.22,30.97},{ 0.16,19.43},
{ 7.67,39.19},{25.22,46.59},{37.39,94.24},{23.87,54.68},
{53.00,94.78},{55.12,113.11},{ 0.39,17.41},{12.25,42.86},
{24.12,67.60},{40.49,92.29},{52.77,87.06},{12.23,46.57},
{67.85,125.89},{42.67,89.64},{34.42,61.02},{ 1.94,18.44},
{53.40,111.16},{89.61,164.56},{ 3.82, 3.73},{96.24,158.21},
{77.04,135.04},{97.05,148.24},{26.71,51.44},{95.02,163.28},
{34.29,61.81},{ 1.62,21.43},{67.74,107.75},{98.19,159.80},
{17.62,54.87},{85.72,146.11},{23.67,53.85},{49.02,101.01},
{93.66,161.56},{44.72,86.99},{72.81,113.39},{60.91,112.51},
{24.17,61.50},{49.89,89.80},{ 8.97,45.83},{26.67,59.28},
{62.50,111.35},{11.07,25.58},{37.01,63.82},{18.94,46.54},
{61.63,108.22},{28.93,50.01},{55.36,99.90},{92.64,173.42},
{28.57,52.10},{ 9.61,30.76},{19.82,52.09},{47.92,90.78},
{28.85,70.65},{33.80,38.50},{29.53,66.71},{42.50,89.01},
{34.95,92.60},{83.24,150.06},{94.97,158.22},{63.79,123.66},
{94.60,157.04},{79.72,136.29},{63.38,116.51},{16.22,41.53},
{40.06,65.75},{54.36,89.16},{65.52,130.07},{19.95,52.07},
{78.01,121.11},{32.30,71.77},{84.85,139.15},{50.25,98.61},
{72.77,124.69},{59.41,100.91},{89.09,168.89},{76.82,142.52},
{26.18,56.42},{10.95,52.42},{62.40,111.33},{62.71,102.03},
{ 2.35,13.42},{ 7.19,41.90},{62.53,123.58},{15.54,52.27},
{ 0.80,20.28},{ 5.30,26.03},{13.01,57.51},{19.16,35.04},
{59.74,133.37},{33.93,83.73},{ 4.54,17.74},{18.61,48.23},
{72.71,133.09},{51.18,90.42},{51.26,104.57},{58.02,83.55},
{68.78,148.00},{29.56,70.05},{10.44,22.10},{90.96,154.32},
{13.82,28.56},{88.00,150.89},{51.69,92.07},{54.30,90.90},
{57.44,101.77},{80.12,149.10},{10.78,39.64},{11.95,64.56},
{97.71,178.99},{37.08,69.88},{ 0.47,17.14},{65.62,109.62},
{99.78,179.04},{81.77,158.12},{11.90,33.54},{85.24,151.30},
{49.38,78.83},{63.79,114.06},{32.79,57.50},{31.96,88.52},
{84.21,144.62},{49.77,102.25},{49.55,88.18},{ 8.26,38.38},
{47.36,90.74},{97.88,170.49},{44.11,78.79},{38.23,88.99},
{40.69,69.98},{ 7.36,36.33},{56.85,111.52},{13.64,36.87},
{53.35,116.88},{72.47,124.76},{46.64,107.91},{94.73,151.85},
{66.61,117.51},{12.35,61.26},{79.14,159.92},{79.02,140.10},
{45.42,94.75},{16.54,29.85},{91.82,153.33},{28.86,55.11},
{50.75,79.96},{10.11,36.95},{32.04,68.39},{71.95,131.62},
{57.09,109.51},{10.91,27.38},{62.49,115.05},{20.30,46.80},
{93.11,159.57},{71.85,130.18},{53.28,108.81},{55.38,111.22},
{85.54,151.96},{22.64,52.50},{56.67,98.37},{ 0.97,21.47},
{72.50,138.03},{26.98,45.21},{96.25,167.19},{16.31,40.83},
{58.79,87.57},{47.38,89.11},{90.04,157.08},{32.23,62.24},
{11.57,34.79},{23.99,51.20},{64.23,105.49},{72.15,107.38},
{37.45,77.37},{73.55,128.18},{36.90,78.88},{45.26,95.74},
{37.99,74.96},{63.67,123.99},{68.51,129.23},{13.85,35.04},
{59.04,93.67},{54.42,102.56},{89.89,148.97},{76.40,139.33},
{15.26,37.71},{61.79,114.18},{31.03,61.43},{96.81,157.36},
{41.43,93.08},{59.88,107.00},{75.72,122.81},{47.51,113.65},
{39.71,81.28},{73.15,145.81},{13.27,27.44},{73.94,130.58},
{48.11,95.15},{91.97,147.09},{29.24,56.59},{88.10,143.34},
{83.07,136.67},{ 1.60,25.57},{83.37,132.98},{32.81,81.72},
{32.76,61.42},{26.69,62.44},{34.24,70.93},{75.68,125.27},
{96.68,165.04},{95.66,168.80},{79.86,144.53},{74.34,121.30},
{57.43,94.75},{56.67,79.08},{54.07,88.83},{99.94,171.14},
{66.96,110.58},{77.27,141.31},{68.77,120.16},{27.42,77.06},
{ 3.47,33.83},{22.31,49.66},{56.78,101.75},{96.06,157.01},
{ 1.29,25.47},{ 2.97,42.15},{66.51,105.60},{37.81,72.23},
{ 3.07,33.29},{37.37,92.70},{ 7.52,32.65},{43.43,75.38},
{63.53,120.10},{55.30,106.01},{65.04,118.04},{ 5.91,21.90},
{65.28,121.06},{29.55,51.16},{41.39,88.10},{35.63,81.24},
{86.27,136.99},{15.92,72.35},{75.93,120.09},{91.92,160.74},
{97.55,169.39},{70.19,117.49},{16.28,38.79},{44.36,81.43},
{87.91,149.02},{ 3.52,38.16},{59.12,120.72},{ 1.90, 0.73},
{83.31,156.42},{44.25,74.81},{36.88,57.45},{80.37,157.35},
{66.99,138.80},{79.54,145.55},{18.33,45.70},{64.15,122.52},
{34.89,69.76},{46.89,93.34},{14.47,48.95},{ 4.47,11.21},
{42.32,86.99},{31.84,63.03},{33.34,81.26},{ 4.88,25.36},
{79.82,133.64},{40.63,100.56},{63.46,121.03},{96.80,151.04},
{92.72,156.50},{90.13,156.67},{87.25,150.80},{63.02,122.96},
{17.30,47.83},{24.10,53.74},{55.24,105.56},{49.54,106.29},
{50.18,92.64},{28.50,73.07},{75.82,141.86},{43.76,88.26},
{33.55,61.23},{66.59,98.81},{25.78,64.50},{ 5.19,31.93},
{32.05,72.33},{61.50,119.08},{39.73,91.92},{80.39,146.69},
{73.53,149.32},{40.57,62.81},{91.25,166.56},{63.33,112.85},
{ 1.32,13.80},{87.01,143.92},{84.90,132.20},{36.73,88.35},
{81.82,127.95},{77.33,143.68},{ 4.44,17.14},{71.90,134.73},
{59.09,106.07},{83.32,145.03},{56.43,87.15},{55.72,118.37},
{35.02,93.87},{76.13,111.18},{43.98,75.47},{92.99,165.88},
{31.66,59.37},{28.52,59.74},{82.09,144.05},{26.09,49.24},
{70.97,117.20},{ 7.68,37.90},{70.42,123.06},{40.47,82.04},
{73.52,133.29},{21.29,62.15},{74.56,121.04},{76.26,137.21},
{10.29,56.09},{28.54,78.38},{21.19,63.67},{40.37,88.01},
{ 9.97,60.42},{59.83,106.32},{36.88,81.58},{64.00,122.44},
{44.79,60.82},{25.61,52.42},{32.59,72.08},{65.16,118.02},
{13.14,39.55},{75.40,123.94},{45.15,97.24},{53.90,113.09},
{75.55,129.32},{ 0.43,21.46},{52.76,92.05},{90.01,148.61},
{26.95,57.55},{30.46,68.83},{39.15,81.42},{58.32,98.73},
{70.37,115.08},{ 5.94,21.53},{ 3.43,33.83},{32.38,68.35},
{59.53,111.46},{37.94,108.20},{24.71,63.30},{96.93,166.78},
{87.47,146.91},{33.94,100.63},{76.73,141.16},{31.78,71.95},
{85.03,155.23},{ 2.52,39.44},{44.84,95.65},{77.68,131.95},
{41.72,86.46},{18.32,57.93},{69.89,120.19},{54.70,86.01},
{54.99,104.64},{48.59,95.15},{24.36,53.97},{51.98,96.80},
{60.23,100.55},{59.09,85.63},{33.81,67.74},{12.22,41.13},
{26.38,65.33},{ 7.09,30.43},{24.85,50.55},{99.52,170.23},
{84.73,129.42},{39.71,92.69},{57.91,105.37},{33.52,75.23},
{33.93,65.91},{27.34,52.79},{58.75,104.12},{60.52,110.72},
{ 2.81,12.48},{ 8.02,27.71},{64.73,120.96},{82.03,159.82},
{22.60,38.52},{24.08,61.92},{66.05,102.86},{19.42,49.76},
{48.04,97.54},{46.20,96.45},{ 1.17,17.39},{63.69,129.79},
{29.84,75.40},{26.53,45.12},{95.19,149.02},{90.77,157.73},
{41.81,86.87},{74.43,110.80},{49.39,97.73},{22.62,49.26},
{ 4.87,18.08},{19.41,58.94},{42.62,107.88},{77.24,159.90},
{80.67,133.41},{44.37,89.30},{51.39,91.86},{25.27,57.14},
{10.84,16.20},{99.73,182.30},{85.08,167.49},{16.49,38.24},
{48.48,98.37},{30.56,50.30},{45.38,97.80},{33.13,73.18},
{39.58,86.47},{56.27,115.05},{18.85,48.41},{51.63,99.71},
{ 7.00,29.08},{32.17,71.87},{44.00,94.70},{ 3.73,38.62},
{72.17,111.87},{29.35,54.28},{50.13,94.46},{91.52,170.01},
{40.05,72.34},{46.87,67.83},{76.24,138.98},{26.75,63.90},
{63.87,105.49},{13.12,23.17},{12.58,53.66},{ 8.20,43.82},
{14.36,32.76},{32.84,51.21},{11.45,24.07},{93.59,140.71},
{58.09,85.90},{52.69,102.77},{38.38,85.50},{98.36,158.74},
{74.87,125.72},{32.47,73.67},{55.48,122.80},{42.12,87.03},
{75.24,144.54},{71.66,134.49},{34.01,66.08},{58.69,105.94},
{35.47,72.45},{51.46,100.28},{87.79,150.58},{10.86,27.33},
{68.38,133.79},{38.57,86.54},{64.01,109.90},{17.09,63.00},
{ 9.34,35.52},{66.20,127.61},{22.82,52.08},{79.23,148.39},
{19.50,45.48},{ 4.76,14.25},{ 0.11,24.33},{55.86,91.16},
{43.58,90.07},{14.59,50.39},{39.88,99.03},{41.04,85.30},
{87.44,169.74},{55.54,98.60},{ 2.07, 1.75},{29.04,64.38},
{41.45,92.95},{73.41,124.41},{78.49,152.32},{33.64,87.75},
{67.48,139.43},{87.13,144.84},{59.65,100.97},{45.11,87.31},
{76.40,139.82},{62.21,124.75},{78.60,163.67},{20.57,49.21},
{80.06,138.88},{60.51,108.48},{ 2.05,29.92},{11.23,23.36},
{10.61,39.17},{30.63,63.71},{ 5.13,41.33},{74.37,123.26},
{14.03,38.39},{ 6.31,36.58},{ 9.16,36.90},{75.16,138.63},
{88.12,149.50},{ 1.78,31.54},{28.88,64.20},{79.20,136.08},
{27.98,48.89},{89.12,158.04},{ 9.51,11.76},{10.45,40.24},
{22.73,61.87},{73.97,124.05},{ 7.09,10.69},{11.73,32.78},
{90.67,166.68},{88.17,167.73},{97.82,164.53},{63.81,103.31},
{74.11,137.22},{71.03,119.75},{43.78,85.30},{84.66,148.37},
{12.33,30.33},{83.29,138.56},{21.34,71.07},{40.14,68.00},
{73.05,119.85},{ 7.44,29.55},{89.02,151.86},{17.24,61.99},
{41.66,73.47},{50.62,99.48},{60.53,111.85},{12.70,17.62},
{66.84,110.12},{52.27,89.56},{98.72,178.46},{79.92,113.48},
{23.55,43.25},{38.26,96.94},{56.52,118.31},{53.04,96.75},
{35.73,72.29},{60.43,109.43},{77.67,137.73},{45.78,98.97},
{32.36,67.11},{23.89,68.74},{24.53,45.00},{97.28,162.74},
{27.73,50.67},{90.85,165.35},{93.94,153.83},{ 6.63,43.74},
{93.38,150.59},{43.87,77.99},{49.91,86.07},{82.99,151.00},
{ 7.00,40.39},{46.17,89.39},{28.87,66.05},{72.85,141.73},
{27.21,58.82},{42.02,79.42},{95.29,149.89},{ 7.03,21.47},
{80.55,133.93},{75.29,147.77},{32.44,69.31},{29.14,61.10},
{94.21,157.98},{48.51,115.01},{ 9.76,32.67},{ 6.69,20.71},
{14.30,44.18},{98.57,173.85},{ 4.01,24.74},{34.46,60.56},
{19.21,46.64},{89.60,166.71},{27.93,53.40},{22.10,65.12},
{20.30,42.75},{95.02,166.30},{76.91,138.66},{ 0.28,32.32},
{62.29,108.93},{18.53,44.52},{58.50,118.40},{79.87,133.47},
{ 1.06,31.67},{43.28,75.77},{34.13,84.84},{71.34,142.31},
{94.14,172.56},{18.77,37.09},{ 3.58,15.15},{34.71,49.88},
{15.87,25.31},{40.55,70.94},{63.57,116.94},{33.01,78.49},
{12.21,36.69},{83.80,139.29},{15.41,38.32},{23.53,70.10},
{19.25,53.57},{32.17,40.06},{80.00,133.35},{15.29,51.71},
{43.63,81.51},{70.07,126.99},{44.69,85.99},{89.03,158.09},
{36.23,60.18},{ 2.37, 1.33},{28.27,71.44},{37.81,80.29},
{74.61,114.15},{32.45,63.47},{76.90,145.43},{45.78,89.56},
{43.76,90.34},{72.40,121.11},{80.03,158.07},{89.76,159.97},
{ 0.79,30.07},{74.50,132.38},{46.19,76.00},{98.40,166.43},
{83.71,152.87},{69.45,138.18},{20.09,57.62},{10.82,44.42},
{94.90,161.52},{56.24,105.19},{25.80,45.99},{78.59,144.32},
{41.90,95.14},{88.38,158.28},{72.22,136.40},{98.04,151.63},
{ 3.44,35.78},{18.58,59.71},{58.74,112.02},{43.90,84.81},
{59.96,131.25},{55.08,113.52},{11.76,36.25},{75.05,134.27},
{18.62,45.25},{49.76,101.82},{80.57,154.63},{93.50,167.65},
{70.39,126.65},{53.57,107.27},{36.88,59.79},{10.52,25.86},
{64.89,100.31},{35.21,90.41},{ 6.23,33.90},{93.30,143.70},
{63.45,129.25},{10.07,36.79},{28.01,58.59},{59.22,100.12},
{46.14,75.11},{51.65,78.56},{42.40,66.31},{99.08,164.34},
{ 8.14,35.13},{61.88,118.50},{39.24,88.28},{37.84,82.29},
{77.53,154.65},{ 3.52,12.20},{94.10,150.41},{52.95,90.29},
{33.45,63.79},{59.77,97.17},{37.34,66.25},{62.51,101.43},
{58.38,123.37},{85.57,146.57},{59.50,110.36},{64.77,113.77},
{52.31,86.72},{74.08,119.62},{20.13,55.40},{70.01,137.11},
{73.03,141.72},{72.90,116.95},{ 9.77,18.64},{77.91,120.62},
{35.13,81.81},{94.76,163.60},{84.97,153.65},{50.99,97.73},
{76.95,139.73},{95.14,165.88},{53.85,91.54},{11.67,32.28},
{74.95,128.36},{62.48,122.55},{52.39,104.02},{84.64,137.02},
{60.79,90.69},{10.88,42.09},{89.36,155.24},{42.14,99.07},
{10.47,24.63},{81.53,125.43},{83.23,156.18},{21.79,42.60},
{22.12,42.96},{84.10,145.52},{ 7.28,19.37},{45.70,87.18},
{68.93,116.49},{44.33,92.72},{83.48,164.04},{36.29,59.75},
{56.87,105.36},{10.77,32.58},{37.26,72.49},{81.52,151.25},
{20.22,51.77},{ 0.53,13.54},{70.22,141.70},{86.98,153.36},
{86.88,155.08},{95.61,163.24},{10.92,46.94},{52.02,86.13},
{79.54,145.77},{45.72,80.50},{23.64,54.82},{40.59,76.38},
{10.51,24.25},{88.39,154.46},{96.15,153.89},{52.43,104.17},
{56.14,93.00},{14.86,52.67},{17.22,45.09},{65.58,106.79},
{37.27,49.60},{21.86,54.55},{30.77,65.57},{18.91,46.54},
{99.20,188.44},{64.15,127.79},{53.69,114.35},{80.75,129.07},
{20.46,42.99},{43.95,89.80},{11.86,34.56},{76.24,137.26},
{60.32,123.89},{13.10,47.27},{ 3.21,27.37},{56.46,123.20},
{28.08,60.38},{62.73,112.94},{56.62,118.19},{ 7.11,21.06},
{35.00,74.47},{99.39,182.65},{31.10,63.43},{18.34,55.60},
{63.21,119.43},{96.73,152.88},{85.87,131.41},{85.13,150.34},
{58.50,106.92},{ 9.39,25.13},{32.07,64.76},{70.15,104.89},
{85.64,126.01},{ 5.71,31.30},{10.14,34.51},{55.14,97.21},
{40.93,71.15},{91.84,166.86},{11.77,33.90},{58.69,95.90},
{32.25,88.75},{79.19,149.50},{38.70,81.86},{23.71,55.47},
{58.19,95.57},{60.07,101.54},{20.08,56.31},{ 5.15,21.22},
{63.36,118.68},{58.66,97.64},{99.72,167.67},{55.95,108.87},
{83.51,155.14},{20.52,56.46},{62.20,126.56},{62.36,108.09},
{25.79,51.49},{10.73,31.13},{40.02,89.61},{ 0.96,19.08}
};
double residual_error(double r, double a, double m, double c) {
double e = (m * r) + c - a;
return e * e;
}
__device__ double d_residual_error(double r, double a, double m, double c) {
double e = (m * r) + c - a;
return e * e;
}
double rms_error(double m, double c) {
int i;
double mean;
double error_sum = 0;
for(i=0; i<n_data; i++) {
error_sum += residual_error(data[i].x, data[i].y, m, c);
}
mean = error_sum / n_data;
return sqrt(mean);
}
__global__ void d_rms_error(double *m, double *c,double *error_sum_arr,point_t *d_data) {
int i = threadIdx.x + blockIdx.x *blockDim.x;
error_sum_arr[i] = d_residual_error(d_data[i].x,d_data[i].y, *m, *c);
}
int time_difference(struct timespec *start, struct timespec *finish, long long int *difference)
{
long long int ds = finish->tv_sec - start->tv_sec;
long long int dn = finish->tv_nsec - start->tv_nsec;
if(dn < 0){
ds--;
dn += 1000000000;
}
*difference = ds * 1000000000 + dn;
return !(*difference > 0);
}
int main(){
int i;
double bm = 1.3;
double bc = 10;
double be;
double dm[8];
double dc[8];
double e[8];
double step = 0.01;
double best_error = 999999999;
int best_error_i;
int minimum_found = 0;
double om[] = {0,1,1, 1, 0,-1,-1,-1};
double oc[] = {1,1,0,-1,-1,-1, 0, 1};
struct timespec start, finish;
long long int time_elapsed;
clock_gettime(CLOCK_MONOTONIC, &start);
hipError_t error;
double *d_dm;
double *d_dc;
double *d_error_sum_arr;
point_t *d_data;
be= rms_error(bm,bc);
error=hipMalloc(&d_dm,(sizeof(double) * 8));
if(error){
fprintf(stderr,"hipMalloc on d_dm returned %d %s\n",error,
hipGetErrorString(error));
exit(1);
}
error=hipMalloc(&d_dc,(sizeof(double) * 8));
if(error){
fprintf(stderr,"hipMalloc on d_dc returned %d %s\n",error,
hipGetErrorString(error));
exit(1);
}
error=hipMalloc(&d_error_sum_arr,(sizeof(double) * 1000));
if(error){
fprintf(stderr,"hipMalloc on d_error_sum_arr returned %d %s\n",error, //371
hipGetErrorString(error));
exit(1);
}
error=hipMalloc(&d_data,sizeof(data)); //376
if(error){
fprintf(stderr,"hipMalloc on d_data returned %d %s\n",error,
hipGetErrorString(error));
exit(1);
}
while(!minimum_found) {
for(i=0;i<8;i++) {
dm[i] = bm + (om[i] * step);
dc[i]= bc + (oc[i] * step);
}
error = hipMemcpy(d_dm,dm,(sizeof(double)*8), hipMemcpyHostToDevice);
if(error){
fprintf(stderr,"hipMemcpy to d_dm returned %d %s\n",error,
hipGetErrorString(error));
}
error = hipMemcpy(d_dc,dc,(sizeof(double)*8), hipMemcpyHostToDevice);
if(error){
fprintf(stderr,"hipMemcpy to d_dc returned %d %s\n",error,
hipGetErrorString(error));
}
error = hipMemcpy(d_data, data,sizeof(data), hipMemcpyHostToDevice); //401
if(error){
fprintf(stderr,"hipMemcpy to d_data returned %d %s\n",error,
hipGetErrorString(error));
}
for(i=0;i<8;i++){
double h_error_sum_arr[1000];
double error_sum_total;
double error_sum_mean;
d_rms_error <<<100,10>>>(&d_dm[i],&d_dc[i],d_error_sum_arr,d_data);
hipDeviceSynchronize();
error =hipMemcpy(&h_error_sum_arr,d_error_sum_arr,(sizeof(double) *1000),
hipMemcpyDeviceToHost);
if(error){
fprintf(stderr,"hipMemcpy to error_sum returned %d %s\n",error,
hipGetErrorString(error));
}
for(int j=0;j<n_data;j++){
error_sum_total+= h_error_sum_arr[j];
}
error_sum_mean = error_sum_total / n_data;
e[i] =sqrt(error_sum_mean);
if(e[i] < best_error){
best_error = e[i];
error_sum_total +=h_error_sum_arr[i];
}
error_sum_mean = error_sum_total /n_data;//431
e[i] = sqrt(error_sum_mean); //432
if(e[i]<best_error){ //434
best_error = e[i];
best_error_i = i;
}
error_sum_total = 0; //438
}
if(best_error <be){
be=best_error;
bm =dm[best_error_i];
bc= dc[best_error_i];
}else {
minimum_found = 1;
}
}
error = hipFree(d_dm);
if(error){
fprintf(stderr,"hipFree on d_dm returned %d %s\n",error,
hipGetErrorString(error)); //453
exit(1);
}
error = hipFree(d_dc);
if(error){
fprintf(stderr,"hipFree on d_dc returned %d %s\n",error,
hipGetErrorString(error));
exit(1);
}
error = hipFree(d_data);
if(error){
fprintf(stderr,"hipFree on d_data returned %d %s\n",error,
hipGetErrorString(error));
exit(1);
}
error = hipFree(d_error_sum_arr);
if(error){
fprintf(stderr,"hipFree on d_error_sum_arr returned %d %s\n",error,
hipGetErrorString(error));
exit(1);
}
printf("minimum m,c is %lf,%lf with error %lf\n", bm, bc, be);
clock_gettime(CLOCK_MONOTONIC, &finish);
time_difference(&start, &finish, &time_elapsed);
printf("Time elapsed was %lldns or %0.9lfs\n", time_elapsed,
(time_elapsed/1.0e9));
return 0;
}
; | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11d_rms_errorPdS_S_P7point_t
.globl _Z11d_rms_errorPdS_S_P7point_t
.p2align 8
.type _Z11d_rms_errorPdS_S_P7point_t,@function
_Z11d_rms_errorPdS_S_P7point_t:
s_clause 0x1
s_load_b32 s8, s[0:1], 0x2c
s_load_b256 s[0:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s8, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, s15, s8, v[0:1]
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 4, v[4:5]
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b128 v[0:3], v[0:1], off
s_load_b64 s[0:1], s[0:1], 0x0
s_load_b64 s[2:3], s[2:3], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fma_f64 v[0:1], v[0:1], s[0:1], s[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[0:1], v[0:1], -v[2:3]
v_lshlrev_b64 v[2:3], 3, v[4:5]
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
v_mul_f64 v[0:1], v[0:1], v[0:1]
global_store_b64 v[2:3], v[0:1], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11d_rms_errorPdS_S_P7point_t
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11d_rms_errorPdS_S_P7point_t, .Lfunc_end0-_Z11d_rms_errorPdS_S_P7point_t
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected d_n_data
.type d_n_data,@object
.data
.globl d_n_data
.p2align 2, 0x0
d_n_data:
.long 1000
.size d_n_data, 4
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11d_rms_errorPdS_S_P7point_t
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11d_rms_errorPdS_S_P7point_t.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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