system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
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You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <algorithm>
#include <cfloat>
#include <chrono>
#include <fstream>
#include <iostream>
#include <random>
#include <sstream>
#include <stdexcept>
#include <vector>
#include <chrono>
#include <time.h>
double gpu_time_used;
#define I(row, col, ncols) (row * ncols + col)
#define CUDA_CALL(x) {if((x) != hipSuccess){ \
printf("CUDA error at %s:%d\n",__FILE__,__LINE__); \
printf(" %s\n", hipGetErrorString(hipGetLastError())); \
exit(EXIT_FAILURE);}}
__global__ void get_dst(float *dst, float *x, float *y,
float *mu_x, float *mu_y){
int i = blockIdx.x;
int j = threadIdx.x;
dst[I(i, j, blockDim.x)] = (x[i] - mu_x[j]) * (x[i] - mu_x[j]);
dst[I(i, j, blockDim.x)] += (y[i] - mu_y[j]) * (y[i] - mu_y[j]);
}
__global__ void regroup(int *group, float *dst, int k){
int i = blockIdx.x;
int j;
float min_dst;
min_dst = dst[I(i, 0, k)];
group[i] = 1;
for(j = 1; j < k; ++j){
if(dst[I(i, j, k)] < min_dst){
min_dst = dst[I(i, j, k)];
group[i] = j + 1;
}
}
}
__global__ void clear(float *sum_x, float *sum_y, int *nx, int *ny){
int j = threadIdx.x;
sum_x[j] = 0;
sum_y[j] = 0;
nx[j] = 0;
ny[j] = 0;
}
__global__ void recenter_step1(float *sum_x, float *sum_y, int *nx, int *ny,
float *x, float *y, int *group, int n){
int i;
int j = threadIdx.x;
for(i = 0; i < n; ++i){
if(group[i] == (j + 1)){
sum_x[j] += x[i];
sum_y[j] += y[i];
nx[j]++;
ny[j]++;
}
}
}
__global__ void recenter_step2(float *mu_x, float *mu_y, float *sum_x,
float *sum_y, int *nx, int *ny){
int j = threadIdx.x;
mu_x[j] = sum_x[j]/nx[j];
mu_y[j] = sum_y[j]/ny[j];
}
void kmeans(int nreps, int n, int k,
float *x_d, float *y_d, float *mu_x_d, float *mu_y_d,
int *group_d, int *nx_d, int *ny_d,
float *sum_x_d, float *sum_y_d, float *dst_d){
int i;
for(i = 0; i < nreps; ++i){
get_dst<<<n,k>>>(dst_d, x_d, y_d, mu_x_d, mu_y_d);
regroup<<<n,1>>>(group_d, dst_d, k);
clear<<<1,k>>>(sum_x_d, sum_y_d, nx_d, ny_d);
recenter_step1<<<1,k>>>(sum_x_d, sum_y_d, nx_d, ny_d, x_d, y_d, group_d, n);
recenter_step2<<<1,k>>>(mu_x_d, mu_y_d, sum_x_d, sum_y_d, nx_d, ny_d);
}
}
void read_data(float **x, float **y, float **mu_x, float **mu_y, int *n, int *k,char* arg);
void print_results(int *group, float *mu_x, float *mu_y, int n, int k,char* argv);
int main(int argc,char* argv[]){
/* cpu variables */
int n; /* number of points */
int k; /* number of clusters */
// int *group;
float *x = NULL, *y = NULL, *mu_x = NULL, *mu_y = NULL;
/* gpu variables */
int *group_d, *nx_d, *ny_d;
float *x_d, *y_d, *mu_x_d, *mu_y_d, *sum_x_d, *sum_y_d, *dst_d;
/* read data from files on cpu */
read_data(&x, &y, &mu_x, &mu_y, &n, &k,argv[2]);
/* allocate cpu memory */
// group = (int*) malloc(n*sizeof(int));
/* allocate gpu memory */
hipMallocManaged(&group_d,n*sizeof(int));
hipMallocManaged(&nx_d, k*sizeof(int));
hipMallocManaged(&ny_d, k*sizeof(int));
hipMallocManaged(&x_d, n*sizeof(float));
hipMallocManaged(&y_d, n*sizeof(float));
hipMallocManaged(&mu_x_d, k*sizeof(float));
hipMallocManaged(&mu_y_d, k*sizeof(float));
hipMallocManaged(&sum_x_d, k*sizeof(float));
hipMallocManaged(&sum_y_d, k*sizeof(float));
hipMallocManaged(&dst_d, n*k*sizeof(float));
memcpy(x_d, x, n*sizeof(float));
memcpy(y_d, x, n*sizeof(float));
memcpy(mu_x_d, mu_x, k*sizeof(float));
memcpy(mu_y_d, mu_y, k*sizeof(float));
/* write data to gpu */
// CUDA_CALL(cudaMemcpy(x_d, x, n*sizeof(float), cudaMemcpyHostToDevice));
// CUDA_CALL(cudaMemcpy(y_d, y, n*sizeof(float), cudaMemcpyHostToDevice));
// CUDA_CALL(cudaMemcpy(mu_x_d, mu_x, k*sizeof(float), cudaMemcpyHostToDevice));
// CUDA_CALL(cudaMemcpy(mu_y_d, mu_y, k*sizeof(float), cudaMemcpyHostToDevice));
/* perform kmeans */
const auto start = std::chrono::high_resolution_clock::now();
kmeans(100, n, k, x_d, y_d, mu_x_d, mu_y_d, group_d, nx_d, ny_d, sum_x_d, sum_y_d, dst_d);
const auto end = std::chrono::high_resolution_clock::now();
const auto duration =
std::chrono::duration_cast<std::chrono::duration<float>>(end - start);
std::cerr << "CUDA Took: " << duration.count() << "s" << " for "<<argv[3]<<" points." << std::endl;
gpu_time_used = duration.count();
/* read back data from gpu */
// CUDA_CALL(cudaMemcpy(group, group_d, n*sizeof(int), cudaMemcpyDeviceToHost));
// CUDA_CALL(cudaMemcpy(mu_x, mu_x_d, k*sizeof(float), cudaMemcpyDeviceToHost));
// CUDA_CALL(cudaMemcpy(mu_y, mu_y_d, k*sizeof(float), cudaMemcpyDeviceToHost));
/* print results and clean up */
print_results(group_d, mu_x_d, mu_y_d, n, k,argv[3]);
free(x);
free(y);
free(mu_x);
free(mu_y);
// free(group);
CUDA_CALL(hipFree(x_d));
CUDA_CALL(hipFree(y_d));
CUDA_CALL(hipFree(mu_x_d));
CUDA_CALL(hipFree(mu_y_d));
CUDA_CALL(hipFree(group_d));
CUDA_CALL(hipFree(nx_d));
CUDA_CALL(hipFree(ny_d));
CUDA_CALL(hipFree(sum_x_d));
CUDA_CALL(hipFree(sum_y_d));
CUDA_CALL(hipFree(dst_d));
return 0;
}
void read_data(float **x, float **y, float **mu_x, float **mu_y, int *n, int *k,char* arg){
FILE *fp;
char buf[64];
*n = 0;
fp = fopen(arg, "r");
while(fgets(buf, 64, fp) != NULL){
*n += 1;
*x = (float*) realloc(*x, (*n)*sizeof(float));
*y = (float*) realloc(*y, (*n)*sizeof(float));
std::istringstream line_stream(buf);
float x1,y1;
line_stream >> x1 >> y1;
(*x)[*n - 1] = x1;
(*y)[*n - 1] = y1;
}
fclose(fp);
*k = 0;
fp = fopen("../../data/kmeans/initCoord.txt", "r");
while(fgets(buf, 64, fp) != NULL){
*k += 1;
*mu_x = (float*) realloc(*mu_x, (*k)*sizeof(float));
*mu_y = (float*) realloc(*mu_y, (*k)*sizeof(float));
std::istringstream line_stream(buf);
float x1,y1;
line_stream >> x1 >> y1;
(*mu_x)[*k - 1] = x1;
(*mu_y)[*k - 1] = x1;
}
fclose(fp);
}
void print_results(int *group, float *mu_x, float *mu_y, int n, int k,char* arg){
FILE *fp;
int i;
std::string str(arg),str1,str2;
str = "result/cuda/" + str;
str1 = str + "_group_members.txt";
fp = fopen(str1.c_str(), "w");
for(i = 0; i < n; ++i){
fprintf(fp, "%d\n", group[i]);
}
fclose(fp);
str2 = str + "_centroids.txt";
fp = fopen(str2.c_str(), "w");
for(i = 0; i < k; ++i){
fprintf(fp, "%0.6f %0.6f\n", mu_x[i], mu_y[i]);
}
fclose(fp);
fp = fopen("CUDAtimes.txt", "a");
fprintf(fp, "%0.6f\n", gpu_time_used);
fclose(fp);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7get_dstPfS_S_S_S_
.globl _Z7get_dstPfS_S_S_S_
.p2align 8
.type _Z7get_dstPfS_S_S_S_,@function
_Z7get_dstPfS_S_S_S_:
s_load_b256 s[4:11], s[0:1], 0x0
v_lshlrev_b32_e32 v3, 2, v0
s_load_b32 s12, s[0:1], 0x34
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_load_b64 s[0:1], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
global_load_b32 v4, v3, s[10:11]
s_lshl_b64 s[10:11], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_add_u32 s6, s6, s10
s_addc_u32 s7, s7, s11
s_load_b32 s3, s[6:7], 0x0
s_and_b32 s6, s12, 0xffff
v_mad_u64_u32 v[1:2], null, s2, s6, v[0:1]
v_mov_b32_e32 v2, 0
s_add_u32 s2, s8, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0) lgkmcnt(0)
v_sub_f32_e32 v4, s3, v4
s_addc_u32 s3, s9, s11
v_mul_f32_e32 v4, v4, v4
global_store_b32 v[0:1], v4, off
global_load_b32 v2, v2, s[2:3]
global_load_b32 v3, v3, s[0:1]
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v4, v2, v2
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7get_dstPfS_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7get_dstPfS_S_S_S_, .Lfunc_end0-_Z7get_dstPfS_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7regroupPiPfi
.globl _Z7regroupPiPfi
.p2align 8
.type _Z7regroupPiPfi,@function
_Z7regroupPiPfi:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x10
s_mov_b32 s4, s15
s_ashr_i32 s5, s15, 31
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 1
s_lshl_b64 s[8:9], s[4:5], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s8
s_addc_u32 s3, s3, s9
s_cmp_lt_i32 s6, 2
global_store_b32 v0, v1, s[2:3]
s_cbranch_scc1 .LBB1_5
s_load_b64 s[0:1], s[0:1], 0x8
s_mul_i32 s8, s4, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s9, s8, 31
s_lshl_b64 s[4:5], s[8:9], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s0, s4
s_addc_u32 s5, s1, s5
s_add_i32 s8, s8, 1
s_load_b32 s4, s[4:5], 0x0
s_ashr_i32 s9, s8, 31
s_mov_b32 s5, 1
s_lshl_b64 s[8:9], s[8:9], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s0, s8
s_addc_u32 s1, s1, s9
s_branch .LBB1_3
.p2align 6
.LBB1_2:
s_add_i32 s5, s5, 1
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s6, s5
s_cbranch_scc0 .LBB1_5
.LBB1_3:
s_load_b32 s7, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_cmp_nlt_f32_e64 s8, s7, s4
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s8
s_cbranch_vccnz .LBB1_2
s_add_i32 s4, s5, 1
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v1, s4
s_mov_b32 s4, s7
global_store_b32 v0, v1, s[2:3]
s_branch .LBB1_2
.LBB1_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7regroupPiPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7regroupPiPfi, .Lfunc_end1-_Z7regroupPiPfi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z5clearPfS_PiS0_
.globl _Z5clearPfS_PiS0_
.p2align 8
.type _Z5clearPfS_PiS0_,@function
_Z5clearPfS_PiS0_:
s_load_b256 s[0:7], s[0:1], 0x0
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x3
global_store_b32 v0, v1, s[0:1]
global_store_b32 v0, v1, s[4:5]
global_store_b32 v0, v1, s[2:3]
global_store_b32 v0, v1, s[6:7]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5clearPfS_PiS0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z5clearPfS_PiS0_, .Lfunc_end2-_Z5clearPfS_PiS0_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z14recenter_step1PfS_PiS0_S_S_S0_i
.globl _Z14recenter_step1PfS_PiS0_S_S_S0_i
.p2align 8
.type _Z14recenter_step1PfS_PiS0_S_S_S0_i,@function
_Z14recenter_step1PfS_PiS0_S_S_S0_i:
s_load_b32 s2, s[0:1], 0x38
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB3_5
s_clause 0x2
s_load_b256 s[8:15], s[0:1], 0x0
s_load_b128 s[4:7], s[0:1], 0x20
s_load_b64 s[0:1], s[0:1], 0x30
v_dual_mov_b32 v9, 0 :: v_dual_lshlrev_b32 v6, 2, v0
v_add_nc_u32_e32 v8, 1, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s3, s8, v6
v_add_co_ci_u32_e64 v1, null, s9, 0, s3
v_add_co_u32 v2, s3, s10, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, null, s11, 0, s3
v_add_co_u32 v4, s3, s12, v6
v_add_co_ci_u32_e64 v5, null, s13, 0, s3
v_add_co_u32 v6, s3, s14, v6
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v7, null, s15, 0, s3
s_set_inst_prefetch_distance 0x1
s_branch .LBB3_3
.p2align 6
.LBB3_2:
s_or_b32 exec_lo, exec_lo, s3
s_add_i32 s2, s2, -1
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_cmp_lg_u32 s2, 0
s_cbranch_scc0 .LBB3_5
.LBB3_3:
global_load_b32 v10, v9, s[0:1]
s_mov_b32 s3, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e64 v10, v8
s_cbranch_execz .LBB3_2
global_load_b32 v10, v9, s[4:5]
global_load_b32 v11, v[0:1], off
global_load_b32 v12, v[4:5], off
s_waitcnt vmcnt(0)
v_dual_add_f32 v10, v10, v11 :: v_dual_add_nc_u32 v11, 1, v12
global_store_b32 v[0:1], v10, off
global_store_b32 v[4:5], v11, off
global_load_b32 v10, v9, s[6:7]
global_load_b32 v11, v[2:3], off
global_load_b32 v12, v[6:7], off
s_waitcnt vmcnt(0)
v_dual_add_f32 v10, v10, v11 :: v_dual_add_nc_u32 v11, 1, v12
global_store_b32 v[2:3], v10, off
global_store_b32 v[6:7], v11, off
s_branch .LBB3_2
.LBB3_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14recenter_step1PfS_PiS0_S_S_S0_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 60
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z14recenter_step1PfS_PiS0_S_S_S0_i, .Lfunc_end3-_Z14recenter_step1PfS_PiS0_S_S_S0_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z14recenter_step2PfS_S_S_PiS0_
.globl _Z14recenter_step2PfS_S_S_PiS0_
.p2align 8
.type _Z14recenter_step2PfS_S_S_PiS0_,@function
_Z14recenter_step2PfS_S_S_PiS0_:
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x20
s_load_b256 s[0:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x2
global_load_b32 v1, v0, s[8:9]
global_load_b32 v2, v0, s[4:5]
global_load_b32 v3, v0, s[10:11]
s_waitcnt vmcnt(2)
v_cvt_f32_i32_e32 v1, v1
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v4, null, v1, v1, v2
v_div_scale_f32 v7, vcc_lo, v2, v1, v2
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_mul_f32_e32 v6, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v4, v6, v7
v_fmac_f32_e32 v6, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v6, v7
v_div_fmas_f32 v4, v4, v5, v6
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v1, v4, v1, v2
s_waitcnt vmcnt(0)
v_cvt_f32_i32_e32 v2, v3
global_store_b32 v0, v1, s[0:1]
global_load_b32 v1, v0, s[6:7]
s_waitcnt vmcnt(0)
v_div_scale_f32 v3, null, v2, v2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
v_fmac_f32_e32 v4, v5, v4
v_div_scale_f32 v5, vcc_lo, v1, v2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v5, v4
v_fma_f32 v7, -v3, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v7, v4
v_fma_f32 v3, -v3, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v3, v3, v4, v6
v_div_fixup_f32 v1, v3, v2, v1
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14recenter_step2PfS_S_S_PiS0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 12
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end4:
.size _Z14recenter_step2PfS_S_S_PiS0_, .Lfunc_end4-_Z14recenter_step2PfS_S_S_PiS0_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7get_dstPfS_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7get_dstPfS_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7regroupPiPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7regroupPiPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5clearPfS_PiS0_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z5clearPfS_PiS0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 60
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14recenter_step1PfS_PiS0_S_S_S0_i
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z14recenter_step1PfS_PiS0_S_S_S0_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14recenter_step2PfS_S_S_PiS0_
.private_segment_fixed_size: 0
.sgpr_count: 14
.sgpr_spill_count: 0
.symbol: _Z14recenter_step2PfS_S_S_PiS0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <assert.h>
#include <stdlib.h>
#include <cuda.h>
__global__ void render(char *out, int width, int height) {
int index = 3 * (blockIdx.x * blockDim.x + threadIdx.x);
int x_dim = (index / 3) % width, y_dim = (index / 3) / width;
float x_origin = ((float) x_dim/width)*3.25 - 2;
float y_origin = ((float) y_dim/width)*2.5 - 1.25;
float x = 0.0;
float y = 0.0;
int iteration = 0;
int scale = 8;
int max_iteration = 256 * scale;
while(x*x + y*y <= 4 && iteration < max_iteration) {
float xtemp = x*x - y*y + x_origin;
y = 2*x*y + y_origin;
x = xtemp;
iteration++;
}
if(iteration == max_iteration) {
out[index] = 0;
out[index + 1] = 0;
out[index + 2] = 0;
} else {
out[index] = iteration / scale;
out[index + 1] = iteration / scale;
out[index + 2] = iteration / scale;
}
}
void runCUDA(int width, int height)
{
// Multiply by 3 here, since we need red, green and blue for each pixel
size_t buffer_size = sizeof(char) * width * height * 3;
char *image;
cudaMalloc((void **) &image, buffer_size);
char *host_image = (char *) malloc(buffer_size);
dim3 blockDim(64, 1, 1);
dim3 gridDim(width * height / blockDim.x, 1, 1);
render<<< gridDim, blockDim, 0 >>>(image, width, height);
cudaMemcpy(host_image, image, buffer_size, cudaMemcpyDeviceToHost);
// Now write the file
/*printf("P3\n%d %d\n255\n", width, height);
for (int row = 0; row < height; row++) {
for (int col = 0; col < width; col++) {
for (int i = 0; i < 3; i++) {
unsigned char c = host_image[(row * width + col) * 3 + i];
printf("%d ", c);
}
}
printf("\n");
}*/
cudaFree(image);
free(host_image);
}
int main(int argc, const char * argv[]) {
int N = 1024;
runCUDA(N, N);
return 0;
} | code for sm_80
Function : _Z6renderPcii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R7, c[0x0][0x168] ; /* 0x00005a0000077a13 */
/* 0x000fe20000000000 */
/*0020*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0030*/ BSSY B0, 0x300 ; /* 0x000002c000007945 */
/* 0x000fe40003800000 */
/*0040*/ I2F.RP R4, R7 ; /* 0x0000000700047306 */
/* 0x000e620000209400 */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e2e0000002100 */
/*0060*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x002e620000001000 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0205 */
/*0080*/ IMAD R0, R0, 0x3, RZ ; /* 0x0000000300007824 */
/* 0x000fe200078e02ff */
/*0090*/ IADD3 R3, R4, 0xffffffe, RZ ; /* 0x0ffffffe04037810 */
/* 0x002fc60007ffe0ff */
/*00a0*/ IMAD.HI R2, R0, 0x55555556, RZ ; /* 0x5555555600027827 */
/* 0x000fc600078e02ff */
/*00b0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e24000021f000 */
/*00c0*/ LEA.HI R5, R2, R2, RZ, 0x1 ; /* 0x0000000202057211 */
/* 0x000fe200078f08ff */
/*00d0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fc600078e00ff */
/*00e0*/ IABS R4, R5 ; /* 0x0000000500047213 */
/* 0x000fe20000000000 */
/*00f0*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x001fc800078e0a03 */
/*0100*/ IMAD R9, R6, R7, RZ ; /* 0x0000000706097224 */
/* 0x000fc800078e02ff */
/*0110*/ IMAD.HI.U32 R2, R3, R9, R2 ; /* 0x0000000903027227 */
/* 0x000fc800078e0002 */
/*0120*/ IMAD.MOV.U32 R3, RZ, RZ, R4 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0004 */
/*0130*/ IMAD.HI.U32 R4, R2, R3, RZ ; /* 0x0000000302047227 */
/* 0x000fc800078e00ff */
/*0140*/ IMAD.MOV R2, RZ, RZ, -R4 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0a04 */
/*0150*/ IMAD R2, R7, R2, R3 ; /* 0x0000000207027224 */
/* 0x000fca00078e0203 */
/*0160*/ ISETP.GT.U32.AND P2, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x000fda0003f44070 */
/*0170*/ @!P2 IMAD.IADD R2, R2, 0x1, -R7 ; /* 0x000000010202a824 */
/* 0x000fe200078e0a07 */
/*0180*/ @!P2 IADD3 R4, R4, 0x1, RZ ; /* 0x000000010404a810 */
/* 0x000fe40007ffe0ff */
/*0190*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe40003f45270 */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R2, R7, PT ; /* 0x000000070200720c */
/* 0x000fe40003f06070 */
/*01b0*/ LOP3.LUT R2, R5, c[0x0][0x168], RZ, 0x3c, !PT ; /* 0x00005a0005027a12 */
/* 0x000fc800078e3cff */
/*01c0*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f26270 */
/*01d0*/ I2F R2, c[0x0][0x168] ; /* 0x00005a0000027b06 */
/* 0x000e2a0000201400 */
/*01e0*/ @P0 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104040810 */
/* 0x000fcc0007ffe0ff */
/*01f0*/ @!P1 IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff049224 */
/* 0x000fe200078e0a04 */
/*0200*/ @!P2 LOP3.LUT R4, RZ, c[0x0][0x168], RZ, 0x33, !PT ; /* 0x00005a00ff04aa12 */
/* 0x000fe200078e33ff */
/*0210*/ MUFU.RCP R3, R2 ; /* 0x0000000200037308 */
/* 0x001e280000001000 */
/*0220*/ IMAD.MOV R6, RZ, RZ, -R4 ; /* 0x000000ffff067224 */
/* 0x000fc800078e0a04 */
/*0230*/ IMAD R5, R6, c[0x0][0x168], R5 ; /* 0x00005a0006057a24 */
/* 0x000fc800078e0205 */
/*0240*/ I2F R9, R5 ; /* 0x0000000500097306 */
/* 0x000e620000201400 */
/*0250*/ FFMA R6, -R2, R3, 1 ; /* 0x3f80000002067423 */
/* 0x001fc80000000103 */
/*0260*/ FFMA R6, R3, R6, R3 ; /* 0x0000000603067223 */
/* 0x000fc60000000003 */
/*0270*/ FCHK P0, R9, R2 ; /* 0x0000000209007302 */
/* 0x002e220000000000 */
/*0280*/ FFMA R3, R9, R6, RZ ; /* 0x0000000609037223 */
/* 0x000fc800000000ff */
/*0290*/ FFMA R7, -R2, R3, R9 ; /* 0x0000000302077223 */
/* 0x000fc80000000109 */
/*02a0*/ FFMA R10, R6, R7, R3 ; /* 0x00000007060a7223 */
/* 0x000fe20000000003 */
/*02b0*/ @!P0 BRA 0x2f0 ; /* 0x0000003000008947 */
/* 0x001fea0003800000 */
/*02c0*/ MOV R6, 0x2e0 ; /* 0x000002e000067802 */
/* 0x000fe40000000f00 */
/*02d0*/ CALL.REL.NOINC 0x670 ; /* 0x0000039000007944 */
/* 0x000fea0003c00000 */
/*02e0*/ IMAD.MOV.U32 R10, RZ, RZ, R5 ; /* 0x000000ffff0a7224 */
/* 0x001fe400078e0005 */
/*02f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0300*/ I2F R11, R4 ; /* 0x00000004000b7306 */
/* 0x000e220000201400 */
/*0310*/ IMAD.MOV.U32 R8, RZ, RZ, 0x0 ; /* 0x00000000ff087424 */
/* 0x000fe200078e00ff */
/*0320*/ BSSY B0, 0x440 ; /* 0x0000011000007945 */
/* 0x000fe20003800000 */
/*0330*/ IMAD.MOV.U32 R9, RZ, RZ, 0x400a0000 ; /* 0x400a0000ff097424 */
/* 0x000fca00078e00ff */
/*0340*/ F2F.F64.F32 R6, R10 ; /* 0x0000000a00067310 */
/* 0x000e700000201800 */
/*0350*/ MUFU.RCP R3, R2 ; /* 0x0000000200037308 */
/* 0x000eb00000001000 */
/*0360*/ FCHK P0, R11, R2 ; /* 0x000000020b007302 */
/* 0x001e220000000000 */
/*0370*/ DFMA R6, R6, R8, -2 ; /* 0xc00000000606742b */
/* 0x002e620000000008 */
/*0380*/ FFMA R12, -R2, R3, 1 ; /* 0x3f800000020c7423 */
/* 0x004fc80000000103 */
/*0390*/ FFMA R12, R3, R12, R3 ; /* 0x0000000c030c7223 */
/* 0x000fe40000000003 */
/*03a0*/ F2F.F32.F64 R3, R6 ; /* 0x0000000600037310 */
/* 0x0022a40000301000 */
/*03b0*/ FFMA R5, R12, R11, RZ ; /* 0x0000000b0c057223 */
/* 0x000fc800000000ff */
/*03c0*/ FFMA R8, -R2, R5, R11 ; /* 0x0000000502087223 */
/* 0x000fc8000000010b */
/*03d0*/ FFMA R8, R12, R8, R5 ; /* 0x000000080c087223 */
/* 0x000fe20000000005 */
/*03e0*/ @!P0 BRA 0x430 ; /* 0x0000004000008947 */
/* 0x001fea0003800000 */
/*03f0*/ IMAD.MOV.U32 R9, RZ, RZ, R11 ; /* 0x000000ffff097224 */
/* 0x002fe200078e000b */
/*0400*/ MOV R6, 0x420 ; /* 0x0000042000067802 */
/* 0x000fe40000000f00 */
/*0410*/ CALL.REL.NOINC 0x670 ; /* 0x0000025000007944 */
/* 0x004fea0003c00000 */
/*0420*/ IMAD.MOV.U32 R8, RZ, RZ, R5 ; /* 0x000000ffff087224 */
/* 0x001fe400078e0005 */
/*0430*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*0440*/ F2F.F64.F32 R4, R8 ; /* 0x0000000800047310 */
/* 0x000e220000201800 */
/*0450*/ IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; /* 0x00000000ff067424 */
/* 0x000fe200078e00ff */
/*0460*/ BSSY B0, 0x5a0 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*0470*/ IMAD.MOV.U32 R7, RZ, RZ, 0x40040000 ; /* 0x40040000ff077424 */
/* 0x000fe400078e00ff */
/*0480*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe400078e00ff */
/*0490*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe400078e00ff */
/*04a0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e00ff */
/*04b0*/ DFMA R4, R4, R6, -1.25 ; /* 0xbff400000404742b */
/* 0x0010440000000006 */
/*04c0*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x001fd0000001ff00 */
/*04d0*/ F2F.F32.F64 R5, R4 ; /* 0x0000000400057310 */
/* 0x0020640000301000 */
/*04e0*/ FADD R2, R7, -R2 ; /* 0x8000000207027221 */
/* 0x000fe20000000000 */
/*04f0*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fe20007ffe0ff */
/*0500*/ FADD R4, R10, R10 ; /* 0x0000000a0a047221 */
/* 0x001fe40000000000 */
/*0510*/ FADD R10, R3, R2 ; /* 0x00000002030a7221 */
/* 0x004fe20000000000 */
/*0520*/ ISETP.GE.U32.AND P0, PT, R6, 0x800, PT ; /* 0x000008000600780c */
/* 0x000fe20003f06070 */
/*0530*/ FFMA R9, R4, R9, R5 ; /* 0x0000000904097223 */
/* 0x002fe40000000005 */
/*0540*/ FMUL R7, R10, R10 ; /* 0x0000000a0a077220 */
/* 0x000fe40000400000 */
/*0550*/ FMUL R2, R9, R9 ; /* 0x0000000909027220 */
/* 0x000fc80000400000 */
/*0560*/ FADD R4, R7, R2 ; /* 0x0000000207047221 */
/* 0x000fca0000000000 */
/*0570*/ FSETP.LE.AND P1, PT, R4, 4, PT ; /* 0x408000000400780b */
/* 0x000fda0003f23000 */
/*0580*/ @!P0 BRA P1, 0x4e0 ; /* 0xffffff5000008947 */
/* 0x000fea000083ffff */
/*0590*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05a0*/ ISETP.NE.AND P0, PT, R6, 0x800, PT ; /* 0x000008000600780c */
/* 0x000fe20003f05270 */
/*05b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*05c0*/ IADD3 R2, P1, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fc80007f3e0ff */
/*05d0*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x164], 0x1, P1 ; /* 0x0000590000037a11 */
/* 0x000fce00008f0eff */
/*05e0*/ @P0 SHF.R.U32.HI R5, RZ, 0x3, R6 ; /* 0x00000003ff050819 */
/* 0x000fca0000011606 */
/*05f0*/ @P0 STG.E.U8 [R2.64], R5 ; /* 0x0000000502000986 */
/* 0x0001e8000c101104 */
/*0600*/ @P0 STG.E.U8 [R2.64+0x1], R5 ; /* 0x0000010502000986 */
/* 0x0001e8000c101104 */
/*0610*/ @P0 STG.E.U8 [R2.64+0x2], R5 ; /* 0x0000020502000986 */
/* 0x0001e2000c101104 */
/*0620*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0630*/ STG.E.U8 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe8000c101104 */
/*0640*/ STG.E.U8 [R2.64+0x1], RZ ; /* 0x000001ff02007986 */
/* 0x000fe8000c101104 */
/*0650*/ STG.E.U8 [R2.64+0x2], RZ ; /* 0x000002ff02007986 */
/* 0x000fe2000c101104 */
/*0660*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0670*/ SHF.R.U32.HI R7, RZ, 0x17, R2.reuse ; /* 0x00000017ff077819 */
/* 0x100fe20000011602 */
/*0680*/ BSSY B1, 0xcd0 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0690*/ SHF.R.U32.HI R5, RZ, 0x17, R9 ; /* 0x00000017ff057819 */
/* 0x000fe20000011609 */
/*06a0*/ IMAD.MOV.U32 R8, RZ, RZ, R2 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0002 */
/*06b0*/ LOP3.LUT R13, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff070d7812 */
/* 0x000fc400078ec0ff */
/*06c0*/ LOP3.LUT R11, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff050b7812 */
/* 0x000fe200078ec0ff */
/*06d0*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0009 */
/*06e0*/ IADD3 R12, R13, -0x1, RZ ; /* 0xffffffff0d0c7810 */
/* 0x000fe40007ffe0ff */
/*06f0*/ IADD3 R10, R11, -0x1, RZ ; /* 0xffffffff0b0a7810 */
/* 0x000fe40007ffe0ff */
/*0700*/ ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ; /* 0x000000fd0c00780c */
/* 0x000fc80003f04070 */
/*0710*/ ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ; /* 0x000000fd0a00780c */
/* 0x000fda0000704470 */
/*0720*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff078224 */
/* 0x000fe200078e00ff */
/*0730*/ @!P0 BRA 0x8b0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0740*/ FSETP.GTU.FTZ.AND P0, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fe40003f1c200 */
/*0750*/ FSETP.GTU.FTZ.AND P1, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fc80003f3c200 */
/*0760*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0770*/ @P0 BRA 0xcb0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0780*/ LOP3.LUT P0, RZ, R8, 0x7fffffff, R5, 0xc8, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000780c805 */
/*0790*/ @!P0 BRA 0xc90 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*07a0*/ FSETP.NEU.FTZ.AND P2, PT, |R9|.reuse, +INF , PT ; /* 0x7f8000000900780b */
/* 0x040fe40003f5d200 */
/*07b0*/ FSETP.NEU.FTZ.AND P1, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fe40003f3d200 */
/*07c0*/ FSETP.NEU.FTZ.AND P0, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fd60003f1d200 */
/*07d0*/ @!P1 BRA !P2, 0xc90 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*07e0*/ LOP3.LUT P2, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05ff7812 */
/* 0x000fc8000784c0ff */
/*07f0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0800*/ @P1 BRA 0xc70 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0810*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000782c0ff */
/*0820*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0830*/ @P0 BRA 0xc40 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0840*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f06270 */
/*0850*/ ISETP.GE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fd60003f26270 */
/*0860*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff070224 */
/* 0x000fe400078e00ff */
/*0870*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, -0x40 ; /* 0xffffffc0ff078424 */
/* 0x000fe400078e00ff */
/*0880*/ @!P0 FFMA R5, R9, 1.84467440737095516160e+19, RZ ; /* 0x5f80000009058823 */
/* 0x000fe400000000ff */
/*0890*/ @!P1 FFMA R8, R2, 1.84467440737095516160e+19, RZ ; /* 0x5f80000002089823 */
/* 0x000fe200000000ff */
/*08a0*/ @!P1 IADD3 R7, R7, 0x40, RZ ; /* 0x0000004007079810 */
/* 0x000fe40007ffe0ff */
/*08b0*/ LEA R9, R13, 0xc0800000, 0x17 ; /* 0xc08000000d097811 */
/* 0x000fe200078eb8ff */
/*08c0*/ BSSY B2, 0xc30 ; /* 0x0000036000027945 */
/* 0x000fe80003800000 */
/*08d0*/ IMAD.IADD R9, R8, 0x1, -R9 ; /* 0x0000000108097824 */
/* 0x000fe200078e0a09 */
/*08e0*/ IADD3 R8, R11, -0x7f, RZ ; /* 0xffffff810b087810 */
/* 0x000fc60007ffe0ff */
/*08f0*/ MUFU.RCP R10, R9 ; /* 0x00000009000a7308 */
/* 0x000e220000001000 */
/*0900*/ FADD.FTZ R12, -R9, -RZ ; /* 0x800000ff090c7221 */
/* 0x000fe40000010100 */
/*0910*/ IMAD R5, R8, -0x800000, R5 ; /* 0xff80000008057824 */
/* 0x000fe400078e0205 */
/*0920*/ FFMA R11, R10, R12, 1 ; /* 0x3f8000000a0b7423 */
/* 0x001fc8000000000c */
/*0930*/ FFMA R14, R10, R11, R10 ; /* 0x0000000b0a0e7223 */
/* 0x000fc8000000000a */
/*0940*/ FFMA R10, R5, R14, RZ ; /* 0x0000000e050a7223 */
/* 0x000fc800000000ff */
/*0950*/ FFMA R11, R12, R10, R5 ; /* 0x0000000a0c0b7223 */
/* 0x000fc80000000005 */
/*0960*/ FFMA R11, R14, R11, R10 ; /* 0x0000000b0e0b7223 */
/* 0x000fe2000000000a */
/*0970*/ IADD3 R10, R8, 0x7f, -R13 ; /* 0x0000007f080a7810 */
/* 0x000fc60007ffe80d */
/*0980*/ FFMA R12, R12, R11, R5 ; /* 0x0000000b0c0c7223 */
/* 0x000fe40000000005 */
/*0990*/ IMAD.IADD R10, R10, 0x1, R7 ; /* 0x000000010a0a7824 */
/* 0x000fe400078e0207 */
/*09a0*/ FFMA R5, R14, R12, R11 ; /* 0x0000000c0e057223 */
/* 0x000fca000000000b */
/*09b0*/ SHF.R.U32.HI R8, RZ, 0x17, R5 ; /* 0x00000017ff087819 */
/* 0x000fc80000011605 */
/*09c0*/ LOP3.LUT R8, R8, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff08087812 */
/* 0x000fca00078ec0ff */
/*09d0*/ IMAD.IADD R13, R8, 0x1, R10 ; /* 0x00000001080d7824 */
/* 0x000fca00078e020a */
/*09e0*/ IADD3 R7, R13, -0x1, RZ ; /* 0xffffffff0d077810 */
/* 0x000fc80007ffe0ff */
/*09f0*/ ISETP.GE.U32.AND P0, PT, R7, 0xfe, PT ; /* 0x000000fe0700780c */
/* 0x000fda0003f06070 */
/*0a00*/ @!P0 BRA 0xc10 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0a10*/ ISETP.GT.AND P0, PT, R13, 0xfe, PT ; /* 0x000000fe0d00780c */
/* 0x000fda0003f04270 */
/*0a20*/ @P0 BRA 0xbe0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0a30*/ ISETP.GE.AND P0, PT, R13, 0x1, PT ; /* 0x000000010d00780c */
/* 0x000fda0003f06270 */
/*0a40*/ @P0 BRA 0xc20 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0a50*/ ISETP.GE.AND P0, PT, R13, -0x18, PT ; /* 0xffffffe80d00780c */
/* 0x000fe40003f06270 */
/*0a60*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fd600078ec0ff */
/*0a70*/ @!P0 BRA 0xc20 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0a80*/ FFMA.RZ R7, R14.reuse, R12.reuse, R11.reuse ; /* 0x0000000c0e077223 */
/* 0x1c0fe2000000c00b */
/*0a90*/ IADD3 R10, R13.reuse, 0x20, RZ ; /* 0x000000200d0a7810 */
/* 0x040fe20007ffe0ff */
/*0aa0*/ FFMA.RM R8, R14.reuse, R12.reuse, R11.reuse ; /* 0x0000000c0e087223 */
/* 0x1c0fe2000000400b */
/*0ab0*/ ISETP.NE.AND P2, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe40003f45270 */
/*0ac0*/ LOP3.LUT R9, R7, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff07097812 */
/* 0x000fe200078ec0ff */
/*0ad0*/ FFMA.RP R7, R14, R12, R11 ; /* 0x0000000c0e077223 */
/* 0x000fe2000000800b */
/*0ae0*/ ISETP.NE.AND P1, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe20003f25270 */
/*0af0*/ IMAD.MOV R11, RZ, RZ, -R13 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0a0d */
/*0b00*/ LOP3.LUT R9, R9, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000009097812 */
/* 0x000fe400078efcff */
/*0b10*/ FSETP.NEU.FTZ.AND P0, PT, R7, R8, PT ; /* 0x000000080700720b */
/* 0x000fc40003f1d000 */
/*0b20*/ SHF.L.U32 R10, R9, R10, RZ ; /* 0x0000000a090a7219 */
/* 0x000fe400000006ff */
/*0b30*/ SEL R8, R11, RZ, P2 ; /* 0x000000ff0b087207 */
/* 0x000fe40001000000 */
/*0b40*/ ISETP.NE.AND P1, PT, R10, RZ, P1 ; /* 0x000000ff0a00720c */
/* 0x000fe40000f25270 */
/*0b50*/ SHF.R.U32.HI R8, RZ, R8, R9 ; /* 0x00000008ff087219 */
/* 0x000fe40000011609 */
/*0b60*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0b70*/ SHF.R.U32.HI R10, RZ, 0x1, R8 ; /* 0x00000001ff0a7819 */
/* 0x000fc40000011608 */
/*0b80*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fc80004000000 */
/*0b90*/ LOP3.LUT R7, R7, 0x1, R10, 0xf8, !PT ; /* 0x0000000107077812 */
/* 0x000fc800078ef80a */
/*0ba0*/ LOP3.LUT R7, R7, R8, RZ, 0xc0, !PT ; /* 0x0000000807077212 */
/* 0x000fca00078ec0ff */
/*0bb0*/ IMAD.IADD R10, R10, 0x1, R7 ; /* 0x000000010a0a7824 */
/* 0x000fca00078e0207 */
/*0bc0*/ LOP3.LUT R5, R10, R5, RZ, 0xfc, !PT ; /* 0x000000050a057212 */
/* 0x000fe200078efcff */
/*0bd0*/ BRA 0xc20 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0be0*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fc800078ec0ff */
/*0bf0*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*0c00*/ BRA 0xc20 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0c10*/ IMAD R5, R10, 0x800000, R5 ; /* 0x008000000a057824 */
/* 0x000fe400078e0205 */
/*0c20*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0c30*/ BRA 0xcc0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0c40*/ LOP3.LUT R5, R8, 0x80000000, R5, 0x48, !PT ; /* 0x8000000008057812 */
/* 0x000fc800078e4805 */
/*0c50*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*0c60*/ BRA 0xcc0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0c70*/ LOP3.LUT R5, R8, 0x80000000, R5, 0x48, !PT ; /* 0x8000000008057812 */
/* 0x000fe200078e4805 */
/*0c80*/ BRA 0xcc0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0c90*/ MUFU.RSQ R5, -QNAN ; /* 0xffc0000000057908 */
/* 0x000e220000001400 */
/*0ca0*/ BRA 0xcc0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0cb0*/ FADD.FTZ R5, R9, R2 ; /* 0x0000000209057221 */
/* 0x000fe40000010000 */
/*0cc0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0cd0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fc800078e00ff */
/*0ce0*/ RET.REL.NODEC R6 0x0 ; /* 0xfffff31006007950 */
/* 0x000fea0003c3ffff */
/*0cf0*/ BRA 0xcf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <assert.h>
#include <stdlib.h>
#include <cuda.h>
__global__ void render(char *out, int width, int height) {
int index = 3 * (blockIdx.x * blockDim.x + threadIdx.x);
int x_dim = (index / 3) % width, y_dim = (index / 3) / width;
float x_origin = ((float) x_dim/width)*3.25 - 2;
float y_origin = ((float) y_dim/width)*2.5 - 1.25;
float x = 0.0;
float y = 0.0;
int iteration = 0;
int scale = 8;
int max_iteration = 256 * scale;
while(x*x + y*y <= 4 && iteration < max_iteration) {
float xtemp = x*x - y*y + x_origin;
y = 2*x*y + y_origin;
x = xtemp;
iteration++;
}
if(iteration == max_iteration) {
out[index] = 0;
out[index + 1] = 0;
out[index + 2] = 0;
} else {
out[index] = iteration / scale;
out[index + 1] = iteration / scale;
out[index + 2] = iteration / scale;
}
}
void runCUDA(int width, int height)
{
// Multiply by 3 here, since we need red, green and blue for each pixel
size_t buffer_size = sizeof(char) * width * height * 3;
char *image;
cudaMalloc((void **) &image, buffer_size);
char *host_image = (char *) malloc(buffer_size);
dim3 blockDim(64, 1, 1);
dim3 gridDim(width * height / blockDim.x, 1, 1);
render<<< gridDim, blockDim, 0 >>>(image, width, height);
cudaMemcpy(host_image, image, buffer_size, cudaMemcpyDeviceToHost);
// Now write the file
/*printf("P3\n%d %d\n255\n", width, height);
for (int row = 0; row < height; row++) {
for (int col = 0; col < width; col++) {
for (int i = 0; i < 3; i++) {
unsigned char c = host_image[(row * width + col) * 3 + i];
printf("%d ", c);
}
}
printf("\n");
}*/
cudaFree(image);
free(host_image);
}
int main(int argc, const char * argv[]) {
int N = 1024;
runCUDA(N, N);
return 0;
} | .file "tmpxft_001b2adc_00000000-6_mandelbrot.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z6renderPciiPcii
.type _Z27__device_stub__Z6renderPciiPcii, @function
_Z27__device_stub__Z6renderPciiPcii:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6renderPcii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z27__device_stub__Z6renderPciiPcii, .-_Z27__device_stub__Z6renderPciiPcii
.globl _Z6renderPcii
.type _Z6renderPcii, @function
_Z6renderPcii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6renderPciiPcii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z6renderPcii, .-_Z6renderPcii
.globl _Z7runCUDAii
.type _Z7runCUDAii, @function
_Z7runCUDAii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movl %esi, %ebp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movslq %edi, %rax
movslq %esi, %rdx
imulq %rdx, %rax
leaq (%rax,%rax,2), %r13
leaq 8(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movq %r13, %rdi
call malloc@PLT
movq %rax, %r12
movl $1, 20(%rsp)
movl %ebx, %eax
imull %ebp, %eax
shrl $6, %eax
movl %eax, 28(%rsp)
movl $1, 32(%rsp)
movl $64, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movq %r13, %rdx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl %ebp, %edx
movl %ebx, %esi
movq 8(%rsp), %rdi
call _Z27__device_stub__Z6renderPciiPcii
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z7runCUDAii, .-_Z7runCUDAii
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $1024, %esi
movl $1024, %edi
call _Z7runCUDAii
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6renderPcii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6renderPcii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <assert.h>
#include <stdlib.h>
#include <cuda.h>
__global__ void render(char *out, int width, int height) {
int index = 3 * (blockIdx.x * blockDim.x + threadIdx.x);
int x_dim = (index / 3) % width, y_dim = (index / 3) / width;
float x_origin = ((float) x_dim/width)*3.25 - 2;
float y_origin = ((float) y_dim/width)*2.5 - 1.25;
float x = 0.0;
float y = 0.0;
int iteration = 0;
int scale = 8;
int max_iteration = 256 * scale;
while(x*x + y*y <= 4 && iteration < max_iteration) {
float xtemp = x*x - y*y + x_origin;
y = 2*x*y + y_origin;
x = xtemp;
iteration++;
}
if(iteration == max_iteration) {
out[index] = 0;
out[index + 1] = 0;
out[index + 2] = 0;
} else {
out[index] = iteration / scale;
out[index + 1] = iteration / scale;
out[index + 2] = iteration / scale;
}
}
void runCUDA(int width, int height)
{
// Multiply by 3 here, since we need red, green and blue for each pixel
size_t buffer_size = sizeof(char) * width * height * 3;
char *image;
cudaMalloc((void **) &image, buffer_size);
char *host_image = (char *) malloc(buffer_size);
dim3 blockDim(64, 1, 1);
dim3 gridDim(width * height / blockDim.x, 1, 1);
render<<< gridDim, blockDim, 0 >>>(image, width, height);
cudaMemcpy(host_image, image, buffer_size, cudaMemcpyDeviceToHost);
// Now write the file
/*printf("P3\n%d %d\n255\n", width, height);
for (int row = 0; row < height; row++) {
for (int col = 0; col < width; col++) {
for (int i = 0; i < 3; i++) {
unsigned char c = host_image[(row * width + col) * 3 + i];
printf("%d ", c);
}
}
printf("\n");
}*/
cudaFree(image);
free(host_image);
}
int main(int argc, const char * argv[]) {
int N = 1024;
runCUDA(N, N);
return 0;
} | #include <stdio.h>
#include <assert.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
__global__ void render(char *out, int width, int height) {
int index = 3 * (blockIdx.x * blockDim.x + threadIdx.x);
int x_dim = (index / 3) % width, y_dim = (index / 3) / width;
float x_origin = ((float) x_dim/width)*3.25 - 2;
float y_origin = ((float) y_dim/width)*2.5 - 1.25;
float x = 0.0;
float y = 0.0;
int iteration = 0;
int scale = 8;
int max_iteration = 256 * scale;
while(x*x + y*y <= 4 && iteration < max_iteration) {
float xtemp = x*x - y*y + x_origin;
y = 2*x*y + y_origin;
x = xtemp;
iteration++;
}
if(iteration == max_iteration) {
out[index] = 0;
out[index + 1] = 0;
out[index + 2] = 0;
} else {
out[index] = iteration / scale;
out[index + 1] = iteration / scale;
out[index + 2] = iteration / scale;
}
}
void runCUDA(int width, int height)
{
// Multiply by 3 here, since we need red, green and blue for each pixel
size_t buffer_size = sizeof(char) * width * height * 3;
char *image;
hipMalloc((void **) &image, buffer_size);
char *host_image = (char *) malloc(buffer_size);
dim3 blockDim(64, 1, 1);
dim3 gridDim(width * height / blockDim.x, 1, 1);
render<<< gridDim, blockDim, 0 >>>(image, width, height);
hipMemcpy(host_image, image, buffer_size, hipMemcpyDeviceToHost);
// Now write the file
/*printf("P3\n%d %d\n255\n", width, height);
for (int row = 0; row < height; row++) {
for (int col = 0; col < width; col++) {
for (int i = 0; i < 3; i++) {
unsigned char c = host_image[(row * width + col) * 3 + i];
printf("%d ", c);
}
}
printf("\n");
}*/
hipFree(image);
free(host_image);
}
int main(int argc, const char * argv[]) {
int N = 1024;
runCUDA(N, N);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <assert.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
__global__ void render(char *out, int width, int height) {
int index = 3 * (blockIdx.x * blockDim.x + threadIdx.x);
int x_dim = (index / 3) % width, y_dim = (index / 3) / width;
float x_origin = ((float) x_dim/width)*3.25 - 2;
float y_origin = ((float) y_dim/width)*2.5 - 1.25;
float x = 0.0;
float y = 0.0;
int iteration = 0;
int scale = 8;
int max_iteration = 256 * scale;
while(x*x + y*y <= 4 && iteration < max_iteration) {
float xtemp = x*x - y*y + x_origin;
y = 2*x*y + y_origin;
x = xtemp;
iteration++;
}
if(iteration == max_iteration) {
out[index] = 0;
out[index + 1] = 0;
out[index + 2] = 0;
} else {
out[index] = iteration / scale;
out[index + 1] = iteration / scale;
out[index + 2] = iteration / scale;
}
}
void runCUDA(int width, int height)
{
// Multiply by 3 here, since we need red, green and blue for each pixel
size_t buffer_size = sizeof(char) * width * height * 3;
char *image;
hipMalloc((void **) &image, buffer_size);
char *host_image = (char *) malloc(buffer_size);
dim3 blockDim(64, 1, 1);
dim3 gridDim(width * height / blockDim.x, 1, 1);
render<<< gridDim, blockDim, 0 >>>(image, width, height);
hipMemcpy(host_image, image, buffer_size, hipMemcpyDeviceToHost);
// Now write the file
/*printf("P3\n%d %d\n255\n", width, height);
for (int row = 0; row < height; row++) {
for (int col = 0; col < width; col++) {
for (int i = 0; i < 3; i++) {
unsigned char c = host_image[(row * width + col) * 3 + i];
printf("%d ", c);
}
}
printf("\n");
}*/
hipFree(image);
free(host_image);
}
int main(int argc, const char * argv[]) {
int N = 1024;
runCUDA(N, N);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6renderPcii
.globl _Z6renderPcii
.p2align 8
.type _Z6renderPcii,@function
_Z6renderPcii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x8
s_load_b32 s3, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_ashr_i32 s4, s2, 31
s_and_b32 s3, s3, 0xffff
s_add_i32 s5, s2, s4
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_xor_b32 s3, s5, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cvt_f32_u32_e32 v0, s3
s_sub_i32 s5, 0, s3
v_lshl_add_u32 v2, v1, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
v_mul_hi_i32 v1, v2, 0x55555556
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v3, 31, v1
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v0, 0x4f7ffffe, v0 :: v_dual_add_nc_u32 v1, v1, v3
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v1
v_mul_lo_u32 v3, s5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v5, v1, v4
v_mul_hi_u32 v3, v0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_xor_b32_e32 v5, v5, v4
v_xor_b32_e32 v4, s4, v4
v_add_nc_u32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v5, v0
v_mul_lo_u32 v3, v0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v5, v3
v_add_nc_u32_e32 v5, 1, v0
v_subrev_nc_u32_e32 v6, s3, v3
v_cmp_le_u32_e32 vcc_lo, s3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v0, v0, v5 :: v_dual_cndmask_b32 v3, v3, v6
v_add_nc_u32_e32 v5, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s3, v3
v_cndmask_b32_e32 v0, v0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v4
v_sub_nc_u32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v3, v0, s2
v_cvt_f32_i32_e32 v0, v0
v_sub_nc_u32_e32 v1, v1, v3
v_cvt_f32_i32_e32 v3, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v1, v1
v_div_scale_f32 v5, null, v3, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_scale_f32 v4, null, v3, v3, v1
v_rcp_f32_e32 v7, v5
v_div_scale_f32 v10, vcc_lo, v1, v3, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v6, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v9, -v5, v7, 1.0
v_fma_f32 v8, -v4, v6, 1.0
v_dual_fmac_f32 v7, v9, v7 :: v_dual_fmac_f32 v6, v8, v6
v_div_scale_f32 v8, s2, v0, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v9, v10, v6
v_mul_f32_e32 v11, v8, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v12, -v4, v9, v10
v_fma_f32 v13, -v5, v11, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v9, v12, v6
v_fmac_f32_e32 v11, v13, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v4, -v4, v9, v10
v_fma_f32 v5, -v5, v11, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_fmas_f32 v4, v4, v6, v9
s_mov_b32 vcc_lo, s2
s_mov_b32 s2, 0
v_div_fmas_f32 v5, v5, v7, v11
s_mov_b32 s3, 0x40040000
v_div_fixup_f32 v1, v4, v3, v1
v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v7, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fixup_f32 v3, v5, v3, v0
v_cvt_f64_f32_e32 v[0:1], v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f64_f32_e32 v[3:4], v3
v_fma_f64 v[0:1], v[0:1], 0x400a0000, -2.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fma_f64 v[3:4], v[3:4], s[2:3], 0xbff40000
s_mov_b32 s2, 0
s_mov_b32 s3, 0
v_cvt_f32_f64_e32 v0, v[0:1]
s_delay_alu instid0(VALU_DEP_2)
v_cvt_f32_f64_e32 v1, v[3:4]
v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v3, 0
.p2align 6
.LBB0_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_dual_sub_f32 v4, v4, v6 :: v_dual_add_f32 v5, v7, v7
s_add_i32 s4, s3, 1
s_cmpk_gt_u32 s3, 0x7fe
s_cselect_b32 s3, -1, 0
v_fma_f32 v3, v3, v5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v7, v4, v0 :: v_dual_mul_f32 v6, v3, v3
v_mul_f32_e32 v4, v7, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v5, v3, v3, v4
v_cmp_nge_f32_e32 vcc_lo, 4.0, v5
v_mov_b32_e32 v5, s4
s_or_b32 s3, vcc_lo, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, exec_lo, s3
s_or_b32 s2, s3, s2
s_mov_b32 s3, s4
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_1
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v4, 31, v2
s_mov_b32 s2, exec_lo
v_cmpx_ne_u32_e32 0x800, v5
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_4
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v2
v_lshrrev_b32_e32 v3, 3, v5
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v4, vcc_lo
global_store_b8 v[0:1], v3, off
.LBB0_4:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB0_6
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v4, vcc_lo
v_mov_b32_e32 v3, 0
global_store_b8 v[0:1], v3, off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s2
s_clause 0x1
global_store_b8 v[0:1], v3, off offset:1
global_store_b8 v[0:1], v3, off offset:2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6renderPcii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6renderPcii, .Lfunc_end0-_Z6renderPcii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6renderPcii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6renderPcii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <assert.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
__global__ void render(char *out, int width, int height) {
int index = 3 * (blockIdx.x * blockDim.x + threadIdx.x);
int x_dim = (index / 3) % width, y_dim = (index / 3) / width;
float x_origin = ((float) x_dim/width)*3.25 - 2;
float y_origin = ((float) y_dim/width)*2.5 - 1.25;
float x = 0.0;
float y = 0.0;
int iteration = 0;
int scale = 8;
int max_iteration = 256 * scale;
while(x*x + y*y <= 4 && iteration < max_iteration) {
float xtemp = x*x - y*y + x_origin;
y = 2*x*y + y_origin;
x = xtemp;
iteration++;
}
if(iteration == max_iteration) {
out[index] = 0;
out[index + 1] = 0;
out[index + 2] = 0;
} else {
out[index] = iteration / scale;
out[index + 1] = iteration / scale;
out[index + 2] = iteration / scale;
}
}
void runCUDA(int width, int height)
{
// Multiply by 3 here, since we need red, green and blue for each pixel
size_t buffer_size = sizeof(char) * width * height * 3;
char *image;
hipMalloc((void **) &image, buffer_size);
char *host_image = (char *) malloc(buffer_size);
dim3 blockDim(64, 1, 1);
dim3 gridDim(width * height / blockDim.x, 1, 1);
render<<< gridDim, blockDim, 0 >>>(image, width, height);
hipMemcpy(host_image, image, buffer_size, hipMemcpyDeviceToHost);
// Now write the file
/*printf("P3\n%d %d\n255\n", width, height);
for (int row = 0; row < height; row++) {
for (int col = 0; col < width; col++) {
for (int i = 0; i < 3; i++) {
unsigned char c = host_image[(row * width + col) * 3 + i];
printf("%d ", c);
}
}
printf("\n");
}*/
hipFree(image);
free(host_image);
}
int main(int argc, const char * argv[]) {
int N = 1024;
runCUDA(N, N);
return 0;
} | .text
.file "mandelbrot.hip"
.globl _Z21__device_stub__renderPcii # -- Begin function _Z21__device_stub__renderPcii
.p2align 4, 0x90
.type _Z21__device_stub__renderPcii,@function
_Z21__device_stub__renderPcii: # @_Z21__device_stub__renderPcii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6renderPcii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__renderPcii, .Lfunc_end0-_Z21__device_stub__renderPcii
.cfi_endproc
# -- End function
.globl _Z7runCUDAii # -- Begin function _Z7runCUDAii
.p2align 4, 0x90
.type _Z7runCUDAii,@function
_Z7runCUDAii: # @_Z7runCUDAii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $104, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movl %edi, %r15d
movslq %edi, %rax
movslq %esi, %rcx
imulq %rax, %rcx
leaq (%rcx,%rcx,2), %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq %rbx, %rdi
callq malloc
movq %rax, %r14
movl %ebp, %edi
imull %r15d, %edi
shrl $6, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $64, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl %r15d, 20(%rsp)
movl %ebp, 16(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6renderPcii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq free
addq $104, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z7runCUDAii, .Lfunc_end1-_Z7runCUDAii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $1024, %edi # imm = 0x400
movl $1024, %esi # imm = 0x400
callq _Z7runCUDAii
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6renderPcii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6renderPcii,@object # @_Z6renderPcii
.section .rodata,"a",@progbits
.globl _Z6renderPcii
.p2align 3, 0x0
_Z6renderPcii:
.quad _Z21__device_stub__renderPcii
.size _Z6renderPcii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6renderPcii"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__renderPcii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6renderPcii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6renderPcii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R7, c[0x0][0x168] ; /* 0x00005a0000077a13 */
/* 0x000fe20000000000 */
/*0020*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0030*/ BSSY B0, 0x300 ; /* 0x000002c000007945 */
/* 0x000fe40003800000 */
/*0040*/ I2F.RP R4, R7 ; /* 0x0000000700047306 */
/* 0x000e620000209400 */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e2e0000002100 */
/*0060*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x002e620000001000 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0205 */
/*0080*/ IMAD R0, R0, 0x3, RZ ; /* 0x0000000300007824 */
/* 0x000fe200078e02ff */
/*0090*/ IADD3 R3, R4, 0xffffffe, RZ ; /* 0x0ffffffe04037810 */
/* 0x002fc60007ffe0ff */
/*00a0*/ IMAD.HI R2, R0, 0x55555556, RZ ; /* 0x5555555600027827 */
/* 0x000fc600078e02ff */
/*00b0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e24000021f000 */
/*00c0*/ LEA.HI R5, R2, R2, RZ, 0x1 ; /* 0x0000000202057211 */
/* 0x000fe200078f08ff */
/*00d0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fc600078e00ff */
/*00e0*/ IABS R4, R5 ; /* 0x0000000500047213 */
/* 0x000fe20000000000 */
/*00f0*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x001fc800078e0a03 */
/*0100*/ IMAD R9, R6, R7, RZ ; /* 0x0000000706097224 */
/* 0x000fc800078e02ff */
/*0110*/ IMAD.HI.U32 R2, R3, R9, R2 ; /* 0x0000000903027227 */
/* 0x000fc800078e0002 */
/*0120*/ IMAD.MOV.U32 R3, RZ, RZ, R4 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0004 */
/*0130*/ IMAD.HI.U32 R4, R2, R3, RZ ; /* 0x0000000302047227 */
/* 0x000fc800078e00ff */
/*0140*/ IMAD.MOV R2, RZ, RZ, -R4 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0a04 */
/*0150*/ IMAD R2, R7, R2, R3 ; /* 0x0000000207027224 */
/* 0x000fca00078e0203 */
/*0160*/ ISETP.GT.U32.AND P2, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x000fda0003f44070 */
/*0170*/ @!P2 IMAD.IADD R2, R2, 0x1, -R7 ; /* 0x000000010202a824 */
/* 0x000fe200078e0a07 */
/*0180*/ @!P2 IADD3 R4, R4, 0x1, RZ ; /* 0x000000010404a810 */
/* 0x000fe40007ffe0ff */
/*0190*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe40003f45270 */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R2, R7, PT ; /* 0x000000070200720c */
/* 0x000fe40003f06070 */
/*01b0*/ LOP3.LUT R2, R5, c[0x0][0x168], RZ, 0x3c, !PT ; /* 0x00005a0005027a12 */
/* 0x000fc800078e3cff */
/*01c0*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f26270 */
/*01d0*/ I2F R2, c[0x0][0x168] ; /* 0x00005a0000027b06 */
/* 0x000e2a0000201400 */
/*01e0*/ @P0 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104040810 */
/* 0x000fcc0007ffe0ff */
/*01f0*/ @!P1 IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff049224 */
/* 0x000fe200078e0a04 */
/*0200*/ @!P2 LOP3.LUT R4, RZ, c[0x0][0x168], RZ, 0x33, !PT ; /* 0x00005a00ff04aa12 */
/* 0x000fe200078e33ff */
/*0210*/ MUFU.RCP R3, R2 ; /* 0x0000000200037308 */
/* 0x001e280000001000 */
/*0220*/ IMAD.MOV R6, RZ, RZ, -R4 ; /* 0x000000ffff067224 */
/* 0x000fc800078e0a04 */
/*0230*/ IMAD R5, R6, c[0x0][0x168], R5 ; /* 0x00005a0006057a24 */
/* 0x000fc800078e0205 */
/*0240*/ I2F R9, R5 ; /* 0x0000000500097306 */
/* 0x000e620000201400 */
/*0250*/ FFMA R6, -R2, R3, 1 ; /* 0x3f80000002067423 */
/* 0x001fc80000000103 */
/*0260*/ FFMA R6, R3, R6, R3 ; /* 0x0000000603067223 */
/* 0x000fc60000000003 */
/*0270*/ FCHK P0, R9, R2 ; /* 0x0000000209007302 */
/* 0x002e220000000000 */
/*0280*/ FFMA R3, R9, R6, RZ ; /* 0x0000000609037223 */
/* 0x000fc800000000ff */
/*0290*/ FFMA R7, -R2, R3, R9 ; /* 0x0000000302077223 */
/* 0x000fc80000000109 */
/*02a0*/ FFMA R10, R6, R7, R3 ; /* 0x00000007060a7223 */
/* 0x000fe20000000003 */
/*02b0*/ @!P0 BRA 0x2f0 ; /* 0x0000003000008947 */
/* 0x001fea0003800000 */
/*02c0*/ MOV R6, 0x2e0 ; /* 0x000002e000067802 */
/* 0x000fe40000000f00 */
/*02d0*/ CALL.REL.NOINC 0x670 ; /* 0x0000039000007944 */
/* 0x000fea0003c00000 */
/*02e0*/ IMAD.MOV.U32 R10, RZ, RZ, R5 ; /* 0x000000ffff0a7224 */
/* 0x001fe400078e0005 */
/*02f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0300*/ I2F R11, R4 ; /* 0x00000004000b7306 */
/* 0x000e220000201400 */
/*0310*/ IMAD.MOV.U32 R8, RZ, RZ, 0x0 ; /* 0x00000000ff087424 */
/* 0x000fe200078e00ff */
/*0320*/ BSSY B0, 0x440 ; /* 0x0000011000007945 */
/* 0x000fe20003800000 */
/*0330*/ IMAD.MOV.U32 R9, RZ, RZ, 0x400a0000 ; /* 0x400a0000ff097424 */
/* 0x000fca00078e00ff */
/*0340*/ F2F.F64.F32 R6, R10 ; /* 0x0000000a00067310 */
/* 0x000e700000201800 */
/*0350*/ MUFU.RCP R3, R2 ; /* 0x0000000200037308 */
/* 0x000eb00000001000 */
/*0360*/ FCHK P0, R11, R2 ; /* 0x000000020b007302 */
/* 0x001e220000000000 */
/*0370*/ DFMA R6, R6, R8, -2 ; /* 0xc00000000606742b */
/* 0x002e620000000008 */
/*0380*/ FFMA R12, -R2, R3, 1 ; /* 0x3f800000020c7423 */
/* 0x004fc80000000103 */
/*0390*/ FFMA R12, R3, R12, R3 ; /* 0x0000000c030c7223 */
/* 0x000fe40000000003 */
/*03a0*/ F2F.F32.F64 R3, R6 ; /* 0x0000000600037310 */
/* 0x0022a40000301000 */
/*03b0*/ FFMA R5, R12, R11, RZ ; /* 0x0000000b0c057223 */
/* 0x000fc800000000ff */
/*03c0*/ FFMA R8, -R2, R5, R11 ; /* 0x0000000502087223 */
/* 0x000fc8000000010b */
/*03d0*/ FFMA R8, R12, R8, R5 ; /* 0x000000080c087223 */
/* 0x000fe20000000005 */
/*03e0*/ @!P0 BRA 0x430 ; /* 0x0000004000008947 */
/* 0x001fea0003800000 */
/*03f0*/ IMAD.MOV.U32 R9, RZ, RZ, R11 ; /* 0x000000ffff097224 */
/* 0x002fe200078e000b */
/*0400*/ MOV R6, 0x420 ; /* 0x0000042000067802 */
/* 0x000fe40000000f00 */
/*0410*/ CALL.REL.NOINC 0x670 ; /* 0x0000025000007944 */
/* 0x004fea0003c00000 */
/*0420*/ IMAD.MOV.U32 R8, RZ, RZ, R5 ; /* 0x000000ffff087224 */
/* 0x001fe400078e0005 */
/*0430*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*0440*/ F2F.F64.F32 R4, R8 ; /* 0x0000000800047310 */
/* 0x000e220000201800 */
/*0450*/ IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; /* 0x00000000ff067424 */
/* 0x000fe200078e00ff */
/*0460*/ BSSY B0, 0x5a0 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*0470*/ IMAD.MOV.U32 R7, RZ, RZ, 0x40040000 ; /* 0x40040000ff077424 */
/* 0x000fe400078e00ff */
/*0480*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe400078e00ff */
/*0490*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe400078e00ff */
/*04a0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e00ff */
/*04b0*/ DFMA R4, R4, R6, -1.25 ; /* 0xbff400000404742b */
/* 0x0010440000000006 */
/*04c0*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x001fd0000001ff00 */
/*04d0*/ F2F.F32.F64 R5, R4 ; /* 0x0000000400057310 */
/* 0x0020640000301000 */
/*04e0*/ FADD R2, R7, -R2 ; /* 0x8000000207027221 */
/* 0x000fe20000000000 */
/*04f0*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fe20007ffe0ff */
/*0500*/ FADD R4, R10, R10 ; /* 0x0000000a0a047221 */
/* 0x001fe40000000000 */
/*0510*/ FADD R10, R3, R2 ; /* 0x00000002030a7221 */
/* 0x004fe20000000000 */
/*0520*/ ISETP.GE.U32.AND P0, PT, R6, 0x800, PT ; /* 0x000008000600780c */
/* 0x000fe20003f06070 */
/*0530*/ FFMA R9, R4, R9, R5 ; /* 0x0000000904097223 */
/* 0x002fe40000000005 */
/*0540*/ FMUL R7, R10, R10 ; /* 0x0000000a0a077220 */
/* 0x000fe40000400000 */
/*0550*/ FMUL R2, R9, R9 ; /* 0x0000000909027220 */
/* 0x000fc80000400000 */
/*0560*/ FADD R4, R7, R2 ; /* 0x0000000207047221 */
/* 0x000fca0000000000 */
/*0570*/ FSETP.LE.AND P1, PT, R4, 4, PT ; /* 0x408000000400780b */
/* 0x000fda0003f23000 */
/*0580*/ @!P0 BRA P1, 0x4e0 ; /* 0xffffff5000008947 */
/* 0x000fea000083ffff */
/*0590*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05a0*/ ISETP.NE.AND P0, PT, R6, 0x800, PT ; /* 0x000008000600780c */
/* 0x000fe20003f05270 */
/*05b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*05c0*/ IADD3 R2, P1, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fc80007f3e0ff */
/*05d0*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x164], 0x1, P1 ; /* 0x0000590000037a11 */
/* 0x000fce00008f0eff */
/*05e0*/ @P0 SHF.R.U32.HI R5, RZ, 0x3, R6 ; /* 0x00000003ff050819 */
/* 0x000fca0000011606 */
/*05f0*/ @P0 STG.E.U8 [R2.64], R5 ; /* 0x0000000502000986 */
/* 0x0001e8000c101104 */
/*0600*/ @P0 STG.E.U8 [R2.64+0x1], R5 ; /* 0x0000010502000986 */
/* 0x0001e8000c101104 */
/*0610*/ @P0 STG.E.U8 [R2.64+0x2], R5 ; /* 0x0000020502000986 */
/* 0x0001e2000c101104 */
/*0620*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0630*/ STG.E.U8 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe8000c101104 */
/*0640*/ STG.E.U8 [R2.64+0x1], RZ ; /* 0x000001ff02007986 */
/* 0x000fe8000c101104 */
/*0650*/ STG.E.U8 [R2.64+0x2], RZ ; /* 0x000002ff02007986 */
/* 0x000fe2000c101104 */
/*0660*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0670*/ SHF.R.U32.HI R7, RZ, 0x17, R2.reuse ; /* 0x00000017ff077819 */
/* 0x100fe20000011602 */
/*0680*/ BSSY B1, 0xcd0 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0690*/ SHF.R.U32.HI R5, RZ, 0x17, R9 ; /* 0x00000017ff057819 */
/* 0x000fe20000011609 */
/*06a0*/ IMAD.MOV.U32 R8, RZ, RZ, R2 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0002 */
/*06b0*/ LOP3.LUT R13, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff070d7812 */
/* 0x000fc400078ec0ff */
/*06c0*/ LOP3.LUT R11, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff050b7812 */
/* 0x000fe200078ec0ff */
/*06d0*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0009 */
/*06e0*/ IADD3 R12, R13, -0x1, RZ ; /* 0xffffffff0d0c7810 */
/* 0x000fe40007ffe0ff */
/*06f0*/ IADD3 R10, R11, -0x1, RZ ; /* 0xffffffff0b0a7810 */
/* 0x000fe40007ffe0ff */
/*0700*/ ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ; /* 0x000000fd0c00780c */
/* 0x000fc80003f04070 */
/*0710*/ ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ; /* 0x000000fd0a00780c */
/* 0x000fda0000704470 */
/*0720*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff078224 */
/* 0x000fe200078e00ff */
/*0730*/ @!P0 BRA 0x8b0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0740*/ FSETP.GTU.FTZ.AND P0, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fe40003f1c200 */
/*0750*/ FSETP.GTU.FTZ.AND P1, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fc80003f3c200 */
/*0760*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0770*/ @P0 BRA 0xcb0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0780*/ LOP3.LUT P0, RZ, R8, 0x7fffffff, R5, 0xc8, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000780c805 */
/*0790*/ @!P0 BRA 0xc90 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*07a0*/ FSETP.NEU.FTZ.AND P2, PT, |R9|.reuse, +INF , PT ; /* 0x7f8000000900780b */
/* 0x040fe40003f5d200 */
/*07b0*/ FSETP.NEU.FTZ.AND P1, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fe40003f3d200 */
/*07c0*/ FSETP.NEU.FTZ.AND P0, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fd60003f1d200 */
/*07d0*/ @!P1 BRA !P2, 0xc90 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*07e0*/ LOP3.LUT P2, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05ff7812 */
/* 0x000fc8000784c0ff */
/*07f0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0800*/ @P1 BRA 0xc70 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0810*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000782c0ff */
/*0820*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0830*/ @P0 BRA 0xc40 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0840*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f06270 */
/*0850*/ ISETP.GE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fd60003f26270 */
/*0860*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff070224 */
/* 0x000fe400078e00ff */
/*0870*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, -0x40 ; /* 0xffffffc0ff078424 */
/* 0x000fe400078e00ff */
/*0880*/ @!P0 FFMA R5, R9, 1.84467440737095516160e+19, RZ ; /* 0x5f80000009058823 */
/* 0x000fe400000000ff */
/*0890*/ @!P1 FFMA R8, R2, 1.84467440737095516160e+19, RZ ; /* 0x5f80000002089823 */
/* 0x000fe200000000ff */
/*08a0*/ @!P1 IADD3 R7, R7, 0x40, RZ ; /* 0x0000004007079810 */
/* 0x000fe40007ffe0ff */
/*08b0*/ LEA R9, R13, 0xc0800000, 0x17 ; /* 0xc08000000d097811 */
/* 0x000fe200078eb8ff */
/*08c0*/ BSSY B2, 0xc30 ; /* 0x0000036000027945 */
/* 0x000fe80003800000 */
/*08d0*/ IMAD.IADD R9, R8, 0x1, -R9 ; /* 0x0000000108097824 */
/* 0x000fe200078e0a09 */
/*08e0*/ IADD3 R8, R11, -0x7f, RZ ; /* 0xffffff810b087810 */
/* 0x000fc60007ffe0ff */
/*08f0*/ MUFU.RCP R10, R9 ; /* 0x00000009000a7308 */
/* 0x000e220000001000 */
/*0900*/ FADD.FTZ R12, -R9, -RZ ; /* 0x800000ff090c7221 */
/* 0x000fe40000010100 */
/*0910*/ IMAD R5, R8, -0x800000, R5 ; /* 0xff80000008057824 */
/* 0x000fe400078e0205 */
/*0920*/ FFMA R11, R10, R12, 1 ; /* 0x3f8000000a0b7423 */
/* 0x001fc8000000000c */
/*0930*/ FFMA R14, R10, R11, R10 ; /* 0x0000000b0a0e7223 */
/* 0x000fc8000000000a */
/*0940*/ FFMA R10, R5, R14, RZ ; /* 0x0000000e050a7223 */
/* 0x000fc800000000ff */
/*0950*/ FFMA R11, R12, R10, R5 ; /* 0x0000000a0c0b7223 */
/* 0x000fc80000000005 */
/*0960*/ FFMA R11, R14, R11, R10 ; /* 0x0000000b0e0b7223 */
/* 0x000fe2000000000a */
/*0970*/ IADD3 R10, R8, 0x7f, -R13 ; /* 0x0000007f080a7810 */
/* 0x000fc60007ffe80d */
/*0980*/ FFMA R12, R12, R11, R5 ; /* 0x0000000b0c0c7223 */
/* 0x000fe40000000005 */
/*0990*/ IMAD.IADD R10, R10, 0x1, R7 ; /* 0x000000010a0a7824 */
/* 0x000fe400078e0207 */
/*09a0*/ FFMA R5, R14, R12, R11 ; /* 0x0000000c0e057223 */
/* 0x000fca000000000b */
/*09b0*/ SHF.R.U32.HI R8, RZ, 0x17, R5 ; /* 0x00000017ff087819 */
/* 0x000fc80000011605 */
/*09c0*/ LOP3.LUT R8, R8, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff08087812 */
/* 0x000fca00078ec0ff */
/*09d0*/ IMAD.IADD R13, R8, 0x1, R10 ; /* 0x00000001080d7824 */
/* 0x000fca00078e020a */
/*09e0*/ IADD3 R7, R13, -0x1, RZ ; /* 0xffffffff0d077810 */
/* 0x000fc80007ffe0ff */
/*09f0*/ ISETP.GE.U32.AND P0, PT, R7, 0xfe, PT ; /* 0x000000fe0700780c */
/* 0x000fda0003f06070 */
/*0a00*/ @!P0 BRA 0xc10 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0a10*/ ISETP.GT.AND P0, PT, R13, 0xfe, PT ; /* 0x000000fe0d00780c */
/* 0x000fda0003f04270 */
/*0a20*/ @P0 BRA 0xbe0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0a30*/ ISETP.GE.AND P0, PT, R13, 0x1, PT ; /* 0x000000010d00780c */
/* 0x000fda0003f06270 */
/*0a40*/ @P0 BRA 0xc20 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0a50*/ ISETP.GE.AND P0, PT, R13, -0x18, PT ; /* 0xffffffe80d00780c */
/* 0x000fe40003f06270 */
/*0a60*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fd600078ec0ff */
/*0a70*/ @!P0 BRA 0xc20 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0a80*/ FFMA.RZ R7, R14.reuse, R12.reuse, R11.reuse ; /* 0x0000000c0e077223 */
/* 0x1c0fe2000000c00b */
/*0a90*/ IADD3 R10, R13.reuse, 0x20, RZ ; /* 0x000000200d0a7810 */
/* 0x040fe20007ffe0ff */
/*0aa0*/ FFMA.RM R8, R14.reuse, R12.reuse, R11.reuse ; /* 0x0000000c0e087223 */
/* 0x1c0fe2000000400b */
/*0ab0*/ ISETP.NE.AND P2, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe40003f45270 */
/*0ac0*/ LOP3.LUT R9, R7, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff07097812 */
/* 0x000fe200078ec0ff */
/*0ad0*/ FFMA.RP R7, R14, R12, R11 ; /* 0x0000000c0e077223 */
/* 0x000fe2000000800b */
/*0ae0*/ ISETP.NE.AND P1, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe20003f25270 */
/*0af0*/ IMAD.MOV R11, RZ, RZ, -R13 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0a0d */
/*0b00*/ LOP3.LUT R9, R9, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000009097812 */
/* 0x000fe400078efcff */
/*0b10*/ FSETP.NEU.FTZ.AND P0, PT, R7, R8, PT ; /* 0x000000080700720b */
/* 0x000fc40003f1d000 */
/*0b20*/ SHF.L.U32 R10, R9, R10, RZ ; /* 0x0000000a090a7219 */
/* 0x000fe400000006ff */
/*0b30*/ SEL R8, R11, RZ, P2 ; /* 0x000000ff0b087207 */
/* 0x000fe40001000000 */
/*0b40*/ ISETP.NE.AND P1, PT, R10, RZ, P1 ; /* 0x000000ff0a00720c */
/* 0x000fe40000f25270 */
/*0b50*/ SHF.R.U32.HI R8, RZ, R8, R9 ; /* 0x00000008ff087219 */
/* 0x000fe40000011609 */
/*0b60*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0b70*/ SHF.R.U32.HI R10, RZ, 0x1, R8 ; /* 0x00000001ff0a7819 */
/* 0x000fc40000011608 */
/*0b80*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fc80004000000 */
/*0b90*/ LOP3.LUT R7, R7, 0x1, R10, 0xf8, !PT ; /* 0x0000000107077812 */
/* 0x000fc800078ef80a */
/*0ba0*/ LOP3.LUT R7, R7, R8, RZ, 0xc0, !PT ; /* 0x0000000807077212 */
/* 0x000fca00078ec0ff */
/*0bb0*/ IMAD.IADD R10, R10, 0x1, R7 ; /* 0x000000010a0a7824 */
/* 0x000fca00078e0207 */
/*0bc0*/ LOP3.LUT R5, R10, R5, RZ, 0xfc, !PT ; /* 0x000000050a057212 */
/* 0x000fe200078efcff */
/*0bd0*/ BRA 0xc20 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0be0*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fc800078ec0ff */
/*0bf0*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*0c00*/ BRA 0xc20 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0c10*/ IMAD R5, R10, 0x800000, R5 ; /* 0x008000000a057824 */
/* 0x000fe400078e0205 */
/*0c20*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0c30*/ BRA 0xcc0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0c40*/ LOP3.LUT R5, R8, 0x80000000, R5, 0x48, !PT ; /* 0x8000000008057812 */
/* 0x000fc800078e4805 */
/*0c50*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*0c60*/ BRA 0xcc0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0c70*/ LOP3.LUT R5, R8, 0x80000000, R5, 0x48, !PT ; /* 0x8000000008057812 */
/* 0x000fe200078e4805 */
/*0c80*/ BRA 0xcc0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0c90*/ MUFU.RSQ R5, -QNAN ; /* 0xffc0000000057908 */
/* 0x000e220000001400 */
/*0ca0*/ BRA 0xcc0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0cb0*/ FADD.FTZ R5, R9, R2 ; /* 0x0000000209057221 */
/* 0x000fe40000010000 */
/*0cc0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0cd0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fc800078e00ff */
/*0ce0*/ RET.REL.NODEC R6 0x0 ; /* 0xfffff31006007950 */
/* 0x000fea0003c3ffff */
/*0cf0*/ BRA 0xcf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6renderPcii
.globl _Z6renderPcii
.p2align 8
.type _Z6renderPcii,@function
_Z6renderPcii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x8
s_load_b32 s3, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_ashr_i32 s4, s2, 31
s_and_b32 s3, s3, 0xffff
s_add_i32 s5, s2, s4
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_xor_b32 s3, s5, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cvt_f32_u32_e32 v0, s3
s_sub_i32 s5, 0, s3
v_lshl_add_u32 v2, v1, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
v_mul_hi_i32 v1, v2, 0x55555556
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v3, 31, v1
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v0, 0x4f7ffffe, v0 :: v_dual_add_nc_u32 v1, v1, v3
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v1
v_mul_lo_u32 v3, s5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v5, v1, v4
v_mul_hi_u32 v3, v0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_xor_b32_e32 v5, v5, v4
v_xor_b32_e32 v4, s4, v4
v_add_nc_u32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v5, v0
v_mul_lo_u32 v3, v0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v5, v3
v_add_nc_u32_e32 v5, 1, v0
v_subrev_nc_u32_e32 v6, s3, v3
v_cmp_le_u32_e32 vcc_lo, s3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v0, v0, v5 :: v_dual_cndmask_b32 v3, v3, v6
v_add_nc_u32_e32 v5, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s3, v3
v_cndmask_b32_e32 v0, v0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v4
v_sub_nc_u32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v3, v0, s2
v_cvt_f32_i32_e32 v0, v0
v_sub_nc_u32_e32 v1, v1, v3
v_cvt_f32_i32_e32 v3, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v1, v1
v_div_scale_f32 v5, null, v3, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_scale_f32 v4, null, v3, v3, v1
v_rcp_f32_e32 v7, v5
v_div_scale_f32 v10, vcc_lo, v1, v3, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v6, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v9, -v5, v7, 1.0
v_fma_f32 v8, -v4, v6, 1.0
v_dual_fmac_f32 v7, v9, v7 :: v_dual_fmac_f32 v6, v8, v6
v_div_scale_f32 v8, s2, v0, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v9, v10, v6
v_mul_f32_e32 v11, v8, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v12, -v4, v9, v10
v_fma_f32 v13, -v5, v11, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v9, v12, v6
v_fmac_f32_e32 v11, v13, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v4, -v4, v9, v10
v_fma_f32 v5, -v5, v11, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_fmas_f32 v4, v4, v6, v9
s_mov_b32 vcc_lo, s2
s_mov_b32 s2, 0
v_div_fmas_f32 v5, v5, v7, v11
s_mov_b32 s3, 0x40040000
v_div_fixup_f32 v1, v4, v3, v1
v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v7, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fixup_f32 v3, v5, v3, v0
v_cvt_f64_f32_e32 v[0:1], v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f64_f32_e32 v[3:4], v3
v_fma_f64 v[0:1], v[0:1], 0x400a0000, -2.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fma_f64 v[3:4], v[3:4], s[2:3], 0xbff40000
s_mov_b32 s2, 0
s_mov_b32 s3, 0
v_cvt_f32_f64_e32 v0, v[0:1]
s_delay_alu instid0(VALU_DEP_2)
v_cvt_f32_f64_e32 v1, v[3:4]
v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v3, 0
.p2align 6
.LBB0_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_dual_sub_f32 v4, v4, v6 :: v_dual_add_f32 v5, v7, v7
s_add_i32 s4, s3, 1
s_cmpk_gt_u32 s3, 0x7fe
s_cselect_b32 s3, -1, 0
v_fma_f32 v3, v3, v5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v7, v4, v0 :: v_dual_mul_f32 v6, v3, v3
v_mul_f32_e32 v4, v7, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v5, v3, v3, v4
v_cmp_nge_f32_e32 vcc_lo, 4.0, v5
v_mov_b32_e32 v5, s4
s_or_b32 s3, vcc_lo, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, exec_lo, s3
s_or_b32 s2, s3, s2
s_mov_b32 s3, s4
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_1
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v4, 31, v2
s_mov_b32 s2, exec_lo
v_cmpx_ne_u32_e32 0x800, v5
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_4
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v2
v_lshrrev_b32_e32 v3, 3, v5
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v4, vcc_lo
global_store_b8 v[0:1], v3, off
.LBB0_4:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB0_6
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v4, vcc_lo
v_mov_b32_e32 v3, 0
global_store_b8 v[0:1], v3, off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s2
s_clause 0x1
global_store_b8 v[0:1], v3, off offset:1
global_store_b8 v[0:1], v3, off offset:2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6renderPcii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6renderPcii, .Lfunc_end0-_Z6renderPcii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6renderPcii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6renderPcii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b2adc_00000000-6_mandelbrot.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z6renderPciiPcii
.type _Z27__device_stub__Z6renderPciiPcii, @function
_Z27__device_stub__Z6renderPciiPcii:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6renderPcii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z27__device_stub__Z6renderPciiPcii, .-_Z27__device_stub__Z6renderPciiPcii
.globl _Z6renderPcii
.type _Z6renderPcii, @function
_Z6renderPcii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6renderPciiPcii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z6renderPcii, .-_Z6renderPcii
.globl _Z7runCUDAii
.type _Z7runCUDAii, @function
_Z7runCUDAii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movl %esi, %ebp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movslq %edi, %rax
movslq %esi, %rdx
imulq %rdx, %rax
leaq (%rax,%rax,2), %r13
leaq 8(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movq %r13, %rdi
call malloc@PLT
movq %rax, %r12
movl $1, 20(%rsp)
movl %ebx, %eax
imull %ebp, %eax
shrl $6, %eax
movl %eax, 28(%rsp)
movl $1, 32(%rsp)
movl $64, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movq %r13, %rdx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl %ebp, %edx
movl %ebx, %esi
movq 8(%rsp), %rdi
call _Z27__device_stub__Z6renderPciiPcii
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z7runCUDAii, .-_Z7runCUDAii
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $1024, %esi
movl $1024, %edi
call _Z7runCUDAii
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6renderPcii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6renderPcii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mandelbrot.hip"
.globl _Z21__device_stub__renderPcii # -- Begin function _Z21__device_stub__renderPcii
.p2align 4, 0x90
.type _Z21__device_stub__renderPcii,@function
_Z21__device_stub__renderPcii: # @_Z21__device_stub__renderPcii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6renderPcii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__renderPcii, .Lfunc_end0-_Z21__device_stub__renderPcii
.cfi_endproc
# -- End function
.globl _Z7runCUDAii # -- Begin function _Z7runCUDAii
.p2align 4, 0x90
.type _Z7runCUDAii,@function
_Z7runCUDAii: # @_Z7runCUDAii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $104, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movl %edi, %r15d
movslq %edi, %rax
movslq %esi, %rcx
imulq %rax, %rcx
leaq (%rcx,%rcx,2), %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq %rbx, %rdi
callq malloc
movq %rax, %r14
movl %ebp, %edi
imull %r15d, %edi
shrl $6, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $64, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl %r15d, 20(%rsp)
movl %ebp, 16(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6renderPcii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq free
addq $104, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z7runCUDAii, .Lfunc_end1-_Z7runCUDAii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $1024, %edi # imm = 0x400
movl $1024, %esi # imm = 0x400
callq _Z7runCUDAii
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6renderPcii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6renderPcii,@object # @_Z6renderPcii
.section .rodata,"a",@progbits
.globl _Z6renderPcii
.p2align 3, 0x0
_Z6renderPcii:
.quad _Z21__device_stub__renderPcii
.size _Z6renderPcii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6renderPcii"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__renderPcii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6renderPcii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
__device__ uint32_t k[64] = {0};
// K specifies the per-round shift amounts
__device__ const uint32_t K[] = {
7, 12, 17, 22, 7, 12, 17, 22, 7, 12, 17, 22, 7, 12, 17, 22,
5, 9, 14, 20, 5, 9, 14, 20, 5, 9, 14, 20, 5, 9, 14, 20,
4, 11, 16, 23, 4, 11, 16, 23, 4, 11, 16, 23, 4, 11, 16, 23,
6, 10, 15, 21, 6, 10, 15, 21, 6, 10, 15, 21, 6, 10, 15, 21};
// leftrotate function definition
__device__ uint32_t leftrotate(uint32_t x, uint32_t C) {
return (((x) << (C)) | ((x) >> (32 - (C))));
}
__device__ void append_bytes(uint32_t val, uint8_t *outputs) {
outputs[0] = (uint8_t)val;
outputs[1] = (uint8_t)(val >> 8);
outputs[2] = (uint8_t)(val >> 16);
outputs[3] = (uint8_t)(val >> 24);
}
__device__ uint32_t append_int(const uint8_t *inputs) {
return (uint32_t)inputs[0] | ((uint32_t)inputs[1] << 8) |
((uint32_t)inputs[2] << 16) | ((uint32_t)inputs[3] << 24);
}
__device__ void md5(const uint8_t *orig_msg, size_t orig_len,
uint8_t *digest) {
// Use binary integer part of the sines of integers (Radians) as constants:
for (int i = 0; i < 64; i++) {
k[i] = (uint32_t)(abs(sin(i + 1.0)) * ((long long)1 << 32));
}
// Initialize variables:
uint32_t a0 = 0x67452301;
uint32_t b0 = 0xefcdab89;
uint32_t c0 = 0x98badcfe;
uint32_t d0 = 0x10325476;
size_t new_len, offset;
uint32_t M[16];
uint32_t A, B, C, D, F, g;
// append "0" bit until message length in bits ≡ 448 (mod 512)
for (new_len = orig_len + 1; new_len % (512 / 8) != 448 / 8; new_len++);
uint8_t *message = (uint8_t *)malloc(new_len + 8);
memcpy(message, orig_msg, orig_len);
// Pre-processing: adding a single 1 bit
message[orig_len] = 0x80;
// Pre-processing: padding with zeros
for (offset = orig_len + 1; offset < new_len; offset++){
message[offset] = 0;
}
// append length mod (2^64) to message
append_bytes(orig_len * 8, message + new_len);
// address the overflow part
append_bytes(orig_len >> 29, message + new_len + 4);
// Process the message in successive 512-bit chunks:
// for each 512-bit chunk of message:
for (offset = 0; offset < new_len; offset += (512 / 8)) {
// break chunk into sixteen 32-bit words w[j], 0 ≤ j ≤ 15
for (int i = 0; i < 16; i++) {
M[i] = append_int(message + offset + i * 4);
}
// Initialize hash value for this chunk:
A = a0;
B = b0;
C = c0;
D = d0;
// Main loop:
for (int i = 0; i < 64; i++) {
if (i < 16) {
F = (B & C) | ((~B) & D);
g = i;
} else if (i < 32) {
F = (D & B) | ((~D) & C);
g = (5 * i + 1) % 16;
} else if (i < 48) {
F = B ^ C ^ D;
g = (3 * i + 5) % 16;
} else {
F = C ^ (B | (~D));
g = (7 * i) % 16;
}
// Be wary of the below definitions of a,b,c,d
F = A + F + k[i] + M[g]; // M[g] must be a 32-bits block
A = D;
D = C;
C = B;
B = B + leftrotate(F, K[i]);
}
// Add this chunk's hash to result so far:
a0 += A;
b0 += B;
c0 += C;
d0 += D;
}
// cleanup
free(message);
// var char digest[16] := a0 append b0 append c0 append d0 //(Output is in
// little-endian)
append_bytes(a0, digest);
append_bytes(b0, digest + 4);
append_bytes(c0, digest + 8);
append_bytes(d0, digest + 12);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
__device__ uint32_t k[64] = {0};
// K specifies the per-round shift amounts
__device__ const uint32_t K[] = {
7, 12, 17, 22, 7, 12, 17, 22, 7, 12, 17, 22, 7, 12, 17, 22,
5, 9, 14, 20, 5, 9, 14, 20, 5, 9, 14, 20, 5, 9, 14, 20,
4, 11, 16, 23, 4, 11, 16, 23, 4, 11, 16, 23, 4, 11, 16, 23,
6, 10, 15, 21, 6, 10, 15, 21, 6, 10, 15, 21, 6, 10, 15, 21};
// leftrotate function definition
__device__ uint32_t leftrotate(uint32_t x, uint32_t C) {
return (((x) << (C)) | ((x) >> (32 - (C))));
}
__device__ void append_bytes(uint32_t val, uint8_t *outputs) {
outputs[0] = (uint8_t)val;
outputs[1] = (uint8_t)(val >> 8);
outputs[2] = (uint8_t)(val >> 16);
outputs[3] = (uint8_t)(val >> 24);
}
__device__ uint32_t append_int(const uint8_t *inputs) {
return (uint32_t)inputs[0] | ((uint32_t)inputs[1] << 8) |
((uint32_t)inputs[2] << 16) | ((uint32_t)inputs[3] << 24);
}
__device__ void md5(const uint8_t *orig_msg, size_t orig_len,
uint8_t *digest) {
// Use binary integer part of the sines of integers (Radians) as constants:
for (int i = 0; i < 64; i++) {
k[i] = (uint32_t)(abs(sin(i + 1.0)) * ((long long)1 << 32));
}
// Initialize variables:
uint32_t a0 = 0x67452301;
uint32_t b0 = 0xefcdab89;
uint32_t c0 = 0x98badcfe;
uint32_t d0 = 0x10325476;
size_t new_len, offset;
uint32_t M[16];
uint32_t A, B, C, D, F, g;
// append "0" bit until message length in bits ≡ 448 (mod 512)
for (new_len = orig_len + 1; new_len % (512 / 8) != 448 / 8; new_len++);
uint8_t *message = (uint8_t *)malloc(new_len + 8);
memcpy(message, orig_msg, orig_len);
// Pre-processing: adding a single 1 bit
message[orig_len] = 0x80;
// Pre-processing: padding with zeros
for (offset = orig_len + 1; offset < new_len; offset++){
message[offset] = 0;
}
// append length mod (2^64) to message
append_bytes(orig_len * 8, message + new_len);
// address the overflow part
append_bytes(orig_len >> 29, message + new_len + 4);
// Process the message in successive 512-bit chunks:
// for each 512-bit chunk of message:
for (offset = 0; offset < new_len; offset += (512 / 8)) {
// break chunk into sixteen 32-bit words w[j], 0 ≤ j ≤ 15
for (int i = 0; i < 16; i++) {
M[i] = append_int(message + offset + i * 4);
}
// Initialize hash value for this chunk:
A = a0;
B = b0;
C = c0;
D = d0;
// Main loop:
for (int i = 0; i < 64; i++) {
if (i < 16) {
F = (B & C) | ((~B) & D);
g = i;
} else if (i < 32) {
F = (D & B) | ((~D) & C);
g = (5 * i + 1) % 16;
} else if (i < 48) {
F = B ^ C ^ D;
g = (3 * i + 5) % 16;
} else {
F = C ^ (B | (~D));
g = (7 * i) % 16;
}
// Be wary of the below definitions of a,b,c,d
F = A + F + k[i] + M[g]; // M[g] must be a 32-bits block
A = D;
D = C;
C = B;
B = B + leftrotate(F, K[i]);
}
// Add this chunk's hash to result so far:
a0 += A;
b0 += B;
c0 += C;
d0 += D;
}
// cleanup
free(message);
// var char digest[16] := a0 append b0 append c0 append d0 //(Output is in
// little-endian)
append_bytes(a0, digest);
append_bytes(b0, digest + 4);
append_bytes(c0, digest + 8);
append_bytes(d0, digest + 12);
} | .file "tmpxft_00028801_00000000-6_hash.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10leftrotatejj
.type _Z10leftrotatejj, @function
_Z10leftrotatejj:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z10leftrotatejj, .-_Z10leftrotatejj
.globl _Z12append_bytesjPh
.type _Z12append_bytesjPh, @function
_Z12append_bytesjPh:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z12append_bytesjPh, .-_Z12append_bytesjPh
.globl _Z10append_intPKh
.type _Z10append_intPKh, @function
_Z10append_intPKh:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z10append_intPKh, .-_Z10append_intPKh
.globl _Z3md5PKhmPh
.type _Z3md5PKhmPh, @function
_Z3md5PKhmPh:
.LFB2060:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size _Z3md5PKhmPh, .-_Z3md5PKhmPh
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "k"
.LC1:
.string "K"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $256, %r9d
movl $0, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1k(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $256, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1K(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata
.align 32
.type _ZL1K, @object
.size _ZL1K, 256
_ZL1K:
.long 7
.long 12
.long 17
.long 22
.long 7
.long 12
.long 17
.long 22
.long 7
.long 12
.long 17
.long 22
.long 7
.long 12
.long 17
.long 22
.long 5
.long 9
.long 14
.long 20
.long 5
.long 9
.long 14
.long 20
.long 5
.long 9
.long 14
.long 20
.long 5
.long 9
.long 14
.long 20
.long 4
.long 11
.long 16
.long 23
.long 4
.long 11
.long 16
.long 23
.long 4
.long 11
.long 16
.long 23
.long 4
.long 11
.long 16
.long 23
.long 6
.long 10
.long 15
.long 21
.long 6
.long 10
.long 15
.long 21
.long 6
.long 10
.long 15
.long 21
.long 6
.long 10
.long 15
.long 21
.local _ZL1k
.comm _ZL1k,256,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
__device__ uint32_t k[64] = {0};
// K specifies the per-round shift amounts
__device__ const uint32_t K[] = {
7, 12, 17, 22, 7, 12, 17, 22, 7, 12, 17, 22, 7, 12, 17, 22,
5, 9, 14, 20, 5, 9, 14, 20, 5, 9, 14, 20, 5, 9, 14, 20,
4, 11, 16, 23, 4, 11, 16, 23, 4, 11, 16, 23, 4, 11, 16, 23,
6, 10, 15, 21, 6, 10, 15, 21, 6, 10, 15, 21, 6, 10, 15, 21};
// leftrotate function definition
__device__ uint32_t leftrotate(uint32_t x, uint32_t C) {
return (((x) << (C)) | ((x) >> (32 - (C))));
}
__device__ void append_bytes(uint32_t val, uint8_t *outputs) {
outputs[0] = (uint8_t)val;
outputs[1] = (uint8_t)(val >> 8);
outputs[2] = (uint8_t)(val >> 16);
outputs[3] = (uint8_t)(val >> 24);
}
__device__ uint32_t append_int(const uint8_t *inputs) {
return (uint32_t)inputs[0] | ((uint32_t)inputs[1] << 8) |
((uint32_t)inputs[2] << 16) | ((uint32_t)inputs[3] << 24);
}
__device__ void md5(const uint8_t *orig_msg, size_t orig_len,
uint8_t *digest) {
// Use binary integer part of the sines of integers (Radians) as constants:
for (int i = 0; i < 64; i++) {
k[i] = (uint32_t)(abs(sin(i + 1.0)) * ((long long)1 << 32));
}
// Initialize variables:
uint32_t a0 = 0x67452301;
uint32_t b0 = 0xefcdab89;
uint32_t c0 = 0x98badcfe;
uint32_t d0 = 0x10325476;
size_t new_len, offset;
uint32_t M[16];
uint32_t A, B, C, D, F, g;
// append "0" bit until message length in bits ≡ 448 (mod 512)
for (new_len = orig_len + 1; new_len % (512 / 8) != 448 / 8; new_len++);
uint8_t *message = (uint8_t *)malloc(new_len + 8);
memcpy(message, orig_msg, orig_len);
// Pre-processing: adding a single 1 bit
message[orig_len] = 0x80;
// Pre-processing: padding with zeros
for (offset = orig_len + 1; offset < new_len; offset++){
message[offset] = 0;
}
// append length mod (2^64) to message
append_bytes(orig_len * 8, message + new_len);
// address the overflow part
append_bytes(orig_len >> 29, message + new_len + 4);
// Process the message in successive 512-bit chunks:
// for each 512-bit chunk of message:
for (offset = 0; offset < new_len; offset += (512 / 8)) {
// break chunk into sixteen 32-bit words w[j], 0 ≤ j ≤ 15
for (int i = 0; i < 16; i++) {
M[i] = append_int(message + offset + i * 4);
}
// Initialize hash value for this chunk:
A = a0;
B = b0;
C = c0;
D = d0;
// Main loop:
for (int i = 0; i < 64; i++) {
if (i < 16) {
F = (B & C) | ((~B) & D);
g = i;
} else if (i < 32) {
F = (D & B) | ((~D) & C);
g = (5 * i + 1) % 16;
} else if (i < 48) {
F = B ^ C ^ D;
g = (3 * i + 5) % 16;
} else {
F = C ^ (B | (~D));
g = (7 * i) % 16;
}
// Be wary of the below definitions of a,b,c,d
F = A + F + k[i] + M[g]; // M[g] must be a 32-bits block
A = D;
D = C;
C = B;
B = B + leftrotate(F, K[i]);
}
// Add this chunk's hash to result so far:
a0 += A;
b0 += B;
c0 += C;
d0 += D;
}
// cleanup
free(message);
// var char digest[16] := a0 append b0 append c0 append d0 //(Output is in
// little-endian)
append_bytes(a0, digest);
append_bytes(b0, digest + 4);
append_bytes(c0, digest + 8);
append_bytes(d0, digest + 12);
} | #include <hip/hip_runtime.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
__device__ uint32_t k[64] = {0};
// K specifies the per-round shift amounts
__device__ const uint32_t K[] = {
7, 12, 17, 22, 7, 12, 17, 22, 7, 12, 17, 22, 7, 12, 17, 22,
5, 9, 14, 20, 5, 9, 14, 20, 5, 9, 14, 20, 5, 9, 14, 20,
4, 11, 16, 23, 4, 11, 16, 23, 4, 11, 16, 23, 4, 11, 16, 23,
6, 10, 15, 21, 6, 10, 15, 21, 6, 10, 15, 21, 6, 10, 15, 21};
// leftrotate function definition
__device__ uint32_t leftrotate(uint32_t x, uint32_t C) {
return (((x) << (C)) | ((x) >> (32 - (C))));
}
__device__ void append_bytes(uint32_t val, uint8_t *outputs) {
outputs[0] = (uint8_t)val;
outputs[1] = (uint8_t)(val >> 8);
outputs[2] = (uint8_t)(val >> 16);
outputs[3] = (uint8_t)(val >> 24);
}
__device__ uint32_t append_int(const uint8_t *inputs) {
return (uint32_t)inputs[0] | ((uint32_t)inputs[1] << 8) |
((uint32_t)inputs[2] << 16) | ((uint32_t)inputs[3] << 24);
}
__device__ void md5(const uint8_t *orig_msg, size_t orig_len,
uint8_t *digest) {
// Use binary integer part of the sines of integers (Radians) as constants:
for (int i = 0; i < 64; i++) {
k[i] = (uint32_t)(abs(sin(i + 1.0)) * ((long long)1 << 32));
}
// Initialize variables:
uint32_t a0 = 0x67452301;
uint32_t b0 = 0xefcdab89;
uint32_t c0 = 0x98badcfe;
uint32_t d0 = 0x10325476;
size_t new_len, offset;
uint32_t M[16];
uint32_t A, B, C, D, F, g;
// append "0" bit until message length in bits ≡ 448 (mod 512)
for (new_len = orig_len + 1; new_len % (512 / 8) != 448 / 8; new_len++);
uint8_t *message = (uint8_t *)malloc(new_len + 8);
memcpy(message, orig_msg, orig_len);
// Pre-processing: adding a single 1 bit
message[orig_len] = 0x80;
// Pre-processing: padding with zeros
for (offset = orig_len + 1; offset < new_len; offset++){
message[offset] = 0;
}
// append length mod (2^64) to message
append_bytes(orig_len * 8, message + new_len);
// address the overflow part
append_bytes(orig_len >> 29, message + new_len + 4);
// Process the message in successive 512-bit chunks:
// for each 512-bit chunk of message:
for (offset = 0; offset < new_len; offset += (512 / 8)) {
// break chunk into sixteen 32-bit words w[j], 0 ≤ j ≤ 15
for (int i = 0; i < 16; i++) {
M[i] = append_int(message + offset + i * 4);
}
// Initialize hash value for this chunk:
A = a0;
B = b0;
C = c0;
D = d0;
// Main loop:
for (int i = 0; i < 64; i++) {
if (i < 16) {
F = (B & C) | ((~B) & D);
g = i;
} else if (i < 32) {
F = (D & B) | ((~D) & C);
g = (5 * i + 1) % 16;
} else if (i < 48) {
F = B ^ C ^ D;
g = (3 * i + 5) % 16;
} else {
F = C ^ (B | (~D));
g = (7 * i) % 16;
}
// Be wary of the below definitions of a,b,c,d
F = A + F + k[i] + M[g]; // M[g] must be a 32-bits block
A = D;
D = C;
C = B;
B = B + leftrotate(F, K[i]);
}
// Add this chunk's hash to result so far:
a0 += A;
b0 += B;
c0 += C;
d0 += D;
}
// cleanup
free(message);
// var char digest[16] := a0 append b0 append c0 append d0 //(Output is in
// little-endian)
append_bytes(a0, digest);
append_bytes(b0, digest + 4);
append_bytes(c0, digest + 8);
append_bytes(d0, digest + 12);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
__device__ uint32_t k[64] = {0};
// K specifies the per-round shift amounts
__device__ const uint32_t K[] = {
7, 12, 17, 22, 7, 12, 17, 22, 7, 12, 17, 22, 7, 12, 17, 22,
5, 9, 14, 20, 5, 9, 14, 20, 5, 9, 14, 20, 5, 9, 14, 20,
4, 11, 16, 23, 4, 11, 16, 23, 4, 11, 16, 23, 4, 11, 16, 23,
6, 10, 15, 21, 6, 10, 15, 21, 6, 10, 15, 21, 6, 10, 15, 21};
// leftrotate function definition
__device__ uint32_t leftrotate(uint32_t x, uint32_t C) {
return (((x) << (C)) | ((x) >> (32 - (C))));
}
__device__ void append_bytes(uint32_t val, uint8_t *outputs) {
outputs[0] = (uint8_t)val;
outputs[1] = (uint8_t)(val >> 8);
outputs[2] = (uint8_t)(val >> 16);
outputs[3] = (uint8_t)(val >> 24);
}
__device__ uint32_t append_int(const uint8_t *inputs) {
return (uint32_t)inputs[0] | ((uint32_t)inputs[1] << 8) |
((uint32_t)inputs[2] << 16) | ((uint32_t)inputs[3] << 24);
}
__device__ void md5(const uint8_t *orig_msg, size_t orig_len,
uint8_t *digest) {
// Use binary integer part of the sines of integers (Radians) as constants:
for (int i = 0; i < 64; i++) {
k[i] = (uint32_t)(abs(sin(i + 1.0)) * ((long long)1 << 32));
}
// Initialize variables:
uint32_t a0 = 0x67452301;
uint32_t b0 = 0xefcdab89;
uint32_t c0 = 0x98badcfe;
uint32_t d0 = 0x10325476;
size_t new_len, offset;
uint32_t M[16];
uint32_t A, B, C, D, F, g;
// append "0" bit until message length in bits ≡ 448 (mod 512)
for (new_len = orig_len + 1; new_len % (512 / 8) != 448 / 8; new_len++);
uint8_t *message = (uint8_t *)malloc(new_len + 8);
memcpy(message, orig_msg, orig_len);
// Pre-processing: adding a single 1 bit
message[orig_len] = 0x80;
// Pre-processing: padding with zeros
for (offset = orig_len + 1; offset < new_len; offset++){
message[offset] = 0;
}
// append length mod (2^64) to message
append_bytes(orig_len * 8, message + new_len);
// address the overflow part
append_bytes(orig_len >> 29, message + new_len + 4);
// Process the message in successive 512-bit chunks:
// for each 512-bit chunk of message:
for (offset = 0; offset < new_len; offset += (512 / 8)) {
// break chunk into sixteen 32-bit words w[j], 0 ≤ j ≤ 15
for (int i = 0; i < 16; i++) {
M[i] = append_int(message + offset + i * 4);
}
// Initialize hash value for this chunk:
A = a0;
B = b0;
C = c0;
D = d0;
// Main loop:
for (int i = 0; i < 64; i++) {
if (i < 16) {
F = (B & C) | ((~B) & D);
g = i;
} else if (i < 32) {
F = (D & B) | ((~D) & C);
g = (5 * i + 1) % 16;
} else if (i < 48) {
F = B ^ C ^ D;
g = (3 * i + 5) % 16;
} else {
F = C ^ (B | (~D));
g = (7 * i) % 16;
}
// Be wary of the below definitions of a,b,c,d
F = A + F + k[i] + M[g]; // M[g] must be a 32-bits block
A = D;
D = C;
C = B;
B = B + leftrotate(F, K[i]);
}
// Add this chunk's hash to result so far:
a0 += A;
b0 += B;
c0 += C;
d0 += D;
}
// cleanup
free(message);
// var char digest[16] := a0 append b0 append c0 append d0 //(Output is in
// little-endian)
append_bytes(a0, digest);
append_bytes(b0, digest + 4);
append_bytes(c0, digest + 8);
append_bytes(d0, digest + 12);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected k
.type k,@object
.section .bss,"aw",@nobits
.globl k
.p2align 4, 0x0
k:
.zero 256
.size k, 256
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym k
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
__device__ uint32_t k[64] = {0};
// K specifies the per-round shift amounts
__device__ const uint32_t K[] = {
7, 12, 17, 22, 7, 12, 17, 22, 7, 12, 17, 22, 7, 12, 17, 22,
5, 9, 14, 20, 5, 9, 14, 20, 5, 9, 14, 20, 5, 9, 14, 20,
4, 11, 16, 23, 4, 11, 16, 23, 4, 11, 16, 23, 4, 11, 16, 23,
6, 10, 15, 21, 6, 10, 15, 21, 6, 10, 15, 21, 6, 10, 15, 21};
// leftrotate function definition
__device__ uint32_t leftrotate(uint32_t x, uint32_t C) {
return (((x) << (C)) | ((x) >> (32 - (C))));
}
__device__ void append_bytes(uint32_t val, uint8_t *outputs) {
outputs[0] = (uint8_t)val;
outputs[1] = (uint8_t)(val >> 8);
outputs[2] = (uint8_t)(val >> 16);
outputs[3] = (uint8_t)(val >> 24);
}
__device__ uint32_t append_int(const uint8_t *inputs) {
return (uint32_t)inputs[0] | ((uint32_t)inputs[1] << 8) |
((uint32_t)inputs[2] << 16) | ((uint32_t)inputs[3] << 24);
}
__device__ void md5(const uint8_t *orig_msg, size_t orig_len,
uint8_t *digest) {
// Use binary integer part of the sines of integers (Radians) as constants:
for (int i = 0; i < 64; i++) {
k[i] = (uint32_t)(abs(sin(i + 1.0)) * ((long long)1 << 32));
}
// Initialize variables:
uint32_t a0 = 0x67452301;
uint32_t b0 = 0xefcdab89;
uint32_t c0 = 0x98badcfe;
uint32_t d0 = 0x10325476;
size_t new_len, offset;
uint32_t M[16];
uint32_t A, B, C, D, F, g;
// append "0" bit until message length in bits ≡ 448 (mod 512)
for (new_len = orig_len + 1; new_len % (512 / 8) != 448 / 8; new_len++);
uint8_t *message = (uint8_t *)malloc(new_len + 8);
memcpy(message, orig_msg, orig_len);
// Pre-processing: adding a single 1 bit
message[orig_len] = 0x80;
// Pre-processing: padding with zeros
for (offset = orig_len + 1; offset < new_len; offset++){
message[offset] = 0;
}
// append length mod (2^64) to message
append_bytes(orig_len * 8, message + new_len);
// address the overflow part
append_bytes(orig_len >> 29, message + new_len + 4);
// Process the message in successive 512-bit chunks:
// for each 512-bit chunk of message:
for (offset = 0; offset < new_len; offset += (512 / 8)) {
// break chunk into sixteen 32-bit words w[j], 0 ≤ j ≤ 15
for (int i = 0; i < 16; i++) {
M[i] = append_int(message + offset + i * 4);
}
// Initialize hash value for this chunk:
A = a0;
B = b0;
C = c0;
D = d0;
// Main loop:
for (int i = 0; i < 64; i++) {
if (i < 16) {
F = (B & C) | ((~B) & D);
g = i;
} else if (i < 32) {
F = (D & B) | ((~D) & C);
g = (5 * i + 1) % 16;
} else if (i < 48) {
F = B ^ C ^ D;
g = (3 * i + 5) % 16;
} else {
F = C ^ (B | (~D));
g = (7 * i) % 16;
}
// Be wary of the below definitions of a,b,c,d
F = A + F + k[i] + M[g]; // M[g] must be a 32-bits block
A = D;
D = C;
C = B;
B = B + leftrotate(F, K[i]);
}
// Add this chunk's hash to result so far:
a0 += A;
b0 += B;
c0 += C;
d0 += D;
}
// cleanup
free(message);
// var char digest[16] := a0 append b0 append c0 append d0 //(Output is in
// little-endian)
append_bytes(a0, digest);
append_bytes(b0, digest + 4);
append_bytes(c0, digest + 8);
append_bytes(d0, digest + 12);
} | .text
.file "hash.hip"
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB0_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB0_2:
movq __hip_gpubin_handle(%rip), %rdi
movl $k, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $256, %r9d # imm = 0x100
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end0:
.size __hip_module_ctor, .Lfunc_end0-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB1_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB1_2:
retq
.Lfunc_end1:
.size __hip_module_dtor, .Lfunc_end1-__hip_module_dtor
.cfi_endproc
# -- End function
.type k,@object # @k
.local k
.comm k,256,16
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "k"
.size .L__unnamed_1, 2
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym k
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected k
.type k,@object
.section .bss,"aw",@nobits
.globl k
.p2align 4, 0x0
k:
.zero 256
.size k, 256
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym k
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00028801_00000000-6_hash.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10leftrotatejj
.type _Z10leftrotatejj, @function
_Z10leftrotatejj:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z10leftrotatejj, .-_Z10leftrotatejj
.globl _Z12append_bytesjPh
.type _Z12append_bytesjPh, @function
_Z12append_bytesjPh:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z12append_bytesjPh, .-_Z12append_bytesjPh
.globl _Z10append_intPKh
.type _Z10append_intPKh, @function
_Z10append_intPKh:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z10append_intPKh, .-_Z10append_intPKh
.globl _Z3md5PKhmPh
.type _Z3md5PKhmPh, @function
_Z3md5PKhmPh:
.LFB2060:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size _Z3md5PKhmPh, .-_Z3md5PKhmPh
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "k"
.LC1:
.string "K"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $256, %r9d
movl $0, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1k(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $256, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1K(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata
.align 32
.type _ZL1K, @object
.size _ZL1K, 256
_ZL1K:
.long 7
.long 12
.long 17
.long 22
.long 7
.long 12
.long 17
.long 22
.long 7
.long 12
.long 17
.long 22
.long 7
.long 12
.long 17
.long 22
.long 5
.long 9
.long 14
.long 20
.long 5
.long 9
.long 14
.long 20
.long 5
.long 9
.long 14
.long 20
.long 5
.long 9
.long 14
.long 20
.long 4
.long 11
.long 16
.long 23
.long 4
.long 11
.long 16
.long 23
.long 4
.long 11
.long 16
.long 23
.long 4
.long 11
.long 16
.long 23
.long 6
.long 10
.long 15
.long 21
.long 6
.long 10
.long 15
.long 21
.long 6
.long 10
.long 15
.long 21
.long 6
.long 10
.long 15
.long 21
.local _ZL1k
.comm _ZL1k,256,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hash.hip"
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB0_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB0_2:
movq __hip_gpubin_handle(%rip), %rdi
movl $k, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $256, %r9d # imm = 0x100
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end0:
.size __hip_module_ctor, .Lfunc_end0-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB1_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB1_2:
retq
.Lfunc_end1:
.size __hip_module_dtor, .Lfunc_end1-__hip_module_dtor
.cfi_endproc
# -- End function
.type k,@object # @k
.local k
.comm k,256,16
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "k"
.size .L__unnamed_1, 2
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym k
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void convolve_gpu_kernel(float *input, float *weights, float *output, int in_w, int in_h, int in_c, int n, int size, int pad)
{
int index = blockIdx.x*blockDim.x + threadIdx.x;
int fil;
// filter index
//for (fil = 0; fil < n; ++fil)
int chan, y, x, f_y, f_x;
// channel index
//for (chan = 0; chan < in_c; ++chan)
// input - y
//for (y = 0; y < in_h; ++y)
// input - x
//for (x = 0; x < in_w; ++x)
x = index % in_w;
int index2 = index / in_w;
y = index2 % in_h;
fil = index2 / in_h;
if (fil < n)
{
int const output_index = fil*in_w*in_h + y*in_w + x;
float sum = 0;
for (chan = 0; chan < in_c; ++chan)
{
int const weights_pre_index = fil*in_c*size*size + chan*size*size;
int const input_pre_index = chan*in_w*in_h;
// filter - y
for (f_y = 0; f_y < size; ++f_y)
{
int input_y = y + f_y - pad;
// filter - x
for (f_x = 0; f_x < size; ++f_x)
{
int input_x = x + f_x - pad;
if (input_y < 0 || input_x < 0 || input_y >= in_h || input_x >= in_w) continue;
int input_index = input_pre_index + input_y*in_w + input_x;
int weights_index = weights_pre_index + f_y*size + f_x;
sum += input[input_index] * weights[weights_index];
}
}
// l.output[filters][width][height] +=
// state.input[channels][width][height] *
// l.weights[filters][channels][filter_width][filter_height];
//output[output_index] += sum;
}
output[output_index] = sum;
}
} | code for sm_80
Function : _Z19convolve_gpu_kernelPfS_S_iiiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R5, c[0x0][0x178] ; /* 0x00005e0000057a13 */
/* 0x000fe20000000000 */
/*0020*/ S2R R17, SR_CTAID.X ; /* 0x0000000000117919 */
/* 0x000e220000002500 */
/*0030*/ IABS R9, c[0x0][0x17c] ; /* 0x00005f0000097a13 */
/* 0x000fe40000000000 */
/*0040*/ I2F.RP R0, R5 ; /* 0x0000000500007306 */
/* 0x000e620000209400 */
/*0050*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e2e0000002100 */
/*0060*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x002e620000001000 */
/*0070*/ IMAD R17, R17, c[0x0][0x0], R4 ; /* 0x0000000011117a24 */
/* 0x001fce00078e0204 */
/*0080*/ I2F.RP R4, R9 ; /* 0x0000000900047306 */
/* 0x000e220000209400 */
/*0090*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x002fce0007ffe0ff */
/*00a0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x0002b0000021f000 */
/*00b0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e220000001000 */
/*00c0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x002fe400078e00ff */
/*00d0*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x004fc800078e0a03 */
/*00e0*/ IMAD R7, R6, R5, RZ ; /* 0x0000000506077224 */
/* 0x000fe200078e02ff */
/*00f0*/ IABS R6, R17 ; /* 0x0000001100067213 */
/* 0x000fc60000000000 */
/*0100*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*0110*/ IMAD.HI.U32 R0, R3, R6, RZ ; /* 0x0000000603007227 */
/* 0x000fe200078e00ff */
/*0120*/ IADD3 R3, R4, 0xffffffe, RZ ; /* 0x0ffffffe04037810 */
/* 0x001fc60007ffe0ff */
/*0130*/ IMAD.MOV R2, RZ, RZ, -R0 ; /* 0x000000ffff027224 */
/* 0x000fc600078e0a00 */
/*0140*/ F2I.FTZ.U32.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e22000021f000 */
/*0150*/ IMAD R2, R5, R2, R6 ; /* 0x0000000205027224 */
/* 0x000fca00078e0206 */
/*0160*/ ISETP.GT.U32.AND P1, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x000fda0003f24070 */
/*0170*/ @!P1 IMAD.IADD R2, R2, 0x1, -R5 ; /* 0x0000000102029824 */
/* 0x000fe200078e0a05 */
/*0180*/ @!P1 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100009810 */
/* 0x000fe40007ffe0ff */
/*0190*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe40003f25270 */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x000fe40003f06070 */
/*01b0*/ LOP3.LUT R2, R17, c[0x0][0x178], RZ, 0x3c, !PT ; /* 0x00005e0011027a12 */
/* 0x000fc800078e3cff */
/*01c0*/ ISETP.GE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f46270 */
/*01d0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fcc00078e00ff */
/*01e0*/ @P0 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100000810 */
/* 0x000fca0007ffe0ff */
/*01f0*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0000 */
/*0200*/ IMAD.MOV R0, RZ, RZ, -R3 ; /* 0x000000ffff007224 */
/* 0x001fe400078e0a03 */
/*0210*/ @!P2 IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff07a224 */
/* 0x000fe200078e0a07 */
/*0220*/ @!P1 LOP3.LUT R7, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff079a12 */
/* 0x000fe200078e33ff */
/*0230*/ IMAD R5, R0, R9, RZ ; /* 0x0000000900057224 */
/* 0x000fc600078e02ff */
/*0240*/ IABS R0, R7 ; /* 0x0000000700007213 */
/* 0x000fe20000000000 */
/*0250*/ IMAD.HI.U32 R2, R3, R5, R2 ; /* 0x0000000503027227 */
/* 0x000fcc00078e0002 */
/*0260*/ IMAD.HI.U32 R18, R2, R0, RZ ; /* 0x0000000002127227 */
/* 0x000fc800078e00ff */
/*0270*/ IMAD.MOV R2, RZ, RZ, -R18 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0a12 */
/*0280*/ IMAD R0, R9, R2, R0 ; /* 0x0000000209007224 */
/* 0x000fca00078e0200 */
/*0290*/ ISETP.GT.U32.AND P1, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fda0003f24070 */
/*02a0*/ @!P1 IMAD.IADD R0, R0, 0x1, -R9 ; /* 0x0000000100009824 */
/* 0x000fe200078e0a09 */
/*02b0*/ @!P1 IADD3 R18, R18, 0x1, RZ ; /* 0x0000000112129810 */
/* 0x000fe40007ffe0ff */
/*02c0*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fe40003f25270 */
/*02d0*/ ISETP.GE.U32.AND P0, PT, R0, R9, PT ; /* 0x000000090000720c */
/* 0x000fe40003f06070 */
/*02e0*/ LOP3.LUT R0, R7, c[0x0][0x17c], RZ, 0x3c, !PT ; /* 0x00005f0007007a12 */
/* 0x000fc800078e3cff */
/*02f0*/ ISETP.GE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fce0003f46270 */
/*0300*/ @P0 IADD3 R18, R18, 0x1, RZ ; /* 0x0000000112120810 */
/* 0x000fcc0007ffe0ff */
/*0310*/ @!P2 IMAD.MOV R18, RZ, RZ, -R18 ; /* 0x000000ffff12a224 */
/* 0x000fe200078e0a12 */
/*0320*/ @!P1 LOP3.LUT R18, RZ, c[0x0][0x17c], RZ, 0x33, !PT ; /* 0x00005f00ff129a12 */
/* 0x000fc800078e33ff */
/*0330*/ ISETP.GE.AND P0, PT, R18, c[0x0][0x184], PT ; /* 0x0000610012007a0c */
/* 0x000fda0003f06270 */
/*0340*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0350*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff027624 */
/* 0x000fe200078e00ff */
/*0360*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0370*/ IMAD.MOV R0, RZ, RZ, -R7 ; /* 0x000000ffff007224 */
/* 0x000fe400078e0a07 */
/*0380*/ IMAD.MOV R16, RZ, RZ, -R18 ; /* 0x000000ffff107224 */
/* 0x000fe200078e0a12 */
/*0390*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f06270 */
/*03a0*/ IMAD R17, R0, c[0x0][0x178], R17 ; /* 0x00005e0000117a24 */
/* 0x000fe400078e0211 */
/*03b0*/ IMAD R16, R16, c[0x0][0x17c], R7 ; /* 0x00005f0010107a24 */
/* 0x000fe400078e0207 */
/*03c0*/ IMAD.MOV.U32 R15, RZ, RZ, RZ ; /* 0x000000ffff0f7224 */
/* 0x000fd000078e00ff */
/*03d0*/ @!P0 BRA 0xb70 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*03e0*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff0e7624 */
/* 0x000fca00078e00ff */
/*03f0*/ ISETP.GE.AND P0, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fda0003f06270 */
/*0400*/ @!P0 BRA 0xb70 ; /* 0x0000076000008947 */
/* 0x000fea0003800000 */
/*0410*/ IADD3 R20, R14.reuse, -0x1, RZ ; /* 0xffffffff0e147810 */
/* 0x040fe20007ffe0ff */
/*0420*/ IMAD.MOV.U32 R15, RZ, RZ, RZ ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e00ff */
/*0430*/ LOP3.LUT R14, R14, 0x3, RZ, 0xc0, !PT ; /* 0x000000030e0e7812 */
/* 0x000fe200078ec0ff */
/*0440*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*0450*/ IADD3 R10, R17.reuse, 0x3, RZ ; /* 0x00000003110a7810 */
/* 0x040fe40007ffe0ff */
/*0460*/ IADD3 R12, R17, -c[0x0][0x18c], RZ ; /* 0x80006300110c7a10 */
/* 0x000fe40007ffe0ff */
/*0470*/ IADD3 R13, R16, -c[0x0][0x18c], RZ ; /* 0x80006300100d7a10 */
/* 0x000fe40007ffe0ff */
/*0480*/ IADD3 R10, R10, -c[0x0][0x18c], RZ ; /* 0x800063000a0a7a10 */
/* 0x000fc40007ffe0ff */
/*0490*/ IADD3 R8, R14, -c[0x0][0x188], RZ ; /* 0x800062000e087a10 */
/* 0x000fe40007ffe0ff */
/*04a0*/ IMAD.MOV.U32 R9, RZ, RZ, R11.reuse ; /* 0x000000ffff097224 */
/* 0x100fe400078e000b */
/*04b0*/ IMAD R7, R18, c[0x0][0x180], R11 ; /* 0x0000600012077a24 */
/* 0x000fe200078e020b */
/*04c0*/ IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b7810 */
/* 0x000fe20007ffe0ff */
/*04d0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fc600078e00ff */
/*04e0*/ ISETP.GE.AND P2, PT, R11, c[0x0][0x180], PT ; /* 0x000060000b007a0c */
/* 0x000fe40003f46270 */
/*04f0*/ ISETP.GE.U32.AND P0, PT, R20, 0x3, PT ; /* 0x000000031400780c */
/* 0x000fe20003f06070 */
/*0500*/ IMAD R21, R7, c[0x0][0x188], R6.reuse ; /* 0x0000620007157a24 */
/* 0x100fe200078e0206 */
/*0510*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0520*/ IMAD.IADD R0, R13, 0x1, R6 ; /* 0x000000010d007824 */
/* 0x000fe200078e0206 */
/*0530*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fe20007ffe0ff */
/*0540*/ IMAD R21, R21, c[0x0][0x188], RZ ; /* 0x0000620015157a24 */
/* 0x000fe200078e02ff */
/*0550*/ ISETP.NE.AND P3, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe20003f65270 */
/*0560*/ IMAD R19, R9, c[0x0][0x17c], R0 ; /* 0x00005f0009137a24 */
/* 0x000fe200078e0200 */
/*0570*/ ISETP.GE.AND P1, PT, R6, c[0x0][0x188], PT ; /* 0x0000620006007a0c */
/* 0x000fca0003f26270 */
/*0580*/ @!P0 BRA 0x8c0 ; /* 0x0000033000008947 */
/* 0x000fec0003800000 */
/*0590*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*05a0*/ ISETP.GE.AND P4, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fe20003f86270 */
/*05b0*/ IMAD R2, R19, c[0x0][0x178], R12 ; /* 0x00005e0013027a24 */
/* 0x000fe200078e020c */
/*05c0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*05d0*/ IMAD.MOV.U32 R23, RZ, RZ, R8 ; /* 0x000000ffff177224 */
/* 0x000fe200078e0008 */
/*05e0*/ ULDC.64 UR8, c[0x0][0x168] ; /* 0x00005a0000087ab9 */
/* 0x000fe20000000a00 */
/*05f0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc800078e0203 */
/*0600*/ IMAD.MOV.U32 R22, RZ, RZ, R2 ; /* 0x000000ffff167224 */
/* 0x000fe400078e0002 */
/*0610*/ IMAD.MOV.U32 R27, RZ, RZ, R3 ; /* 0x000000ffff1b7224 */
/* 0x000fe400078e0003 */
/*0620*/ IMAD.MOV.U32 R25, RZ, RZ, R10 ; /* 0x000000ffff197224 */
/* 0x000fca00078e000a */
/*0630*/ IADD3 R3, R25.reuse, -0x3, RZ ; /* 0xfffffffd19037810 */
/* 0x040fe40007ffe0ff */
/*0640*/ IADD3 R5, R25, -0x2, RZ ; /* 0xfffffffe19057810 */
/* 0x000fe40007ffe0ff */
/*0650*/ LOP3.LUT R2, R3, R0.reuse, RZ, 0xfc, !PT ; /* 0x0000000003027212 */
/* 0x080fe400078efcff */
/*0660*/ LOP3.LUT R4, R5, R0, RZ, 0xfc, !PT ; /* 0x0000000005047212 */
/* 0x000fc400078efcff */
/*0670*/ ISETP.LT.OR P0, PT, R2, RZ, P4 ; /* 0x000000ff0200720c */
/* 0x000fe20002701670 */
/*0680*/ IMAD.U32 R2, RZ, RZ, UR8 ; /* 0x00000008ff027e24 */
/* 0x000fe2000f8e00ff */
/*0690*/ ISETP.LT.OR P5, PT, R4, RZ, P4 ; /* 0x000000ff0400720c */
/* 0x000fe200027a1670 */
/*06a0*/ IMAD.MOV.U32 R4, RZ, RZ, R22 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0016 */
/*06b0*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fe20000706670 */
/*06c0*/ IMAD.U32 R3, RZ, RZ, UR9 ; /* 0x00000009ff037e24 */
/* 0x000fe2000f8e00ff */
/*06d0*/ ISETP.GE.OR P5, PT, R5, c[0x0][0x178], P5 ; /* 0x00005e0005007a0c */
/* 0x000fe20002fa6670 */
/*06e0*/ IMAD.MOV.U32 R5, RZ, RZ, R27 ; /* 0x000000ffff057224 */
/* 0x000fe400078e001b */
/*06f0*/ IMAD.WIDE R2, R21, 0x4, R2 ; /* 0x0000000415027825 */
/* 0x000fd000078e0202 */
/*0700*/ @!P0 LDG.E R24, [R2.64] ; /* 0x0000000602188981 */
/* 0x000ea8000c1e1900 */
/*0710*/ @!P0 LDG.E R22, [R4.64] ; /* 0x0000000604168981 */
/* 0x000ea8000c1e1900 */
/*0720*/ @!P5 LDG.E R26, [R2.64+0x4] ; /* 0x00000406021ad981 */
/* 0x000ee8000c1e1900 */
/*0730*/ @!P5 LDG.E R27, [R4.64+0x4] ; /* 0x00000406041bd981 */
/* 0x000ee2000c1e1900 */
/*0740*/ IADD3 R29, R25, -0x1, RZ ; /* 0xffffffff191d7810 */
/* 0x000fe20007ffe0ff */
/*0750*/ @!P0 FFMA R15, R22, R24, R15 ; /* 0x00000018160f8223 */
/* 0x004fc6000000000f */
/*0760*/ LOP3.LUT R22, R29, R0, RZ, 0xfc, !PT ; /* 0x000000001d167212 */
/* 0x000fc800078efcff */
/*0770*/ ISETP.LT.OR P0, PT, R22, RZ, P4 ; /* 0x000000ff1600720c */
/* 0x000fe40002701670 */
/*0780*/ LOP3.LUT R22, R25, R0, RZ, 0xfc, !PT ; /* 0x0000000019167212 */
/* 0x000fe200078efcff */
/*0790*/ @!P5 FFMA R15, R26, R27, R15 ; /* 0x0000001b1a0fd223 */
/* 0x008fe2000000000f */
/*07a0*/ ISETP.GE.OR P5, PT, R29, c[0x0][0x178], P0 ; /* 0x00005e001d007a0c */
/* 0x000fe400007a6670 */
/*07b0*/ ISETP.LT.OR P0, PT, R22, RZ, P4 ; /* 0x000000ff1600720c */
/* 0x000fc80002701670 */
/*07c0*/ ISETP.GE.OR P0, PT, R25, c[0x0][0x178], P0 ; /* 0x00005e0019007a0c */
/* 0x000fce0000706670 */
/*07d0*/ @!P5 LDG.E R22, [R2.64+0x8] ; /* 0x000008060216d981 */
/* 0x000ea8000c1e1900 */
/*07e0*/ @!P5 LDG.E R24, [R4.64+0x8] ; /* 0x000008060418d981 */
/* 0x000ea8000c1e1900 */
/*07f0*/ @!P0 LDG.E R26, [R2.64+0xc] ; /* 0x00000c06021a8981 */
/* 0x000ee8000c1e1900 */
/*0800*/ @!P0 LDG.E R28, [R4.64+0xc] ; /* 0x00000c06041c8981 */
/* 0x000ee2000c1e1900 */
/*0810*/ IADD3 R23, R23, 0x4, RZ ; /* 0x0000000417177810 */
/* 0x000fe20007ffe0ff */
/*0820*/ UIADD3 UR8, UP0, UR8, 0x10, URZ ; /* 0x0000001008087890 */
/* 0x000fe2000ff1e03f */
/*0830*/ IADD3 R25, R25, 0x4, RZ ; /* 0x0000000419197810 */
/* 0x000fe20007ffe0ff */
/*0840*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0850*/ ISETP.NE.AND P6, PT, R23, RZ, PT ; /* 0x000000ff1700720c */
/* 0x000fe20003fc5270 */
/*0860*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe200087fe43f */
/*0870*/ @!P5 FFMA R15, R22, R24, R15 ; /* 0x00000018160fd223 */
/* 0x004fe2000000000f */
/*0880*/ IADD3 R22, P5, R4, 0x10, RZ ; /* 0x0000001004167810 */
/* 0x000fca0007fbe0ff */
/*0890*/ IMAD.X R27, RZ, RZ, R5, P5 ; /* 0x000000ffff1b7224 */
/* 0x000fe400028e0605 */
/*08a0*/ @!P0 FFMA R15, R26, R28, R15 ; /* 0x0000001c1a0f8223 */
/* 0x008fc6000000000f */
/*08b0*/ @P6 BRA 0x630 ; /* 0xfffffd7000006947 */
/* 0x000fea000383ffff */
/*08c0*/ @!P3 BRA 0xb50 ; /* 0x000002800000b947 */
/* 0x000fea0003800000 */
/*08d0*/ IADD3 R22, R12, UR4, RZ ; /* 0x000000040c167c10 */
/* 0x000fe2000fffe0ff */
/*08e0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*08f0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fe20003f06270 */
/*0900*/ BSSY B0, 0x9e0 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*0910*/ LOP3.LUT R2, R22, R0, RZ, 0xfc, !PT ; /* 0x0000000016027212 */
/* 0x000fe200078efcff */
/*0920*/ IMAD R4, R19, c[0x0][0x178], R22 ; /* 0x00005e0013047a24 */
/* 0x000fe200078e0216 */
/*0930*/ ISETP.NE.AND P4, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fe40003f85270 */
/*0940*/ ISETP.LT.OR P3, PT, R2, RZ, P0 ; /* 0x000000ff0200720c */
/* 0x000fe40000761670 */
/*0950*/ IADD3 R2, R21, UR4, RZ ; /* 0x0000000415027c10 */
/* 0x000fc4000fffe0ff */
/*0960*/ ISETP.GE.OR P3, PT, R22, c[0x0][0x178], P3 ; /* 0x00005e0016007a0c */
/* 0x000fc60001f66670 */
/*0970*/ IMAD.WIDE R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fc800078e0205 */
/*0980*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fcc00078e0205 */
/*0990*/ @P3 BRA 0x9d0 ; /* 0x0000003000003947 */
/* 0x000fea0003800000 */
/*09a0*/ LDG.E R24, [R4.64] ; /* 0x0000000604187981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ LDG.E R19, [R2.64] ; /* 0x0000000602137981 */
/* 0x000ea4000c1e1900 */
/*09c0*/ FFMA R15, R24, R19, R15 ; /* 0x00000013180f7223 */
/* 0x004fe4000000000f */
/*09d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*09e0*/ @!P4 BRA 0xb50 ; /* 0x000001600000c947 */
/* 0x000fea0003800000 */
/*09f0*/ IADD3 R19, R22, 0x1, RZ ; /* 0x0000000116137810 */
/* 0x000fe20007ffe0ff */
/*0a00*/ BSSY B0, 0xaa0 ; /* 0x0000009000007945 */
/* 0x000fe20003800000 */
/*0a10*/ ISETP.NE.AND P4, PT, R14, 0x2, PT ; /* 0x000000020e00780c */
/* 0x000fe40003f85270 */
/*0a20*/ LOP3.LUT R21, R19, R0, RZ, 0xfc, !PT ; /* 0x0000000013157212 */
/* 0x000fc800078efcff */
/*0a30*/ ISETP.LT.OR P3, PT, R21, RZ, P0 ; /* 0x000000ff1500720c */
/* 0x000fc80000761670 */
/*0a40*/ ISETP.GE.OR P3, PT, R19, c[0x0][0x178], P3 ; /* 0x00005e0013007a0c */
/* 0x000fda0001f66670 */
/*0a50*/ @P3 BRA 0xa90 ; /* 0x0000003000003947 */
/* 0x000fea0003800000 */
/*0a60*/ LDG.E R24, [R2.64+0x4] ; /* 0x0000040602187981 */
/* 0x000ea8000c1e1900 */
/*0a70*/ LDG.E R19, [R4.64+0x4] ; /* 0x0000040604137981 */
/* 0x000ea4000c1e1900 */
/*0a80*/ FFMA R15, R24, R19, R15 ; /* 0x00000013180f7223 */
/* 0x004fe4000000000f */
/*0a90*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0aa0*/ @!P4 BRA 0xb50 ; /* 0x000000a00000c947 */
/* 0x000fea0003800000 */
/*0ab0*/ IADD3 R19, R22, 0x2, RZ ; /* 0x0000000216137810 */
/* 0x000fe20007ffe0ff */
/*0ac0*/ BSSY B0, 0xb50 ; /* 0x0000008000007945 */
/* 0x000fe60003800000 */
/*0ad0*/ LOP3.LUT R0, R19, R0, RZ, 0xfc, !PT ; /* 0x0000000013007212 */
/* 0x000fc800078efcff */
/*0ae0*/ ISETP.LT.OR P0, PT, R0, RZ, P0 ; /* 0x000000ff0000720c */
/* 0x000fc80000701670 */
/*0af0*/ ISETP.GE.OR P0, PT, R19, c[0x0][0x178], P0 ; /* 0x00005e0013007a0c */
/* 0x000fda0000706670 */
/*0b00*/ @P0 BRA 0xb40 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0b10*/ LDG.E R2, [R2.64+0x8] ; /* 0x0000080602027981 */
/* 0x000ea8000c1e1900 */
/*0b20*/ LDG.E R4, [R4.64+0x8] ; /* 0x0000080604047981 */
/* 0x000ea4000c1e1900 */
/*0b30*/ FFMA R15, R2, R4, R15 ; /* 0x00000004020f7223 */
/* 0x004fe4000000000f */
/*0b40*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0b50*/ @!P1 BRA 0x4f0 ; /* 0xfffff99000009947 */
/* 0x000fea000383ffff */
/*0b60*/ @!P2 BRA 0x4a0 ; /* 0xfffff9300000a947 */
/* 0x000fea000383ffff */
/*0b70*/ IMAD R16, R18, c[0x0][0x17c], R16 ; /* 0x00005f0012107a24 */
/* 0x000fe400078e0210 */
/*0b80*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*0b90*/ IMAD R2, R16, c[0x0][0x178], R17 ; /* 0x00005e0010027a24 */
/* 0x000fc800078e0211 */
/*0ba0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0bb0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x000fe2000c101906 */
/*0bc0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0bd0*/ BRA 0xbd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void convolve_gpu_kernel(float *input, float *weights, float *output, int in_w, int in_h, int in_c, int n, int size, int pad)
{
int index = blockIdx.x*blockDim.x + threadIdx.x;
int fil;
// filter index
//for (fil = 0; fil < n; ++fil)
int chan, y, x, f_y, f_x;
// channel index
//for (chan = 0; chan < in_c; ++chan)
// input - y
//for (y = 0; y < in_h; ++y)
// input - x
//for (x = 0; x < in_w; ++x)
x = index % in_w;
int index2 = index / in_w;
y = index2 % in_h;
fil = index2 / in_h;
if (fil < n)
{
int const output_index = fil*in_w*in_h + y*in_w + x;
float sum = 0;
for (chan = 0; chan < in_c; ++chan)
{
int const weights_pre_index = fil*in_c*size*size + chan*size*size;
int const input_pre_index = chan*in_w*in_h;
// filter - y
for (f_y = 0; f_y < size; ++f_y)
{
int input_y = y + f_y - pad;
// filter - x
for (f_x = 0; f_x < size; ++f_x)
{
int input_x = x + f_x - pad;
if (input_y < 0 || input_x < 0 || input_y >= in_h || input_x >= in_w) continue;
int input_index = input_pre_index + input_y*in_w + input_x;
int weights_index = weights_pre_index + f_y*size + f_x;
sum += input[input_index] * weights[weights_index];
}
}
// l.output[filters][width][height] +=
// state.input[channels][width][height] *
// l.weights[filters][channels][filter_width][filter_height];
//output[output_index] += sum;
}
output[output_index] = sum;
}
} | .file "tmpxft_000b0c02_00000000-6_convolve_gpu_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z19convolve_gpu_kernelPfS_S_iiiiiiPfS_S_iiiiii
.type _Z49__device_stub__Z19convolve_gpu_kernelPfS_S_iiiiiiPfS_S_iiiiii, @function
_Z49__device_stub__Z19convolve_gpu_kernelPfS_S_iiiiiiPfS_S_iiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z19convolve_gpu_kernelPfS_S_iiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z19convolve_gpu_kernelPfS_S_iiiiiiPfS_S_iiiiii, .-_Z49__device_stub__Z19convolve_gpu_kernelPfS_S_iiiiiiPfS_S_iiiiii
.globl _Z19convolve_gpu_kernelPfS_S_iiiiii
.type _Z19convolve_gpu_kernelPfS_S_iiiiii, @function
_Z19convolve_gpu_kernelPfS_S_iiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z49__device_stub__Z19convolve_gpu_kernelPfS_S_iiiiiiPfS_S_iiiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19convolve_gpu_kernelPfS_S_iiiiii, .-_Z19convolve_gpu_kernelPfS_S_iiiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19convolve_gpu_kernelPfS_S_iiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19convolve_gpu_kernelPfS_S_iiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void convolve_gpu_kernel(float *input, float *weights, float *output, int in_w, int in_h, int in_c, int n, int size, int pad)
{
int index = blockIdx.x*blockDim.x + threadIdx.x;
int fil;
// filter index
//for (fil = 0; fil < n; ++fil)
int chan, y, x, f_y, f_x;
// channel index
//for (chan = 0; chan < in_c; ++chan)
// input - y
//for (y = 0; y < in_h; ++y)
// input - x
//for (x = 0; x < in_w; ++x)
x = index % in_w;
int index2 = index / in_w;
y = index2 % in_h;
fil = index2 / in_h;
if (fil < n)
{
int const output_index = fil*in_w*in_h + y*in_w + x;
float sum = 0;
for (chan = 0; chan < in_c; ++chan)
{
int const weights_pre_index = fil*in_c*size*size + chan*size*size;
int const input_pre_index = chan*in_w*in_h;
// filter - y
for (f_y = 0; f_y < size; ++f_y)
{
int input_y = y + f_y - pad;
// filter - x
for (f_x = 0; f_x < size; ++f_x)
{
int input_x = x + f_x - pad;
if (input_y < 0 || input_x < 0 || input_y >= in_h || input_x >= in_w) continue;
int input_index = input_pre_index + input_y*in_w + input_x;
int weights_index = weights_pre_index + f_y*size + f_x;
sum += input[input_index] * weights[weights_index];
}
}
// l.output[filters][width][height] +=
// state.input[channels][width][height] *
// l.weights[filters][channels][filter_width][filter_height];
//output[output_index] += sum;
}
output[output_index] = sum;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void convolve_gpu_kernel(float *input, float *weights, float *output, int in_w, int in_h, int in_c, int n, int size, int pad)
{
int index = blockIdx.x*blockDim.x + threadIdx.x;
int fil;
// filter index
//for (fil = 0; fil < n; ++fil)
int chan, y, x, f_y, f_x;
// channel index
//for (chan = 0; chan < in_c; ++chan)
// input - y
//for (y = 0; y < in_h; ++y)
// input - x
//for (x = 0; x < in_w; ++x)
x = index % in_w;
int index2 = index / in_w;
y = index2 % in_h;
fil = index2 / in_h;
if (fil < n)
{
int const output_index = fil*in_w*in_h + y*in_w + x;
float sum = 0;
for (chan = 0; chan < in_c; ++chan)
{
int const weights_pre_index = fil*in_c*size*size + chan*size*size;
int const input_pre_index = chan*in_w*in_h;
// filter - y
for (f_y = 0; f_y < size; ++f_y)
{
int input_y = y + f_y - pad;
// filter - x
for (f_x = 0; f_x < size; ++f_x)
{
int input_x = x + f_x - pad;
if (input_y < 0 || input_x < 0 || input_y >= in_h || input_x >= in_w) continue;
int input_index = input_pre_index + input_y*in_w + input_x;
int weights_index = weights_pre_index + f_y*size + f_x;
sum += input[input_index] * weights[weights_index];
}
}
// l.output[filters][width][height] +=
// state.input[channels][width][height] *
// l.weights[filters][channels][filter_width][filter_height];
//output[output_index] += sum;
}
output[output_index] = sum;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void convolve_gpu_kernel(float *input, float *weights, float *output, int in_w, int in_h, int in_c, int n, int size, int pad)
{
int index = blockIdx.x*blockDim.x + threadIdx.x;
int fil;
// filter index
//for (fil = 0; fil < n; ++fil)
int chan, y, x, f_y, f_x;
// channel index
//for (chan = 0; chan < in_c; ++chan)
// input - y
//for (y = 0; y < in_h; ++y)
// input - x
//for (x = 0; x < in_w; ++x)
x = index % in_w;
int index2 = index / in_w;
y = index2 % in_h;
fil = index2 / in_h;
if (fil < n)
{
int const output_index = fil*in_w*in_h + y*in_w + x;
float sum = 0;
for (chan = 0; chan < in_c; ++chan)
{
int const weights_pre_index = fil*in_c*size*size + chan*size*size;
int const input_pre_index = chan*in_w*in_h;
// filter - y
for (f_y = 0; f_y < size; ++f_y)
{
int input_y = y + f_y - pad;
// filter - x
for (f_x = 0; f_x < size; ++f_x)
{
int input_x = x + f_x - pad;
if (input_y < 0 || input_x < 0 || input_y >= in_h || input_x >= in_w) continue;
int input_index = input_pre_index + input_y*in_w + input_x;
int weights_index = weights_pre_index + f_y*size + f_x;
sum += input[input_index] * weights[weights_index];
}
}
// l.output[filters][width][height] +=
// state.input[channels][width][height] *
// l.weights[filters][channels][filter_width][filter_height];
//output[output_index] += sum;
}
output[output_index] = sum;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19convolve_gpu_kernelPfS_S_iiiiii
.globl _Z19convolve_gpu_kernelPfS_S_iiiiii
.p2align 8
.type _Z19convolve_gpu_kernelPfS_S_iiiiii,@function
_Z19convolve_gpu_kernelPfS_S_iiiiii:
s_clause 0x2
s_load_b64 s[8:9], s[0:1], 0x18
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x3c
s_waitcnt lgkmcnt(0)
s_ashr_i32 s4, s8, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s5, s8, s4
s_and_b32 s3, s3, 0xffff
s_xor_b32 s5, s5, s4
v_cvt_f32_u32_e32 v1, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s3, v[0:1]
s_sub_i32 s3, 0, s5
v_mul_lo_u32 v0, s3, v1
s_ashr_i32 s3, s9, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_add_i32 s6, s9, s3
v_ashrrev_i32_e32 v3, 31, v2
s_xor_b32 s6, s6, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f32_u32_e32 v5, s6
v_mul_hi_u32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v4, v2, v3
v_rcp_iflag_f32_e32 v5, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_xor_b32_e32 v4, v4, v3
v_xor_b32_e32 v3, s4, v3
v_add_nc_u32_e32 v0, v1, v0
s_sub_i32 s4, 0, s6
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v5, 0x4f7ffffe, v5
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v0, s5
v_sub_nc_u32_e32 v1, v4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v6, s5, v1
v_cmp_le_u32_e32 vcc_lo, s5, v1
v_dual_cndmask_b32 v1, v1, v6 :: v_dual_add_nc_u32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, 1, v0
v_cvt_u32_f32_e32 v1, v5
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v4, s4, v1
v_xor_b32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v4, v1, v4
v_sub_nc_u32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v3, 31, v0
v_add_nc_u32_e32 v1, v1, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, v0, v3
v_xor_b32_e32 v4, v5, v3
v_xor_b32_e32 v3, s3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v1, v4, v1
v_mul_lo_u32 v5, v1, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v4, v4, v5
v_add_nc_u32_e32 v5, 1, v1
v_subrev_nc_u32_e32 v6, s6, v4
v_cmp_le_u32_e32 vcc_lo, s6, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v4, v4, v6 :: v_dual_cndmask_b32 v1, v1, v5
v_cmp_le_u32_e32 vcc_lo, s6, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, 1, v1
v_cndmask_b32_e32 v1, v1, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v1, v1, v3
v_sub_nc_u32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v3
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_13
s_load_b32 s12, s[0:1], 0x20
v_mul_lo_u32 v1, v3, s9
v_mul_lo_u32 v4, v0, s8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v1, v0, v1
v_sub_nc_u32_e32 v0, v2, v4
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s12, 1
s_cbranch_scc1 .LBB0_11
s_clause 0x1
s_load_b64 s[10:11], s[0:1], 0x28
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s14, 0
s_mul_i32 s15, s9, s8
s_waitcnt lgkmcnt(0)
s_mov_b32 s2, s11
s_mul_i32 s13, s10, s10
v_mad_u64_u32 v[4:5], null, s9, v3, s[2:3]
s_mul_i32 s2, s13, s12
v_subrev_nc_u32_e32 v5, s11, v0
v_mul_lo_u32 v6, s2, v3
s_cmp_gt_i32 s10, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, 0, v4
v_mad_u64_u32 v[7:8], null, s8, v4, v[2:3]
v_mov_b32_e32 v2, 0
v_subrev_nc_u32_e32 v4, s11, v1
s_delay_alu instid0(VALU_DEP_3)
v_subrev_nc_u32_e32 v7, s11, v7
s_cselect_b32 s11, -1, 0
s_branch .LBB0_4
.LBB0_3:
s_set_inst_prefetch_distance 0x2
v_add_nc_u32_e32 v6, s13, v6
v_add_nc_u32_e32 v7, s15, v7
s_add_i32 s14, s14, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s14, s12
s_cbranch_scc0 .LBB0_12
.LBB0_4:
s_and_not1_b32 vcc_lo, exec_lo, s11
s_cbranch_vccnz .LBB0_3
v_dual_mov_b32 v8, v7 :: v_dual_mov_b32 v9, v6
s_mov_b32 s16, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_7
.p2align 6
.LBB0_6:
v_add_nc_u32_e32 v9, s10, v9
v_add_nc_u32_e32 v8, s8, v8
s_add_i32 s16, s16, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s16, s10
s_cbranch_scc0 .LBB0_3
.LBB0_7:
v_add_nc_u32_e32 v10, s16, v4
s_mov_b32 s17, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s9, v10
s_branch .LBB0_9
.p2align 6
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s3
s_add_i32 s17, s17, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s10, s17
s_cbranch_scc0 .LBB0_6
.LBB0_9:
v_add_nc_u32_e32 v11, s17, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_or_b32_e32 v12, v10, v11
v_cmp_gt_i32_e64 s3, s8, v11
v_cmp_lt_i32_e64 s2, -1, v12
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_8
v_add_nc_u32_e32 v11, s17, v8
v_add_nc_u32_e32 v13, s17, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v12, 31, v11
v_ashrrev_i32_e32 v14, 31, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_lshlrev_b64 v[13:14], 2, v[13:14]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v11, s2, s4, v11
v_add_co_ci_u32_e64 v12, s2, s5, v12, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v13, s2, s6, v13
v_add_co_ci_u32_e64 v14, s2, s7, v14, s2
global_load_b32 v11, v[11:12], off
global_load_b32 v12, v[13:14], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v2, v11, v12
s_branch .LBB0_8
.LBB0_11:
v_mov_b32_e32 v2, 0
.LBB0_12:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v3, s9, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[5:6], null, v4, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[0:1], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19convolve_gpu_kernelPfS_S_iiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19convolve_gpu_kernelPfS_S_iiiiii, .Lfunc_end0-_Z19convolve_gpu_kernelPfS_S_iiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19convolve_gpu_kernelPfS_S_iiiiii
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z19convolve_gpu_kernelPfS_S_iiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void convolve_gpu_kernel(float *input, float *weights, float *output, int in_w, int in_h, int in_c, int n, int size, int pad)
{
int index = blockIdx.x*blockDim.x + threadIdx.x;
int fil;
// filter index
//for (fil = 0; fil < n; ++fil)
int chan, y, x, f_y, f_x;
// channel index
//for (chan = 0; chan < in_c; ++chan)
// input - y
//for (y = 0; y < in_h; ++y)
// input - x
//for (x = 0; x < in_w; ++x)
x = index % in_w;
int index2 = index / in_w;
y = index2 % in_h;
fil = index2 / in_h;
if (fil < n)
{
int const output_index = fil*in_w*in_h + y*in_w + x;
float sum = 0;
for (chan = 0; chan < in_c; ++chan)
{
int const weights_pre_index = fil*in_c*size*size + chan*size*size;
int const input_pre_index = chan*in_w*in_h;
// filter - y
for (f_y = 0; f_y < size; ++f_y)
{
int input_y = y + f_y - pad;
// filter - x
for (f_x = 0; f_x < size; ++f_x)
{
int input_x = x + f_x - pad;
if (input_y < 0 || input_x < 0 || input_y >= in_h || input_x >= in_w) continue;
int input_index = input_pre_index + input_y*in_w + input_x;
int weights_index = weights_pre_index + f_y*size + f_x;
sum += input[input_index] * weights[weights_index];
}
}
// l.output[filters][width][height] +=
// state.input[channels][width][height] *
// l.weights[filters][channels][filter_width][filter_height];
//output[output_index] += sum;
}
output[output_index] = sum;
}
} | .text
.file "convolve_gpu_kernel.hip"
.globl _Z34__device_stub__convolve_gpu_kernelPfS_S_iiiiii # -- Begin function _Z34__device_stub__convolve_gpu_kernelPfS_S_iiiiii
.p2align 4, 0x90
.type _Z34__device_stub__convolve_gpu_kernelPfS_S_iiiiii,@function
_Z34__device_stub__convolve_gpu_kernelPfS_S_iiiiii: # @_Z34__device_stub__convolve_gpu_kernelPfS_S_iiiiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19convolve_gpu_kernelPfS_S_iiiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z34__device_stub__convolve_gpu_kernelPfS_S_iiiiii, .Lfunc_end0-_Z34__device_stub__convolve_gpu_kernelPfS_S_iiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19convolve_gpu_kernelPfS_S_iiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19convolve_gpu_kernelPfS_S_iiiiii,@object # @_Z19convolve_gpu_kernelPfS_S_iiiiii
.section .rodata,"a",@progbits
.globl _Z19convolve_gpu_kernelPfS_S_iiiiii
.p2align 3, 0x0
_Z19convolve_gpu_kernelPfS_S_iiiiii:
.quad _Z34__device_stub__convolve_gpu_kernelPfS_S_iiiiii
.size _Z19convolve_gpu_kernelPfS_S_iiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19convolve_gpu_kernelPfS_S_iiiiii"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__convolve_gpu_kernelPfS_S_iiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19convolve_gpu_kernelPfS_S_iiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19convolve_gpu_kernelPfS_S_iiiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R5, c[0x0][0x178] ; /* 0x00005e0000057a13 */
/* 0x000fe20000000000 */
/*0020*/ S2R R17, SR_CTAID.X ; /* 0x0000000000117919 */
/* 0x000e220000002500 */
/*0030*/ IABS R9, c[0x0][0x17c] ; /* 0x00005f0000097a13 */
/* 0x000fe40000000000 */
/*0040*/ I2F.RP R0, R5 ; /* 0x0000000500007306 */
/* 0x000e620000209400 */
/*0050*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e2e0000002100 */
/*0060*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x002e620000001000 */
/*0070*/ IMAD R17, R17, c[0x0][0x0], R4 ; /* 0x0000000011117a24 */
/* 0x001fce00078e0204 */
/*0080*/ I2F.RP R4, R9 ; /* 0x0000000900047306 */
/* 0x000e220000209400 */
/*0090*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x002fce0007ffe0ff */
/*00a0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x0002b0000021f000 */
/*00b0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e220000001000 */
/*00c0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x002fe400078e00ff */
/*00d0*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x004fc800078e0a03 */
/*00e0*/ IMAD R7, R6, R5, RZ ; /* 0x0000000506077224 */
/* 0x000fe200078e02ff */
/*00f0*/ IABS R6, R17 ; /* 0x0000001100067213 */
/* 0x000fc60000000000 */
/*0100*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*0110*/ IMAD.HI.U32 R0, R3, R6, RZ ; /* 0x0000000603007227 */
/* 0x000fe200078e00ff */
/*0120*/ IADD3 R3, R4, 0xffffffe, RZ ; /* 0x0ffffffe04037810 */
/* 0x001fc60007ffe0ff */
/*0130*/ IMAD.MOV R2, RZ, RZ, -R0 ; /* 0x000000ffff027224 */
/* 0x000fc600078e0a00 */
/*0140*/ F2I.FTZ.U32.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e22000021f000 */
/*0150*/ IMAD R2, R5, R2, R6 ; /* 0x0000000205027224 */
/* 0x000fca00078e0206 */
/*0160*/ ISETP.GT.U32.AND P1, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x000fda0003f24070 */
/*0170*/ @!P1 IMAD.IADD R2, R2, 0x1, -R5 ; /* 0x0000000102029824 */
/* 0x000fe200078e0a05 */
/*0180*/ @!P1 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100009810 */
/* 0x000fe40007ffe0ff */
/*0190*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe40003f25270 */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x000fe40003f06070 */
/*01b0*/ LOP3.LUT R2, R17, c[0x0][0x178], RZ, 0x3c, !PT ; /* 0x00005e0011027a12 */
/* 0x000fc800078e3cff */
/*01c0*/ ISETP.GE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f46270 */
/*01d0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fcc00078e00ff */
/*01e0*/ @P0 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100000810 */
/* 0x000fca0007ffe0ff */
/*01f0*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0000 */
/*0200*/ IMAD.MOV R0, RZ, RZ, -R3 ; /* 0x000000ffff007224 */
/* 0x001fe400078e0a03 */
/*0210*/ @!P2 IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff07a224 */
/* 0x000fe200078e0a07 */
/*0220*/ @!P1 LOP3.LUT R7, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff079a12 */
/* 0x000fe200078e33ff */
/*0230*/ IMAD R5, R0, R9, RZ ; /* 0x0000000900057224 */
/* 0x000fc600078e02ff */
/*0240*/ IABS R0, R7 ; /* 0x0000000700007213 */
/* 0x000fe20000000000 */
/*0250*/ IMAD.HI.U32 R2, R3, R5, R2 ; /* 0x0000000503027227 */
/* 0x000fcc00078e0002 */
/*0260*/ IMAD.HI.U32 R18, R2, R0, RZ ; /* 0x0000000002127227 */
/* 0x000fc800078e00ff */
/*0270*/ IMAD.MOV R2, RZ, RZ, -R18 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0a12 */
/*0280*/ IMAD R0, R9, R2, R0 ; /* 0x0000000209007224 */
/* 0x000fca00078e0200 */
/*0290*/ ISETP.GT.U32.AND P1, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fda0003f24070 */
/*02a0*/ @!P1 IMAD.IADD R0, R0, 0x1, -R9 ; /* 0x0000000100009824 */
/* 0x000fe200078e0a09 */
/*02b0*/ @!P1 IADD3 R18, R18, 0x1, RZ ; /* 0x0000000112129810 */
/* 0x000fe40007ffe0ff */
/*02c0*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fe40003f25270 */
/*02d0*/ ISETP.GE.U32.AND P0, PT, R0, R9, PT ; /* 0x000000090000720c */
/* 0x000fe40003f06070 */
/*02e0*/ LOP3.LUT R0, R7, c[0x0][0x17c], RZ, 0x3c, !PT ; /* 0x00005f0007007a12 */
/* 0x000fc800078e3cff */
/*02f0*/ ISETP.GE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fce0003f46270 */
/*0300*/ @P0 IADD3 R18, R18, 0x1, RZ ; /* 0x0000000112120810 */
/* 0x000fcc0007ffe0ff */
/*0310*/ @!P2 IMAD.MOV R18, RZ, RZ, -R18 ; /* 0x000000ffff12a224 */
/* 0x000fe200078e0a12 */
/*0320*/ @!P1 LOP3.LUT R18, RZ, c[0x0][0x17c], RZ, 0x33, !PT ; /* 0x00005f00ff129a12 */
/* 0x000fc800078e33ff */
/*0330*/ ISETP.GE.AND P0, PT, R18, c[0x0][0x184], PT ; /* 0x0000610012007a0c */
/* 0x000fda0003f06270 */
/*0340*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0350*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff027624 */
/* 0x000fe200078e00ff */
/*0360*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0370*/ IMAD.MOV R0, RZ, RZ, -R7 ; /* 0x000000ffff007224 */
/* 0x000fe400078e0a07 */
/*0380*/ IMAD.MOV R16, RZ, RZ, -R18 ; /* 0x000000ffff107224 */
/* 0x000fe200078e0a12 */
/*0390*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f06270 */
/*03a0*/ IMAD R17, R0, c[0x0][0x178], R17 ; /* 0x00005e0000117a24 */
/* 0x000fe400078e0211 */
/*03b0*/ IMAD R16, R16, c[0x0][0x17c], R7 ; /* 0x00005f0010107a24 */
/* 0x000fe400078e0207 */
/*03c0*/ IMAD.MOV.U32 R15, RZ, RZ, RZ ; /* 0x000000ffff0f7224 */
/* 0x000fd000078e00ff */
/*03d0*/ @!P0 BRA 0xb70 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*03e0*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff0e7624 */
/* 0x000fca00078e00ff */
/*03f0*/ ISETP.GE.AND P0, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fda0003f06270 */
/*0400*/ @!P0 BRA 0xb70 ; /* 0x0000076000008947 */
/* 0x000fea0003800000 */
/*0410*/ IADD3 R20, R14.reuse, -0x1, RZ ; /* 0xffffffff0e147810 */
/* 0x040fe20007ffe0ff */
/*0420*/ IMAD.MOV.U32 R15, RZ, RZ, RZ ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e00ff */
/*0430*/ LOP3.LUT R14, R14, 0x3, RZ, 0xc0, !PT ; /* 0x000000030e0e7812 */
/* 0x000fe200078ec0ff */
/*0440*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*0450*/ IADD3 R10, R17.reuse, 0x3, RZ ; /* 0x00000003110a7810 */
/* 0x040fe40007ffe0ff */
/*0460*/ IADD3 R12, R17, -c[0x0][0x18c], RZ ; /* 0x80006300110c7a10 */
/* 0x000fe40007ffe0ff */
/*0470*/ IADD3 R13, R16, -c[0x0][0x18c], RZ ; /* 0x80006300100d7a10 */
/* 0x000fe40007ffe0ff */
/*0480*/ IADD3 R10, R10, -c[0x0][0x18c], RZ ; /* 0x800063000a0a7a10 */
/* 0x000fc40007ffe0ff */
/*0490*/ IADD3 R8, R14, -c[0x0][0x188], RZ ; /* 0x800062000e087a10 */
/* 0x000fe40007ffe0ff */
/*04a0*/ IMAD.MOV.U32 R9, RZ, RZ, R11.reuse ; /* 0x000000ffff097224 */
/* 0x100fe400078e000b */
/*04b0*/ IMAD R7, R18, c[0x0][0x180], R11 ; /* 0x0000600012077a24 */
/* 0x000fe200078e020b */
/*04c0*/ IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b7810 */
/* 0x000fe20007ffe0ff */
/*04d0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fc600078e00ff */
/*04e0*/ ISETP.GE.AND P2, PT, R11, c[0x0][0x180], PT ; /* 0x000060000b007a0c */
/* 0x000fe40003f46270 */
/*04f0*/ ISETP.GE.U32.AND P0, PT, R20, 0x3, PT ; /* 0x000000031400780c */
/* 0x000fe20003f06070 */
/*0500*/ IMAD R21, R7, c[0x0][0x188], R6.reuse ; /* 0x0000620007157a24 */
/* 0x100fe200078e0206 */
/*0510*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0520*/ IMAD.IADD R0, R13, 0x1, R6 ; /* 0x000000010d007824 */
/* 0x000fe200078e0206 */
/*0530*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fe20007ffe0ff */
/*0540*/ IMAD R21, R21, c[0x0][0x188], RZ ; /* 0x0000620015157a24 */
/* 0x000fe200078e02ff */
/*0550*/ ISETP.NE.AND P3, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe20003f65270 */
/*0560*/ IMAD R19, R9, c[0x0][0x17c], R0 ; /* 0x00005f0009137a24 */
/* 0x000fe200078e0200 */
/*0570*/ ISETP.GE.AND P1, PT, R6, c[0x0][0x188], PT ; /* 0x0000620006007a0c */
/* 0x000fca0003f26270 */
/*0580*/ @!P0 BRA 0x8c0 ; /* 0x0000033000008947 */
/* 0x000fec0003800000 */
/*0590*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*05a0*/ ISETP.GE.AND P4, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fe20003f86270 */
/*05b0*/ IMAD R2, R19, c[0x0][0x178], R12 ; /* 0x00005e0013027a24 */
/* 0x000fe200078e020c */
/*05c0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*05d0*/ IMAD.MOV.U32 R23, RZ, RZ, R8 ; /* 0x000000ffff177224 */
/* 0x000fe200078e0008 */
/*05e0*/ ULDC.64 UR8, c[0x0][0x168] ; /* 0x00005a0000087ab9 */
/* 0x000fe20000000a00 */
/*05f0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc800078e0203 */
/*0600*/ IMAD.MOV.U32 R22, RZ, RZ, R2 ; /* 0x000000ffff167224 */
/* 0x000fe400078e0002 */
/*0610*/ IMAD.MOV.U32 R27, RZ, RZ, R3 ; /* 0x000000ffff1b7224 */
/* 0x000fe400078e0003 */
/*0620*/ IMAD.MOV.U32 R25, RZ, RZ, R10 ; /* 0x000000ffff197224 */
/* 0x000fca00078e000a */
/*0630*/ IADD3 R3, R25.reuse, -0x3, RZ ; /* 0xfffffffd19037810 */
/* 0x040fe40007ffe0ff */
/*0640*/ IADD3 R5, R25, -0x2, RZ ; /* 0xfffffffe19057810 */
/* 0x000fe40007ffe0ff */
/*0650*/ LOP3.LUT R2, R3, R0.reuse, RZ, 0xfc, !PT ; /* 0x0000000003027212 */
/* 0x080fe400078efcff */
/*0660*/ LOP3.LUT R4, R5, R0, RZ, 0xfc, !PT ; /* 0x0000000005047212 */
/* 0x000fc400078efcff */
/*0670*/ ISETP.LT.OR P0, PT, R2, RZ, P4 ; /* 0x000000ff0200720c */
/* 0x000fe20002701670 */
/*0680*/ IMAD.U32 R2, RZ, RZ, UR8 ; /* 0x00000008ff027e24 */
/* 0x000fe2000f8e00ff */
/*0690*/ ISETP.LT.OR P5, PT, R4, RZ, P4 ; /* 0x000000ff0400720c */
/* 0x000fe200027a1670 */
/*06a0*/ IMAD.MOV.U32 R4, RZ, RZ, R22 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0016 */
/*06b0*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fe20000706670 */
/*06c0*/ IMAD.U32 R3, RZ, RZ, UR9 ; /* 0x00000009ff037e24 */
/* 0x000fe2000f8e00ff */
/*06d0*/ ISETP.GE.OR P5, PT, R5, c[0x0][0x178], P5 ; /* 0x00005e0005007a0c */
/* 0x000fe20002fa6670 */
/*06e0*/ IMAD.MOV.U32 R5, RZ, RZ, R27 ; /* 0x000000ffff057224 */
/* 0x000fe400078e001b */
/*06f0*/ IMAD.WIDE R2, R21, 0x4, R2 ; /* 0x0000000415027825 */
/* 0x000fd000078e0202 */
/*0700*/ @!P0 LDG.E R24, [R2.64] ; /* 0x0000000602188981 */
/* 0x000ea8000c1e1900 */
/*0710*/ @!P0 LDG.E R22, [R4.64] ; /* 0x0000000604168981 */
/* 0x000ea8000c1e1900 */
/*0720*/ @!P5 LDG.E R26, [R2.64+0x4] ; /* 0x00000406021ad981 */
/* 0x000ee8000c1e1900 */
/*0730*/ @!P5 LDG.E R27, [R4.64+0x4] ; /* 0x00000406041bd981 */
/* 0x000ee2000c1e1900 */
/*0740*/ IADD3 R29, R25, -0x1, RZ ; /* 0xffffffff191d7810 */
/* 0x000fe20007ffe0ff */
/*0750*/ @!P0 FFMA R15, R22, R24, R15 ; /* 0x00000018160f8223 */
/* 0x004fc6000000000f */
/*0760*/ LOP3.LUT R22, R29, R0, RZ, 0xfc, !PT ; /* 0x000000001d167212 */
/* 0x000fc800078efcff */
/*0770*/ ISETP.LT.OR P0, PT, R22, RZ, P4 ; /* 0x000000ff1600720c */
/* 0x000fe40002701670 */
/*0780*/ LOP3.LUT R22, R25, R0, RZ, 0xfc, !PT ; /* 0x0000000019167212 */
/* 0x000fe200078efcff */
/*0790*/ @!P5 FFMA R15, R26, R27, R15 ; /* 0x0000001b1a0fd223 */
/* 0x008fe2000000000f */
/*07a0*/ ISETP.GE.OR P5, PT, R29, c[0x0][0x178], P0 ; /* 0x00005e001d007a0c */
/* 0x000fe400007a6670 */
/*07b0*/ ISETP.LT.OR P0, PT, R22, RZ, P4 ; /* 0x000000ff1600720c */
/* 0x000fc80002701670 */
/*07c0*/ ISETP.GE.OR P0, PT, R25, c[0x0][0x178], P0 ; /* 0x00005e0019007a0c */
/* 0x000fce0000706670 */
/*07d0*/ @!P5 LDG.E R22, [R2.64+0x8] ; /* 0x000008060216d981 */
/* 0x000ea8000c1e1900 */
/*07e0*/ @!P5 LDG.E R24, [R4.64+0x8] ; /* 0x000008060418d981 */
/* 0x000ea8000c1e1900 */
/*07f0*/ @!P0 LDG.E R26, [R2.64+0xc] ; /* 0x00000c06021a8981 */
/* 0x000ee8000c1e1900 */
/*0800*/ @!P0 LDG.E R28, [R4.64+0xc] ; /* 0x00000c06041c8981 */
/* 0x000ee2000c1e1900 */
/*0810*/ IADD3 R23, R23, 0x4, RZ ; /* 0x0000000417177810 */
/* 0x000fe20007ffe0ff */
/*0820*/ UIADD3 UR8, UP0, UR8, 0x10, URZ ; /* 0x0000001008087890 */
/* 0x000fe2000ff1e03f */
/*0830*/ IADD3 R25, R25, 0x4, RZ ; /* 0x0000000419197810 */
/* 0x000fe20007ffe0ff */
/*0840*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0850*/ ISETP.NE.AND P6, PT, R23, RZ, PT ; /* 0x000000ff1700720c */
/* 0x000fe20003fc5270 */
/*0860*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe200087fe43f */
/*0870*/ @!P5 FFMA R15, R22, R24, R15 ; /* 0x00000018160fd223 */
/* 0x004fe2000000000f */
/*0880*/ IADD3 R22, P5, R4, 0x10, RZ ; /* 0x0000001004167810 */
/* 0x000fca0007fbe0ff */
/*0890*/ IMAD.X R27, RZ, RZ, R5, P5 ; /* 0x000000ffff1b7224 */
/* 0x000fe400028e0605 */
/*08a0*/ @!P0 FFMA R15, R26, R28, R15 ; /* 0x0000001c1a0f8223 */
/* 0x008fc6000000000f */
/*08b0*/ @P6 BRA 0x630 ; /* 0xfffffd7000006947 */
/* 0x000fea000383ffff */
/*08c0*/ @!P3 BRA 0xb50 ; /* 0x000002800000b947 */
/* 0x000fea0003800000 */
/*08d0*/ IADD3 R22, R12, UR4, RZ ; /* 0x000000040c167c10 */
/* 0x000fe2000fffe0ff */
/*08e0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*08f0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fe20003f06270 */
/*0900*/ BSSY B0, 0x9e0 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*0910*/ LOP3.LUT R2, R22, R0, RZ, 0xfc, !PT ; /* 0x0000000016027212 */
/* 0x000fe200078efcff */
/*0920*/ IMAD R4, R19, c[0x0][0x178], R22 ; /* 0x00005e0013047a24 */
/* 0x000fe200078e0216 */
/*0930*/ ISETP.NE.AND P4, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fe40003f85270 */
/*0940*/ ISETP.LT.OR P3, PT, R2, RZ, P0 ; /* 0x000000ff0200720c */
/* 0x000fe40000761670 */
/*0950*/ IADD3 R2, R21, UR4, RZ ; /* 0x0000000415027c10 */
/* 0x000fc4000fffe0ff */
/*0960*/ ISETP.GE.OR P3, PT, R22, c[0x0][0x178], P3 ; /* 0x00005e0016007a0c */
/* 0x000fc60001f66670 */
/*0970*/ IMAD.WIDE R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fc800078e0205 */
/*0980*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fcc00078e0205 */
/*0990*/ @P3 BRA 0x9d0 ; /* 0x0000003000003947 */
/* 0x000fea0003800000 */
/*09a0*/ LDG.E R24, [R4.64] ; /* 0x0000000604187981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ LDG.E R19, [R2.64] ; /* 0x0000000602137981 */
/* 0x000ea4000c1e1900 */
/*09c0*/ FFMA R15, R24, R19, R15 ; /* 0x00000013180f7223 */
/* 0x004fe4000000000f */
/*09d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*09e0*/ @!P4 BRA 0xb50 ; /* 0x000001600000c947 */
/* 0x000fea0003800000 */
/*09f0*/ IADD3 R19, R22, 0x1, RZ ; /* 0x0000000116137810 */
/* 0x000fe20007ffe0ff */
/*0a00*/ BSSY B0, 0xaa0 ; /* 0x0000009000007945 */
/* 0x000fe20003800000 */
/*0a10*/ ISETP.NE.AND P4, PT, R14, 0x2, PT ; /* 0x000000020e00780c */
/* 0x000fe40003f85270 */
/*0a20*/ LOP3.LUT R21, R19, R0, RZ, 0xfc, !PT ; /* 0x0000000013157212 */
/* 0x000fc800078efcff */
/*0a30*/ ISETP.LT.OR P3, PT, R21, RZ, P0 ; /* 0x000000ff1500720c */
/* 0x000fc80000761670 */
/*0a40*/ ISETP.GE.OR P3, PT, R19, c[0x0][0x178], P3 ; /* 0x00005e0013007a0c */
/* 0x000fda0001f66670 */
/*0a50*/ @P3 BRA 0xa90 ; /* 0x0000003000003947 */
/* 0x000fea0003800000 */
/*0a60*/ LDG.E R24, [R2.64+0x4] ; /* 0x0000040602187981 */
/* 0x000ea8000c1e1900 */
/*0a70*/ LDG.E R19, [R4.64+0x4] ; /* 0x0000040604137981 */
/* 0x000ea4000c1e1900 */
/*0a80*/ FFMA R15, R24, R19, R15 ; /* 0x00000013180f7223 */
/* 0x004fe4000000000f */
/*0a90*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0aa0*/ @!P4 BRA 0xb50 ; /* 0x000000a00000c947 */
/* 0x000fea0003800000 */
/*0ab0*/ IADD3 R19, R22, 0x2, RZ ; /* 0x0000000216137810 */
/* 0x000fe20007ffe0ff */
/*0ac0*/ BSSY B0, 0xb50 ; /* 0x0000008000007945 */
/* 0x000fe60003800000 */
/*0ad0*/ LOP3.LUT R0, R19, R0, RZ, 0xfc, !PT ; /* 0x0000000013007212 */
/* 0x000fc800078efcff */
/*0ae0*/ ISETP.LT.OR P0, PT, R0, RZ, P0 ; /* 0x000000ff0000720c */
/* 0x000fc80000701670 */
/*0af0*/ ISETP.GE.OR P0, PT, R19, c[0x0][0x178], P0 ; /* 0x00005e0013007a0c */
/* 0x000fda0000706670 */
/*0b00*/ @P0 BRA 0xb40 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0b10*/ LDG.E R2, [R2.64+0x8] ; /* 0x0000080602027981 */
/* 0x000ea8000c1e1900 */
/*0b20*/ LDG.E R4, [R4.64+0x8] ; /* 0x0000080604047981 */
/* 0x000ea4000c1e1900 */
/*0b30*/ FFMA R15, R2, R4, R15 ; /* 0x00000004020f7223 */
/* 0x004fe4000000000f */
/*0b40*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0b50*/ @!P1 BRA 0x4f0 ; /* 0xfffff99000009947 */
/* 0x000fea000383ffff */
/*0b60*/ @!P2 BRA 0x4a0 ; /* 0xfffff9300000a947 */
/* 0x000fea000383ffff */
/*0b70*/ IMAD R16, R18, c[0x0][0x17c], R16 ; /* 0x00005f0012107a24 */
/* 0x000fe400078e0210 */
/*0b80*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*0b90*/ IMAD R2, R16, c[0x0][0x178], R17 ; /* 0x00005e0010027a24 */
/* 0x000fc800078e0211 */
/*0ba0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0bb0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x000fe2000c101906 */
/*0bc0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0bd0*/ BRA 0xbd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19convolve_gpu_kernelPfS_S_iiiiii
.globl _Z19convolve_gpu_kernelPfS_S_iiiiii
.p2align 8
.type _Z19convolve_gpu_kernelPfS_S_iiiiii,@function
_Z19convolve_gpu_kernelPfS_S_iiiiii:
s_clause 0x2
s_load_b64 s[8:9], s[0:1], 0x18
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x3c
s_waitcnt lgkmcnt(0)
s_ashr_i32 s4, s8, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s5, s8, s4
s_and_b32 s3, s3, 0xffff
s_xor_b32 s5, s5, s4
v_cvt_f32_u32_e32 v1, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s3, v[0:1]
s_sub_i32 s3, 0, s5
v_mul_lo_u32 v0, s3, v1
s_ashr_i32 s3, s9, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_add_i32 s6, s9, s3
v_ashrrev_i32_e32 v3, 31, v2
s_xor_b32 s6, s6, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f32_u32_e32 v5, s6
v_mul_hi_u32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v4, v2, v3
v_rcp_iflag_f32_e32 v5, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_xor_b32_e32 v4, v4, v3
v_xor_b32_e32 v3, s4, v3
v_add_nc_u32_e32 v0, v1, v0
s_sub_i32 s4, 0, s6
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v5, 0x4f7ffffe, v5
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v0, s5
v_sub_nc_u32_e32 v1, v4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v6, s5, v1
v_cmp_le_u32_e32 vcc_lo, s5, v1
v_dual_cndmask_b32 v1, v1, v6 :: v_dual_add_nc_u32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, 1, v0
v_cvt_u32_f32_e32 v1, v5
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v4, s4, v1
v_xor_b32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v4, v1, v4
v_sub_nc_u32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v3, 31, v0
v_add_nc_u32_e32 v1, v1, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, v0, v3
v_xor_b32_e32 v4, v5, v3
v_xor_b32_e32 v3, s3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v1, v4, v1
v_mul_lo_u32 v5, v1, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v4, v4, v5
v_add_nc_u32_e32 v5, 1, v1
v_subrev_nc_u32_e32 v6, s6, v4
v_cmp_le_u32_e32 vcc_lo, s6, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v4, v4, v6 :: v_dual_cndmask_b32 v1, v1, v5
v_cmp_le_u32_e32 vcc_lo, s6, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, 1, v1
v_cndmask_b32_e32 v1, v1, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v1, v1, v3
v_sub_nc_u32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v3
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_13
s_load_b32 s12, s[0:1], 0x20
v_mul_lo_u32 v1, v3, s9
v_mul_lo_u32 v4, v0, s8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v1, v0, v1
v_sub_nc_u32_e32 v0, v2, v4
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s12, 1
s_cbranch_scc1 .LBB0_11
s_clause 0x1
s_load_b64 s[10:11], s[0:1], 0x28
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s14, 0
s_mul_i32 s15, s9, s8
s_waitcnt lgkmcnt(0)
s_mov_b32 s2, s11
s_mul_i32 s13, s10, s10
v_mad_u64_u32 v[4:5], null, s9, v3, s[2:3]
s_mul_i32 s2, s13, s12
v_subrev_nc_u32_e32 v5, s11, v0
v_mul_lo_u32 v6, s2, v3
s_cmp_gt_i32 s10, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, 0, v4
v_mad_u64_u32 v[7:8], null, s8, v4, v[2:3]
v_mov_b32_e32 v2, 0
v_subrev_nc_u32_e32 v4, s11, v1
s_delay_alu instid0(VALU_DEP_3)
v_subrev_nc_u32_e32 v7, s11, v7
s_cselect_b32 s11, -1, 0
s_branch .LBB0_4
.LBB0_3:
s_set_inst_prefetch_distance 0x2
v_add_nc_u32_e32 v6, s13, v6
v_add_nc_u32_e32 v7, s15, v7
s_add_i32 s14, s14, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s14, s12
s_cbranch_scc0 .LBB0_12
.LBB0_4:
s_and_not1_b32 vcc_lo, exec_lo, s11
s_cbranch_vccnz .LBB0_3
v_dual_mov_b32 v8, v7 :: v_dual_mov_b32 v9, v6
s_mov_b32 s16, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_7
.p2align 6
.LBB0_6:
v_add_nc_u32_e32 v9, s10, v9
v_add_nc_u32_e32 v8, s8, v8
s_add_i32 s16, s16, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s16, s10
s_cbranch_scc0 .LBB0_3
.LBB0_7:
v_add_nc_u32_e32 v10, s16, v4
s_mov_b32 s17, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s9, v10
s_branch .LBB0_9
.p2align 6
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s3
s_add_i32 s17, s17, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s10, s17
s_cbranch_scc0 .LBB0_6
.LBB0_9:
v_add_nc_u32_e32 v11, s17, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_or_b32_e32 v12, v10, v11
v_cmp_gt_i32_e64 s3, s8, v11
v_cmp_lt_i32_e64 s2, -1, v12
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_8
v_add_nc_u32_e32 v11, s17, v8
v_add_nc_u32_e32 v13, s17, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v12, 31, v11
v_ashrrev_i32_e32 v14, 31, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_lshlrev_b64 v[13:14], 2, v[13:14]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v11, s2, s4, v11
v_add_co_ci_u32_e64 v12, s2, s5, v12, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v13, s2, s6, v13
v_add_co_ci_u32_e64 v14, s2, s7, v14, s2
global_load_b32 v11, v[11:12], off
global_load_b32 v12, v[13:14], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v2, v11, v12
s_branch .LBB0_8
.LBB0_11:
v_mov_b32_e32 v2, 0
.LBB0_12:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v3, s9, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[5:6], null, v4, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[0:1], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19convolve_gpu_kernelPfS_S_iiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19convolve_gpu_kernelPfS_S_iiiiii, .Lfunc_end0-_Z19convolve_gpu_kernelPfS_S_iiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19convolve_gpu_kernelPfS_S_iiiiii
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z19convolve_gpu_kernelPfS_S_iiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b0c02_00000000-6_convolve_gpu_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z19convolve_gpu_kernelPfS_S_iiiiiiPfS_S_iiiiii
.type _Z49__device_stub__Z19convolve_gpu_kernelPfS_S_iiiiiiPfS_S_iiiiii, @function
_Z49__device_stub__Z19convolve_gpu_kernelPfS_S_iiiiiiPfS_S_iiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z19convolve_gpu_kernelPfS_S_iiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z19convolve_gpu_kernelPfS_S_iiiiiiPfS_S_iiiiii, .-_Z49__device_stub__Z19convolve_gpu_kernelPfS_S_iiiiiiPfS_S_iiiiii
.globl _Z19convolve_gpu_kernelPfS_S_iiiiii
.type _Z19convolve_gpu_kernelPfS_S_iiiiii, @function
_Z19convolve_gpu_kernelPfS_S_iiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z49__device_stub__Z19convolve_gpu_kernelPfS_S_iiiiiiPfS_S_iiiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19convolve_gpu_kernelPfS_S_iiiiii, .-_Z19convolve_gpu_kernelPfS_S_iiiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19convolve_gpu_kernelPfS_S_iiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19convolve_gpu_kernelPfS_S_iiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "convolve_gpu_kernel.hip"
.globl _Z34__device_stub__convolve_gpu_kernelPfS_S_iiiiii # -- Begin function _Z34__device_stub__convolve_gpu_kernelPfS_S_iiiiii
.p2align 4, 0x90
.type _Z34__device_stub__convolve_gpu_kernelPfS_S_iiiiii,@function
_Z34__device_stub__convolve_gpu_kernelPfS_S_iiiiii: # @_Z34__device_stub__convolve_gpu_kernelPfS_S_iiiiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19convolve_gpu_kernelPfS_S_iiiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z34__device_stub__convolve_gpu_kernelPfS_S_iiiiii, .Lfunc_end0-_Z34__device_stub__convolve_gpu_kernelPfS_S_iiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19convolve_gpu_kernelPfS_S_iiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19convolve_gpu_kernelPfS_S_iiiiii,@object # @_Z19convolve_gpu_kernelPfS_S_iiiiii
.section .rodata,"a",@progbits
.globl _Z19convolve_gpu_kernelPfS_S_iiiiii
.p2align 3, 0x0
_Z19convolve_gpu_kernelPfS_S_iiiiii:
.quad _Z34__device_stub__convolve_gpu_kernelPfS_S_iiiiii
.size _Z19convolve_gpu_kernelPfS_S_iiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19convolve_gpu_kernelPfS_S_iiiiii"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__convolve_gpu_kernelPfS_S_iiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19convolve_gpu_kernelPfS_S_iiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
int main( void )
{
int deviceCount;
cudaGetDeviceCount( &deviceCount );
printf("Hello, Physics 244 Class! You have %d devices\n", deviceCount );
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
int main( void )
{
int deviceCount;
cudaGetDeviceCount( &deviceCount );
printf("Hello, Physics 244 Class! You have %d devices\n", deviceCount );
return 0;
} | .file "tmpxft_001462ba_00000000-6_simple_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Hello, Physics 244 Class! You have %d devices\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 4(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L6
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
int main( void )
{
int deviceCount;
cudaGetDeviceCount( &deviceCount );
printf("Hello, Physics 244 Class! You have %d devices\n", deviceCount );
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
int main( void )
{
int deviceCount;
hipGetDeviceCount( &deviceCount );
printf("Hello, Physics 244 Class! You have %d devices\n", deviceCount );
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
int main( void )
{
int deviceCount;
hipGetDeviceCount( &deviceCount );
printf("Hello, Physics 244 Class! You have %d devices\n", deviceCount );
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
int main( void )
{
int deviceCount;
hipGetDeviceCount( &deviceCount );
printf("Hello, Physics 244 Class! You have %d devices\n", deviceCount );
return 0;
} | .text
.file "simple_hello.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
movl 4(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Hello, Physics 244 Class! You have %d devices\n"
.size .L.str, 47
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001462ba_00000000-6_simple_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Hello, Physics 244 Class! You have %d devices\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 4(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L6
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "simple_hello.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
movl 4(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Hello, Physics 244 Class! You have %d devices\n"
.size .L.str, 47
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cstdio>
#include <cstdlib>
#include <iostream>
#include <cassert>
constexpr size_t BLOCK_SIZE = 1024; // Размер блока.
constexpr size_t SIZE = 2048;
// Отдельный компаратор сравнивает пару ключей
// и производит обмен соответствующих элементов и
// ключей для обеспечения заданного порядка.
__device__ void Comparator (uint& keyA, uint& valA, uint& keyB, uint& valB, uint dir) {
uint t;
// Поменять местами (keyA, valA) и (keyB, valB)
if ( (keyA > keyB) == dir ) {
t = keyA;
keyA = keyB;
keyB = t;
t = valA;
valA = valB;
valB = t;
}
}
__global__ void bitonicSortShared (uint* dstKey,
uint* dstVal,
uint* srcKey,
uint* srcVal,
uint arrayLength,
uint dir) {
__shared__ uint sk [BLOCK_SIZE * 2];
__shared__ uint sv [BLOCK_SIZE * 2];
int index = blockIdx.x * BLOCK_SIZE * 2 + threadIdx.x;
sk [threadIdx.x] = srcKey[index];
sv [threadIdx.x] = srcVal[index];
sk [threadIdx.x + BLOCK_SIZE] = srcKey [index + BLOCK_SIZE];
sv [threadIdx.x + BLOCK_SIZE] = srcVal [index + BLOCK_SIZE];
assert(threadIdx.x + BLOCK_SIZE < SIZE && index + BLOCK_SIZE < SIZE);
for (uint size = 2; size < arrayLength; size <<= 1u )
{
// Битоническое слияние
uint ddd = dir ^ ((threadIdx.x & (size / 2)) != 0);
for (uint stride = size >> 1u; stride > 0; stride >>= 1u)
{
__syncthreads ();
uint pos = 2 * threadIdx.x - (threadIdx.x & (stride - 1));
assert(pos + stride < 2 * BLOCK_SIZE);
Comparator( sk[pos], sv[pos], sk[pos+stride], sv[pos+stride], ddd);
}
__syncthreads();
}
for (uint stride = arrayLength >> 1u; stride > 0; stride >>= 1u)
{
__syncthreads ();
uint pos = 2 * threadIdx.x - (threadIdx.x & (stride - 1));
// assert(pos + stride < 2 * BLOCK_SIZE);
Comparator( sk[pos], sv[pos], sk[pos + stride], sv[pos+stride], dir);
// Comparator(srcKey[blockIdx.x * BLOCK_SIZE * 2 + pos], srcVal[blockIdx.x * BLOCK_SIZE * 2 + pos],
// srcKey[blockIdx.x * BLOCK_SIZE * 2 + pos + stride], srcVal[blockIdx.x * BLOCK_SIZE * 2 + pos + stride], dir);
}
__syncthreads ();
dstKey[index] = sk[threadIdx.x] ;
dstVal[index] = sv[threadIdx.x] ;
dstKey[index + BLOCK_SIZE] = sk[threadIdx.x + BLOCK_SIZE];
dstVal[index + BLOCK_SIZE] = sv[threadIdx.x + BLOCK_SIZE];
}
__host__ int main()
{
uint* key_arr = new uint[SIZE];
uint* value_arr = new uint[SIZE];
for (size_t i=0; i<SIZE; i++)
{
key_arr[i] = uint(rand()) % 100;
value_arr[i] = i;
}
uint* dst_key_arr = new uint[SIZE];
cudaMalloc((void **)&dst_key_arr, SIZE * sizeof(uint));
uint* dst_value_arr = new uint[SIZE];
cudaMalloc((void **)&dst_value_arr, SIZE * sizeof(uint));
uint* cuda_key_arr;
cudaMalloc((void **)&cuda_key_arr, SIZE * sizeof(uint));
cudaMemcpy(cuda_key_arr, key_arr, SIZE * sizeof(uint),cudaMemcpyHostToDevice);
uint* cuda_value_arr;
cudaMalloc((void **)&cuda_value_arr, SIZE * sizeof(uint));
cudaMemcpy(cuda_value_arr, value_arr, SIZE * sizeof(uint),cudaMemcpyHostToDevice);
cudaEvent_t start, stop;
float gpuTime = 0.0f;
// printf("Elapsed time: %.2f\n", gpuTime);
// for(size_t i=0; i<SIZE; i++)
// {
// std::cout << key_arr[i] << " ";
// }
std::cout << std::endl;
cudaEventCreate (&start);
cudaEventCreate (&stop);
cudaEventRecord (start, 0);
bitonicSortShared<<<dim3(SIZE / (2 * BLOCK_SIZE)), dim3(BLOCK_SIZE)>>>(dst_key_arr,
dst_value_arr,
cuda_key_arr,
cuda_value_arr,
SIZE,
1);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&gpuTime, start, stop);
cudaMemcpy(value_arr, dst_value_arr, SIZE * sizeof(uint), cudaMemcpyDeviceToHost);
cudaMemcpy(key_arr, dst_key_arr, SIZE * sizeof(uint), cudaMemcpyDeviceToHost);
printf("Elapsed time: %.2f\n", gpuTime);
for(size_t i=0; i<SIZE-1; i++)
{
if (key_arr[i] > key_arr[i+1])
std::cout << "Error " << key_arr[i] << "> " << key_arr[i+1] << std::endl;
}
std::cout << std::endl;
delete [] key_arr;
cudaFree(cuda_key_arr);
cudaFree(cuda_value_arr);
cudaFree(dst_value_arr);
cudaFree(dst_key_arr);
} | code for sm_80
Function : _Z17bitonicSortSharedPjS_S_S_jj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R3, 0x800, R2 ; /* 0x0000080003007824 */
/* 0x001fc800078e0202 */
/*0060*/ IMAD.WIDE R4, R0, R7, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R6, R0, R7, c[0x0][0x178] ; /* 0x00005e0000067625 */
/* 0x000fe200078e0207 */
/*0080*/ LDG.E R3, [R4.64] ; /* 0x0000000604037981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R11, [R4.64+0x1000] ; /* 0x00100006040b7981 */
/* 0x000ee8000c1e1900 */
/*00a0*/ LDG.E R9, [R6.64] ; /* 0x0000000606097981 */
/* 0x000f28000c1e1900 */
/*00b0*/ LDG.E R13, [R6.64+0x1000] ; /* 0x00100006060d7981 */
/* 0x000f62000c1e1900 */
/*00c0*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff087624 */
/* 0x000fca00078e00ff */
/*00d0*/ ISETP.GE.U32.AND P0, PT, R8, 0x3, PT ; /* 0x000000030800780c */
/* 0x000fe20003f06070 */
/*00e0*/ STS [R2.X4], R3 ; /* 0x0000000302007388 */
/* 0x0041e80000004800 */
/*00f0*/ STS [R2.X4+0x1000], R11 ; /* 0x0010000b02007388 */
/* 0x0081e80000004800 */
/*0100*/ STS [R2.X4+0x2000], R9 ; /* 0x0020000902007388 */
/* 0x0101e80000004800 */
/*0110*/ STS [R2.X4+0x3000], R13 ; /* 0x0030000d02007388 */
/* 0x0201e20000004800 */
/*0120*/ @!P0 BRA 0x320 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0130*/ IMAD.MOV.U32 R10, RZ, RZ, 0x2 ; /* 0x00000002ff0a7424 */
/* 0x000fca00078e00ff */
/*0140*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f05270 */
/*0150*/ @!P0 BRA 0x2e0 ; /* 0x0000018000008947 */
/* 0x001fea0003800000 */
/*0160*/ SHF.R.U32.HI R3, RZ, 0x1, R10 ; /* 0x00000001ff037819 */
/* 0x001fc8000001160a */
/*0170*/ LOP3.LUT P0, RZ, R3, R2, RZ, 0xc0, !PT ; /* 0x0000000203ff7212 */
/* 0x000fc8000780c0ff */
/*0180*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*0190*/ LOP3.LUT R7, R4, c[0x0][0x184], RZ, 0x3c, !PT ; /* 0x0000610004077a12 */
/* 0x000fe400078e3cff */
/*01a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01b0*/ IADD3 R5, R3, -0x1, RZ ; /* 0xffffffff03057810 */
/* 0x000fc80007ffe0ff */
/*01c0*/ LOP3.LUT R5, R5, R2, RZ, 0xc0, !PT ; /* 0x0000000205057212 */
/* 0x000fca00078ec0ff */
/*01d0*/ IMAD R5, R2, 0x2, -R5 ; /* 0x0000000202057824 */
/* 0x000fc800078e0a05 */
/*01e0*/ IMAD.SHL.U32 R6, R5, 0x4, RZ ; /* 0x0000000405067824 */
/* 0x000fc800078e00ff */
/*01f0*/ IMAD R9, R3, 0x4, R6 ; /* 0x0000000403097824 */
/* 0x000fe200078e0206 */
/*0200*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fe20000011603 */
/*0210*/ LDS R8, [R6] ; /* 0x0000000006087984 */
/* 0x000fe80000000800 */
/*0220*/ LDS R11, [R9] ; /* 0x00000000090b7984 */
/* 0x000e240000000800 */
/*0230*/ ISETP.GT.U32.AND P0, PT, R8, R11, PT ; /* 0x0000000b0800720c */
/* 0x001fc80003f04070 */
/*0240*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*0250*/ ISETP.NE.AND P0, PT, R7, R4, PT ; /* 0x000000040700720c */
/* 0x000fda0003f05270 */
/*0260*/ @!P0 STS [R6], R11 ; /* 0x0000000b06008388 */
/* 0x000fe80000000800 */
/*0270*/ @!P0 STS [R9], R8 ; /* 0x0000000809008388 */
/* 0x000fe80000000800 */
/*0280*/ @!P0 LDS R5, [R9+0x2000] ; /* 0x0020000009058984 */
/* 0x000e280000000800 */
/*0290*/ @!P0 LDS R4, [R6+0x2000] ; /* 0x0020000006048984 */
/* 0x000e680000000800 */
/*02a0*/ @!P0 STS [R6+0x2000], R5 ; /* 0x0020000506008388 */
/* 0x0011e80000000800 */
/*02b0*/ @!P0 STS [R9+0x2000], R4 ; /* 0x0020000409008388 */
/* 0x0021e20000000800 */
/*02c0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*02d0*/ @P0 BRA 0x1a0 ; /* 0xfffffec000000947 */
/* 0x001fea000383ffff */
/*02e0*/ IMAD.SHL.U32 R10, R10, 0x2, RZ ; /* 0x000000020a0a7824 */
/* 0x000fe200078e00ff */
/*02f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe80000010000 */
/*0300*/ ISETP.GE.U32.AND P0, PT, R10, c[0x0][0x180], PT ; /* 0x000060000a007a0c */
/* 0x000fda0003f06070 */
/*0310*/ @!P0 BRA 0x140 ; /* 0xfffffe2000008947 */
/* 0x000fea000383ffff */
/*0320*/ ULDC UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fe40000000800 */
/*0330*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*0340*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf05270 */
/*0350*/ @!P0 BRA 0x4b0 ; /* 0x0000015000008947 */
/* 0x000fea0003800000 */
/*0360*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x001fc8000f8e00ff */
/*0370*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0380*/ IADD3 R5, R3, -0x1, RZ ; /* 0xffffffff03057810 */
/* 0x000fc80007ffe0ff */
/*0390*/ LOP3.LUT R5, R5, R2, RZ, 0xc0, !PT ; /* 0x0000000205057212 */
/* 0x000fca00078ec0ff */
/*03a0*/ IMAD R5, R2, 0x2, -R5 ; /* 0x0000000202057824 */
/* 0x000fc800078e0a05 */
/*03b0*/ IMAD.SHL.U32 R6, R5, 0x4, RZ ; /* 0x0000000405067824 */
/* 0x000fc800078e00ff */
/*03c0*/ IMAD R7, R3, 0x4, R6 ; /* 0x0000000403077824 */
/* 0x000fe200078e0206 */
/*03d0*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fe20000011603 */
/*03e0*/ LDS R8, [R6] ; /* 0x0000000006087984 */
/* 0x000fe80000000800 */
/*03f0*/ LDS R9, [R7] ; /* 0x0000000007097984 */
/* 0x000e240000000800 */
/*0400*/ ISETP.GT.U32.AND P0, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x001fc80003f04070 */
/*0410*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*0420*/ ISETP.NE.AND P0, PT, R4, c[0x0][0x184], PT ; /* 0x0000610004007a0c */
/* 0x000fda0003f05270 */
/*0430*/ @!P0 STS [R6], R9 ; /* 0x0000000906008388 */
/* 0x000fe80000000800 */
/*0440*/ @!P0 STS [R7], R8 ; /* 0x0000000807008388 */
/* 0x000fe80000000800 */
/*0450*/ @!P0 LDS R5, [R7+0x2000] ; /* 0x0020000007058984 */
/* 0x000e280000000800 */
/*0460*/ @!P0 LDS R4, [R6+0x2000] ; /* 0x0020000006048984 */
/* 0x000e680000000800 */
/*0470*/ @!P0 STS [R6+0x2000], R5 ; /* 0x0020000506008388 */
/* 0x0011e80000000800 */
/*0480*/ @!P0 STS [R7+0x2000], R4 ; /* 0x0020000407008388 */
/* 0x0021e20000000800 */
/*0490*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*04a0*/ @P0 BRA 0x370 ; /* 0xfffffec000000947 */
/* 0x001fea000383ffff */
/*04b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*04c0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fc800078e00ff */
/*04d0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc800078e0207 */
/*04e0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x000fe200078e0207 */
/*04f0*/ LDS R3, [R2.X4] ; /* 0x0000000002037984 */
/* 0x001e280000004800 */
/*0500*/ LDS R9, [R2.X4+0x2000] ; /* 0x0020000002097984 */
/* 0x000e680000004800 */
/*0510*/ LDS R11, [R2.X4+0x1000] ; /* 0x00100000020b7984 */
/* 0x000ea80000004800 */
/*0520*/ LDS R13, [R2.X4+0x3000] ; /* 0x00300000020d7984 */
/* 0x000ee80000004800 */
/*0530*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x001fe8000c101906 */
/*0540*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x002fe8000c101906 */
/*0550*/ STG.E [R4.64+0x1000], R11 ; /* 0x0010000b04007986 */
/* 0x004fe8000c101906 */
/*0560*/ STG.E [R6.64+0x1000], R13 ; /* 0x0010000d06007986 */
/* 0x008fe2000c101906 */
/*0570*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0580*/ BRA 0x580; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cstdio>
#include <cstdlib>
#include <iostream>
#include <cassert>
constexpr size_t BLOCK_SIZE = 1024; // Размер блока.
constexpr size_t SIZE = 2048;
// Отдельный компаратор сравнивает пару ключей
// и производит обмен соответствующих элементов и
// ключей для обеспечения заданного порядка.
__device__ void Comparator (uint& keyA, uint& valA, uint& keyB, uint& valB, uint dir) {
uint t;
// Поменять местами (keyA, valA) и (keyB, valB)
if ( (keyA > keyB) == dir ) {
t = keyA;
keyA = keyB;
keyB = t;
t = valA;
valA = valB;
valB = t;
}
}
__global__ void bitonicSortShared (uint* dstKey,
uint* dstVal,
uint* srcKey,
uint* srcVal,
uint arrayLength,
uint dir) {
__shared__ uint sk [BLOCK_SIZE * 2];
__shared__ uint sv [BLOCK_SIZE * 2];
int index = blockIdx.x * BLOCK_SIZE * 2 + threadIdx.x;
sk [threadIdx.x] = srcKey[index];
sv [threadIdx.x] = srcVal[index];
sk [threadIdx.x + BLOCK_SIZE] = srcKey [index + BLOCK_SIZE];
sv [threadIdx.x + BLOCK_SIZE] = srcVal [index + BLOCK_SIZE];
assert(threadIdx.x + BLOCK_SIZE < SIZE && index + BLOCK_SIZE < SIZE);
for (uint size = 2; size < arrayLength; size <<= 1u )
{
// Битоническое слияние
uint ddd = dir ^ ((threadIdx.x & (size / 2)) != 0);
for (uint stride = size >> 1u; stride > 0; stride >>= 1u)
{
__syncthreads ();
uint pos = 2 * threadIdx.x - (threadIdx.x & (stride - 1));
assert(pos + stride < 2 * BLOCK_SIZE);
Comparator( sk[pos], sv[pos], sk[pos+stride], sv[pos+stride], ddd);
}
__syncthreads();
}
for (uint stride = arrayLength >> 1u; stride > 0; stride >>= 1u)
{
__syncthreads ();
uint pos = 2 * threadIdx.x - (threadIdx.x & (stride - 1));
// assert(pos + stride < 2 * BLOCK_SIZE);
Comparator( sk[pos], sv[pos], sk[pos + stride], sv[pos+stride], dir);
// Comparator(srcKey[blockIdx.x * BLOCK_SIZE * 2 + pos], srcVal[blockIdx.x * BLOCK_SIZE * 2 + pos],
// srcKey[blockIdx.x * BLOCK_SIZE * 2 + pos + stride], srcVal[blockIdx.x * BLOCK_SIZE * 2 + pos + stride], dir);
}
__syncthreads ();
dstKey[index] = sk[threadIdx.x] ;
dstVal[index] = sv[threadIdx.x] ;
dstKey[index + BLOCK_SIZE] = sk[threadIdx.x + BLOCK_SIZE];
dstVal[index + BLOCK_SIZE] = sv[threadIdx.x + BLOCK_SIZE];
}
__host__ int main()
{
uint* key_arr = new uint[SIZE];
uint* value_arr = new uint[SIZE];
for (size_t i=0; i<SIZE; i++)
{
key_arr[i] = uint(rand()) % 100;
value_arr[i] = i;
}
uint* dst_key_arr = new uint[SIZE];
cudaMalloc((void **)&dst_key_arr, SIZE * sizeof(uint));
uint* dst_value_arr = new uint[SIZE];
cudaMalloc((void **)&dst_value_arr, SIZE * sizeof(uint));
uint* cuda_key_arr;
cudaMalloc((void **)&cuda_key_arr, SIZE * sizeof(uint));
cudaMemcpy(cuda_key_arr, key_arr, SIZE * sizeof(uint),cudaMemcpyHostToDevice);
uint* cuda_value_arr;
cudaMalloc((void **)&cuda_value_arr, SIZE * sizeof(uint));
cudaMemcpy(cuda_value_arr, value_arr, SIZE * sizeof(uint),cudaMemcpyHostToDevice);
cudaEvent_t start, stop;
float gpuTime = 0.0f;
// printf("Elapsed time: %.2f\n", gpuTime);
// for(size_t i=0; i<SIZE; i++)
// {
// std::cout << key_arr[i] << " ";
// }
std::cout << std::endl;
cudaEventCreate (&start);
cudaEventCreate (&stop);
cudaEventRecord (start, 0);
bitonicSortShared<<<dim3(SIZE / (2 * BLOCK_SIZE)), dim3(BLOCK_SIZE)>>>(dst_key_arr,
dst_value_arr,
cuda_key_arr,
cuda_value_arr,
SIZE,
1);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&gpuTime, start, stop);
cudaMemcpy(value_arr, dst_value_arr, SIZE * sizeof(uint), cudaMemcpyDeviceToHost);
cudaMemcpy(key_arr, dst_key_arr, SIZE * sizeof(uint), cudaMemcpyDeviceToHost);
printf("Elapsed time: %.2f\n", gpuTime);
for(size_t i=0; i<SIZE-1; i++)
{
if (key_arr[i] > key_arr[i+1])
std::cout << "Error " << key_arr[i] << "> " << key_arr[i+1] << std::endl;
}
std::cout << std::endl;
delete [] key_arr;
cudaFree(cuda_key_arr);
cudaFree(cuda_value_arr);
cudaFree(dst_value_arr);
cudaFree(dst_key_arr);
} | .file "tmpxft_000f8163_00000000-6_lab5.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10ComparatorRjS_S_S_j
.type _Z10ComparatorRjS_S_S_j, @function
_Z10ComparatorRjS_S_S_j:
.LFB3669:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z10ComparatorRjS_S_S_j, .-_Z10ComparatorRjS_S_S_j
.globl _Z45__device_stub__Z17bitonicSortSharedPjS_S_S_jjPjS_S_S_jj
.type _Z45__device_stub__Z17bitonicSortSharedPjS_S_S_jjPjS_S_S_jj, @function
_Z45__device_stub__Z17bitonicSortSharedPjS_S_S_jjPjS_S_S_jj:
.LFB3695:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z17bitonicSortSharedPjS_S_S_jj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z45__device_stub__Z17bitonicSortSharedPjS_S_S_jjPjS_S_S_jj, .-_Z45__device_stub__Z17bitonicSortSharedPjS_S_S_jjPjS_S_S_jj
.globl _Z17bitonicSortSharedPjS_S_S_jj
.type _Z17bitonicSortSharedPjS_S_S_jj, @function
_Z17bitonicSortSharedPjS_S_S_jj:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z17bitonicSortSharedPjS_S_S_jjPjS_S_S_jj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z17bitonicSortSharedPjS_S_S_jj, .-_Z17bitonicSortSharedPjS_S_S_jj
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Elapsed time: %.2f\n"
.LC2:
.string "Error "
.LC3:
.string "> "
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $8192, %edi
call _Znam@PLT
movq %rax, %r13
movl $8192, %edi
call _Znam@PLT
movq %rax, %rbp
movl $0, %ebx
.L14:
call rand@PLT
movl %eax, %edx
imulq $1374389535, %rdx, %rdx
shrq $37, %rdx
imull $100, %edx, %edx
subl %edx, %eax
movl %eax, 0(%r13,%rbx,4)
movl %ebx, 0(%rbp,%rbx,4)
addq $1, %rbx
cmpq $2048, %rbx
jne .L14
movl $8192, %edi
call _Znam@PLT
movq %rax, 16(%rsp)
leaq 16(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
movl $8192, %edi
call _Znam@PLT
movq %rax, 24(%rsp)
leaq 24(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $8192, %edx
movq %r13, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
leaq 40(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $8192, %edx
movq %rbp, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $0x00000000, 12(%rsp)
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $1024, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L15:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $2, %ecx
movl $8192, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $8192, %edx
movq 16(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r13, %rbx
leaq 8188(%r13), %r14
leaq _ZSt4cout(%rip), %r15
jmp .L21
.L26:
movl $1, %r9d
movl $2048, %r8d
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z45__device_stub__Z17bitonicSortSharedPjS_S_S_jjPjS_S_S_jj
jmp .L15
.L29:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L27
call _ZSt16__throw_bad_castv@PLT
.L27:
call __stack_chk_fail@PLT
.L30:
movzbl 67(%r12), %esi
.L20:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.L16:
addq $4, %rbx
cmpq %r14, %rbx
je .L28
.L21:
movl (%rbx), %eax
cmpl %eax, 4(%rbx)
jnb .L16
movl $6, %edx
leaq .LC2(%rip), %rsi
movq %r15, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl (%rbx), %esi
movq %r15, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbp
movl $2, %edx
leaq .LC3(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 4(%rbx), %esi
movq %rbp, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L29
cmpb $0, 56(%r12)
jne .L30
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L20
.L28:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r13, %rdi
call _ZdaPv@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "_Z17bitonicSortSharedPjS_S_S_jj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z17bitonicSortSharedPjS_S_S_jj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cstdio>
#include <cstdlib>
#include <iostream>
#include <cassert>
constexpr size_t BLOCK_SIZE = 1024; // Размер блока.
constexpr size_t SIZE = 2048;
// Отдельный компаратор сравнивает пару ключей
// и производит обмен соответствующих элементов и
// ключей для обеспечения заданного порядка.
__device__ void Comparator (uint& keyA, uint& valA, uint& keyB, uint& valB, uint dir) {
uint t;
// Поменять местами (keyA, valA) и (keyB, valB)
if ( (keyA > keyB) == dir ) {
t = keyA;
keyA = keyB;
keyB = t;
t = valA;
valA = valB;
valB = t;
}
}
__global__ void bitonicSortShared (uint* dstKey,
uint* dstVal,
uint* srcKey,
uint* srcVal,
uint arrayLength,
uint dir) {
__shared__ uint sk [BLOCK_SIZE * 2];
__shared__ uint sv [BLOCK_SIZE * 2];
int index = blockIdx.x * BLOCK_SIZE * 2 + threadIdx.x;
sk [threadIdx.x] = srcKey[index];
sv [threadIdx.x] = srcVal[index];
sk [threadIdx.x + BLOCK_SIZE] = srcKey [index + BLOCK_SIZE];
sv [threadIdx.x + BLOCK_SIZE] = srcVal [index + BLOCK_SIZE];
assert(threadIdx.x + BLOCK_SIZE < SIZE && index + BLOCK_SIZE < SIZE);
for (uint size = 2; size < arrayLength; size <<= 1u )
{
// Битоническое слияние
uint ddd = dir ^ ((threadIdx.x & (size / 2)) != 0);
for (uint stride = size >> 1u; stride > 0; stride >>= 1u)
{
__syncthreads ();
uint pos = 2 * threadIdx.x - (threadIdx.x & (stride - 1));
assert(pos + stride < 2 * BLOCK_SIZE);
Comparator( sk[pos], sv[pos], sk[pos+stride], sv[pos+stride], ddd);
}
__syncthreads();
}
for (uint stride = arrayLength >> 1u; stride > 0; stride >>= 1u)
{
__syncthreads ();
uint pos = 2 * threadIdx.x - (threadIdx.x & (stride - 1));
// assert(pos + stride < 2 * BLOCK_SIZE);
Comparator( sk[pos], sv[pos], sk[pos + stride], sv[pos+stride], dir);
// Comparator(srcKey[blockIdx.x * BLOCK_SIZE * 2 + pos], srcVal[blockIdx.x * BLOCK_SIZE * 2 + pos],
// srcKey[blockIdx.x * BLOCK_SIZE * 2 + pos + stride], srcVal[blockIdx.x * BLOCK_SIZE * 2 + pos + stride], dir);
}
__syncthreads ();
dstKey[index] = sk[threadIdx.x] ;
dstVal[index] = sv[threadIdx.x] ;
dstKey[index + BLOCK_SIZE] = sk[threadIdx.x + BLOCK_SIZE];
dstVal[index + BLOCK_SIZE] = sv[threadIdx.x + BLOCK_SIZE];
}
__host__ int main()
{
uint* key_arr = new uint[SIZE];
uint* value_arr = new uint[SIZE];
for (size_t i=0; i<SIZE; i++)
{
key_arr[i] = uint(rand()) % 100;
value_arr[i] = i;
}
uint* dst_key_arr = new uint[SIZE];
cudaMalloc((void **)&dst_key_arr, SIZE * sizeof(uint));
uint* dst_value_arr = new uint[SIZE];
cudaMalloc((void **)&dst_value_arr, SIZE * sizeof(uint));
uint* cuda_key_arr;
cudaMalloc((void **)&cuda_key_arr, SIZE * sizeof(uint));
cudaMemcpy(cuda_key_arr, key_arr, SIZE * sizeof(uint),cudaMemcpyHostToDevice);
uint* cuda_value_arr;
cudaMalloc((void **)&cuda_value_arr, SIZE * sizeof(uint));
cudaMemcpy(cuda_value_arr, value_arr, SIZE * sizeof(uint),cudaMemcpyHostToDevice);
cudaEvent_t start, stop;
float gpuTime = 0.0f;
// printf("Elapsed time: %.2f\n", gpuTime);
// for(size_t i=0; i<SIZE; i++)
// {
// std::cout << key_arr[i] << " ";
// }
std::cout << std::endl;
cudaEventCreate (&start);
cudaEventCreate (&stop);
cudaEventRecord (start, 0);
bitonicSortShared<<<dim3(SIZE / (2 * BLOCK_SIZE)), dim3(BLOCK_SIZE)>>>(dst_key_arr,
dst_value_arr,
cuda_key_arr,
cuda_value_arr,
SIZE,
1);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&gpuTime, start, stop);
cudaMemcpy(value_arr, dst_value_arr, SIZE * sizeof(uint), cudaMemcpyDeviceToHost);
cudaMemcpy(key_arr, dst_key_arr, SIZE * sizeof(uint), cudaMemcpyDeviceToHost);
printf("Elapsed time: %.2f\n", gpuTime);
for(size_t i=0; i<SIZE-1; i++)
{
if (key_arr[i] > key_arr[i+1])
std::cout << "Error " << key_arr[i] << "> " << key_arr[i+1] << std::endl;
}
std::cout << std::endl;
delete [] key_arr;
cudaFree(cuda_key_arr);
cudaFree(cuda_value_arr);
cudaFree(dst_value_arr);
cudaFree(dst_key_arr);
} | #include <hip/hip_runtime.h>
#include <cstdio>
#include <cstdlib>
#include <iostream>
#include <cassert>
constexpr size_t BLOCK_SIZE = 1024; // Размер блока.
constexpr size_t SIZE = 2048;
// Отдельный компаратор сравнивает пару ключей
// и производит обмен соответствующих элементов и
// ключей для обеспечения заданного порядка.
__device__ void Comparator (uint& keyA, uint& valA, uint& keyB, uint& valB, uint dir) {
uint t;
// Поменять местами (keyA, valA) и (keyB, valB)
if ( (keyA > keyB) == dir ) {
t = keyA;
keyA = keyB;
keyB = t;
t = valA;
valA = valB;
valB = t;
}
}
__global__ void bitonicSortShared (uint* dstKey,
uint* dstVal,
uint* srcKey,
uint* srcVal,
uint arrayLength,
uint dir) {
__shared__ uint sk [BLOCK_SIZE * 2];
__shared__ uint sv [BLOCK_SIZE * 2];
int index = blockIdx.x * BLOCK_SIZE * 2 + threadIdx.x;
sk [threadIdx.x] = srcKey[index];
sv [threadIdx.x] = srcVal[index];
sk [threadIdx.x + BLOCK_SIZE] = srcKey [index + BLOCK_SIZE];
sv [threadIdx.x + BLOCK_SIZE] = srcVal [index + BLOCK_SIZE];
assert(threadIdx.x + BLOCK_SIZE < SIZE && index + BLOCK_SIZE < SIZE);
for (uint size = 2; size < arrayLength; size <<= 1u )
{
// Битоническое слияние
uint ddd = dir ^ ((threadIdx.x & (size / 2)) != 0);
for (uint stride = size >> 1u; stride > 0; stride >>= 1u)
{
__syncthreads ();
uint pos = 2 * threadIdx.x - (threadIdx.x & (stride - 1));
assert(pos + stride < 2 * BLOCK_SIZE);
Comparator( sk[pos], sv[pos], sk[pos+stride], sv[pos+stride], ddd);
}
__syncthreads();
}
for (uint stride = arrayLength >> 1u; stride > 0; stride >>= 1u)
{
__syncthreads ();
uint pos = 2 * threadIdx.x - (threadIdx.x & (stride - 1));
// assert(pos + stride < 2 * BLOCK_SIZE);
Comparator( sk[pos], sv[pos], sk[pos + stride], sv[pos+stride], dir);
// Comparator(srcKey[blockIdx.x * BLOCK_SIZE * 2 + pos], srcVal[blockIdx.x * BLOCK_SIZE * 2 + pos],
// srcKey[blockIdx.x * BLOCK_SIZE * 2 + pos + stride], srcVal[blockIdx.x * BLOCK_SIZE * 2 + pos + stride], dir);
}
__syncthreads ();
dstKey[index] = sk[threadIdx.x] ;
dstVal[index] = sv[threadIdx.x] ;
dstKey[index + BLOCK_SIZE] = sk[threadIdx.x + BLOCK_SIZE];
dstVal[index + BLOCK_SIZE] = sv[threadIdx.x + BLOCK_SIZE];
}
__host__ int main()
{
uint* key_arr = new uint[SIZE];
uint* value_arr = new uint[SIZE];
for (size_t i=0; i<SIZE; i++)
{
key_arr[i] = uint(rand()) % 100;
value_arr[i] = i;
}
uint* dst_key_arr = new uint[SIZE];
hipMalloc((void **)&dst_key_arr, SIZE * sizeof(uint));
uint* dst_value_arr = new uint[SIZE];
hipMalloc((void **)&dst_value_arr, SIZE * sizeof(uint));
uint* cuda_key_arr;
hipMalloc((void **)&cuda_key_arr, SIZE * sizeof(uint));
hipMemcpy(cuda_key_arr, key_arr, SIZE * sizeof(uint),hipMemcpyHostToDevice);
uint* cuda_value_arr;
hipMalloc((void **)&cuda_value_arr, SIZE * sizeof(uint));
hipMemcpy(cuda_value_arr, value_arr, SIZE * sizeof(uint),hipMemcpyHostToDevice);
hipEvent_t start, stop;
float gpuTime = 0.0f;
// printf("Elapsed time: %.2f\n", gpuTime);
// for(size_t i=0; i<SIZE; i++)
// {
// std::cout << key_arr[i] << " ";
// }
std::cout << std::endl;
hipEventCreate (&start);
hipEventCreate (&stop);
hipEventRecord (start, 0);
bitonicSortShared<<<dim3(SIZE / (2 * BLOCK_SIZE)), dim3(BLOCK_SIZE)>>>(dst_key_arr,
dst_value_arr,
cuda_key_arr,
cuda_value_arr,
SIZE,
1);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&gpuTime, start, stop);
hipMemcpy(value_arr, dst_value_arr, SIZE * sizeof(uint), hipMemcpyDeviceToHost);
hipMemcpy(key_arr, dst_key_arr, SIZE * sizeof(uint), hipMemcpyDeviceToHost);
printf("Elapsed time: %.2f\n", gpuTime);
for(size_t i=0; i<SIZE-1; i++)
{
if (key_arr[i] > key_arr[i+1])
std::cout << "Error " << key_arr[i] << "> " << key_arr[i+1] << std::endl;
}
std::cout << std::endl;
delete [] key_arr;
hipFree(cuda_key_arr);
hipFree(cuda_value_arr);
hipFree(dst_value_arr);
hipFree(dst_key_arr);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
#include <cstdlib>
#include <iostream>
#include <cassert>
constexpr size_t BLOCK_SIZE = 1024; // Размер блока.
constexpr size_t SIZE = 2048;
// Отдельный компаратор сравнивает пару ключей
// и производит обмен соответствующих элементов и
// ключей для обеспечения заданного порядка.
__device__ void Comparator (uint& keyA, uint& valA, uint& keyB, uint& valB, uint dir) {
uint t;
// Поменять местами (keyA, valA) и (keyB, valB)
if ( (keyA > keyB) == dir ) {
t = keyA;
keyA = keyB;
keyB = t;
t = valA;
valA = valB;
valB = t;
}
}
__global__ void bitonicSortShared (uint* dstKey,
uint* dstVal,
uint* srcKey,
uint* srcVal,
uint arrayLength,
uint dir) {
__shared__ uint sk [BLOCK_SIZE * 2];
__shared__ uint sv [BLOCK_SIZE * 2];
int index = blockIdx.x * BLOCK_SIZE * 2 + threadIdx.x;
sk [threadIdx.x] = srcKey[index];
sv [threadIdx.x] = srcVal[index];
sk [threadIdx.x + BLOCK_SIZE] = srcKey [index + BLOCK_SIZE];
sv [threadIdx.x + BLOCK_SIZE] = srcVal [index + BLOCK_SIZE];
assert(threadIdx.x + BLOCK_SIZE < SIZE && index + BLOCK_SIZE < SIZE);
for (uint size = 2; size < arrayLength; size <<= 1u )
{
// Битоническое слияние
uint ddd = dir ^ ((threadIdx.x & (size / 2)) != 0);
for (uint stride = size >> 1u; stride > 0; stride >>= 1u)
{
__syncthreads ();
uint pos = 2 * threadIdx.x - (threadIdx.x & (stride - 1));
assert(pos + stride < 2 * BLOCK_SIZE);
Comparator( sk[pos], sv[pos], sk[pos+stride], sv[pos+stride], ddd);
}
__syncthreads();
}
for (uint stride = arrayLength >> 1u; stride > 0; stride >>= 1u)
{
__syncthreads ();
uint pos = 2 * threadIdx.x - (threadIdx.x & (stride - 1));
// assert(pos + stride < 2 * BLOCK_SIZE);
Comparator( sk[pos], sv[pos], sk[pos + stride], sv[pos+stride], dir);
// Comparator(srcKey[blockIdx.x * BLOCK_SIZE * 2 + pos], srcVal[blockIdx.x * BLOCK_SIZE * 2 + pos],
// srcKey[blockIdx.x * BLOCK_SIZE * 2 + pos + stride], srcVal[blockIdx.x * BLOCK_SIZE * 2 + pos + stride], dir);
}
__syncthreads ();
dstKey[index] = sk[threadIdx.x] ;
dstVal[index] = sv[threadIdx.x] ;
dstKey[index + BLOCK_SIZE] = sk[threadIdx.x + BLOCK_SIZE];
dstVal[index + BLOCK_SIZE] = sv[threadIdx.x + BLOCK_SIZE];
}
__host__ int main()
{
uint* key_arr = new uint[SIZE];
uint* value_arr = new uint[SIZE];
for (size_t i=0; i<SIZE; i++)
{
key_arr[i] = uint(rand()) % 100;
value_arr[i] = i;
}
uint* dst_key_arr = new uint[SIZE];
hipMalloc((void **)&dst_key_arr, SIZE * sizeof(uint));
uint* dst_value_arr = new uint[SIZE];
hipMalloc((void **)&dst_value_arr, SIZE * sizeof(uint));
uint* cuda_key_arr;
hipMalloc((void **)&cuda_key_arr, SIZE * sizeof(uint));
hipMemcpy(cuda_key_arr, key_arr, SIZE * sizeof(uint),hipMemcpyHostToDevice);
uint* cuda_value_arr;
hipMalloc((void **)&cuda_value_arr, SIZE * sizeof(uint));
hipMemcpy(cuda_value_arr, value_arr, SIZE * sizeof(uint),hipMemcpyHostToDevice);
hipEvent_t start, stop;
float gpuTime = 0.0f;
// printf("Elapsed time: %.2f\n", gpuTime);
// for(size_t i=0; i<SIZE; i++)
// {
// std::cout << key_arr[i] << " ";
// }
std::cout << std::endl;
hipEventCreate (&start);
hipEventCreate (&stop);
hipEventRecord (start, 0);
bitonicSortShared<<<dim3(SIZE / (2 * BLOCK_SIZE)), dim3(BLOCK_SIZE)>>>(dst_key_arr,
dst_value_arr,
cuda_key_arr,
cuda_value_arr,
SIZE,
1);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&gpuTime, start, stop);
hipMemcpy(value_arr, dst_value_arr, SIZE * sizeof(uint), hipMemcpyDeviceToHost);
hipMemcpy(key_arr, dst_key_arr, SIZE * sizeof(uint), hipMemcpyDeviceToHost);
printf("Elapsed time: %.2f\n", gpuTime);
for(size_t i=0; i<SIZE-1; i++)
{
if (key_arr[i] > key_arr[i+1])
std::cout << "Error " << key_arr[i] << "> " << key_arr[i+1] << std::endl;
}
std::cout << std::endl;
delete [] key_arr;
hipFree(cuda_key_arr);
hipFree(cuda_value_arr);
hipFree(dst_value_arr);
hipFree(dst_key_arr);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17bitonicSortSharedPjS_S_S_jj
.globl _Z17bitonicSortSharedPjS_S_S_jj
.p2align 8
.type _Z17bitonicSortSharedPjS_S_S_jj,@function
_Z17bitonicSortSharedPjS_S_S_jj:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x20
v_lshl_or_b32 v1, s15, 11, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_or_b32_e32 v3, 0x400, v1
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_mov_b32_e32 v4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[7:8], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v6, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
v_add_co_u32 v11, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v8, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v9, v[9:10], off
global_load_b32 v6, v[5:6], off
global_load_b32 v10, v[11:12], off
global_load_b32 v7, v[7:8], off
v_lshlrev_b32_e32 v5, 2, v0
s_mov_b32 s4, 2
s_cmp_lt_u32 s2, 3
s_waitcnt vmcnt(1)
ds_store_2addr_stride64_b32 v5, v9, v10 offset1:16
s_waitcnt vmcnt(0)
ds_store_2addr_stride64_b32 v5, v6, v7 offset0:32 offset1:48
s_cbranch_scc1 .LBB0_8
v_lshlrev_b32_e32 v6, 1, v0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_lshl_b32 s4, s4, 1
s_waitcnt lgkmcnt(0)
s_cmp_ge_u32 s4, s2
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_8
.LBB0_3:
s_cmp_eq_u32 s4, 0
s_cbranch_scc1 .LBB0_2
s_lshr_b32 s5, s4, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v7, s5, v0
s_mov_b32 s5, s4
v_cmp_ne_u32_e32 vcc_lo, 0, v7
v_cndmask_b32_e64 v7, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_xor_b32_e32 v7, s3, v7
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s7
s_cmp_lt_u32 s5, 4
s_mov_b32 s5, s6
s_cbranch_scc1 .LBB0_2
.LBB0_6:
s_lshr_b32 s6, s5, 1
s_waitcnt lgkmcnt(0)
s_add_i32 s7, s6, -1
s_barrier
v_and_b32_e32 v8, s7, v0
buffer_gl0_inv
s_mov_b32 s7, exec_lo
v_sub_nc_u32_e32 v8, v6, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v9, s6, v8
v_lshlrev_b32_e32 v8, 2, v8
v_lshlrev_b32_e32 v9, 2, v9
ds_load_b32 v10, v8
ds_load_b32 v11, v9
s_waitcnt lgkmcnt(0)
v_cmp_gt_u32_e32 vcc_lo, v10, v11
v_cndmask_b32_e64 v12, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e64 v7, v12
s_cbranch_execz .LBB0_5
ds_load_b32 v12, v9 offset:8192
ds_load_b32 v13, v8 offset:8192
ds_store_b32 v8, v11
s_waitcnt lgkmcnt(2)
ds_store_b32 v8, v12 offset:8192
s_waitcnt lgkmcnt(2)
ds_store_2addr_stride64_b32 v9, v10, v13 offset1:32
s_branch .LBB0_5
.LBB0_8:
s_set_inst_prefetch_distance 0x2
v_or_b32_e32 v7, 0x2000, v5
v_or_b32_e32 v8, 0x1000, v5
v_or_b32_e32 v6, 0x3000, v5
s_cmp_lt_u32 s2, 2
s_cbranch_scc1 .LBB0_13
v_lshlrev_b32_e32 v9, 1, v0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_11
.p2align 6
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s5
s_cmp_lt_u32 s2, 4
s_mov_b32 s2, s4
s_cbranch_scc1 .LBB0_13
.LBB0_11:
s_lshr_b32 s4, s2, 1
s_waitcnt lgkmcnt(0)
s_add_i32 s5, s4, -1
s_barrier
v_and_b32_e32 v10, s5, v0
buffer_gl0_inv
s_mov_b32 s5, exec_lo
v_sub_nc_u32_e32 v10, v9, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v11, s4, v10
v_lshlrev_b32_e32 v10, 2, v10
v_lshlrev_b32_e32 v11, 2, v11
ds_load_b32 v12, v10
ds_load_b32 v13, v11
s_waitcnt lgkmcnt(0)
v_cmp_gt_u32_e32 vcc_lo, v12, v13
v_cndmask_b32_e64 v14, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e64 s3, v14
s_cbranch_execz .LBB0_10
ds_load_b32 v14, v11 offset:8192
ds_load_b32 v15, v10 offset:8192
ds_store_b32 v10, v13
s_waitcnt lgkmcnt(2)
ds_store_b32 v10, v14 offset:8192
s_waitcnt lgkmcnt(2)
ds_store_2addr_stride64_b32 v11, v12, v15 offset1:32
s_branch .LBB0_10
.LBB0_13:
s_set_inst_prefetch_distance 0x2
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v9, v5
ds_load_b32 v10, v7
ds_load_b32 v8, v8
ds_load_b32 v11, v6
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_lshlrev_b64 v[2:3], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v6, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_waitcnt lgkmcnt(3)
global_store_b32 v[4:5], v9, off
s_waitcnt lgkmcnt(2)
global_store_b32 v[0:1], v10, off
s_waitcnt lgkmcnt(1)
global_store_b32 v[6:7], v8, off
s_waitcnt lgkmcnt(0)
global_store_b32 v[2:3], v11, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17bitonicSortSharedPjS_S_S_jj
.amdhsa_group_segment_fixed_size 16384
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17bitonicSortSharedPjS_S_S_jj, .Lfunc_end0-_Z17bitonicSortSharedPjS_S_S_jj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 16384
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17bitonicSortSharedPjS_S_S_jj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17bitonicSortSharedPjS_S_S_jj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
#include <cstdlib>
#include <iostream>
#include <cassert>
constexpr size_t BLOCK_SIZE = 1024; // Размер блока.
constexpr size_t SIZE = 2048;
// Отдельный компаратор сравнивает пару ключей
// и производит обмен соответствующих элементов и
// ключей для обеспечения заданного порядка.
__device__ void Comparator (uint& keyA, uint& valA, uint& keyB, uint& valB, uint dir) {
uint t;
// Поменять местами (keyA, valA) и (keyB, valB)
if ( (keyA > keyB) == dir ) {
t = keyA;
keyA = keyB;
keyB = t;
t = valA;
valA = valB;
valB = t;
}
}
__global__ void bitonicSortShared (uint* dstKey,
uint* dstVal,
uint* srcKey,
uint* srcVal,
uint arrayLength,
uint dir) {
__shared__ uint sk [BLOCK_SIZE * 2];
__shared__ uint sv [BLOCK_SIZE * 2];
int index = blockIdx.x * BLOCK_SIZE * 2 + threadIdx.x;
sk [threadIdx.x] = srcKey[index];
sv [threadIdx.x] = srcVal[index];
sk [threadIdx.x + BLOCK_SIZE] = srcKey [index + BLOCK_SIZE];
sv [threadIdx.x + BLOCK_SIZE] = srcVal [index + BLOCK_SIZE];
assert(threadIdx.x + BLOCK_SIZE < SIZE && index + BLOCK_SIZE < SIZE);
for (uint size = 2; size < arrayLength; size <<= 1u )
{
// Битоническое слияние
uint ddd = dir ^ ((threadIdx.x & (size / 2)) != 0);
for (uint stride = size >> 1u; stride > 0; stride >>= 1u)
{
__syncthreads ();
uint pos = 2 * threadIdx.x - (threadIdx.x & (stride - 1));
assert(pos + stride < 2 * BLOCK_SIZE);
Comparator( sk[pos], sv[pos], sk[pos+stride], sv[pos+stride], ddd);
}
__syncthreads();
}
for (uint stride = arrayLength >> 1u; stride > 0; stride >>= 1u)
{
__syncthreads ();
uint pos = 2 * threadIdx.x - (threadIdx.x & (stride - 1));
// assert(pos + stride < 2 * BLOCK_SIZE);
Comparator( sk[pos], sv[pos], sk[pos + stride], sv[pos+stride], dir);
// Comparator(srcKey[blockIdx.x * BLOCK_SIZE * 2 + pos], srcVal[blockIdx.x * BLOCK_SIZE * 2 + pos],
// srcKey[blockIdx.x * BLOCK_SIZE * 2 + pos + stride], srcVal[blockIdx.x * BLOCK_SIZE * 2 + pos + stride], dir);
}
__syncthreads ();
dstKey[index] = sk[threadIdx.x] ;
dstVal[index] = sv[threadIdx.x] ;
dstKey[index + BLOCK_SIZE] = sk[threadIdx.x + BLOCK_SIZE];
dstVal[index + BLOCK_SIZE] = sv[threadIdx.x + BLOCK_SIZE];
}
__host__ int main()
{
uint* key_arr = new uint[SIZE];
uint* value_arr = new uint[SIZE];
for (size_t i=0; i<SIZE; i++)
{
key_arr[i] = uint(rand()) % 100;
value_arr[i] = i;
}
uint* dst_key_arr = new uint[SIZE];
hipMalloc((void **)&dst_key_arr, SIZE * sizeof(uint));
uint* dst_value_arr = new uint[SIZE];
hipMalloc((void **)&dst_value_arr, SIZE * sizeof(uint));
uint* cuda_key_arr;
hipMalloc((void **)&cuda_key_arr, SIZE * sizeof(uint));
hipMemcpy(cuda_key_arr, key_arr, SIZE * sizeof(uint),hipMemcpyHostToDevice);
uint* cuda_value_arr;
hipMalloc((void **)&cuda_value_arr, SIZE * sizeof(uint));
hipMemcpy(cuda_value_arr, value_arr, SIZE * sizeof(uint),hipMemcpyHostToDevice);
hipEvent_t start, stop;
float gpuTime = 0.0f;
// printf("Elapsed time: %.2f\n", gpuTime);
// for(size_t i=0; i<SIZE; i++)
// {
// std::cout << key_arr[i] << " ";
// }
std::cout << std::endl;
hipEventCreate (&start);
hipEventCreate (&stop);
hipEventRecord (start, 0);
bitonicSortShared<<<dim3(SIZE / (2 * BLOCK_SIZE)), dim3(BLOCK_SIZE)>>>(dst_key_arr,
dst_value_arr,
cuda_key_arr,
cuda_value_arr,
SIZE,
1);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&gpuTime, start, stop);
hipMemcpy(value_arr, dst_value_arr, SIZE * sizeof(uint), hipMemcpyDeviceToHost);
hipMemcpy(key_arr, dst_key_arr, SIZE * sizeof(uint), hipMemcpyDeviceToHost);
printf("Elapsed time: %.2f\n", gpuTime);
for(size_t i=0; i<SIZE-1; i++)
{
if (key_arr[i] > key_arr[i+1])
std::cout << "Error " << key_arr[i] << "> " << key_arr[i+1] << std::endl;
}
std::cout << std::endl;
delete [] key_arr;
hipFree(cuda_key_arr);
hipFree(cuda_value_arr);
hipFree(dst_value_arr);
hipFree(dst_key_arr);
} | .text
.file "lab5.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z32__device_stub__bitonicSortSharedPjS_S_S_jj # -- Begin function _Z32__device_stub__bitonicSortSharedPjS_S_S_jj
.p2align 4, 0x90
.type _Z32__device_stub__bitonicSortSharedPjS_S_S_jj,@function
_Z32__device_stub__bitonicSortSharedPjS_S_S_jj: # @_Z32__device_stub__bitonicSortSharedPjS_S_S_jj
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17bitonicSortSharedPjS_S_S_jj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z32__device_stub__bitonicSortSharedPjS_S_S_jj, .Lfunc_end0-_Z32__device_stub__bitonicSortSharedPjS_S_S_jj
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $200, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $8192, %edi # imm = 0x2000
callq _Znam
movq %rax, %rbx
movl $8192, %edi # imm = 0x2000
callq _Znam
movq %rax, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
movl %eax, %ecx
imulq $1374389535, %rcx, %rcx # imm = 0x51EB851F
shrq $37, %rcx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
movl %r15d, (%r14,%r15,4)
incq %r15
cmpq $2048, %r15 # imm = 0x800
jne .LBB1_1
# %bb.2:
movl $8192, %edi # imm = 0x2000
callq _Znam
movq %rax, 16(%rsp)
leaq 16(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
movl $8192, %edi # imm = 0x2000
callq _Znam
movq %rax, 8(%rsp)
leaq 8(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
leaq 40(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
movq 40(%rsp), %rdi
movl $8192, %edx # imm = 0x2000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 32(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
movq 32(%rsp), %rdi
movl $8192, %edx # imm = 0x2000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movl $0, 4(%rsp)
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB1_21
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB1_5
# %bb.4:
movzbl 67(%r15), %eax
jmp .LBB1_6
.LBB1_5:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 56(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movq 56(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 1023(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movq %rsi, 112(%rsp)
movl $2048, 52(%rsp) # imm = 0x800
movl $1, 48(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 112(%rsp), %rax
movq %rax, 168(%rsp)
leaq 52(%rsp), %rax
movq %rax, 176(%rsp)
leaq 48(%rsp), %rax
movq %rax, 184(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z17bitonicSortSharedPjS_S_S_jj, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 56(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movq 8(%rsp), %rsi
movl $8192, %edx # imm = 0x2000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rsi
movl $8192, %edx # imm = 0x2000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movl $1, %r15d
jmp .LBB1_9
.LBB1_18: # in Loop: Header=BB1_9 Depth=1
movq %r14, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB1_19: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit34
# in Loop: Header=BB1_9 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_20: # in Loop: Header=BB1_9 Depth=1
incq %r15
cmpq $2048, %r15 # imm = 0x800
je .LBB1_13
.LBB1_9: # =>This Inner Loop Header: Depth=1
movl -4(%rbx,%r15,4), %eax
cmpl (%rbx,%r15,4), %eax
jbe .LBB1_20
# %bb.10: # in Loop: Header=BB1_9 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl -4(%rbx,%r15,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %r14
movl $.L.str.2, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%rbx,%r15,4), %esi
movq %r14, %rdi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_21
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i31
# in Loop: Header=BB1_9 Depth=1
cmpb $0, 56(%r14)
je .LBB1_18
# %bb.12: # in Loop: Header=BB1_9 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB1_19
.LBB1_13:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB1_21
# %bb.14: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i26
cmpb $0, 56(%r14)
je .LBB1_16
# %bb.15:
movzbl 67(%r14), %eax
jmp .LBB1_17
.LBB1_16:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_17: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit29
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq _ZdaPv
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_21:
.cfi_def_cfa_offset 240
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17bitonicSortSharedPjS_S_S_jj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17bitonicSortSharedPjS_S_S_jj,@object # @_Z17bitonicSortSharedPjS_S_S_jj
.section .rodata,"a",@progbits
.globl _Z17bitonicSortSharedPjS_S_S_jj
.p2align 3, 0x0
_Z17bitonicSortSharedPjS_S_S_jj:
.quad _Z32__device_stub__bitonicSortSharedPjS_S_S_jj
.size _Z17bitonicSortSharedPjS_S_S_jj, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Elapsed time: %.2f\n"
.size .L.str, 20
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error "
.size .L.str.1, 7
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "> "
.size .L.str.2, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z17bitonicSortSharedPjS_S_S_jj"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__bitonicSortSharedPjS_S_S_jj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17bitonicSortSharedPjS_S_S_jj
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17bitonicSortSharedPjS_S_S_jj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R3, 0x800, R2 ; /* 0x0000080003007824 */
/* 0x001fc800078e0202 */
/*0060*/ IMAD.WIDE R4, R0, R7, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R6, R0, R7, c[0x0][0x178] ; /* 0x00005e0000067625 */
/* 0x000fe200078e0207 */
/*0080*/ LDG.E R3, [R4.64] ; /* 0x0000000604037981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R11, [R4.64+0x1000] ; /* 0x00100006040b7981 */
/* 0x000ee8000c1e1900 */
/*00a0*/ LDG.E R9, [R6.64] ; /* 0x0000000606097981 */
/* 0x000f28000c1e1900 */
/*00b0*/ LDG.E R13, [R6.64+0x1000] ; /* 0x00100006060d7981 */
/* 0x000f62000c1e1900 */
/*00c0*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff087624 */
/* 0x000fca00078e00ff */
/*00d0*/ ISETP.GE.U32.AND P0, PT, R8, 0x3, PT ; /* 0x000000030800780c */
/* 0x000fe20003f06070 */
/*00e0*/ STS [R2.X4], R3 ; /* 0x0000000302007388 */
/* 0x0041e80000004800 */
/*00f0*/ STS [R2.X4+0x1000], R11 ; /* 0x0010000b02007388 */
/* 0x0081e80000004800 */
/*0100*/ STS [R2.X4+0x2000], R9 ; /* 0x0020000902007388 */
/* 0x0101e80000004800 */
/*0110*/ STS [R2.X4+0x3000], R13 ; /* 0x0030000d02007388 */
/* 0x0201e20000004800 */
/*0120*/ @!P0 BRA 0x320 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0130*/ IMAD.MOV.U32 R10, RZ, RZ, 0x2 ; /* 0x00000002ff0a7424 */
/* 0x000fca00078e00ff */
/*0140*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f05270 */
/*0150*/ @!P0 BRA 0x2e0 ; /* 0x0000018000008947 */
/* 0x001fea0003800000 */
/*0160*/ SHF.R.U32.HI R3, RZ, 0x1, R10 ; /* 0x00000001ff037819 */
/* 0x001fc8000001160a */
/*0170*/ LOP3.LUT P0, RZ, R3, R2, RZ, 0xc0, !PT ; /* 0x0000000203ff7212 */
/* 0x000fc8000780c0ff */
/*0180*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*0190*/ LOP3.LUT R7, R4, c[0x0][0x184], RZ, 0x3c, !PT ; /* 0x0000610004077a12 */
/* 0x000fe400078e3cff */
/*01a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01b0*/ IADD3 R5, R3, -0x1, RZ ; /* 0xffffffff03057810 */
/* 0x000fc80007ffe0ff */
/*01c0*/ LOP3.LUT R5, R5, R2, RZ, 0xc0, !PT ; /* 0x0000000205057212 */
/* 0x000fca00078ec0ff */
/*01d0*/ IMAD R5, R2, 0x2, -R5 ; /* 0x0000000202057824 */
/* 0x000fc800078e0a05 */
/*01e0*/ IMAD.SHL.U32 R6, R5, 0x4, RZ ; /* 0x0000000405067824 */
/* 0x000fc800078e00ff */
/*01f0*/ IMAD R9, R3, 0x4, R6 ; /* 0x0000000403097824 */
/* 0x000fe200078e0206 */
/*0200*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fe20000011603 */
/*0210*/ LDS R8, [R6] ; /* 0x0000000006087984 */
/* 0x000fe80000000800 */
/*0220*/ LDS R11, [R9] ; /* 0x00000000090b7984 */
/* 0x000e240000000800 */
/*0230*/ ISETP.GT.U32.AND P0, PT, R8, R11, PT ; /* 0x0000000b0800720c */
/* 0x001fc80003f04070 */
/*0240*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*0250*/ ISETP.NE.AND P0, PT, R7, R4, PT ; /* 0x000000040700720c */
/* 0x000fda0003f05270 */
/*0260*/ @!P0 STS [R6], R11 ; /* 0x0000000b06008388 */
/* 0x000fe80000000800 */
/*0270*/ @!P0 STS [R9], R8 ; /* 0x0000000809008388 */
/* 0x000fe80000000800 */
/*0280*/ @!P0 LDS R5, [R9+0x2000] ; /* 0x0020000009058984 */
/* 0x000e280000000800 */
/*0290*/ @!P0 LDS R4, [R6+0x2000] ; /* 0x0020000006048984 */
/* 0x000e680000000800 */
/*02a0*/ @!P0 STS [R6+0x2000], R5 ; /* 0x0020000506008388 */
/* 0x0011e80000000800 */
/*02b0*/ @!P0 STS [R9+0x2000], R4 ; /* 0x0020000409008388 */
/* 0x0021e20000000800 */
/*02c0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*02d0*/ @P0 BRA 0x1a0 ; /* 0xfffffec000000947 */
/* 0x001fea000383ffff */
/*02e0*/ IMAD.SHL.U32 R10, R10, 0x2, RZ ; /* 0x000000020a0a7824 */
/* 0x000fe200078e00ff */
/*02f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe80000010000 */
/*0300*/ ISETP.GE.U32.AND P0, PT, R10, c[0x0][0x180], PT ; /* 0x000060000a007a0c */
/* 0x000fda0003f06070 */
/*0310*/ @!P0 BRA 0x140 ; /* 0xfffffe2000008947 */
/* 0x000fea000383ffff */
/*0320*/ ULDC UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fe40000000800 */
/*0330*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*0340*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf05270 */
/*0350*/ @!P0 BRA 0x4b0 ; /* 0x0000015000008947 */
/* 0x000fea0003800000 */
/*0360*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x001fc8000f8e00ff */
/*0370*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0380*/ IADD3 R5, R3, -0x1, RZ ; /* 0xffffffff03057810 */
/* 0x000fc80007ffe0ff */
/*0390*/ LOP3.LUT R5, R5, R2, RZ, 0xc0, !PT ; /* 0x0000000205057212 */
/* 0x000fca00078ec0ff */
/*03a0*/ IMAD R5, R2, 0x2, -R5 ; /* 0x0000000202057824 */
/* 0x000fc800078e0a05 */
/*03b0*/ IMAD.SHL.U32 R6, R5, 0x4, RZ ; /* 0x0000000405067824 */
/* 0x000fc800078e00ff */
/*03c0*/ IMAD R7, R3, 0x4, R6 ; /* 0x0000000403077824 */
/* 0x000fe200078e0206 */
/*03d0*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fe20000011603 */
/*03e0*/ LDS R8, [R6] ; /* 0x0000000006087984 */
/* 0x000fe80000000800 */
/*03f0*/ LDS R9, [R7] ; /* 0x0000000007097984 */
/* 0x000e240000000800 */
/*0400*/ ISETP.GT.U32.AND P0, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x001fc80003f04070 */
/*0410*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*0420*/ ISETP.NE.AND P0, PT, R4, c[0x0][0x184], PT ; /* 0x0000610004007a0c */
/* 0x000fda0003f05270 */
/*0430*/ @!P0 STS [R6], R9 ; /* 0x0000000906008388 */
/* 0x000fe80000000800 */
/*0440*/ @!P0 STS [R7], R8 ; /* 0x0000000807008388 */
/* 0x000fe80000000800 */
/*0450*/ @!P0 LDS R5, [R7+0x2000] ; /* 0x0020000007058984 */
/* 0x000e280000000800 */
/*0460*/ @!P0 LDS R4, [R6+0x2000] ; /* 0x0020000006048984 */
/* 0x000e680000000800 */
/*0470*/ @!P0 STS [R6+0x2000], R5 ; /* 0x0020000506008388 */
/* 0x0011e80000000800 */
/*0480*/ @!P0 STS [R7+0x2000], R4 ; /* 0x0020000407008388 */
/* 0x0021e20000000800 */
/*0490*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*04a0*/ @P0 BRA 0x370 ; /* 0xfffffec000000947 */
/* 0x001fea000383ffff */
/*04b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*04c0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fc800078e00ff */
/*04d0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc800078e0207 */
/*04e0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x000fe200078e0207 */
/*04f0*/ LDS R3, [R2.X4] ; /* 0x0000000002037984 */
/* 0x001e280000004800 */
/*0500*/ LDS R9, [R2.X4+0x2000] ; /* 0x0020000002097984 */
/* 0x000e680000004800 */
/*0510*/ LDS R11, [R2.X4+0x1000] ; /* 0x00100000020b7984 */
/* 0x000ea80000004800 */
/*0520*/ LDS R13, [R2.X4+0x3000] ; /* 0x00300000020d7984 */
/* 0x000ee80000004800 */
/*0530*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x001fe8000c101906 */
/*0540*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x002fe8000c101906 */
/*0550*/ STG.E [R4.64+0x1000], R11 ; /* 0x0010000b04007986 */
/* 0x004fe8000c101906 */
/*0560*/ STG.E [R6.64+0x1000], R13 ; /* 0x0010000d06007986 */
/* 0x008fe2000c101906 */
/*0570*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0580*/ BRA 0x580; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17bitonicSortSharedPjS_S_S_jj
.globl _Z17bitonicSortSharedPjS_S_S_jj
.p2align 8
.type _Z17bitonicSortSharedPjS_S_S_jj,@function
_Z17bitonicSortSharedPjS_S_S_jj:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x20
v_lshl_or_b32 v1, s15, 11, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_or_b32_e32 v3, 0x400, v1
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_mov_b32_e32 v4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[7:8], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v6, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
v_add_co_u32 v11, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v8, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v9, v[9:10], off
global_load_b32 v6, v[5:6], off
global_load_b32 v10, v[11:12], off
global_load_b32 v7, v[7:8], off
v_lshlrev_b32_e32 v5, 2, v0
s_mov_b32 s4, 2
s_cmp_lt_u32 s2, 3
s_waitcnt vmcnt(1)
ds_store_2addr_stride64_b32 v5, v9, v10 offset1:16
s_waitcnt vmcnt(0)
ds_store_2addr_stride64_b32 v5, v6, v7 offset0:32 offset1:48
s_cbranch_scc1 .LBB0_8
v_lshlrev_b32_e32 v6, 1, v0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_lshl_b32 s4, s4, 1
s_waitcnt lgkmcnt(0)
s_cmp_ge_u32 s4, s2
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_8
.LBB0_3:
s_cmp_eq_u32 s4, 0
s_cbranch_scc1 .LBB0_2
s_lshr_b32 s5, s4, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v7, s5, v0
s_mov_b32 s5, s4
v_cmp_ne_u32_e32 vcc_lo, 0, v7
v_cndmask_b32_e64 v7, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_xor_b32_e32 v7, s3, v7
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s7
s_cmp_lt_u32 s5, 4
s_mov_b32 s5, s6
s_cbranch_scc1 .LBB0_2
.LBB0_6:
s_lshr_b32 s6, s5, 1
s_waitcnt lgkmcnt(0)
s_add_i32 s7, s6, -1
s_barrier
v_and_b32_e32 v8, s7, v0
buffer_gl0_inv
s_mov_b32 s7, exec_lo
v_sub_nc_u32_e32 v8, v6, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v9, s6, v8
v_lshlrev_b32_e32 v8, 2, v8
v_lshlrev_b32_e32 v9, 2, v9
ds_load_b32 v10, v8
ds_load_b32 v11, v9
s_waitcnt lgkmcnt(0)
v_cmp_gt_u32_e32 vcc_lo, v10, v11
v_cndmask_b32_e64 v12, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e64 v7, v12
s_cbranch_execz .LBB0_5
ds_load_b32 v12, v9 offset:8192
ds_load_b32 v13, v8 offset:8192
ds_store_b32 v8, v11
s_waitcnt lgkmcnt(2)
ds_store_b32 v8, v12 offset:8192
s_waitcnt lgkmcnt(2)
ds_store_2addr_stride64_b32 v9, v10, v13 offset1:32
s_branch .LBB0_5
.LBB0_8:
s_set_inst_prefetch_distance 0x2
v_or_b32_e32 v7, 0x2000, v5
v_or_b32_e32 v8, 0x1000, v5
v_or_b32_e32 v6, 0x3000, v5
s_cmp_lt_u32 s2, 2
s_cbranch_scc1 .LBB0_13
v_lshlrev_b32_e32 v9, 1, v0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_11
.p2align 6
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s5
s_cmp_lt_u32 s2, 4
s_mov_b32 s2, s4
s_cbranch_scc1 .LBB0_13
.LBB0_11:
s_lshr_b32 s4, s2, 1
s_waitcnt lgkmcnt(0)
s_add_i32 s5, s4, -1
s_barrier
v_and_b32_e32 v10, s5, v0
buffer_gl0_inv
s_mov_b32 s5, exec_lo
v_sub_nc_u32_e32 v10, v9, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v11, s4, v10
v_lshlrev_b32_e32 v10, 2, v10
v_lshlrev_b32_e32 v11, 2, v11
ds_load_b32 v12, v10
ds_load_b32 v13, v11
s_waitcnt lgkmcnt(0)
v_cmp_gt_u32_e32 vcc_lo, v12, v13
v_cndmask_b32_e64 v14, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e64 s3, v14
s_cbranch_execz .LBB0_10
ds_load_b32 v14, v11 offset:8192
ds_load_b32 v15, v10 offset:8192
ds_store_b32 v10, v13
s_waitcnt lgkmcnt(2)
ds_store_b32 v10, v14 offset:8192
s_waitcnt lgkmcnt(2)
ds_store_2addr_stride64_b32 v11, v12, v15 offset1:32
s_branch .LBB0_10
.LBB0_13:
s_set_inst_prefetch_distance 0x2
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v9, v5
ds_load_b32 v10, v7
ds_load_b32 v8, v8
ds_load_b32 v11, v6
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_lshlrev_b64 v[2:3], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v6, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_waitcnt lgkmcnt(3)
global_store_b32 v[4:5], v9, off
s_waitcnt lgkmcnt(2)
global_store_b32 v[0:1], v10, off
s_waitcnt lgkmcnt(1)
global_store_b32 v[6:7], v8, off
s_waitcnt lgkmcnt(0)
global_store_b32 v[2:3], v11, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17bitonicSortSharedPjS_S_S_jj
.amdhsa_group_segment_fixed_size 16384
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17bitonicSortSharedPjS_S_S_jj, .Lfunc_end0-_Z17bitonicSortSharedPjS_S_S_jj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 16384
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17bitonicSortSharedPjS_S_S_jj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17bitonicSortSharedPjS_S_S_jj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f8163_00000000-6_lab5.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10ComparatorRjS_S_S_j
.type _Z10ComparatorRjS_S_S_j, @function
_Z10ComparatorRjS_S_S_j:
.LFB3669:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z10ComparatorRjS_S_S_j, .-_Z10ComparatorRjS_S_S_j
.globl _Z45__device_stub__Z17bitonicSortSharedPjS_S_S_jjPjS_S_S_jj
.type _Z45__device_stub__Z17bitonicSortSharedPjS_S_S_jjPjS_S_S_jj, @function
_Z45__device_stub__Z17bitonicSortSharedPjS_S_S_jjPjS_S_S_jj:
.LFB3695:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z17bitonicSortSharedPjS_S_S_jj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z45__device_stub__Z17bitonicSortSharedPjS_S_S_jjPjS_S_S_jj, .-_Z45__device_stub__Z17bitonicSortSharedPjS_S_S_jjPjS_S_S_jj
.globl _Z17bitonicSortSharedPjS_S_S_jj
.type _Z17bitonicSortSharedPjS_S_S_jj, @function
_Z17bitonicSortSharedPjS_S_S_jj:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z17bitonicSortSharedPjS_S_S_jjPjS_S_S_jj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z17bitonicSortSharedPjS_S_S_jj, .-_Z17bitonicSortSharedPjS_S_S_jj
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Elapsed time: %.2f\n"
.LC2:
.string "Error "
.LC3:
.string "> "
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $8192, %edi
call _Znam@PLT
movq %rax, %r13
movl $8192, %edi
call _Znam@PLT
movq %rax, %rbp
movl $0, %ebx
.L14:
call rand@PLT
movl %eax, %edx
imulq $1374389535, %rdx, %rdx
shrq $37, %rdx
imull $100, %edx, %edx
subl %edx, %eax
movl %eax, 0(%r13,%rbx,4)
movl %ebx, 0(%rbp,%rbx,4)
addq $1, %rbx
cmpq $2048, %rbx
jne .L14
movl $8192, %edi
call _Znam@PLT
movq %rax, 16(%rsp)
leaq 16(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
movl $8192, %edi
call _Znam@PLT
movq %rax, 24(%rsp)
leaq 24(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $8192, %edx
movq %r13, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
leaq 40(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $8192, %edx
movq %rbp, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $0x00000000, 12(%rsp)
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $1024, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L15:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $2, %ecx
movl $8192, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $8192, %edx
movq 16(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r13, %rbx
leaq 8188(%r13), %r14
leaq _ZSt4cout(%rip), %r15
jmp .L21
.L26:
movl $1, %r9d
movl $2048, %r8d
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z45__device_stub__Z17bitonicSortSharedPjS_S_S_jjPjS_S_S_jj
jmp .L15
.L29:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L27
call _ZSt16__throw_bad_castv@PLT
.L27:
call __stack_chk_fail@PLT
.L30:
movzbl 67(%r12), %esi
.L20:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.L16:
addq $4, %rbx
cmpq %r14, %rbx
je .L28
.L21:
movl (%rbx), %eax
cmpl %eax, 4(%rbx)
jnb .L16
movl $6, %edx
leaq .LC2(%rip), %rsi
movq %r15, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl (%rbx), %esi
movq %r15, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbp
movl $2, %edx
leaq .LC3(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 4(%rbx), %esi
movq %rbp, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L29
cmpb $0, 56(%r12)
jne .L30
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L20
.L28:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r13, %rdi
call _ZdaPv@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "_Z17bitonicSortSharedPjS_S_S_jj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z17bitonicSortSharedPjS_S_S_jj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "lab5.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z32__device_stub__bitonicSortSharedPjS_S_S_jj # -- Begin function _Z32__device_stub__bitonicSortSharedPjS_S_S_jj
.p2align 4, 0x90
.type _Z32__device_stub__bitonicSortSharedPjS_S_S_jj,@function
_Z32__device_stub__bitonicSortSharedPjS_S_S_jj: # @_Z32__device_stub__bitonicSortSharedPjS_S_S_jj
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17bitonicSortSharedPjS_S_S_jj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z32__device_stub__bitonicSortSharedPjS_S_S_jj, .Lfunc_end0-_Z32__device_stub__bitonicSortSharedPjS_S_S_jj
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $200, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $8192, %edi # imm = 0x2000
callq _Znam
movq %rax, %rbx
movl $8192, %edi # imm = 0x2000
callq _Znam
movq %rax, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
movl %eax, %ecx
imulq $1374389535, %rcx, %rcx # imm = 0x51EB851F
shrq $37, %rcx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
movl %r15d, (%r14,%r15,4)
incq %r15
cmpq $2048, %r15 # imm = 0x800
jne .LBB1_1
# %bb.2:
movl $8192, %edi # imm = 0x2000
callq _Znam
movq %rax, 16(%rsp)
leaq 16(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
movl $8192, %edi # imm = 0x2000
callq _Znam
movq %rax, 8(%rsp)
leaq 8(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
leaq 40(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
movq 40(%rsp), %rdi
movl $8192, %edx # imm = 0x2000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 32(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
movq 32(%rsp), %rdi
movl $8192, %edx # imm = 0x2000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movl $0, 4(%rsp)
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB1_21
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB1_5
# %bb.4:
movzbl 67(%r15), %eax
jmp .LBB1_6
.LBB1_5:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 56(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movq 56(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 1023(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movq %rsi, 112(%rsp)
movl $2048, 52(%rsp) # imm = 0x800
movl $1, 48(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 112(%rsp), %rax
movq %rax, 168(%rsp)
leaq 52(%rsp), %rax
movq %rax, 176(%rsp)
leaq 48(%rsp), %rax
movq %rax, 184(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z17bitonicSortSharedPjS_S_S_jj, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 56(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movq 8(%rsp), %rsi
movl $8192, %edx # imm = 0x2000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rsi
movl $8192, %edx # imm = 0x2000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movl $1, %r15d
jmp .LBB1_9
.LBB1_18: # in Loop: Header=BB1_9 Depth=1
movq %r14, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB1_19: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit34
# in Loop: Header=BB1_9 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_20: # in Loop: Header=BB1_9 Depth=1
incq %r15
cmpq $2048, %r15 # imm = 0x800
je .LBB1_13
.LBB1_9: # =>This Inner Loop Header: Depth=1
movl -4(%rbx,%r15,4), %eax
cmpl (%rbx,%r15,4), %eax
jbe .LBB1_20
# %bb.10: # in Loop: Header=BB1_9 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl -4(%rbx,%r15,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %r14
movl $.L.str.2, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%rbx,%r15,4), %esi
movq %r14, %rdi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_21
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i31
# in Loop: Header=BB1_9 Depth=1
cmpb $0, 56(%r14)
je .LBB1_18
# %bb.12: # in Loop: Header=BB1_9 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB1_19
.LBB1_13:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB1_21
# %bb.14: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i26
cmpb $0, 56(%r14)
je .LBB1_16
# %bb.15:
movzbl 67(%r14), %eax
jmp .LBB1_17
.LBB1_16:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_17: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit29
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq _ZdaPv
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_21:
.cfi_def_cfa_offset 240
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17bitonicSortSharedPjS_S_S_jj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17bitonicSortSharedPjS_S_S_jj,@object # @_Z17bitonicSortSharedPjS_S_S_jj
.section .rodata,"a",@progbits
.globl _Z17bitonicSortSharedPjS_S_S_jj
.p2align 3, 0x0
_Z17bitonicSortSharedPjS_S_S_jj:
.quad _Z32__device_stub__bitonicSortSharedPjS_S_S_jj
.size _Z17bitonicSortSharedPjS_S_S_jj, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Elapsed time: %.2f\n"
.size .L.str, 20
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error "
.size .L.str.1, 7
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "> "
.size .L.str.2, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z17bitonicSortSharedPjS_S_S_jj"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__bitonicSortSharedPjS_S_S_jj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17bitonicSortSharedPjS_S_S_jj
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <cmath>
#include <algorithm>
#include <fstream>
#define N 100
#define nrange 20
#define bkgd 3
#define CL 0.9
__global__ void kernel(double*, int*, double*);
__device__ double poissonP(double, double);
__device__ double factorial(double n);
__global__ void kernel(double* mu, int* n, double* R) {
int thId = threadIdx.x;
int blId = blockIdx.x;
int atId = threadIdx.x + blockIdx.x * blockDim.x;
__shared__ double cacheR[nrange];
cacheR[thId] = poissonP(mu[blId], thId)/poissonP(max(0, thId - bkgd), thId);
__syncthreads();
n[atId] = thId;
R[atId] = cacheR[thId];
}
__device__ double poissonP(double mu, double n) {
return pow(mu + 3., n)*exp(-(mu + 3.))/factorial(n);
}
__device__ double factorial(double n) {
double fn = 1.;
if (n == 0) {
return 1.;
} else {
for (int i = 1; i < n + 1; i++) {
fn *= (double)i;
}
}
return fn;
}
int main() {
double* mu = new double[N];
double* R = new double[N*nrange];
int* n = new int[N*nrange];
double* dev_mu;
double* dev_R;
int* dev_n;
cudaMalloc((void**)&dev_mu, N*sizeof(double));
cudaMalloc((void**)&dev_R, N*nrange*sizeof(double));
cudaMalloc((void**)&dev_n, N*nrange*sizeof(int));
double muMax = 10;
double muMin = 0;
double step = (muMax - muMin)/N;
for (int i = 0; i < N; i++) {
mu[i] = muMin + (double)i * step;
}
cudaMemcpy(dev_mu, mu, N*sizeof(double), cudaMemcpyHostToDevice);
kernel<<<N,nrange>>>(dev_mu, dev_n, dev_R);
cudaMemcpy(R, dev_R, N*nrange*sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(n, dev_n, N*nrange*sizeof(int), cudaMemcpyDeviceToHost);
std::ofstream ofs;
ofs.open ("ul.dat", std::ofstream::out | std::ofstream::app);
for (int i = 0; i < N; i++) {
ofs << mu[i];
for (int j = 0; j < nrange; j++) {
ofs << "," << n[j + i*nrange] << "," << R[j + i * nrange];
}
ofs << std::endl;
}
ofs.close();
cudaFree(dev_mu);
cudaFree(dev_n);
cudaFree(dev_R);
return 0;
} | .file "tmpxft_000219d4_00000000-6_FeldmanCousinsPoisson.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8poissonPdd
.type _Z8poissonPdd, @function
_Z8poissonPdd:
.LFB4054:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4054:
.size _Z8poissonPdd, .-_Z8poissonPdd
.globl _Z9factoriald
.type _Z9factoriald, @function
_Z9factoriald:
.LFB4055:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4055:
.size _Z9factoriald, .-_Z9factoriald
.globl _Z29__device_stub__Z6kernelPdPiS_PdPiS_
.type _Z29__device_stub__Z6kernelPdPiS_PdPiS_, @function
_Z29__device_stub__Z6kernelPdPiS_PdPiS_:
.LFB4081:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6kernelPdPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4081:
.size _Z29__device_stub__Z6kernelPdPiS_PdPiS_, .-_Z29__device_stub__Z6kernelPdPiS_PdPiS_
.globl _Z6kernelPdPiS_
.type _Z6kernelPdPiS_, @function
_Z6kernelPdPiS_:
.LFB4082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6kernelPdPiS_PdPiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4082:
.size _Z6kernelPdPiS_, .-_Z6kernelPdPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kernelPdPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPdPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.1
.LC3:
.string "ul.dat"
.LC4:
.string ","
.text
.globl main
.type main, @function
main:
.LFB4056:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4056
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $600, %rsp
.cfi_def_cfa_offset 656
movq %fs:40, %rax
movq %rax, 584(%rsp)
xorl %eax, %eax
movl $800, %edi
.LEHB0:
call _Znam@PLT
movq %rax, %r15
movl $16000, %edi
call _Znam@PLT
movq %rax, %rbx
movl $8000, %edi
call _Znam@PLT
movq %rax, %r14
leaq 16(%rsp), %rdi
movl $800, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $16000, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $8000, %esi
call cudaMalloc@PLT
movl $0, %eax
movsd .LC1(%rip), %xmm2
pxor %xmm1, %xmm1
.L18:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd %xmm2, %xmm0
addsd %xmm1, %xmm0
movsd %xmm0, (%r15,%rax,8)
addq $1, %rax
cmpq $100, %rax
jne .L18
movl $1, %ecx
movl $800, %edx
movq %r15, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $20, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $100, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L19:
movl $2, %ecx
movl $8000, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $8000, %edx
movq 32(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
leaq 64(%rsp), %rbp
movq %rbp, %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE0:
movl $17, %edx
leaq .LC3(%rip), %rsi
movq %rbp, %rdi
.LEHB1:
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
.LEHE1:
jmp .L36
.L35:
movq 24(%rsp), %rdx
movq 32(%rsp), %rsi
movq 16(%rsp), %rdi
.LEHB2:
call _Z29__device_stub__Z6kernelPdPiS_PdPiS_
.LEHE2:
jmp .L19
.L36:
movq %rbx, %r13
leaq 16000(%rbx), %rax
movq %rax, 8(%rsp)
leaq .LC4(%rip), %r12
jmp .L25
.L43:
movl $0, %ebx
jmp .L20
.L38:
movl (%r14,%rbx,4), %esi
leaq 64(%rsp), %rdi
.LEHB3:
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $1, %edx
movq %r12, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movsd 0(%r13,%rbx,8), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
addq $1, %rbx
cmpq $20, %rbx
je .L37
.L20:
leaq 64(%rsp), %rdi
movl $1, %edx
movq %r12, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L38
.L37:
movq 64(%rsp), %rax
movq -24(%rax), %rax
movq 304(%rsp,%rax), %rbx
testq %rbx, %rbx
je .L39
cmpb $0, 56(%rbx)
je .L23
movzbl 67(%rbx), %esi
.L24:
movsbl %sil, %esi
leaq 64(%rsp), %rdi
call _ZNSo3putEc@PLT
jmp .L40
.L39:
movq 584(%rsp), %rax
subq %fs:40, %rax
jne .L41
call _ZSt16__throw_bad_castv@PLT
.L29:
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 584(%rsp), %rax
subq %fs:40, %rax
je .L27
call __stack_chk_fail@PLT
.L41:
call __stack_chk_fail@PLT
.L23:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L24
.L40:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $8, %r15
addq $160, %r13
addq $80, %r14
movq 8(%rsp), %rax
cmpq %rax, %r13
je .L42
.L25:
movsd (%r15), %xmm0
leaq 64(%rsp), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
jmp .L43
.L42:
leaq 64(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
.LEHE3:
leaq 64(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 584(%rsp), %rax
subq %fs:40, %rax
jne .L44
movl $0, %eax
addq $600, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L44:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4056:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4056:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4056-.LLSDACSB4056
.LLSDACSB4056:
.uleb128 .LEHB0-.LFB4056
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4056
.uleb128 .LEHE1-.LEHB1
.uleb128 .L29-.LFB4056
.uleb128 0
.uleb128 .LEHB2-.LFB4056
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB4056
.uleb128 .LEHE3-.LEHB3
.uleb128 .L29-.LFB4056
.uleb128 0
.uleb128 .LEHB4-.LFB4056
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE4056:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -1717986918
.long 1069128089
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cmath>
#include <algorithm>
#include <fstream>
#define N 100
#define nrange 20
#define bkgd 3
#define CL 0.9
__global__ void kernel(double*, int*, double*);
__device__ double poissonP(double, double);
__device__ double factorial(double n);
__global__ void kernel(double* mu, int* n, double* R) {
int thId = threadIdx.x;
int blId = blockIdx.x;
int atId = threadIdx.x + blockIdx.x * blockDim.x;
__shared__ double cacheR[nrange];
cacheR[thId] = poissonP(mu[blId], thId)/poissonP(max(0, thId - bkgd), thId);
__syncthreads();
n[atId] = thId;
R[atId] = cacheR[thId];
}
__device__ double poissonP(double mu, double n) {
return pow(mu + 3., n)*exp(-(mu + 3.))/factorial(n);
}
__device__ double factorial(double n) {
double fn = 1.;
if (n == 0) {
return 1.;
} else {
for (int i = 1; i < n + 1; i++) {
fn *= (double)i;
}
}
return fn;
}
int main() {
double* mu = new double[N];
double* R = new double[N*nrange];
int* n = new int[N*nrange];
double* dev_mu;
double* dev_R;
int* dev_n;
cudaMalloc((void**)&dev_mu, N*sizeof(double));
cudaMalloc((void**)&dev_R, N*nrange*sizeof(double));
cudaMalloc((void**)&dev_n, N*nrange*sizeof(int));
double muMax = 10;
double muMin = 0;
double step = (muMax - muMin)/N;
for (int i = 0; i < N; i++) {
mu[i] = muMin + (double)i * step;
}
cudaMemcpy(dev_mu, mu, N*sizeof(double), cudaMemcpyHostToDevice);
kernel<<<N,nrange>>>(dev_mu, dev_n, dev_R);
cudaMemcpy(R, dev_R, N*nrange*sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(n, dev_n, N*nrange*sizeof(int), cudaMemcpyDeviceToHost);
std::ofstream ofs;
ofs.open ("ul.dat", std::ofstream::out | std::ofstream::app);
for (int i = 0; i < N; i++) {
ofs << mu[i];
for (int j = 0; j < nrange; j++) {
ofs << "," << n[j + i*nrange] << "," << R[j + i * nrange];
}
ofs << std::endl;
}
ofs.close();
cudaFree(dev_mu);
cudaFree(dev_n);
cudaFree(dev_R);
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <cmath>
#include <algorithm>
#include <fstream>
#define N 100
#define nrange 20
#define bkgd 3
#define CL 0.9
__global__ void kernel(double*, int*, double*);
__device__ double poissonP(double, double);
__device__ double factorial(double n);
__global__ void kernel(double* mu, int* n, double* R) {
int thId = threadIdx.x;
int blId = blockIdx.x;
int atId = threadIdx.x + blockIdx.x * blockDim.x;
__shared__ double cacheR[nrange];
cacheR[thId] = poissonP(mu[blId], thId)/poissonP(max(0, thId - bkgd), thId);
__syncthreads();
n[atId] = thId;
R[atId] = cacheR[thId];
}
__device__ double poissonP(double mu, double n) {
return pow(mu + 3., n)*exp(-(mu + 3.))/factorial(n);
}
__device__ double factorial(double n) {
double fn = 1.;
if (n == 0) {
return 1.;
} else {
for (int i = 1; i < n + 1; i++) {
fn *= (double)i;
}
}
return fn;
}
int main() {
double* mu = new double[N];
double* R = new double[N*nrange];
int* n = new int[N*nrange];
double* dev_mu;
double* dev_R;
int* dev_n;
hipMalloc((void**)&dev_mu, N*sizeof(double));
hipMalloc((void**)&dev_R, N*nrange*sizeof(double));
hipMalloc((void**)&dev_n, N*nrange*sizeof(int));
double muMax = 10;
double muMin = 0;
double step = (muMax - muMin)/N;
for (int i = 0; i < N; i++) {
mu[i] = muMin + (double)i * step;
}
hipMemcpy(dev_mu, mu, N*sizeof(double), hipMemcpyHostToDevice);
kernel<<<N,nrange>>>(dev_mu, dev_n, dev_R);
hipMemcpy(R, dev_R, N*nrange*sizeof(int), hipMemcpyDeviceToHost);
hipMemcpy(n, dev_n, N*nrange*sizeof(int), hipMemcpyDeviceToHost);
std::ofstream ofs;
ofs.open ("ul.dat", std::ofstream::out | std::ofstream::app);
for (int i = 0; i < N; i++) {
ofs << mu[i];
for (int j = 0; j < nrange; j++) {
ofs << "," << n[j + i*nrange] << "," << R[j + i * nrange];
}
ofs << std::endl;
}
ofs.close();
hipFree(dev_mu);
hipFree(dev_n);
hipFree(dev_R);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cmath>
#include <algorithm>
#include <fstream>
#define N 100
#define nrange 20
#define bkgd 3
#define CL 0.9
__global__ void kernel(double*, int*, double*);
__device__ double poissonP(double, double);
__device__ double factorial(double n);
__global__ void kernel(double* mu, int* n, double* R) {
int thId = threadIdx.x;
int blId = blockIdx.x;
int atId = threadIdx.x + blockIdx.x * blockDim.x;
__shared__ double cacheR[nrange];
cacheR[thId] = poissonP(mu[blId], thId)/poissonP(max(0, thId - bkgd), thId);
__syncthreads();
n[atId] = thId;
R[atId] = cacheR[thId];
}
__device__ double poissonP(double mu, double n) {
return pow(mu + 3., n)*exp(-(mu + 3.))/factorial(n);
}
__device__ double factorial(double n) {
double fn = 1.;
if (n == 0) {
return 1.;
} else {
for (int i = 1; i < n + 1; i++) {
fn *= (double)i;
}
}
return fn;
}
int main() {
double* mu = new double[N];
double* R = new double[N*nrange];
int* n = new int[N*nrange];
double* dev_mu;
double* dev_R;
int* dev_n;
hipMalloc((void**)&dev_mu, N*sizeof(double));
hipMalloc((void**)&dev_R, N*nrange*sizeof(double));
hipMalloc((void**)&dev_n, N*nrange*sizeof(int));
double muMax = 10;
double muMin = 0;
double step = (muMax - muMin)/N;
for (int i = 0; i < N; i++) {
mu[i] = muMin + (double)i * step;
}
hipMemcpy(dev_mu, mu, N*sizeof(double), hipMemcpyHostToDevice);
kernel<<<N,nrange>>>(dev_mu, dev_n, dev_R);
hipMemcpy(R, dev_R, N*nrange*sizeof(int), hipMemcpyDeviceToHost);
hipMemcpy(n, dev_n, N*nrange*sizeof(int), hipMemcpyDeviceToHost);
std::ofstream ofs;
ofs.open ("ul.dat", std::ofstream::out | std::ofstream::app);
for (int i = 0; i < N; i++) {
ofs << mu[i];
for (int j = 0; j < nrange; j++) {
ofs << "," << n[j + i*nrange] << "," << R[j + i * nrange];
}
ofs << std::endl;
}
ofs.close();
hipFree(dev_mu);
hipFree(dev_n);
hipFree(dev_R);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPdPiS_
.globl _Z6kernelPdPiS_
.p2align 8
.type _Z6kernelPdPiS_,@function
_Z6kernelPdPiS_:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s7, s[0:1], 0x24
v_cvt_f64_i32_e32 v[5:6], v0
s_mov_b32 s8, s15
s_ashr_i32 s9, s15, 31
v_mov_b32_e32 v1, 0
s_lshl_b64 s[4:5], s[8:9], 3
v_mov_b32_e32 v2, 0x3ff00000
v_cmp_ne_u32_e32 vcc_lo, 0, v0
s_delay_alu instid0(VALU_DEP_2)
v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s4
s_addc_u32 s3, s3, s5
s_load_b64 s[4:5], s[2:3], 0x0
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_6
v_add_f64 v[7:8], v[5:6], 1.0
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0x3ff00000
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_3)
v_cmpx_lt_f64_e32 1.0, v[7:8]
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v9, 0
v_mov_b32_e32 v10, 0x3ff00000
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mov_b32_e32 v3, v9
s_mov_b32 s10, 2
s_mov_b32 s9, 0
v_mov_b32_e32 v4, v10
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mul_f64 v[3:4], v[9:10], v[3:4]
v_cvt_f64_i32_e32 v[9:10], s10
s_add_i32 s10, s10, 1
v_cmp_ngt_f64_e64 s2, v[7:8], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s9, s2, s9
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s9
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s6
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_12
v_add_f64 v[7:8], v[5:6], 1.0
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0x3ff00000
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_3)
v_cmpx_lt_f64_e32 1.0, v[7:8]
s_cbranch_execz .LBB0_11
v_mov_b32_e32 v9, 0
v_mov_b32_e32 v10, 0x3ff00000
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mov_b32_e32 v1, v9
s_mov_b32 s9, 2
s_mov_b32 s6, 0
v_mov_b32_e32 v2, v10
.LBB0_9:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mul_f64 v[1:2], v[9:10], v[1:2]
v_cvt_f64_i32_e32 v[9:10], s9
s_add_i32 s9, s9, 1
v_cmp_ngt_f64_e32 vcc_lo, v[7:8], v[9:10]
s_or_b32 s6, vcc_lo, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_9
s_or_b32 exec_lo, exec_lo, s6
.LBB0_11:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s3
.LBB0_12:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt lgkmcnt(0)
v_add_f64 v[7:8], s[4:5], 0x40080000
s_mov_b32 s5, 0x3fe55555
s_mov_b32 s4, 0x55555555
v_max_i32_e32 v15, 3, v0
v_cmp_ne_u32_e64 s2, 0, v0
s_mov_b32 s11, 0x3fba6564
s_mov_b32 s10, 0x968915a9
s_mov_b32 s13, 0x3fbdee67
v_cvt_f64_i32_e32 v[15:16], v15
s_mov_b32 s12, 0x4222de17
s_mov_b32 s15, 0x3fbe25e4
s_mov_b32 s14, 0x3abe935a
s_mov_b32 s17, 0x3fc110ef
s_mov_b32 s16, 0x47e6c9c2
s_mov_b32 s3, 0xbc7abc9e
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cmp_neq_f64_e32 vcc_lo, 1.0, v[7:8]
v_cndmask_b32_e32 v12, 0x3ff00000, v6, vcc_lo
v_cndmask_b32_e32 v11, 0, v5, vcc_lo
v_cmp_neq_f64_e32 vcc_lo, 0, v[11:12]
v_cndmask_b32_e32 v10, 0x3ff00000, v8, vcc_lo
v_cndmask_b32_e32 v9, 0, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_frexp_mant_f64_e64 v[13:14], |v[9:10]|
v_cmp_gt_f64_e32 vcc_lo, s[4:5], v[13:14]
v_cndmask_b32_e64 v17, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_ldexp_f64 v[17:18], v[13:14], v17
v_cndmask_b32_e64 v14, 0x3ff00000, v16, s2
v_cndmask_b32_e64 v13, 0, v15, s2
v_frexp_mant_f64_e64 v[21:22], |v[13:14]|
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[19:20], v[17:18], 1.0
v_add_f64 v[33:34], v[17:18], -1.0
v_cmp_gt_f64_e64 s2, s[4:5], v[21:22]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_rcp_f64_e32 v[23:24], v[19:20]
v_add_f64 v[35:36], v[19:20], -1.0
v_cndmask_b32_e64 v25, 0, 1, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ldexp_f64 v[21:22], v[21:22], v25
v_add_f64 v[17:18], v[17:18], -v[35:36]
s_waitcnt_depctr 0xfff
v_fma_f64 v[25:26], -v[19:20], v[23:24], 1.0
v_add_f64 v[27:28], v[21:22], 1.0
v_add_f64 v[39:40], v[21:22], -1.0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[23:24], v[25:26], v[23:24], v[23:24]
v_rcp_f64_e32 v[25:26], v[27:28]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_fma_f64 v[29:30], -v[19:20], v[23:24], 1.0
s_waitcnt_depctr 0xfff
v_fma_f64 v[31:32], -v[27:28], v[25:26], 1.0
v_fma_f64 v[23:24], v[29:30], v[23:24], v[23:24]
v_fma_f64 v[25:26], v[31:32], v[25:26], v[25:26]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[29:30], v[33:34], v[23:24]
v_fma_f64 v[31:32], -v[27:28], v[25:26], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[37:38], v[19:20], v[29:30]
v_fma_f64 v[25:26], v[31:32], v[25:26], v[25:26]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[19:20], v[29:30], v[19:20], -v[37:38]
v_mul_f64 v[31:32], v[39:40], v[25:26]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[17:18], v[29:30], v[17:18], v[19:20]
v_add_f64 v[19:20], v[27:28], -1.0
v_mul_f64 v[35:36], v[27:28], v[31:32]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[41:42], v[37:38], v[17:18]
v_add_f64 v[19:20], v[21:22], -v[19:20]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[21:22], v[31:32], v[27:28], -v[35:36]
v_add_f64 v[27:28], v[33:34], -v[41:42]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[19:20], v[31:32], v[19:20], v[21:22]
v_add_f64 v[21:22], v[41:42], -v[37:38]
v_add_f64 v[33:34], v[33:34], -v[27:28]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[37:38], v[35:36], v[19:20]
v_add_f64 v[17:18], v[21:22], -v[17:18]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[21:22], v[33:34], -v[41:42]
v_add_f64 v[33:34], v[39:40], -v[37:38]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[17:18], v[17:18], v[21:22]
v_add_f64 v[21:22], v[37:38], -v[35:36]
v_add_f64 v[35:36], v[39:40], -v[33:34]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[17:18], v[27:28], v[17:18]
v_add_f64 v[19:20], v[21:22], -v[19:20]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[21:22], v[35:36], -v[37:38]
v_mul_f64 v[17:18], v[23:24], v[17:18]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[19:20], v[19:20], v[21:22]
v_add_f64 v[21:22], v[29:30], v[17:18]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[19:20], v[33:34], v[19:20]
v_add_f64 v[23:24], v[21:22], -v[29:30]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_f64 v[19:20], v[25:26], v[19:20]
v_mul_f64 v[25:26], v[21:22], v[21:22]
v_add_f64 v[17:18], v[17:18], -v[23:24]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[23:24], v[31:32], v[19:20]
v_fma_f64 v[27:28], v[21:22], v[21:22], -v[25:26]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[29:30], v[17:18], v[17:18]
v_add_f64 v[31:32], v[23:24], -v[31:32]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[27:28], v[21:22], v[29:30], v[27:28]
v_mul_f64 v[29:30], v[23:24], v[23:24]
v_add_f64 v[19:20], v[19:20], -v[31:32]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[31:32], v[25:26], v[27:28]
v_fma_f64 v[33:34], v[23:24], v[23:24], -v[29:30]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[35:36], v[19:20], v[19:20]
v_fma_f64 v[37:38], v[31:32], s[12:13], s[10:11]
v_add_f64 v[25:26], v[31:32], -v[25:26]
v_mul_f64 v[47:48], v[21:22], v[31:32]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[33:34], v[23:24], v[35:36], v[33:34]
v_fma_f64 v[35:36], v[31:32], v[37:38], s[14:15]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[25:26], v[27:28], -v[25:26]
v_add_f64 v[37:38], v[29:30], v[33:34]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[35:36], v[31:32], v[35:36], s[16:17]
v_fma_f64 v[39:40], v[37:38], s[12:13], s[10:11]
s_mov_b32 s11, 0x3fc3b13b
s_mov_b32 s10, 0xcfa74449
s_mov_b32 s13, 0x3fc745d1
s_mov_b32 s12, 0x71bf3c30
v_add_f64 v[29:30], v[37:38], -v[29:30]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[35:36], v[31:32], v[35:36], s[10:11]
v_fma_f64 v[39:40], v[37:38], v[39:40], s[14:15]
s_mov_b32 s15, 0x3fcc71c7
s_mov_b32 s14, 0x1c7792ce
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[29:30], v[33:34], -v[29:30]
v_fma_f64 v[35:36], v[31:32], v[35:36], s[12:13]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fma_f64 v[39:40], v[37:38], v[39:40], s[16:17]
s_mov_b32 s17, 0x3efa0199
s_mov_b32 s16, 0x7c89e6b0
v_fma_f64 v[35:36], v[31:32], v[35:36], s[14:15]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[39:40], v[37:38], v[39:40], s[10:11]
s_mov_b32 s11, 0x3fd24924
s_mov_b32 s10, 0x924920da
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[35:36], v[31:32], v[35:36], s[10:11]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[39:40], v[37:38], v[39:40], s[12:13]
s_mov_b32 s13, 0x3fd99999
s_mov_b32 s12, 0x9999999c
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[35:36], v[31:32], v[35:36], s[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fma_f64 v[39:40], v[37:38], v[39:40], s[14:15]
s_mov_b32 s15, 0x3e5ade15
s_mov_b32 s14, 0x6a5dcb37
v_mul_f64 v[41:42], v[31:32], v[35:36]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fma_f64 v[39:40], v[37:38], v[39:40], s[10:11]
s_mov_b32 s11, 0xbfe55555
s_mov_b32 s10, s4
v_fma_f64 v[27:28], v[31:32], v[35:36], -v[41:42]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fma_f64 v[39:40], v[37:38], v[39:40], s[12:13]
s_mov_b32 s13, 0x3c8543b0
s_mov_b32 s12, 0xd5df274d
v_fma_f64 v[27:28], v[25:26], v[35:36], v[27:28]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[35:36], v[37:38], v[39:40]
v_add_f64 v[43:44], v[41:42], v[27:28]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[33:34], v[37:38], v[39:40], -v[35:36]
v_add_f64 v[41:42], v[43:44], -v[41:42]
v_add_f64 v[45:46], v[43:44], s[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[33:34], v[29:30], v[39:40], v[33:34]
v_add_f64 v[27:28], v[27:28], -v[41:42]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_f64 v[39:40], v[45:46], s[10:11]
v_fma_f64 v[41:42], v[31:32], v[21:22], -v[47:48]
v_add_f64 v[49:50], v[35:36], v[33:34]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[27:28], v[27:28], s[12:13]
v_add_f64 v[39:40], v[43:44], -v[39:40]
s_delay_alu instid0(VALU_DEP_4)
v_fma_f64 v[31:32], v[31:32], v[17:18], v[41:42]
v_mul_f64 v[43:44], v[23:24], v[37:38]
v_ldexp_f64 v[17:18], v[17:18], 1
v_add_f64 v[35:36], v[49:50], -v[35:36]
v_add_f64 v[41:42], v[49:50], s[4:5]
s_mov_b32 s4, 0xfefa39ef
s_mov_b32 s5, 0xbfe62e42
v_add_f64 v[27:28], v[27:28], v[39:40]
v_fma_f64 v[25:26], v[25:26], v[21:22], v[31:32]
v_ldexp_f64 v[21:22], v[21:22], 1
v_add_f64 v[31:32], v[33:34], -v[35:36]
v_add_f64 v[33:34], v[41:42], s[10:11]
v_fma_f64 v[35:36], v[37:38], v[23:24], -v[43:44]
s_mov_b32 s11, 0x3fe62e42
s_mov_b32 s10, s4
v_add_f64 v[39:40], v[45:46], v[27:28]
v_add_f64 v[51:52], v[47:48], v[25:26]
v_add_f64 v[31:32], v[31:32], s[12:13]
v_add_f64 v[33:34], v[49:50], -v[33:34]
v_fma_f64 v[35:36], v[37:38], v[19:20], v[35:36]
s_mov_b32 s13, 0x3c7abc9e
v_ldexp_f64 v[19:20], v[19:20], 1
v_add_f64 v[37:38], v[45:46], -v[39:40]
v_mul_f64 v[45:46], v[51:52], v[39:40]
v_add_f64 v[31:32], v[31:32], v[33:34]
v_fma_f64 v[29:30], v[29:30], v[23:24], v[35:36]
v_add_f64 v[33:34], v[51:52], -v[47:48]
v_ldexp_f64 v[23:24], v[23:24], 1
v_add_f64 v[27:28], v[27:28], v[37:38]
v_fma_f64 v[35:36], v[51:52], v[39:40], -v[45:46]
v_add_f64 v[37:38], v[41:42], v[31:32]
v_add_f64 v[47:48], v[43:44], v[29:30]
v_add_f64 v[25:26], v[25:26], -v[33:34]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[27:28], v[51:52], v[27:28], v[35:36]
v_add_f64 v[33:34], v[41:42], -v[37:38]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_mul_f64 v[35:36], v[47:48], v[37:38]
v_frexp_exp_i32_f64_e32 v41, v[9:10]
v_fma_f64 v[25:26], v[25:26], v[39:40], v[27:28]
v_add_f64 v[27:28], v[47:48], -v[43:44]
v_frexp_exp_i32_f64_e32 v43, v[13:14]
v_add_f64 v[31:32], v[31:32], v[33:34]
v_fma_f64 v[33:34], v[47:48], v[37:38], -v[35:36]
v_add_f64 v[39:40], v[45:46], v[25:26]
v_add_f64 v[27:28], v[29:30], -v[27:28]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[29:30], v[47:48], v[31:32], v[33:34]
v_subrev_co_ci_u32_e32 v31, vcc_lo, 0, v41, vcc_lo
v_cvt_f64_i32_e32 v[31:32], v31
v_add_f64 v[33:34], v[39:40], -v[45:46]
v_add_f64 v[41:42], v[21:22], v[39:40]
v_fma_f64 v[27:28], v[27:28], v[37:38], v[29:30]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_f64 v[29:30], v[31:32], s[10:11]
v_add_f64 v[25:26], v[25:26], -v[33:34]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[21:22], v[41:42], -v[21:22]
v_add_f64 v[33:34], v[35:36], v[27:28]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[37:38], v[31:32], s[10:11], -v[29:30]
v_add_f64 v[17:18], v[17:18], v[25:26]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_f64 v[21:22], v[39:40], -v[21:22]
v_subrev_co_ci_u32_e64 v25, vcc_lo, 0, v43, s2
s_mov_b32 s2, 0x3b39803f
s_mov_b32 s12, s2
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f64_i32_e32 v[25:26], v25
v_add_f64 v[35:36], v[33:34], -v[35:36]
v_add_f64 v[39:40], v[23:24], v[33:34]
v_fma_f64 v[31:32], v[31:32], s[12:13], v[37:38]
v_add_f64 v[17:18], v[17:18], v[21:22]
v_mul_f64 v[21:22], v[25:26], s[10:11]
v_add_f64 v[27:28], v[27:28], -v[35:36]
v_add_f64 v[23:24], v[39:40], -v[23:24]
v_add_f64 v[35:36], v[29:30], v[31:32]
v_add_f64 v[37:38], v[41:42], v[17:18]
v_fma_f64 v[43:44], v[25:26], s[10:11], -v[21:22]
s_mov_b32 s10, 0x652b82fe
s_mov_b32 s11, 0xbff71547
v_add_f64 v[19:20], v[19:20], v[27:28]
v_add_f64 v[23:24], v[33:34], -v[23:24]
v_add_f64 v[29:30], v[35:36], -v[29:30]
v_add_f64 v[27:28], v[35:36], v[37:38]
v_add_f64 v[41:42], v[37:38], -v[41:42]
v_fma_f64 v[25:26], v[25:26], s[12:13], v[43:44]
s_mov_b32 s13, 0x3ff71547
s_mov_b32 s12, s10
v_add_f64 v[19:20], v[19:20], v[23:24]
v_add_f64 v[29:30], v[31:32], -v[29:30]
v_add_f64 v[23:24], v[27:28], -v[35:36]
v_add_f64 v[17:18], v[17:18], -v[41:42]
v_add_f64 v[33:34], v[21:22], v[25:26]
v_add_f64 v[43:44], v[39:40], v[19:20]
s_delay_alu instid0(VALU_DEP_4)
v_add_f64 v[45:46], v[27:28], -v[23:24]
v_add_f64 v[23:24], v[37:38], -v[23:24]
v_add_f64 v[37:38], v[29:30], v[17:18]
v_add_f64 v[21:22], v[33:34], -v[21:22]
v_add_f64 v[47:48], v[33:34], v[43:44]
v_add_f64 v[31:32], v[35:36], -v[45:46]
v_mul_f64 v[45:46], v[15:16], s[10:11]
v_add_f64 v[41:42], v[37:38], -v[29:30]
v_add_f64 v[21:22], v[25:26], -v[21:22]
v_add_f64 v[35:36], v[47:48], -v[33:34]
v_add_f64 v[23:24], v[23:24], v[31:32]
v_add_f64 v[31:32], v[43:44], -v[39:40]
v_add_f64 v[17:18], v[17:18], -v[41:42]
v_rndne_f64_e32 v[45:46], v[45:46]
v_add_f64 v[39:40], v[47:48], -v[35:36]
v_add_f64 v[25:26], v[43:44], -v[35:36]
v_add_f64 v[23:24], v[37:38], v[23:24]
v_add_f64 v[19:20], v[19:20], -v[31:32]
v_fma_f64 v[15:16], v[45:46], s[4:5], -v[15:16]
v_add_f64 v[31:32], v[33:34], -v[39:40]
v_add_f64 v[33:34], v[37:38], -v[41:42]
v_mul_f64 v[39:40], v[7:8], s[10:11]
s_mov_b32 s11, 0x3ec71dee
s_mov_b32 s10, 0x623fde64
v_add_f64 v[35:36], v[27:28], v[23:24]
v_add_f64 v[37:38], v[21:22], v[19:20]
v_fma_f64 v[15:16], v[45:46], s[2:3], v[15:16]
v_add_f64 v[25:26], v[25:26], v[31:32]
v_add_f64 v[29:30], v[29:30], -v[33:34]
v_rndne_f64_e32 v[39:40], v[39:40]
v_add_f64 v[27:28], v[35:36], -v[27:28]
v_add_f64 v[31:32], v[37:38], -v[21:22]
v_add_f64 v[25:26], v[37:38], v[25:26]
v_add_f64 v[17:18], v[17:18], v[29:30]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[23:24], v[23:24], -v[27:28]
v_add_f64 v[27:28], v[37:38], -v[31:32]
v_add_f64 v[19:20], v[19:20], -v[31:32]
v_add_f64 v[29:30], v[47:48], v[25:26]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[17:18], v[17:18], v[23:24]
v_add_f64 v[21:22], v[21:22], -v[27:28]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_f64 v[23:24], v[29:30], -v[47:48]
v_fma_f64 v[47:48], v[39:40], s[4:5], -v[7:8]
v_add_f64 v[27:28], v[35:36], v[17:18]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[19:20], v[19:20], v[21:22]
v_add_f64 v[21:22], v[25:26], -v[23:24]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[47:48], v[39:40], s[2:3], v[47:48]
v_add_f64 v[23:24], v[27:28], -v[35:36]
v_mul_f64 v[25:26], v[11:12], v[27:28]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[19:20], v[19:20], v[21:22]
v_add_f64 v[17:18], v[17:18], -v[23:24]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_fma_f64 v[21:22], v[11:12], v[27:28], -v[25:26]
v_cmp_class_f64_e64 vcc_lo, v[25:26], 0x204
v_add_f64 v[23:24], v[29:30], v[19:20]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[17:18], v[11:12], v[17:18], v[21:22]
v_add_f64 v[21:22], v[23:24], -v[29:30]
v_mul_f64 v[27:28], v[23:24], v[5:6]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[29:30], v[25:26], v[17:18]
v_add_f64 v[19:20], v[19:20], -v[21:22]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[21:22], v[5:6], v[23:24], -v[27:28]
v_dual_cndmask_b32 v24, v30, v26 :: v_dual_cndmask_b32 v23, v29, v25
v_cmp_class_f64_e64 vcc_lo, v[27:28], 0x204
v_add_f64 v[25:26], v[29:30], -v[25:26]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_mul_f64 v[31:32], v[23:24], s[12:13]
v_fma_f64 v[19:20], v[5:6], v[19:20], v[21:22]
v_mul_f64 v[5:6], v[5:6], 0.5
v_add_f64 v[17:18], v[17:18], -v[25:26]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_rndne_f64_e32 v[21:22], v[31:32]
v_add_f64 v[31:32], v[27:28], v[19:20]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_i32_f64_e32 v55, v[21:22]
v_dual_cndmask_b32 v36, v32, v28 :: v_dual_cndmask_b32 v35, v31, v27
v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[23:24]|
v_cmp_class_f64_e64 s9, v[9:10], 0x204
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_mul_f64 v[37:38], v[35:36], s[12:13]
s_mov_b32 s13, 0x3e928af3
s_mov_b32 s12, 0xfca7ab0c
v_fma_f64 v[51:52], v[47:48], s[14:15], s[12:13]
v_fma_f64 v[53:54], v[15:16], s[14:15], s[12:13]
v_cndmask_b32_e32 v18, 0, v18, vcc_lo
v_fma_f64 v[33:34], v[21:22], s[4:5], v[23:24]
v_cndmask_b32_e32 v17, 0, v17, vcc_lo
v_rndne_f64_e32 v[37:38], v[37:38]
v_fma_f64 v[51:52], v[47:48], v[51:52], s[10:11]
v_fma_f64 v[53:54], v[15:16], v[53:54], s[10:11]
v_fma_f64 v[33:34], v[21:22], s[2:3], v[33:34]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_fma_f64 v[43:44], v[37:38], s[4:5], v[35:36]
s_mov_b32 s5, 0x3f2a01a0
s_mov_b32 s4, 0x14761f6e
v_fma_f64 v[51:52], v[47:48], v[51:52], s[16:17]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[53:54], v[15:16], v[53:54], s[16:17]
v_fma_f64 v[41:42], v[33:34], s[14:15], s[12:13]
s_delay_alu instid0(VALU_DEP_4)
v_fma_f64 v[43:44], v[37:38], s[2:3], v[43:44]
s_mov_b32 s3, 0x3f56c16c
s_mov_b32 s2, 0x1852b7b0
v_cvt_i32_f64_e32 v37, v[37:38]
v_fma_f64 v[51:52], v[47:48], v[51:52], s[4:5]
v_fma_f64 v[53:54], v[15:16], v[53:54], s[4:5]
v_fma_f64 v[41:42], v[33:34], v[41:42], s[10:11]
v_fma_f64 v[49:50], v[43:44], s[14:15], s[12:13]
s_mov_b32 s13, 0x3f811111
s_mov_b32 s12, 0x11122322
s_mov_b32 s15, 0x3fc55555
s_mov_b32 s14, 0x55555511
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[51:52], v[47:48], v[51:52], s[2:3]
v_fma_f64 v[53:54], v[15:16], v[53:54], s[2:3]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[41:42], v[33:34], v[41:42], s[16:17]
v_fma_f64 v[49:50], v[43:44], v[49:50], s[10:11]
s_mov_b32 s11, 0x3fa55555
s_mov_b32 s10, 0x555502a1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[51:52], v[47:48], v[51:52], s[12:13]
v_fma_f64 v[53:54], v[15:16], v[53:54], s[12:13]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[41:42], v[33:34], v[41:42], s[4:5]
v_fma_f64 v[49:50], v[43:44], v[49:50], s[16:17]
s_mov_b32 s17, 0x3fe00000
s_mov_b32 s16, 11
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[51:52], v[47:48], v[51:52], s[10:11]
v_fma_f64 v[41:42], v[33:34], v[41:42], s[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[49:50], v[43:44], v[49:50], s[4:5]
v_fma_f64 v[41:42], v[33:34], v[41:42], s[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_fma_f64 v[49:50], v[43:44], v[49:50], s[2:3]
v_cmp_nlt_f64_e64 s2, 0x40900000, v[23:24]
v_cmp_ngt_f64_e64 s3, 0xc090cc00, v[23:24]
v_fma_f64 v[41:42], v[33:34], v[41:42], s[10:11]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[49:50], v[43:44], v[49:50], s[12:13]
s_and_b32 vcc_lo, s3, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[41:42], v[33:34], v[41:42], s[14:15]
v_fma_f64 v[49:50], v[43:44], v[49:50], s[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[41:42], v[33:34], v[41:42], s[16:17]
v_fma_f64 v[49:50], v[43:44], v[49:50], s[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[41:42], v[33:34], v[41:42], 1.0
v_fma_f64 v[21:22], v[33:34], v[41:42], 1.0
s_delay_alu instid0(VALU_DEP_3)
v_fma_f64 v[33:34], v[43:44], v[49:50], s[16:17]
v_fma_f64 v[41:42], v[47:48], v[51:52], s[14:15]
v_fma_f64 v[51:52], v[15:16], v[53:54], s[10:11]
v_mul_f64 v[49:50], v[11:12], 0.5
v_ldexp_f64 v[21:22], v[21:22], v55
v_fma_f64 v[29:30], v[43:44], v[33:34], 1.0
v_fma_f64 v[33:34], v[47:48], v[41:42], s[16:17]
v_fma_f64 v[51:52], v[15:16], v[51:52], s[14:15]
v_trunc_f64_e32 v[41:42], v[11:12]
v_trunc_f64_e32 v[53:54], v[49:50]
v_cndmask_b32_e64 v26, 0x7ff00000, v22, s2
v_fma_f64 v[22:23], v[43:44], v[29:30], 1.0
v_fma_f64 v[24:25], v[47:48], v[33:34], 1.0
v_fma_f64 v[29:30], v[15:16], v[51:52], s[16:17]
v_cndmask_b32_e32 v33, 0, v21, vcc_lo
v_cndmask_b32_e64 v34, 0, v26, s3
v_add_f64 v[26:27], v[31:32], -v[27:28]
v_cmp_eq_f64_e64 s4, v[41:42], v[11:12]
v_cmp_neq_f64_e64 s5, v[53:54], v[49:50]
v_cvt_i32_f64_e32 v31, v[39:40]
v_fma_f64 v[17:18], v[33:34], v[17:18], v[33:34]
v_cmp_class_f64_e64 vcc_lo, v[33:34], 0x204
v_cmp_gt_f64_e64 s2, 0, v[11:12]
v_cmp_eq_f64_e64 s3, 0, v[9:10]
v_ldexp_f64 v[21:22], v[22:23], v37
v_fma_f64 v[23:24], v[47:48], v[24:25], 1.0
v_fma_f64 v[28:29], v[15:16], v[29:30], 1.0
v_add_f64 v[11:12], v[19:20], -v[26:27]
s_and_b32 s5, s4, s5
s_delay_alu instid0(SALU_CYCLE_1)
v_cndmask_b32_e64 v30, 0x3ff00000, v10, s5
v_dual_cndmask_b32 v26, v17, v33 :: v_dual_cndmask_b32 v17, v18, v34
v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[35:36]
v_cmp_ngt_f64_e64 s6, 0xc090cc00, v[35:36]
v_cndmask_b32_e64 v25, 0, v10, s5
v_cmp_neq_f64_e64 s5, 0x7ff00000, |v[35:36]|
v_bfi_b32 v27, 0x7fffffff, v17, v30
v_trunc_f64_e32 v[17:18], v[5:6]
v_cndmask_b32_e64 v32, 0, v26, s4
s_xor_b32 s2, s2, s3
s_or_b32 s3, s3, s9
v_cndmask_b32_e64 v30, 0x7ff80000, v27, s4
v_cmp_gt_f64_e64 s4, 0, v[9:10]
v_ldexp_f64 v[19:20], v[23:24], v31
v_cvt_i32_f64_e32 v23, v[45:46]
v_fma_f64 v[15:16], v[15:16], v[28:29], 1.0
v_cndmask_b32_e64 v24, 0x7ff00000, 0, s2
v_cndmask_b32_e32 v22, 0x7ff00000, v22, vcc_lo
s_and_b32 vcc_lo, s6, vcc_lo
v_cndmask_b32_e64 v12, 0, v12, s5
v_cndmask_b32_e64 v11, 0, v11, s5
s_delay_alu instid0(VALU_DEP_3)
v_cndmask_b32_e64 v22, 0, v22, s6
v_cndmask_b32_e32 v21, 0, v21, vcc_lo
v_cmp_neq_f64_e32 vcc_lo, v[17:18], v[5:6]
v_cmp_eq_f64_e64 s6, 0, v[13:14]
v_bfi_b32 v17, 0x7fffffff, v24, v25
v_cmp_nlt_f64_e64 s5, 0x4090cc00, v[7:8]
v_fma_f64 v[5:6], v[21:22], v[11:12], v[21:22]
v_cmp_class_f64_e64 s2, v[21:22], 0x204
v_cndmask_b32_e64 v11, v26, v32, s4
v_cndmask_b32_e64 v12, v27, v30, s4
v_cmp_ngt_f64_e64 s4, 0xc0900000, v[7:8]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v11, v11, 0, s3
v_cndmask_b32_e64 v12, v12, v17, s3
v_cmp_o_f64_e64 s3, v[9:10], v[9:10]
v_ldexp_f64 v[7:8], v[15:16], v23
v_cndmask_b32_e32 v10, 0, v14, vcc_lo
v_cndmask_b32_e64 v9, 0x7ff00000, 0, s6
v_cndmask_b32_e32 v13, 0x3ff00000, v14, vcc_lo
v_cndmask_b32_e64 v15, v6, v22, s2
v_cndmask_b32_e64 v14, v5, v21, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_bfi_b32 v16, 0x7fffffff, v9, v10
v_cndmask_b32_e64 v18, 0x7ff00000, v20, s4
s_and_b32 vcc_lo, s5, s4
v_bfi_b32 v13, 0x7fffffff, v15, v13
v_cndmask_b32_e32 v5, 0, v19, vcc_lo
v_cndmask_b32_e64 v6, 0, v18, s5
v_cndmask_b32_e64 v9, 0, v11, s3
v_cndmask_b32_e64 v10, 0x7ff80000, v12, s3
v_cndmask_b32_e64 v11, v14, 0, s6
v_cndmask_b32_e64 v12, v13, v16, s6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[5:6], v[5:6], v[9:10]
v_mul_f64 v[7:8], v[7:8], v[11:12]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_scale_f64 v[9:10], null, v[3:4], v[3:4], v[5:6]
v_div_scale_f64 v[11:12], null, v[1:2], v[1:2], v[7:8]
v_div_scale_f64 v[21:22], vcc_lo, v[5:6], v[3:4], v[5:6]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f64_e32 v[13:14], v[9:10]
v_rcp_f64_e32 v[15:16], v[11:12]
s_waitcnt_depctr 0xfff
v_fma_f64 v[17:18], -v[9:10], v[13:14], 1.0
v_fma_f64 v[19:20], -v[11:12], v[15:16], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[13:14], v[13:14], v[17:18], v[13:14]
v_fma_f64 v[15:16], v[15:16], v[19:20], v[15:16]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[17:18], -v[9:10], v[13:14], 1.0
v_fma_f64 v[19:20], -v[11:12], v[15:16], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[13:14], v[13:14], v[17:18], v[13:14]
v_div_scale_f64 v[17:18], s2, v[7:8], v[1:2], v[7:8]
v_fma_f64 v[15:16], v[15:16], v[19:20], v[15:16]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[19:20], v[21:22], v[13:14]
v_mul_f64 v[23:24], v[17:18], v[15:16]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[9:10], -v[9:10], v[19:20], v[21:22]
v_fma_f64 v[11:12], -v[11:12], v[23:24], v[17:18]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[9:10], v[9:10], v[13:14], v[19:20]
s_mov_b32 vcc_lo, s2
s_and_b32 s2, 0xffff, s7
v_div_fmas_f64 v[11:12], v[11:12], v[15:16], v[23:24]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f64 v[3:4], v[9:10], v[3:4], v[5:6]
v_div_fixup_f64 v[1:2], v[11:12], v[1:2], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f64 v[5:6], null, v[1:2], v[1:2], v[3:4]
v_div_scale_f64 v[11:12], vcc_lo, v[3:4], v[1:2], v[3:4]
v_rcp_f64_e32 v[7:8], v[5:6]
s_waitcnt_depctr 0xfff
v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
v_mul_f64 v[9:10], v[11:12], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[5:6], -v[5:6], v[9:10], v[11:12]
v_div_fmas_f64 v[5:6], v[5:6], v[7:8], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fixup_f64 v[1:2], v[5:6], v[1:2], v[3:4]
v_lshlrev_b32_e32 v5, 3, v0
v_mad_u64_u32 v[3:4], null, s8, s2, v[0:1]
s_load_b128 s[0:3], s[0:1], 0x8
ds_store_b64 v5, v[1:2]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b64 v[1:2], v5
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[3:4]
v_lshlrev_b64 v[3:4], 3, v[3:4]
v_add_co_u32 v5, vcc_lo, s0, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_store_b32 v[5:6], v0, off
s_waitcnt lgkmcnt(0)
global_store_b64 v[3:4], v[1:2], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPdPiS_
.amdhsa_group_segment_fixed_size 160
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 56
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPdPiS_, .Lfunc_end0-_Z6kernelPdPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 160
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPdPiS_
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z6kernelPdPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 56
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cmath>
#include <algorithm>
#include <fstream>
#define N 100
#define nrange 20
#define bkgd 3
#define CL 0.9
__global__ void kernel(double*, int*, double*);
__device__ double poissonP(double, double);
__device__ double factorial(double n);
__global__ void kernel(double* mu, int* n, double* R) {
int thId = threadIdx.x;
int blId = blockIdx.x;
int atId = threadIdx.x + blockIdx.x * blockDim.x;
__shared__ double cacheR[nrange];
cacheR[thId] = poissonP(mu[blId], thId)/poissonP(max(0, thId - bkgd), thId);
__syncthreads();
n[atId] = thId;
R[atId] = cacheR[thId];
}
__device__ double poissonP(double mu, double n) {
return pow(mu + 3., n)*exp(-(mu + 3.))/factorial(n);
}
__device__ double factorial(double n) {
double fn = 1.;
if (n == 0) {
return 1.;
} else {
for (int i = 1; i < n + 1; i++) {
fn *= (double)i;
}
}
return fn;
}
int main() {
double* mu = new double[N];
double* R = new double[N*nrange];
int* n = new int[N*nrange];
double* dev_mu;
double* dev_R;
int* dev_n;
hipMalloc((void**)&dev_mu, N*sizeof(double));
hipMalloc((void**)&dev_R, N*nrange*sizeof(double));
hipMalloc((void**)&dev_n, N*nrange*sizeof(int));
double muMax = 10;
double muMin = 0;
double step = (muMax - muMin)/N;
for (int i = 0; i < N; i++) {
mu[i] = muMin + (double)i * step;
}
hipMemcpy(dev_mu, mu, N*sizeof(double), hipMemcpyHostToDevice);
kernel<<<N,nrange>>>(dev_mu, dev_n, dev_R);
hipMemcpy(R, dev_R, N*nrange*sizeof(int), hipMemcpyDeviceToHost);
hipMemcpy(n, dev_n, N*nrange*sizeof(int), hipMemcpyDeviceToHost);
std::ofstream ofs;
ofs.open ("ul.dat", std::ofstream::out | std::ofstream::app);
for (int i = 0; i < N; i++) {
ofs << mu[i];
for (int j = 0; j < nrange; j++) {
ofs << "," << n[j + i*nrange] << "," << R[j + i * nrange];
}
ofs << std::endl;
}
ofs.close();
hipFree(dev_mu);
hipFree(dev_n);
hipFree(dev_R);
return 0;
} | .text
.file "FeldmanCousinsPoisson.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__kernelPdPiS_ # -- Begin function _Z21__device_stub__kernelPdPiS_
.p2align 4, 0x90
.type _Z21__device_stub__kernelPdPiS_,@function
_Z21__device_stub__kernelPdPiS_: # @_Z21__device_stub__kernelPdPiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelPdPiS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPdPiS_, .Lfunc_end0-_Z21__device_stub__kernelPdPiS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3fb999999999999a # double 0.10000000000000001
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $632, %rsp # imm = 0x278
.cfi_def_cfa_offset 688
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
.cfi_escape 0x2e, 0x00
movl $800, %edi # imm = 0x320
callq _Znam
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
movl $16000, %edi # imm = 0x3E80
callq _Znam
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movl $8000, %edi # imm = 0x1F40
callq _Znam
movq %rax, %r15
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
movl $800, %esi # imm = 0x320
callq hipMalloc
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
movl $16000, %esi # imm = 0x3E80
callq hipMalloc
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $8000, %esi # imm = 0x1F40
callq hipMalloc
xorl %eax, %eax
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
xorpd %xmm1, %xmm1
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm2, %xmm2
cvtsi2sd %eax, %xmm2
mulsd %xmm0, %xmm2
addsd %xmm1, %xmm2
movsd %xmm2, (%rbx,%rax,8)
incq %rax
cmpq $100, %rax
jne .LBB1_1
# %bb.2:
movq 24(%rsp), %rdi
.cfi_escape 0x2e, 0x00
movl $800, %edx # imm = 0x320
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967316, %rdx # imm = 0x100000014
leaq 80(%rdx), %rdi
.cfi_escape 0x2e, 0x00
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
.cfi_escape 0x2e, 0x00
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
.cfi_escape 0x2e, 0x10
leaq 112(%rsp), %r9
movl $_Z6kernelPdPiS_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 16(%rsp), %rsi
.cfi_escape 0x2e, 0x00
movl $8000, %edx # imm = 0x1F40
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rsi
.cfi_escape 0x2e, 0x00
movl $8000, %edx # imm = 0x1F40
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
.cfi_escape 0x2e, 0x00
leaq 112(%rsp), %r13
movq %r13, %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev
leaq 120(%rsp), %rdi
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $.L.str, %esi
movl $17, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp1:
# %bb.5: # %.noexc
movq 112(%rsp), %rcx
addq -24(%rcx), %r13
xorl %esi, %esi
testq %rax, %rax
jne .LBB1_7
# %bb.6:
movl 32(%r13), %esi
orl $4, %esi
.LBB1_7: # %.invoke
.Ltmp2:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp3:
# %bb.8: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit
xorl %r12d, %r12d
leaq 112(%rsp), %r13
movq %rbx, 32(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB1_9: # =>This Loop Header: Depth=1
# Child Loop BB1_11 Depth 2
movsd (%rbx,%r12,8), %xmm0 # xmm0 = mem[0],zero
.Ltmp4:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp5:
# %bb.10: # %_ZNSolsEd.exit.preheader
# in Loop: Header=BB1_9 Depth=1
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_11: # Parent Loop BB1_9 Depth=1
# => This Inner Loop Header: Depth=2
.Ltmp6:
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %esi
movl $1, %edx
movq %r13, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp7:
# %bb.12: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
# in Loop: Header=BB1_11 Depth=2
movl (%r15,%rbx,4), %esi
.Ltmp8:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
callq _ZNSolsEi
.Ltmp9:
# %bb.13: # in Loop: Header=BB1_11 Depth=2
.Ltmp10:
movq %rax, %rbp
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp11:
# %bb.14: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit44
# in Loop: Header=BB1_11 Depth=2
movsd (%r14,%rbx,8), %xmm0 # xmm0 = mem[0],zero
.Ltmp12:
.cfi_escape 0x2e, 0x00
movq %rbp, %rdi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp13:
# %bb.15: # %_ZNSolsEd.exit46
# in Loop: Header=BB1_11 Depth=2
incq %rbx
cmpq $20, %rbx
jne .LBB1_11
# %bb.16: # in Loop: Header=BB1_9 Depth=1
movq 112(%rsp), %rax
movq -24(%rax), %rax
movq 352(%rsp,%rax), %rbp
testq %rbp, %rbp
je .LBB1_17
# %bb.26: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_9 Depth=1
cmpb $0, 56(%rbp)
movq 32(%rsp), %rbx # 8-byte Reload
je .LBB1_28
# %bb.27: # in Loop: Header=BB1_9 Depth=1
movzbl 67(%rbp), %eax
jmp .LBB1_30
.p2align 4, 0x90
.LBB1_28: # in Loop: Header=BB1_9 Depth=1
.Ltmp15:
.cfi_escape 0x2e, 0x00
movq %rbp, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp16:
# %bb.29: # %.noexc48
# in Loop: Header=BB1_9 Depth=1
movq (%rbp), %rax
.Ltmp17:
.cfi_escape 0x2e, 0x00
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp18:
.LBB1_30: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
# in Loop: Header=BB1_9 Depth=1
.Ltmp19:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r13, %rdi
callq _ZNSo3putEc
.Ltmp20:
# %bb.31: # %.noexc50
# in Loop: Header=BB1_9 Depth=1
.Ltmp21:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp22:
# %bb.32: # %_ZNSolsEPFRSoS_E.exit
# in Loop: Header=BB1_9 Depth=1
incq %r12
addq $160, %r14
addq $80, %r15
cmpq $100, %r12
jne .LBB1_9
# %bb.18:
.Ltmp24:
.cfi_escape 0x2e, 0x00
leaq 120(%rsp), %rdi
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp25:
# %bb.19: # %.noexc38
testq %rax, %rax
jne .LBB1_21
# %bb.20:
movq 112(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $112, %rdi
movl 144(%rsp,%rax), %esi
orl $4, %esi
.Ltmp26:
.cfi_escape 0x2e, 0x00
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp27:
.LBB1_21: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv.exit
movq 24(%rsp), %rdi
.Ltmp28:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp29:
# %bb.22:
movq 8(%rsp), %rdi
.Ltmp30:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp31:
# %bb.23:
movq 16(%rsp), %rdi
.Ltmp32:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp33:
# %bb.24:
.cfi_escape 0x2e, 0x00
leaq 112(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
xorl %eax, %eax
addq $632, %rsp # imm = 0x278
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_17:
.cfi_def_cfa_offset 688
.Ltmp35:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp36:
# %bb.25: # %.noexc47
.LBB1_36:
.Ltmp34:
jmp .LBB1_37
.LBB1_34: # %.loopexit.split-lp
.Ltmp37:
jmp .LBB1_37
.LBB1_33: # %.loopexit
.Ltmp23:
jmp .LBB1_37
.LBB1_35:
.Ltmp14:
.LBB1_37:
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
leaq 112(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp3-.Ltmp0 # Call between .Ltmp0 and .Ltmp3
.uleb128 .Ltmp34-.Lfunc_begin0 # jumps to .Ltmp34
.byte 0 # On action: cleanup
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp5-.Ltmp4 # Call between .Ltmp4 and .Ltmp5
.uleb128 .Ltmp23-.Lfunc_begin0 # jumps to .Ltmp23
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp13-.Ltmp6 # Call between .Ltmp6 and .Ltmp13
.uleb128 .Ltmp14-.Lfunc_begin0 # jumps to .Ltmp14
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp22-.Ltmp15 # Call between .Ltmp15 and .Ltmp22
.uleb128 .Ltmp23-.Lfunc_begin0 # jumps to .Ltmp23
.byte 0 # On action: cleanup
.uleb128 .Ltmp24-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp33-.Ltmp24 # Call between .Ltmp24 and .Ltmp33
.uleb128 .Ltmp34-.Lfunc_begin0 # jumps to .Ltmp34
.byte 0 # On action: cleanup
.uleb128 .Ltmp35-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp36-.Ltmp35 # Call between .Ltmp35 and .Ltmp36
.uleb128 .Ltmp37-.Lfunc_begin0 # jumps to .Ltmp37
.byte 0 # On action: cleanup
.uleb128 .Ltmp36-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Lfunc_end1-.Ltmp36 # Call between .Ltmp36 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPdPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPdPiS_,@object # @_Z6kernelPdPiS_
.section .rodata,"a",@progbits
.globl _Z6kernelPdPiS_
.p2align 3, 0x0
_Z6kernelPdPiS_:
.quad _Z21__device_stub__kernelPdPiS_
.size _Z6kernelPdPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "ul.dat"
.size .L.str, 7
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz ","
.size .L.str.1, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPdPiS_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPdPiS_
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z6kernelPdPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000219d4_00000000-6_FeldmanCousinsPoisson.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8poissonPdd
.type _Z8poissonPdd, @function
_Z8poissonPdd:
.LFB4054:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4054:
.size _Z8poissonPdd, .-_Z8poissonPdd
.globl _Z9factoriald
.type _Z9factoriald, @function
_Z9factoriald:
.LFB4055:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4055:
.size _Z9factoriald, .-_Z9factoriald
.globl _Z29__device_stub__Z6kernelPdPiS_PdPiS_
.type _Z29__device_stub__Z6kernelPdPiS_PdPiS_, @function
_Z29__device_stub__Z6kernelPdPiS_PdPiS_:
.LFB4081:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6kernelPdPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4081:
.size _Z29__device_stub__Z6kernelPdPiS_PdPiS_, .-_Z29__device_stub__Z6kernelPdPiS_PdPiS_
.globl _Z6kernelPdPiS_
.type _Z6kernelPdPiS_, @function
_Z6kernelPdPiS_:
.LFB4082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6kernelPdPiS_PdPiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4082:
.size _Z6kernelPdPiS_, .-_Z6kernelPdPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kernelPdPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPdPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.1
.LC3:
.string "ul.dat"
.LC4:
.string ","
.text
.globl main
.type main, @function
main:
.LFB4056:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4056
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $600, %rsp
.cfi_def_cfa_offset 656
movq %fs:40, %rax
movq %rax, 584(%rsp)
xorl %eax, %eax
movl $800, %edi
.LEHB0:
call _Znam@PLT
movq %rax, %r15
movl $16000, %edi
call _Znam@PLT
movq %rax, %rbx
movl $8000, %edi
call _Znam@PLT
movq %rax, %r14
leaq 16(%rsp), %rdi
movl $800, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $16000, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $8000, %esi
call cudaMalloc@PLT
movl $0, %eax
movsd .LC1(%rip), %xmm2
pxor %xmm1, %xmm1
.L18:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd %xmm2, %xmm0
addsd %xmm1, %xmm0
movsd %xmm0, (%r15,%rax,8)
addq $1, %rax
cmpq $100, %rax
jne .L18
movl $1, %ecx
movl $800, %edx
movq %r15, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $20, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $100, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L19:
movl $2, %ecx
movl $8000, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $8000, %edx
movq 32(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
leaq 64(%rsp), %rbp
movq %rbp, %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE0:
movl $17, %edx
leaq .LC3(%rip), %rsi
movq %rbp, %rdi
.LEHB1:
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
.LEHE1:
jmp .L36
.L35:
movq 24(%rsp), %rdx
movq 32(%rsp), %rsi
movq 16(%rsp), %rdi
.LEHB2:
call _Z29__device_stub__Z6kernelPdPiS_PdPiS_
.LEHE2:
jmp .L19
.L36:
movq %rbx, %r13
leaq 16000(%rbx), %rax
movq %rax, 8(%rsp)
leaq .LC4(%rip), %r12
jmp .L25
.L43:
movl $0, %ebx
jmp .L20
.L38:
movl (%r14,%rbx,4), %esi
leaq 64(%rsp), %rdi
.LEHB3:
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $1, %edx
movq %r12, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movsd 0(%r13,%rbx,8), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
addq $1, %rbx
cmpq $20, %rbx
je .L37
.L20:
leaq 64(%rsp), %rdi
movl $1, %edx
movq %r12, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L38
.L37:
movq 64(%rsp), %rax
movq -24(%rax), %rax
movq 304(%rsp,%rax), %rbx
testq %rbx, %rbx
je .L39
cmpb $0, 56(%rbx)
je .L23
movzbl 67(%rbx), %esi
.L24:
movsbl %sil, %esi
leaq 64(%rsp), %rdi
call _ZNSo3putEc@PLT
jmp .L40
.L39:
movq 584(%rsp), %rax
subq %fs:40, %rax
jne .L41
call _ZSt16__throw_bad_castv@PLT
.L29:
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 584(%rsp), %rax
subq %fs:40, %rax
je .L27
call __stack_chk_fail@PLT
.L41:
call __stack_chk_fail@PLT
.L23:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L24
.L40:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $8, %r15
addq $160, %r13
addq $80, %r14
movq 8(%rsp), %rax
cmpq %rax, %r13
je .L42
.L25:
movsd (%r15), %xmm0
leaq 64(%rsp), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
jmp .L43
.L42:
leaq 64(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
.LEHE3:
leaq 64(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 584(%rsp), %rax
subq %fs:40, %rax
jne .L44
movl $0, %eax
addq $600, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L44:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4056:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4056:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4056-.LLSDACSB4056
.LLSDACSB4056:
.uleb128 .LEHB0-.LFB4056
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4056
.uleb128 .LEHE1-.LEHB1
.uleb128 .L29-.LFB4056
.uleb128 0
.uleb128 .LEHB2-.LFB4056
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB4056
.uleb128 .LEHE3-.LEHB3
.uleb128 .L29-.LFB4056
.uleb128 0
.uleb128 .LEHB4-.LFB4056
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE4056:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -1717986918
.long 1069128089
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "FeldmanCousinsPoisson.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__kernelPdPiS_ # -- Begin function _Z21__device_stub__kernelPdPiS_
.p2align 4, 0x90
.type _Z21__device_stub__kernelPdPiS_,@function
_Z21__device_stub__kernelPdPiS_: # @_Z21__device_stub__kernelPdPiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelPdPiS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPdPiS_, .Lfunc_end0-_Z21__device_stub__kernelPdPiS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3fb999999999999a # double 0.10000000000000001
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $632, %rsp # imm = 0x278
.cfi_def_cfa_offset 688
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
.cfi_escape 0x2e, 0x00
movl $800, %edi # imm = 0x320
callq _Znam
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
movl $16000, %edi # imm = 0x3E80
callq _Znam
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movl $8000, %edi # imm = 0x1F40
callq _Znam
movq %rax, %r15
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
movl $800, %esi # imm = 0x320
callq hipMalloc
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
movl $16000, %esi # imm = 0x3E80
callq hipMalloc
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $8000, %esi # imm = 0x1F40
callq hipMalloc
xorl %eax, %eax
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
xorpd %xmm1, %xmm1
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm2, %xmm2
cvtsi2sd %eax, %xmm2
mulsd %xmm0, %xmm2
addsd %xmm1, %xmm2
movsd %xmm2, (%rbx,%rax,8)
incq %rax
cmpq $100, %rax
jne .LBB1_1
# %bb.2:
movq 24(%rsp), %rdi
.cfi_escape 0x2e, 0x00
movl $800, %edx # imm = 0x320
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967316, %rdx # imm = 0x100000014
leaq 80(%rdx), %rdi
.cfi_escape 0x2e, 0x00
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
.cfi_escape 0x2e, 0x00
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
.cfi_escape 0x2e, 0x10
leaq 112(%rsp), %r9
movl $_Z6kernelPdPiS_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 16(%rsp), %rsi
.cfi_escape 0x2e, 0x00
movl $8000, %edx # imm = 0x1F40
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rsi
.cfi_escape 0x2e, 0x00
movl $8000, %edx # imm = 0x1F40
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
.cfi_escape 0x2e, 0x00
leaq 112(%rsp), %r13
movq %r13, %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev
leaq 120(%rsp), %rdi
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $.L.str, %esi
movl $17, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp1:
# %bb.5: # %.noexc
movq 112(%rsp), %rcx
addq -24(%rcx), %r13
xorl %esi, %esi
testq %rax, %rax
jne .LBB1_7
# %bb.6:
movl 32(%r13), %esi
orl $4, %esi
.LBB1_7: # %.invoke
.Ltmp2:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp3:
# %bb.8: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit
xorl %r12d, %r12d
leaq 112(%rsp), %r13
movq %rbx, 32(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB1_9: # =>This Loop Header: Depth=1
# Child Loop BB1_11 Depth 2
movsd (%rbx,%r12,8), %xmm0 # xmm0 = mem[0],zero
.Ltmp4:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp5:
# %bb.10: # %_ZNSolsEd.exit.preheader
# in Loop: Header=BB1_9 Depth=1
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_11: # Parent Loop BB1_9 Depth=1
# => This Inner Loop Header: Depth=2
.Ltmp6:
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %esi
movl $1, %edx
movq %r13, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp7:
# %bb.12: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
# in Loop: Header=BB1_11 Depth=2
movl (%r15,%rbx,4), %esi
.Ltmp8:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
callq _ZNSolsEi
.Ltmp9:
# %bb.13: # in Loop: Header=BB1_11 Depth=2
.Ltmp10:
movq %rax, %rbp
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp11:
# %bb.14: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit44
# in Loop: Header=BB1_11 Depth=2
movsd (%r14,%rbx,8), %xmm0 # xmm0 = mem[0],zero
.Ltmp12:
.cfi_escape 0x2e, 0x00
movq %rbp, %rdi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp13:
# %bb.15: # %_ZNSolsEd.exit46
# in Loop: Header=BB1_11 Depth=2
incq %rbx
cmpq $20, %rbx
jne .LBB1_11
# %bb.16: # in Loop: Header=BB1_9 Depth=1
movq 112(%rsp), %rax
movq -24(%rax), %rax
movq 352(%rsp,%rax), %rbp
testq %rbp, %rbp
je .LBB1_17
# %bb.26: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_9 Depth=1
cmpb $0, 56(%rbp)
movq 32(%rsp), %rbx # 8-byte Reload
je .LBB1_28
# %bb.27: # in Loop: Header=BB1_9 Depth=1
movzbl 67(%rbp), %eax
jmp .LBB1_30
.p2align 4, 0x90
.LBB1_28: # in Loop: Header=BB1_9 Depth=1
.Ltmp15:
.cfi_escape 0x2e, 0x00
movq %rbp, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp16:
# %bb.29: # %.noexc48
# in Loop: Header=BB1_9 Depth=1
movq (%rbp), %rax
.Ltmp17:
.cfi_escape 0x2e, 0x00
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp18:
.LBB1_30: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
# in Loop: Header=BB1_9 Depth=1
.Ltmp19:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r13, %rdi
callq _ZNSo3putEc
.Ltmp20:
# %bb.31: # %.noexc50
# in Loop: Header=BB1_9 Depth=1
.Ltmp21:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp22:
# %bb.32: # %_ZNSolsEPFRSoS_E.exit
# in Loop: Header=BB1_9 Depth=1
incq %r12
addq $160, %r14
addq $80, %r15
cmpq $100, %r12
jne .LBB1_9
# %bb.18:
.Ltmp24:
.cfi_escape 0x2e, 0x00
leaq 120(%rsp), %rdi
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp25:
# %bb.19: # %.noexc38
testq %rax, %rax
jne .LBB1_21
# %bb.20:
movq 112(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $112, %rdi
movl 144(%rsp,%rax), %esi
orl $4, %esi
.Ltmp26:
.cfi_escape 0x2e, 0x00
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp27:
.LBB1_21: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv.exit
movq 24(%rsp), %rdi
.Ltmp28:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp29:
# %bb.22:
movq 8(%rsp), %rdi
.Ltmp30:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp31:
# %bb.23:
movq 16(%rsp), %rdi
.Ltmp32:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp33:
# %bb.24:
.cfi_escape 0x2e, 0x00
leaq 112(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
xorl %eax, %eax
addq $632, %rsp # imm = 0x278
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_17:
.cfi_def_cfa_offset 688
.Ltmp35:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp36:
# %bb.25: # %.noexc47
.LBB1_36:
.Ltmp34:
jmp .LBB1_37
.LBB1_34: # %.loopexit.split-lp
.Ltmp37:
jmp .LBB1_37
.LBB1_33: # %.loopexit
.Ltmp23:
jmp .LBB1_37
.LBB1_35:
.Ltmp14:
.LBB1_37:
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
leaq 112(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp3-.Ltmp0 # Call between .Ltmp0 and .Ltmp3
.uleb128 .Ltmp34-.Lfunc_begin0 # jumps to .Ltmp34
.byte 0 # On action: cleanup
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp5-.Ltmp4 # Call between .Ltmp4 and .Ltmp5
.uleb128 .Ltmp23-.Lfunc_begin0 # jumps to .Ltmp23
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp13-.Ltmp6 # Call between .Ltmp6 and .Ltmp13
.uleb128 .Ltmp14-.Lfunc_begin0 # jumps to .Ltmp14
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp22-.Ltmp15 # Call between .Ltmp15 and .Ltmp22
.uleb128 .Ltmp23-.Lfunc_begin0 # jumps to .Ltmp23
.byte 0 # On action: cleanup
.uleb128 .Ltmp24-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp33-.Ltmp24 # Call between .Ltmp24 and .Ltmp33
.uleb128 .Ltmp34-.Lfunc_begin0 # jumps to .Ltmp34
.byte 0 # On action: cleanup
.uleb128 .Ltmp35-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp36-.Ltmp35 # Call between .Ltmp35 and .Ltmp36
.uleb128 .Ltmp37-.Lfunc_begin0 # jumps to .Ltmp37
.byte 0 # On action: cleanup
.uleb128 .Ltmp36-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Lfunc_end1-.Ltmp36 # Call between .Ltmp36 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPdPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPdPiS_,@object # @_Z6kernelPdPiS_
.section .rodata,"a",@progbits
.globl _Z6kernelPdPiS_
.p2align 3, 0x0
_Z6kernelPdPiS_:
.quad _Z21__device_stub__kernelPdPiS_
.size _Z6kernelPdPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "ul.dat"
.size .L.str, 7
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz ","
.size .L.str.1, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPdPiS_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPdPiS_
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z6kernelPdPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void reduce6(const float* g_idata, float* g_odata, float* g_omask, unsigned int n) {
extern __shared__ float sharedData[];
float* sdata = &sharedData[0];
float* smask = &sharedData[blockDim.x];
// perform first level of reduction,
// reading from global memory, writing to shared memory
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * blockDim.x * 2 + threadIdx.x;
unsigned int gridSize = blockDim.x * 2 * gridDim.x;
sdata[tid] = 0;
smask[tid] = 0;
// we reduce multiple elements per thread. The number is determined by the
// number of active thread blocks (via gridSize). More blocks will result
// in a larger gridSize and therefore fewer elements per thread
while (i < n) {
sdata[tid] += g_idata[i];
smask[tid] += (g_idata[i] > 0 ? 1 : 0);
if (i + blockDim.x < n) {
sdata[tid] += g_idata[i + blockDim.x];
smask[tid] += (g_idata[i + blockDim.x] > 0 ? 1 : 0);
}
i += gridSize;
}
__syncthreads();
// do reduction in shared mem
if (blockDim.x >= 512) {
if (tid < 256) {
sdata[tid] += sdata[tid + 256];
smask[tid] += smask[tid + 256];
}
__syncthreads();
}
if (blockDim.x >= 256) {
if (tid < 128) {
sdata[tid] += sdata[tid + 128];
smask[tid] += smask[tid + 128];
}
__syncthreads();
}
if (blockDim.x >= 128) {
if (tid < 64) {
sdata[tid] += sdata[tid + 64];
smask[tid] += smask[tid + 64];
}
__syncthreads();
}
if (tid < 32) {
if (blockDim.x >= 64) {
sdata[tid] += sdata[tid + 32];
smask[tid] += smask[tid + 32];
}
if (blockDim.x >= 32) {
sdata[tid] += sdata[tid + 16];
smask[tid] += smask[tid + 16];
}
if (blockDim.x >= 16) {
sdata[tid] += sdata[tid + 8];
smask[tid] += smask[tid + 8];
}
if (blockDim.x >= 8) {
sdata[tid] += sdata[tid + 4];
smask[tid] += smask[tid + 4];
}
if (blockDim.x >= 4) {
sdata[tid] += sdata[tid + 2];
smask[tid] += smask[tid + 2];
}
if (blockDim.x >= 2) {
sdata[tid] += sdata[tid + 1];
smask[tid] += smask[tid + 1];
}
}
// write result for this block to global mem
if (tid == 0) {
g_odata[blockIdx.x] = sdata[0];
g_omask[blockIdx.x] = smask[0];
}
} | code for sm_80
Function : _Z7reduce6PKfPfS1_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0020*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ MOV R6, c[0x0][0x0] ; /* 0x0000000000067a02 */
/* 0x000fe20000000f00 */
/*0040*/ USHF.L.U32 UR4, UR4, 0x2, URZ ; /* 0x0000000204047899 */
/* 0x000fe2000800063f */
/*0050*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e620000002500 */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0070*/ SHF.L.U32 R6, R6, 0x1, RZ ; /* 0x0000000106067819 */
/* 0x000fe200000006ff */
/*0080*/ BSSY B0, 0x2c0 ; /* 0x0000023000007945 */
/* 0x000fe20003800000 */
/*0090*/ SHF.L.U32 R2, R3, 0x2, RZ ; /* 0x0000000203027819 */
/* 0x001fe200000006ff */
/*00a0*/ STS [R3.X4], RZ ; /* 0x000000ff03007388 */
/* 0x0001e40000004800 */
/*00b0*/ IMAD R4, R6, R0, R3 ; /* 0x0000000006047224 */
/* 0x002fc400078e0203 */
/*00c0*/ STS [R2+UR4], RZ ; /* 0x000000ff02007988 */
/* 0x0001e60008000804 */
/*00d0*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fda0003f06070 */
/*00e0*/ @P0 BRA 0x2b0 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*00f0*/ MOV R7, R4 ; /* 0x0000000400077202 */
/* 0x001fe40000000f00 */
/*0100*/ HFMA2.MMA R12, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0c7435 */
/* 0x000fe200000001ff */
/*0110*/ LDS R8, [R3.X4] ; /* 0x0000000003087984 */
/* 0x001e320000004800 */
/*0120*/ IMAD.WIDE.U32 R4, R7, R12, c[0x0][0x160] ; /* 0x0000580007047625 */
/* 0x000fcc00078e000c */
/*0130*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000e22000c1e1900 */
/*0140*/ IADD3 R11, R7, c[0x0][0x0], RZ ; /* 0x00000000070b7a10 */
/* 0x000fe20007ffe0ff */
/*0150*/ IMAD R7, R6, c[0x0][0xc], R7 ; /* 0x0000030006077a24 */
/* 0x000fe200078e0207 */
/*0160*/ BSSY B1, 0x2a0 ; /* 0x0000013000017945 */
/* 0x000fe40003800000 */
/*0170*/ ISETP.GE.U32.AND P0, PT, R11, c[0x0][0x178], PT ; /* 0x00005e000b007a0c */
/* 0x000fe40003f06070 */
/*0180*/ ISETP.GE.U32.AND P1, PT, R7, c[0x0][0x178], PT ; /* 0x00005e0007007a0c */
/* 0x000fe20003f26070 */
/*0190*/ FADD R8, R8, R5 ; /* 0x0000000508087221 */
/* 0x001fe20000000000 */
/*01a0*/ FSET.BF.GT.AND R9, R5, RZ, PT ; /* 0x000000ff0509720a */
/* 0x000fc80003804000 */
/*01b0*/ STS [R3.X4], R8 ; /* 0x0000000803007388 */
/* 0x000fe80000004800 */
/*01c0*/ LDS R10, [R2+UR4] ; /* 0x00000004020a7984 */
/* 0x000e240008000800 */
/*01d0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x001fca0000000000 */
/*01e0*/ STS [R2+UR4], R9 ; /* 0x0000000902007988 */
/* 0x0001e20008000804 */
/*01f0*/ @P0 BRA 0x290 ; /* 0x0000009000000947 */
/* 0x000fea0003800000 */
/*0200*/ IMAD.WIDE.U32 R4, R11, R12, c[0x0][0x160] ; /* 0x000058000b047625 */
/* 0x000fe200078e000c */
/*0210*/ LDS R8, [R3.X4] ; /* 0x0000000003087984 */
/* 0x000e6a0000004800 */
/*0220*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000e64000c1e1900 */
/*0230*/ FADD R8, R8, R5 ; /* 0x0000000508087221 */
/* 0x002fe20000000000 */
/*0240*/ FSET.BF.GT.AND R9, R5, RZ, PT ; /* 0x000000ff0509720a */
/* 0x001fc80003804000 */
/*0250*/ STS [R3.X4], R8 ; /* 0x0000000803007388 */
/* 0x000fe80000004800 */
/*0260*/ LDS R10, [R2+UR4] ; /* 0x00000004020a7984 */
/* 0x000e240008000800 */
/*0270*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x001fca0000000000 */
/*0280*/ STS [R2+UR4], R9 ; /* 0x0000000902007988 */
/* 0x0001e40008000804 */
/*0290*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*02a0*/ @!P1 BRA 0x100 ; /* 0xfffffe5000009947 */
/* 0x000fea000383ffff */
/*02b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*02c0*/ MOV R7, c[0x0][0x0] ; /* 0x0000000000077a02 */
/* 0x000fe20000000f00 */
/*02d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02e0*/ ISETP.GT.U32.AND P0, PT, R3, 0x1f, PT ; /* 0x0000001f0300780c */
/* 0x000fe40003f04070 */
/*02f0*/ ISETP.GE.U32.AND P1, PT, R7.reuse, 0x200, PT ; /* 0x000002000700780c */
/* 0x040fe40003f26070 */
/*0300*/ ISETP.GE.U32.AND P2, PT, R7.reuse, 0x100, PT ; /* 0x000001000700780c */
/* 0x040fe40003f46070 */
/*0310*/ ISETP.GE.U32.AND P3, PT, R7, 0x80, PT ; /* 0x000000800700780c */
/* 0x000fd20003f66070 */
/*0320*/ @!P1 BRA 0x3d0 ; /* 0x000000a000009947 */
/* 0x000fea0003800000 */
/*0330*/ ISETP.GT.U32.AND P1, PT, R3, 0xff, PT ; /* 0x000000ff0300780c */
/* 0x000fda0003f24070 */
/*0340*/ @!P1 LDS R4, [R3.X4] ; /* 0x0000000003049984 */
/* 0x000fe80000004800 */
/*0350*/ @!P1 LDS R5, [R3.X4+0x400] ; /* 0x0004000003059984 */
/* 0x000e240000004800 */
/*0360*/ @!P1 FADD R4, R4, R5 ; /* 0x0000000504049221 */
/* 0x001fca0000000000 */
/*0370*/ @!P1 STS [R3.X4], R4 ; /* 0x0000000403009388 */
/* 0x000fe80000004800 */
/*0380*/ @!P1 LDS R5, [R2+UR4] ; /* 0x0000000402059984 */
/* 0x000fe80008000800 */
/*0390*/ @!P1 LDS R6, [R2+UR4+0x400] ; /* 0x0004000402069984 */
/* 0x000e240008000800 */
/*03a0*/ @!P1 FADD R5, R5, R6 ; /* 0x0000000605059221 */
/* 0x001fca0000000000 */
/*03b0*/ @!P1 STS [R2+UR4], R5 ; /* 0x0000000502009988 */
/* 0x0001e80008000804 */
/*03c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03d0*/ @!P2 BRA 0x480 ; /* 0x000000a00000a947 */
/* 0x000fea0003800000 */
/*03e0*/ ISETP.GT.U32.AND P1, PT, R3, 0x7f, PT ; /* 0x0000007f0300780c */
/* 0x000fda0003f24070 */
/*03f0*/ @!P1 LDS R4, [R3.X4] ; /* 0x0000000003049984 */
/* 0x000fe80000004800 */
/*0400*/ @!P1 LDS R5, [R3.X4+0x200] ; /* 0x0002000003059984 */
/* 0x001e240000004800 */
/*0410*/ @!P1 FADD R4, R4, R5 ; /* 0x0000000504049221 */
/* 0x001fca0000000000 */
/*0420*/ @!P1 STS [R3.X4], R4 ; /* 0x0000000403009388 */
/* 0x000fe80000004800 */
/*0430*/ @!P1 LDS R5, [R2+UR4] ; /* 0x0000000402059984 */
/* 0x000fe80008000800 */
/*0440*/ @!P1 LDS R6, [R2+UR4+0x200] ; /* 0x0002000402069984 */
/* 0x000e240008000800 */
/*0450*/ @!P1 FADD R5, R5, R6 ; /* 0x0000000605059221 */
/* 0x001fca0000000000 */
/*0460*/ @!P1 STS [R2+UR4], R5 ; /* 0x0000000502009988 */
/* 0x0001e80008000804 */
/*0470*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0480*/ @!P3 BRA 0x530 ; /* 0x000000a00000b947 */
/* 0x000fea0003800000 */
/*0490*/ ISETP.GT.U32.AND P1, PT, R3, 0x3f, PT ; /* 0x0000003f0300780c */
/* 0x000fda0003f24070 */
/*04a0*/ @!P1 LDS R4, [R3.X4] ; /* 0x0000000003049984 */
/* 0x000fe80000004800 */
/*04b0*/ @!P1 LDS R5, [R3.X4+0x100] ; /* 0x0001000003059984 */
/* 0x001e240000004800 */
/*04c0*/ @!P1 FADD R4, R4, R5 ; /* 0x0000000504049221 */
/* 0x001fca0000000000 */
/*04d0*/ @!P1 STS [R3.X4], R4 ; /* 0x0000000403009388 */
/* 0x000fe80000004800 */
/*04e0*/ @!P1 LDS R5, [R2+UR4] ; /* 0x0000000402059984 */
/* 0x000fe80008000800 */
/*04f0*/ @!P1 LDS R6, [R2+UR4+0x100] ; /* 0x0001000402069984 */
/* 0x000e240008000800 */
/*0500*/ @!P1 FADD R5, R5, R6 ; /* 0x0000000605059221 */
/* 0x001fca0000000000 */
/*0510*/ @!P1 STS [R2+UR4], R5 ; /* 0x0000000502009988 */
/* 0x0001e80008000804 */
/*0520*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0530*/ BSSY B0, 0x920 ; /* 0x000003e000007945 */
/* 0x000fe20003800000 */
/*0540*/ @P0 BRA 0x910 ; /* 0x000003c000000947 */
/* 0x000fea0003800000 */
/*0550*/ ISETP.GE.U32.AND P0, PT, R7.reuse, 0x40, PT ; /* 0x000000400700780c */
/* 0x040fe40003f06070 */
/*0560*/ ISETP.GE.U32.AND P1, PT, R7.reuse, 0x20, PT ; /* 0x000000200700780c */
/* 0x040fe40003f26070 */
/*0570*/ ISETP.GE.U32.AND P2, PT, R7.reuse, 0x10, PT ; /* 0x000000100700780c */
/* 0x040fe40003f46070 */
/*0580*/ ISETP.GE.U32.AND P3, PT, R7, 0x8, PT ; /* 0x000000080700780c */
/* 0x000fc40003f66070 */
/*0590*/ ISETP.GE.U32.AND P4, PT, R7.reuse, 0x4, PT ; /* 0x000000040700780c */
/* 0x040fe40003f86070 */
/*05a0*/ ISETP.GE.U32.AND P5, PT, R7, 0x2, PT ; /* 0x000000020700780c */
/* 0x000fc60003fa6070 */
/*05b0*/ @!P0 BRA 0x640 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*05c0*/ LDS R4, [R3.X4] ; /* 0x0000000003047984 */
/* 0x000fe80000004800 */
/*05d0*/ LDS R5, [R3.X4+0x80] ; /* 0x0000800003057984 */
/* 0x001e240000004800 */
/*05e0*/ FADD R4, R4, R5 ; /* 0x0000000504047221 */
/* 0x001fca0000000000 */
/*05f0*/ STS [R3.X4], R4 ; /* 0x0000000403007388 */
/* 0x000fe80000004800 */
/*0600*/ LDS R5, [R2+UR4] ; /* 0x0000000402057984 */
/* 0x000fe80008000800 */
/*0610*/ LDS R6, [R2+UR4+0x80] ; /* 0x0000800402067984 */
/* 0x000e240008000800 */
/*0620*/ FADD R5, R5, R6 ; /* 0x0000000605057221 */
/* 0x001fca0000000000 */
/*0630*/ STS [R2+UR4], R5 ; /* 0x0000000502007988 */
/* 0x0001e40008000804 */
/*0640*/ @!P1 BRA 0x6d0 ; /* 0x0000008000009947 */
/* 0x000fea0003800000 */
/*0650*/ LDS R4, [R3.X4] ; /* 0x0000000003047984 */
/* 0x000fe80000004800 */
/*0660*/ LDS R5, [R3.X4+0x40] ; /* 0x0000400003057984 */
/* 0x001e240000004800 */
/*0670*/ FADD R4, R4, R5 ; /* 0x0000000504047221 */
/* 0x001fca0000000000 */
/*0680*/ STS [R3.X4], R4 ; /* 0x0000000403007388 */
/* 0x000fe80000004800 */
/*0690*/ LDS R5, [R2+UR4] ; /* 0x0000000402057984 */
/* 0x000fe80008000800 */
/*06a0*/ LDS R6, [R2+UR4+0x40] ; /* 0x0000400402067984 */
/* 0x000e240008000800 */
/*06b0*/ FADD R5, R5, R6 ; /* 0x0000000605057221 */
/* 0x001fca0000000000 */
/*06c0*/ STS [R2+UR4], R5 ; /* 0x0000000502007988 */
/* 0x0001e40008000804 */
/*06d0*/ @!P2 BRA 0x760 ; /* 0x000000800000a947 */
/* 0x000fea0003800000 */
/*06e0*/ LDS R4, [R3.X4] ; /* 0x0000000003047984 */
/* 0x000fe80000004800 */
/*06f0*/ LDS R5, [R3.X4+0x20] ; /* 0x0000200003057984 */
/* 0x001e240000004800 */
/*0700*/ FADD R4, R4, R5 ; /* 0x0000000504047221 */
/* 0x001fca0000000000 */
/*0710*/ STS [R3.X4], R4 ; /* 0x0000000403007388 */
/* 0x000fe80000004800 */
/*0720*/ LDS R5, [R2+UR4] ; /* 0x0000000402057984 */
/* 0x000fe80008000800 */
/*0730*/ LDS R6, [R2+UR4+0x20] ; /* 0x0000200402067984 */
/* 0x000e240008000800 */
/*0740*/ FADD R5, R5, R6 ; /* 0x0000000605057221 */
/* 0x001fca0000000000 */
/*0750*/ STS [R2+UR4], R5 ; /* 0x0000000502007988 */
/* 0x0001e40008000804 */
/*0760*/ @!P3 BRA 0x7f0 ; /* 0x000000800000b947 */
/* 0x000fea0003800000 */
/*0770*/ LDS R4, [R3.X4] ; /* 0x0000000003047984 */
/* 0x000fe80000004800 */
/*0780*/ LDS R5, [R3.X4+0x10] ; /* 0x0000100003057984 */
/* 0x001e240000004800 */
/*0790*/ FADD R4, R4, R5 ; /* 0x0000000504047221 */
/* 0x001fca0000000000 */
/*07a0*/ STS [R3.X4], R4 ; /* 0x0000000403007388 */
/* 0x000fe80000004800 */
/*07b0*/ LDS R5, [R2+UR4] ; /* 0x0000000402057984 */
/* 0x000fe80008000800 */
/*07c0*/ LDS R6, [R2+UR4+0x10] ; /* 0x0000100402067984 */
/* 0x000e240008000800 */
/*07d0*/ FADD R5, R5, R6 ; /* 0x0000000605057221 */
/* 0x001fca0000000000 */
/*07e0*/ STS [R2+UR4], R5 ; /* 0x0000000502007988 */
/* 0x0001e40008000804 */
/*07f0*/ @!P4 BRA 0x880 ; /* 0x000000800000c947 */
/* 0x000fea0003800000 */
/*0800*/ LDS R4, [R3.X4] ; /* 0x0000000003047984 */
/* 0x000fe80000004800 */
/*0810*/ LDS R5, [R3.X4+0x8] ; /* 0x0000080003057984 */
/* 0x001e240000004800 */
/*0820*/ FADD R4, R4, R5 ; /* 0x0000000504047221 */
/* 0x001fca0000000000 */
/*0830*/ STS [R3.X4], R4 ; /* 0x0000000403007388 */
/* 0x000fe80000004800 */
/*0840*/ LDS R5, [R2+UR4] ; /* 0x0000000402057984 */
/* 0x000fe80008000800 */
/*0850*/ LDS R6, [R2+UR4+0x8] ; /* 0x0000080402067984 */
/* 0x000e240008000800 */
/*0860*/ FADD R5, R5, R6 ; /* 0x0000000605057221 */
/* 0x001fca0000000000 */
/*0870*/ STS [R2+UR4], R5 ; /* 0x0000000502007988 */
/* 0x0001e40008000804 */
/*0880*/ @!P5 BRA 0x910 ; /* 0x000000800000d947 */
/* 0x000fea0003800000 */
/*0890*/ LDS R4, [R3.X4] ; /* 0x0000000003047984 */
/* 0x000fe80000004800 */
/*08a0*/ LDS R5, [R3.X4+0x4] ; /* 0x0000040003057984 */
/* 0x001e240000004800 */
/*08b0*/ FADD R4, R4, R5 ; /* 0x0000000504047221 */
/* 0x001fca0000000000 */
/*08c0*/ STS [R3.X4], R4 ; /* 0x0000000403007388 */
/* 0x000fe80000004800 */
/*08d0*/ LDS R5, [R2+UR4] ; /* 0x0000000402057984 */
/* 0x000fe80008000800 */
/*08e0*/ LDS R6, [R2+UR4+0x4] ; /* 0x0000040402067984 */
/* 0x000e240008000800 */
/*08f0*/ FADD R5, R5, R6 ; /* 0x0000000605057221 */
/* 0x001fca0000000000 */
/*0900*/ STS [R2+UR4], R5 ; /* 0x0000000502007988 */
/* 0x0001e40008000804 */
/*0910*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0920*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*0930*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0940*/ LDS R7, [RZ] ; /* 0x00000000ff077984 */
/* 0x000e620000000800 */
/*0950*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x001fc600000001ff */
/*0960*/ LDS R9, [UR4] ; /* 0x00000004ff097984 */
/* 0x000e2e0008000800 */
/*0970*/ IMAD.WIDE.U32 R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0005 */
/*0980*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fe200078e0005 */
/*0990*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x002fe8000c101906 */
/*09a0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x001fe2000c101906 */
/*09b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*09c0*/ BRA 0x9c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void reduce6(const float* g_idata, float* g_odata, float* g_omask, unsigned int n) {
extern __shared__ float sharedData[];
float* sdata = &sharedData[0];
float* smask = &sharedData[blockDim.x];
// perform first level of reduction,
// reading from global memory, writing to shared memory
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * blockDim.x * 2 + threadIdx.x;
unsigned int gridSize = blockDim.x * 2 * gridDim.x;
sdata[tid] = 0;
smask[tid] = 0;
// we reduce multiple elements per thread. The number is determined by the
// number of active thread blocks (via gridSize). More blocks will result
// in a larger gridSize and therefore fewer elements per thread
while (i < n) {
sdata[tid] += g_idata[i];
smask[tid] += (g_idata[i] > 0 ? 1 : 0);
if (i + blockDim.x < n) {
sdata[tid] += g_idata[i + blockDim.x];
smask[tid] += (g_idata[i + blockDim.x] > 0 ? 1 : 0);
}
i += gridSize;
}
__syncthreads();
// do reduction in shared mem
if (blockDim.x >= 512) {
if (tid < 256) {
sdata[tid] += sdata[tid + 256];
smask[tid] += smask[tid + 256];
}
__syncthreads();
}
if (blockDim.x >= 256) {
if (tid < 128) {
sdata[tid] += sdata[tid + 128];
smask[tid] += smask[tid + 128];
}
__syncthreads();
}
if (blockDim.x >= 128) {
if (tid < 64) {
sdata[tid] += sdata[tid + 64];
smask[tid] += smask[tid + 64];
}
__syncthreads();
}
if (tid < 32) {
if (blockDim.x >= 64) {
sdata[tid] += sdata[tid + 32];
smask[tid] += smask[tid + 32];
}
if (blockDim.x >= 32) {
sdata[tid] += sdata[tid + 16];
smask[tid] += smask[tid + 16];
}
if (blockDim.x >= 16) {
sdata[tid] += sdata[tid + 8];
smask[tid] += smask[tid + 8];
}
if (blockDim.x >= 8) {
sdata[tid] += sdata[tid + 4];
smask[tid] += smask[tid + 4];
}
if (blockDim.x >= 4) {
sdata[tid] += sdata[tid + 2];
smask[tid] += smask[tid + 2];
}
if (blockDim.x >= 2) {
sdata[tid] += sdata[tid + 1];
smask[tid] += smask[tid + 1];
}
}
// write result for this block to global mem
if (tid == 0) {
g_odata[blockIdx.x] = sdata[0];
g_omask[blockIdx.x] = smask[0];
}
} | .file "tmpxft_00095adb_00000000-6_reduce6.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z7reduce6PKfPfS1_jPKfPfS1_j
.type _Z33__device_stub__Z7reduce6PKfPfS1_jPKfPfS1_j, @function
_Z33__device_stub__Z7reduce6PKfPfS1_jPKfPfS1_j:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7reduce6PKfPfS1_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z7reduce6PKfPfS1_jPKfPfS1_j, .-_Z33__device_stub__Z7reduce6PKfPfS1_jPKfPfS1_j
.globl _Z7reduce6PKfPfS1_j
.type _Z7reduce6PKfPfS1_j, @function
_Z7reduce6PKfPfS1_j:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z7reduce6PKfPfS1_jPKfPfS1_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7reduce6PKfPfS1_j, .-_Z7reduce6PKfPfS1_j
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7reduce6PKfPfS1_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7reduce6PKfPfS1_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void reduce6(const float* g_idata, float* g_odata, float* g_omask, unsigned int n) {
extern __shared__ float sharedData[];
float* sdata = &sharedData[0];
float* smask = &sharedData[blockDim.x];
// perform first level of reduction,
// reading from global memory, writing to shared memory
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * blockDim.x * 2 + threadIdx.x;
unsigned int gridSize = blockDim.x * 2 * gridDim.x;
sdata[tid] = 0;
smask[tid] = 0;
// we reduce multiple elements per thread. The number is determined by the
// number of active thread blocks (via gridSize). More blocks will result
// in a larger gridSize and therefore fewer elements per thread
while (i < n) {
sdata[tid] += g_idata[i];
smask[tid] += (g_idata[i] > 0 ? 1 : 0);
if (i + blockDim.x < n) {
sdata[tid] += g_idata[i + blockDim.x];
smask[tid] += (g_idata[i + blockDim.x] > 0 ? 1 : 0);
}
i += gridSize;
}
__syncthreads();
// do reduction in shared mem
if (blockDim.x >= 512) {
if (tid < 256) {
sdata[tid] += sdata[tid + 256];
smask[tid] += smask[tid + 256];
}
__syncthreads();
}
if (blockDim.x >= 256) {
if (tid < 128) {
sdata[tid] += sdata[tid + 128];
smask[tid] += smask[tid + 128];
}
__syncthreads();
}
if (blockDim.x >= 128) {
if (tid < 64) {
sdata[tid] += sdata[tid + 64];
smask[tid] += smask[tid + 64];
}
__syncthreads();
}
if (tid < 32) {
if (blockDim.x >= 64) {
sdata[tid] += sdata[tid + 32];
smask[tid] += smask[tid + 32];
}
if (blockDim.x >= 32) {
sdata[tid] += sdata[tid + 16];
smask[tid] += smask[tid + 16];
}
if (blockDim.x >= 16) {
sdata[tid] += sdata[tid + 8];
smask[tid] += smask[tid + 8];
}
if (blockDim.x >= 8) {
sdata[tid] += sdata[tid + 4];
smask[tid] += smask[tid + 4];
}
if (blockDim.x >= 4) {
sdata[tid] += sdata[tid + 2];
smask[tid] += smask[tid + 2];
}
if (blockDim.x >= 2) {
sdata[tid] += sdata[tid + 1];
smask[tid] += smask[tid + 1];
}
}
// write result for this block to global mem
if (tid == 0) {
g_odata[blockIdx.x] = sdata[0];
g_omask[blockIdx.x] = smask[0];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void reduce6(const float* g_idata, float* g_odata, float* g_omask, unsigned int n) {
extern __shared__ float sharedData[];
float* sdata = &sharedData[0];
float* smask = &sharedData[blockDim.x];
// perform first level of reduction,
// reading from global memory, writing to shared memory
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * blockDim.x * 2 + threadIdx.x;
unsigned int gridSize = blockDim.x * 2 * gridDim.x;
sdata[tid] = 0;
smask[tid] = 0;
// we reduce multiple elements per thread. The number is determined by the
// number of active thread blocks (via gridSize). More blocks will result
// in a larger gridSize and therefore fewer elements per thread
while (i < n) {
sdata[tid] += g_idata[i];
smask[tid] += (g_idata[i] > 0 ? 1 : 0);
if (i + blockDim.x < n) {
sdata[tid] += g_idata[i + blockDim.x];
smask[tid] += (g_idata[i + blockDim.x] > 0 ? 1 : 0);
}
i += gridSize;
}
__syncthreads();
// do reduction in shared mem
if (blockDim.x >= 512) {
if (tid < 256) {
sdata[tid] += sdata[tid + 256];
smask[tid] += smask[tid + 256];
}
__syncthreads();
}
if (blockDim.x >= 256) {
if (tid < 128) {
sdata[tid] += sdata[tid + 128];
smask[tid] += smask[tid + 128];
}
__syncthreads();
}
if (blockDim.x >= 128) {
if (tid < 64) {
sdata[tid] += sdata[tid + 64];
smask[tid] += smask[tid + 64];
}
__syncthreads();
}
if (tid < 32) {
if (blockDim.x >= 64) {
sdata[tid] += sdata[tid + 32];
smask[tid] += smask[tid + 32];
}
if (blockDim.x >= 32) {
sdata[tid] += sdata[tid + 16];
smask[tid] += smask[tid + 16];
}
if (blockDim.x >= 16) {
sdata[tid] += sdata[tid + 8];
smask[tid] += smask[tid + 8];
}
if (blockDim.x >= 8) {
sdata[tid] += sdata[tid + 4];
smask[tid] += smask[tid + 4];
}
if (blockDim.x >= 4) {
sdata[tid] += sdata[tid + 2];
smask[tid] += smask[tid + 2];
}
if (blockDim.x >= 2) {
sdata[tid] += sdata[tid + 1];
smask[tid] += smask[tid + 1];
}
}
// write result for this block to global mem
if (tid == 0) {
g_odata[blockIdx.x] = sdata[0];
g_omask[blockIdx.x] = smask[0];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void reduce6(const float* g_idata, float* g_odata, float* g_omask, unsigned int n) {
extern __shared__ float sharedData[];
float* sdata = &sharedData[0];
float* smask = &sharedData[blockDim.x];
// perform first level of reduction,
// reading from global memory, writing to shared memory
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * blockDim.x * 2 + threadIdx.x;
unsigned int gridSize = blockDim.x * 2 * gridDim.x;
sdata[tid] = 0;
smask[tid] = 0;
// we reduce multiple elements per thread. The number is determined by the
// number of active thread blocks (via gridSize). More blocks will result
// in a larger gridSize and therefore fewer elements per thread
while (i < n) {
sdata[tid] += g_idata[i];
smask[tid] += (g_idata[i] > 0 ? 1 : 0);
if (i + blockDim.x < n) {
sdata[tid] += g_idata[i + blockDim.x];
smask[tid] += (g_idata[i + blockDim.x] > 0 ? 1 : 0);
}
i += gridSize;
}
__syncthreads();
// do reduction in shared mem
if (blockDim.x >= 512) {
if (tid < 256) {
sdata[tid] += sdata[tid + 256];
smask[tid] += smask[tid + 256];
}
__syncthreads();
}
if (blockDim.x >= 256) {
if (tid < 128) {
sdata[tid] += sdata[tid + 128];
smask[tid] += smask[tid + 128];
}
__syncthreads();
}
if (blockDim.x >= 128) {
if (tid < 64) {
sdata[tid] += sdata[tid + 64];
smask[tid] += smask[tid + 64];
}
__syncthreads();
}
if (tid < 32) {
if (blockDim.x >= 64) {
sdata[tid] += sdata[tid + 32];
smask[tid] += smask[tid + 32];
}
if (blockDim.x >= 32) {
sdata[tid] += sdata[tid + 16];
smask[tid] += smask[tid + 16];
}
if (blockDim.x >= 16) {
sdata[tid] += sdata[tid + 8];
smask[tid] += smask[tid + 8];
}
if (blockDim.x >= 8) {
sdata[tid] += sdata[tid + 4];
smask[tid] += smask[tid + 4];
}
if (blockDim.x >= 4) {
sdata[tid] += sdata[tid + 2];
smask[tid] += smask[tid + 2];
}
if (blockDim.x >= 2) {
sdata[tid] += sdata[tid + 1];
smask[tid] += smask[tid + 1];
}
}
// write result for this block to global mem
if (tid == 0) {
g_odata[blockIdx.x] = sdata[0];
g_omask[blockIdx.x] = smask[0];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7reduce6PKfPfS1_j
.globl _Z7reduce6PKfPfS1_j
.p2align 8
.type _Z7reduce6PKfPfS1_j,@function
_Z7reduce6PKfPfS1_j:
s_clause 0x1
s_load_b32 s7, s[0:1], 0x2c
s_load_b32 s8, s[0:1], 0x18
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 2, v0
s_lshl_b32 s12, s15, 1
s_mov_b32 s2, s15
s_mov_b32 s10, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v4, 0, v1
s_mov_b32 s11, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s7, 0xffff
s_lshl_b32 s3, s6, 2
s_mul_i32 s9, s12, s6
s_add_i32 s3, s3, 0
v_add_nc_u32_e32 v5, s9, v0
v_add_nc_u32_e32 v3, s3, v1
ds_store_b32 v4, v2
ds_store_b32 v3, v2
v_cmpx_gt_u32_e64 s8, v5
s_cbranch_execz .LBB0_5
s_load_b32 s13, s[4:5], 0x0
s_load_b64 s[4:5], s[0:1], 0x0
v_mov_b32_e32 v5, v0
s_add_i32 s14, s12, 1
s_waitcnt lgkmcnt(0)
s_mul_i32 s13, s13, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b32 s12, s13, 1
s_mul_i32 s13, s14, s6
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s14
v_add_nc_u32_e32 v5, s12, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, s9, v5
v_cmp_le_u32_e32 vcc_lo, s8, v1
s_or_b32 s10, vcc_lo, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execz .LBB0_5
.LBB0_3:
v_add_nc_u32_e32 v1, s9, v5
s_mov_b32 s14, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[1:2]
v_add_co_u32 v6, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_b32 v1, v[6:7], off
ds_load_b32 v6, v4
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v6, v1, v6
v_cmp_lt_f32_e32 vcc_lo, 0, v1
v_add_nc_u32_e32 v1, s13, v5
ds_store_b32 v4, v6
ds_load_b32 v6, v3
v_cndmask_b32_e64 v7, 0, 1.0, vcc_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v6, v6, v7
ds_store_b32 v3, v6
v_cmpx_gt_u32_e64 s8, v1
s_cbranch_execz .LBB0_2
v_lshlrev_b64 v[6:7], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_b32 v1, v[6:7], off
ds_load_b32 v6, v4
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v6, v1, v6
v_cmp_lt_f32_e32 vcc_lo, 0, v1
ds_store_b32 v4, v6
ds_load_b32 v6, v3
v_cndmask_b32_e64 v1, 0, 1.0, vcc_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v1, v6, v1
ds_store_b32 v3, v1
s_branch .LBB0_2
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s11
v_cmp_gt_u16_e64 s4, 0x200, s7
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 vcc_lo, exec_lo, s4
s_cbranch_vccnz .LBB0_9
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e32 0x100, v0
s_cbranch_execz .LBB0_8
v_lshl_or_b32 v1, v0, 2, 0x400
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v2, 0, v1
v_add_nc_u32_e32 v1, s3, v1
ds_load_b32 v2, v2
ds_load_b32 v5, v4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v5
ds_store_b32 v4, v2
ds_load_b32 v1, v1
ds_load_b32 v2, v3
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v1, v1, v2
ds_store_b32 v3, v1
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_9:
v_cmp_gt_u16_e64 s4, 0x100, s7
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s4
s_cbranch_vccnz .LBB0_13
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e32 0x80, v0
s_cbranch_execz .LBB0_12
v_lshl_or_b32 v1, v0, 2, 0x200
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v2, 0, v1
v_add_nc_u32_e32 v1, s3, v1
ds_load_b32 v2, v2
ds_load_b32 v5, v4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v5
ds_store_b32 v4, v2
ds_load_b32 v1, v1
ds_load_b32 v2, v3
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v1, v1, v2
ds_store_b32 v3, v1
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_13:
v_cmp_gt_u16_e64 s4, 0x80, s7
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s4
s_cbranch_vccnz .LBB0_17
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e32 64, v0
s_cbranch_execz .LBB0_16
v_lshl_or_b32 v1, v0, 2, 0x100
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v2, 0, v1
v_add_nc_u32_e32 v1, s3, v1
ds_load_b32 v2, v2
ds_load_b32 v5, v4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v5
ds_store_b32 v4, v2
ds_load_b32 v1, v1
ds_load_b32 v2, v3
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v1, v1, v2
ds_store_b32 v3, v1
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_17:
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB0_27
v_cmp_lt_u16_e64 s5, s7, 64
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s5
s_and_b32 s5, 0xffff, s7
s_cbranch_vccnz .LBB0_20
v_lshl_or_b32 v1, v0, 2, 0x80
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v2, 0, v1
v_add_nc_u32_e32 v1, s3, v1
ds_load_b32 v2, v2
ds_load_b32 v5, v4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v5
ds_store_b32 v4, v2
ds_load_b32 v1, v1
ds_load_b32 v2, v3
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v1, v1, v2
ds_store_b32 v3, v1
.LBB0_20:
s_and_b32 s8, 0xffff, s7
s_cmp_lt_u32 s5, 32
s_cbranch_scc1 .LBB0_22
v_lshl_add_u32 v1, v0, 2, 64
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v2, 0, v1
v_add_nc_u32_e32 v1, s3, v1
ds_load_b32 v2, v2
ds_load_b32 v5, v4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v5
ds_store_b32 v4, v2
ds_load_b32 v1, v1
ds_load_b32 v2, v3
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v1, v1, v2
ds_store_b32 v3, v1
.LBB0_22:
s_and_b32 s5, 0xffff, s7
s_cmp_lt_u32 s8, 16
s_cbranch_scc0 .LBB0_30
s_cmp_lt_u32 s5, 8
s_cbranch_scc0 .LBB0_31
.LBB0_24:
s_cmp_lt_u32 s5, 4
s_cbranch_scc0 .LBB0_32
.LBB0_25:
s_cmp_lt_u32 s6, 2
s_cbranch_scc1 .LBB0_27
.LBB0_26:
v_lshl_add_u32 v1, v0, 2, 4
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v2, 0, v1
v_add_nc_u32_e32 v1, s3, v1
ds_load_b32 v2, v2
ds_load_b32 v5, v4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v5
ds_store_b32 v4, v2
ds_load_b32 v1, v1
ds_load_b32 v2, v3
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v1, v1, v2
ds_store_b32 v3, v1
.LBB0_27:
s_or_b32 exec_lo, exec_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_29
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s3
s_load_b128 s[4:7], s[0:1], 0x8
s_mov_b32 s3, 0
v_mov_b32_e32 v2, 0
ds_load_b32 v0, v0
ds_load_b32 v1, v1
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s4, s0
s_addc_u32 s3, s5, s1
s_add_u32 s0, s6, s0
s_addc_u32 s1, s7, s1
s_clause 0x1
global_store_b32 v2, v0, s[2:3]
global_store_b32 v2, v1, s[0:1]
.LBB0_29:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.LBB0_30:
v_lshl_add_u32 v1, v0, 2, 32
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v2, 0, v1
v_add_nc_u32_e32 v1, s3, v1
ds_load_b32 v2, v2
ds_load_b32 v5, v4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v5
ds_store_b32 v4, v2
ds_load_b32 v1, v1
ds_load_b32 v2, v3
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v1, v1, v2
ds_store_b32 v3, v1
s_cmp_lt_u32 s5, 8
s_cbranch_scc1 .LBB0_24
.LBB0_31:
v_lshl_add_u32 v1, v0, 2, 16
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v2, 0, v1
v_add_nc_u32_e32 v1, s3, v1
ds_load_b32 v2, v2
ds_load_b32 v5, v4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v5
ds_store_b32 v4, v2
ds_load_b32 v1, v1
ds_load_b32 v2, v3
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v1, v1, v2
ds_store_b32 v3, v1
s_cmp_lt_u32 s5, 4
s_cbranch_scc1 .LBB0_25
.LBB0_32:
v_lshl_add_u32 v1, v0, 2, 8
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v2, 0, v1
v_add_nc_u32_e32 v1, s3, v1
ds_load_b32 v2, v2
ds_load_b32 v5, v4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v5
ds_store_b32 v4, v2
ds_load_b32 v1, v1
ds_load_b32 v2, v3
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v1, v1, v2
ds_store_b32 v3, v1
s_cmp_lt_u32 s6, 2
s_cbranch_scc0 .LBB0_26
s_branch .LBB0_27
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7reduce6PKfPfS1_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7reduce6PKfPfS1_j, .Lfunc_end0-_Z7reduce6PKfPfS1_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
- .offset: 152
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7reduce6PKfPfS1_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7reduce6PKfPfS1_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void reduce6(const float* g_idata, float* g_odata, float* g_omask, unsigned int n) {
extern __shared__ float sharedData[];
float* sdata = &sharedData[0];
float* smask = &sharedData[blockDim.x];
// perform first level of reduction,
// reading from global memory, writing to shared memory
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * blockDim.x * 2 + threadIdx.x;
unsigned int gridSize = blockDim.x * 2 * gridDim.x;
sdata[tid] = 0;
smask[tid] = 0;
// we reduce multiple elements per thread. The number is determined by the
// number of active thread blocks (via gridSize). More blocks will result
// in a larger gridSize and therefore fewer elements per thread
while (i < n) {
sdata[tid] += g_idata[i];
smask[tid] += (g_idata[i] > 0 ? 1 : 0);
if (i + blockDim.x < n) {
sdata[tid] += g_idata[i + blockDim.x];
smask[tid] += (g_idata[i + blockDim.x] > 0 ? 1 : 0);
}
i += gridSize;
}
__syncthreads();
// do reduction in shared mem
if (blockDim.x >= 512) {
if (tid < 256) {
sdata[tid] += sdata[tid + 256];
smask[tid] += smask[tid + 256];
}
__syncthreads();
}
if (blockDim.x >= 256) {
if (tid < 128) {
sdata[tid] += sdata[tid + 128];
smask[tid] += smask[tid + 128];
}
__syncthreads();
}
if (blockDim.x >= 128) {
if (tid < 64) {
sdata[tid] += sdata[tid + 64];
smask[tid] += smask[tid + 64];
}
__syncthreads();
}
if (tid < 32) {
if (blockDim.x >= 64) {
sdata[tid] += sdata[tid + 32];
smask[tid] += smask[tid + 32];
}
if (blockDim.x >= 32) {
sdata[tid] += sdata[tid + 16];
smask[tid] += smask[tid + 16];
}
if (blockDim.x >= 16) {
sdata[tid] += sdata[tid + 8];
smask[tid] += smask[tid + 8];
}
if (blockDim.x >= 8) {
sdata[tid] += sdata[tid + 4];
smask[tid] += smask[tid + 4];
}
if (blockDim.x >= 4) {
sdata[tid] += sdata[tid + 2];
smask[tid] += smask[tid + 2];
}
if (blockDim.x >= 2) {
sdata[tid] += sdata[tid + 1];
smask[tid] += smask[tid + 1];
}
}
// write result for this block to global mem
if (tid == 0) {
g_odata[blockIdx.x] = sdata[0];
g_omask[blockIdx.x] = smask[0];
}
} | .text
.file "reduce6.hip"
.globl _Z22__device_stub__reduce6PKfPfS1_j # -- Begin function _Z22__device_stub__reduce6PKfPfS1_j
.p2align 4, 0x90
.type _Z22__device_stub__reduce6PKfPfS1_j,@function
_Z22__device_stub__reduce6PKfPfS1_j: # @_Z22__device_stub__reduce6PKfPfS1_j
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7reduce6PKfPfS1_j, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__reduce6PKfPfS1_j, .Lfunc_end0-_Z22__device_stub__reduce6PKfPfS1_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7reduce6PKfPfS1_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7reduce6PKfPfS1_j,@object # @_Z7reduce6PKfPfS1_j
.section .rodata,"a",@progbits
.globl _Z7reduce6PKfPfS1_j
.p2align 3, 0x0
_Z7reduce6PKfPfS1_j:
.quad _Z22__device_stub__reduce6PKfPfS1_j
.size _Z7reduce6PKfPfS1_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7reduce6PKfPfS1_j"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__reduce6PKfPfS1_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7reduce6PKfPfS1_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7reduce6PKfPfS1_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0020*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ MOV R6, c[0x0][0x0] ; /* 0x0000000000067a02 */
/* 0x000fe20000000f00 */
/*0040*/ USHF.L.U32 UR4, UR4, 0x2, URZ ; /* 0x0000000204047899 */
/* 0x000fe2000800063f */
/*0050*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e620000002500 */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0070*/ SHF.L.U32 R6, R6, 0x1, RZ ; /* 0x0000000106067819 */
/* 0x000fe200000006ff */
/*0080*/ BSSY B0, 0x2c0 ; /* 0x0000023000007945 */
/* 0x000fe20003800000 */
/*0090*/ SHF.L.U32 R2, R3, 0x2, RZ ; /* 0x0000000203027819 */
/* 0x001fe200000006ff */
/*00a0*/ STS [R3.X4], RZ ; /* 0x000000ff03007388 */
/* 0x0001e40000004800 */
/*00b0*/ IMAD R4, R6, R0, R3 ; /* 0x0000000006047224 */
/* 0x002fc400078e0203 */
/*00c0*/ STS [R2+UR4], RZ ; /* 0x000000ff02007988 */
/* 0x0001e60008000804 */
/*00d0*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fda0003f06070 */
/*00e0*/ @P0 BRA 0x2b0 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*00f0*/ MOV R7, R4 ; /* 0x0000000400077202 */
/* 0x001fe40000000f00 */
/*0100*/ HFMA2.MMA R12, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0c7435 */
/* 0x000fe200000001ff */
/*0110*/ LDS R8, [R3.X4] ; /* 0x0000000003087984 */
/* 0x001e320000004800 */
/*0120*/ IMAD.WIDE.U32 R4, R7, R12, c[0x0][0x160] ; /* 0x0000580007047625 */
/* 0x000fcc00078e000c */
/*0130*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000e22000c1e1900 */
/*0140*/ IADD3 R11, R7, c[0x0][0x0], RZ ; /* 0x00000000070b7a10 */
/* 0x000fe20007ffe0ff */
/*0150*/ IMAD R7, R6, c[0x0][0xc], R7 ; /* 0x0000030006077a24 */
/* 0x000fe200078e0207 */
/*0160*/ BSSY B1, 0x2a0 ; /* 0x0000013000017945 */
/* 0x000fe40003800000 */
/*0170*/ ISETP.GE.U32.AND P0, PT, R11, c[0x0][0x178], PT ; /* 0x00005e000b007a0c */
/* 0x000fe40003f06070 */
/*0180*/ ISETP.GE.U32.AND P1, PT, R7, c[0x0][0x178], PT ; /* 0x00005e0007007a0c */
/* 0x000fe20003f26070 */
/*0190*/ FADD R8, R8, R5 ; /* 0x0000000508087221 */
/* 0x001fe20000000000 */
/*01a0*/ FSET.BF.GT.AND R9, R5, RZ, PT ; /* 0x000000ff0509720a */
/* 0x000fc80003804000 */
/*01b0*/ STS [R3.X4], R8 ; /* 0x0000000803007388 */
/* 0x000fe80000004800 */
/*01c0*/ LDS R10, [R2+UR4] ; /* 0x00000004020a7984 */
/* 0x000e240008000800 */
/*01d0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x001fca0000000000 */
/*01e0*/ STS [R2+UR4], R9 ; /* 0x0000000902007988 */
/* 0x0001e20008000804 */
/*01f0*/ @P0 BRA 0x290 ; /* 0x0000009000000947 */
/* 0x000fea0003800000 */
/*0200*/ IMAD.WIDE.U32 R4, R11, R12, c[0x0][0x160] ; /* 0x000058000b047625 */
/* 0x000fe200078e000c */
/*0210*/ LDS R8, [R3.X4] ; /* 0x0000000003087984 */
/* 0x000e6a0000004800 */
/*0220*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000e64000c1e1900 */
/*0230*/ FADD R8, R8, R5 ; /* 0x0000000508087221 */
/* 0x002fe20000000000 */
/*0240*/ FSET.BF.GT.AND R9, R5, RZ, PT ; /* 0x000000ff0509720a */
/* 0x001fc80003804000 */
/*0250*/ STS [R3.X4], R8 ; /* 0x0000000803007388 */
/* 0x000fe80000004800 */
/*0260*/ LDS R10, [R2+UR4] ; /* 0x00000004020a7984 */
/* 0x000e240008000800 */
/*0270*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x001fca0000000000 */
/*0280*/ STS [R2+UR4], R9 ; /* 0x0000000902007988 */
/* 0x0001e40008000804 */
/*0290*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*02a0*/ @!P1 BRA 0x100 ; /* 0xfffffe5000009947 */
/* 0x000fea000383ffff */
/*02b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*02c0*/ MOV R7, c[0x0][0x0] ; /* 0x0000000000077a02 */
/* 0x000fe20000000f00 */
/*02d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02e0*/ ISETP.GT.U32.AND P0, PT, R3, 0x1f, PT ; /* 0x0000001f0300780c */
/* 0x000fe40003f04070 */
/*02f0*/ ISETP.GE.U32.AND P1, PT, R7.reuse, 0x200, PT ; /* 0x000002000700780c */
/* 0x040fe40003f26070 */
/*0300*/ ISETP.GE.U32.AND P2, PT, R7.reuse, 0x100, PT ; /* 0x000001000700780c */
/* 0x040fe40003f46070 */
/*0310*/ ISETP.GE.U32.AND P3, PT, R7, 0x80, PT ; /* 0x000000800700780c */
/* 0x000fd20003f66070 */
/*0320*/ @!P1 BRA 0x3d0 ; /* 0x000000a000009947 */
/* 0x000fea0003800000 */
/*0330*/ ISETP.GT.U32.AND P1, PT, R3, 0xff, PT ; /* 0x000000ff0300780c */
/* 0x000fda0003f24070 */
/*0340*/ @!P1 LDS R4, [R3.X4] ; /* 0x0000000003049984 */
/* 0x000fe80000004800 */
/*0350*/ @!P1 LDS R5, [R3.X4+0x400] ; /* 0x0004000003059984 */
/* 0x000e240000004800 */
/*0360*/ @!P1 FADD R4, R4, R5 ; /* 0x0000000504049221 */
/* 0x001fca0000000000 */
/*0370*/ @!P1 STS [R3.X4], R4 ; /* 0x0000000403009388 */
/* 0x000fe80000004800 */
/*0380*/ @!P1 LDS R5, [R2+UR4] ; /* 0x0000000402059984 */
/* 0x000fe80008000800 */
/*0390*/ @!P1 LDS R6, [R2+UR4+0x400] ; /* 0x0004000402069984 */
/* 0x000e240008000800 */
/*03a0*/ @!P1 FADD R5, R5, R6 ; /* 0x0000000605059221 */
/* 0x001fca0000000000 */
/*03b0*/ @!P1 STS [R2+UR4], R5 ; /* 0x0000000502009988 */
/* 0x0001e80008000804 */
/*03c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03d0*/ @!P2 BRA 0x480 ; /* 0x000000a00000a947 */
/* 0x000fea0003800000 */
/*03e0*/ ISETP.GT.U32.AND P1, PT, R3, 0x7f, PT ; /* 0x0000007f0300780c */
/* 0x000fda0003f24070 */
/*03f0*/ @!P1 LDS R4, [R3.X4] ; /* 0x0000000003049984 */
/* 0x000fe80000004800 */
/*0400*/ @!P1 LDS R5, [R3.X4+0x200] ; /* 0x0002000003059984 */
/* 0x001e240000004800 */
/*0410*/ @!P1 FADD R4, R4, R5 ; /* 0x0000000504049221 */
/* 0x001fca0000000000 */
/*0420*/ @!P1 STS [R3.X4], R4 ; /* 0x0000000403009388 */
/* 0x000fe80000004800 */
/*0430*/ @!P1 LDS R5, [R2+UR4] ; /* 0x0000000402059984 */
/* 0x000fe80008000800 */
/*0440*/ @!P1 LDS R6, [R2+UR4+0x200] ; /* 0x0002000402069984 */
/* 0x000e240008000800 */
/*0450*/ @!P1 FADD R5, R5, R6 ; /* 0x0000000605059221 */
/* 0x001fca0000000000 */
/*0460*/ @!P1 STS [R2+UR4], R5 ; /* 0x0000000502009988 */
/* 0x0001e80008000804 */
/*0470*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0480*/ @!P3 BRA 0x530 ; /* 0x000000a00000b947 */
/* 0x000fea0003800000 */
/*0490*/ ISETP.GT.U32.AND P1, PT, R3, 0x3f, PT ; /* 0x0000003f0300780c */
/* 0x000fda0003f24070 */
/*04a0*/ @!P1 LDS R4, [R3.X4] ; /* 0x0000000003049984 */
/* 0x000fe80000004800 */
/*04b0*/ @!P1 LDS R5, [R3.X4+0x100] ; /* 0x0001000003059984 */
/* 0x001e240000004800 */
/*04c0*/ @!P1 FADD R4, R4, R5 ; /* 0x0000000504049221 */
/* 0x001fca0000000000 */
/*04d0*/ @!P1 STS [R3.X4], R4 ; /* 0x0000000403009388 */
/* 0x000fe80000004800 */
/*04e0*/ @!P1 LDS R5, [R2+UR4] ; /* 0x0000000402059984 */
/* 0x000fe80008000800 */
/*04f0*/ @!P1 LDS R6, [R2+UR4+0x100] ; /* 0x0001000402069984 */
/* 0x000e240008000800 */
/*0500*/ @!P1 FADD R5, R5, R6 ; /* 0x0000000605059221 */
/* 0x001fca0000000000 */
/*0510*/ @!P1 STS [R2+UR4], R5 ; /* 0x0000000502009988 */
/* 0x0001e80008000804 */
/*0520*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0530*/ BSSY B0, 0x920 ; /* 0x000003e000007945 */
/* 0x000fe20003800000 */
/*0540*/ @P0 BRA 0x910 ; /* 0x000003c000000947 */
/* 0x000fea0003800000 */
/*0550*/ ISETP.GE.U32.AND P0, PT, R7.reuse, 0x40, PT ; /* 0x000000400700780c */
/* 0x040fe40003f06070 */
/*0560*/ ISETP.GE.U32.AND P1, PT, R7.reuse, 0x20, PT ; /* 0x000000200700780c */
/* 0x040fe40003f26070 */
/*0570*/ ISETP.GE.U32.AND P2, PT, R7.reuse, 0x10, PT ; /* 0x000000100700780c */
/* 0x040fe40003f46070 */
/*0580*/ ISETP.GE.U32.AND P3, PT, R7, 0x8, PT ; /* 0x000000080700780c */
/* 0x000fc40003f66070 */
/*0590*/ ISETP.GE.U32.AND P4, PT, R7.reuse, 0x4, PT ; /* 0x000000040700780c */
/* 0x040fe40003f86070 */
/*05a0*/ ISETP.GE.U32.AND P5, PT, R7, 0x2, PT ; /* 0x000000020700780c */
/* 0x000fc60003fa6070 */
/*05b0*/ @!P0 BRA 0x640 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*05c0*/ LDS R4, [R3.X4] ; /* 0x0000000003047984 */
/* 0x000fe80000004800 */
/*05d0*/ LDS R5, [R3.X4+0x80] ; /* 0x0000800003057984 */
/* 0x001e240000004800 */
/*05e0*/ FADD R4, R4, R5 ; /* 0x0000000504047221 */
/* 0x001fca0000000000 */
/*05f0*/ STS [R3.X4], R4 ; /* 0x0000000403007388 */
/* 0x000fe80000004800 */
/*0600*/ LDS R5, [R2+UR4] ; /* 0x0000000402057984 */
/* 0x000fe80008000800 */
/*0610*/ LDS R6, [R2+UR4+0x80] ; /* 0x0000800402067984 */
/* 0x000e240008000800 */
/*0620*/ FADD R5, R5, R6 ; /* 0x0000000605057221 */
/* 0x001fca0000000000 */
/*0630*/ STS [R2+UR4], R5 ; /* 0x0000000502007988 */
/* 0x0001e40008000804 */
/*0640*/ @!P1 BRA 0x6d0 ; /* 0x0000008000009947 */
/* 0x000fea0003800000 */
/*0650*/ LDS R4, [R3.X4] ; /* 0x0000000003047984 */
/* 0x000fe80000004800 */
/*0660*/ LDS R5, [R3.X4+0x40] ; /* 0x0000400003057984 */
/* 0x001e240000004800 */
/*0670*/ FADD R4, R4, R5 ; /* 0x0000000504047221 */
/* 0x001fca0000000000 */
/*0680*/ STS [R3.X4], R4 ; /* 0x0000000403007388 */
/* 0x000fe80000004800 */
/*0690*/ LDS R5, [R2+UR4] ; /* 0x0000000402057984 */
/* 0x000fe80008000800 */
/*06a0*/ LDS R6, [R2+UR4+0x40] ; /* 0x0000400402067984 */
/* 0x000e240008000800 */
/*06b0*/ FADD R5, R5, R6 ; /* 0x0000000605057221 */
/* 0x001fca0000000000 */
/*06c0*/ STS [R2+UR4], R5 ; /* 0x0000000502007988 */
/* 0x0001e40008000804 */
/*06d0*/ @!P2 BRA 0x760 ; /* 0x000000800000a947 */
/* 0x000fea0003800000 */
/*06e0*/ LDS R4, [R3.X4] ; /* 0x0000000003047984 */
/* 0x000fe80000004800 */
/*06f0*/ LDS R5, [R3.X4+0x20] ; /* 0x0000200003057984 */
/* 0x001e240000004800 */
/*0700*/ FADD R4, R4, R5 ; /* 0x0000000504047221 */
/* 0x001fca0000000000 */
/*0710*/ STS [R3.X4], R4 ; /* 0x0000000403007388 */
/* 0x000fe80000004800 */
/*0720*/ LDS R5, [R2+UR4] ; /* 0x0000000402057984 */
/* 0x000fe80008000800 */
/*0730*/ LDS R6, [R2+UR4+0x20] ; /* 0x0000200402067984 */
/* 0x000e240008000800 */
/*0740*/ FADD R5, R5, R6 ; /* 0x0000000605057221 */
/* 0x001fca0000000000 */
/*0750*/ STS [R2+UR4], R5 ; /* 0x0000000502007988 */
/* 0x0001e40008000804 */
/*0760*/ @!P3 BRA 0x7f0 ; /* 0x000000800000b947 */
/* 0x000fea0003800000 */
/*0770*/ LDS R4, [R3.X4] ; /* 0x0000000003047984 */
/* 0x000fe80000004800 */
/*0780*/ LDS R5, [R3.X4+0x10] ; /* 0x0000100003057984 */
/* 0x001e240000004800 */
/*0790*/ FADD R4, R4, R5 ; /* 0x0000000504047221 */
/* 0x001fca0000000000 */
/*07a0*/ STS [R3.X4], R4 ; /* 0x0000000403007388 */
/* 0x000fe80000004800 */
/*07b0*/ LDS R5, [R2+UR4] ; /* 0x0000000402057984 */
/* 0x000fe80008000800 */
/*07c0*/ LDS R6, [R2+UR4+0x10] ; /* 0x0000100402067984 */
/* 0x000e240008000800 */
/*07d0*/ FADD R5, R5, R6 ; /* 0x0000000605057221 */
/* 0x001fca0000000000 */
/*07e0*/ STS [R2+UR4], R5 ; /* 0x0000000502007988 */
/* 0x0001e40008000804 */
/*07f0*/ @!P4 BRA 0x880 ; /* 0x000000800000c947 */
/* 0x000fea0003800000 */
/*0800*/ LDS R4, [R3.X4] ; /* 0x0000000003047984 */
/* 0x000fe80000004800 */
/*0810*/ LDS R5, [R3.X4+0x8] ; /* 0x0000080003057984 */
/* 0x001e240000004800 */
/*0820*/ FADD R4, R4, R5 ; /* 0x0000000504047221 */
/* 0x001fca0000000000 */
/*0830*/ STS [R3.X4], R4 ; /* 0x0000000403007388 */
/* 0x000fe80000004800 */
/*0840*/ LDS R5, [R2+UR4] ; /* 0x0000000402057984 */
/* 0x000fe80008000800 */
/*0850*/ LDS R6, [R2+UR4+0x8] ; /* 0x0000080402067984 */
/* 0x000e240008000800 */
/*0860*/ FADD R5, R5, R6 ; /* 0x0000000605057221 */
/* 0x001fca0000000000 */
/*0870*/ STS [R2+UR4], R5 ; /* 0x0000000502007988 */
/* 0x0001e40008000804 */
/*0880*/ @!P5 BRA 0x910 ; /* 0x000000800000d947 */
/* 0x000fea0003800000 */
/*0890*/ LDS R4, [R3.X4] ; /* 0x0000000003047984 */
/* 0x000fe80000004800 */
/*08a0*/ LDS R5, [R3.X4+0x4] ; /* 0x0000040003057984 */
/* 0x001e240000004800 */
/*08b0*/ FADD R4, R4, R5 ; /* 0x0000000504047221 */
/* 0x001fca0000000000 */
/*08c0*/ STS [R3.X4], R4 ; /* 0x0000000403007388 */
/* 0x000fe80000004800 */
/*08d0*/ LDS R5, [R2+UR4] ; /* 0x0000000402057984 */
/* 0x000fe80008000800 */
/*08e0*/ LDS R6, [R2+UR4+0x4] ; /* 0x0000040402067984 */
/* 0x000e240008000800 */
/*08f0*/ FADD R5, R5, R6 ; /* 0x0000000605057221 */
/* 0x001fca0000000000 */
/*0900*/ STS [R2+UR4], R5 ; /* 0x0000000502007988 */
/* 0x0001e40008000804 */
/*0910*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0920*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*0930*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0940*/ LDS R7, [RZ] ; /* 0x00000000ff077984 */
/* 0x000e620000000800 */
/*0950*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x001fc600000001ff */
/*0960*/ LDS R9, [UR4] ; /* 0x00000004ff097984 */
/* 0x000e2e0008000800 */
/*0970*/ IMAD.WIDE.U32 R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0005 */
/*0980*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fe200078e0005 */
/*0990*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x002fe8000c101906 */
/*09a0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x001fe2000c101906 */
/*09b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*09c0*/ BRA 0x9c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7reduce6PKfPfS1_j
.globl _Z7reduce6PKfPfS1_j
.p2align 8
.type _Z7reduce6PKfPfS1_j,@function
_Z7reduce6PKfPfS1_j:
s_clause 0x1
s_load_b32 s7, s[0:1], 0x2c
s_load_b32 s8, s[0:1], 0x18
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 2, v0
s_lshl_b32 s12, s15, 1
s_mov_b32 s2, s15
s_mov_b32 s10, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v4, 0, v1
s_mov_b32 s11, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s7, 0xffff
s_lshl_b32 s3, s6, 2
s_mul_i32 s9, s12, s6
s_add_i32 s3, s3, 0
v_add_nc_u32_e32 v5, s9, v0
v_add_nc_u32_e32 v3, s3, v1
ds_store_b32 v4, v2
ds_store_b32 v3, v2
v_cmpx_gt_u32_e64 s8, v5
s_cbranch_execz .LBB0_5
s_load_b32 s13, s[4:5], 0x0
s_load_b64 s[4:5], s[0:1], 0x0
v_mov_b32_e32 v5, v0
s_add_i32 s14, s12, 1
s_waitcnt lgkmcnt(0)
s_mul_i32 s13, s13, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b32 s12, s13, 1
s_mul_i32 s13, s14, s6
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s14
v_add_nc_u32_e32 v5, s12, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, s9, v5
v_cmp_le_u32_e32 vcc_lo, s8, v1
s_or_b32 s10, vcc_lo, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execz .LBB0_5
.LBB0_3:
v_add_nc_u32_e32 v1, s9, v5
s_mov_b32 s14, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[1:2]
v_add_co_u32 v6, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_b32 v1, v[6:7], off
ds_load_b32 v6, v4
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v6, v1, v6
v_cmp_lt_f32_e32 vcc_lo, 0, v1
v_add_nc_u32_e32 v1, s13, v5
ds_store_b32 v4, v6
ds_load_b32 v6, v3
v_cndmask_b32_e64 v7, 0, 1.0, vcc_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v6, v6, v7
ds_store_b32 v3, v6
v_cmpx_gt_u32_e64 s8, v1
s_cbranch_execz .LBB0_2
v_lshlrev_b64 v[6:7], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_b32 v1, v[6:7], off
ds_load_b32 v6, v4
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v6, v1, v6
v_cmp_lt_f32_e32 vcc_lo, 0, v1
ds_store_b32 v4, v6
ds_load_b32 v6, v3
v_cndmask_b32_e64 v1, 0, 1.0, vcc_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v1, v6, v1
ds_store_b32 v3, v1
s_branch .LBB0_2
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s11
v_cmp_gt_u16_e64 s4, 0x200, s7
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 vcc_lo, exec_lo, s4
s_cbranch_vccnz .LBB0_9
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e32 0x100, v0
s_cbranch_execz .LBB0_8
v_lshl_or_b32 v1, v0, 2, 0x400
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v2, 0, v1
v_add_nc_u32_e32 v1, s3, v1
ds_load_b32 v2, v2
ds_load_b32 v5, v4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v5
ds_store_b32 v4, v2
ds_load_b32 v1, v1
ds_load_b32 v2, v3
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v1, v1, v2
ds_store_b32 v3, v1
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_9:
v_cmp_gt_u16_e64 s4, 0x100, s7
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s4
s_cbranch_vccnz .LBB0_13
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e32 0x80, v0
s_cbranch_execz .LBB0_12
v_lshl_or_b32 v1, v0, 2, 0x200
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v2, 0, v1
v_add_nc_u32_e32 v1, s3, v1
ds_load_b32 v2, v2
ds_load_b32 v5, v4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v5
ds_store_b32 v4, v2
ds_load_b32 v1, v1
ds_load_b32 v2, v3
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v1, v1, v2
ds_store_b32 v3, v1
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_13:
v_cmp_gt_u16_e64 s4, 0x80, s7
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s4
s_cbranch_vccnz .LBB0_17
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e32 64, v0
s_cbranch_execz .LBB0_16
v_lshl_or_b32 v1, v0, 2, 0x100
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v2, 0, v1
v_add_nc_u32_e32 v1, s3, v1
ds_load_b32 v2, v2
ds_load_b32 v5, v4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v5
ds_store_b32 v4, v2
ds_load_b32 v1, v1
ds_load_b32 v2, v3
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v1, v1, v2
ds_store_b32 v3, v1
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_17:
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB0_27
v_cmp_lt_u16_e64 s5, s7, 64
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s5
s_and_b32 s5, 0xffff, s7
s_cbranch_vccnz .LBB0_20
v_lshl_or_b32 v1, v0, 2, 0x80
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v2, 0, v1
v_add_nc_u32_e32 v1, s3, v1
ds_load_b32 v2, v2
ds_load_b32 v5, v4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v5
ds_store_b32 v4, v2
ds_load_b32 v1, v1
ds_load_b32 v2, v3
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v1, v1, v2
ds_store_b32 v3, v1
.LBB0_20:
s_and_b32 s8, 0xffff, s7
s_cmp_lt_u32 s5, 32
s_cbranch_scc1 .LBB0_22
v_lshl_add_u32 v1, v0, 2, 64
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v2, 0, v1
v_add_nc_u32_e32 v1, s3, v1
ds_load_b32 v2, v2
ds_load_b32 v5, v4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v5
ds_store_b32 v4, v2
ds_load_b32 v1, v1
ds_load_b32 v2, v3
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v1, v1, v2
ds_store_b32 v3, v1
.LBB0_22:
s_and_b32 s5, 0xffff, s7
s_cmp_lt_u32 s8, 16
s_cbranch_scc0 .LBB0_30
s_cmp_lt_u32 s5, 8
s_cbranch_scc0 .LBB0_31
.LBB0_24:
s_cmp_lt_u32 s5, 4
s_cbranch_scc0 .LBB0_32
.LBB0_25:
s_cmp_lt_u32 s6, 2
s_cbranch_scc1 .LBB0_27
.LBB0_26:
v_lshl_add_u32 v1, v0, 2, 4
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v2, 0, v1
v_add_nc_u32_e32 v1, s3, v1
ds_load_b32 v2, v2
ds_load_b32 v5, v4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v5
ds_store_b32 v4, v2
ds_load_b32 v1, v1
ds_load_b32 v2, v3
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v1, v1, v2
ds_store_b32 v3, v1
.LBB0_27:
s_or_b32 exec_lo, exec_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_29
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s3
s_load_b128 s[4:7], s[0:1], 0x8
s_mov_b32 s3, 0
v_mov_b32_e32 v2, 0
ds_load_b32 v0, v0
ds_load_b32 v1, v1
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s4, s0
s_addc_u32 s3, s5, s1
s_add_u32 s0, s6, s0
s_addc_u32 s1, s7, s1
s_clause 0x1
global_store_b32 v2, v0, s[2:3]
global_store_b32 v2, v1, s[0:1]
.LBB0_29:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.LBB0_30:
v_lshl_add_u32 v1, v0, 2, 32
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v2, 0, v1
v_add_nc_u32_e32 v1, s3, v1
ds_load_b32 v2, v2
ds_load_b32 v5, v4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v5
ds_store_b32 v4, v2
ds_load_b32 v1, v1
ds_load_b32 v2, v3
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v1, v1, v2
ds_store_b32 v3, v1
s_cmp_lt_u32 s5, 8
s_cbranch_scc1 .LBB0_24
.LBB0_31:
v_lshl_add_u32 v1, v0, 2, 16
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v2, 0, v1
v_add_nc_u32_e32 v1, s3, v1
ds_load_b32 v2, v2
ds_load_b32 v5, v4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v5
ds_store_b32 v4, v2
ds_load_b32 v1, v1
ds_load_b32 v2, v3
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v1, v1, v2
ds_store_b32 v3, v1
s_cmp_lt_u32 s5, 4
s_cbranch_scc1 .LBB0_25
.LBB0_32:
v_lshl_add_u32 v1, v0, 2, 8
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v2, 0, v1
v_add_nc_u32_e32 v1, s3, v1
ds_load_b32 v2, v2
ds_load_b32 v5, v4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v5
ds_store_b32 v4, v2
ds_load_b32 v1, v1
ds_load_b32 v2, v3
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v1, v1, v2
ds_store_b32 v3, v1
s_cmp_lt_u32 s6, 2
s_cbranch_scc0 .LBB0_26
s_branch .LBB0_27
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7reduce6PKfPfS1_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7reduce6PKfPfS1_j, .Lfunc_end0-_Z7reduce6PKfPfS1_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
- .offset: 152
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7reduce6PKfPfS1_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7reduce6PKfPfS1_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00095adb_00000000-6_reduce6.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z7reduce6PKfPfS1_jPKfPfS1_j
.type _Z33__device_stub__Z7reduce6PKfPfS1_jPKfPfS1_j, @function
_Z33__device_stub__Z7reduce6PKfPfS1_jPKfPfS1_j:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7reduce6PKfPfS1_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z7reduce6PKfPfS1_jPKfPfS1_j, .-_Z33__device_stub__Z7reduce6PKfPfS1_jPKfPfS1_j
.globl _Z7reduce6PKfPfS1_j
.type _Z7reduce6PKfPfS1_j, @function
_Z7reduce6PKfPfS1_j:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z7reduce6PKfPfS1_jPKfPfS1_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7reduce6PKfPfS1_j, .-_Z7reduce6PKfPfS1_j
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7reduce6PKfPfS1_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7reduce6PKfPfS1_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "reduce6.hip"
.globl _Z22__device_stub__reduce6PKfPfS1_j # -- Begin function _Z22__device_stub__reduce6PKfPfS1_j
.p2align 4, 0x90
.type _Z22__device_stub__reduce6PKfPfS1_j,@function
_Z22__device_stub__reduce6PKfPfS1_j: # @_Z22__device_stub__reduce6PKfPfS1_j
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7reduce6PKfPfS1_j, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__reduce6PKfPfS1_j, .Lfunc_end0-_Z22__device_stub__reduce6PKfPfS1_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7reduce6PKfPfS1_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7reduce6PKfPfS1_j,@object # @_Z7reduce6PKfPfS1_j
.section .rodata,"a",@progbits
.globl _Z7reduce6PKfPfS1_j
.p2align 3, 0x0
_Z7reduce6PKfPfS1_j:
.quad _Z22__device_stub__reduce6PKfPfS1_j
.size _Z7reduce6PKfPfS1_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7reduce6PKfPfS1_j"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__reduce6PKfPfS1_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7reduce6PKfPfS1_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void kArgMaxColumnwise(float* mat, float* target, unsigned int width, unsigned int height) {
__shared__ float max_vals[32];
__shared__ unsigned int max_args[32];
float cur_max = -2e38;
unsigned int cur_arg = 0;
float val = 0;
for (unsigned int i = threadIdx.x; i < height; i += 32) {
val = mat[i * width + blockIdx.x];
if (val > cur_max) {
cur_max = val;
cur_arg = i;
}
}
max_vals[threadIdx.x] = cur_max;
max_args[threadIdx.x] = cur_arg;
__syncthreads();
if (threadIdx.x == 0) {
cur_max = -2e38;
cur_arg = 0;
for (unsigned int i = 0; i < 32; i++)
if (max_vals[i] > cur_max) {
cur_max = max_vals[i];
cur_arg = max_args[i];
}
target[blockIdx.x] = cur_arg;
}
} | code for sm_80
Function : _Z17kArgMaxColumnwisePfS_jj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x5c0 ; /* 0x0000058000007945 */
/* 0x000fe20003800000 */
/*0040*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe400078e00ff */
/*0050*/ IMAD.MOV.U32 R7, RZ, RZ, -0xe98967 ; /* 0xff167699ff077424 */
/* 0x000fe200078e00ff */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x001fda0003f06070 */
/*0070*/ @P0 BRA 0x5b0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0080*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0090*/ ISETP.GE.U32.AND P3, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f66070 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fd800078e0000 */
/*00b0*/ @P3 IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff093424 */
/* 0x000fe400078e00ff */
/*00c0*/ @P3 IMAD R8, R2, c[0x0][0x170], R5 ; /* 0x00005c0002083a24 */
/* 0x001fc800078e0205 */
/*00d0*/ @P3 IMAD.WIDE.U32 R8, R8, R9, c[0x0][0x160] ; /* 0x0000580008083625 */
/* 0x000fcc00078e0009 */
/*00e0*/ @P3 LDG.E R8, [R8.64] ; /* 0x0000000408083981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD.MOV.U32 R7, RZ, RZ, -0xe98967 ; /* 0xff167699ff077424 */
/* 0x000fe200078e00ff */
/*0100*/ BSSY B1, 0x3c0 ; /* 0x000002b000017945 */
/* 0x000fe20003800000 */
/*0110*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fc600078e00ff */
/*0120*/ @P3 FSETP.GT.AND P2, PT, R8, R7, PT ; /* 0x000000070800320b */
/* 0x004fc80003f44000 */
/*0130*/ @P3 SEL R3, R2.reuse, R3, P2 ; /* 0x0000000302033207 */
/* 0x040fe40001000000 */
/*0140*/ @P3 IADD3 R2, R2, 0x20, RZ ; /* 0x0000002002023810 */
/* 0x000fe40007ffe0ff */
/*0150*/ @P3 FSEL R7, R8, R7, P2 ; /* 0x0000000708073208 */
/* 0x000fe40001000000 */
/*0160*/ ISETP.GE.U32.AND P0, PT, R2.reuse, c[0x0][0x174], PT ; /* 0x00005d0002007a0c */
/* 0x040fe40003f06070 */
/*0170*/ IADD3 R4, -R2, c[0x0][0x174], RZ ; /* 0x00005d0002047a10 */
/* 0x000fc80007ffe1ff */
/*0180*/ ISETP.LE.U32.OR P1, PT, R4, 0x60, P0 ; /* 0x000000600400780c */
/* 0x000fe40000723470 */
/*0190*/ PLOP3.LUT P0, PT, P3, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60001f0e170 */
/*01a0*/ @P1 BRA 0x3b0 ; /* 0x0000020000001947 */
/* 0x000fea0003800000 */
/*01b0*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff0f7624 */
/* 0x000fe200078e00ff */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc80003f0e170 */
/*01d0*/ IADD3 R15, R15, -0x60, RZ ; /* 0xffffffa00f0f7810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; /* 0x00000004ff117424 */
/* 0x000fe200078e00ff */
/*01f0*/ IADD3 R4, R2.reuse, 0x20, RZ ; /* 0x0000002002047810 */
/* 0x040fe20007ffe0ff */
/*0200*/ IMAD R8, R2, c[0x0][0x170], R5 ; /* 0x00005c0002087a24 */
/* 0x000fc800078e0205 */
/*0210*/ IMAD.WIDE.U32 R8, R8, R17, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fc800078e0011 */
/*0220*/ IMAD R10, R4, c[0x0][0x170], R5 ; /* 0x00005c00040a7a24 */
/* 0x000fe400078e0205 */
/*0230*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea4000c1e1900 */
/*0240*/ IMAD.WIDE.U32 R10, R10, R17, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fcc00078e0011 */
/*0250*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ee2000c1e1900 */
/*0260*/ IADD3 R6, R2, 0x40, RZ ; /* 0x0000004002067810 */
/* 0x000fca0007ffe0ff */
/*0270*/ IMAD R12, R6, c[0x0][0x170], R5 ; /* 0x00005c00060c7a24 */
/* 0x000fc800078e0205 */
/*0280*/ IMAD.WIDE.U32 R12, R12, R17, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x000fcc00078e0011 */
/*0290*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f22000c1e1900 */
/*02a0*/ FSETP.GT.AND P1, PT, R8, R7, PT ; /* 0x000000070800720b */
/* 0x004fc80003f24000 */
/*02b0*/ FSEL R7, R8, R7, P1 ; /* 0x0000000708077208 */
/* 0x000fc80000800000 */
/*02c0*/ FSETP.GT.AND P2, PT, R10, R7, PT ; /* 0x000000070a00720b */
/* 0x008fda0003f44000 */
/*02d0*/ @!P2 SEL R4, R2.reuse, R3, P1 ; /* 0x000000030204a207 */
/* 0x040fe40000800000 */
/*02e0*/ IADD3 R3, R2, 0x60, RZ ; /* 0x0000006002037810 */
/* 0x000fca0007ffe0ff */
/*02f0*/ IMAD R8, R3, c[0x0][0x170], R5 ; /* 0x00005c0003087a24 */
/* 0x000fc800078e0205 */
/*0300*/ IMAD.WIDE.U32 R8, R8, R17, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fcc00078e0011 */
/*0310*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1900 */
/*0320*/ FSEL R7, R10, R7, P2 ; /* 0x000000070a077208 */
/* 0x000fe40001000000 */
/*0330*/ IADD3 R2, R2, 0x80, RZ ; /* 0x0000008002027810 */
/* 0x000fe40007ffe0ff */
/*0340*/ FSETP.GT.AND P1, PT, R12, R7, PT ; /* 0x000000070c00720b */
/* 0x010fe40003f24000 */
/*0350*/ ISETP.GE.U32.AND P3, PT, R2, R15, PT ; /* 0x0000000f0200720c */
/* 0x000fe40003f66070 */
/*0360*/ FSEL R7, R12, R7, P1 ; /* 0x000000070c077208 */
/* 0x000fc80000800000 */
/*0370*/ FSETP.GT.AND P2, PT, R8, R7, PT ; /* 0x000000070800720b */
/* 0x004fc80003f44000 */
/*0380*/ FSEL R7, R8, R7, P2 ; /* 0x0000000708077208 */
/* 0x000fd20001000000 */
/*0390*/ @!P2 SEL R3, R6, R4, P1 ; /* 0x000000040603a207 */
/* 0x000fe20000800000 */
/*03a0*/ @!P3 BRA 0x1e0 ; /* 0xfffffe300000b947 */
/* 0x000fea000383ffff */
/*03b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*03c0*/ ISETP.GE.U32.AND P1, PT, R2.reuse, c[0x0][0x174], PT ; /* 0x00005d0002007a0c */
/* 0x040fe20003f26070 */
/*03d0*/ BSSY B1, 0x520 ; /* 0x0000014000017945 */
/* 0x000fe20003800000 */
/*03e0*/ IADD3 R4, -R2, c[0x0][0x174], RZ ; /* 0x00005d0002047a10 */
/* 0x000fc80007ffe1ff */
/*03f0*/ ISETP.LE.U32.OR P1, PT, R4, 0x20, P1 ; /* 0x000000200400780c */
/* 0x000fda0000f23470 */
/*0400*/ @P1 BRA 0x510 ; /* 0x0000010000001947 */
/* 0x000fea0003800000 */
/*0410*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0420*/ IADD3 R4, R2.reuse, 0x20, RZ ; /* 0x0000002002047810 */
/* 0x040fe20007ffe0ff */
/*0430*/ IMAD R10, R2, c[0x0][0x170], R5 ; /* 0x00005c00020a7a24 */
/* 0x000fc800078e0205 */
/*0440*/ IMAD.WIDE.U32 R10, R10, R9, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fc800078e0009 */
/*0450*/ IMAD R8, R4, c[0x0][0x170], R5 ; /* 0x00005c0004087a24 */
/* 0x000fe400078e0205 */
/*0460*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea4000c1e1900 */
/*0470*/ IMAD.WIDE.U32 R8, R8, R9, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fcc00078e0009 */
/*0480*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee2000c1e1900 */
/*0490*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*04a0*/ FSETP.GT.AND P1, PT, R10, R7, PT ; /* 0x000000070a00720b */
/* 0x004fc80003f24000 */
/*04b0*/ FSEL R7, R10, R7, P1 ; /* 0x000000070a077208 */
/* 0x000fc80000800000 */
/*04c0*/ FSETP.GT.AND P2, PT, R8, R7, PT ; /* 0x000000070800720b */
/* 0x008fc80003f44000 */
/*04d0*/ FSEL R7, R8, R7, P2 ; /* 0x0000000708077208 */
/* 0x000fd20001000000 */
/*04e0*/ @!P2 SEL R4, R2.reuse, R3, P1 ; /* 0x000000030204a207 */
/* 0x040fe40000800000 */
/*04f0*/ IADD3 R2, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x000fc60007ffe0ff */
/*0500*/ IMAD.MOV.U32 R3, RZ, RZ, R4 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0004 */
/*0510*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0520*/ ISETP.LT.U32.OR P0, PT, R2, c[0x0][0x174], P0 ; /* 0x00005d0002007a0c */
/* 0x000fda0000701470 */
/*0530*/ @!P0 BRA 0x5b0 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*0540*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe400078e00ff */
/*0550*/ IMAD R5, R2, c[0x0][0x170], R5 ; /* 0x00005c0002057a24 */
/* 0x000fc800078e0205 */
/*0560*/ IMAD.WIDE.U32 R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fcc00078e0004 */
/*0570*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*0580*/ FSETP.GT.AND P0, PT, R4, R7, PT ; /* 0x000000070400720b */
/* 0x004fc80003f04000 */
/*0590*/ FSEL R7, R4, R7, P0 ; /* 0x0000000704077208 */
/* 0x000fe40000000000 */
/*05a0*/ SEL R3, R2, R3, P0 ; /* 0x0000000302037207 */
/* 0x000fe40000000000 */
/*05b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05c0*/ STS [R0.X4], R7 ; /* 0x0000000700007388 */
/* 0x0001e20000004800 */
/*05d0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc60003f05270 */
/*05e0*/ STS [R0.X4+0x80], R3 ; /* 0x0000800300007388 */
/* 0x0001e80000004800 */
/*05f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0600*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0610*/ LDS.128 R16, [RZ] ; /* 0x00000000ff107984 */
/* 0x001e220000000c00 */
/*0620*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc600078e00ff */
/*0630*/ LDS.128 R12, [0x10] ; /* 0x00001000ff0c7984 */
/* 0x000fe80000000c00 */
/*0640*/ LDS.128 R24, [0x80] ; /* 0x00008000ff187984 */
/* 0x000e680000000c00 */
/*0650*/ LDS.128 R8, [0x20] ; /* 0x00002000ff087984 */
/* 0x000fe80000000c00 */
/*0660*/ LDS.128 R4, [0x90] ; /* 0x00009000ff047984 */
/* 0x000ea80000000c00 */
/*0670*/ LDS.128 R20, [0x30] ; /* 0x00003000ff147984 */
/* 0x000fe80000000c00 */
/*0680*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000ee20000002500 */
/*0690*/ FMNMX R0, R16, -1.99999993605713849301e+38, !PT ; /* 0xff16769910007809 */
/* 0x001fc40007800000 */
/*06a0*/ FSETP.GT.AND P2, PT, R16, -1.99999993605713849301e+38, PT ; /* 0xff1676991000780b */
/* 0x000fe40003f44000 */
/*06b0*/ FSETP.GT.AND P6, PT, R17, R0, PT ; /* 0x000000001100720b */
/* 0x000fc80003fc4000 */
/*06c0*/ FSEL R17, R17, R0, P6 ; /* 0x0000000011117208 */
/* 0x000fe20003000000 */
/*06d0*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x008fc600078e0003 */
/*06e0*/ FSETP.GT.AND P0, PT, R18, R17, PT ; /* 0x000000111200720b */
/* 0x000fc80003f04000 */
/*06f0*/ FSEL R18, R18, R17, P0 ; /* 0x0000001112127208 */
/* 0x000fe40000000000 */
/*0700*/ @!P6 SEL R25, R24, RZ, P2 ; /* 0x000000ff1819e207 */
/* 0x002fe40001000000 */
/*0710*/ FSETP.GT.AND P4, PT, R19, R18, PT ; /* 0x000000121300720b */
/* 0x000fc80003f84000 */
/*0720*/ FSEL R19, R19, R18, P4 ; /* 0x0000001213137208 */
/* 0x000fc80002000000 */
/*0730*/ FSETP.GT.AND P1, PT, R12, R19, PT ; /* 0x000000130c00720b */
/* 0x000fc80003f24000 */
/*0740*/ FSEL R12, R12, R19, P1 ; /* 0x000000130c0c7208 */
/* 0x000fe40000800000 */
/*0750*/ @!P4 SEL R27, R26, R25, P0 ; /* 0x000000191a1bc207 */
/* 0x000fe20000000000 */
/*0760*/ LDS.128 R16, [0xa0] ; /* 0x0000a000ff107984 */
/* 0x000e220000000c00 */
/*0770*/ FSETP.GT.AND P5, PT, R13, R12, PT ; /* 0x0000000c0d00720b */
/* 0x000fc80003fa4000 */
/*0780*/ FSEL R13, R13, R12, P5 ; /* 0x0000000c0d0d7208 */
/* 0x000fc80002800000 */
/*0790*/ FSETP.GT.AND P3, PT, R14, R13, PT ; /* 0x0000000d0e00720b */
/* 0x000fc80003f64000 */
/*07a0*/ FSEL R14, R14, R13, P3 ; /* 0x0000000d0e0e7208 */
/* 0x000fe40001800000 */
/*07b0*/ @!P5 SEL R5, R4, R27, P1 ; /* 0x0000001b0405d207 */
/* 0x004fe40000800000 */
/*07c0*/ FSETP.GT.AND P6, PT, R15, R14, PT ; /* 0x0000000e0f00720b */
/* 0x000fc80003fc4000 */
/*07d0*/ FSEL R15, R15, R14, P6 ; /* 0x0000000e0f0f7208 */
/* 0x000fc80003000000 */
/*07e0*/ FSETP.GT.AND P2, PT, R8, R15, PT ; /* 0x0000000f0800720b */
/* 0x000fc80003f44000 */
/*07f0*/ FSEL R8, R8, R15, P2 ; /* 0x0000000f08087208 */
/* 0x000fe40001000000 */
/*0800*/ LDS.128 R12, [0x40] ; /* 0x00004000ff0c7984 */
/* 0x000e620000000c00 */
/*0810*/ @!P6 SEL R7, R6, R5, P3 ; /* 0x000000050607e207 */
/* 0x000fe40001800000 */
/*0820*/ FSETP.GT.AND P4, PT, R9, R8, PT ; /* 0x000000080900720b */
/* 0x000fc80003f84000 */
/*0830*/ FSEL R9, R9, R8, P4 ; /* 0x0000000809097208 */
/* 0x000fc80002000000 */
/*0840*/ FSETP.GT.AND P0, PT, R10, R9, PT ; /* 0x000000090a00720b */
/* 0x000fc80003f04000 */
/*0850*/ FSEL R10, R10, R9, P0 ; /* 0x000000090a0a7208 */
/* 0x000fe40000000000 */
/*0860*/ @!P4 SEL R17, R16, R7, P2 ; /* 0x000000071011c207 */
/* 0x001fe40001000000 */
/*0870*/ FSETP.GT.AND P1, PT, R11.reuse, R10.reuse, PT ; /* 0x0000000a0b00720b */
/* 0x0c0fe20003f24000 */
/*0880*/ LDS.128 R4, [0x50] ; /* 0x00005000ff047984 */
/* 0x000fe60000000c00 */
/*0890*/ FSEL R11, R11, R10, P1 ; /* 0x0000000a0b0b7208 */
/* 0x000fc80000800000 */
/*08a0*/ FSETP.GT.AND P5, PT, R20, R11, PT ; /* 0x0000000b1400720b */
/* 0x000fc80003fa4000 */
/*08b0*/ FSEL R20, R20, R11, P5 ; /* 0x0000000b14147208 */
/* 0x000fe40002800000 */
/*08c0*/ LDS.128 R8, [0xb0] ; /* 0x0000b000ff087984 */
/* 0x000e220000000c00 */
/*08d0*/ @!P1 SEL R19, R18, R17, P0 ; /* 0x0000001112139207 */
/* 0x000fe40000000000 */
/*08e0*/ FSETP.GT.AND P6, PT, R21, R20, PT ; /* 0x000000141500720b */
/* 0x000fc80003fc4000 */
/*08f0*/ FSEL R21, R21, R20, P6 ; /* 0x0000001415157208 */
/* 0x000fc80003000000 */
/*0900*/ FSETP.GT.AND P3, PT, R22, R21, PT ; /* 0x000000151600720b */
/* 0x000fc80003f64000 */
/*0910*/ FSEL R22, R22, R21, P3 ; /* 0x0000001516167208 */
/* 0x000fc80001800000 */
/*0920*/ FSETP.GT.AND P4, PT, R23, R22, PT ; /* 0x000000161700720b */
/* 0x000fc80003f84000 */
/*0930*/ FSEL R23, R23, R22, P4 ; /* 0x0000001617177208 */
/* 0x000fc80002000000 */
/*0940*/ FSETP.GT.AND P2, PT, R12, R23, PT ; /* 0x000000170c00720b */
/* 0x002fc80003f44000 */
/*0950*/ FSEL R12, R12, R23, P2 ; /* 0x000000170c0c7208 */
/* 0x000fe40001000000 */
/*0960*/ LDS.128 R20, [0xc0] ; /* 0x0000c000ff147984 */
/* 0x000e640000000c00 */
/*0970*/ FSETP.GT.AND P0, PT, R13, R12, PT ; /* 0x0000000c0d00720b */
/* 0x000fc80003f04000 */
/*0980*/ FSEL R13, R13, R12, P0 ; /* 0x0000000c0d0d7208 */
/* 0x000fe40000000000 */
/*0990*/ @!P6 SEL R9, R8, R19, P5 ; /* 0x000000130809e207 */
/* 0x001fe40002800000 */
/*09a0*/ FSETP.GT.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720b */
/* 0x000fe20003f24000 */
/*09b0*/ LDS.128 R16, [0x60] ; /* 0x00006000ff107984 */
/* 0x000e220000000c00 */
/*09c0*/ @!P4 SEL R11, R10, R9, P3 ; /* 0x000000090a0bc207 */
/* 0x000fe40001800000 */
/*09d0*/ FSEL R14, R14, R13, P1 ; /* 0x0000000d0e0e7208 */
/* 0x000fc80000800000 */
/*09e0*/ FSETP.GT.AND P6, PT, R15, R14, PT ; /* 0x0000000e0f00720b */
/* 0x000fc80003fc4000 */
/*09f0*/ FSEL R15, R15, R14, P6 ; /* 0x0000000e0f0f7208 */
/* 0x000fc80003000000 */
/*0a00*/ FSETP.GT.AND P5, PT, R4, R15, PT ; /* 0x0000000f0400720b */
/* 0x000fc80003fa4000 */
/*0a10*/ FSEL R4, R4, R15, P5 ; /* 0x0000000f04047208 */
/* 0x000fe40002800000 */
/*0a20*/ LDS.128 R12, [0xd0] ; /* 0x0000d000ff0c7984 */
/* 0x000ea40000000c00 */
/*0a30*/ FSETP.GT.AND P4, PT, R5, R4, PT ; /* 0x000000040500720b */
/* 0x000fc80003f84000 */
/*0a40*/ FSEL R5, R5, R4, P4 ; /* 0x0000000405057208 */
/* 0x000fe40002000000 */
/*0a50*/ @!P0 SEL R21, R20, R11, P2 ; /* 0x0000000b14158207 */
/* 0x002fe40001000000 */
/*0a60*/ FSETP.GT.AND P3, PT, R6, R5, PT ; /* 0x000000050600720b */
/* 0x000fe20003f64000 */
/*0a70*/ LDS.128 R8, [0x70] ; /* 0x00007000ff087984 */
/* 0x000e620000000c00 */
/*0a80*/ @!P6 SEL R23, R22, R21, P1 ; /* 0x000000151617e207 */
/* 0x000fe40000800000 */
/*0a90*/ FSEL R6, R6, R5, P3 ; /* 0x0000000506067208 */
/* 0x000fc80001800000 */
/*0aa0*/ FSETP.GT.AND P0, PT, R7, R6, PT ; /* 0x000000060700720b */
/* 0x000fc80003f04000 */
/*0ab0*/ FSEL R7, R7, R6, P0 ; /* 0x0000000607077208 */
/* 0x000fc80000000000 */
/*0ac0*/ FSETP.GT.AND P2, PT, R16, R7, PT ; /* 0x000000071000720b */
/* 0x001fc80003f44000 */
/*0ad0*/ FSEL R16, R16, R7, P2 ; /* 0x0000000710107208 */
/* 0x000fe40001000000 */
/*0ae0*/ LDS.128 R4, [0xe0] ; /* 0x0000e000ff047984 */
/* 0x000e240000000c00 */
/*0af0*/ FSETP.GT.AND P1, PT, R17, R16, PT ; /* 0x000000101100720b */
/* 0x000fc80003f24000 */
/*0b00*/ FSEL R17, R17, R16, P1 ; /* 0x0000001011117208 */
/* 0x000fe40000800000 */
/*0b10*/ @!P4 SEL R13, R12, R23, P5 ; /* 0x000000170c0dc207 */
/* 0x004fe40002800000 */
/*0b20*/ FSETP.GT.AND P6, PT, R18, R17, PT ; /* 0x000000111200720b */
/* 0x000fe20003fc4000 */
/*0b30*/ LDS.128 R20, [0xf0] ; /* 0x0000f000ff147984 */
/* 0x000ea20000000c00 */
/*0b40*/ @!P0 SEL R15, R14, R13, P3 ; /* 0x0000000d0e0f8207 */
/* 0x000fe40001800000 */
/*0b50*/ FSEL R18, R18, R17, P6 ; /* 0x0000001112127208 */
/* 0x000fc80003000000 */
/*0b60*/ FSETP.GT.AND P4, PT, R19, R18, PT ; /* 0x000000121300720b */
/* 0x000fc80003f84000 */
/*0b70*/ FSEL R19, R19, R18, P4 ; /* 0x0000001213137208 */
/* 0x000fc80002000000 */
/*0b80*/ FSETP.GT.AND P5, PT, R8, R19, PT ; /* 0x000000130800720b */
/* 0x002fc80003fa4000 */
/*0b90*/ FSEL R8, R8, R19, P5 ; /* 0x0000001308087208 */
/* 0x000fc80002800000 */
/*0ba0*/ FSETP.GT.AND P3, PT, R9, R8, PT ; /* 0x000000080900720b */
/* 0x000fc80003f64000 */
/*0bb0*/ FSEL R9, R9, R8, P3 ; /* 0x0000000809097208 */
/* 0x000fe40001800000 */
/*0bc0*/ @!P1 SEL R5, R4, R15, P2 ; /* 0x0000000f04059207 */
/* 0x001fe40001000000 */
/*0bd0*/ FSETP.GT.AND P0, PT, R10, R9, PT ; /* 0x000000090a00720b */
/* 0x000fe40003f04000 */
/*0be0*/ @!P4 SEL R7, R6, R5, P6 ; /* 0x000000050607c207 */
/* 0x000fe40003000000 */
/*0bf0*/ FSEL R10, R10, R9, P0 ; /* 0x000000090a0a7208 */
/* 0x000fc80000000000 */
/*0c00*/ FSETP.GT.AND P1, PT, R11, R10, PT ; /* 0x0000000a0b00720b */
/* 0x000fe40003f24000 */
/*0c10*/ @!P3 SEL R21, R20, R7, P5 ; /* 0x000000071415b207 */
/* 0x004fd60002800000 */
/*0c20*/ @!P1 SEL R23, R22, R21, P0 ; /* 0x0000001516179207 */
/* 0x000fcc0000000000 */
/*0c30*/ I2F.U32 R23, R23 ; /* 0x0000001700177306 */
/* 0x000e240000201000 */
/*0c40*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x001fe2000c101904 */
/*0c50*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c60*/ BRA 0xc60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kArgMaxColumnwise(float* mat, float* target, unsigned int width, unsigned int height) {
__shared__ float max_vals[32];
__shared__ unsigned int max_args[32];
float cur_max = -2e38;
unsigned int cur_arg = 0;
float val = 0;
for (unsigned int i = threadIdx.x; i < height; i += 32) {
val = mat[i * width + blockIdx.x];
if (val > cur_max) {
cur_max = val;
cur_arg = i;
}
}
max_vals[threadIdx.x] = cur_max;
max_args[threadIdx.x] = cur_arg;
__syncthreads();
if (threadIdx.x == 0) {
cur_max = -2e38;
cur_arg = 0;
for (unsigned int i = 0; i < 32; i++)
if (max_vals[i] > cur_max) {
cur_max = max_vals[i];
cur_arg = max_args[i];
}
target[blockIdx.x] = cur_arg;
}
} | .file "tmpxft_0019ad13_00000000-6_kArgMaxColumnwise.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z17kArgMaxColumnwisePfS_jjPfS_jj
.type _Z41__device_stub__Z17kArgMaxColumnwisePfS_jjPfS_jj, @function
_Z41__device_stub__Z17kArgMaxColumnwisePfS_jjPfS_jj:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17kArgMaxColumnwisePfS_jj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z17kArgMaxColumnwisePfS_jjPfS_jj, .-_Z41__device_stub__Z17kArgMaxColumnwisePfS_jjPfS_jj
.globl _Z17kArgMaxColumnwisePfS_jj
.type _Z17kArgMaxColumnwisePfS_jj, @function
_Z17kArgMaxColumnwisePfS_jj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z17kArgMaxColumnwisePfS_jjPfS_jj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17kArgMaxColumnwisePfS_jj, .-_Z17kArgMaxColumnwisePfS_jj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17kArgMaxColumnwisePfS_jj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17kArgMaxColumnwisePfS_jj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kArgMaxColumnwise(float* mat, float* target, unsigned int width, unsigned int height) {
__shared__ float max_vals[32];
__shared__ unsigned int max_args[32];
float cur_max = -2e38;
unsigned int cur_arg = 0;
float val = 0;
for (unsigned int i = threadIdx.x; i < height; i += 32) {
val = mat[i * width + blockIdx.x];
if (val > cur_max) {
cur_max = val;
cur_arg = i;
}
}
max_vals[threadIdx.x] = cur_max;
max_args[threadIdx.x] = cur_arg;
__syncthreads();
if (threadIdx.x == 0) {
cur_max = -2e38;
cur_arg = 0;
for (unsigned int i = 0; i < 32; i++)
if (max_vals[i] > cur_max) {
cur_max = max_vals[i];
cur_arg = max_args[i];
}
target[blockIdx.x] = cur_arg;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kArgMaxColumnwise(float* mat, float* target, unsigned int width, unsigned int height) {
__shared__ float max_vals[32];
__shared__ unsigned int max_args[32];
float cur_max = -2e38;
unsigned int cur_arg = 0;
float val = 0;
for (unsigned int i = threadIdx.x; i < height; i += 32) {
val = mat[i * width + blockIdx.x];
if (val > cur_max) {
cur_max = val;
cur_arg = i;
}
}
max_vals[threadIdx.x] = cur_max;
max_args[threadIdx.x] = cur_arg;
__syncthreads();
if (threadIdx.x == 0) {
cur_max = -2e38;
cur_arg = 0;
for (unsigned int i = 0; i < 32; i++)
if (max_vals[i] > cur_max) {
cur_max = max_vals[i];
cur_arg = max_args[i];
}
target[blockIdx.x] = cur_arg;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kArgMaxColumnwise(float* mat, float* target, unsigned int width, unsigned int height) {
__shared__ float max_vals[32];
__shared__ unsigned int max_args[32];
float cur_max = -2e38;
unsigned int cur_arg = 0;
float val = 0;
for (unsigned int i = threadIdx.x; i < height; i += 32) {
val = mat[i * width + blockIdx.x];
if (val > cur_max) {
cur_max = val;
cur_arg = i;
}
}
max_vals[threadIdx.x] = cur_max;
max_args[threadIdx.x] = cur_arg;
__syncthreads();
if (threadIdx.x == 0) {
cur_max = -2e38;
cur_arg = 0;
for (unsigned int i = 0; i < 32; i++)
if (max_vals[i] > cur_max) {
cur_max = max_vals[i];
cur_arg = max_args[i];
}
target[blockIdx.x] = cur_arg;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17kArgMaxColumnwisePfS_jj
.globl _Z17kArgMaxColumnwisePfS_jj
.p2align 8
.type _Z17kArgMaxColumnwisePfS_jj,@function
_Z17kArgMaxColumnwisePfS_jj:
s_load_b32 s3, s[0:1], 0x14
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, 0xff167699
s_mov_b32 s2, s15
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB0_4
s_clause 0x1
s_load_b32 s7, s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x0
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, 0xff167699
v_mov_b32_e32 v5, v0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, v0, s7, s[2:3]
v_mov_b32_e32 v2, 0
s_lshl_b32 s8, s7, 5
s_mov_b32 s7, 0
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[1:2]
v_add_nc_u32_e32 v1, s8, v1
v_add_co_u32 v6, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_b32 v6, v[6:7], off
s_waitcnt vmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, v6, v4
v_dual_cndmask_b32 v4, v4, v6 :: v_dual_cndmask_b32 v3, v3, v5
v_add_nc_u32_e32 v5, 32, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_u32_e32 vcc_lo, s3, v5
s_or_b32 s7, vcc_lo, s7
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s7
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s6
v_lshlrev_b32_e32 v1, 2, v0
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
ds_store_2addr_b32 v1, v3, v4 offset1:32
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_10
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0xff167699
s_branch .LBB0_7
.LBB0_6:
s_add_i32 s3, s3, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_eq_i32 s3, 0x80
s_cbranch_scc1 .LBB0_9
.LBB0_7:
v_mov_b32_e32 v2, s3
ds_load_b32 v2, v2 offset:128
s_waitcnt lgkmcnt(0)
v_cmp_ngt_f32_e32 vcc_lo, v2, v1
s_cbranch_vccnz .LBB0_6
v_dual_mov_b32 v0, s3 :: v_dual_mov_b32 v1, v2
ds_load_b32 v0, v0
s_branch .LBB0_6
.LBB0_9:
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v0, v0
s_lshl_b64 s[2:3], s[2:3], 2
v_mov_b32_e32 v1, 0
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17kArgMaxColumnwisePfS_jj
.amdhsa_group_segment_fixed_size 256
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17kArgMaxColumnwisePfS_jj, .Lfunc_end0-_Z17kArgMaxColumnwisePfS_jj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 256
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17kArgMaxColumnwisePfS_jj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17kArgMaxColumnwisePfS_jj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kArgMaxColumnwise(float* mat, float* target, unsigned int width, unsigned int height) {
__shared__ float max_vals[32];
__shared__ unsigned int max_args[32];
float cur_max = -2e38;
unsigned int cur_arg = 0;
float val = 0;
for (unsigned int i = threadIdx.x; i < height; i += 32) {
val = mat[i * width + blockIdx.x];
if (val > cur_max) {
cur_max = val;
cur_arg = i;
}
}
max_vals[threadIdx.x] = cur_max;
max_args[threadIdx.x] = cur_arg;
__syncthreads();
if (threadIdx.x == 0) {
cur_max = -2e38;
cur_arg = 0;
for (unsigned int i = 0; i < 32; i++)
if (max_vals[i] > cur_max) {
cur_max = max_vals[i];
cur_arg = max_args[i];
}
target[blockIdx.x] = cur_arg;
}
} | .text
.file "kArgMaxColumnwise.hip"
.globl _Z32__device_stub__kArgMaxColumnwisePfS_jj # -- Begin function _Z32__device_stub__kArgMaxColumnwisePfS_jj
.p2align 4, 0x90
.type _Z32__device_stub__kArgMaxColumnwisePfS_jj,@function
_Z32__device_stub__kArgMaxColumnwisePfS_jj: # @_Z32__device_stub__kArgMaxColumnwisePfS_jj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17kArgMaxColumnwisePfS_jj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z32__device_stub__kArgMaxColumnwisePfS_jj, .Lfunc_end0-_Z32__device_stub__kArgMaxColumnwisePfS_jj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17kArgMaxColumnwisePfS_jj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17kArgMaxColumnwisePfS_jj,@object # @_Z17kArgMaxColumnwisePfS_jj
.section .rodata,"a",@progbits
.globl _Z17kArgMaxColumnwisePfS_jj
.p2align 3, 0x0
_Z17kArgMaxColumnwisePfS_jj:
.quad _Z32__device_stub__kArgMaxColumnwisePfS_jj
.size _Z17kArgMaxColumnwisePfS_jj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17kArgMaxColumnwisePfS_jj"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__kArgMaxColumnwisePfS_jj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17kArgMaxColumnwisePfS_jj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17kArgMaxColumnwisePfS_jj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x5c0 ; /* 0x0000058000007945 */
/* 0x000fe20003800000 */
/*0040*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe400078e00ff */
/*0050*/ IMAD.MOV.U32 R7, RZ, RZ, -0xe98967 ; /* 0xff167699ff077424 */
/* 0x000fe200078e00ff */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x001fda0003f06070 */
/*0070*/ @P0 BRA 0x5b0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0080*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0090*/ ISETP.GE.U32.AND P3, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f66070 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fd800078e0000 */
/*00b0*/ @P3 IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff093424 */
/* 0x000fe400078e00ff */
/*00c0*/ @P3 IMAD R8, R2, c[0x0][0x170], R5 ; /* 0x00005c0002083a24 */
/* 0x001fc800078e0205 */
/*00d0*/ @P3 IMAD.WIDE.U32 R8, R8, R9, c[0x0][0x160] ; /* 0x0000580008083625 */
/* 0x000fcc00078e0009 */
/*00e0*/ @P3 LDG.E R8, [R8.64] ; /* 0x0000000408083981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD.MOV.U32 R7, RZ, RZ, -0xe98967 ; /* 0xff167699ff077424 */
/* 0x000fe200078e00ff */
/*0100*/ BSSY B1, 0x3c0 ; /* 0x000002b000017945 */
/* 0x000fe20003800000 */
/*0110*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fc600078e00ff */
/*0120*/ @P3 FSETP.GT.AND P2, PT, R8, R7, PT ; /* 0x000000070800320b */
/* 0x004fc80003f44000 */
/*0130*/ @P3 SEL R3, R2.reuse, R3, P2 ; /* 0x0000000302033207 */
/* 0x040fe40001000000 */
/*0140*/ @P3 IADD3 R2, R2, 0x20, RZ ; /* 0x0000002002023810 */
/* 0x000fe40007ffe0ff */
/*0150*/ @P3 FSEL R7, R8, R7, P2 ; /* 0x0000000708073208 */
/* 0x000fe40001000000 */
/*0160*/ ISETP.GE.U32.AND P0, PT, R2.reuse, c[0x0][0x174], PT ; /* 0x00005d0002007a0c */
/* 0x040fe40003f06070 */
/*0170*/ IADD3 R4, -R2, c[0x0][0x174], RZ ; /* 0x00005d0002047a10 */
/* 0x000fc80007ffe1ff */
/*0180*/ ISETP.LE.U32.OR P1, PT, R4, 0x60, P0 ; /* 0x000000600400780c */
/* 0x000fe40000723470 */
/*0190*/ PLOP3.LUT P0, PT, P3, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60001f0e170 */
/*01a0*/ @P1 BRA 0x3b0 ; /* 0x0000020000001947 */
/* 0x000fea0003800000 */
/*01b0*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff0f7624 */
/* 0x000fe200078e00ff */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc80003f0e170 */
/*01d0*/ IADD3 R15, R15, -0x60, RZ ; /* 0xffffffa00f0f7810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; /* 0x00000004ff117424 */
/* 0x000fe200078e00ff */
/*01f0*/ IADD3 R4, R2.reuse, 0x20, RZ ; /* 0x0000002002047810 */
/* 0x040fe20007ffe0ff */
/*0200*/ IMAD R8, R2, c[0x0][0x170], R5 ; /* 0x00005c0002087a24 */
/* 0x000fc800078e0205 */
/*0210*/ IMAD.WIDE.U32 R8, R8, R17, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fc800078e0011 */
/*0220*/ IMAD R10, R4, c[0x0][0x170], R5 ; /* 0x00005c00040a7a24 */
/* 0x000fe400078e0205 */
/*0230*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea4000c1e1900 */
/*0240*/ IMAD.WIDE.U32 R10, R10, R17, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fcc00078e0011 */
/*0250*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ee2000c1e1900 */
/*0260*/ IADD3 R6, R2, 0x40, RZ ; /* 0x0000004002067810 */
/* 0x000fca0007ffe0ff */
/*0270*/ IMAD R12, R6, c[0x0][0x170], R5 ; /* 0x00005c00060c7a24 */
/* 0x000fc800078e0205 */
/*0280*/ IMAD.WIDE.U32 R12, R12, R17, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x000fcc00078e0011 */
/*0290*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f22000c1e1900 */
/*02a0*/ FSETP.GT.AND P1, PT, R8, R7, PT ; /* 0x000000070800720b */
/* 0x004fc80003f24000 */
/*02b0*/ FSEL R7, R8, R7, P1 ; /* 0x0000000708077208 */
/* 0x000fc80000800000 */
/*02c0*/ FSETP.GT.AND P2, PT, R10, R7, PT ; /* 0x000000070a00720b */
/* 0x008fda0003f44000 */
/*02d0*/ @!P2 SEL R4, R2.reuse, R3, P1 ; /* 0x000000030204a207 */
/* 0x040fe40000800000 */
/*02e0*/ IADD3 R3, R2, 0x60, RZ ; /* 0x0000006002037810 */
/* 0x000fca0007ffe0ff */
/*02f0*/ IMAD R8, R3, c[0x0][0x170], R5 ; /* 0x00005c0003087a24 */
/* 0x000fc800078e0205 */
/*0300*/ IMAD.WIDE.U32 R8, R8, R17, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fcc00078e0011 */
/*0310*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1900 */
/*0320*/ FSEL R7, R10, R7, P2 ; /* 0x000000070a077208 */
/* 0x000fe40001000000 */
/*0330*/ IADD3 R2, R2, 0x80, RZ ; /* 0x0000008002027810 */
/* 0x000fe40007ffe0ff */
/*0340*/ FSETP.GT.AND P1, PT, R12, R7, PT ; /* 0x000000070c00720b */
/* 0x010fe40003f24000 */
/*0350*/ ISETP.GE.U32.AND P3, PT, R2, R15, PT ; /* 0x0000000f0200720c */
/* 0x000fe40003f66070 */
/*0360*/ FSEL R7, R12, R7, P1 ; /* 0x000000070c077208 */
/* 0x000fc80000800000 */
/*0370*/ FSETP.GT.AND P2, PT, R8, R7, PT ; /* 0x000000070800720b */
/* 0x004fc80003f44000 */
/*0380*/ FSEL R7, R8, R7, P2 ; /* 0x0000000708077208 */
/* 0x000fd20001000000 */
/*0390*/ @!P2 SEL R3, R6, R4, P1 ; /* 0x000000040603a207 */
/* 0x000fe20000800000 */
/*03a0*/ @!P3 BRA 0x1e0 ; /* 0xfffffe300000b947 */
/* 0x000fea000383ffff */
/*03b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*03c0*/ ISETP.GE.U32.AND P1, PT, R2.reuse, c[0x0][0x174], PT ; /* 0x00005d0002007a0c */
/* 0x040fe20003f26070 */
/*03d0*/ BSSY B1, 0x520 ; /* 0x0000014000017945 */
/* 0x000fe20003800000 */
/*03e0*/ IADD3 R4, -R2, c[0x0][0x174], RZ ; /* 0x00005d0002047a10 */
/* 0x000fc80007ffe1ff */
/*03f0*/ ISETP.LE.U32.OR P1, PT, R4, 0x20, P1 ; /* 0x000000200400780c */
/* 0x000fda0000f23470 */
/*0400*/ @P1 BRA 0x510 ; /* 0x0000010000001947 */
/* 0x000fea0003800000 */
/*0410*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0420*/ IADD3 R4, R2.reuse, 0x20, RZ ; /* 0x0000002002047810 */
/* 0x040fe20007ffe0ff */
/*0430*/ IMAD R10, R2, c[0x0][0x170], R5 ; /* 0x00005c00020a7a24 */
/* 0x000fc800078e0205 */
/*0440*/ IMAD.WIDE.U32 R10, R10, R9, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fc800078e0009 */
/*0450*/ IMAD R8, R4, c[0x0][0x170], R5 ; /* 0x00005c0004087a24 */
/* 0x000fe400078e0205 */
/*0460*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea4000c1e1900 */
/*0470*/ IMAD.WIDE.U32 R8, R8, R9, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fcc00078e0009 */
/*0480*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee2000c1e1900 */
/*0490*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*04a0*/ FSETP.GT.AND P1, PT, R10, R7, PT ; /* 0x000000070a00720b */
/* 0x004fc80003f24000 */
/*04b0*/ FSEL R7, R10, R7, P1 ; /* 0x000000070a077208 */
/* 0x000fc80000800000 */
/*04c0*/ FSETP.GT.AND P2, PT, R8, R7, PT ; /* 0x000000070800720b */
/* 0x008fc80003f44000 */
/*04d0*/ FSEL R7, R8, R7, P2 ; /* 0x0000000708077208 */
/* 0x000fd20001000000 */
/*04e0*/ @!P2 SEL R4, R2.reuse, R3, P1 ; /* 0x000000030204a207 */
/* 0x040fe40000800000 */
/*04f0*/ IADD3 R2, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x000fc60007ffe0ff */
/*0500*/ IMAD.MOV.U32 R3, RZ, RZ, R4 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0004 */
/*0510*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0520*/ ISETP.LT.U32.OR P0, PT, R2, c[0x0][0x174], P0 ; /* 0x00005d0002007a0c */
/* 0x000fda0000701470 */
/*0530*/ @!P0 BRA 0x5b0 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*0540*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe400078e00ff */
/*0550*/ IMAD R5, R2, c[0x0][0x170], R5 ; /* 0x00005c0002057a24 */
/* 0x000fc800078e0205 */
/*0560*/ IMAD.WIDE.U32 R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fcc00078e0004 */
/*0570*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*0580*/ FSETP.GT.AND P0, PT, R4, R7, PT ; /* 0x000000070400720b */
/* 0x004fc80003f04000 */
/*0590*/ FSEL R7, R4, R7, P0 ; /* 0x0000000704077208 */
/* 0x000fe40000000000 */
/*05a0*/ SEL R3, R2, R3, P0 ; /* 0x0000000302037207 */
/* 0x000fe40000000000 */
/*05b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05c0*/ STS [R0.X4], R7 ; /* 0x0000000700007388 */
/* 0x0001e20000004800 */
/*05d0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc60003f05270 */
/*05e0*/ STS [R0.X4+0x80], R3 ; /* 0x0000800300007388 */
/* 0x0001e80000004800 */
/*05f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0600*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0610*/ LDS.128 R16, [RZ] ; /* 0x00000000ff107984 */
/* 0x001e220000000c00 */
/*0620*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc600078e00ff */
/*0630*/ LDS.128 R12, [0x10] ; /* 0x00001000ff0c7984 */
/* 0x000fe80000000c00 */
/*0640*/ LDS.128 R24, [0x80] ; /* 0x00008000ff187984 */
/* 0x000e680000000c00 */
/*0650*/ LDS.128 R8, [0x20] ; /* 0x00002000ff087984 */
/* 0x000fe80000000c00 */
/*0660*/ LDS.128 R4, [0x90] ; /* 0x00009000ff047984 */
/* 0x000ea80000000c00 */
/*0670*/ LDS.128 R20, [0x30] ; /* 0x00003000ff147984 */
/* 0x000fe80000000c00 */
/*0680*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000ee20000002500 */
/*0690*/ FMNMX R0, R16, -1.99999993605713849301e+38, !PT ; /* 0xff16769910007809 */
/* 0x001fc40007800000 */
/*06a0*/ FSETP.GT.AND P2, PT, R16, -1.99999993605713849301e+38, PT ; /* 0xff1676991000780b */
/* 0x000fe40003f44000 */
/*06b0*/ FSETP.GT.AND P6, PT, R17, R0, PT ; /* 0x000000001100720b */
/* 0x000fc80003fc4000 */
/*06c0*/ FSEL R17, R17, R0, P6 ; /* 0x0000000011117208 */
/* 0x000fe20003000000 */
/*06d0*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x008fc600078e0003 */
/*06e0*/ FSETP.GT.AND P0, PT, R18, R17, PT ; /* 0x000000111200720b */
/* 0x000fc80003f04000 */
/*06f0*/ FSEL R18, R18, R17, P0 ; /* 0x0000001112127208 */
/* 0x000fe40000000000 */
/*0700*/ @!P6 SEL R25, R24, RZ, P2 ; /* 0x000000ff1819e207 */
/* 0x002fe40001000000 */
/*0710*/ FSETP.GT.AND P4, PT, R19, R18, PT ; /* 0x000000121300720b */
/* 0x000fc80003f84000 */
/*0720*/ FSEL R19, R19, R18, P4 ; /* 0x0000001213137208 */
/* 0x000fc80002000000 */
/*0730*/ FSETP.GT.AND P1, PT, R12, R19, PT ; /* 0x000000130c00720b */
/* 0x000fc80003f24000 */
/*0740*/ FSEL R12, R12, R19, P1 ; /* 0x000000130c0c7208 */
/* 0x000fe40000800000 */
/*0750*/ @!P4 SEL R27, R26, R25, P0 ; /* 0x000000191a1bc207 */
/* 0x000fe20000000000 */
/*0760*/ LDS.128 R16, [0xa0] ; /* 0x0000a000ff107984 */
/* 0x000e220000000c00 */
/*0770*/ FSETP.GT.AND P5, PT, R13, R12, PT ; /* 0x0000000c0d00720b */
/* 0x000fc80003fa4000 */
/*0780*/ FSEL R13, R13, R12, P5 ; /* 0x0000000c0d0d7208 */
/* 0x000fc80002800000 */
/*0790*/ FSETP.GT.AND P3, PT, R14, R13, PT ; /* 0x0000000d0e00720b */
/* 0x000fc80003f64000 */
/*07a0*/ FSEL R14, R14, R13, P3 ; /* 0x0000000d0e0e7208 */
/* 0x000fe40001800000 */
/*07b0*/ @!P5 SEL R5, R4, R27, P1 ; /* 0x0000001b0405d207 */
/* 0x004fe40000800000 */
/*07c0*/ FSETP.GT.AND P6, PT, R15, R14, PT ; /* 0x0000000e0f00720b */
/* 0x000fc80003fc4000 */
/*07d0*/ FSEL R15, R15, R14, P6 ; /* 0x0000000e0f0f7208 */
/* 0x000fc80003000000 */
/*07e0*/ FSETP.GT.AND P2, PT, R8, R15, PT ; /* 0x0000000f0800720b */
/* 0x000fc80003f44000 */
/*07f0*/ FSEL R8, R8, R15, P2 ; /* 0x0000000f08087208 */
/* 0x000fe40001000000 */
/*0800*/ LDS.128 R12, [0x40] ; /* 0x00004000ff0c7984 */
/* 0x000e620000000c00 */
/*0810*/ @!P6 SEL R7, R6, R5, P3 ; /* 0x000000050607e207 */
/* 0x000fe40001800000 */
/*0820*/ FSETP.GT.AND P4, PT, R9, R8, PT ; /* 0x000000080900720b */
/* 0x000fc80003f84000 */
/*0830*/ FSEL R9, R9, R8, P4 ; /* 0x0000000809097208 */
/* 0x000fc80002000000 */
/*0840*/ FSETP.GT.AND P0, PT, R10, R9, PT ; /* 0x000000090a00720b */
/* 0x000fc80003f04000 */
/*0850*/ FSEL R10, R10, R9, P0 ; /* 0x000000090a0a7208 */
/* 0x000fe40000000000 */
/*0860*/ @!P4 SEL R17, R16, R7, P2 ; /* 0x000000071011c207 */
/* 0x001fe40001000000 */
/*0870*/ FSETP.GT.AND P1, PT, R11.reuse, R10.reuse, PT ; /* 0x0000000a0b00720b */
/* 0x0c0fe20003f24000 */
/*0880*/ LDS.128 R4, [0x50] ; /* 0x00005000ff047984 */
/* 0x000fe60000000c00 */
/*0890*/ FSEL R11, R11, R10, P1 ; /* 0x0000000a0b0b7208 */
/* 0x000fc80000800000 */
/*08a0*/ FSETP.GT.AND P5, PT, R20, R11, PT ; /* 0x0000000b1400720b */
/* 0x000fc80003fa4000 */
/*08b0*/ FSEL R20, R20, R11, P5 ; /* 0x0000000b14147208 */
/* 0x000fe40002800000 */
/*08c0*/ LDS.128 R8, [0xb0] ; /* 0x0000b000ff087984 */
/* 0x000e220000000c00 */
/*08d0*/ @!P1 SEL R19, R18, R17, P0 ; /* 0x0000001112139207 */
/* 0x000fe40000000000 */
/*08e0*/ FSETP.GT.AND P6, PT, R21, R20, PT ; /* 0x000000141500720b */
/* 0x000fc80003fc4000 */
/*08f0*/ FSEL R21, R21, R20, P6 ; /* 0x0000001415157208 */
/* 0x000fc80003000000 */
/*0900*/ FSETP.GT.AND P3, PT, R22, R21, PT ; /* 0x000000151600720b */
/* 0x000fc80003f64000 */
/*0910*/ FSEL R22, R22, R21, P3 ; /* 0x0000001516167208 */
/* 0x000fc80001800000 */
/*0920*/ FSETP.GT.AND P4, PT, R23, R22, PT ; /* 0x000000161700720b */
/* 0x000fc80003f84000 */
/*0930*/ FSEL R23, R23, R22, P4 ; /* 0x0000001617177208 */
/* 0x000fc80002000000 */
/*0940*/ FSETP.GT.AND P2, PT, R12, R23, PT ; /* 0x000000170c00720b */
/* 0x002fc80003f44000 */
/*0950*/ FSEL R12, R12, R23, P2 ; /* 0x000000170c0c7208 */
/* 0x000fe40001000000 */
/*0960*/ LDS.128 R20, [0xc0] ; /* 0x0000c000ff147984 */
/* 0x000e640000000c00 */
/*0970*/ FSETP.GT.AND P0, PT, R13, R12, PT ; /* 0x0000000c0d00720b */
/* 0x000fc80003f04000 */
/*0980*/ FSEL R13, R13, R12, P0 ; /* 0x0000000c0d0d7208 */
/* 0x000fe40000000000 */
/*0990*/ @!P6 SEL R9, R8, R19, P5 ; /* 0x000000130809e207 */
/* 0x001fe40002800000 */
/*09a0*/ FSETP.GT.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720b */
/* 0x000fe20003f24000 */
/*09b0*/ LDS.128 R16, [0x60] ; /* 0x00006000ff107984 */
/* 0x000e220000000c00 */
/*09c0*/ @!P4 SEL R11, R10, R9, P3 ; /* 0x000000090a0bc207 */
/* 0x000fe40001800000 */
/*09d0*/ FSEL R14, R14, R13, P1 ; /* 0x0000000d0e0e7208 */
/* 0x000fc80000800000 */
/*09e0*/ FSETP.GT.AND P6, PT, R15, R14, PT ; /* 0x0000000e0f00720b */
/* 0x000fc80003fc4000 */
/*09f0*/ FSEL R15, R15, R14, P6 ; /* 0x0000000e0f0f7208 */
/* 0x000fc80003000000 */
/*0a00*/ FSETP.GT.AND P5, PT, R4, R15, PT ; /* 0x0000000f0400720b */
/* 0x000fc80003fa4000 */
/*0a10*/ FSEL R4, R4, R15, P5 ; /* 0x0000000f04047208 */
/* 0x000fe40002800000 */
/*0a20*/ LDS.128 R12, [0xd0] ; /* 0x0000d000ff0c7984 */
/* 0x000ea40000000c00 */
/*0a30*/ FSETP.GT.AND P4, PT, R5, R4, PT ; /* 0x000000040500720b */
/* 0x000fc80003f84000 */
/*0a40*/ FSEL R5, R5, R4, P4 ; /* 0x0000000405057208 */
/* 0x000fe40002000000 */
/*0a50*/ @!P0 SEL R21, R20, R11, P2 ; /* 0x0000000b14158207 */
/* 0x002fe40001000000 */
/*0a60*/ FSETP.GT.AND P3, PT, R6, R5, PT ; /* 0x000000050600720b */
/* 0x000fe20003f64000 */
/*0a70*/ LDS.128 R8, [0x70] ; /* 0x00007000ff087984 */
/* 0x000e620000000c00 */
/*0a80*/ @!P6 SEL R23, R22, R21, P1 ; /* 0x000000151617e207 */
/* 0x000fe40000800000 */
/*0a90*/ FSEL R6, R6, R5, P3 ; /* 0x0000000506067208 */
/* 0x000fc80001800000 */
/*0aa0*/ FSETP.GT.AND P0, PT, R7, R6, PT ; /* 0x000000060700720b */
/* 0x000fc80003f04000 */
/*0ab0*/ FSEL R7, R7, R6, P0 ; /* 0x0000000607077208 */
/* 0x000fc80000000000 */
/*0ac0*/ FSETP.GT.AND P2, PT, R16, R7, PT ; /* 0x000000071000720b */
/* 0x001fc80003f44000 */
/*0ad0*/ FSEL R16, R16, R7, P2 ; /* 0x0000000710107208 */
/* 0x000fe40001000000 */
/*0ae0*/ LDS.128 R4, [0xe0] ; /* 0x0000e000ff047984 */
/* 0x000e240000000c00 */
/*0af0*/ FSETP.GT.AND P1, PT, R17, R16, PT ; /* 0x000000101100720b */
/* 0x000fc80003f24000 */
/*0b00*/ FSEL R17, R17, R16, P1 ; /* 0x0000001011117208 */
/* 0x000fe40000800000 */
/*0b10*/ @!P4 SEL R13, R12, R23, P5 ; /* 0x000000170c0dc207 */
/* 0x004fe40002800000 */
/*0b20*/ FSETP.GT.AND P6, PT, R18, R17, PT ; /* 0x000000111200720b */
/* 0x000fe20003fc4000 */
/*0b30*/ LDS.128 R20, [0xf0] ; /* 0x0000f000ff147984 */
/* 0x000ea20000000c00 */
/*0b40*/ @!P0 SEL R15, R14, R13, P3 ; /* 0x0000000d0e0f8207 */
/* 0x000fe40001800000 */
/*0b50*/ FSEL R18, R18, R17, P6 ; /* 0x0000001112127208 */
/* 0x000fc80003000000 */
/*0b60*/ FSETP.GT.AND P4, PT, R19, R18, PT ; /* 0x000000121300720b */
/* 0x000fc80003f84000 */
/*0b70*/ FSEL R19, R19, R18, P4 ; /* 0x0000001213137208 */
/* 0x000fc80002000000 */
/*0b80*/ FSETP.GT.AND P5, PT, R8, R19, PT ; /* 0x000000130800720b */
/* 0x002fc80003fa4000 */
/*0b90*/ FSEL R8, R8, R19, P5 ; /* 0x0000001308087208 */
/* 0x000fc80002800000 */
/*0ba0*/ FSETP.GT.AND P3, PT, R9, R8, PT ; /* 0x000000080900720b */
/* 0x000fc80003f64000 */
/*0bb0*/ FSEL R9, R9, R8, P3 ; /* 0x0000000809097208 */
/* 0x000fe40001800000 */
/*0bc0*/ @!P1 SEL R5, R4, R15, P2 ; /* 0x0000000f04059207 */
/* 0x001fe40001000000 */
/*0bd0*/ FSETP.GT.AND P0, PT, R10, R9, PT ; /* 0x000000090a00720b */
/* 0x000fe40003f04000 */
/*0be0*/ @!P4 SEL R7, R6, R5, P6 ; /* 0x000000050607c207 */
/* 0x000fe40003000000 */
/*0bf0*/ FSEL R10, R10, R9, P0 ; /* 0x000000090a0a7208 */
/* 0x000fc80000000000 */
/*0c00*/ FSETP.GT.AND P1, PT, R11, R10, PT ; /* 0x0000000a0b00720b */
/* 0x000fe40003f24000 */
/*0c10*/ @!P3 SEL R21, R20, R7, P5 ; /* 0x000000071415b207 */
/* 0x004fd60002800000 */
/*0c20*/ @!P1 SEL R23, R22, R21, P0 ; /* 0x0000001516179207 */
/* 0x000fcc0000000000 */
/*0c30*/ I2F.U32 R23, R23 ; /* 0x0000001700177306 */
/* 0x000e240000201000 */
/*0c40*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x001fe2000c101904 */
/*0c50*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c60*/ BRA 0xc60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17kArgMaxColumnwisePfS_jj
.globl _Z17kArgMaxColumnwisePfS_jj
.p2align 8
.type _Z17kArgMaxColumnwisePfS_jj,@function
_Z17kArgMaxColumnwisePfS_jj:
s_load_b32 s3, s[0:1], 0x14
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, 0xff167699
s_mov_b32 s2, s15
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB0_4
s_clause 0x1
s_load_b32 s7, s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x0
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, 0xff167699
v_mov_b32_e32 v5, v0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, v0, s7, s[2:3]
v_mov_b32_e32 v2, 0
s_lshl_b32 s8, s7, 5
s_mov_b32 s7, 0
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[1:2]
v_add_nc_u32_e32 v1, s8, v1
v_add_co_u32 v6, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_b32 v6, v[6:7], off
s_waitcnt vmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, v6, v4
v_dual_cndmask_b32 v4, v4, v6 :: v_dual_cndmask_b32 v3, v3, v5
v_add_nc_u32_e32 v5, 32, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_u32_e32 vcc_lo, s3, v5
s_or_b32 s7, vcc_lo, s7
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s7
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s6
v_lshlrev_b32_e32 v1, 2, v0
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
ds_store_2addr_b32 v1, v3, v4 offset1:32
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_10
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0xff167699
s_branch .LBB0_7
.LBB0_6:
s_add_i32 s3, s3, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_eq_i32 s3, 0x80
s_cbranch_scc1 .LBB0_9
.LBB0_7:
v_mov_b32_e32 v2, s3
ds_load_b32 v2, v2 offset:128
s_waitcnt lgkmcnt(0)
v_cmp_ngt_f32_e32 vcc_lo, v2, v1
s_cbranch_vccnz .LBB0_6
v_dual_mov_b32 v0, s3 :: v_dual_mov_b32 v1, v2
ds_load_b32 v0, v0
s_branch .LBB0_6
.LBB0_9:
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v0, v0
s_lshl_b64 s[2:3], s[2:3], 2
v_mov_b32_e32 v1, 0
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17kArgMaxColumnwisePfS_jj
.amdhsa_group_segment_fixed_size 256
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17kArgMaxColumnwisePfS_jj, .Lfunc_end0-_Z17kArgMaxColumnwisePfS_jj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 256
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17kArgMaxColumnwisePfS_jj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17kArgMaxColumnwisePfS_jj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019ad13_00000000-6_kArgMaxColumnwise.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z17kArgMaxColumnwisePfS_jjPfS_jj
.type _Z41__device_stub__Z17kArgMaxColumnwisePfS_jjPfS_jj, @function
_Z41__device_stub__Z17kArgMaxColumnwisePfS_jjPfS_jj:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17kArgMaxColumnwisePfS_jj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z17kArgMaxColumnwisePfS_jjPfS_jj, .-_Z41__device_stub__Z17kArgMaxColumnwisePfS_jjPfS_jj
.globl _Z17kArgMaxColumnwisePfS_jj
.type _Z17kArgMaxColumnwisePfS_jj, @function
_Z17kArgMaxColumnwisePfS_jj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z17kArgMaxColumnwisePfS_jjPfS_jj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17kArgMaxColumnwisePfS_jj, .-_Z17kArgMaxColumnwisePfS_jj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17kArgMaxColumnwisePfS_jj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17kArgMaxColumnwisePfS_jj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kArgMaxColumnwise.hip"
.globl _Z32__device_stub__kArgMaxColumnwisePfS_jj # -- Begin function _Z32__device_stub__kArgMaxColumnwisePfS_jj
.p2align 4, 0x90
.type _Z32__device_stub__kArgMaxColumnwisePfS_jj,@function
_Z32__device_stub__kArgMaxColumnwisePfS_jj: # @_Z32__device_stub__kArgMaxColumnwisePfS_jj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17kArgMaxColumnwisePfS_jj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z32__device_stub__kArgMaxColumnwisePfS_jj, .Lfunc_end0-_Z32__device_stub__kArgMaxColumnwisePfS_jj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17kArgMaxColumnwisePfS_jj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17kArgMaxColumnwisePfS_jj,@object # @_Z17kArgMaxColumnwisePfS_jj
.section .rodata,"a",@progbits
.globl _Z17kArgMaxColumnwisePfS_jj
.p2align 3, 0x0
_Z17kArgMaxColumnwisePfS_jj:
.quad _Z32__device_stub__kArgMaxColumnwisePfS_jj
.size _Z17kArgMaxColumnwisePfS_jj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17kArgMaxColumnwisePfS_jj"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__kArgMaxColumnwisePfS_jj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17kArgMaxColumnwisePfS_jj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#define KERNEL_RADIUS 8
#define KERNEL_LENGTH (2 * KERNEL_RADIUS + 1)
#define TILE_SIZE 1024
__constant__ float c_M[KERNEL_LENGTH];
const int Width = 10240000;
const int nIter = 300;
float * h_Kernel,*h_Input,*h_Output;
float * d_Kernel, *d_Input, * d_Output;
__global__ void convolution_1D_basic_kernel(float* N, float* g_M, float* P,int Mask_Width, int Width){
int i = blockIdx.x * blockDim.x + threadIdx.x;
float Pvalue = 0;
int N_start_point = i - (Mask_Width/2);
for(int j = 0;j<Mask_Width;j++){
if(N_start_point + j>=0 && N_start_point + j <Width){
Pvalue += N[N_start_point + j] * g_M[j];
}else if(N_start_point + j<0){
Pvalue += N[0] * g_M[j];
}else{
Pvalue += N[Width - 1] * g_M[j];
}
}
P[i] = Pvalue;
}
__global__ void convolution_1D_constant_kernel(float * N,float* P,int Mask_Width,int Width){
int i = blockIdx.x * blockDim.x + threadIdx.x;
float Pvalue = 0;
int N_start_point = i - (Mask_Width/2);
for(int j = 0;j<Mask_Width;j++){
if(N_start_point + j>=0 && N_start_point + j <Width){
Pvalue += N[N_start_point + j] * c_M[j];
}else if(N_start_point + j < 0){
Pvalue += N[0] * c_M[j];
}else{
Pvalue += N[Width - 1] * c_M[j];
}
}
P[i] = Pvalue;
}
__global__ void convolution_1D_tiled_kernel(float* N, float* P,int Mask_Width, int Width){
int i = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ float N_ds[TILE_SIZE + KERNEL_LENGTH-1];
int n = Mask_Width/2;
int halo_index_left = (blockIdx.x - 1) * blockDim.x + threadIdx.x;
if(threadIdx.x >= blockDim.x - n){
N_ds[threadIdx.x - (blockDim.x - n)] = (halo_index_left<0) ? N[0]:N[halo_index_left];
}
N_ds[n+threadIdx.x] = N[blockIdx.x * blockDim.x + threadIdx.x];
int halo_index_right = (blockIdx.x + 1) * blockDim.x + threadIdx.x;
if(threadIdx.x < n){
N_ds[n + blockDim.x + threadIdx.x] = (halo_index_right >= Width) ? N[Width - 1]:N[halo_index_right];
}
__syncthreads();
float Pvalue = 0;
for(int j = 0;j<Mask_Width;j++){
Pvalue += N_ds[threadIdx.x + j] * c_M[j];
}
P[i] = Pvalue;
}
__global__ void convolution_1D_tiled_caching_kernel(float* N, float* P, int Mask_Width, int Width){
int i = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ float N_ds[TILE_SIZE];
N_ds[threadIdx.x] = N[i];
__syncthreads();
int This_tile_start_point = blockIdx.x * blockDim.x;
int Next_tile_start_point = (blockIdx.x + 1) * blockDim.x;
int N_start_point = i - (Mask_Width/2);
float Pvalue = 0;
for(int j = 0;j<Mask_Width;j++){
int N_index = N_start_point + j;
if(N_index >=0 && N_index<Width){
if((N_index>=This_tile_start_point) && (N_index< Next_tile_start_point)){
Pvalue += N_ds[threadIdx.x+ j - (Mask_Width/2)] * c_M[j];
}else{
Pvalue += N[N_index];
}
}
}
P[i] = Pvalue;
}
void gpuRunBasicKernel(){
convolution_1D_basic_kernel<<<(Width+TILE_SIZE - 1)/TILE_SIZE,TILE_SIZE>>>(d_Input,d_Kernel,d_Output,KERNEL_LENGTH,Width);
cudaDeviceSynchronize();
cudaEvent_t start;
cudaEventCreate(&start);
cudaEvent_t stop;
cudaEventCreate(&stop);
cudaEventRecord(start,NULL);
for(int i = 0;i<nIter;i++){
convolution_1D_basic_kernel<<<(Width+TILE_SIZE - 1)/TILE_SIZE,TILE_SIZE>>>(d_Input,d_Kernel,d_Output,KERNEL_LENGTH,Width);
}
cudaEventRecord(stop, NULL);
cudaDeviceSynchronize();
float msecTotal = 0.0f;
cudaEventElapsedTime(&msecTotal,start,stop);
float gpuTime = (msecTotal / nIter) * 0.001;
printf("Basic Kernel Throughput = %0.4f MPixels/sec, Time= %.5f sec, Size= %u Pixels\n",
(1.0e-6 * (Width)/gpuTime),
gpuTime,
Width);
cudaMemcpy(h_Output,d_Output,Width * sizeof(float),cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
bool correct = true;
double eps = 1.e-6;
for(int i = 0;i<Width;i++){
double abs_err = fabs(h_Output[i] - KERNEL_LENGTH * 1.0);
if (abs_err > eps)
{
printf("Error! Index = %d,h_Output = %f,true value = %d\n",
i, h_Output[i], KERNEL_LENGTH);
correct = false;
}
}
printf("%s\n", correct ? "Result = PASS" : "Result = FAIL");
}
void gpuRunConstantKernel(){
convolution_1D_constant_kernel<<<(Width+TILE_SIZE - 1)/TILE_SIZE,TILE_SIZE>>>(d_Input,d_Output,KERNEL_LENGTH,Width);
cudaDeviceSynchronize();
cudaEvent_t start;
cudaEventCreate(&start);
cudaEvent_t stop;
cudaEventCreate(&stop);
cudaEventRecord(start,NULL);
for(int i = 0;i<nIter;i++){
convolution_1D_constant_kernel<<<(Width+TILE_SIZE - 1)/TILE_SIZE,TILE_SIZE>>>(d_Input,d_Output,KERNEL_LENGTH,Width);
}
cudaEventRecord(stop, NULL);
cudaDeviceSynchronize();
float msecTotal = 0.0f;
cudaEventElapsedTime(&msecTotal,start,stop);
float gpuTime = (msecTotal / nIter) * 0.001;
printf("Constant Kernel Throughput = %0.4f MPixels/sec, Time= %.5f sec, Size= %u Pixels\n",
(1.0e-6 * (Width)/gpuTime),
gpuTime,
Width);
cudaMemcpy(h_Output,d_Output,Width * sizeof(float),cudaMemcpyDeviceToHost);
bool correct = true;
double eps = 1.e-6;
for(int i = 0;i<Width;i++){
double abs_err = fabs(h_Output[i] - KERNEL_LENGTH * 1.0);
if (abs_err > eps)
{
printf("Error! Index = %d,h_Output = %f,true value = %d\n",
i, h_Output[i], KERNEL_LENGTH);
correct = false;
}
}
printf("%s\n", correct ? "Result = PASS" : "Result = FAIL");
}
void gpuRunTiledKernel(){
convolution_1D_tiled_kernel<<<(Width+TILE_SIZE - 1)/TILE_SIZE,TILE_SIZE>>>(d_Input,d_Output,KERNEL_LENGTH,Width);
cudaDeviceSynchronize();
cudaEvent_t start;
cudaEventCreate(&start);
cudaEvent_t stop;
cudaEventCreate(&stop);
cudaEventRecord(start,NULL);
for(int i = 0;i<nIter;i++){
convolution_1D_tiled_kernel<<<(Width+TILE_SIZE - 1)/TILE_SIZE,TILE_SIZE>>>(d_Input,d_Output,KERNEL_LENGTH,Width);
}
cudaEventRecord(stop, NULL);
cudaDeviceSynchronize();
float msecTotal = 0.0f;
cudaEventElapsedTime(&msecTotal,start,stop);
float gpuTime = (msecTotal / nIter) * 0.001;
printf("Tiled Kernel Throughput = %0.4f MPixels/sec, Time= %.5f sec, Size= %u Pixels\n",
(1.0e-6 * (Width)/gpuTime),
gpuTime,
Width);
cudaMemcpy(h_Output,d_Output,Width * sizeof(float),cudaMemcpyDeviceToHost);
bool correct = true;
double eps = 1.e-6;
for(int i = 0;i<Width;i++){
double abs_err = fabs(h_Output[i] - KERNEL_LENGTH * 1.0);
if (abs_err > eps)
{
printf("Error! Index = %d,h_Output = %f,true value = %d\n",
i, h_Output[i], KERNEL_LENGTH);
correct = false;
}
}
printf("%s\n", correct ? "Result = PASS" : "Result = FAIL");
}
void gpuRunTiledCacheKernel(){
convolution_1D_tiled_caching_kernel<<<(Width+TILE_SIZE - 1)/TILE_SIZE,TILE_SIZE>>>(d_Input,d_Output,KERNEL_LENGTH,Width);
cudaDeviceSynchronize();
cudaEvent_t start;
cudaEventCreate(&start);
cudaEvent_t stop;
cudaEventCreate(&stop);
cudaEventRecord(start,NULL);
for(int i = 0;i<nIter;i++){
convolution_1D_tiled_caching_kernel<<<(Width+TILE_SIZE - 1)/TILE_SIZE,TILE_SIZE>>>(d_Input,d_Output,KERNEL_LENGTH,Width);
}
cudaEventRecord(stop, NULL);
cudaDeviceSynchronize();
float msecTotal = 0.0f;
cudaEventElapsedTime(&msecTotal,start,stop);
float gpuTime = (msecTotal / nIter) * 0.001;
printf("Tiled Cache Kernel Throughput = %0.4f MPixels/sec, Time= %.5f sec, Size= %u Pixels\n",
(1.0e-6 * (Width)/gpuTime),
gpuTime,
Width);
cudaMemcpy(h_Output,d_Output,Width * sizeof(float),cudaMemcpyDeviceToHost);
bool correct = true;
double eps = 1.e-6;
for(int i = 0;i<Width;i++){
double abs_err = fabs(h_Output[i] - KERNEL_LENGTH * 1.0);
if (abs_err > eps)
{
printf("Error! Index = %d,h_Output = %f,true value = %d\n",
i, h_Output[i], KERNEL_LENGTH);
correct = false;
}
}
printf("%s\n", correct ? "Result = PASS" : "Result = FAIL");
}
int main(){
h_Kernel = (float*)malloc(KERNEL_LENGTH * sizeof(float));
h_Input = (float*)malloc(Width * sizeof(float));
h_Output = (float*)malloc(Width * sizeof(float));
for(unsigned int i = 0;i<KERNEL_LENGTH;i++){
h_Kernel[i] = 1.0f;
}
for(unsigned int i = 0;i<Width;i++){
h_Input[i] = 1.0f;
}
cudaMalloc((void**)&d_Input,Width * sizeof(float));
cudaMalloc((void**)&d_Output,Width * sizeof(float));
cudaMalloc((void**)&d_Kernel,KERNEL_LENGTH * sizeof(float));
cudaMemcpy(d_Input,h_Input,Width * sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpy(d_Kernel,h_Kernel,KERNEL_LENGTH * sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(c_M,h_Kernel,KERNEL_LENGTH * sizeof(float));
printf("Running GPU convlution 1D ....\n");
gpuRunBasicKernel();
gpuRunConstantKernel();
gpuRunTiledKernel();
gpuRunTiledCacheKernel();
free(h_Input);
free(h_Kernel);
free(h_Output);
cudaFree(d_Input);
cudaFree(d_Kernel);
cudaFree(d_Output);
} | .file "tmpxft_0005c9da_00000000-6_convolution.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z53__device_stub__Z27convolution_1D_basic_kernelPfS_S_iiPfS_S_ii
.type _Z53__device_stub__Z27convolution_1D_basic_kernelPfS_S_iiPfS_S_ii, @function
_Z53__device_stub__Z27convolution_1D_basic_kernelPfS_S_iiPfS_S_ii:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z27convolution_1D_basic_kernelPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z53__device_stub__Z27convolution_1D_basic_kernelPfS_S_iiPfS_S_ii, .-_Z53__device_stub__Z27convolution_1D_basic_kernelPfS_S_iiPfS_S_ii
.globl _Z27convolution_1D_basic_kernelPfS_S_ii
.type _Z27convolution_1D_basic_kernelPfS_S_ii, @function
_Z27convolution_1D_basic_kernelPfS_S_ii:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z27convolution_1D_basic_kernelPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z27convolution_1D_basic_kernelPfS_S_ii, .-_Z27convolution_1D_basic_kernelPfS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Result = PASS"
.LC1:
.string "Result = FAIL"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "Basic Kernel Throughput = %0.4f MPixels/sec, Time= %.5f sec, Size= %u Pixels\n"
.align 8
.LC10:
.string "Error! Index = %d,h_Output = %f,true value = %d\n"
.section .rodata.str1.1
.LC11:
.string "%s\n"
.text
.globl _Z17gpuRunBasicKernelv
.type _Z17gpuRunBasicKernelv, @function
_Z17gpuRunBasicKernelv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $10000, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L12:
call cudaDeviceSynchronize@PLT
movq %rsp, %rdi
call cudaEventCreate@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq (%rsp), %rdi
call cudaEventRecord@PLT
movl $300, %ebx
jmp .L14
.L25:
movl $10240000, %r8d
movl $17, %ecx
movq d_Output(%rip), %rdx
movq d_Kernel(%rip), %rsi
movq d_Input(%rip), %rdi
call _Z53__device_stub__Z27convolution_1D_basic_kernelPfS_S_iiPfS_S_ii
jmp .L12
.L13:
subl $1, %ebx
je .L26
.L14:
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $10000, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L13
movl $10240000, %r8d
movl $17, %ecx
movq d_Output(%rip), %rdx
movq d_Kernel(%rip), %rsi
movq d_Input(%rip), %rdi
call _Z53__device_stub__Z27convolution_1D_basic_kernelPfS_S_iiPfS_S_ii
jmp .L13
.L26:
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
call cudaDeviceSynchronize@PLT
movl $0x00000000, 28(%rsp)
leaq 28(%rsp), %rdi
movq 8(%rsp), %rdx
movq (%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 28(%rsp), %xmm1
divss .LC3(%rip), %xmm1
cvtss2sd %xmm1, %xmm1
mulsd .LC4(%rip), %xmm1
cvtsd2ss %xmm1, %xmm1
cvtss2sd %xmm1, %xmm1
movsd .LC5(%rip), %xmm0
divsd %xmm1, %xmm0
movl $10240000, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $40960000, %edx
movq d_Output(%rip), %rsi
movq h_Output(%rip), %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
movl $0, %ebx
movl $1, %edx
leaq .LC10(%rip), %rbp
jmp .L17
.L15:
addq $1, %rbx
cmpq $10240000, %rbx
je .L27
.L17:
movq h_Output(%rip), %rax
pxor %xmm1, %xmm1
cvtss2sd (%rax,%rbx,4), %xmm1
movapd %xmm1, %xmm0
subsd .LC7(%rip), %xmm0
andpd .LC8(%rip), %xmm0
comisd .LC9(%rip), %xmm0
jbe .L15
movl $17, %ecx
movapd %xmm1, %xmm0
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %edx
jmp .L15
.L27:
testb %dl, %dl
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rax
cmovne %rax, %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z17gpuRunBasicKernelv, .-_Z17gpuRunBasicKernelv
.globl _Z54__device_stub__Z30convolution_1D_constant_kernelPfS_iiPfS_ii
.type _Z54__device_stub__Z30convolution_1D_constant_kernelPfS_iiPfS_ii, @function
_Z54__device_stub__Z30convolution_1D_constant_kernelPfS_iiPfS_ii:
.LFB2088:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z30convolution_1D_constant_kernelPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z54__device_stub__Z30convolution_1D_constant_kernelPfS_iiPfS_ii, .-_Z54__device_stub__Z30convolution_1D_constant_kernelPfS_iiPfS_ii
.globl _Z30convolution_1D_constant_kernelPfS_ii
.type _Z30convolution_1D_constant_kernelPfS_ii, @function
_Z30convolution_1D_constant_kernelPfS_ii:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z54__device_stub__Z30convolution_1D_constant_kernelPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z30convolution_1D_constant_kernelPfS_ii, .-_Z30convolution_1D_constant_kernelPfS_ii
.section .rodata.str1.8
.align 8
.LC12:
.string "Constant Kernel Throughput = %0.4f MPixels/sec, Time= %.5f sec, Size= %u Pixels\n"
.text
.globl _Z20gpuRunConstantKernelv
.type _Z20gpuRunConstantKernelv, @function
_Z20gpuRunConstantKernelv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $10000, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L51
.L38:
call cudaDeviceSynchronize@PLT
movq %rsp, %rdi
call cudaEventCreate@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq (%rsp), %rdi
call cudaEventRecord@PLT
movl $300, %ebx
jmp .L40
.L51:
movl $10240000, %ecx
movl $17, %edx
movq d_Output(%rip), %rsi
movq d_Input(%rip), %rdi
call _Z54__device_stub__Z30convolution_1D_constant_kernelPfS_iiPfS_ii
jmp .L38
.L39:
subl $1, %ebx
je .L52
.L40:
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $10000, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L39
movl $10240000, %ecx
movl $17, %edx
movq d_Output(%rip), %rsi
movq d_Input(%rip), %rdi
call _Z54__device_stub__Z30convolution_1D_constant_kernelPfS_iiPfS_ii
jmp .L39
.L52:
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
call cudaDeviceSynchronize@PLT
movl $0x00000000, 28(%rsp)
leaq 28(%rsp), %rdi
movq 8(%rsp), %rdx
movq (%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 28(%rsp), %xmm1
divss .LC3(%rip), %xmm1
cvtss2sd %xmm1, %xmm1
mulsd .LC4(%rip), %xmm1
cvtsd2ss %xmm1, %xmm1
cvtss2sd %xmm1, %xmm1
movsd .LC5(%rip), %xmm0
divsd %xmm1, %xmm0
movl $10240000, %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $40960000, %edx
movq d_Output(%rip), %rsi
movq h_Output(%rip), %rdi
call cudaMemcpy@PLT
movl $0, %ebx
movl $1, %edx
leaq .LC10(%rip), %rbp
jmp .L43
.L41:
addq $1, %rbx
cmpq $10240000, %rbx
je .L53
.L43:
movq h_Output(%rip), %rax
pxor %xmm1, %xmm1
cvtss2sd (%rax,%rbx,4), %xmm1
movapd %xmm1, %xmm0
subsd .LC7(%rip), %xmm0
andpd .LC8(%rip), %xmm0
comisd .LC9(%rip), %xmm0
jbe .L41
movl $17, %ecx
movapd %xmm1, %xmm0
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %edx
jmp .L41
.L53:
testb %dl, %dl
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rax
cmovne %rax, %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L54
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z20gpuRunConstantKernelv, .-_Z20gpuRunConstantKernelv
.globl _Z51__device_stub__Z27convolution_1D_tiled_kernelPfS_iiPfS_ii
.type _Z51__device_stub__Z27convolution_1D_tiled_kernelPfS_iiPfS_ii, @function
_Z51__device_stub__Z27convolution_1D_tiled_kernelPfS_iiPfS_ii:
.LFB2090:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L59
.L55:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L60
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L59:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z27convolution_1D_tiled_kernelPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L55
.L60:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z51__device_stub__Z27convolution_1D_tiled_kernelPfS_iiPfS_ii, .-_Z51__device_stub__Z27convolution_1D_tiled_kernelPfS_iiPfS_ii
.globl _Z27convolution_1D_tiled_kernelPfS_ii
.type _Z27convolution_1D_tiled_kernelPfS_ii, @function
_Z27convolution_1D_tiled_kernelPfS_ii:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z27convolution_1D_tiled_kernelPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z27convolution_1D_tiled_kernelPfS_ii, .-_Z27convolution_1D_tiled_kernelPfS_ii
.section .rodata.str1.8
.align 8
.LC13:
.string "Tiled Kernel Throughput = %0.4f MPixels/sec, Time= %.5f sec, Size= %u Pixels\n"
.text
.globl _Z17gpuRunTiledKernelv
.type _Z17gpuRunTiledKernelv, @function
_Z17gpuRunTiledKernelv:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $10000, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L77
.L64:
call cudaDeviceSynchronize@PLT
movq %rsp, %rdi
call cudaEventCreate@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq (%rsp), %rdi
call cudaEventRecord@PLT
movl $300, %ebx
jmp .L66
.L77:
movl $10240000, %ecx
movl $17, %edx
movq d_Output(%rip), %rsi
movq d_Input(%rip), %rdi
call _Z51__device_stub__Z27convolution_1D_tiled_kernelPfS_iiPfS_ii
jmp .L64
.L65:
subl $1, %ebx
je .L78
.L66:
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $10000, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L65
movl $10240000, %ecx
movl $17, %edx
movq d_Output(%rip), %rsi
movq d_Input(%rip), %rdi
call _Z51__device_stub__Z27convolution_1D_tiled_kernelPfS_iiPfS_ii
jmp .L65
.L78:
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
call cudaDeviceSynchronize@PLT
movl $0x00000000, 28(%rsp)
leaq 28(%rsp), %rdi
movq 8(%rsp), %rdx
movq (%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 28(%rsp), %xmm1
divss .LC3(%rip), %xmm1
cvtss2sd %xmm1, %xmm1
mulsd .LC4(%rip), %xmm1
cvtsd2ss %xmm1, %xmm1
cvtss2sd %xmm1, %xmm1
movsd .LC5(%rip), %xmm0
divsd %xmm1, %xmm0
movl $10240000, %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $40960000, %edx
movq d_Output(%rip), %rsi
movq h_Output(%rip), %rdi
call cudaMemcpy@PLT
movl $0, %ebx
movl $1, %edx
leaq .LC10(%rip), %rbp
jmp .L69
.L67:
addq $1, %rbx
cmpq $10240000, %rbx
je .L79
.L69:
movq h_Output(%rip), %rax
pxor %xmm1, %xmm1
cvtss2sd (%rax,%rbx,4), %xmm1
movapd %xmm1, %xmm0
subsd .LC7(%rip), %xmm0
andpd .LC8(%rip), %xmm0
comisd .LC9(%rip), %xmm0
jbe .L67
movl $17, %ecx
movapd %xmm1, %xmm0
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %edx
jmp .L67
.L79:
testb %dl, %dl
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rax
cmovne %rax, %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L80
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L80:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z17gpuRunTiledKernelv, .-_Z17gpuRunTiledKernelv
.globl _Z59__device_stub__Z35convolution_1D_tiled_caching_kernelPfS_iiPfS_ii
.type _Z59__device_stub__Z35convolution_1D_tiled_caching_kernelPfS_iiPfS_ii, @function
_Z59__device_stub__Z35convolution_1D_tiled_caching_kernelPfS_iiPfS_ii:
.LFB2092:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L85
.L81:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L86
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L85:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z35convolution_1D_tiled_caching_kernelPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L81
.L86:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2092:
.size _Z59__device_stub__Z35convolution_1D_tiled_caching_kernelPfS_iiPfS_ii, .-_Z59__device_stub__Z35convolution_1D_tiled_caching_kernelPfS_iiPfS_ii
.globl _Z35convolution_1D_tiled_caching_kernelPfS_ii
.type _Z35convolution_1D_tiled_caching_kernelPfS_ii, @function
_Z35convolution_1D_tiled_caching_kernelPfS_ii:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z59__device_stub__Z35convolution_1D_tiled_caching_kernelPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _Z35convolution_1D_tiled_caching_kernelPfS_ii, .-_Z35convolution_1D_tiled_caching_kernelPfS_ii
.section .rodata.str1.8
.align 8
.LC14:
.string "Tiled Cache Kernel Throughput = %0.4f MPixels/sec, Time= %.5f sec, Size= %u Pixels\n"
.text
.globl _Z22gpuRunTiledCacheKernelv
.type _Z22gpuRunTiledCacheKernelv, @function
_Z22gpuRunTiledCacheKernelv:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $10000, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L103
.L90:
call cudaDeviceSynchronize@PLT
movq %rsp, %rdi
call cudaEventCreate@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq (%rsp), %rdi
call cudaEventRecord@PLT
movl $300, %ebx
jmp .L92
.L103:
movl $10240000, %ecx
movl $17, %edx
movq d_Output(%rip), %rsi
movq d_Input(%rip), %rdi
call _Z59__device_stub__Z35convolution_1D_tiled_caching_kernelPfS_iiPfS_ii
jmp .L90
.L91:
subl $1, %ebx
je .L104
.L92:
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $10000, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L91
movl $10240000, %ecx
movl $17, %edx
movq d_Output(%rip), %rsi
movq d_Input(%rip), %rdi
call _Z59__device_stub__Z35convolution_1D_tiled_caching_kernelPfS_iiPfS_ii
jmp .L91
.L104:
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
call cudaDeviceSynchronize@PLT
movl $0x00000000, 28(%rsp)
leaq 28(%rsp), %rdi
movq 8(%rsp), %rdx
movq (%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 28(%rsp), %xmm1
divss .LC3(%rip), %xmm1
cvtss2sd %xmm1, %xmm1
mulsd .LC4(%rip), %xmm1
cvtsd2ss %xmm1, %xmm1
cvtss2sd %xmm1, %xmm1
movsd .LC5(%rip), %xmm0
divsd %xmm1, %xmm0
movl $10240000, %edx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $40960000, %edx
movq d_Output(%rip), %rsi
movq h_Output(%rip), %rdi
call cudaMemcpy@PLT
movl $0, %ebx
movl $1, %edx
leaq .LC10(%rip), %rbp
jmp .L95
.L93:
addq $1, %rbx
cmpq $10240000, %rbx
je .L105
.L95:
movq h_Output(%rip), %rax
pxor %xmm1, %xmm1
cvtss2sd (%rax,%rbx,4), %xmm1
movapd %xmm1, %xmm0
subsd .LC7(%rip), %xmm0
andpd .LC8(%rip), %xmm0
comisd .LC9(%rip), %xmm0
jbe .L93
movl $17, %ecx
movapd %xmm1, %xmm0
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %edx
jmp .L93
.L105:
testb %dl, %dl
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rax
cmovne %rax, %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L106
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L106:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z22gpuRunTiledCacheKernelv, .-_Z22gpuRunTiledCacheKernelv
.section .rodata.str1.8
.align 8
.LC16:
.string "Running GPU convlution 1D ....\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $68, %edi
call malloc@PLT
movq %rax, h_Kernel(%rip)
movl $40960000, %edi
call malloc@PLT
movq %rax, h_Input(%rip)
movl $40960000, %edi
call malloc@PLT
movq %rax, h_Output(%rip)
movl $0, %eax
movss .LC15(%rip), %xmm0
.L108:
movq h_Kernel(%rip), %rdx
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $68, %rax
jne .L108
movl $0, %eax
movss .LC15(%rip), %xmm0
.L109:
movq h_Input(%rip), %rdx
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $40960000, %rax
jne .L109
movl $40960000, %esi
leaq d_Input(%rip), %rdi
call cudaMalloc@PLT
movl $40960000, %esi
leaq d_Output(%rip), %rdi
call cudaMalloc@PLT
movl $68, %esi
leaq d_Kernel(%rip), %rdi
call cudaMalloc@PLT
movl $1, %ecx
movl $40960000, %edx
movq h_Input(%rip), %rsi
movq d_Input(%rip), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $68, %edx
movq h_Kernel(%rip), %rsi
movq d_Kernel(%rip), %rdi
call cudaMemcpy@PLT
movl $1, %r8d
movl $0, %ecx
movl $68, %edx
movq h_Kernel(%rip), %rsi
leaq _ZL3c_M(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z17gpuRunBasicKernelv
call _Z20gpuRunConstantKernelv
call _Z17gpuRunTiledKernelv
call _Z22gpuRunTiledCacheKernelv
movq h_Input(%rip), %rdi
call free@PLT
movq h_Kernel(%rip), %rdi
call free@PLT
movq h_Output(%rip), %rdi
call free@PLT
movq d_Input(%rip), %rdi
call cudaFree@PLT
movq d_Kernel(%rip), %rdi
call cudaFree@PLT
movq d_Output(%rip), %rdi
call cudaFree@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC17:
.string "_Z35convolution_1D_tiled_caching_kernelPfS_ii"
.align 8
.LC18:
.string "_Z27convolution_1D_tiled_kernelPfS_ii"
.align 8
.LC19:
.string "_Z30convolution_1D_constant_kernelPfS_ii"
.align 8
.LC20:
.string "_Z27convolution_1D_basic_kernelPfS_S_ii"
.section .rodata.str1.1
.LC21:
.string "c_M"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2095:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z35convolution_1D_tiled_caching_kernelPfS_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z27convolution_1D_tiled_kernelPfS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z30convolution_1D_constant_kernelPfS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _Z27convolution_1D_basic_kernelPfS_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $68, %r9d
movl $0, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _ZL3c_M(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2095:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl d_Output
.bss
.align 8
.type d_Output, @object
.size d_Output, 8
d_Output:
.zero 8
.globl d_Input
.align 8
.type d_Input, @object
.size d_Input, 8
d_Input:
.zero 8
.globl d_Kernel
.align 8
.type d_Kernel, @object
.size d_Kernel, 8
d_Kernel:
.zero 8
.globl h_Output
.align 8
.type h_Output, @object
.size h_Output, 8
h_Output:
.zero 8
.globl h_Input
.align 8
.type h_Input, @object
.size h_Input, 8
h_Input:
.zero 8
.globl h_Kernel
.align 8
.type h_Kernel, @object
.size h_Kernel, 8
h_Kernel:
.zero 8
.local _ZL3c_M
.comm _ZL3c_M,68,32
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 1133903872
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long -755914244
.long 1062232653
.align 8
.LC5:
.long 1202590843
.long 1076132577
.align 8
.LC7:
.long 0
.long 1076953088
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC8:
.long -1
.long 2147483647
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC9:
.long -1598689907
.long 1051772663
.section .rodata.cst4
.align 4
.LC15:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#define KERNEL_RADIUS 8
#define KERNEL_LENGTH (2 * KERNEL_RADIUS + 1)
#define TILE_SIZE 1024
__constant__ float c_M[KERNEL_LENGTH];
const int Width = 10240000;
const int nIter = 300;
float * h_Kernel,*h_Input,*h_Output;
float * d_Kernel, *d_Input, * d_Output;
__global__ void convolution_1D_basic_kernel(float* N, float* g_M, float* P,int Mask_Width, int Width){
int i = blockIdx.x * blockDim.x + threadIdx.x;
float Pvalue = 0;
int N_start_point = i - (Mask_Width/2);
for(int j = 0;j<Mask_Width;j++){
if(N_start_point + j>=0 && N_start_point + j <Width){
Pvalue += N[N_start_point + j] * g_M[j];
}else if(N_start_point + j<0){
Pvalue += N[0] * g_M[j];
}else{
Pvalue += N[Width - 1] * g_M[j];
}
}
P[i] = Pvalue;
}
__global__ void convolution_1D_constant_kernel(float * N,float* P,int Mask_Width,int Width){
int i = blockIdx.x * blockDim.x + threadIdx.x;
float Pvalue = 0;
int N_start_point = i - (Mask_Width/2);
for(int j = 0;j<Mask_Width;j++){
if(N_start_point + j>=0 && N_start_point + j <Width){
Pvalue += N[N_start_point + j] * c_M[j];
}else if(N_start_point + j < 0){
Pvalue += N[0] * c_M[j];
}else{
Pvalue += N[Width - 1] * c_M[j];
}
}
P[i] = Pvalue;
}
__global__ void convolution_1D_tiled_kernel(float* N, float* P,int Mask_Width, int Width){
int i = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ float N_ds[TILE_SIZE + KERNEL_LENGTH-1];
int n = Mask_Width/2;
int halo_index_left = (blockIdx.x - 1) * blockDim.x + threadIdx.x;
if(threadIdx.x >= blockDim.x - n){
N_ds[threadIdx.x - (blockDim.x - n)] = (halo_index_left<0) ? N[0]:N[halo_index_left];
}
N_ds[n+threadIdx.x] = N[blockIdx.x * blockDim.x + threadIdx.x];
int halo_index_right = (blockIdx.x + 1) * blockDim.x + threadIdx.x;
if(threadIdx.x < n){
N_ds[n + blockDim.x + threadIdx.x] = (halo_index_right >= Width) ? N[Width - 1]:N[halo_index_right];
}
__syncthreads();
float Pvalue = 0;
for(int j = 0;j<Mask_Width;j++){
Pvalue += N_ds[threadIdx.x + j] * c_M[j];
}
P[i] = Pvalue;
}
__global__ void convolution_1D_tiled_caching_kernel(float* N, float* P, int Mask_Width, int Width){
int i = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ float N_ds[TILE_SIZE];
N_ds[threadIdx.x] = N[i];
__syncthreads();
int This_tile_start_point = blockIdx.x * blockDim.x;
int Next_tile_start_point = (blockIdx.x + 1) * blockDim.x;
int N_start_point = i - (Mask_Width/2);
float Pvalue = 0;
for(int j = 0;j<Mask_Width;j++){
int N_index = N_start_point + j;
if(N_index >=0 && N_index<Width){
if((N_index>=This_tile_start_point) && (N_index< Next_tile_start_point)){
Pvalue += N_ds[threadIdx.x+ j - (Mask_Width/2)] * c_M[j];
}else{
Pvalue += N[N_index];
}
}
}
P[i] = Pvalue;
}
void gpuRunBasicKernel(){
convolution_1D_basic_kernel<<<(Width+TILE_SIZE - 1)/TILE_SIZE,TILE_SIZE>>>(d_Input,d_Kernel,d_Output,KERNEL_LENGTH,Width);
cudaDeviceSynchronize();
cudaEvent_t start;
cudaEventCreate(&start);
cudaEvent_t stop;
cudaEventCreate(&stop);
cudaEventRecord(start,NULL);
for(int i = 0;i<nIter;i++){
convolution_1D_basic_kernel<<<(Width+TILE_SIZE - 1)/TILE_SIZE,TILE_SIZE>>>(d_Input,d_Kernel,d_Output,KERNEL_LENGTH,Width);
}
cudaEventRecord(stop, NULL);
cudaDeviceSynchronize();
float msecTotal = 0.0f;
cudaEventElapsedTime(&msecTotal,start,stop);
float gpuTime = (msecTotal / nIter) * 0.001;
printf("Basic Kernel Throughput = %0.4f MPixels/sec, Time= %.5f sec, Size= %u Pixels\n",
(1.0e-6 * (Width)/gpuTime),
gpuTime,
Width);
cudaMemcpy(h_Output,d_Output,Width * sizeof(float),cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
bool correct = true;
double eps = 1.e-6;
for(int i = 0;i<Width;i++){
double abs_err = fabs(h_Output[i] - KERNEL_LENGTH * 1.0);
if (abs_err > eps)
{
printf("Error! Index = %d,h_Output = %f,true value = %d\n",
i, h_Output[i], KERNEL_LENGTH);
correct = false;
}
}
printf("%s\n", correct ? "Result = PASS" : "Result = FAIL");
}
void gpuRunConstantKernel(){
convolution_1D_constant_kernel<<<(Width+TILE_SIZE - 1)/TILE_SIZE,TILE_SIZE>>>(d_Input,d_Output,KERNEL_LENGTH,Width);
cudaDeviceSynchronize();
cudaEvent_t start;
cudaEventCreate(&start);
cudaEvent_t stop;
cudaEventCreate(&stop);
cudaEventRecord(start,NULL);
for(int i = 0;i<nIter;i++){
convolution_1D_constant_kernel<<<(Width+TILE_SIZE - 1)/TILE_SIZE,TILE_SIZE>>>(d_Input,d_Output,KERNEL_LENGTH,Width);
}
cudaEventRecord(stop, NULL);
cudaDeviceSynchronize();
float msecTotal = 0.0f;
cudaEventElapsedTime(&msecTotal,start,stop);
float gpuTime = (msecTotal / nIter) * 0.001;
printf("Constant Kernel Throughput = %0.4f MPixels/sec, Time= %.5f sec, Size= %u Pixels\n",
(1.0e-6 * (Width)/gpuTime),
gpuTime,
Width);
cudaMemcpy(h_Output,d_Output,Width * sizeof(float),cudaMemcpyDeviceToHost);
bool correct = true;
double eps = 1.e-6;
for(int i = 0;i<Width;i++){
double abs_err = fabs(h_Output[i] - KERNEL_LENGTH * 1.0);
if (abs_err > eps)
{
printf("Error! Index = %d,h_Output = %f,true value = %d\n",
i, h_Output[i], KERNEL_LENGTH);
correct = false;
}
}
printf("%s\n", correct ? "Result = PASS" : "Result = FAIL");
}
void gpuRunTiledKernel(){
convolution_1D_tiled_kernel<<<(Width+TILE_SIZE - 1)/TILE_SIZE,TILE_SIZE>>>(d_Input,d_Output,KERNEL_LENGTH,Width);
cudaDeviceSynchronize();
cudaEvent_t start;
cudaEventCreate(&start);
cudaEvent_t stop;
cudaEventCreate(&stop);
cudaEventRecord(start,NULL);
for(int i = 0;i<nIter;i++){
convolution_1D_tiled_kernel<<<(Width+TILE_SIZE - 1)/TILE_SIZE,TILE_SIZE>>>(d_Input,d_Output,KERNEL_LENGTH,Width);
}
cudaEventRecord(stop, NULL);
cudaDeviceSynchronize();
float msecTotal = 0.0f;
cudaEventElapsedTime(&msecTotal,start,stop);
float gpuTime = (msecTotal / nIter) * 0.001;
printf("Tiled Kernel Throughput = %0.4f MPixels/sec, Time= %.5f sec, Size= %u Pixels\n",
(1.0e-6 * (Width)/gpuTime),
gpuTime,
Width);
cudaMemcpy(h_Output,d_Output,Width * sizeof(float),cudaMemcpyDeviceToHost);
bool correct = true;
double eps = 1.e-6;
for(int i = 0;i<Width;i++){
double abs_err = fabs(h_Output[i] - KERNEL_LENGTH * 1.0);
if (abs_err > eps)
{
printf("Error! Index = %d,h_Output = %f,true value = %d\n",
i, h_Output[i], KERNEL_LENGTH);
correct = false;
}
}
printf("%s\n", correct ? "Result = PASS" : "Result = FAIL");
}
void gpuRunTiledCacheKernel(){
convolution_1D_tiled_caching_kernel<<<(Width+TILE_SIZE - 1)/TILE_SIZE,TILE_SIZE>>>(d_Input,d_Output,KERNEL_LENGTH,Width);
cudaDeviceSynchronize();
cudaEvent_t start;
cudaEventCreate(&start);
cudaEvent_t stop;
cudaEventCreate(&stop);
cudaEventRecord(start,NULL);
for(int i = 0;i<nIter;i++){
convolution_1D_tiled_caching_kernel<<<(Width+TILE_SIZE - 1)/TILE_SIZE,TILE_SIZE>>>(d_Input,d_Output,KERNEL_LENGTH,Width);
}
cudaEventRecord(stop, NULL);
cudaDeviceSynchronize();
float msecTotal = 0.0f;
cudaEventElapsedTime(&msecTotal,start,stop);
float gpuTime = (msecTotal / nIter) * 0.001;
printf("Tiled Cache Kernel Throughput = %0.4f MPixels/sec, Time= %.5f sec, Size= %u Pixels\n",
(1.0e-6 * (Width)/gpuTime),
gpuTime,
Width);
cudaMemcpy(h_Output,d_Output,Width * sizeof(float),cudaMemcpyDeviceToHost);
bool correct = true;
double eps = 1.e-6;
for(int i = 0;i<Width;i++){
double abs_err = fabs(h_Output[i] - KERNEL_LENGTH * 1.0);
if (abs_err > eps)
{
printf("Error! Index = %d,h_Output = %f,true value = %d\n",
i, h_Output[i], KERNEL_LENGTH);
correct = false;
}
}
printf("%s\n", correct ? "Result = PASS" : "Result = FAIL");
}
int main(){
h_Kernel = (float*)malloc(KERNEL_LENGTH * sizeof(float));
h_Input = (float*)malloc(Width * sizeof(float));
h_Output = (float*)malloc(Width * sizeof(float));
for(unsigned int i = 0;i<KERNEL_LENGTH;i++){
h_Kernel[i] = 1.0f;
}
for(unsigned int i = 0;i<Width;i++){
h_Input[i] = 1.0f;
}
cudaMalloc((void**)&d_Input,Width * sizeof(float));
cudaMalloc((void**)&d_Output,Width * sizeof(float));
cudaMalloc((void**)&d_Kernel,KERNEL_LENGTH * sizeof(float));
cudaMemcpy(d_Input,h_Input,Width * sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpy(d_Kernel,h_Kernel,KERNEL_LENGTH * sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(c_M,h_Kernel,KERNEL_LENGTH * sizeof(float));
printf("Running GPU convlution 1D ....\n");
gpuRunBasicKernel();
gpuRunConstantKernel();
gpuRunTiledKernel();
gpuRunTiledCacheKernel();
free(h_Input);
free(h_Kernel);
free(h_Output);
cudaFree(d_Input);
cudaFree(d_Kernel);
cudaFree(d_Output);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define KERNEL_RADIUS 8
#define KERNEL_LENGTH (2 * KERNEL_RADIUS + 1)
#define TILE_SIZE 1024
__constant__ float c_M[KERNEL_LENGTH];
const int Width = 10240000;
const int nIter = 300;
float * h_Kernel,*h_Input,*h_Output;
float * d_Kernel, *d_Input, * d_Output;
__global__ void convolution_1D_basic_kernel(float* N, float* g_M, float* P,int Mask_Width, int Width){
int i = blockIdx.x * blockDim.x + threadIdx.x;
float Pvalue = 0;
int N_start_point = i - (Mask_Width/2);
for(int j = 0;j<Mask_Width;j++){
if(N_start_point + j>=0 && N_start_point + j <Width){
Pvalue += N[N_start_point + j] * g_M[j];
}else if(N_start_point + j<0){
Pvalue += N[0] * g_M[j];
}else{
Pvalue += N[Width - 1] * g_M[j];
}
}
P[i] = Pvalue;
}
__global__ void convolution_1D_constant_kernel(float * N,float* P,int Mask_Width,int Width){
int i = blockIdx.x * blockDim.x + threadIdx.x;
float Pvalue = 0;
int N_start_point = i - (Mask_Width/2);
for(int j = 0;j<Mask_Width;j++){
if(N_start_point + j>=0 && N_start_point + j <Width){
Pvalue += N[N_start_point + j] * c_M[j];
}else if(N_start_point + j < 0){
Pvalue += N[0] * c_M[j];
}else{
Pvalue += N[Width - 1] * c_M[j];
}
}
P[i] = Pvalue;
}
__global__ void convolution_1D_tiled_kernel(float* N, float* P,int Mask_Width, int Width){
int i = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ float N_ds[TILE_SIZE + KERNEL_LENGTH-1];
int n = Mask_Width/2;
int halo_index_left = (blockIdx.x - 1) * blockDim.x + threadIdx.x;
if(threadIdx.x >= blockDim.x - n){
N_ds[threadIdx.x - (blockDim.x - n)] = (halo_index_left<0) ? N[0]:N[halo_index_left];
}
N_ds[n+threadIdx.x] = N[blockIdx.x * blockDim.x + threadIdx.x];
int halo_index_right = (blockIdx.x + 1) * blockDim.x + threadIdx.x;
if(threadIdx.x < n){
N_ds[n + blockDim.x + threadIdx.x] = (halo_index_right >= Width) ? N[Width - 1]:N[halo_index_right];
}
__syncthreads();
float Pvalue = 0;
for(int j = 0;j<Mask_Width;j++){
Pvalue += N_ds[threadIdx.x + j] * c_M[j];
}
P[i] = Pvalue;
}
__global__ void convolution_1D_tiled_caching_kernel(float* N, float* P, int Mask_Width, int Width){
int i = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ float N_ds[TILE_SIZE];
N_ds[threadIdx.x] = N[i];
__syncthreads();
int This_tile_start_point = blockIdx.x * blockDim.x;
int Next_tile_start_point = (blockIdx.x + 1) * blockDim.x;
int N_start_point = i - (Mask_Width/2);
float Pvalue = 0;
for(int j = 0;j<Mask_Width;j++){
int N_index = N_start_point + j;
if(N_index >=0 && N_index<Width){
if((N_index>=This_tile_start_point) && (N_index< Next_tile_start_point)){
Pvalue += N_ds[threadIdx.x+ j - (Mask_Width/2)] * c_M[j];
}else{
Pvalue += N[N_index];
}
}
}
P[i] = Pvalue;
}
void gpuRunBasicKernel(){
convolution_1D_basic_kernel<<<(Width+TILE_SIZE - 1)/TILE_SIZE,TILE_SIZE>>>(d_Input,d_Kernel,d_Output,KERNEL_LENGTH,Width);
hipDeviceSynchronize();
hipEvent_t start;
hipEventCreate(&start);
hipEvent_t stop;
hipEventCreate(&stop);
hipEventRecord(start,NULL);
for(int i = 0;i<nIter;i++){
convolution_1D_basic_kernel<<<(Width+TILE_SIZE - 1)/TILE_SIZE,TILE_SIZE>>>(d_Input,d_Kernel,d_Output,KERNEL_LENGTH,Width);
}
hipEventRecord(stop, NULL);
hipDeviceSynchronize();
float msecTotal = 0.0f;
hipEventElapsedTime(&msecTotal,start,stop);
float gpuTime = (msecTotal / nIter) * 0.001;
printf("Basic Kernel Throughput = %0.4f MPixels/sec, Time= %.5f sec, Size= %u Pixels\n",
(1.0e-6 * (Width)/gpuTime),
gpuTime,
Width);
hipMemcpy(h_Output,d_Output,Width * sizeof(float),hipMemcpyDeviceToHost);
hipDeviceSynchronize();
bool correct = true;
double eps = 1.e-6;
for(int i = 0;i<Width;i++){
double abs_err = fabs(h_Output[i] - KERNEL_LENGTH * 1.0);
if (abs_err > eps)
{
printf("Error! Index = %d,h_Output = %f,true value = %d\n",
i, h_Output[i], KERNEL_LENGTH);
correct = false;
}
}
printf("%s\n", correct ? "Result = PASS" : "Result = FAIL");
}
void gpuRunConstantKernel(){
convolution_1D_constant_kernel<<<(Width+TILE_SIZE - 1)/TILE_SIZE,TILE_SIZE>>>(d_Input,d_Output,KERNEL_LENGTH,Width);
hipDeviceSynchronize();
hipEvent_t start;
hipEventCreate(&start);
hipEvent_t stop;
hipEventCreate(&stop);
hipEventRecord(start,NULL);
for(int i = 0;i<nIter;i++){
convolution_1D_constant_kernel<<<(Width+TILE_SIZE - 1)/TILE_SIZE,TILE_SIZE>>>(d_Input,d_Output,KERNEL_LENGTH,Width);
}
hipEventRecord(stop, NULL);
hipDeviceSynchronize();
float msecTotal = 0.0f;
hipEventElapsedTime(&msecTotal,start,stop);
float gpuTime = (msecTotal / nIter) * 0.001;
printf("Constant Kernel Throughput = %0.4f MPixels/sec, Time= %.5f sec, Size= %u Pixels\n",
(1.0e-6 * (Width)/gpuTime),
gpuTime,
Width);
hipMemcpy(h_Output,d_Output,Width * sizeof(float),hipMemcpyDeviceToHost);
bool correct = true;
double eps = 1.e-6;
for(int i = 0;i<Width;i++){
double abs_err = fabs(h_Output[i] - KERNEL_LENGTH * 1.0);
if (abs_err > eps)
{
printf("Error! Index = %d,h_Output = %f,true value = %d\n",
i, h_Output[i], KERNEL_LENGTH);
correct = false;
}
}
printf("%s\n", correct ? "Result = PASS" : "Result = FAIL");
}
void gpuRunTiledKernel(){
convolution_1D_tiled_kernel<<<(Width+TILE_SIZE - 1)/TILE_SIZE,TILE_SIZE>>>(d_Input,d_Output,KERNEL_LENGTH,Width);
hipDeviceSynchronize();
hipEvent_t start;
hipEventCreate(&start);
hipEvent_t stop;
hipEventCreate(&stop);
hipEventRecord(start,NULL);
for(int i = 0;i<nIter;i++){
convolution_1D_tiled_kernel<<<(Width+TILE_SIZE - 1)/TILE_SIZE,TILE_SIZE>>>(d_Input,d_Output,KERNEL_LENGTH,Width);
}
hipEventRecord(stop, NULL);
hipDeviceSynchronize();
float msecTotal = 0.0f;
hipEventElapsedTime(&msecTotal,start,stop);
float gpuTime = (msecTotal / nIter) * 0.001;
printf("Tiled Kernel Throughput = %0.4f MPixels/sec, Time= %.5f sec, Size= %u Pixels\n",
(1.0e-6 * (Width)/gpuTime),
gpuTime,
Width);
hipMemcpy(h_Output,d_Output,Width * sizeof(float),hipMemcpyDeviceToHost);
bool correct = true;
double eps = 1.e-6;
for(int i = 0;i<Width;i++){
double abs_err = fabs(h_Output[i] - KERNEL_LENGTH * 1.0);
if (abs_err > eps)
{
printf("Error! Index = %d,h_Output = %f,true value = %d\n",
i, h_Output[i], KERNEL_LENGTH);
correct = false;
}
}
printf("%s\n", correct ? "Result = PASS" : "Result = FAIL");
}
void gpuRunTiledCacheKernel(){
convolution_1D_tiled_caching_kernel<<<(Width+TILE_SIZE - 1)/TILE_SIZE,TILE_SIZE>>>(d_Input,d_Output,KERNEL_LENGTH,Width);
hipDeviceSynchronize();
hipEvent_t start;
hipEventCreate(&start);
hipEvent_t stop;
hipEventCreate(&stop);
hipEventRecord(start,NULL);
for(int i = 0;i<nIter;i++){
convolution_1D_tiled_caching_kernel<<<(Width+TILE_SIZE - 1)/TILE_SIZE,TILE_SIZE>>>(d_Input,d_Output,KERNEL_LENGTH,Width);
}
hipEventRecord(stop, NULL);
hipDeviceSynchronize();
float msecTotal = 0.0f;
hipEventElapsedTime(&msecTotal,start,stop);
float gpuTime = (msecTotal / nIter) * 0.001;
printf("Tiled Cache Kernel Throughput = %0.4f MPixels/sec, Time= %.5f sec, Size= %u Pixels\n",
(1.0e-6 * (Width)/gpuTime),
gpuTime,
Width);
hipMemcpy(h_Output,d_Output,Width * sizeof(float),hipMemcpyDeviceToHost);
bool correct = true;
double eps = 1.e-6;
for(int i = 0;i<Width;i++){
double abs_err = fabs(h_Output[i] - KERNEL_LENGTH * 1.0);
if (abs_err > eps)
{
printf("Error! Index = %d,h_Output = %f,true value = %d\n",
i, h_Output[i], KERNEL_LENGTH);
correct = false;
}
}
printf("%s\n", correct ? "Result = PASS" : "Result = FAIL");
}
int main(){
h_Kernel = (float*)malloc(KERNEL_LENGTH * sizeof(float));
h_Input = (float*)malloc(Width * sizeof(float));
h_Output = (float*)malloc(Width * sizeof(float));
for(unsigned int i = 0;i<KERNEL_LENGTH;i++){
h_Kernel[i] = 1.0f;
}
for(unsigned int i = 0;i<Width;i++){
h_Input[i] = 1.0f;
}
hipMalloc((void**)&d_Input,Width * sizeof(float));
hipMalloc((void**)&d_Output,Width * sizeof(float));
hipMalloc((void**)&d_Kernel,KERNEL_LENGTH * sizeof(float));
hipMemcpy(d_Input,h_Input,Width * sizeof(float),hipMemcpyHostToDevice);
hipMemcpy(d_Kernel,h_Kernel,KERNEL_LENGTH * sizeof(float),hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(c_M),h_Kernel,KERNEL_LENGTH * sizeof(float));
printf("Running GPU convlution 1D ....\n");
gpuRunBasicKernel();
gpuRunConstantKernel();
gpuRunTiledKernel();
gpuRunTiledCacheKernel();
free(h_Input);
free(h_Kernel);
free(h_Output);
hipFree(d_Input);
hipFree(d_Kernel);
hipFree(d_Output);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define KERNEL_RADIUS 8
#define KERNEL_LENGTH (2 * KERNEL_RADIUS + 1)
#define TILE_SIZE 1024
__constant__ float c_M[KERNEL_LENGTH];
const int Width = 10240000;
const int nIter = 300;
float * h_Kernel,*h_Input,*h_Output;
float * d_Kernel, *d_Input, * d_Output;
__global__ void convolution_1D_basic_kernel(float* N, float* g_M, float* P,int Mask_Width, int Width){
int i = blockIdx.x * blockDim.x + threadIdx.x;
float Pvalue = 0;
int N_start_point = i - (Mask_Width/2);
for(int j = 0;j<Mask_Width;j++){
if(N_start_point + j>=0 && N_start_point + j <Width){
Pvalue += N[N_start_point + j] * g_M[j];
}else if(N_start_point + j<0){
Pvalue += N[0] * g_M[j];
}else{
Pvalue += N[Width - 1] * g_M[j];
}
}
P[i] = Pvalue;
}
__global__ void convolution_1D_constant_kernel(float * N,float* P,int Mask_Width,int Width){
int i = blockIdx.x * blockDim.x + threadIdx.x;
float Pvalue = 0;
int N_start_point = i - (Mask_Width/2);
for(int j = 0;j<Mask_Width;j++){
if(N_start_point + j>=0 && N_start_point + j <Width){
Pvalue += N[N_start_point + j] * c_M[j];
}else if(N_start_point + j < 0){
Pvalue += N[0] * c_M[j];
}else{
Pvalue += N[Width - 1] * c_M[j];
}
}
P[i] = Pvalue;
}
__global__ void convolution_1D_tiled_kernel(float* N, float* P,int Mask_Width, int Width){
int i = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ float N_ds[TILE_SIZE + KERNEL_LENGTH-1];
int n = Mask_Width/2;
int halo_index_left = (blockIdx.x - 1) * blockDim.x + threadIdx.x;
if(threadIdx.x >= blockDim.x - n){
N_ds[threadIdx.x - (blockDim.x - n)] = (halo_index_left<0) ? N[0]:N[halo_index_left];
}
N_ds[n+threadIdx.x] = N[blockIdx.x * blockDim.x + threadIdx.x];
int halo_index_right = (blockIdx.x + 1) * blockDim.x + threadIdx.x;
if(threadIdx.x < n){
N_ds[n + blockDim.x + threadIdx.x] = (halo_index_right >= Width) ? N[Width - 1]:N[halo_index_right];
}
__syncthreads();
float Pvalue = 0;
for(int j = 0;j<Mask_Width;j++){
Pvalue += N_ds[threadIdx.x + j] * c_M[j];
}
P[i] = Pvalue;
}
__global__ void convolution_1D_tiled_caching_kernel(float* N, float* P, int Mask_Width, int Width){
int i = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ float N_ds[TILE_SIZE];
N_ds[threadIdx.x] = N[i];
__syncthreads();
int This_tile_start_point = blockIdx.x * blockDim.x;
int Next_tile_start_point = (blockIdx.x + 1) * blockDim.x;
int N_start_point = i - (Mask_Width/2);
float Pvalue = 0;
for(int j = 0;j<Mask_Width;j++){
int N_index = N_start_point + j;
if(N_index >=0 && N_index<Width){
if((N_index>=This_tile_start_point) && (N_index< Next_tile_start_point)){
Pvalue += N_ds[threadIdx.x+ j - (Mask_Width/2)] * c_M[j];
}else{
Pvalue += N[N_index];
}
}
}
P[i] = Pvalue;
}
void gpuRunBasicKernel(){
convolution_1D_basic_kernel<<<(Width+TILE_SIZE - 1)/TILE_SIZE,TILE_SIZE>>>(d_Input,d_Kernel,d_Output,KERNEL_LENGTH,Width);
hipDeviceSynchronize();
hipEvent_t start;
hipEventCreate(&start);
hipEvent_t stop;
hipEventCreate(&stop);
hipEventRecord(start,NULL);
for(int i = 0;i<nIter;i++){
convolution_1D_basic_kernel<<<(Width+TILE_SIZE - 1)/TILE_SIZE,TILE_SIZE>>>(d_Input,d_Kernel,d_Output,KERNEL_LENGTH,Width);
}
hipEventRecord(stop, NULL);
hipDeviceSynchronize();
float msecTotal = 0.0f;
hipEventElapsedTime(&msecTotal,start,stop);
float gpuTime = (msecTotal / nIter) * 0.001;
printf("Basic Kernel Throughput = %0.4f MPixels/sec, Time= %.5f sec, Size= %u Pixels\n",
(1.0e-6 * (Width)/gpuTime),
gpuTime,
Width);
hipMemcpy(h_Output,d_Output,Width * sizeof(float),hipMemcpyDeviceToHost);
hipDeviceSynchronize();
bool correct = true;
double eps = 1.e-6;
for(int i = 0;i<Width;i++){
double abs_err = fabs(h_Output[i] - KERNEL_LENGTH * 1.0);
if (abs_err > eps)
{
printf("Error! Index = %d,h_Output = %f,true value = %d\n",
i, h_Output[i], KERNEL_LENGTH);
correct = false;
}
}
printf("%s\n", correct ? "Result = PASS" : "Result = FAIL");
}
void gpuRunConstantKernel(){
convolution_1D_constant_kernel<<<(Width+TILE_SIZE - 1)/TILE_SIZE,TILE_SIZE>>>(d_Input,d_Output,KERNEL_LENGTH,Width);
hipDeviceSynchronize();
hipEvent_t start;
hipEventCreate(&start);
hipEvent_t stop;
hipEventCreate(&stop);
hipEventRecord(start,NULL);
for(int i = 0;i<nIter;i++){
convolution_1D_constant_kernel<<<(Width+TILE_SIZE - 1)/TILE_SIZE,TILE_SIZE>>>(d_Input,d_Output,KERNEL_LENGTH,Width);
}
hipEventRecord(stop, NULL);
hipDeviceSynchronize();
float msecTotal = 0.0f;
hipEventElapsedTime(&msecTotal,start,stop);
float gpuTime = (msecTotal / nIter) * 0.001;
printf("Constant Kernel Throughput = %0.4f MPixels/sec, Time= %.5f sec, Size= %u Pixels\n",
(1.0e-6 * (Width)/gpuTime),
gpuTime,
Width);
hipMemcpy(h_Output,d_Output,Width * sizeof(float),hipMemcpyDeviceToHost);
bool correct = true;
double eps = 1.e-6;
for(int i = 0;i<Width;i++){
double abs_err = fabs(h_Output[i] - KERNEL_LENGTH * 1.0);
if (abs_err > eps)
{
printf("Error! Index = %d,h_Output = %f,true value = %d\n",
i, h_Output[i], KERNEL_LENGTH);
correct = false;
}
}
printf("%s\n", correct ? "Result = PASS" : "Result = FAIL");
}
void gpuRunTiledKernel(){
convolution_1D_tiled_kernel<<<(Width+TILE_SIZE - 1)/TILE_SIZE,TILE_SIZE>>>(d_Input,d_Output,KERNEL_LENGTH,Width);
hipDeviceSynchronize();
hipEvent_t start;
hipEventCreate(&start);
hipEvent_t stop;
hipEventCreate(&stop);
hipEventRecord(start,NULL);
for(int i = 0;i<nIter;i++){
convolution_1D_tiled_kernel<<<(Width+TILE_SIZE - 1)/TILE_SIZE,TILE_SIZE>>>(d_Input,d_Output,KERNEL_LENGTH,Width);
}
hipEventRecord(stop, NULL);
hipDeviceSynchronize();
float msecTotal = 0.0f;
hipEventElapsedTime(&msecTotal,start,stop);
float gpuTime = (msecTotal / nIter) * 0.001;
printf("Tiled Kernel Throughput = %0.4f MPixels/sec, Time= %.5f sec, Size= %u Pixels\n",
(1.0e-6 * (Width)/gpuTime),
gpuTime,
Width);
hipMemcpy(h_Output,d_Output,Width * sizeof(float),hipMemcpyDeviceToHost);
bool correct = true;
double eps = 1.e-6;
for(int i = 0;i<Width;i++){
double abs_err = fabs(h_Output[i] - KERNEL_LENGTH * 1.0);
if (abs_err > eps)
{
printf("Error! Index = %d,h_Output = %f,true value = %d\n",
i, h_Output[i], KERNEL_LENGTH);
correct = false;
}
}
printf("%s\n", correct ? "Result = PASS" : "Result = FAIL");
}
void gpuRunTiledCacheKernel(){
convolution_1D_tiled_caching_kernel<<<(Width+TILE_SIZE - 1)/TILE_SIZE,TILE_SIZE>>>(d_Input,d_Output,KERNEL_LENGTH,Width);
hipDeviceSynchronize();
hipEvent_t start;
hipEventCreate(&start);
hipEvent_t stop;
hipEventCreate(&stop);
hipEventRecord(start,NULL);
for(int i = 0;i<nIter;i++){
convolution_1D_tiled_caching_kernel<<<(Width+TILE_SIZE - 1)/TILE_SIZE,TILE_SIZE>>>(d_Input,d_Output,KERNEL_LENGTH,Width);
}
hipEventRecord(stop, NULL);
hipDeviceSynchronize();
float msecTotal = 0.0f;
hipEventElapsedTime(&msecTotal,start,stop);
float gpuTime = (msecTotal / nIter) * 0.001;
printf("Tiled Cache Kernel Throughput = %0.4f MPixels/sec, Time= %.5f sec, Size= %u Pixels\n",
(1.0e-6 * (Width)/gpuTime),
gpuTime,
Width);
hipMemcpy(h_Output,d_Output,Width * sizeof(float),hipMemcpyDeviceToHost);
bool correct = true;
double eps = 1.e-6;
for(int i = 0;i<Width;i++){
double abs_err = fabs(h_Output[i] - KERNEL_LENGTH * 1.0);
if (abs_err > eps)
{
printf("Error! Index = %d,h_Output = %f,true value = %d\n",
i, h_Output[i], KERNEL_LENGTH);
correct = false;
}
}
printf("%s\n", correct ? "Result = PASS" : "Result = FAIL");
}
int main(){
h_Kernel = (float*)malloc(KERNEL_LENGTH * sizeof(float));
h_Input = (float*)malloc(Width * sizeof(float));
h_Output = (float*)malloc(Width * sizeof(float));
for(unsigned int i = 0;i<KERNEL_LENGTH;i++){
h_Kernel[i] = 1.0f;
}
for(unsigned int i = 0;i<Width;i++){
h_Input[i] = 1.0f;
}
hipMalloc((void**)&d_Input,Width * sizeof(float));
hipMalloc((void**)&d_Output,Width * sizeof(float));
hipMalloc((void**)&d_Kernel,KERNEL_LENGTH * sizeof(float));
hipMemcpy(d_Input,h_Input,Width * sizeof(float),hipMemcpyHostToDevice);
hipMemcpy(d_Kernel,h_Kernel,KERNEL_LENGTH * sizeof(float),hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(c_M),h_Kernel,KERNEL_LENGTH * sizeof(float));
printf("Running GPU convlution 1D ....\n");
gpuRunBasicKernel();
gpuRunConstantKernel();
gpuRunTiledKernel();
gpuRunTiledCacheKernel();
free(h_Input);
free(h_Kernel);
free(h_Output);
hipFree(d_Input);
hipFree(d_Kernel);
hipFree(d_Output);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z27convolution_1D_basic_kernelPfS_S_ii
.globl _Z27convolution_1D_basic_kernelPfS_S_ii
.p2align 8
.type _Z27convolution_1D_basic_kernelPfS_S_ii,@function
_Z27convolution_1D_basic_kernelPfS_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_cmp_lt_i32 s3, 1
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_cbranch_scc1 .LBB0_7
s_clause 0x1
s_load_b32 s8, s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x0
s_lshr_b32 s2, s3, 31
v_mov_b32_e32 v3, 0
s_add_i32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s2, s2, 1
v_subrev_nc_u32_e32 v2, s2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_mov_b32_e32 v0, v3
s_waitcnt lgkmcnt(0)
s_ashr_i32 s9, s8, 31
s_lshl_b64 s[10:11], s[8:9], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s2, s4, s10
s_addc_u32 s10, s5, s11
s_add_u32 s9, s2, -4
s_addc_u32 s10, s10, -1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
global_load_b32 v4, v[4:5], off
s_add_i32 s3, s3, -1
v_add_nc_u32_e32 v2, 1, v2
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_cmp_eq_u32 s3, 0
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v0, v4, v6
s_cbranch_scc1 .LBB0_8
.LBB0_3:
v_cmp_gt_i32_e32 vcc_lo, 0, v2
v_cmp_le_i32_e64 s2, s8, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s12, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s12
s_cbranch_execz .LBB0_5
s_load_b32 s11, s[6:7], 0x0
v_mov_b32_e32 v4, s5
v_mov_b32_e32 v6, s4
v_cmp_gt_i32_e32 vcc_lo, 0, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v5, s10, v4, vcc_lo
v_cndmask_b32_e32 v4, s9, v6, vcc_lo
.LBB0_5:
s_or_saveexec_b32 s2, s2
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v6, s11
s_xor_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_2
s_load_b32 s11, s[6:7], 0x0
v_lshlrev_b64 v[4:5], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v6, s11
s_branch .LBB0_2
.LBB0_7:
v_mov_b32_e32 v0, 0
.LBB0_8:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z27convolution_1D_basic_kernelPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z27convolution_1D_basic_kernelPfS_S_ii, .Lfunc_end0-_Z27convolution_1D_basic_kernelPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z30convolution_1D_constant_kernelPfS_ii
.globl _Z30convolution_1D_constant_kernelPfS_ii
.p2align 8
.type _Z30convolution_1D_constant_kernelPfS_ii,@function
_Z30convolution_1D_constant_kernelPfS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_cmp_lt_i32 s3, 1
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_cbranch_scc1 .LBB1_11
s_clause 0x1
s_load_b32 s4, s[0:1], 0x14
s_load_b64 s[6:7], s[0:1], 0x0
s_lshr_b32 s2, s3, 31
v_mov_b32_e32 v3, 0
s_add_i32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s2, s2, 1
v_subrev_nc_u32_e32 v2, s2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_mov_b32_e32 v0, v3
s_waitcnt lgkmcnt(0)
s_ashr_i32 s5, s4, 31
s_lshl_b64 s[8:9], s[4:5], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s2, s6, s8
s_addc_u32 s5, s7, s9
s_add_u32 s8, s2, -4
s_addc_u32 s9, s5, -1
s_getpc_b64 s[10:11]
s_add_u32 s10, s10, c_M@rel32@lo+4
s_addc_u32 s11, s11, c_M@rel32@hi+12
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_3
.p2align 6
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v0, v0, v4
s_add_i32 s3, s3, -1
v_add_nc_u32_e32 v2, 1, v2
s_add_u32 s10, s10, 4
s_addc_u32 s11, s11, 0
s_cmp_eq_u32 s3, 0
s_cbranch_scc1 .LBB1_12
.LBB1_3:
v_cmp_gt_i32_e32 vcc_lo, 0, v2
v_cmp_le_i32_e64 s2, s4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_or_b32 s2, vcc_lo, s2
s_waitcnt lgkmcnt(0)
s_and_saveexec_b32 s5, s2
s_xor_b32 s2, exec_lo, s5
s_cbranch_execz .LBB1_9
s_load_b32 s5, s[10:11], 0x0
s_mov_b32 s12, exec_lo
v_cmpx_lt_i32_e32 -1, v2
s_xor_b32 s12, exec_lo, s12
s_cbranch_execz .LBB1_6
s_load_b32 s13, s[8:9], 0x0
s_waitcnt lgkmcnt(0)
v_mul_f32_e64 v4, s13, s5
.LBB1_6:
s_and_not1_saveexec_b32 s12, s12
s_cbranch_execz .LBB1_8
s_load_b32 s13, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
v_mul_f32_e64 v4, s13, s5
.LBB1_8:
s_or_b32 exec_lo, exec_lo, s12
.LBB1_9:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB1_2
v_lshlrev_b64 v[4:5], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_load_b32 s5, s[10:11], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mul_f32_e32 v4, s5, v4
s_branch .LBB1_2
.LBB1_11:
v_mov_b32_e32 v0, 0
.LBB1_12:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z30convolution_1D_constant_kernelPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z30convolution_1D_constant_kernelPfS_ii, .Lfunc_end1-_Z30convolution_1D_constant_kernelPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z27convolution_1D_tiled_kernelPfS_ii
.globl _Z27convolution_1D_tiled_kernelPfS_ii
.p2align 8
.type _Z27convolution_1D_tiled_kernelPfS_ii,@function
_Z27convolution_1D_tiled_kernelPfS_ii:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x10
s_load_b32 s5, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s6, s4, 31
s_and_b32 s5, s5, 0xffff
s_add_i32 s6, s4, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s6, s6, 1
s_sub_i32 s7, s5, s6
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_le_u32_e32 vcc_lo, s7, v0
s_and_saveexec_b32 s7, vcc_lo
s_cbranch_execz .LBB2_2
s_add_i32 s8, s15, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s8, s5, v[0:1]
v_mov_b32_e32 v2, 0
v_max_i32_e32 v1, 0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_load_b32 v1, v[1:2], off
v_add_nc_u32_e32 v2, s6, v0
v_subrev_nc_u32_e32 v2, s5, v2
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v2, 2, v2
s_waitcnt vmcnt(0)
ds_store_b32 v2, v1
.LBB2_2:
s_or_b32 exec_lo, exec_lo, s7
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
v_mov_b32_e32 v2, 0
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v3, v[3:4], off
v_add_lshl_u32 v4, s6, v0, 2
s_waitcnt vmcnt(0)
ds_store_b32 v4, v3
v_cmpx_gt_u32_e64 s6, v0
s_cbranch_execz .LBB2_4
s_load_b32 s8, s[0:1], 0x14
s_add_i32 s15, s15, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s15, s5, v[0:1]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_ashr_i32 s9, s8, 31
v_add_co_u32 v6, vcc_lo, s2, v4
s_lshl_b64 s[10:11], s[8:9], 2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v5, vcc_lo
s_add_u32 s2, s2, s10
v_cmp_gt_i32_e32 vcc_lo, s8, v3
s_addc_u32 s3, s3, s11
s_add_u32 s2, s2, -4
s_addc_u32 s3, s3, -1
s_add_i32 s5, s5, s6
v_cndmask_b32_e32 v4, s3, v4, vcc_lo
v_cndmask_b32_e32 v3, s2, v6, vcc_lo
global_load_b32 v3, v[3:4], off
v_add_lshl_u32 v4, s5, v0, 2
s_waitcnt vmcnt(0)
ds_store_b32 v4, v3
.LBB2_4:
s_or_b32 exec_lo, exec_lo, s7
s_cmp_lt_i32 s4, 1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB2_7
v_lshlrev_b32_e32 v0, 2, v0
v_mov_b32_e32 v2, 0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, c_M@rel32@lo+4
s_addc_u32 s3, s3, c_M@rel32@hi+12
.LBB2_6:
ds_load_b32 v3, v0
s_load_b32 s5, s[2:3], 0x0
s_add_i32 s4, s4, -1
v_add_nc_u32_e32 v0, 4, v0
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s4, 0
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, s5, v3
s_cbranch_scc0 .LBB2_6
.LBB2_7:
s_load_b64 s[0:1], s[0:1], 0x8
v_ashrrev_i32_e32 v4, 31, v1
v_mov_b32_e32 v3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z27convolution_1D_tiled_kernelPfS_ii
.amdhsa_group_segment_fixed_size 4160
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z27convolution_1D_tiled_kernelPfS_ii, .Lfunc_end2-_Z27convolution_1D_tiled_kernelPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z35convolution_1D_tiled_caching_kernelPfS_ii
.globl _Z35convolution_1D_tiled_caching_kernelPfS_ii
.p2align 8
.type _Z35convolution_1D_tiled_caching_kernelPfS_ii,@function
_Z35convolution_1D_tiled_caching_kernelPfS_ii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_cmp_lt_i32 s8, 1
s_mul_i32 s3, s15, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v1, s3, v0
v_lshlrev_b32_e32 v0, 2, v0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
ds_store_b32 v0, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB3_9
s_load_b32 s9, s[0:1], 0x14
s_lshr_b32 s6, s8, 31
v_mov_b32_e32 v4, 0
s_add_i32 s6, s8, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s6, s6, 1
s_lshl_b32 s7, s6, 2
v_subrev_nc_u32_e32 v3, s6, v1
v_subrev_nc_u32_e32 v5, s7, v0
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, c_M@rel32@lo+4
s_addc_u32 s7, s7, c_M@rel32@hi+12
v_mov_b32_e32 v0, v4
s_add_i32 s10, s15, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s10, s10, s2
s_set_inst_prefetch_distance 0x1
s_branch .LBB3_4
.p2align 6
.LBB3_2:
s_or_b32 exec_lo, exec_lo, s2
.LBB3_3:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s11
s_add_i32 s8, s8, -1
v_add_nc_u32_e32 v3, 1, v3
v_add_nc_u32_e32 v5, 4, v5
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB3_10
.LBB3_4:
v_cmp_lt_i32_e32 vcc_lo, -1, v3
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s2, s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s11, s2
s_cbranch_execz .LBB3_3
v_cmp_gt_i32_e32 vcc_lo, s3, v3
v_cmp_le_i32_e64 s2, s10, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s12, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s12
s_cbranch_execz .LBB3_7
v_lshlrev_b64 v[6:7], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_b32 v6, v[6:7], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v6
.LBB3_7:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB3_2
ds_load_b32 v6, v5
s_load_b32 s12, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v0, s12, v6
s_branch .LBB3_2
.LBB3_9:
v_mov_b32_e32 v0, 0
.LBB3_10:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z35convolution_1D_tiled_caching_kernelPfS_ii
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z35convolution_1D_tiled_caching_kernelPfS_ii, .Lfunc_end3-_Z35convolution_1D_tiled_caching_kernelPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected c_M
.type c_M,@object
.section .bss,"aw",@nobits
.globl c_M
.p2align 4, 0x0
c_M:
.zero 68
.size c_M, 68
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym c_M
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
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.name: _Z35convolution_1D_tiled_caching_kernelPfS_ii
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amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define KERNEL_RADIUS 8
#define KERNEL_LENGTH (2 * KERNEL_RADIUS + 1)
#define TILE_SIZE 1024
__constant__ float c_M[KERNEL_LENGTH];
const int Width = 10240000;
const int nIter = 300;
float * h_Kernel,*h_Input,*h_Output;
float * d_Kernel, *d_Input, * d_Output;
__global__ void convolution_1D_basic_kernel(float* N, float* g_M, float* P,int Mask_Width, int Width){
int i = blockIdx.x * blockDim.x + threadIdx.x;
float Pvalue = 0;
int N_start_point = i - (Mask_Width/2);
for(int j = 0;j<Mask_Width;j++){
if(N_start_point + j>=0 && N_start_point + j <Width){
Pvalue += N[N_start_point + j] * g_M[j];
}else if(N_start_point + j<0){
Pvalue += N[0] * g_M[j];
}else{
Pvalue += N[Width - 1] * g_M[j];
}
}
P[i] = Pvalue;
}
__global__ void convolution_1D_constant_kernel(float * N,float* P,int Mask_Width,int Width){
int i = blockIdx.x * blockDim.x + threadIdx.x;
float Pvalue = 0;
int N_start_point = i - (Mask_Width/2);
for(int j = 0;j<Mask_Width;j++){
if(N_start_point + j>=0 && N_start_point + j <Width){
Pvalue += N[N_start_point + j] * c_M[j];
}else if(N_start_point + j < 0){
Pvalue += N[0] * c_M[j];
}else{
Pvalue += N[Width - 1] * c_M[j];
}
}
P[i] = Pvalue;
}
__global__ void convolution_1D_tiled_kernel(float* N, float* P,int Mask_Width, int Width){
int i = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ float N_ds[TILE_SIZE + KERNEL_LENGTH-1];
int n = Mask_Width/2;
int halo_index_left = (blockIdx.x - 1) * blockDim.x + threadIdx.x;
if(threadIdx.x >= blockDim.x - n){
N_ds[threadIdx.x - (blockDim.x - n)] = (halo_index_left<0) ? N[0]:N[halo_index_left];
}
N_ds[n+threadIdx.x] = N[blockIdx.x * blockDim.x + threadIdx.x];
int halo_index_right = (blockIdx.x + 1) * blockDim.x + threadIdx.x;
if(threadIdx.x < n){
N_ds[n + blockDim.x + threadIdx.x] = (halo_index_right >= Width) ? N[Width - 1]:N[halo_index_right];
}
__syncthreads();
float Pvalue = 0;
for(int j = 0;j<Mask_Width;j++){
Pvalue += N_ds[threadIdx.x + j] * c_M[j];
}
P[i] = Pvalue;
}
__global__ void convolution_1D_tiled_caching_kernel(float* N, float* P, int Mask_Width, int Width){
int i = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ float N_ds[TILE_SIZE];
N_ds[threadIdx.x] = N[i];
__syncthreads();
int This_tile_start_point = blockIdx.x * blockDim.x;
int Next_tile_start_point = (blockIdx.x + 1) * blockDim.x;
int N_start_point = i - (Mask_Width/2);
float Pvalue = 0;
for(int j = 0;j<Mask_Width;j++){
int N_index = N_start_point + j;
if(N_index >=0 && N_index<Width){
if((N_index>=This_tile_start_point) && (N_index< Next_tile_start_point)){
Pvalue += N_ds[threadIdx.x+ j - (Mask_Width/2)] * c_M[j];
}else{
Pvalue += N[N_index];
}
}
}
P[i] = Pvalue;
}
void gpuRunBasicKernel(){
convolution_1D_basic_kernel<<<(Width+TILE_SIZE - 1)/TILE_SIZE,TILE_SIZE>>>(d_Input,d_Kernel,d_Output,KERNEL_LENGTH,Width);
hipDeviceSynchronize();
hipEvent_t start;
hipEventCreate(&start);
hipEvent_t stop;
hipEventCreate(&stop);
hipEventRecord(start,NULL);
for(int i = 0;i<nIter;i++){
convolution_1D_basic_kernel<<<(Width+TILE_SIZE - 1)/TILE_SIZE,TILE_SIZE>>>(d_Input,d_Kernel,d_Output,KERNEL_LENGTH,Width);
}
hipEventRecord(stop, NULL);
hipDeviceSynchronize();
float msecTotal = 0.0f;
hipEventElapsedTime(&msecTotal,start,stop);
float gpuTime = (msecTotal / nIter) * 0.001;
printf("Basic Kernel Throughput = %0.4f MPixels/sec, Time= %.5f sec, Size= %u Pixels\n",
(1.0e-6 * (Width)/gpuTime),
gpuTime,
Width);
hipMemcpy(h_Output,d_Output,Width * sizeof(float),hipMemcpyDeviceToHost);
hipDeviceSynchronize();
bool correct = true;
double eps = 1.e-6;
for(int i = 0;i<Width;i++){
double abs_err = fabs(h_Output[i] - KERNEL_LENGTH * 1.0);
if (abs_err > eps)
{
printf("Error! Index = %d,h_Output = %f,true value = %d\n",
i, h_Output[i], KERNEL_LENGTH);
correct = false;
}
}
printf("%s\n", correct ? "Result = PASS" : "Result = FAIL");
}
void gpuRunConstantKernel(){
convolution_1D_constant_kernel<<<(Width+TILE_SIZE - 1)/TILE_SIZE,TILE_SIZE>>>(d_Input,d_Output,KERNEL_LENGTH,Width);
hipDeviceSynchronize();
hipEvent_t start;
hipEventCreate(&start);
hipEvent_t stop;
hipEventCreate(&stop);
hipEventRecord(start,NULL);
for(int i = 0;i<nIter;i++){
convolution_1D_constant_kernel<<<(Width+TILE_SIZE - 1)/TILE_SIZE,TILE_SIZE>>>(d_Input,d_Output,KERNEL_LENGTH,Width);
}
hipEventRecord(stop, NULL);
hipDeviceSynchronize();
float msecTotal = 0.0f;
hipEventElapsedTime(&msecTotal,start,stop);
float gpuTime = (msecTotal / nIter) * 0.001;
printf("Constant Kernel Throughput = %0.4f MPixels/sec, Time= %.5f sec, Size= %u Pixels\n",
(1.0e-6 * (Width)/gpuTime),
gpuTime,
Width);
hipMemcpy(h_Output,d_Output,Width * sizeof(float),hipMemcpyDeviceToHost);
bool correct = true;
double eps = 1.e-6;
for(int i = 0;i<Width;i++){
double abs_err = fabs(h_Output[i] - KERNEL_LENGTH * 1.0);
if (abs_err > eps)
{
printf("Error! Index = %d,h_Output = %f,true value = %d\n",
i, h_Output[i], KERNEL_LENGTH);
correct = false;
}
}
printf("%s\n", correct ? "Result = PASS" : "Result = FAIL");
}
void gpuRunTiledKernel(){
convolution_1D_tiled_kernel<<<(Width+TILE_SIZE - 1)/TILE_SIZE,TILE_SIZE>>>(d_Input,d_Output,KERNEL_LENGTH,Width);
hipDeviceSynchronize();
hipEvent_t start;
hipEventCreate(&start);
hipEvent_t stop;
hipEventCreate(&stop);
hipEventRecord(start,NULL);
for(int i = 0;i<nIter;i++){
convolution_1D_tiled_kernel<<<(Width+TILE_SIZE - 1)/TILE_SIZE,TILE_SIZE>>>(d_Input,d_Output,KERNEL_LENGTH,Width);
}
hipEventRecord(stop, NULL);
hipDeviceSynchronize();
float msecTotal = 0.0f;
hipEventElapsedTime(&msecTotal,start,stop);
float gpuTime = (msecTotal / nIter) * 0.001;
printf("Tiled Kernel Throughput = %0.4f MPixels/sec, Time= %.5f sec, Size= %u Pixels\n",
(1.0e-6 * (Width)/gpuTime),
gpuTime,
Width);
hipMemcpy(h_Output,d_Output,Width * sizeof(float),hipMemcpyDeviceToHost);
bool correct = true;
double eps = 1.e-6;
for(int i = 0;i<Width;i++){
double abs_err = fabs(h_Output[i] - KERNEL_LENGTH * 1.0);
if (abs_err > eps)
{
printf("Error! Index = %d,h_Output = %f,true value = %d\n",
i, h_Output[i], KERNEL_LENGTH);
correct = false;
}
}
printf("%s\n", correct ? "Result = PASS" : "Result = FAIL");
}
void gpuRunTiledCacheKernel(){
convolution_1D_tiled_caching_kernel<<<(Width+TILE_SIZE - 1)/TILE_SIZE,TILE_SIZE>>>(d_Input,d_Output,KERNEL_LENGTH,Width);
hipDeviceSynchronize();
hipEvent_t start;
hipEventCreate(&start);
hipEvent_t stop;
hipEventCreate(&stop);
hipEventRecord(start,NULL);
for(int i = 0;i<nIter;i++){
convolution_1D_tiled_caching_kernel<<<(Width+TILE_SIZE - 1)/TILE_SIZE,TILE_SIZE>>>(d_Input,d_Output,KERNEL_LENGTH,Width);
}
hipEventRecord(stop, NULL);
hipDeviceSynchronize();
float msecTotal = 0.0f;
hipEventElapsedTime(&msecTotal,start,stop);
float gpuTime = (msecTotal / nIter) * 0.001;
printf("Tiled Cache Kernel Throughput = %0.4f MPixels/sec, Time= %.5f sec, Size= %u Pixels\n",
(1.0e-6 * (Width)/gpuTime),
gpuTime,
Width);
hipMemcpy(h_Output,d_Output,Width * sizeof(float),hipMemcpyDeviceToHost);
bool correct = true;
double eps = 1.e-6;
for(int i = 0;i<Width;i++){
double abs_err = fabs(h_Output[i] - KERNEL_LENGTH * 1.0);
if (abs_err > eps)
{
printf("Error! Index = %d,h_Output = %f,true value = %d\n",
i, h_Output[i], KERNEL_LENGTH);
correct = false;
}
}
printf("%s\n", correct ? "Result = PASS" : "Result = FAIL");
}
int main(){
h_Kernel = (float*)malloc(KERNEL_LENGTH * sizeof(float));
h_Input = (float*)malloc(Width * sizeof(float));
h_Output = (float*)malloc(Width * sizeof(float));
for(unsigned int i = 0;i<KERNEL_LENGTH;i++){
h_Kernel[i] = 1.0f;
}
for(unsigned int i = 0;i<Width;i++){
h_Input[i] = 1.0f;
}
hipMalloc((void**)&d_Input,Width * sizeof(float));
hipMalloc((void**)&d_Output,Width * sizeof(float));
hipMalloc((void**)&d_Kernel,KERNEL_LENGTH * sizeof(float));
hipMemcpy(d_Input,h_Input,Width * sizeof(float),hipMemcpyHostToDevice);
hipMemcpy(d_Kernel,h_Kernel,KERNEL_LENGTH * sizeof(float),hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(c_M),h_Kernel,KERNEL_LENGTH * sizeof(float));
printf("Running GPU convlution 1D ....\n");
gpuRunBasicKernel();
gpuRunConstantKernel();
gpuRunTiledKernel();
gpuRunTiledCacheKernel();
free(h_Input);
free(h_Kernel);
free(h_Output);
hipFree(d_Input);
hipFree(d_Kernel);
hipFree(d_Output);
} | .text
.file "convolution.hip"
.globl _Z42__device_stub__convolution_1D_basic_kernelPfS_S_ii # -- Begin function _Z42__device_stub__convolution_1D_basic_kernelPfS_S_ii
.p2align 4, 0x90
.type _Z42__device_stub__convolution_1D_basic_kernelPfS_S_ii,@function
_Z42__device_stub__convolution_1D_basic_kernelPfS_S_ii: # @_Z42__device_stub__convolution_1D_basic_kernelPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z27convolution_1D_basic_kernelPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z42__device_stub__convolution_1D_basic_kernelPfS_S_ii, .Lfunc_end0-_Z42__device_stub__convolution_1D_basic_kernelPfS_S_ii
.cfi_endproc
# -- End function
.globl _Z45__device_stub__convolution_1D_constant_kernelPfS_ii # -- Begin function _Z45__device_stub__convolution_1D_constant_kernelPfS_ii
.p2align 4, 0x90
.type _Z45__device_stub__convolution_1D_constant_kernelPfS_ii,@function
_Z45__device_stub__convolution_1D_constant_kernelPfS_ii: # @_Z45__device_stub__convolution_1D_constant_kernelPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z30convolution_1D_constant_kernelPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z45__device_stub__convolution_1D_constant_kernelPfS_ii, .Lfunc_end1-_Z45__device_stub__convolution_1D_constant_kernelPfS_ii
.cfi_endproc
# -- End function
.globl _Z42__device_stub__convolution_1D_tiled_kernelPfS_ii # -- Begin function _Z42__device_stub__convolution_1D_tiled_kernelPfS_ii
.p2align 4, 0x90
.type _Z42__device_stub__convolution_1D_tiled_kernelPfS_ii,@function
_Z42__device_stub__convolution_1D_tiled_kernelPfS_ii: # @_Z42__device_stub__convolution_1D_tiled_kernelPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z27convolution_1D_tiled_kernelPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z42__device_stub__convolution_1D_tiled_kernelPfS_ii, .Lfunc_end2-_Z42__device_stub__convolution_1D_tiled_kernelPfS_ii
.cfi_endproc
# -- End function
.globl _Z50__device_stub__convolution_1D_tiled_caching_kernelPfS_ii # -- Begin function _Z50__device_stub__convolution_1D_tiled_caching_kernelPfS_ii
.p2align 4, 0x90
.type _Z50__device_stub__convolution_1D_tiled_caching_kernelPfS_ii,@function
_Z50__device_stub__convolution_1D_tiled_caching_kernelPfS_ii: # @_Z50__device_stub__convolution_1D_tiled_caching_kernelPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z35convolution_1D_tiled_caching_kernelPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z50__device_stub__convolution_1D_tiled_caching_kernelPfS_ii, .Lfunc_end3-_Z50__device_stub__convolution_1D_tiled_caching_kernelPfS_ii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z17gpuRunBasicKernelv
.LCPI4_0:
.long 0x43960000 # float 300
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI4_1:
.quad 0x3f50624dd2f1a9fc # double 0.001
.LCPI4_2:
.quad 0x40247ae147ae147b # double 10.24
.LCPI4_3:
.quad 0xc031000000000000 # double -17
.LCPI4_5:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI4_4:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl _Z17gpuRunBasicKernelv
.p2align 4, 0x90
.type _Z17gpuRunBasicKernelv,@function
_Z17gpuRunBasicKernelv: # @_Z17gpuRunBasicKernelv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294968320, %rbx # imm = 0x100000400
leaq 8976(%rbx), %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_2
# %bb.1:
movq d_Input(%rip), %rax
movq d_Kernel(%rip), %rcx
movq d_Output(%rip), %rdx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movq %rdx, 64(%rsp)
movl $17, 8(%rsp)
movl $10240000, (%rsp) # imm = 0x9C4000
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z27convolution_1D_basic_kernelPfS_S_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_2:
callq hipDeviceSynchronize
leaq 8(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $300, %r12d # imm = 0x12C
leaq 8976(%rbx), %r14
leaq 24(%rsp), %r13
leaq 16(%rsp), %rbp
leaq 96(%rsp), %r15
jmp .LBB4_3
.p2align 4, 0x90
.LBB4_5: # in Loop: Header=BB4_3 Depth=1
decl %r12d
je .LBB4_6
.LBB4_3: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_5
# %bb.4: # in Loop: Header=BB4_3 Depth=1
movq d_Input(%rip), %rax
movq d_Kernel(%rip), %rcx
movq d_Output(%rip), %rdx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movq %rdx, 64(%rsp)
movl $17, 92(%rsp)
movl $10240000, 88(%rsp) # imm = 0x9C4000
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 92(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z27convolution_1D_basic_kernelPfS_S_ii, %edi
movq %r15, %r9
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB4_5
.LBB4_6:
movq (%rsp), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq hipEventRecord
callq hipDeviceSynchronize
movl $0, 96(%rsp)
movq 8(%rsp), %rsi
movq (%rsp), %rdx
leaq 96(%rsp), %rdi
callq hipEventElapsedTime
movss 96(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI4_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
mulsd .LCPI4_1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm1
movsd .LCPI4_2(%rip), %xmm0 # xmm0 = mem[0],zero
divsd %xmm1, %xmm0
movl $.L.str, %edi
movl $10240000, %esi # imm = 0x9C4000
movb $2, %al
callq printf
movq h_Output(%rip), %rdi
movq d_Output(%rip), %rsi
movl $40960000, %edx # imm = 0x2710000
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
movb $1, %al
movsd .LCPI4_3(%rip), %xmm2 # xmm2 = mem[0],zero
movapd .LCPI4_4(%rip), %xmm3 # xmm3 = [NaN,NaN]
movsd .LCPI4_5(%rip), %xmm4 # xmm4 = mem[0],zero
jmp .LBB4_7
.p2align 4, 0x90
.LBB4_9: # in Loop: Header=BB4_7 Depth=1
incq %rbx
cmpq $10240000, %rbx # imm = 0x9C4000
je .LBB4_10
.LBB4_7: # =>This Inner Loop Header: Depth=1
movq h_Output(%rip), %rcx
movss (%rcx,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movaps %xmm0, %xmm1
addsd %xmm2, %xmm1
andpd %xmm3, %xmm1
ucomisd %xmm4, %xmm1
jbe .LBB4_9
# %bb.8: # in Loop: Header=BB4_7 Depth=1
movl $.L.str.1, %edi
movl %ebx, %esi
movl $17, %edx
movb $1, %al
callq printf
movsd .LCPI4_5(%rip), %xmm4 # xmm4 = mem[0],zero
movapd .LCPI4_4(%rip), %xmm3 # xmm3 = [NaN,NaN]
movsd .LCPI4_3(%rip), %xmm2 # xmm2 = mem[0],zero
xorl %eax, %eax
jmp .LBB4_9
.LBB4_10:
testb $1, %al
movl $.L.str.4, %eax
movl $.L.str.3, %edi
cmoveq %rax, %rdi
callq puts@PLT
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z17gpuRunBasicKernelv, .Lfunc_end4-_Z17gpuRunBasicKernelv
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z20gpuRunConstantKernelv
.LCPI5_0:
.long 0x43960000 # float 300
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI5_1:
.quad 0x3f50624dd2f1a9fc # double 0.001
.LCPI5_2:
.quad 0x40247ae147ae147b # double 10.24
.LCPI5_3:
.quad 0xc031000000000000 # double -17
.LCPI5_5:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI5_4:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl _Z20gpuRunConstantKernelv
.p2align 4, 0x90
.type _Z20gpuRunConstantKernelv,@function
_Z20gpuRunConstantKernelv: # @_Z20gpuRunConstantKernelv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294968320, %rbx # imm = 0x100000400
leaq 8976(%rbx), %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_2
# %bb.1:
movq d_Input(%rip), %rax
movq d_Output(%rip), %rcx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movl $17, 16(%rsp)
movl $10240000, 8(%rsp) # imm = 0x9C4000
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z30convolution_1D_constant_kernelPfS_ii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_2:
callq hipDeviceSynchronize
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $300, %r12d # imm = 0x12C
leaq 8976(%rbx), %r14
leaq 32(%rsp), %r13
leaq 24(%rsp), %rbp
leaq 96(%rsp), %r15
jmp .LBB5_3
.p2align 4, 0x90
.LBB5_5: # in Loop: Header=BB5_3 Depth=1
decl %r12d
je .LBB5_6
.LBB5_3: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_5
# %bb.4: # in Loop: Header=BB5_3 Depth=1
movq d_Input(%rip), %rax
movq d_Output(%rip), %rcx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movl $17, 92(%rsp)
movl $10240000, 88(%rsp) # imm = 0x9C4000
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 92(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z30convolution_1D_constant_kernelPfS_ii, %edi
movq %r15, %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB5_5
.LBB5_6:
movq 8(%rsp), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq hipEventRecord
callq hipDeviceSynchronize
movl $0, 96(%rsp)
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 96(%rsp), %rdi
callq hipEventElapsedTime
movss 96(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI5_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
mulsd .LCPI5_1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm1
movsd .LCPI5_2(%rip), %xmm0 # xmm0 = mem[0],zero
divsd %xmm1, %xmm0
movl $.L.str.5, %edi
movl $10240000, %esi # imm = 0x9C4000
movb $2, %al
callq printf
movq h_Output(%rip), %rdi
movq d_Output(%rip), %rsi
movl $40960000, %edx # imm = 0x2710000
movl $2, %ecx
callq hipMemcpy
movb $1, %al
movsd .LCPI5_3(%rip), %xmm2 # xmm2 = mem[0],zero
movapd .LCPI5_4(%rip), %xmm3 # xmm3 = [NaN,NaN]
movsd .LCPI5_5(%rip), %xmm4 # xmm4 = mem[0],zero
jmp .LBB5_7
.p2align 4, 0x90
.LBB5_9: # in Loop: Header=BB5_7 Depth=1
incq %rbx
cmpq $10240000, %rbx # imm = 0x9C4000
je .LBB5_10
.LBB5_7: # =>This Inner Loop Header: Depth=1
movq h_Output(%rip), %rcx
movss (%rcx,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movaps %xmm0, %xmm1
addsd %xmm2, %xmm1
andpd %xmm3, %xmm1
ucomisd %xmm4, %xmm1
jbe .LBB5_9
# %bb.8: # in Loop: Header=BB5_7 Depth=1
movl $.L.str.1, %edi
movl %ebx, %esi
movl $17, %edx
movb $1, %al
callq printf
movsd .LCPI5_5(%rip), %xmm4 # xmm4 = mem[0],zero
movapd .LCPI5_4(%rip), %xmm3 # xmm3 = [NaN,NaN]
movsd .LCPI5_3(%rip), %xmm2 # xmm2 = mem[0],zero
xorl %eax, %eax
jmp .LBB5_9
.LBB5_10:
testb $1, %al
movl $.L.str.4, %eax
movl $.L.str.3, %edi
cmoveq %rax, %rdi
callq puts@PLT
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z20gpuRunConstantKernelv, .Lfunc_end5-_Z20gpuRunConstantKernelv
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z17gpuRunTiledKernelv
.LCPI6_0:
.long 0x43960000 # float 300
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI6_1:
.quad 0x3f50624dd2f1a9fc # double 0.001
.LCPI6_2:
.quad 0x40247ae147ae147b # double 10.24
.LCPI6_3:
.quad 0xc031000000000000 # double -17
.LCPI6_5:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI6_4:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl _Z17gpuRunTiledKernelv
.p2align 4, 0x90
.type _Z17gpuRunTiledKernelv,@function
_Z17gpuRunTiledKernelv: # @_Z17gpuRunTiledKernelv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294968320, %rbx # imm = 0x100000400
leaq 8976(%rbx), %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_2
# %bb.1:
movq d_Input(%rip), %rax
movq d_Output(%rip), %rcx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movl $17, 16(%rsp)
movl $10240000, 8(%rsp) # imm = 0x9C4000
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z27convolution_1D_tiled_kernelPfS_ii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_2:
callq hipDeviceSynchronize
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $300, %r12d # imm = 0x12C
leaq 8976(%rbx), %r14
leaq 32(%rsp), %r13
leaq 24(%rsp), %rbp
leaq 96(%rsp), %r15
jmp .LBB6_3
.p2align 4, 0x90
.LBB6_5: # in Loop: Header=BB6_3 Depth=1
decl %r12d
je .LBB6_6
.LBB6_3: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_5
# %bb.4: # in Loop: Header=BB6_3 Depth=1
movq d_Input(%rip), %rax
movq d_Output(%rip), %rcx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movl $17, 92(%rsp)
movl $10240000, 88(%rsp) # imm = 0x9C4000
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 92(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z27convolution_1D_tiled_kernelPfS_ii, %edi
movq %r15, %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB6_5
.LBB6_6:
movq 8(%rsp), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq hipEventRecord
callq hipDeviceSynchronize
movl $0, 96(%rsp)
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 96(%rsp), %rdi
callq hipEventElapsedTime
movss 96(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI6_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
mulsd .LCPI6_1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm1
movsd .LCPI6_2(%rip), %xmm0 # xmm0 = mem[0],zero
divsd %xmm1, %xmm0
movl $.L.str.6, %edi
movl $10240000, %esi # imm = 0x9C4000
movb $2, %al
callq printf
movq h_Output(%rip), %rdi
movq d_Output(%rip), %rsi
movl $40960000, %edx # imm = 0x2710000
movl $2, %ecx
callq hipMemcpy
movb $1, %al
movsd .LCPI6_3(%rip), %xmm2 # xmm2 = mem[0],zero
movapd .LCPI6_4(%rip), %xmm3 # xmm3 = [NaN,NaN]
movsd .LCPI6_5(%rip), %xmm4 # xmm4 = mem[0],zero
jmp .LBB6_7
.p2align 4, 0x90
.LBB6_9: # in Loop: Header=BB6_7 Depth=1
incq %rbx
cmpq $10240000, %rbx # imm = 0x9C4000
je .LBB6_10
.LBB6_7: # =>This Inner Loop Header: Depth=1
movq h_Output(%rip), %rcx
movss (%rcx,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movaps %xmm0, %xmm1
addsd %xmm2, %xmm1
andpd %xmm3, %xmm1
ucomisd %xmm4, %xmm1
jbe .LBB6_9
# %bb.8: # in Loop: Header=BB6_7 Depth=1
movl $.L.str.1, %edi
movl %ebx, %esi
movl $17, %edx
movb $1, %al
callq printf
movsd .LCPI6_5(%rip), %xmm4 # xmm4 = mem[0],zero
movapd .LCPI6_4(%rip), %xmm3 # xmm3 = [NaN,NaN]
movsd .LCPI6_3(%rip), %xmm2 # xmm2 = mem[0],zero
xorl %eax, %eax
jmp .LBB6_9
.LBB6_10:
testb $1, %al
movl $.L.str.4, %eax
movl $.L.str.3, %edi
cmoveq %rax, %rdi
callq puts@PLT
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z17gpuRunTiledKernelv, .Lfunc_end6-_Z17gpuRunTiledKernelv
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z22gpuRunTiledCacheKernelv
.LCPI7_0:
.long 0x43960000 # float 300
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI7_1:
.quad 0x3f50624dd2f1a9fc # double 0.001
.LCPI7_2:
.quad 0x40247ae147ae147b # double 10.24
.LCPI7_3:
.quad 0xc031000000000000 # double -17
.LCPI7_5:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI7_4:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl _Z22gpuRunTiledCacheKernelv
.p2align 4, 0x90
.type _Z22gpuRunTiledCacheKernelv,@function
_Z22gpuRunTiledCacheKernelv: # @_Z22gpuRunTiledCacheKernelv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294968320, %rbx # imm = 0x100000400
leaq 8976(%rbx), %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_2
# %bb.1:
movq d_Input(%rip), %rax
movq d_Output(%rip), %rcx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movl $17, 16(%rsp)
movl $10240000, 8(%rsp) # imm = 0x9C4000
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z35convolution_1D_tiled_caching_kernelPfS_ii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_2:
callq hipDeviceSynchronize
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $300, %r12d # imm = 0x12C
leaq 8976(%rbx), %r14
leaq 32(%rsp), %r13
leaq 24(%rsp), %rbp
leaq 96(%rsp), %r15
jmp .LBB7_3
.p2align 4, 0x90
.LBB7_5: # in Loop: Header=BB7_3 Depth=1
decl %r12d
je .LBB7_6
.LBB7_3: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_5
# %bb.4: # in Loop: Header=BB7_3 Depth=1
movq d_Input(%rip), %rax
movq d_Output(%rip), %rcx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movl $17, 92(%rsp)
movl $10240000, 88(%rsp) # imm = 0x9C4000
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 92(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z35convolution_1D_tiled_caching_kernelPfS_ii, %edi
movq %r15, %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB7_5
.LBB7_6:
movq 8(%rsp), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq hipEventRecord
callq hipDeviceSynchronize
movl $0, 96(%rsp)
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 96(%rsp), %rdi
callq hipEventElapsedTime
movss 96(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI7_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
mulsd .LCPI7_1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm1
movsd .LCPI7_2(%rip), %xmm0 # xmm0 = mem[0],zero
divsd %xmm1, %xmm0
movl $.L.str.7, %edi
movl $10240000, %esi # imm = 0x9C4000
movb $2, %al
callq printf
movq h_Output(%rip), %rdi
movq d_Output(%rip), %rsi
movl $40960000, %edx # imm = 0x2710000
movl $2, %ecx
callq hipMemcpy
movb $1, %al
movsd .LCPI7_3(%rip), %xmm2 # xmm2 = mem[0],zero
movapd .LCPI7_4(%rip), %xmm3 # xmm3 = [NaN,NaN]
movsd .LCPI7_5(%rip), %xmm4 # xmm4 = mem[0],zero
jmp .LBB7_7
.p2align 4, 0x90
.LBB7_9: # in Loop: Header=BB7_7 Depth=1
incq %rbx
cmpq $10240000, %rbx # imm = 0x9C4000
je .LBB7_10
.LBB7_7: # =>This Inner Loop Header: Depth=1
movq h_Output(%rip), %rcx
movss (%rcx,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movaps %xmm0, %xmm1
addsd %xmm2, %xmm1
andpd %xmm3, %xmm1
ucomisd %xmm4, %xmm1
jbe .LBB7_9
# %bb.8: # in Loop: Header=BB7_7 Depth=1
movl $.L.str.1, %edi
movl %ebx, %esi
movl $17, %edx
movb $1, %al
callq printf
movsd .LCPI7_5(%rip), %xmm4 # xmm4 = mem[0],zero
movapd .LCPI7_4(%rip), %xmm3 # xmm3 = [NaN,NaN]
movsd .LCPI7_3(%rip), %xmm2 # xmm2 = mem[0],zero
xorl %eax, %eax
jmp .LBB7_9
.LBB7_10:
testb $1, %al
movl $.L.str.4, %eax
movl $.L.str.3, %edi
cmoveq %rax, %rdi
callq puts@PLT
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size _Z22gpuRunTiledCacheKernelv, .Lfunc_end7-_Z22gpuRunTiledCacheKernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $68, %edi
callq malloc
movq %rax, %r14
movq %rax, h_Kernel(%rip)
movl $40960000, %edi # imm = 0x2710000
callq malloc
movq %rax, %rbx
movq %rax, h_Input(%rip)
movl $40960000, %edi # imm = 0x2710000
callq malloc
movq %rax, h_Output(%rip)
xorl %eax, %eax
.p2align 4, 0x90
.LBB8_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%r14,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $17, %rax
jne .LBB8_1
# %bb.2: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB8_3: # %.preheader
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $10240000, %rax # imm = 0x9C4000
jne .LBB8_3
# %bb.4:
movl $d_Input, %edi
movl $40960000, %esi # imm = 0x2710000
callq hipMalloc
movl $d_Output, %edi
movl $40960000, %esi # imm = 0x2710000
callq hipMalloc
movl $d_Kernel, %edi
movl $68, %esi
callq hipMalloc
movq d_Input(%rip), %rdi
movq h_Input(%rip), %rsi
movl $40960000, %edx # imm = 0x2710000
movl $1, %ecx
callq hipMemcpy
movq d_Kernel(%rip), %rdi
movq h_Kernel(%rip), %rsi
movl $68, %edx
movl $1, %ecx
callq hipMemcpy
movq h_Kernel(%rip), %rsi
movl $c_M, %edi
movl $68, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movl $.Lstr, %edi
callq puts@PLT
callq _Z17gpuRunBasicKernelv
callq _Z20gpuRunConstantKernelv
callq _Z17gpuRunTiledKernelv
callq _Z22gpuRunTiledCacheKernelv
movq h_Input(%rip), %rdi
callq free
movq h_Kernel(%rip), %rdi
callq free
movq h_Output(%rip), %rdi
callq free
movq d_Input(%rip), %rdi
callq hipFree
movq d_Kernel(%rip), %rdi
callq hipFree
movq d_Output(%rip), %rdi
callq hipFree
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size main, .Lfunc_end8-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB9_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB9_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27convolution_1D_basic_kernelPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z30convolution_1D_constant_kernelPfS_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27convolution_1D_tiled_kernelPfS_ii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z35convolution_1D_tiled_caching_kernelPfS_ii, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $c_M, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movl $68, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end9:
.size __hip_module_ctor, .Lfunc_end9-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB10_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB10_2:
retq
.Lfunc_end10:
.size __hip_module_dtor, .Lfunc_end10-__hip_module_dtor
.cfi_endproc
# -- End function
.type c_M,@object # @c_M
.local c_M
.comm c_M,68,16
.type h_Kernel,@object # @h_Kernel
.bss
.globl h_Kernel
.p2align 3, 0x0
h_Kernel:
.quad 0
.size h_Kernel, 8
.type h_Input,@object # @h_Input
.globl h_Input
.p2align 3, 0x0
h_Input:
.quad 0
.size h_Input, 8
.type h_Output,@object # @h_Output
.globl h_Output
.p2align 3, 0x0
h_Output:
.quad 0
.size h_Output, 8
.type d_Kernel,@object # @d_Kernel
.globl d_Kernel
.p2align 3, 0x0
d_Kernel:
.quad 0
.size d_Kernel, 8
.type d_Input,@object # @d_Input
.globl d_Input
.p2align 3, 0x0
d_Input:
.quad 0
.size d_Input, 8
.type d_Output,@object # @d_Output
.globl d_Output
.p2align 3, 0x0
d_Output:
.quad 0
.size d_Output, 8
.type _Z27convolution_1D_basic_kernelPfS_S_ii,@object # @_Z27convolution_1D_basic_kernelPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z27convolution_1D_basic_kernelPfS_S_ii
.p2align 3, 0x0
_Z27convolution_1D_basic_kernelPfS_S_ii:
.quad _Z42__device_stub__convolution_1D_basic_kernelPfS_S_ii
.size _Z27convolution_1D_basic_kernelPfS_S_ii, 8
.type _Z30convolution_1D_constant_kernelPfS_ii,@object # @_Z30convolution_1D_constant_kernelPfS_ii
.globl _Z30convolution_1D_constant_kernelPfS_ii
.p2align 3, 0x0
_Z30convolution_1D_constant_kernelPfS_ii:
.quad _Z45__device_stub__convolution_1D_constant_kernelPfS_ii
.size _Z30convolution_1D_constant_kernelPfS_ii, 8
.type _Z27convolution_1D_tiled_kernelPfS_ii,@object # @_Z27convolution_1D_tiled_kernelPfS_ii
.globl _Z27convolution_1D_tiled_kernelPfS_ii
.p2align 3, 0x0
_Z27convolution_1D_tiled_kernelPfS_ii:
.quad _Z42__device_stub__convolution_1D_tiled_kernelPfS_ii
.size _Z27convolution_1D_tiled_kernelPfS_ii, 8
.type _Z35convolution_1D_tiled_caching_kernelPfS_ii,@object # @_Z35convolution_1D_tiled_caching_kernelPfS_ii
.globl _Z35convolution_1D_tiled_caching_kernelPfS_ii
.p2align 3, 0x0
_Z35convolution_1D_tiled_caching_kernelPfS_ii:
.quad _Z50__device_stub__convolution_1D_tiled_caching_kernelPfS_ii
.size _Z35convolution_1D_tiled_caching_kernelPfS_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Basic Kernel Throughput = %0.4f MPixels/sec, Time= %.5f sec, Size= %u Pixels\n"
.size .L.str, 78
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error! Index = %d,h_Output = %f,true value = %d\n"
.size .L.str.1, 49
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Result = PASS"
.size .L.str.3, 14
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Result = FAIL"
.size .L.str.4, 14
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Constant Kernel Throughput = %0.4f MPixels/sec, Time= %.5f sec, Size= %u Pixels\n"
.size .L.str.5, 81
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Tiled Kernel Throughput = %0.4f MPixels/sec, Time= %.5f sec, Size= %u Pixels\n"
.size .L.str.6, 78
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Tiled Cache Kernel Throughput = %0.4f MPixels/sec, Time= %.5f sec, Size= %u Pixels\n"
.size .L.str.7, 84
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z27convolution_1D_basic_kernelPfS_S_ii"
.size .L__unnamed_1, 40
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z30convolution_1D_constant_kernelPfS_ii"
.size .L__unnamed_2, 41
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z27convolution_1D_tiled_kernelPfS_ii"
.size .L__unnamed_3, 38
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z35convolution_1D_tiled_caching_kernelPfS_ii"
.size .L__unnamed_4, 46
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "c_M"
.size .L__unnamed_5, 4
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Running GPU convlution 1D ...."
.size .Lstr, 31
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z42__device_stub__convolution_1D_basic_kernelPfS_S_ii
.addrsig_sym _Z45__device_stub__convolution_1D_constant_kernelPfS_ii
.addrsig_sym _Z42__device_stub__convolution_1D_tiled_kernelPfS_ii
.addrsig_sym _Z50__device_stub__convolution_1D_tiled_caching_kernelPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym c_M
.addrsig_sym d_Kernel
.addrsig_sym d_Input
.addrsig_sym d_Output
.addrsig_sym _Z27convolution_1D_basic_kernelPfS_S_ii
.addrsig_sym _Z30convolution_1D_constant_kernelPfS_ii
.addrsig_sym _Z27convolution_1D_tiled_kernelPfS_ii
.addrsig_sym _Z35convolution_1D_tiled_caching_kernelPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<math.h>
#include<time.h>
#define N 256
void matrix_vecter_multi_cpu(float *A,float *B,float *C){
int i,j;
for(j=0;j<N;j++){
A[j]=0.0F;
for(i=0;i<N;i++){
A[j]=A[j]+B[j*N+i]*C[i];
}
}
}
int main(){
int i,j;
float A[N],B[N*N],C[N];
clock_t start,end;
for(j=0;j<N;j++){
for(i=0;i<N;i++){
B[j*N+i]=((float)j)/256.0;
}
}
for(j=0;j<N;j++){
C[j]=1.0F;
}
start=clock();
matrix_vecter_multi_cpu(A,B,C);
end=clock();
for(j=0;j<N;j++){
printf("A[ %d ]=%f \n",j,A[j]);
}
printf("Calculation time is %lf\n",(double)(end-start)/CLOCKS_PER_SEC);
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<math.h>
#include<time.h>
#define N 256
void matrix_vecter_multi_cpu(float *A,float *B,float *C){
int i,j;
for(j=0;j<N;j++){
A[j]=0.0F;
for(i=0;i<N;i++){
A[j]=A[j]+B[j*N+i]*C[i];
}
}
}
int main(){
int i,j;
float A[N],B[N*N],C[N];
clock_t start,end;
for(j=0;j<N;j++){
for(i=0;i<N;i++){
B[j*N+i]=((float)j)/256.0;
}
}
for(j=0;j<N;j++){
C[j]=1.0F;
}
start=clock();
matrix_vecter_multi_cpu(A,B,C);
end=clock();
for(j=0;j<N;j++){
printf("A[ %d ]=%f \n",j,A[j]);
}
printf("Calculation time is %lf\n",(double)(end-start)/CLOCKS_PER_SEC);
return 0;
} | .file "tmpxft_00100464_00000000-6_Matrix.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23matrix_vecter_multi_cpuPfS_S_
.type _Z23matrix_vecter_multi_cpuPfS_S_, @function
_Z23matrix_vecter_multi_cpuPfS_S_:
.LFB2057:
.cfi_startproc
endbr64
movq %rdi, %r8
movq %rdx, %rdi
movq %rsi, %rcx
movl $0, %esi
.L5:
movq %r8, %rdx
movl $0x00000000, (%r8)
movl $0, %eax
.L4:
movss (%rcx,%rax), %xmm0
mulss (%rdi,%rax), %xmm0
addss (%rdx), %xmm0
movss %xmm0, (%rdx)
addq $4, %rax
cmpq $1024, %rax
jne .L4
addq $4, %r8
addl $256, %esi
addq $1024, %rcx
cmpl $65536, %esi
jne .L5
ret
.cfi_endproc
.LFE2057:
.size _Z23matrix_vecter_multi_cpuPfS_S_, .-_Z23matrix_vecter_multi_cpuPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "A[ %d ]=%f \n"
.LC5:
.string "Calculation time is %lf\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
leaq -262144(%rsp), %r11
.cfi_def_cfa 11, 262184
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $2072, %rsp
.cfi_def_cfa_offset 264256
movq %fs:40, %rax
movq %rax, 264200(%rsp)
xorl %eax, %eax
leaq 3072(%rsp), %rdx
movl $0, %ecx
movss .LC1(%rip), %xmm1
.L9:
pxor %xmm0, %xmm0
cvtsi2ssl %ecx, %xmm0
mulss %xmm1, %xmm0
leaq -1024(%rdx), %rax
.L10:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L10
addl $1, %ecx
addq $1024, %rdx
cmpl $256, %ecx
jne .L9
leaq 1024(%rsp), %rax
leaq 2048(%rsp), %rdx
movss .LC2(%rip), %xmm0
.L12:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L12
call clock@PLT
movq %rax, %r12
leaq 1024(%rsp), %rdx
leaq 2048(%rsp), %rsi
movq %rsp, %rdi
call _Z23matrix_vecter_multi_cpuPfS_S_
call clock@PLT
movq %rax, %r13
movl $0, %ebx
leaq .LC3(%rip), %rbp
.L13:
pxor %xmm0, %xmm0
cvtss2sd (%rsp,%rbx,4), %xmm0
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $256, %rbx
jne .L13
movq %r13, %rax
subq %r12, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC4(%rip), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 264200(%rsp), %rax
subq %fs:40, %rax
jne .L19
movl $0, %eax
addq $264216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 998244352
.align 4
.LC2:
.long 1065353216
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<math.h>
#include<time.h>
#define N 256
void matrix_vecter_multi_cpu(float *A,float *B,float *C){
int i,j;
for(j=0;j<N;j++){
A[j]=0.0F;
for(i=0;i<N;i++){
A[j]=A[j]+B[j*N+i]*C[i];
}
}
}
int main(){
int i,j;
float A[N],B[N*N],C[N];
clock_t start,end;
for(j=0;j<N;j++){
for(i=0;i<N;i++){
B[j*N+i]=((float)j)/256.0;
}
}
for(j=0;j<N;j++){
C[j]=1.0F;
}
start=clock();
matrix_vecter_multi_cpu(A,B,C);
end=clock();
for(j=0;j<N;j++){
printf("A[ %d ]=%f \n",j,A[j]);
}
printf("Calculation time is %lf\n",(double)(end-start)/CLOCKS_PER_SEC);
return 0;
} | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<math.h>
#include<time.h>
#define N 256
void matrix_vecter_multi_cpu(float *A,float *B,float *C){
int i,j;
for(j=0;j<N;j++){
A[j]=0.0F;
for(i=0;i<N;i++){
A[j]=A[j]+B[j*N+i]*C[i];
}
}
}
int main(){
int i,j;
float A[N],B[N*N],C[N];
clock_t start,end;
for(j=0;j<N;j++){
for(i=0;i<N;i++){
B[j*N+i]=((float)j)/256.0;
}
}
for(j=0;j<N;j++){
C[j]=1.0F;
}
start=clock();
matrix_vecter_multi_cpu(A,B,C);
end=clock();
for(j=0;j<N;j++){
printf("A[ %d ]=%f \n",j,A[j]);
}
printf("Calculation time is %lf\n",(double)(end-start)/CLOCKS_PER_SEC);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<math.h>
#include<time.h>
#define N 256
void matrix_vecter_multi_cpu(float *A,float *B,float *C){
int i,j;
for(j=0;j<N;j++){
A[j]=0.0F;
for(i=0;i<N;i++){
A[j]=A[j]+B[j*N+i]*C[i];
}
}
}
int main(){
int i,j;
float A[N],B[N*N],C[N];
clock_t start,end;
for(j=0;j<N;j++){
for(i=0;i<N;i++){
B[j*N+i]=((float)j)/256.0;
}
}
for(j=0;j<N;j++){
C[j]=1.0F;
}
start=clock();
matrix_vecter_multi_cpu(A,B,C);
end=clock();
for(j=0;j<N;j++){
printf("A[ %d ]=%f \n",j,A[j]);
}
printf("Calculation time is %lf\n",(double)(end-start)/CLOCKS_PER_SEC);
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<math.h>
#include<time.h>
#define N 256
void matrix_vecter_multi_cpu(float *A,float *B,float *C){
int i,j;
for(j=0;j<N;j++){
A[j]=0.0F;
for(i=0;i<N;i++){
A[j]=A[j]+B[j*N+i]*C[i];
}
}
}
int main(){
int i,j;
float A[N],B[N*N],C[N];
clock_t start,end;
for(j=0;j<N;j++){
for(i=0;i<N;i++){
B[j*N+i]=((float)j)/256.0;
}
}
for(j=0;j<N;j++){
C[j]=1.0F;
}
start=clock();
matrix_vecter_multi_cpu(A,B,C);
end=clock();
for(j=0;j<N;j++){
printf("A[ %d ]=%f \n",j,A[j]);
}
printf("Calculation time is %lf\n",(double)(end-start)/CLOCKS_PER_SEC);
return 0;
} | .text
.file "Matrix.hip"
.globl _Z23matrix_vecter_multi_cpuPfS_S_ # -- Begin function _Z23matrix_vecter_multi_cpuPfS_S_
.p2align 4, 0x90
.type _Z23matrix_vecter_multi_cpuPfS_S_,@function
_Z23matrix_vecter_multi_cpuPfS_S_: # @_Z23matrix_vecter_multi_cpuPfS_S_
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
movl $0, (%rdi,%rax,4)
xorps %xmm0, %xmm0
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_2: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rsi,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rdx,%rcx,4), %xmm1
addss %xmm1, %xmm0
movss %xmm0, (%rdi,%rax,4)
incq %rcx
cmpq $256, %rcx # imm = 0x100
jne .LBB0_2
# %bb.3: # in Loop: Header=BB0_1 Depth=1
incq %rax
addq $1024, %rsi # imm = 0x400
cmpq $256, %rax # imm = 0x100
jne .LBB0_1
# %bb.4:
retq
.Lfunc_end0:
.size _Z23matrix_vecter_multi_cpuPfS_S_, .Lfunc_end0-_Z23matrix_vecter_multi_cpuPfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3f70000000000000 # double 0.00390625
.LCPI1_1:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $264192, %rsp # imm = 0x40800
.cfi_def_cfa_offset 264224
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 2048(%rsp), %rax
xorl %ecx, %ecx
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB1_1: # %.preheader17
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorps %xmm1, %xmm1
cvtsi2sd %ecx, %xmm1
mulsd %xmm0, %xmm1
cvtsd2ss %xmm1, %xmm1
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movss %xmm1, (%rax,%rdx,4)
incq %rdx
cmpq $256, %rdx # imm = 0x100
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %rcx
addq $1024, %rax # imm = 0x400
cmpq $256, %rcx # imm = 0x100
jne .LBB1_1
# %bb.4: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_5: # %.preheader
# =>This Inner Loop Header: Depth=1
movl $1065353216, 1024(%rsp,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $256, %rax # imm = 0x100
jne .LBB1_5
# %bb.6:
leaq 2048(%rsp), %r14
xorl %r15d, %r15d
callq clock
movq %rax, %rbx
.p2align 4, 0x90
.LBB1_7: # =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
movl $0, (%rsp,%r15,4)
xorpd %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_8: # Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss 1024(%rsp,%rax,4), %xmm1
addss %xmm1, %xmm0
incq %rax
cmpq $256, %rax # imm = 0x100
jne .LBB1_8
# %bb.9: # in Loop: Header=BB1_7 Depth=1
movss %xmm0, (%rsp,%r15,4)
incq %r15
addq $1024, %r14 # imm = 0x400
cmpq $256, %r15 # imm = 0x100
jne .LBB1_7
# %bb.10: # %_Z23matrix_vecter_multi_cpuPfS_S_.exit
xorl %r14d, %r14d
callq clock
movq %rax, %r15
.p2align 4, 0x90
.LBB1_11: # =>This Inner Loop Header: Depth=1
movss (%rsp,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movl %r14d, %esi
movb $1, %al
callq printf
incq %r14
cmpq $256, %r14 # imm = 0x100
jne .LBB1_11
# %bb.12:
subq %rbx, %r15
xorps %xmm0, %xmm0
cvtsi2sd %r15, %xmm0
divsd .LCPI1_1(%rip), %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $264192, %rsp # imm = 0x40800
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "A[ %d ]=%f \n"
.size .L.str, 13
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Calculation time is %lf\n"
.size .L.str.1, 25
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00100464_00000000-6_Matrix.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23matrix_vecter_multi_cpuPfS_S_
.type _Z23matrix_vecter_multi_cpuPfS_S_, @function
_Z23matrix_vecter_multi_cpuPfS_S_:
.LFB2057:
.cfi_startproc
endbr64
movq %rdi, %r8
movq %rdx, %rdi
movq %rsi, %rcx
movl $0, %esi
.L5:
movq %r8, %rdx
movl $0x00000000, (%r8)
movl $0, %eax
.L4:
movss (%rcx,%rax), %xmm0
mulss (%rdi,%rax), %xmm0
addss (%rdx), %xmm0
movss %xmm0, (%rdx)
addq $4, %rax
cmpq $1024, %rax
jne .L4
addq $4, %r8
addl $256, %esi
addq $1024, %rcx
cmpl $65536, %esi
jne .L5
ret
.cfi_endproc
.LFE2057:
.size _Z23matrix_vecter_multi_cpuPfS_S_, .-_Z23matrix_vecter_multi_cpuPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "A[ %d ]=%f \n"
.LC5:
.string "Calculation time is %lf\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
leaq -262144(%rsp), %r11
.cfi_def_cfa 11, 262184
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $2072, %rsp
.cfi_def_cfa_offset 264256
movq %fs:40, %rax
movq %rax, 264200(%rsp)
xorl %eax, %eax
leaq 3072(%rsp), %rdx
movl $0, %ecx
movss .LC1(%rip), %xmm1
.L9:
pxor %xmm0, %xmm0
cvtsi2ssl %ecx, %xmm0
mulss %xmm1, %xmm0
leaq -1024(%rdx), %rax
.L10:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L10
addl $1, %ecx
addq $1024, %rdx
cmpl $256, %ecx
jne .L9
leaq 1024(%rsp), %rax
leaq 2048(%rsp), %rdx
movss .LC2(%rip), %xmm0
.L12:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L12
call clock@PLT
movq %rax, %r12
leaq 1024(%rsp), %rdx
leaq 2048(%rsp), %rsi
movq %rsp, %rdi
call _Z23matrix_vecter_multi_cpuPfS_S_
call clock@PLT
movq %rax, %r13
movl $0, %ebx
leaq .LC3(%rip), %rbp
.L13:
pxor %xmm0, %xmm0
cvtss2sd (%rsp,%rbx,4), %xmm0
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $256, %rbx
jne .L13
movq %r13, %rax
subq %r12, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC4(%rip), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 264200(%rsp), %rax
subq %fs:40, %rax
jne .L19
movl $0, %eax
addq $264216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 998244352
.align 4
.LC2:
.long 1065353216
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Matrix.hip"
.globl _Z23matrix_vecter_multi_cpuPfS_S_ # -- Begin function _Z23matrix_vecter_multi_cpuPfS_S_
.p2align 4, 0x90
.type _Z23matrix_vecter_multi_cpuPfS_S_,@function
_Z23matrix_vecter_multi_cpuPfS_S_: # @_Z23matrix_vecter_multi_cpuPfS_S_
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
movl $0, (%rdi,%rax,4)
xorps %xmm0, %xmm0
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_2: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rsi,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rdx,%rcx,4), %xmm1
addss %xmm1, %xmm0
movss %xmm0, (%rdi,%rax,4)
incq %rcx
cmpq $256, %rcx # imm = 0x100
jne .LBB0_2
# %bb.3: # in Loop: Header=BB0_1 Depth=1
incq %rax
addq $1024, %rsi # imm = 0x400
cmpq $256, %rax # imm = 0x100
jne .LBB0_1
# %bb.4:
retq
.Lfunc_end0:
.size _Z23matrix_vecter_multi_cpuPfS_S_, .Lfunc_end0-_Z23matrix_vecter_multi_cpuPfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3f70000000000000 # double 0.00390625
.LCPI1_1:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $264192, %rsp # imm = 0x40800
.cfi_def_cfa_offset 264224
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 2048(%rsp), %rax
xorl %ecx, %ecx
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB1_1: # %.preheader17
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorps %xmm1, %xmm1
cvtsi2sd %ecx, %xmm1
mulsd %xmm0, %xmm1
cvtsd2ss %xmm1, %xmm1
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movss %xmm1, (%rax,%rdx,4)
incq %rdx
cmpq $256, %rdx # imm = 0x100
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %rcx
addq $1024, %rax # imm = 0x400
cmpq $256, %rcx # imm = 0x100
jne .LBB1_1
# %bb.4: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_5: # %.preheader
# =>This Inner Loop Header: Depth=1
movl $1065353216, 1024(%rsp,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $256, %rax # imm = 0x100
jne .LBB1_5
# %bb.6:
leaq 2048(%rsp), %r14
xorl %r15d, %r15d
callq clock
movq %rax, %rbx
.p2align 4, 0x90
.LBB1_7: # =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
movl $0, (%rsp,%r15,4)
xorpd %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_8: # Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss 1024(%rsp,%rax,4), %xmm1
addss %xmm1, %xmm0
incq %rax
cmpq $256, %rax # imm = 0x100
jne .LBB1_8
# %bb.9: # in Loop: Header=BB1_7 Depth=1
movss %xmm0, (%rsp,%r15,4)
incq %r15
addq $1024, %r14 # imm = 0x400
cmpq $256, %r15 # imm = 0x100
jne .LBB1_7
# %bb.10: # %_Z23matrix_vecter_multi_cpuPfS_S_.exit
xorl %r14d, %r14d
callq clock
movq %rax, %r15
.p2align 4, 0x90
.LBB1_11: # =>This Inner Loop Header: Depth=1
movss (%rsp,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movl %r14d, %esi
movb $1, %al
callq printf
incq %r14
cmpq $256, %r14 # imm = 0x100
jne .LBB1_11
# %bb.12:
subq %rbx, %r15
xorps %xmm0, %xmm0
cvtsi2sd %r15, %xmm0
divsd .LCPI1_1(%rip), %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $264192, %rsp # imm = 0x40800
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "A[ %d ]=%f \n"
.size .L.str, 13
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Calculation time is %lf\n"
.size .L.str.1, 25
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // test the size of shared memory for each block
#include <iostream>
#include <cstdio>
using namespace std;
#define N 100
__const__ int NN = 1;
__global__
void fun(double *py)
{
printf("NN = %d\n", NN);
double a[NN];
*py = 0.;
for (int i=0; i<1000000; ++i)
*py += 3.1415927;
}
int main()
{
double *py, y;
int N0 = 13;
cudaMemcpyToSymbol(NN, &N0, sizeof(int));
cudaMalloc(&py, sizeof(double));
fun<<<1,1>>>(py);
cudaMemcpy(&y, py, sizeof(double), cudaMemcpyDeviceToHost);
cout << "y = " << y << endl;
cudaDeviceSynchronize();
} | code for sm_80
Function : _Z3funPd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fca00078e00ff */
/*0010*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0020*/ IMAD.MOV.U32 R10, RZ, RZ, 0x1 ; /* 0x00000001ff0a7424 */
/* 0x000fe200078e00ff */
/*0030*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0040*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0050*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0070*/ STL [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0001e20000100800 */
/*0080*/ LDC.64 R8, c[0x4][R0] ; /* 0x0100000000087b82 */
/* 0x0000620000000a00 */
/*0090*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe200078e00ff */
/*00a0*/ ULDC.64 UR36, c[0x0][0x118] ; /* 0x0000460000247ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fca00000e06ff */
/*00c0*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x001fe40000000000 */
/*00d0*/ MOV R3, 0x140 ; /* 0x0000014000037802 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R20, 0xc0 ; /* 0x000000c000147802 */
/* 0x000fc40000000f00 */
/*00f0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0100*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0110*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0120*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0130*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x002fea0003c00000 */
/*0140*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff047624 */
/* 0x000fe200078e00ff */
/*0150*/ BSSY B0, 0x5d0 ; /* 0x0000047000007945 */
/* 0x000fe20003800000 */
/*0160*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*0170*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fc8000001ff00 */
/*0180*/ STG.E.64 [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x0001e6000c101b24 */
/*0190*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e620000000000 */
/*01a0*/ IADD3 R2, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x000fc80007ffe0ff */
/*01b0*/ ISETP.NE.AND P0, PT, R2, 0xf4240, PT ; /* 0x000f42400200780c */
/* 0x000fe20003f05270 */
/*01c0*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*01d0*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*01e0*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*01f0*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*0200*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*0210*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*0220*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*0230*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*0240*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*0250*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*0260*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*0270*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*0280*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*0290*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*02a0*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*02b0*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*02c0*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*02d0*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*02e0*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*02f0*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*0300*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*0310*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*0320*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*0330*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*0340*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*0350*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*0360*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*0370*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*0380*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*0390*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*03a0*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*03b0*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*03c0*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*03d0*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*03e0*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*03f0*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*0400*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*0410*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*0420*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*0430*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*0440*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*0450*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*0460*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*0470*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*0480*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*0490*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*04a0*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*04b0*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*04c0*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*04d0*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*04e0*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*04f0*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*0500*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*0510*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*0520*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*0530*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*0540*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*0550*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*0560*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*0570*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*0580*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*0590*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e4c0000000000 */
/*05a0*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x002e620000000000 */
/*05b0*/ @P0 BRA 0x190 ; /* 0xfffffbd000000947 */
/* 0x000fea000383ffff */
/*05c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05d0*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x002fe2000c101b24 */
/*05e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05f0*/ BRA 0x5f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // test the size of shared memory for each block
#include <iostream>
#include <cstdio>
using namespace std;
#define N 100
__const__ int NN = 1;
__global__
void fun(double *py)
{
printf("NN = %d\n", NN);
double a[NN];
*py = 0.;
for (int i=0; i<1000000; ++i)
*py += 3.1415927;
}
int main()
{
double *py, y;
int N0 = 13;
cudaMemcpyToSymbol(NN, &N0, sizeof(int));
cudaMalloc(&py, sizeof(double));
fun<<<1,1>>>(py);
cudaMemcpy(&y, py, sizeof(double), cudaMemcpyDeviceToHost);
cout << "y = " << y << endl;
cudaDeviceSynchronize();
} | .file "tmpxft_000c57ed_00000000-6_thread.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22__device_stub__Z3funPdPd
.type _Z22__device_stub__Z3funPdPd, @function
_Z22__device_stub__Z3funPdPd:
.LFB3694:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3funPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z22__device_stub__Z3funPdPd, .-_Z22__device_stub__Z3funPdPd
.globl _Z3funPd
.type _Z3funPd, @function
_Z3funPd:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z3funPdPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3funPd, .-_Z3funPd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "y = "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $13, 12(%rsp)
leaq 12(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL2NN(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 16(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 40(%rsp), %rdi
movl $2, %ecx
movl $8, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 40(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call cudaDeviceSynchronize@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 16(%rsp), %rdi
call _Z22__device_stub__Z3funPdPd
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3funPd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3funPd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata
.align 4
.type _ZL2NN, @object
.size _ZL2NN, 4
_ZL2NN:
.long 1
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // test the size of shared memory for each block
#include <iostream>
#include <cstdio>
using namespace std;
#define N 100
__const__ int NN = 1;
__global__
void fun(double *py)
{
printf("NN = %d\n", NN);
double a[NN];
*py = 0.;
for (int i=0; i<1000000; ++i)
*py += 3.1415927;
}
int main()
{
double *py, y;
int N0 = 13;
cudaMemcpyToSymbol(NN, &N0, sizeof(int));
cudaMalloc(&py, sizeof(double));
fun<<<1,1>>>(py);
cudaMemcpy(&y, py, sizeof(double), cudaMemcpyDeviceToHost);
cout << "y = " << y << endl;
cudaDeviceSynchronize();
} | // test the size of shared memory for each block
#include <hip/hip_runtime.h>
#include <iostream>
#include <cstdio>
using namespace std;
#define N 100
__const__ int NN = 1;
__global__
void fun(double *py)
{
printf("NN = %d\n", NN);
double a[NN];
*py = 0.;
for (int i=0; i<1000000; ++i)
*py += 3.1415927;
}
int main()
{
double *py, y;
int N0 = 13;
hipMemcpyToSymbol(HIP_SYMBOL(NN), &N0, sizeof(int));
hipMalloc(&py, sizeof(double));
fun<<<1,1>>>(py);
hipMemcpy(&y, py, sizeof(double), hipMemcpyDeviceToHost);
cout << "y = " << y << endl;
hipDeviceSynchronize();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // test the size of shared memory for each block
#include <hip/hip_runtime.h>
#include <iostream>
#include <cstdio>
using namespace std;
#define N 100
__const__ int NN = 1;
__global__
void fun(double *py)
{
printf("NN = %d\n", NN);
double a[NN];
*py = 0.;
for (int i=0; i<1000000; ++i)
*py += 3.1415927;
}
int main()
{
double *py, y;
int N0 = 13;
hipMemcpyToSymbol(HIP_SYMBOL(NN), &N0, sizeof(int));
hipMalloc(&py, sizeof(double));
fun<<<1,1>>>(py);
hipMemcpy(&y, py, sizeof(double), hipMemcpyDeviceToHost);
cout << "y = " << y << endl;
hipDeviceSynchronize();
} | .text
.file "thread.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__funPd # -- Begin function _Z18__device_stub__funPd
.p2align 4, 0x90
.type _Z18__device_stub__funPd,@function
_Z18__device_stub__funPd: # @_Z18__device_stub__funPd
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z3funPd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z18__device_stub__funPd, .Lfunc_end0-_Z18__device_stub__funPd
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $88, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $13, 4(%rsp)
leaq 4(%rsp), %rsi
movl $_ZL2NN, %edi
movl $4, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 24(%rsp), %rdi
movl $8, %esi
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 24(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 32(%rsp)
leaq 8(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z3funPd, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 24(%rsp), %rsi
leaq 8(%rsp), %rdi
movl $8, %edx
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 8(%rsp), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_7
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_5
# %bb.4:
movzbl 67(%rbx), %ecx
jmp .LBB1_6
.LBB1_5:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq hipDeviceSynchronize
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_7:
.cfi_def_cfa_offset 112
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3funPd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3funPd,@object # @_Z3funPd
.section .rodata,"a",@progbits
.globl _Z3funPd
.p2align 3, 0x0
_Z3funPd:
.quad _Z18__device_stub__funPd
.size _Z3funPd, 8
.type _ZL2NN,@object # @_ZL2NN
.p2align 2, 0x0
_ZL2NN:
.long 1 # 0x1
.size _ZL2NN, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "y = "
.size .L.str, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3funPd"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__funPd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3funPd
.addrsig_sym _ZL2NN
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c57ed_00000000-6_thread.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22__device_stub__Z3funPdPd
.type _Z22__device_stub__Z3funPdPd, @function
_Z22__device_stub__Z3funPdPd:
.LFB3694:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3funPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z22__device_stub__Z3funPdPd, .-_Z22__device_stub__Z3funPdPd
.globl _Z3funPd
.type _Z3funPd, @function
_Z3funPd:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z3funPdPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3funPd, .-_Z3funPd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "y = "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $13, 12(%rsp)
leaq 12(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL2NN(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 16(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 40(%rsp), %rdi
movl $2, %ecx
movl $8, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 40(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call cudaDeviceSynchronize@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 16(%rsp), %rdi
call _Z22__device_stub__Z3funPdPd
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3funPd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3funPd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata
.align 4
.type _ZL2NN, @object
.size _ZL2NN, 4
_ZL2NN:
.long 1
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "thread.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__funPd # -- Begin function _Z18__device_stub__funPd
.p2align 4, 0x90
.type _Z18__device_stub__funPd,@function
_Z18__device_stub__funPd: # @_Z18__device_stub__funPd
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z3funPd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z18__device_stub__funPd, .Lfunc_end0-_Z18__device_stub__funPd
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $88, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $13, 4(%rsp)
leaq 4(%rsp), %rsi
movl $_ZL2NN, %edi
movl $4, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 24(%rsp), %rdi
movl $8, %esi
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 24(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 32(%rsp)
leaq 8(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z3funPd, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 24(%rsp), %rsi
leaq 8(%rsp), %rdi
movl $8, %edx
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 8(%rsp), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_7
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_5
# %bb.4:
movzbl 67(%rbx), %ecx
jmp .LBB1_6
.LBB1_5:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq hipDeviceSynchronize
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_7:
.cfi_def_cfa_offset 112
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3funPd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3funPd,@object # @_Z3funPd
.section .rodata,"a",@progbits
.globl _Z3funPd
.p2align 3, 0x0
_Z3funPd:
.quad _Z18__device_stub__funPd
.size _Z3funPd, 8
.type _ZL2NN,@object # @_ZL2NN
.p2align 2, 0x0
_ZL2NN:
.long 1 # 0x1
.size _ZL2NN, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "y = "
.size .L.str, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3funPd"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__funPd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3funPd
.addrsig_sym _ZL2NN
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define IDX2D(a, i, stride, j) ((a)[(i)*(stride) + (j)])
__global__ void sim_kernel_tiled(double *z, double *v, size_t nx, size_t ny, double dx2inv, double dy2inv, double dt) {
extern __shared__ double z_tile[];
const int block_mesh_x = blockDim.x*blockIdx.x + 1;
const int block_mesh_y = blockDim.y*blockIdx.y + 1;
const int mesh_xx = block_mesh_x + threadIdx.x;
const int mesh_xy = block_mesh_y + threadIdx.y;
// We have to read into the tile BEFORE dropping threads so that it's actually fully
// initialized!
const double z_val = IDX2D(z_tile, threadIdx.y, blockDim.x, threadIdx.x)
= IDX2D(z, mesh_xy, nx, mesh_xx);
if (mesh_xx >= nx-1 || mesh_xy >= ny-1)
return;
__syncthreads();
double ax, ay;
if (1 <= threadIdx.x && threadIdx.x <= blockDim.x-2)
ax = dx2inv*(IDX2D(z_tile, threadIdx.y, blockDim.x, threadIdx.x-1)
+ IDX2D(z_tile, threadIdx.y, blockDim.x, threadIdx.x+1)
- 2.0*z_val);
else {
const int n = threadIdx.x == 0 ? -1 : +1;
ax = dx2inv*(IDX2D(z, mesh_xy, nx, mesh_xx+n)
+ IDX2D(z_tile, threadIdx.y, blockDim.x, threadIdx.x-n)
- 2.0*z_val);
}
if (1 <= threadIdx.y && threadIdx.y <= blockDim.y-2)
ay = dy2inv*(IDX2D(z_tile, threadIdx.y-1, blockDim.x, threadIdx.x)
+ IDX2D(z_tile, threadIdx.y+1, blockDim.x, threadIdx.x)
- 2.0*z_val);
else {
const int n = threadIdx.y == 0 ? -1 : +1;
ay = dx2inv*(IDX2D(z, mesh_xy+n, nx, mesh_xx)
+ IDX2D(z_tile, threadIdx.y-n, blockDim.x, threadIdx.x)
- 2.0*z_val);
}
const double v_val = IDX2D(v, mesh_xy, nx, mesh_xx) += (ax+ay)/2.0*dt;
IDX2D(z, mesh_xy, nx, mesh_xx) += dt*v_val;
} | code for sm_80
Function : _Z16sim_kernel_tiledPdS_mmddd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R21, SR_TID.Y ; /* 0x0000000000157919 */
/* 0x000e280000002200 */
/*0040*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e680000002500 */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0060*/ IMAD R11, R2, c[0x0][0x4], R21 ; /* 0x00000100020b7a24 */
/* 0x001fca00078e0215 */
/*0070*/ IADD3 R25, R11, 0x1, RZ ; /* 0x000000010b197810 */
/* 0x000fe20007ffe0ff */
/*0080*/ IMAD R8, R9, c[0x0][0x0], R0 ; /* 0x0000000009087a24 */
/* 0x002fc600078e0200 */
/*0090*/ SHF.R.S32.HI R10, RZ, 0x1f, R25 ; /* 0x0000001fff0a7819 */
/* 0x000fe40000011419 */
/*00a0*/ SHF.R.S32.HI R9, RZ, 0x1f, R8 ; /* 0x0000001fff097819 */
/* 0x000fc60000011408 */
/*00b0*/ IMAD R2, R10, c[0x0][0x170], RZ ; /* 0x00005c000a027a24 */
/* 0x000fe400078e02ff */
/*00c0*/ IMAD.WIDE.U32 R4, R25, c[0x0][0x170], R8 ; /* 0x00005c0019047a25 */
/* 0x000fc800078e0008 */
/*00d0*/ IMAD R23, R25, c[0x0][0x174], R2 ; /* 0x00005d0019177a24 */
/* 0x000fe200078e0202 */
/*00e0*/ LEA R2, P0, R4, c[0x0][0x160], 0x3 ; /* 0x0000580004027a11 */
/* 0x000fc600078018ff */
/*00f0*/ IMAD.IADD R3, R5, 0x1, R23 ; /* 0x0000000105037824 */
/* 0x000fca00078e0217 */
/*0100*/ LEA.HI.X R3, R4, c[0x0][0x164], R3, 0x3, P0 ; /* 0x0000590004037a11 */
/* 0x000fca00000f1c03 */
/*0110*/ LDG.E.64 R6, [R2.64+0x8] ; /* 0x0000080602067981 */
/* 0x000ea2000c1e1b00 */
/*0120*/ IMAD.MOV.U32 R13, RZ, RZ, 0x1 ; /* 0x00000001ff0d7424 */
/* 0x000fe400078e00ff */
/*0130*/ IMAD.MOV.U32 R19, RZ, RZ, -0x1 ; /* 0xffffffffff137424 */
/* 0x000fe400078e00ff */
/*0140*/ IMAD R17, R21, c[0x0][0x0], R0 ; /* 0x0000000015117a24 */
/* 0x000fe200078e0200 */
/*0150*/ IADD3 R4, P1, -R13.reuse, c[0x0][0x178], RZ ; /* 0x00005e000d047a10 */
/* 0x040fe40007f3e1ff */
/*0160*/ IADD3 R13, P2, -R13, c[0x0][0x170], RZ ; /* 0x00005c000d0d7a10 */
/* 0x000fe40007f5e1ff */
/*0170*/ ISETP.GT.U32.AND P0, PT, R4, R25, PT ; /* 0x000000190400720c */
/* 0x000fc40003f04070 */
/*0180*/ IADD3 R4, R8, 0x1, RZ ; /* 0x0000000108047810 */
/* 0x000fe40007ffe0ff */
/*0190*/ IADD3.X R5, R19, c[0x0][0x17c], RZ, P1, !PT ; /* 0x00005f0013057a10 */
/* 0x000fe40000ffe4ff */
/*01a0*/ ISETP.LE.U32.AND P1, PT, R13, R4, PT ; /* 0x000000040d00720c */
/* 0x000fe40003f23070 */
/*01b0*/ ISETP.GT.U32.AND.EX P0, PT, R5, R10, PT, P0 ; /* 0x0000000a0500720c */
/* 0x000fe40003f04100 */
/*01c0*/ IADD3.X R13, R19, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d00130d7a10 */
/* 0x000fe400017fe4ff */
/*01d0*/ SHF.R.S32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x000fc80000011404 */
/*01e0*/ ISETP.LE.U32.OR.EX P0, PT, R13, R5, !P0, P1 ; /* 0x000000050d00720c */
/* 0x000fe20004703510 */
/*01f0*/ STS.64 [R17.X8], R6 ; /* 0x0000000611007388 */
/* 0x0041d80000008a00 */
/*0200*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0210*/ ULDC UR4, c[0x0][0x4] ; /* 0x0000010000047ab9 */
/* 0x000fe20000000800 */
/*0220*/ IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff107624 */
/* 0x000fe200078e00ff */
/*0230*/ UIADD3 UR4, UR4, -0x2, URZ ; /* 0xfffffffe04047890 */
/* 0x000fe2000fffe03f */
/*0240*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*0250*/ IADD3 R9, R16, -0x2, RZ ; /* 0xfffffffe10097810 */
/* 0x000fe40007ffe0ff */
/*0260*/ ISETP.GT.U32.AND P0, PT, R21, UR4, PT ; /* 0x0000000415007c0c */
/* 0x000fe4000bf04070 */
/*0270*/ ISETP.GT.U32.AND P1, PT, R0, R9, PT ; /* 0x000000090000720c */
/* 0x000fc40003f24070 */
/*0280*/ ISETP.NE.AND P0, PT, R21, RZ, !P0 ; /* 0x000000ff1500720c */
/* 0x000fe40004705270 */
/*0290*/ ISETP.NE.AND P1, PT, R0, RZ, !P1 ; /* 0x000000ff0000720c */
/* 0x000fd60004f25270 */
/*02a0*/ @!P0 ISETP.NE.AND P3, PT, R21, RZ, PT ; /* 0x000000ff1500820c */
/* 0x000fe40003f65270 */
/*02b0*/ @!P1 ISETP.NE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000920c */
/* 0x000fe40003f45270 */
/*02c0*/ @!P0 SEL R18, R19.reuse, 0x1, !P3 ; /* 0x0000000113128807 */
/* 0x040fe40005800000 */
/*02d0*/ @!P1 SEL R19, R19, 0x1, !P2 ; /* 0x0000000113139807 */
/* 0x000fe40005000000 */
/*02e0*/ @!P0 IADD3 R13, R11, 0x1, R18 ; /* 0x000000010b0d8810 */
/* 0x000fe40007ffe012 */
/*02f0*/ @!P1 IADD3 R8, R8, 0x1, R19 ; /* 0x0000000108089810 */
/* 0x000fc40007ffe013 */
/*0300*/ @!P0 SHF.R.S32.HI R10, RZ, 0x1f, R13 ; /* 0x0000001fff0a8819 */
/* 0x000fe4000001140d */
/*0310*/ @!P1 SHF.R.S32.HI R9, RZ, 0x1f, R8 ; /* 0x0000001fff099819 */
/* 0x000fc60000011408 */
/*0320*/ @!P0 IMAD R12, R10, c[0x0][0x170], RZ ; /* 0x00005c000a0c8a24 */
/* 0x000fe400078e02ff */
/*0330*/ @!P0 IMAD.WIDE.U32 R10, R13, c[0x0][0x170], R4 ; /* 0x00005c000d0a8a25 */
/* 0x000fc800078e0004 */
/*0340*/ @!P0 IMAD R15, R13, c[0x0][0x174], R12 ; /* 0x00005d000d0f8a24 */
/* 0x000fe200078e020c */
/*0350*/ @!P0 LEA R14, P3, R10, c[0x0][0x160], 0x3 ; /* 0x000058000a0e8a11 */
/* 0x000fe200078618ff */
/*0360*/ @!P1 IMAD.WIDE.U32 R12, R25, c[0x0][0x170], R8 ; /* 0x00005c00190c9a25 */
/* 0x000fc800078e0008 */
/*0370*/ @!P0 IMAD.IADD R9, R11, 0x1, R15 ; /* 0x000000010b098824 */
/* 0x000fe200078e020f */
/*0380*/ @!P1 LEA R8, P2, R12, c[0x0][0x160], 0x3 ; /* 0x000058000c089a11 */
/* 0x000fe200078418ff */
/*0390*/ @!P1 IMAD.IADD R11, R23, 0x1, R13 ; /* 0x00000001170b9824 */
/* 0x000fc600078e020d */
/*03a0*/ @!P0 LEA.HI.X R15, R10, c[0x0][0x164], R9, 0x3, P3 ; /* 0x000059000a0f8a11 */
/* 0x000fe400018f1c09 */
/*03b0*/ @!P1 LEA.HI.X R9, R12, c[0x0][0x164], R11, 0x3, P2 ; /* 0x000059000c099a11 */
/* 0x000fc800010f1c0b */
/*03c0*/ @!P0 LDG.E.64 R14, [R14.64] ; /* 0x000000060e0e8981 */
/* 0x000ea8000c1e1b00 */
/*03d0*/ @!P1 LDG.E.64 R8, [R8.64] ; /* 0x0000000608089981 */
/* 0x000ee2000c1e1b00 */
/*03e0*/ IMAD.WIDE.U32 R10, R25, c[0x0][0x170], R4 ; /* 0x00005c00190a7a25 */
/* 0x000fc800078e0004 */
/*03f0*/ IMAD.IADD R23, R23, 0x1, R11 ; /* 0x0000000117177824 */
/* 0x000fe200078e020b */
/*0400*/ LEA R4, P2, R10, c[0x0][0x168], 0x3 ; /* 0x00005a000a047a11 */
/* 0x000fc800078418ff */
/*0410*/ LEA.HI.X R5, R10, c[0x0][0x16c], R23, 0x3, P2 ; /* 0x00005b000a057a11 */
/* 0x000fca00010f1c17 */
/*0420*/ LDG.E.64 R10, [R4.64] ; /* 0x00000006040a7981 */
/* 0x000f22000c1e1b00 */
/*0430*/ @!P0 IMAD.IADD R23, R21.reuse, 0x1, -R18 ; /* 0x0000000115178824 */
/* 0x040fe200078e0a12 */
/*0440*/ @P0 IADD3 R23, R21.reuse, 0x1, RZ ; /* 0x0000000115170810 */
/* 0x040fe20007ffe0ff */
/*0450*/ @P0 IMAD R13, R21, R16, -c[0x0][0x0] ; /* 0x80000000150d0624 */
/* 0x000fe400078e0210 */
/*0460*/ @!P1 IMAD.IADD R12, R0.reuse, 0x1, -R19 ; /* 0x00000001000c9824 */
/* 0x040fe200078e0a13 */
/*0470*/ @P1 IADD3 R12, R0, 0x1, RZ ; /* 0x00000001000c1810 */
/* 0x000fe20007ffe0ff */
/*0480*/ @P0 IMAD.IADD R16, R13, 0x1, R0.reuse ; /* 0x000000010d100824 */
/* 0x100fe400078e0200 */
/*0490*/ IMAD R23, R23, c[0x0][0x0], R0 ; /* 0x0000000017177a24 */
/* 0x000fe400078e0200 */
/*04a0*/ IMAD R12, R21, c[0x0][0x0], R12 ; /* 0x00000000150c7a24 */
/* 0x000fc600078e020c */
/*04b0*/ LDS.64 R18, [R23.X8] ; /* 0x0000000017127984 */
/* 0x000fe80000008a00 */
/*04c0*/ LDS.64 R12, [R12.X8] ; /* 0x000000000c0c7984 */
/* 0x000fe80000008a00 */
/*04d0*/ @P0 LDS.64 R14, [R16.X8] ; /* 0x00000000100e0984 */
/* 0x000ea80000008a00 */
/*04e0*/ @P1 LDS.64 R8, [R17.X8+-0x8] ; /* 0xfffff80011081984 */
/* 0x000ee20000008a00 */
/*04f0*/ DADD R18, R18, R14 ; /* 0x0000000012127229 */
/* 0x004fc8000000000e */
/*0500*/ DADD R14, R6, R6 ; /* 0x00000000060e7229 */
/* 0x0002a40000000006 */
/*0510*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff067624 */
/* 0x003fe400078e00ff */
/*0520*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff077624 */
/* 0x000fe200078e00ff */
/*0530*/ DADD R8, R12, R8 ; /* 0x000000000c087229 */
/* 0x008e220000000008 */
/*0540*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff068624 */
/* 0x000fe400078e00ff */
/*0550*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff078624 */
/* 0x000fe200078e00ff */
/*0560*/ DADD R18, -R14, R18 ; /* 0x000000000e127229 */
/* 0x004e480000000112 */
/*0570*/ DADD R14, R8, -R14 ; /* 0x00000000080e7229 */
/* 0x001fc8000000080e */
/*0580*/ DMUL R6, R18, R6 ; /* 0x0000000612067228 */
/* 0x002e0c0000000000 */
/*0590*/ DFMA R6, R14, c[0x0][0x180], R6 ; /* 0x000060000e067a2b */
/* 0x001e0c0000000006 */
/*05a0*/ DMUL R6, R6, 0.5 ; /* 0x3fe0000006067828 */
/* 0x001f0c0000000000 */
/*05b0*/ DFMA R6, R6, c[0x0][0x190], R10 ; /* 0x0000640006067a2b */
/* 0x010e0e000000000a */
/*05c0*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x001fe8000c101b06 */
/*05d0*/ LDG.E.64 R8, [R2.64+0x8] ; /* 0x0000080602087981 */
/* 0x000ea4000c1e1b00 */
/*05e0*/ DFMA R8, R6, c[0x0][0x190], R8 ; /* 0x0000640006087a2b */
/* 0x004e0e0000000008 */
/*05f0*/ STG.E.64 [R2.64+0x8], R8 ; /* 0x0000080802007986 */
/* 0x001fe2000c101b06 */
/*0600*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0610*/ BRA 0x610; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define IDX2D(a, i, stride, j) ((a)[(i)*(stride) + (j)])
__global__ void sim_kernel_tiled(double *z, double *v, size_t nx, size_t ny, double dx2inv, double dy2inv, double dt) {
extern __shared__ double z_tile[];
const int block_mesh_x = blockDim.x*blockIdx.x + 1;
const int block_mesh_y = blockDim.y*blockIdx.y + 1;
const int mesh_xx = block_mesh_x + threadIdx.x;
const int mesh_xy = block_mesh_y + threadIdx.y;
// We have to read into the tile BEFORE dropping threads so that it's actually fully
// initialized!
const double z_val = IDX2D(z_tile, threadIdx.y, blockDim.x, threadIdx.x)
= IDX2D(z, mesh_xy, nx, mesh_xx);
if (mesh_xx >= nx-1 || mesh_xy >= ny-1)
return;
__syncthreads();
double ax, ay;
if (1 <= threadIdx.x && threadIdx.x <= blockDim.x-2)
ax = dx2inv*(IDX2D(z_tile, threadIdx.y, blockDim.x, threadIdx.x-1)
+ IDX2D(z_tile, threadIdx.y, blockDim.x, threadIdx.x+1)
- 2.0*z_val);
else {
const int n = threadIdx.x == 0 ? -1 : +1;
ax = dx2inv*(IDX2D(z, mesh_xy, nx, mesh_xx+n)
+ IDX2D(z_tile, threadIdx.y, blockDim.x, threadIdx.x-n)
- 2.0*z_val);
}
if (1 <= threadIdx.y && threadIdx.y <= blockDim.y-2)
ay = dy2inv*(IDX2D(z_tile, threadIdx.y-1, blockDim.x, threadIdx.x)
+ IDX2D(z_tile, threadIdx.y+1, blockDim.x, threadIdx.x)
- 2.0*z_val);
else {
const int n = threadIdx.y == 0 ? -1 : +1;
ay = dx2inv*(IDX2D(z, mesh_xy+n, nx, mesh_xx)
+ IDX2D(z_tile, threadIdx.y-n, blockDim.x, threadIdx.x)
- 2.0*z_val);
}
const double v_val = IDX2D(v, mesh_xy, nx, mesh_xx) += (ax+ay)/2.0*dt;
IDX2D(z, mesh_xy, nx, mesh_xx) += dt*v_val;
} | .file "tmpxft_0012a623_00000000-6_sim_kernel_tiled.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z16sim_kernel_tiledPdS_mmdddPdS_mmddd
.type _Z43__device_stub__Z16sim_kernel_tiledPdS_mmdddPdS_mmddd, @function
_Z43__device_stub__Z16sim_kernel_tiledPdS_mmdddPdS_mmddd:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movsd %xmm0, 24(%rsp)
movsd %xmm1, 16(%rsp)
movsd %xmm2, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z16sim_kernel_tiledPdS_mmddd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z16sim_kernel_tiledPdS_mmdddPdS_mmddd, .-_Z43__device_stub__Z16sim_kernel_tiledPdS_mmdddPdS_mmddd
.globl _Z16sim_kernel_tiledPdS_mmddd
.type _Z16sim_kernel_tiledPdS_mmddd, @function
_Z16sim_kernel_tiledPdS_mmddd:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z16sim_kernel_tiledPdS_mmdddPdS_mmddd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16sim_kernel_tiledPdS_mmddd, .-_Z16sim_kernel_tiledPdS_mmddd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16sim_kernel_tiledPdS_mmddd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16sim_kernel_tiledPdS_mmddd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define IDX2D(a, i, stride, j) ((a)[(i)*(stride) + (j)])
__global__ void sim_kernel_tiled(double *z, double *v, size_t nx, size_t ny, double dx2inv, double dy2inv, double dt) {
extern __shared__ double z_tile[];
const int block_mesh_x = blockDim.x*blockIdx.x + 1;
const int block_mesh_y = blockDim.y*blockIdx.y + 1;
const int mesh_xx = block_mesh_x + threadIdx.x;
const int mesh_xy = block_mesh_y + threadIdx.y;
// We have to read into the tile BEFORE dropping threads so that it's actually fully
// initialized!
const double z_val = IDX2D(z_tile, threadIdx.y, blockDim.x, threadIdx.x)
= IDX2D(z, mesh_xy, nx, mesh_xx);
if (mesh_xx >= nx-1 || mesh_xy >= ny-1)
return;
__syncthreads();
double ax, ay;
if (1 <= threadIdx.x && threadIdx.x <= blockDim.x-2)
ax = dx2inv*(IDX2D(z_tile, threadIdx.y, blockDim.x, threadIdx.x-1)
+ IDX2D(z_tile, threadIdx.y, blockDim.x, threadIdx.x+1)
- 2.0*z_val);
else {
const int n = threadIdx.x == 0 ? -1 : +1;
ax = dx2inv*(IDX2D(z, mesh_xy, nx, mesh_xx+n)
+ IDX2D(z_tile, threadIdx.y, blockDim.x, threadIdx.x-n)
- 2.0*z_val);
}
if (1 <= threadIdx.y && threadIdx.y <= blockDim.y-2)
ay = dy2inv*(IDX2D(z_tile, threadIdx.y-1, blockDim.x, threadIdx.x)
+ IDX2D(z_tile, threadIdx.y+1, blockDim.x, threadIdx.x)
- 2.0*z_val);
else {
const int n = threadIdx.y == 0 ? -1 : +1;
ay = dx2inv*(IDX2D(z, mesh_xy+n, nx, mesh_xx)
+ IDX2D(z_tile, threadIdx.y-n, blockDim.x, threadIdx.x)
- 2.0*z_val);
}
const double v_val = IDX2D(v, mesh_xy, nx, mesh_xx) += (ax+ay)/2.0*dt;
IDX2D(z, mesh_xy, nx, mesh_xx) += dt*v_val;
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define IDX2D(a, i, stride, j) ((a)[(i)*(stride) + (j)])
__global__ void sim_kernel_tiled(double *z, double *v, size_t nx, size_t ny, double dx2inv, double dy2inv, double dt) {
extern __shared__ double z_tile[];
const int block_mesh_x = blockDim.x*blockIdx.x + 1;
const int block_mesh_y = blockDim.y*blockIdx.y + 1;
const int mesh_xx = block_mesh_x + threadIdx.x;
const int mesh_xy = block_mesh_y + threadIdx.y;
// We have to read into the tile BEFORE dropping threads so that it's actually fully
// initialized!
const double z_val = IDX2D(z_tile, threadIdx.y, blockDim.x, threadIdx.x)
= IDX2D(z, mesh_xy, nx, mesh_xx);
if (mesh_xx >= nx-1 || mesh_xy >= ny-1)
return;
__syncthreads();
double ax, ay;
if (1 <= threadIdx.x && threadIdx.x <= blockDim.x-2)
ax = dx2inv*(IDX2D(z_tile, threadIdx.y, blockDim.x, threadIdx.x-1)
+ IDX2D(z_tile, threadIdx.y, blockDim.x, threadIdx.x+1)
- 2.0*z_val);
else {
const int n = threadIdx.x == 0 ? -1 : +1;
ax = dx2inv*(IDX2D(z, mesh_xy, nx, mesh_xx+n)
+ IDX2D(z_tile, threadIdx.y, blockDim.x, threadIdx.x-n)
- 2.0*z_val);
}
if (1 <= threadIdx.y && threadIdx.y <= blockDim.y-2)
ay = dy2inv*(IDX2D(z_tile, threadIdx.y-1, blockDim.x, threadIdx.x)
+ IDX2D(z_tile, threadIdx.y+1, blockDim.x, threadIdx.x)
- 2.0*z_val);
else {
const int n = threadIdx.y == 0 ? -1 : +1;
ay = dx2inv*(IDX2D(z, mesh_xy+n, nx, mesh_xx)
+ IDX2D(z_tile, threadIdx.y-n, blockDim.x, threadIdx.x)
- 2.0*z_val);
}
const double v_val = IDX2D(v, mesh_xy, nx, mesh_xx) += (ax+ay)/2.0*dt;
IDX2D(z, mesh_xy, nx, mesh_xx) += dt*v_val;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define IDX2D(a, i, stride, j) ((a)[(i)*(stride) + (j)])
__global__ void sim_kernel_tiled(double *z, double *v, size_t nx, size_t ny, double dx2inv, double dy2inv, double dt) {
extern __shared__ double z_tile[];
const int block_mesh_x = blockDim.x*blockIdx.x + 1;
const int block_mesh_y = blockDim.y*blockIdx.y + 1;
const int mesh_xx = block_mesh_x + threadIdx.x;
const int mesh_xy = block_mesh_y + threadIdx.y;
// We have to read into the tile BEFORE dropping threads so that it's actually fully
// initialized!
const double z_val = IDX2D(z_tile, threadIdx.y, blockDim.x, threadIdx.x)
= IDX2D(z, mesh_xy, nx, mesh_xx);
if (mesh_xx >= nx-1 || mesh_xy >= ny-1)
return;
__syncthreads();
double ax, ay;
if (1 <= threadIdx.x && threadIdx.x <= blockDim.x-2)
ax = dx2inv*(IDX2D(z_tile, threadIdx.y, blockDim.x, threadIdx.x-1)
+ IDX2D(z_tile, threadIdx.y, blockDim.x, threadIdx.x+1)
- 2.0*z_val);
else {
const int n = threadIdx.x == 0 ? -1 : +1;
ax = dx2inv*(IDX2D(z, mesh_xy, nx, mesh_xx+n)
+ IDX2D(z_tile, threadIdx.y, blockDim.x, threadIdx.x-n)
- 2.0*z_val);
}
if (1 <= threadIdx.y && threadIdx.y <= blockDim.y-2)
ay = dy2inv*(IDX2D(z_tile, threadIdx.y-1, blockDim.x, threadIdx.x)
+ IDX2D(z_tile, threadIdx.y+1, blockDim.x, threadIdx.x)
- 2.0*z_val);
else {
const int n = threadIdx.y == 0 ? -1 : +1;
ay = dx2inv*(IDX2D(z, mesh_xy+n, nx, mesh_xx)
+ IDX2D(z_tile, threadIdx.y-n, blockDim.x, threadIdx.x)
- 2.0*z_val);
}
const double v_val = IDX2D(v, mesh_xy, nx, mesh_xx) += (ax+ay)/2.0*dt;
IDX2D(z, mesh_xy, nx, mesh_xx) += dt*v_val;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16sim_kernel_tiledPdS_mmddd
.globl _Z16sim_kernel_tiledPdS_mmddd
.p2align 8
.type _Z16sim_kernel_tiledPdS_mmddd,@function
_Z16sim_kernel_tiledPdS_mmddd:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x44
s_load_b128 s[4:7], s[0:1], 0x10
v_bfe_u32 v16, v0, 10, 10
v_and_b32_e32 v15, 0x3ff, v0
s_load_b64 s[8:9], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s10, s2, 0xffff
s_and_b32 s11, s3, 0xffff
s_mul_i32 s14, s14, s10
s_mul_i32 s15, s15, s11
v_add3_u32 v6, v15, s14, 1
v_add3_u32 v8, v16, s15, 1
s_add_u32 s2, s4, -1
s_addc_u32 s3, s5, -1
s_add_u32 s6, s6, -1
v_ashrrev_i32_e32 v7, 31, v6
v_ashrrev_i32_e32 v9, 31, v8
v_mul_lo_u32 v0, v8, s5
v_mad_u64_u32 v[11:12], null, v8, s4, 0
v_mad_u32_u24 v10, v16, s10, v15
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v1, v9, s4
s_addc_u32 s7, s7, -1
v_add_co_u32 v4, vcc_lo, v11, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v12, v12, v0, v1
v_add_co_ci_u32_e32 v5, vcc_lo, v12, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[4:5]
v_add_co_u32 v0, vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[6:7]
v_cmp_gt_u64_e64 s2, s[6:7], v[8:9]
v_lshl_add_u32 v9, v10, 3, 0
global_load_b64 v[2:3], v[0:1], off
s_and_b32 s2, vcc_lo, s2
s_waitcnt vmcnt(0)
ds_store_b64 v9, v[2:3]
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_10
v_add_nc_u32_e32 v9, -1, v15
s_add_i32 s2, s10, -2
v_mul_u32_u24_e32 v13, s10, v16
s_waitcnt lgkmcnt(0)
s_barrier
v_cmp_le_u32_e32 vcc_lo, s2, v9
buffer_gl0_inv
s_and_saveexec_b32 s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_3
v_cmp_eq_u32_e32 vcc_lo, 0, v15
v_lshlrev_b64 v[11:12], 3, v[11:12]
v_cndmask_b32_e64 v9, 1, -1, vcc_lo
v_cndmask_b32_e64 v14, -1, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v11, vcc_lo, s8, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s9, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v9, v6, v9
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[9:10], 3, v[9:10]
v_add_co_u32 v9, vcc_lo, v11, v9
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, v12, v10, vcc_lo
global_load_b64 v[9:10], v[9:10], off
.LBB0_3:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB0_5
s_waitcnt vmcnt(0)
v_add_lshl_u32 v9, v13, v15, 3
v_dual_mov_b32 v14, v13 :: v_dual_mov_b32 v13, 1
s_delay_alu instid0(VALU_DEP_2)
v_add3_u32 v9, v9, 0, -8
ds_load_b64 v[9:10], v9
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s2
v_add3_u32 v11, v14, v15, v13
s_load_b64 s[2:3], s[0:1], 0x20
v_add_nc_u32_e32 v13, -1, v16
s_add_i32 s11, s11, -2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v11, v11, 3, 0
v_cmp_le_u32_e32 vcc_lo, s11, v13
ds_load_b64 v[11:12], v11
s_and_saveexec_b32 s6, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s6, exec_lo, s6
s_cbranch_execz .LBB0_7
v_cmp_eq_u32_e32 vcc_lo, 0, v16
v_lshlrev_b64 v[6:7], 3, v[6:7]
v_cndmask_b32_e64 v17, 1, -1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v8, v8, v17
v_sub_nc_u32_e32 v17, v16, v17
v_ashrrev_i32_e32 v18, 31, v8
v_mul_lo_u32 v19, v8, s5
v_mad_u64_u32 v[13:14], null, v8, s4, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v8, v18, s4
v_add3_u32 v14, v14, v19, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[13:14], 3, v[13:14]
v_add_co_u32 v8, vcc_lo, s8, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v13, vcc_lo, s9, v14, vcc_lo
v_add_co_u32 v6, vcc_lo, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, v13, v7, vcc_lo
global_load_b64 v[13:14], v[6:7], off
.LBB0_7:
s_or_saveexec_b32 s4, s6
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v7, s3 :: v_dual_mov_b32 v6, s2
s_xor_b32 exec_lo, exec_lo, s4
s_cbranch_execz .LBB0_9
s_load_b64 s[6:7], s[0:1], 0x28
v_add_nc_u32_e32 v6, -1, v16
v_add_nc_u32_e32 v17, 1, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_i32_i24 v6, v6, s10, v15
v_lshl_add_u32 v6, v6, 3, 0
s_waitcnt vmcnt(0)
ds_load_b64 v[13:14], v6
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s4
s_load_b64 s[4:5], s[0:1], 0x8
v_lshlrev_b64 v[4:5], 3, v[4:5]
v_mad_i32_i24 v8, v17, s10, v15
s_load_b64 s[0:1], s[0:1], 0x30
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v8, v8, 3, 0
ds_load_b64 v[15:16], v8
s_waitcnt vmcnt(0)
v_add_f64 v[8:9], v[9:10], v[11:12]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b64 v[18:19], v[4:5], off
v_add_f64 v[13:14], v[13:14], v[15:16]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[10:11], v[2:3], -2.0, v[13:14]
v_fma_f64 v[2:3], v[2:3], -2.0, v[8:9]
v_mul_f64 v[6:7], v[10:11], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], v[2:3], s[2:3], v[6:7]
v_mul_f64 v[2:3], v[2:3], 0.5
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[2:3], v[2:3], s[0:1], v[18:19]
global_store_b64 v[4:5], v[2:3], off
global_load_b64 v[4:5], v[0:1], off
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[2:3], s[0:1], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16sim_kernel_tiledPdS_mmddd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 20
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16sim_kernel_tiledPdS_mmddd, .Lfunc_end0-_Z16sim_kernel_tiledPdS_mmddd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
- .offset: 48
.size: 8
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
- .offset: 176
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16sim_kernel_tiledPdS_mmddd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16sim_kernel_tiledPdS_mmddd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 20
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define IDX2D(a, i, stride, j) ((a)[(i)*(stride) + (j)])
__global__ void sim_kernel_tiled(double *z, double *v, size_t nx, size_t ny, double dx2inv, double dy2inv, double dt) {
extern __shared__ double z_tile[];
const int block_mesh_x = blockDim.x*blockIdx.x + 1;
const int block_mesh_y = blockDim.y*blockIdx.y + 1;
const int mesh_xx = block_mesh_x + threadIdx.x;
const int mesh_xy = block_mesh_y + threadIdx.y;
// We have to read into the tile BEFORE dropping threads so that it's actually fully
// initialized!
const double z_val = IDX2D(z_tile, threadIdx.y, blockDim.x, threadIdx.x)
= IDX2D(z, mesh_xy, nx, mesh_xx);
if (mesh_xx >= nx-1 || mesh_xy >= ny-1)
return;
__syncthreads();
double ax, ay;
if (1 <= threadIdx.x && threadIdx.x <= blockDim.x-2)
ax = dx2inv*(IDX2D(z_tile, threadIdx.y, blockDim.x, threadIdx.x-1)
+ IDX2D(z_tile, threadIdx.y, blockDim.x, threadIdx.x+1)
- 2.0*z_val);
else {
const int n = threadIdx.x == 0 ? -1 : +1;
ax = dx2inv*(IDX2D(z, mesh_xy, nx, mesh_xx+n)
+ IDX2D(z_tile, threadIdx.y, blockDim.x, threadIdx.x-n)
- 2.0*z_val);
}
if (1 <= threadIdx.y && threadIdx.y <= blockDim.y-2)
ay = dy2inv*(IDX2D(z_tile, threadIdx.y-1, blockDim.x, threadIdx.x)
+ IDX2D(z_tile, threadIdx.y+1, blockDim.x, threadIdx.x)
- 2.0*z_val);
else {
const int n = threadIdx.y == 0 ? -1 : +1;
ay = dx2inv*(IDX2D(z, mesh_xy+n, nx, mesh_xx)
+ IDX2D(z_tile, threadIdx.y-n, blockDim.x, threadIdx.x)
- 2.0*z_val);
}
const double v_val = IDX2D(v, mesh_xy, nx, mesh_xx) += (ax+ay)/2.0*dt;
IDX2D(z, mesh_xy, nx, mesh_xx) += dt*v_val;
} | .text
.file "sim_kernel_tiled.hip"
.globl _Z31__device_stub__sim_kernel_tiledPdS_mmddd # -- Begin function _Z31__device_stub__sim_kernel_tiledPdS_mmddd
.p2align 4, 0x90
.type _Z31__device_stub__sim_kernel_tiledPdS_mmddd,@function
_Z31__device_stub__sim_kernel_tiledPdS_mmddd: # @_Z31__device_stub__sim_kernel_tiledPdS_mmddd
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movsd %xmm0, 72(%rsp)
movsd %xmm1, 64(%rsp)
movsd %xmm2, 56(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z16sim_kernel_tiledPdS_mmddd, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z31__device_stub__sim_kernel_tiledPdS_mmddd, .Lfunc_end0-_Z31__device_stub__sim_kernel_tiledPdS_mmddd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16sim_kernel_tiledPdS_mmddd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16sim_kernel_tiledPdS_mmddd,@object # @_Z16sim_kernel_tiledPdS_mmddd
.section .rodata,"a",@progbits
.globl _Z16sim_kernel_tiledPdS_mmddd
.p2align 3, 0x0
_Z16sim_kernel_tiledPdS_mmddd:
.quad _Z31__device_stub__sim_kernel_tiledPdS_mmddd
.size _Z16sim_kernel_tiledPdS_mmddd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16sim_kernel_tiledPdS_mmddd"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__sim_kernel_tiledPdS_mmddd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16sim_kernel_tiledPdS_mmddd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16sim_kernel_tiledPdS_mmddd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R21, SR_TID.Y ; /* 0x0000000000157919 */
/* 0x000e280000002200 */
/*0040*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e680000002500 */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0060*/ IMAD R11, R2, c[0x0][0x4], R21 ; /* 0x00000100020b7a24 */
/* 0x001fca00078e0215 */
/*0070*/ IADD3 R25, R11, 0x1, RZ ; /* 0x000000010b197810 */
/* 0x000fe20007ffe0ff */
/*0080*/ IMAD R8, R9, c[0x0][0x0], R0 ; /* 0x0000000009087a24 */
/* 0x002fc600078e0200 */
/*0090*/ SHF.R.S32.HI R10, RZ, 0x1f, R25 ; /* 0x0000001fff0a7819 */
/* 0x000fe40000011419 */
/*00a0*/ SHF.R.S32.HI R9, RZ, 0x1f, R8 ; /* 0x0000001fff097819 */
/* 0x000fc60000011408 */
/*00b0*/ IMAD R2, R10, c[0x0][0x170], RZ ; /* 0x00005c000a027a24 */
/* 0x000fe400078e02ff */
/*00c0*/ IMAD.WIDE.U32 R4, R25, c[0x0][0x170], R8 ; /* 0x00005c0019047a25 */
/* 0x000fc800078e0008 */
/*00d0*/ IMAD R23, R25, c[0x0][0x174], R2 ; /* 0x00005d0019177a24 */
/* 0x000fe200078e0202 */
/*00e0*/ LEA R2, P0, R4, c[0x0][0x160], 0x3 ; /* 0x0000580004027a11 */
/* 0x000fc600078018ff */
/*00f0*/ IMAD.IADD R3, R5, 0x1, R23 ; /* 0x0000000105037824 */
/* 0x000fca00078e0217 */
/*0100*/ LEA.HI.X R3, R4, c[0x0][0x164], R3, 0x3, P0 ; /* 0x0000590004037a11 */
/* 0x000fca00000f1c03 */
/*0110*/ LDG.E.64 R6, [R2.64+0x8] ; /* 0x0000080602067981 */
/* 0x000ea2000c1e1b00 */
/*0120*/ IMAD.MOV.U32 R13, RZ, RZ, 0x1 ; /* 0x00000001ff0d7424 */
/* 0x000fe400078e00ff */
/*0130*/ IMAD.MOV.U32 R19, RZ, RZ, -0x1 ; /* 0xffffffffff137424 */
/* 0x000fe400078e00ff */
/*0140*/ IMAD R17, R21, c[0x0][0x0], R0 ; /* 0x0000000015117a24 */
/* 0x000fe200078e0200 */
/*0150*/ IADD3 R4, P1, -R13.reuse, c[0x0][0x178], RZ ; /* 0x00005e000d047a10 */
/* 0x040fe40007f3e1ff */
/*0160*/ IADD3 R13, P2, -R13, c[0x0][0x170], RZ ; /* 0x00005c000d0d7a10 */
/* 0x000fe40007f5e1ff */
/*0170*/ ISETP.GT.U32.AND P0, PT, R4, R25, PT ; /* 0x000000190400720c */
/* 0x000fc40003f04070 */
/*0180*/ IADD3 R4, R8, 0x1, RZ ; /* 0x0000000108047810 */
/* 0x000fe40007ffe0ff */
/*0190*/ IADD3.X R5, R19, c[0x0][0x17c], RZ, P1, !PT ; /* 0x00005f0013057a10 */
/* 0x000fe40000ffe4ff */
/*01a0*/ ISETP.LE.U32.AND P1, PT, R13, R4, PT ; /* 0x000000040d00720c */
/* 0x000fe40003f23070 */
/*01b0*/ ISETP.GT.U32.AND.EX P0, PT, R5, R10, PT, P0 ; /* 0x0000000a0500720c */
/* 0x000fe40003f04100 */
/*01c0*/ IADD3.X R13, R19, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d00130d7a10 */
/* 0x000fe400017fe4ff */
/*01d0*/ SHF.R.S32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x000fc80000011404 */
/*01e0*/ ISETP.LE.U32.OR.EX P0, PT, R13, R5, !P0, P1 ; /* 0x000000050d00720c */
/* 0x000fe20004703510 */
/*01f0*/ STS.64 [R17.X8], R6 ; /* 0x0000000611007388 */
/* 0x0041d80000008a00 */
/*0200*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0210*/ ULDC UR4, c[0x0][0x4] ; /* 0x0000010000047ab9 */
/* 0x000fe20000000800 */
/*0220*/ IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff107624 */
/* 0x000fe200078e00ff */
/*0230*/ UIADD3 UR4, UR4, -0x2, URZ ; /* 0xfffffffe04047890 */
/* 0x000fe2000fffe03f */
/*0240*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*0250*/ IADD3 R9, R16, -0x2, RZ ; /* 0xfffffffe10097810 */
/* 0x000fe40007ffe0ff */
/*0260*/ ISETP.GT.U32.AND P0, PT, R21, UR4, PT ; /* 0x0000000415007c0c */
/* 0x000fe4000bf04070 */
/*0270*/ ISETP.GT.U32.AND P1, PT, R0, R9, PT ; /* 0x000000090000720c */
/* 0x000fc40003f24070 */
/*0280*/ ISETP.NE.AND P0, PT, R21, RZ, !P0 ; /* 0x000000ff1500720c */
/* 0x000fe40004705270 */
/*0290*/ ISETP.NE.AND P1, PT, R0, RZ, !P1 ; /* 0x000000ff0000720c */
/* 0x000fd60004f25270 */
/*02a0*/ @!P0 ISETP.NE.AND P3, PT, R21, RZ, PT ; /* 0x000000ff1500820c */
/* 0x000fe40003f65270 */
/*02b0*/ @!P1 ISETP.NE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000920c */
/* 0x000fe40003f45270 */
/*02c0*/ @!P0 SEL R18, R19.reuse, 0x1, !P3 ; /* 0x0000000113128807 */
/* 0x040fe40005800000 */
/*02d0*/ @!P1 SEL R19, R19, 0x1, !P2 ; /* 0x0000000113139807 */
/* 0x000fe40005000000 */
/*02e0*/ @!P0 IADD3 R13, R11, 0x1, R18 ; /* 0x000000010b0d8810 */
/* 0x000fe40007ffe012 */
/*02f0*/ @!P1 IADD3 R8, R8, 0x1, R19 ; /* 0x0000000108089810 */
/* 0x000fc40007ffe013 */
/*0300*/ @!P0 SHF.R.S32.HI R10, RZ, 0x1f, R13 ; /* 0x0000001fff0a8819 */
/* 0x000fe4000001140d */
/*0310*/ @!P1 SHF.R.S32.HI R9, RZ, 0x1f, R8 ; /* 0x0000001fff099819 */
/* 0x000fc60000011408 */
/*0320*/ @!P0 IMAD R12, R10, c[0x0][0x170], RZ ; /* 0x00005c000a0c8a24 */
/* 0x000fe400078e02ff */
/*0330*/ @!P0 IMAD.WIDE.U32 R10, R13, c[0x0][0x170], R4 ; /* 0x00005c000d0a8a25 */
/* 0x000fc800078e0004 */
/*0340*/ @!P0 IMAD R15, R13, c[0x0][0x174], R12 ; /* 0x00005d000d0f8a24 */
/* 0x000fe200078e020c */
/*0350*/ @!P0 LEA R14, P3, R10, c[0x0][0x160], 0x3 ; /* 0x000058000a0e8a11 */
/* 0x000fe200078618ff */
/*0360*/ @!P1 IMAD.WIDE.U32 R12, R25, c[0x0][0x170], R8 ; /* 0x00005c00190c9a25 */
/* 0x000fc800078e0008 */
/*0370*/ @!P0 IMAD.IADD R9, R11, 0x1, R15 ; /* 0x000000010b098824 */
/* 0x000fe200078e020f */
/*0380*/ @!P1 LEA R8, P2, R12, c[0x0][0x160], 0x3 ; /* 0x000058000c089a11 */
/* 0x000fe200078418ff */
/*0390*/ @!P1 IMAD.IADD R11, R23, 0x1, R13 ; /* 0x00000001170b9824 */
/* 0x000fc600078e020d */
/*03a0*/ @!P0 LEA.HI.X R15, R10, c[0x0][0x164], R9, 0x3, P3 ; /* 0x000059000a0f8a11 */
/* 0x000fe400018f1c09 */
/*03b0*/ @!P1 LEA.HI.X R9, R12, c[0x0][0x164], R11, 0x3, P2 ; /* 0x000059000c099a11 */
/* 0x000fc800010f1c0b */
/*03c0*/ @!P0 LDG.E.64 R14, [R14.64] ; /* 0x000000060e0e8981 */
/* 0x000ea8000c1e1b00 */
/*03d0*/ @!P1 LDG.E.64 R8, [R8.64] ; /* 0x0000000608089981 */
/* 0x000ee2000c1e1b00 */
/*03e0*/ IMAD.WIDE.U32 R10, R25, c[0x0][0x170], R4 ; /* 0x00005c00190a7a25 */
/* 0x000fc800078e0004 */
/*03f0*/ IMAD.IADD R23, R23, 0x1, R11 ; /* 0x0000000117177824 */
/* 0x000fe200078e020b */
/*0400*/ LEA R4, P2, R10, c[0x0][0x168], 0x3 ; /* 0x00005a000a047a11 */
/* 0x000fc800078418ff */
/*0410*/ LEA.HI.X R5, R10, c[0x0][0x16c], R23, 0x3, P2 ; /* 0x00005b000a057a11 */
/* 0x000fca00010f1c17 */
/*0420*/ LDG.E.64 R10, [R4.64] ; /* 0x00000006040a7981 */
/* 0x000f22000c1e1b00 */
/*0430*/ @!P0 IMAD.IADD R23, R21.reuse, 0x1, -R18 ; /* 0x0000000115178824 */
/* 0x040fe200078e0a12 */
/*0440*/ @P0 IADD3 R23, R21.reuse, 0x1, RZ ; /* 0x0000000115170810 */
/* 0x040fe20007ffe0ff */
/*0450*/ @P0 IMAD R13, R21, R16, -c[0x0][0x0] ; /* 0x80000000150d0624 */
/* 0x000fe400078e0210 */
/*0460*/ @!P1 IMAD.IADD R12, R0.reuse, 0x1, -R19 ; /* 0x00000001000c9824 */
/* 0x040fe200078e0a13 */
/*0470*/ @P1 IADD3 R12, R0, 0x1, RZ ; /* 0x00000001000c1810 */
/* 0x000fe20007ffe0ff */
/*0480*/ @P0 IMAD.IADD R16, R13, 0x1, R0.reuse ; /* 0x000000010d100824 */
/* 0x100fe400078e0200 */
/*0490*/ IMAD R23, R23, c[0x0][0x0], R0 ; /* 0x0000000017177a24 */
/* 0x000fe400078e0200 */
/*04a0*/ IMAD R12, R21, c[0x0][0x0], R12 ; /* 0x00000000150c7a24 */
/* 0x000fc600078e020c */
/*04b0*/ LDS.64 R18, [R23.X8] ; /* 0x0000000017127984 */
/* 0x000fe80000008a00 */
/*04c0*/ LDS.64 R12, [R12.X8] ; /* 0x000000000c0c7984 */
/* 0x000fe80000008a00 */
/*04d0*/ @P0 LDS.64 R14, [R16.X8] ; /* 0x00000000100e0984 */
/* 0x000ea80000008a00 */
/*04e0*/ @P1 LDS.64 R8, [R17.X8+-0x8] ; /* 0xfffff80011081984 */
/* 0x000ee20000008a00 */
/*04f0*/ DADD R18, R18, R14 ; /* 0x0000000012127229 */
/* 0x004fc8000000000e */
/*0500*/ DADD R14, R6, R6 ; /* 0x00000000060e7229 */
/* 0x0002a40000000006 */
/*0510*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff067624 */
/* 0x003fe400078e00ff */
/*0520*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff077624 */
/* 0x000fe200078e00ff */
/*0530*/ DADD R8, R12, R8 ; /* 0x000000000c087229 */
/* 0x008e220000000008 */
/*0540*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff068624 */
/* 0x000fe400078e00ff */
/*0550*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff078624 */
/* 0x000fe200078e00ff */
/*0560*/ DADD R18, -R14, R18 ; /* 0x000000000e127229 */
/* 0x004e480000000112 */
/*0570*/ DADD R14, R8, -R14 ; /* 0x00000000080e7229 */
/* 0x001fc8000000080e */
/*0580*/ DMUL R6, R18, R6 ; /* 0x0000000612067228 */
/* 0x002e0c0000000000 */
/*0590*/ DFMA R6, R14, c[0x0][0x180], R6 ; /* 0x000060000e067a2b */
/* 0x001e0c0000000006 */
/*05a0*/ DMUL R6, R6, 0.5 ; /* 0x3fe0000006067828 */
/* 0x001f0c0000000000 */
/*05b0*/ DFMA R6, R6, c[0x0][0x190], R10 ; /* 0x0000640006067a2b */
/* 0x010e0e000000000a */
/*05c0*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x001fe8000c101b06 */
/*05d0*/ LDG.E.64 R8, [R2.64+0x8] ; /* 0x0000080602087981 */
/* 0x000ea4000c1e1b00 */
/*05e0*/ DFMA R8, R6, c[0x0][0x190], R8 ; /* 0x0000640006087a2b */
/* 0x004e0e0000000008 */
/*05f0*/ STG.E.64 [R2.64+0x8], R8 ; /* 0x0000080802007986 */
/* 0x001fe2000c101b06 */
/*0600*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0610*/ BRA 0x610; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16sim_kernel_tiledPdS_mmddd
.globl _Z16sim_kernel_tiledPdS_mmddd
.p2align 8
.type _Z16sim_kernel_tiledPdS_mmddd,@function
_Z16sim_kernel_tiledPdS_mmddd:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x44
s_load_b128 s[4:7], s[0:1], 0x10
v_bfe_u32 v16, v0, 10, 10
v_and_b32_e32 v15, 0x3ff, v0
s_load_b64 s[8:9], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s10, s2, 0xffff
s_and_b32 s11, s3, 0xffff
s_mul_i32 s14, s14, s10
s_mul_i32 s15, s15, s11
v_add3_u32 v6, v15, s14, 1
v_add3_u32 v8, v16, s15, 1
s_add_u32 s2, s4, -1
s_addc_u32 s3, s5, -1
s_add_u32 s6, s6, -1
v_ashrrev_i32_e32 v7, 31, v6
v_ashrrev_i32_e32 v9, 31, v8
v_mul_lo_u32 v0, v8, s5
v_mad_u64_u32 v[11:12], null, v8, s4, 0
v_mad_u32_u24 v10, v16, s10, v15
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v1, v9, s4
s_addc_u32 s7, s7, -1
v_add_co_u32 v4, vcc_lo, v11, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v12, v12, v0, v1
v_add_co_ci_u32_e32 v5, vcc_lo, v12, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[4:5]
v_add_co_u32 v0, vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[6:7]
v_cmp_gt_u64_e64 s2, s[6:7], v[8:9]
v_lshl_add_u32 v9, v10, 3, 0
global_load_b64 v[2:3], v[0:1], off
s_and_b32 s2, vcc_lo, s2
s_waitcnt vmcnt(0)
ds_store_b64 v9, v[2:3]
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_10
v_add_nc_u32_e32 v9, -1, v15
s_add_i32 s2, s10, -2
v_mul_u32_u24_e32 v13, s10, v16
s_waitcnt lgkmcnt(0)
s_barrier
v_cmp_le_u32_e32 vcc_lo, s2, v9
buffer_gl0_inv
s_and_saveexec_b32 s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_3
v_cmp_eq_u32_e32 vcc_lo, 0, v15
v_lshlrev_b64 v[11:12], 3, v[11:12]
v_cndmask_b32_e64 v9, 1, -1, vcc_lo
v_cndmask_b32_e64 v14, -1, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v11, vcc_lo, s8, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s9, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v9, v6, v9
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[9:10], 3, v[9:10]
v_add_co_u32 v9, vcc_lo, v11, v9
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, v12, v10, vcc_lo
global_load_b64 v[9:10], v[9:10], off
.LBB0_3:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB0_5
s_waitcnt vmcnt(0)
v_add_lshl_u32 v9, v13, v15, 3
v_dual_mov_b32 v14, v13 :: v_dual_mov_b32 v13, 1
s_delay_alu instid0(VALU_DEP_2)
v_add3_u32 v9, v9, 0, -8
ds_load_b64 v[9:10], v9
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s2
v_add3_u32 v11, v14, v15, v13
s_load_b64 s[2:3], s[0:1], 0x20
v_add_nc_u32_e32 v13, -1, v16
s_add_i32 s11, s11, -2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v11, v11, 3, 0
v_cmp_le_u32_e32 vcc_lo, s11, v13
ds_load_b64 v[11:12], v11
s_and_saveexec_b32 s6, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s6, exec_lo, s6
s_cbranch_execz .LBB0_7
v_cmp_eq_u32_e32 vcc_lo, 0, v16
v_lshlrev_b64 v[6:7], 3, v[6:7]
v_cndmask_b32_e64 v17, 1, -1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v8, v8, v17
v_sub_nc_u32_e32 v17, v16, v17
v_ashrrev_i32_e32 v18, 31, v8
v_mul_lo_u32 v19, v8, s5
v_mad_u64_u32 v[13:14], null, v8, s4, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v8, v18, s4
v_add3_u32 v14, v14, v19, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[13:14], 3, v[13:14]
v_add_co_u32 v8, vcc_lo, s8, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v13, vcc_lo, s9, v14, vcc_lo
v_add_co_u32 v6, vcc_lo, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, v13, v7, vcc_lo
global_load_b64 v[13:14], v[6:7], off
.LBB0_7:
s_or_saveexec_b32 s4, s6
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v7, s3 :: v_dual_mov_b32 v6, s2
s_xor_b32 exec_lo, exec_lo, s4
s_cbranch_execz .LBB0_9
s_load_b64 s[6:7], s[0:1], 0x28
v_add_nc_u32_e32 v6, -1, v16
v_add_nc_u32_e32 v17, 1, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_i32_i24 v6, v6, s10, v15
v_lshl_add_u32 v6, v6, 3, 0
s_waitcnt vmcnt(0)
ds_load_b64 v[13:14], v6
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s4
s_load_b64 s[4:5], s[0:1], 0x8
v_lshlrev_b64 v[4:5], 3, v[4:5]
v_mad_i32_i24 v8, v17, s10, v15
s_load_b64 s[0:1], s[0:1], 0x30
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v8, v8, 3, 0
ds_load_b64 v[15:16], v8
s_waitcnt vmcnt(0)
v_add_f64 v[8:9], v[9:10], v[11:12]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b64 v[18:19], v[4:5], off
v_add_f64 v[13:14], v[13:14], v[15:16]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[10:11], v[2:3], -2.0, v[13:14]
v_fma_f64 v[2:3], v[2:3], -2.0, v[8:9]
v_mul_f64 v[6:7], v[10:11], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], v[2:3], s[2:3], v[6:7]
v_mul_f64 v[2:3], v[2:3], 0.5
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[2:3], v[2:3], s[0:1], v[18:19]
global_store_b64 v[4:5], v[2:3], off
global_load_b64 v[4:5], v[0:1], off
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[2:3], s[0:1], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16sim_kernel_tiledPdS_mmddd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 20
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16sim_kernel_tiledPdS_mmddd, .Lfunc_end0-_Z16sim_kernel_tiledPdS_mmddd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
- .offset: 48
.size: 8
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
- .offset: 176
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16sim_kernel_tiledPdS_mmddd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16sim_kernel_tiledPdS_mmddd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 20
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012a623_00000000-6_sim_kernel_tiled.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z16sim_kernel_tiledPdS_mmdddPdS_mmddd
.type _Z43__device_stub__Z16sim_kernel_tiledPdS_mmdddPdS_mmddd, @function
_Z43__device_stub__Z16sim_kernel_tiledPdS_mmdddPdS_mmddd:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movsd %xmm0, 24(%rsp)
movsd %xmm1, 16(%rsp)
movsd %xmm2, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z16sim_kernel_tiledPdS_mmddd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z16sim_kernel_tiledPdS_mmdddPdS_mmddd, .-_Z43__device_stub__Z16sim_kernel_tiledPdS_mmdddPdS_mmddd
.globl _Z16sim_kernel_tiledPdS_mmddd
.type _Z16sim_kernel_tiledPdS_mmddd, @function
_Z16sim_kernel_tiledPdS_mmddd:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z16sim_kernel_tiledPdS_mmdddPdS_mmddd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16sim_kernel_tiledPdS_mmddd, .-_Z16sim_kernel_tiledPdS_mmddd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16sim_kernel_tiledPdS_mmddd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16sim_kernel_tiledPdS_mmddd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sim_kernel_tiled.hip"
.globl _Z31__device_stub__sim_kernel_tiledPdS_mmddd # -- Begin function _Z31__device_stub__sim_kernel_tiledPdS_mmddd
.p2align 4, 0x90
.type _Z31__device_stub__sim_kernel_tiledPdS_mmddd,@function
_Z31__device_stub__sim_kernel_tiledPdS_mmddd: # @_Z31__device_stub__sim_kernel_tiledPdS_mmddd
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movsd %xmm0, 72(%rsp)
movsd %xmm1, 64(%rsp)
movsd %xmm2, 56(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z16sim_kernel_tiledPdS_mmddd, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z31__device_stub__sim_kernel_tiledPdS_mmddd, .Lfunc_end0-_Z31__device_stub__sim_kernel_tiledPdS_mmddd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16sim_kernel_tiledPdS_mmddd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16sim_kernel_tiledPdS_mmddd,@object # @_Z16sim_kernel_tiledPdS_mmddd
.section .rodata,"a",@progbits
.globl _Z16sim_kernel_tiledPdS_mmddd
.p2align 3, 0x0
_Z16sim_kernel_tiledPdS_mmddd:
.quad _Z31__device_stub__sim_kernel_tiledPdS_mmddd
.size _Z16sim_kernel_tiledPdS_mmddd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16sim_kernel_tiledPdS_mmddd"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__sim_kernel_tiledPdS_mmddd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16sim_kernel_tiledPdS_mmddd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /* Simple benchmark to test matrix addition */
#include <stdio.h>
#include <math.h>
#define ROWS 5000
#define COLS 5000
#define CUDA_BLOCK_X 128
#define CUDA_BLOCK_Y 1
#define CUDA_BLOCK_Z 1
__global__ void _auto_kernel_0(float A[5000][5000],float B[5000][5000],float C[5000][5000])
{
int thread_x_id;thread_x_id = blockIdx.x * blockDim.x + threadIdx.x;
int thread_y_id;thread_y_id = blockIdx.y * blockDim.y + threadIdx.y;
if (thread_x_id && thread_y_id)
if (thread_x_id <= 5000 && thread_y_id <= 5000) {
C[1 * thread_x_id + -1][1 * thread_y_id + -1] = A[1 * thread_x_id + -1][1 * thread_y_id + -1] + B[1 * thread_x_id + -1][1 * thread_y_id + -1];
}
}
int main()
{
int j_nom_4;
int i_nom_3;
int j_nom_2;
int i_nom_1;
int j;
int i;
/* Declare three arrays: C = A + B */
static float A[5000][5000];
static float B[5000][5000];
static float C[5000][5000];
/* Initialize */
for (i = 1; i <= 5000; i += 1) {
for (j = 1; j <= 5000; j += 1) {
A[1 * i + -1][1 * j + -1] = (sin((1 * i + -1 + (1 * j + -1))) * sin((1 * i + -1 + (1 * j + -1))));
B[1 * i + -1][1 * j + -1] = (cos((1 * i + -1 + (1 * j + -1))) * cos((1 * i + -1 + (1 * j + -1))));
}
}
{
/* Auto-generated code for call to _auto_kernel_0 */
typedef float _narray_A[5000];
_narray_A *d_A;
cudaMalloc((void **) &d_A, sizeof(float ) * 5000 * 5000);
cudaMemcpy(d_A, A, sizeof(float ) * 5000 * 5000, cudaMemcpyHostToDevice);
typedef float _narray_B[5000];
_narray_B *d_B;
cudaMalloc((void **) &d_B, sizeof(float ) * 5000 * 5000);
cudaMemcpy(d_B, B, sizeof(float ) * 5000 * 5000, cudaMemcpyHostToDevice);
typedef float _narray_C[5000];
_narray_C *d_C;
cudaMalloc((void **) &d_C, sizeof(float ) * 5000 * 5000);
cudaMemcpy(d_C, C, sizeof(float ) * 5000 * 5000, cudaMemcpyHostToDevice);
int CUDA_GRID_X;
CUDA_GRID_X = (5000 + CUDA_BLOCK_X - 1)/CUDA_BLOCK_X;
int CUDA_GRID_Y;
CUDA_GRID_Y = (5000 + CUDA_BLOCK_Y - 1)/CUDA_BLOCK_Y;
int CUDA_GRID_Z;
CUDA_GRID_Z = (1 + CUDA_BLOCK_Z - 1)/CUDA_BLOCK_Z;
const dim3 CUDA_blockSize(CUDA_BLOCK_X, CUDA_BLOCK_Y, CUDA_BLOCK_Z);
const dim3 CUDA_gridSize(CUDA_GRID_X, CUDA_GRID_Y, CUDA_GRID_Z);
_auto_kernel_0<<<CUDA_gridSize,CUDA_blockSize>>>(d_A, d_B, d_C);
cudaMemcpy(A, d_A, sizeof(float ) * 5000 * 5000, cudaMemcpyDeviceToHost);
cudaMemcpy(B, d_B, sizeof(float ) * 5000 * 5000, cudaMemcpyDeviceToHost);
cudaMemcpy(C, d_C, sizeof(float ) * 5000 * 5000, cudaMemcpyDeviceToHost);
}
/* Check the result */
double sum = 0;
for (i_nom_3 = 1; i_nom_3 <= 5000; i_nom_3 += 1) {
for (j_nom_4 = 1; j_nom_4 <= 5000; j_nom_4 += 1) {
sum += C[1 * i_nom_3 + -1][1 * j_nom_4 + -1];
}
}
/* Report the result */
double r = (double )5000;
double c = (double )5000;
printf("Result (Should be close to 1.00) : %f\n",sum / (r * c));
return 0;
} | code for sm_80
Function : _Z14_auto_kernel_0PA5000_fS0_S0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0070*/ IMAD R2, R2, c[0x0][0x4], R5 ; /* 0x0000010002027a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.EQ.OR P0, PT, R2, RZ, !P0 ; /* 0x000000ff0200720c */
/* 0x000fda0004702670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ ISETP.GT.AND P0, PT, R2, 0x1388, PT ; /* 0x000013880200780c */
/* 0x000fc80003f04270 */
/*00b0*/ ISETP.GT.OR P0, PT, R0, 0x1388, P0 ; /* 0x000013880000780c */
/* 0x000fda0000704670 */
/*00c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00d0*/ HFMA2.MMA R7, -RZ, RZ, 0, 24.5 ; /* 0x00004e20ff077435 */
/* 0x000fe200000001ff */
/*00e0*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*00f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0100*/ IADD3 R9, R2, -0x1, RZ ; /* 0xffffffff02097810 */
/* 0x000fce0007ffe0ff */
/*0110*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0207 */
/*0120*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*0130*/ IMAD.WIDE R2, R9, 0x4, R2 ; /* 0x0000000409027825 */
/* 0x000fc800078e0202 */
/*0140*/ IMAD.WIDE R4, R9, 0x4, R4 ; /* 0x0000000409047825 */
/* 0x000fe400078e0204 */
/*0150*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0160*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0170*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fcc00078e0207 */
/*0180*/ IMAD.WIDE R6, R9, 0x4, R6 ; /* 0x0000000409067825 */
/* 0x000fc800078e0206 */
/*0190*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*01a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* Simple benchmark to test matrix addition */
#include <stdio.h>
#include <math.h>
#define ROWS 5000
#define COLS 5000
#define CUDA_BLOCK_X 128
#define CUDA_BLOCK_Y 1
#define CUDA_BLOCK_Z 1
__global__ void _auto_kernel_0(float A[5000][5000],float B[5000][5000],float C[5000][5000])
{
int thread_x_id;thread_x_id = blockIdx.x * blockDim.x + threadIdx.x;
int thread_y_id;thread_y_id = blockIdx.y * blockDim.y + threadIdx.y;
if (thread_x_id && thread_y_id)
if (thread_x_id <= 5000 && thread_y_id <= 5000) {
C[1 * thread_x_id + -1][1 * thread_y_id + -1] = A[1 * thread_x_id + -1][1 * thread_y_id + -1] + B[1 * thread_x_id + -1][1 * thread_y_id + -1];
}
}
int main()
{
int j_nom_4;
int i_nom_3;
int j_nom_2;
int i_nom_1;
int j;
int i;
/* Declare three arrays: C = A + B */
static float A[5000][5000];
static float B[5000][5000];
static float C[5000][5000];
/* Initialize */
for (i = 1; i <= 5000; i += 1) {
for (j = 1; j <= 5000; j += 1) {
A[1 * i + -1][1 * j + -1] = (sin((1 * i + -1 + (1 * j + -1))) * sin((1 * i + -1 + (1 * j + -1))));
B[1 * i + -1][1 * j + -1] = (cos((1 * i + -1 + (1 * j + -1))) * cos((1 * i + -1 + (1 * j + -1))));
}
}
{
/* Auto-generated code for call to _auto_kernel_0 */
typedef float _narray_A[5000];
_narray_A *d_A;
cudaMalloc((void **) &d_A, sizeof(float ) * 5000 * 5000);
cudaMemcpy(d_A, A, sizeof(float ) * 5000 * 5000, cudaMemcpyHostToDevice);
typedef float _narray_B[5000];
_narray_B *d_B;
cudaMalloc((void **) &d_B, sizeof(float ) * 5000 * 5000);
cudaMemcpy(d_B, B, sizeof(float ) * 5000 * 5000, cudaMemcpyHostToDevice);
typedef float _narray_C[5000];
_narray_C *d_C;
cudaMalloc((void **) &d_C, sizeof(float ) * 5000 * 5000);
cudaMemcpy(d_C, C, sizeof(float ) * 5000 * 5000, cudaMemcpyHostToDevice);
int CUDA_GRID_X;
CUDA_GRID_X = (5000 + CUDA_BLOCK_X - 1)/CUDA_BLOCK_X;
int CUDA_GRID_Y;
CUDA_GRID_Y = (5000 + CUDA_BLOCK_Y - 1)/CUDA_BLOCK_Y;
int CUDA_GRID_Z;
CUDA_GRID_Z = (1 + CUDA_BLOCK_Z - 1)/CUDA_BLOCK_Z;
const dim3 CUDA_blockSize(CUDA_BLOCK_X, CUDA_BLOCK_Y, CUDA_BLOCK_Z);
const dim3 CUDA_gridSize(CUDA_GRID_X, CUDA_GRID_Y, CUDA_GRID_Z);
_auto_kernel_0<<<CUDA_gridSize,CUDA_blockSize>>>(d_A, d_B, d_C);
cudaMemcpy(A, d_A, sizeof(float ) * 5000 * 5000, cudaMemcpyDeviceToHost);
cudaMemcpy(B, d_B, sizeof(float ) * 5000 * 5000, cudaMemcpyDeviceToHost);
cudaMemcpy(C, d_C, sizeof(float ) * 5000 * 5000, cudaMemcpyDeviceToHost);
}
/* Check the result */
double sum = 0;
for (i_nom_3 = 1; i_nom_3 <= 5000; i_nom_3 += 1) {
for (j_nom_4 = 1; j_nom_4 <= 5000; j_nom_4 += 1) {
sum += C[1 * i_nom_3 + -1][1 * j_nom_4 + -1];
}
}
/* Report the result */
double r = (double )5000;
double c = (double )5000;
printf("Result (Should be close to 1.00) : %f\n",sum / (r * c));
return 0;
} | .file "tmpxft_0009241c_00000000-6_matrix_addition.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z14_auto_kernel_0PA5000_fS0_S0_PA5000_fS0_S0_
.type _Z46__device_stub__Z14_auto_kernel_0PA5000_fS0_S0_PA5000_fS0_S0_, @function
_Z46__device_stub__Z14_auto_kernel_0PA5000_fS0_S0_PA5000_fS0_S0_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14_auto_kernel_0PA5000_fS0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z46__device_stub__Z14_auto_kernel_0PA5000_fS0_S0_PA5000_fS0_S0_, .-_Z46__device_stub__Z14_auto_kernel_0PA5000_fS0_S0_PA5000_fS0_S0_
.globl _Z14_auto_kernel_0PA5000_fS0_S0_
.type _Z14_auto_kernel_0PA5000_fS0_S0_, @function
_Z14_auto_kernel_0PA5000_fS0_S0_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z14_auto_kernel_0PA5000_fS0_S0_PA5000_fS0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z14_auto_kernel_0PA5000_fS0_S0_, .-_Z14_auto_kernel_0PA5000_fS0_S0_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Result (Should be close to 1.00) : %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
movl $5000, %r13d
leaq 24(%rsp), %r15
leaq 16(%rsp), %r14
.L12:
leal -5000(%r13), %ebx
movq 8(%rsp), %rax
leaq _ZZ4mainE1A(%rip), %rcx
leaq (%rax,%rcx), %r12
leaq _ZZ4mainE1B(%rip), %rcx
leaq (%rax,%rcx), %rbp
.L13:
pxor %xmm0, %xmm0
cvtsi2sdl %ebx, %xmm0
movq %r14, %rsi
movq %r15, %rdi
call sincos@PLT
movsd 16(%rsp), %xmm0
movsd 24(%rsp), %xmm1
mulsd %xmm1, %xmm1
cvtsd2ss %xmm1, %xmm1
movss %xmm1, (%r12)
mulsd %xmm0, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 0(%rbp)
addl $1, %ebx
addq $4, %r12
addq $4, %rbp
cmpl %r13d, %ebx
jne .L13
addl $1, %r13d
addq $20000, 8(%rsp)
cmpl $10000, %r13d
jne .L12
leaq 40(%rsp), %rdi
movl $100000000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $100000000, %edx
leaq _ZZ4mainE1A(%rip), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
leaq 48(%rsp), %rdi
movl $100000000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $100000000, %edx
leaq _ZZ4mainE1B(%rip), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
leaq 56(%rsp), %rdi
movl $100000000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $100000000, %edx
leaq _ZZ4mainE1C(%rip), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 64(%rsp)
movl $1, 68(%rsp)
movl $40, 76(%rsp)
movl $5000, 80(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 76(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L15:
movl $2, %ecx
movl $100000000, %edx
movq 40(%rsp), %rsi
leaq _ZZ4mainE1A(%rip), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $100000000, %edx
movq 48(%rsp), %rsi
leaq _ZZ4mainE1B(%rip), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $100000000, %edx
movq 56(%rsp), %rsi
leaq _ZZ4mainE1C(%rip), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 20000(%rbx), %rdx
leaq 100020000(%rbx), %rcx
pxor %xmm0, %xmm0
.L16:
leaq -20000(%rdx), %rax
.L17:
pxor %xmm1, %xmm1
cvtss2sd (%rax), %xmm1
addsd %xmm1, %xmm0
addq $4, %rax
cmpq %rdx, %rax
jne .L17
addq $20000, %rdx
cmpq %rcx, %rdx
jne .L16
divsd .LC1(%rip), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z46__device_stub__Z14_auto_kernel_0PA5000_fS0_S0_PA5000_fS0_S0_
jmp .L15
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC4:
.string "_Z14_auto_kernel_0PA5000_fS0_S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z14_auto_kernel_0PA5000_fS0_S0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZZ4mainE1C
.comm _ZZ4mainE1C,100000000,32
.local _ZZ4mainE1B
.comm _ZZ4mainE1B,100000000,32
.local _ZZ4mainE1A
.comm _ZZ4mainE1A,100000000,32
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1098372996
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* Simple benchmark to test matrix addition */
#include <stdio.h>
#include <math.h>
#define ROWS 5000
#define COLS 5000
#define CUDA_BLOCK_X 128
#define CUDA_BLOCK_Y 1
#define CUDA_BLOCK_Z 1
__global__ void _auto_kernel_0(float A[5000][5000],float B[5000][5000],float C[5000][5000])
{
int thread_x_id;thread_x_id = blockIdx.x * blockDim.x + threadIdx.x;
int thread_y_id;thread_y_id = blockIdx.y * blockDim.y + threadIdx.y;
if (thread_x_id && thread_y_id)
if (thread_x_id <= 5000 && thread_y_id <= 5000) {
C[1 * thread_x_id + -1][1 * thread_y_id + -1] = A[1 * thread_x_id + -1][1 * thread_y_id + -1] + B[1 * thread_x_id + -1][1 * thread_y_id + -1];
}
}
int main()
{
int j_nom_4;
int i_nom_3;
int j_nom_2;
int i_nom_1;
int j;
int i;
/* Declare three arrays: C = A + B */
static float A[5000][5000];
static float B[5000][5000];
static float C[5000][5000];
/* Initialize */
for (i = 1; i <= 5000; i += 1) {
for (j = 1; j <= 5000; j += 1) {
A[1 * i + -1][1 * j + -1] = (sin((1 * i + -1 + (1 * j + -1))) * sin((1 * i + -1 + (1 * j + -1))));
B[1 * i + -1][1 * j + -1] = (cos((1 * i + -1 + (1 * j + -1))) * cos((1 * i + -1 + (1 * j + -1))));
}
}
{
/* Auto-generated code for call to _auto_kernel_0 */
typedef float _narray_A[5000];
_narray_A *d_A;
cudaMalloc((void **) &d_A, sizeof(float ) * 5000 * 5000);
cudaMemcpy(d_A, A, sizeof(float ) * 5000 * 5000, cudaMemcpyHostToDevice);
typedef float _narray_B[5000];
_narray_B *d_B;
cudaMalloc((void **) &d_B, sizeof(float ) * 5000 * 5000);
cudaMemcpy(d_B, B, sizeof(float ) * 5000 * 5000, cudaMemcpyHostToDevice);
typedef float _narray_C[5000];
_narray_C *d_C;
cudaMalloc((void **) &d_C, sizeof(float ) * 5000 * 5000);
cudaMemcpy(d_C, C, sizeof(float ) * 5000 * 5000, cudaMemcpyHostToDevice);
int CUDA_GRID_X;
CUDA_GRID_X = (5000 + CUDA_BLOCK_X - 1)/CUDA_BLOCK_X;
int CUDA_GRID_Y;
CUDA_GRID_Y = (5000 + CUDA_BLOCK_Y - 1)/CUDA_BLOCK_Y;
int CUDA_GRID_Z;
CUDA_GRID_Z = (1 + CUDA_BLOCK_Z - 1)/CUDA_BLOCK_Z;
const dim3 CUDA_blockSize(CUDA_BLOCK_X, CUDA_BLOCK_Y, CUDA_BLOCK_Z);
const dim3 CUDA_gridSize(CUDA_GRID_X, CUDA_GRID_Y, CUDA_GRID_Z);
_auto_kernel_0<<<CUDA_gridSize,CUDA_blockSize>>>(d_A, d_B, d_C);
cudaMemcpy(A, d_A, sizeof(float ) * 5000 * 5000, cudaMemcpyDeviceToHost);
cudaMemcpy(B, d_B, sizeof(float ) * 5000 * 5000, cudaMemcpyDeviceToHost);
cudaMemcpy(C, d_C, sizeof(float ) * 5000 * 5000, cudaMemcpyDeviceToHost);
}
/* Check the result */
double sum = 0;
for (i_nom_3 = 1; i_nom_3 <= 5000; i_nom_3 += 1) {
for (j_nom_4 = 1; j_nom_4 <= 5000; j_nom_4 += 1) {
sum += C[1 * i_nom_3 + -1][1 * j_nom_4 + -1];
}
}
/* Report the result */
double r = (double )5000;
double c = (double )5000;
printf("Result (Should be close to 1.00) : %f\n",sum / (r * c));
return 0;
} | /* Simple benchmark to test matrix addition */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#define ROWS 5000
#define COLS 5000
#define CUDA_BLOCK_X 128
#define CUDA_BLOCK_Y 1
#define CUDA_BLOCK_Z 1
__global__ void _auto_kernel_0(float A[5000][5000],float B[5000][5000],float C[5000][5000])
{
int thread_x_id;thread_x_id = blockIdx.x * blockDim.x + threadIdx.x;
int thread_y_id;thread_y_id = blockIdx.y * blockDim.y + threadIdx.y;
if (thread_x_id && thread_y_id)
if (thread_x_id <= 5000 && thread_y_id <= 5000) {
C[1 * thread_x_id + -1][1 * thread_y_id + -1] = A[1 * thread_x_id + -1][1 * thread_y_id + -1] + B[1 * thread_x_id + -1][1 * thread_y_id + -1];
}
}
int main()
{
int j_nom_4;
int i_nom_3;
int j_nom_2;
int i_nom_1;
int j;
int i;
/* Declare three arrays: C = A + B */
static float A[5000][5000];
static float B[5000][5000];
static float C[5000][5000];
/* Initialize */
for (i = 1; i <= 5000; i += 1) {
for (j = 1; j <= 5000; j += 1) {
A[1 * i + -1][1 * j + -1] = (sin((1 * i + -1 + (1 * j + -1))) * sin((1 * i + -1 + (1 * j + -1))));
B[1 * i + -1][1 * j + -1] = (cos((1 * i + -1 + (1 * j + -1))) * cos((1 * i + -1 + (1 * j + -1))));
}
}
{
/* Auto-generated code for call to _auto_kernel_0 */
typedef float _narray_A[5000];
_narray_A *d_A;
hipMalloc((void **) &d_A, sizeof(float ) * 5000 * 5000);
hipMemcpy(d_A, A, sizeof(float ) * 5000 * 5000, hipMemcpyHostToDevice);
typedef float _narray_B[5000];
_narray_B *d_B;
hipMalloc((void **) &d_B, sizeof(float ) * 5000 * 5000);
hipMemcpy(d_B, B, sizeof(float ) * 5000 * 5000, hipMemcpyHostToDevice);
typedef float _narray_C[5000];
_narray_C *d_C;
hipMalloc((void **) &d_C, sizeof(float ) * 5000 * 5000);
hipMemcpy(d_C, C, sizeof(float ) * 5000 * 5000, hipMemcpyHostToDevice);
int CUDA_GRID_X;
CUDA_GRID_X = (5000 + CUDA_BLOCK_X - 1)/CUDA_BLOCK_X;
int CUDA_GRID_Y;
CUDA_GRID_Y = (5000 + CUDA_BLOCK_Y - 1)/CUDA_BLOCK_Y;
int CUDA_GRID_Z;
CUDA_GRID_Z = (1 + CUDA_BLOCK_Z - 1)/CUDA_BLOCK_Z;
const dim3 CUDA_blockSize(CUDA_BLOCK_X, CUDA_BLOCK_Y, CUDA_BLOCK_Z);
const dim3 CUDA_gridSize(CUDA_GRID_X, CUDA_GRID_Y, CUDA_GRID_Z);
_auto_kernel_0<<<CUDA_gridSize,CUDA_blockSize>>>(d_A, d_B, d_C);
hipMemcpy(A, d_A, sizeof(float ) * 5000 * 5000, hipMemcpyDeviceToHost);
hipMemcpy(B, d_B, sizeof(float ) * 5000 * 5000, hipMemcpyDeviceToHost);
hipMemcpy(C, d_C, sizeof(float ) * 5000 * 5000, hipMemcpyDeviceToHost);
}
/* Check the result */
double sum = 0;
for (i_nom_3 = 1; i_nom_3 <= 5000; i_nom_3 += 1) {
for (j_nom_4 = 1; j_nom_4 <= 5000; j_nom_4 += 1) {
sum += C[1 * i_nom_3 + -1][1 * j_nom_4 + -1];
}
}
/* Report the result */
double r = (double )5000;
double c = (double )5000;
printf("Result (Should be close to 1.00) : %f\n",sum / (r * c));
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /* Simple benchmark to test matrix addition */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#define ROWS 5000
#define COLS 5000
#define CUDA_BLOCK_X 128
#define CUDA_BLOCK_Y 1
#define CUDA_BLOCK_Z 1
__global__ void _auto_kernel_0(float A[5000][5000],float B[5000][5000],float C[5000][5000])
{
int thread_x_id;thread_x_id = blockIdx.x * blockDim.x + threadIdx.x;
int thread_y_id;thread_y_id = blockIdx.y * blockDim.y + threadIdx.y;
if (thread_x_id && thread_y_id)
if (thread_x_id <= 5000 && thread_y_id <= 5000) {
C[1 * thread_x_id + -1][1 * thread_y_id + -1] = A[1 * thread_x_id + -1][1 * thread_y_id + -1] + B[1 * thread_x_id + -1][1 * thread_y_id + -1];
}
}
int main()
{
int j_nom_4;
int i_nom_3;
int j_nom_2;
int i_nom_1;
int j;
int i;
/* Declare three arrays: C = A + B */
static float A[5000][5000];
static float B[5000][5000];
static float C[5000][5000];
/* Initialize */
for (i = 1; i <= 5000; i += 1) {
for (j = 1; j <= 5000; j += 1) {
A[1 * i + -1][1 * j + -1] = (sin((1 * i + -1 + (1 * j + -1))) * sin((1 * i + -1 + (1 * j + -1))));
B[1 * i + -1][1 * j + -1] = (cos((1 * i + -1 + (1 * j + -1))) * cos((1 * i + -1 + (1 * j + -1))));
}
}
{
/* Auto-generated code for call to _auto_kernel_0 */
typedef float _narray_A[5000];
_narray_A *d_A;
hipMalloc((void **) &d_A, sizeof(float ) * 5000 * 5000);
hipMemcpy(d_A, A, sizeof(float ) * 5000 * 5000, hipMemcpyHostToDevice);
typedef float _narray_B[5000];
_narray_B *d_B;
hipMalloc((void **) &d_B, sizeof(float ) * 5000 * 5000);
hipMemcpy(d_B, B, sizeof(float ) * 5000 * 5000, hipMemcpyHostToDevice);
typedef float _narray_C[5000];
_narray_C *d_C;
hipMalloc((void **) &d_C, sizeof(float ) * 5000 * 5000);
hipMemcpy(d_C, C, sizeof(float ) * 5000 * 5000, hipMemcpyHostToDevice);
int CUDA_GRID_X;
CUDA_GRID_X = (5000 + CUDA_BLOCK_X - 1)/CUDA_BLOCK_X;
int CUDA_GRID_Y;
CUDA_GRID_Y = (5000 + CUDA_BLOCK_Y - 1)/CUDA_BLOCK_Y;
int CUDA_GRID_Z;
CUDA_GRID_Z = (1 + CUDA_BLOCK_Z - 1)/CUDA_BLOCK_Z;
const dim3 CUDA_blockSize(CUDA_BLOCK_X, CUDA_BLOCK_Y, CUDA_BLOCK_Z);
const dim3 CUDA_gridSize(CUDA_GRID_X, CUDA_GRID_Y, CUDA_GRID_Z);
_auto_kernel_0<<<CUDA_gridSize,CUDA_blockSize>>>(d_A, d_B, d_C);
hipMemcpy(A, d_A, sizeof(float ) * 5000 * 5000, hipMemcpyDeviceToHost);
hipMemcpy(B, d_B, sizeof(float ) * 5000 * 5000, hipMemcpyDeviceToHost);
hipMemcpy(C, d_C, sizeof(float ) * 5000 * 5000, hipMemcpyDeviceToHost);
}
/* Check the result */
double sum = 0;
for (i_nom_3 = 1; i_nom_3 <= 5000; i_nom_3 += 1) {
for (j_nom_4 = 1; j_nom_4 <= 5000; j_nom_4 += 1) {
sum += C[1 * i_nom_3 + -1][1 * j_nom_4 + -1];
}
}
/* Report the result */
double r = (double )5000;
double c = (double )5000;
printf("Result (Should be close to 1.00) : %f\n",sum / (r * c));
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14_auto_kernel_0PA5000_fS0_S0_
.globl _Z14_auto_kernel_0PA5000_fS0_S0_
.p2align 8
.type _Z14_auto_kernel_0PA5000_fS0_S0_,@function
_Z14_auto_kernel_0PA5000_fS0_S0_:
s_load_b32 s2, s[0:1], 0x24
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_mad_u64_u32 v[0:1], null, s15, s2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e32 vcc_lo, 0, v2
v_max_i32_e32 v1, v2, v0
v_cmp_ne_u32_e64 s2, 0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e64 s3, 0x1389, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v4, -1, v2
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_mad_i64_i32 v[2:3], null, v4, 0x4e20, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v0, -4
v_add_co_ci_u32_e32 v7, vcc_lo, -1, v1, vcc_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, v0, v6
v_add_co_ci_u32_e32 v1, vcc_lo, v1, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, v4, v6
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v7, vcc_lo
global_load_b32 v0, v[0:1], off
global_load_b32 v1, v[4:5], off
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v4, v0, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, v2, v6
v_add_co_ci_u32_e32 v1, vcc_lo, v3, v7, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14_auto_kernel_0PA5000_fS0_S0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14_auto_kernel_0PA5000_fS0_S0_, .Lfunc_end0-_Z14_auto_kernel_0PA5000_fS0_S0_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14_auto_kernel_0PA5000_fS0_S0_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14_auto_kernel_0PA5000_fS0_S0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* Simple benchmark to test matrix addition */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#define ROWS 5000
#define COLS 5000
#define CUDA_BLOCK_X 128
#define CUDA_BLOCK_Y 1
#define CUDA_BLOCK_Z 1
__global__ void _auto_kernel_0(float A[5000][5000],float B[5000][5000],float C[5000][5000])
{
int thread_x_id;thread_x_id = blockIdx.x * blockDim.x + threadIdx.x;
int thread_y_id;thread_y_id = blockIdx.y * blockDim.y + threadIdx.y;
if (thread_x_id && thread_y_id)
if (thread_x_id <= 5000 && thread_y_id <= 5000) {
C[1 * thread_x_id + -1][1 * thread_y_id + -1] = A[1 * thread_x_id + -1][1 * thread_y_id + -1] + B[1 * thread_x_id + -1][1 * thread_y_id + -1];
}
}
int main()
{
int j_nom_4;
int i_nom_3;
int j_nom_2;
int i_nom_1;
int j;
int i;
/* Declare three arrays: C = A + B */
static float A[5000][5000];
static float B[5000][5000];
static float C[5000][5000];
/* Initialize */
for (i = 1; i <= 5000; i += 1) {
for (j = 1; j <= 5000; j += 1) {
A[1 * i + -1][1 * j + -1] = (sin((1 * i + -1 + (1 * j + -1))) * sin((1 * i + -1 + (1 * j + -1))));
B[1 * i + -1][1 * j + -1] = (cos((1 * i + -1 + (1 * j + -1))) * cos((1 * i + -1 + (1 * j + -1))));
}
}
{
/* Auto-generated code for call to _auto_kernel_0 */
typedef float _narray_A[5000];
_narray_A *d_A;
hipMalloc((void **) &d_A, sizeof(float ) * 5000 * 5000);
hipMemcpy(d_A, A, sizeof(float ) * 5000 * 5000, hipMemcpyHostToDevice);
typedef float _narray_B[5000];
_narray_B *d_B;
hipMalloc((void **) &d_B, sizeof(float ) * 5000 * 5000);
hipMemcpy(d_B, B, sizeof(float ) * 5000 * 5000, hipMemcpyHostToDevice);
typedef float _narray_C[5000];
_narray_C *d_C;
hipMalloc((void **) &d_C, sizeof(float ) * 5000 * 5000);
hipMemcpy(d_C, C, sizeof(float ) * 5000 * 5000, hipMemcpyHostToDevice);
int CUDA_GRID_X;
CUDA_GRID_X = (5000 + CUDA_BLOCK_X - 1)/CUDA_BLOCK_X;
int CUDA_GRID_Y;
CUDA_GRID_Y = (5000 + CUDA_BLOCK_Y - 1)/CUDA_BLOCK_Y;
int CUDA_GRID_Z;
CUDA_GRID_Z = (1 + CUDA_BLOCK_Z - 1)/CUDA_BLOCK_Z;
const dim3 CUDA_blockSize(CUDA_BLOCK_X, CUDA_BLOCK_Y, CUDA_BLOCK_Z);
const dim3 CUDA_gridSize(CUDA_GRID_X, CUDA_GRID_Y, CUDA_GRID_Z);
_auto_kernel_0<<<CUDA_gridSize,CUDA_blockSize>>>(d_A, d_B, d_C);
hipMemcpy(A, d_A, sizeof(float ) * 5000 * 5000, hipMemcpyDeviceToHost);
hipMemcpy(B, d_B, sizeof(float ) * 5000 * 5000, hipMemcpyDeviceToHost);
hipMemcpy(C, d_C, sizeof(float ) * 5000 * 5000, hipMemcpyDeviceToHost);
}
/* Check the result */
double sum = 0;
for (i_nom_3 = 1; i_nom_3 <= 5000; i_nom_3 += 1) {
for (j_nom_4 = 1; j_nom_4 <= 5000; j_nom_4 += 1) {
sum += C[1 * i_nom_3 + -1][1 * j_nom_4 + -1];
}
}
/* Report the result */
double r = (double )5000;
double c = (double )5000;
printf("Result (Should be close to 1.00) : %f\n",sum / (r * c));
return 0;
} | .text
.file "matrix_addition.hip"
.globl _Z29__device_stub___auto_kernel_0PA5000_fS0_S0_ # -- Begin function _Z29__device_stub___auto_kernel_0PA5000_fS0_S0_
.p2align 4, 0x90
.type _Z29__device_stub___auto_kernel_0PA5000_fS0_S0_,@function
_Z29__device_stub___auto_kernel_0PA5000_fS0_S0_: # @_Z29__device_stub___auto_kernel_0PA5000_fS0_S0_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14_auto_kernel_0PA5000_fS0_S0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z29__device_stub___auto_kernel_0PA5000_fS0_S0_, .Lfunc_end0-_Z29__device_stub___auto_kernel_0PA5000_fS0_S0_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x4177d78400000000 # double 2.5E+7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $136, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $1, %ebx
xorl %r14d, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_1: # %.preheader40
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
leal (%r14,%r12), %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
callq sin
movsd %xmm0, (%rsp) # 8-byte Spill
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq sin
mulsd (%rsp), %xmm0 # 8-byte Folded Reload
cvtsd2ss %xmm0, %xmm0
movss %xmm0, _ZZ4mainE1A(%r15,%r12,4)
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq cos
movsd %xmm0, (%rsp) # 8-byte Spill
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq cos
mulsd (%rsp), %xmm0 # 8-byte Folded Reload
cvtsd2ss %xmm0, %xmm0
movss %xmm0, _ZZ4mainE1B(%r15,%r12,4)
incq %r12
cmpq $5000, %r12 # imm = 0x1388
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %rbx
addq $20000, %r15 # imm = 0x4E20
incq %r14
cmpq $5001, %rbx # imm = 0x1389
jne .LBB1_1
# %bb.4:
leaq 32(%rsp), %rdi
movl $100000000, %esi # imm = 0x5F5E100
callq hipMalloc
movq 32(%rsp), %rdi
movl $_ZZ4mainE1A, %esi
movl $100000000, %edx # imm = 0x5F5E100
movl $1, %ecx
callq hipMemcpy
leaq 24(%rsp), %rdi
movl $100000000, %esi # imm = 0x5F5E100
callq hipMalloc
movq 24(%rsp), %rdi
movl $_ZZ4mainE1B, %esi
movl $100000000, %edx # imm = 0x5F5E100
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
movl $100000000, %esi # imm = 0x5F5E100
callq hipMalloc
movq 16(%rsp), %rdi
movl $_ZZ4mainE1C, %ebx
movl $_ZZ4mainE1C, %esi
movl $100000000, %edx # imm = 0x5F5E100
movl $1, %ecx
callq hipMemcpy
movabsq $21474836480040, %rdi # imm = 0x138800000028
movabsq $4294967424, %rdx # imm = 0x100000080
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z14_auto_kernel_0PA5000_fS0_S0_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 32(%rsp), %rsi
movl $_ZZ4mainE1A, %edi
movl $100000000, %edx # imm = 0x5F5E100
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rsi
movl $_ZZ4mainE1B, %edi
movl $100000000, %edx # imm = 0x5F5E100
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rsi
movl $_ZZ4mainE1C, %edi
movl $100000000, %edx # imm = 0x5F5E100
movl $2, %ecx
callq hipMemcpy
xorps %xmm0, %xmm0
movl $1, %eax
.p2align 4, 0x90
.LBB1_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_8: # Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
addsd %xmm1, %xmm0
incq %rcx
cmpq $5000, %rcx # imm = 0x1388
jne .LBB1_8
# %bb.9: # in Loop: Header=BB1_7 Depth=1
incq %rax
addq $20000, %rbx # imm = 0x4E20
cmpq $5001, %rax # imm = 0x1389
jne .LBB1_7
# %bb.10:
divsd .LCPI1_0(%rip), %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14_auto_kernel_0PA5000_fS0_S0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14_auto_kernel_0PA5000_fS0_S0_,@object # @_Z14_auto_kernel_0PA5000_fS0_S0_
.section .rodata,"a",@progbits
.globl _Z14_auto_kernel_0PA5000_fS0_S0_
.p2align 3, 0x0
_Z14_auto_kernel_0PA5000_fS0_S0_:
.quad _Z29__device_stub___auto_kernel_0PA5000_fS0_S0_
.size _Z14_auto_kernel_0PA5000_fS0_S0_, 8
.type _ZZ4mainE1A,@object # @_ZZ4mainE1A
.local _ZZ4mainE1A
.comm _ZZ4mainE1A,100000000,16
.type _ZZ4mainE1B,@object # @_ZZ4mainE1B
.local _ZZ4mainE1B
.comm _ZZ4mainE1B,100000000,16
.type _ZZ4mainE1C,@object # @_ZZ4mainE1C
.local _ZZ4mainE1C
.comm _ZZ4mainE1C,100000000,16
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Result (Should be close to 1.00) : %f\n"
.size .L.str, 39
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14_auto_kernel_0PA5000_fS0_S0_"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub___auto_kernel_0PA5000_fS0_S0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14_auto_kernel_0PA5000_fS0_S0_
.addrsig_sym _ZZ4mainE1A
.addrsig_sym _ZZ4mainE1B
.addrsig_sym _ZZ4mainE1C
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14_auto_kernel_0PA5000_fS0_S0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0070*/ IMAD R2, R2, c[0x0][0x4], R5 ; /* 0x0000010002027a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.EQ.OR P0, PT, R2, RZ, !P0 ; /* 0x000000ff0200720c */
/* 0x000fda0004702670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ ISETP.GT.AND P0, PT, R2, 0x1388, PT ; /* 0x000013880200780c */
/* 0x000fc80003f04270 */
/*00b0*/ ISETP.GT.OR P0, PT, R0, 0x1388, P0 ; /* 0x000013880000780c */
/* 0x000fda0000704670 */
/*00c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00d0*/ HFMA2.MMA R7, -RZ, RZ, 0, 24.5 ; /* 0x00004e20ff077435 */
/* 0x000fe200000001ff */
/*00e0*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*00f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0100*/ IADD3 R9, R2, -0x1, RZ ; /* 0xffffffff02097810 */
/* 0x000fce0007ffe0ff */
/*0110*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0207 */
/*0120*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*0130*/ IMAD.WIDE R2, R9, 0x4, R2 ; /* 0x0000000409027825 */
/* 0x000fc800078e0202 */
/*0140*/ IMAD.WIDE R4, R9, 0x4, R4 ; /* 0x0000000409047825 */
/* 0x000fe400078e0204 */
/*0150*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0160*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0170*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fcc00078e0207 */
/*0180*/ IMAD.WIDE R6, R9, 0x4, R6 ; /* 0x0000000409067825 */
/* 0x000fc800078e0206 */
/*0190*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*01a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14_auto_kernel_0PA5000_fS0_S0_
.globl _Z14_auto_kernel_0PA5000_fS0_S0_
.p2align 8
.type _Z14_auto_kernel_0PA5000_fS0_S0_,@function
_Z14_auto_kernel_0PA5000_fS0_S0_:
s_load_b32 s2, s[0:1], 0x24
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_mad_u64_u32 v[0:1], null, s15, s2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e32 vcc_lo, 0, v2
v_max_i32_e32 v1, v2, v0
v_cmp_ne_u32_e64 s2, 0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e64 s3, 0x1389, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v4, -1, v2
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_mad_i64_i32 v[2:3], null, v4, 0x4e20, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v0, -4
v_add_co_ci_u32_e32 v7, vcc_lo, -1, v1, vcc_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, v0, v6
v_add_co_ci_u32_e32 v1, vcc_lo, v1, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, v4, v6
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v7, vcc_lo
global_load_b32 v0, v[0:1], off
global_load_b32 v1, v[4:5], off
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v4, v0, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, v2, v6
v_add_co_ci_u32_e32 v1, vcc_lo, v3, v7, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14_auto_kernel_0PA5000_fS0_S0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14_auto_kernel_0PA5000_fS0_S0_, .Lfunc_end0-_Z14_auto_kernel_0PA5000_fS0_S0_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14_auto_kernel_0PA5000_fS0_S0_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14_auto_kernel_0PA5000_fS0_S0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009241c_00000000-6_matrix_addition.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z14_auto_kernel_0PA5000_fS0_S0_PA5000_fS0_S0_
.type _Z46__device_stub__Z14_auto_kernel_0PA5000_fS0_S0_PA5000_fS0_S0_, @function
_Z46__device_stub__Z14_auto_kernel_0PA5000_fS0_S0_PA5000_fS0_S0_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14_auto_kernel_0PA5000_fS0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z46__device_stub__Z14_auto_kernel_0PA5000_fS0_S0_PA5000_fS0_S0_, .-_Z46__device_stub__Z14_auto_kernel_0PA5000_fS0_S0_PA5000_fS0_S0_
.globl _Z14_auto_kernel_0PA5000_fS0_S0_
.type _Z14_auto_kernel_0PA5000_fS0_S0_, @function
_Z14_auto_kernel_0PA5000_fS0_S0_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z14_auto_kernel_0PA5000_fS0_S0_PA5000_fS0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z14_auto_kernel_0PA5000_fS0_S0_, .-_Z14_auto_kernel_0PA5000_fS0_S0_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Result (Should be close to 1.00) : %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
movl $5000, %r13d
leaq 24(%rsp), %r15
leaq 16(%rsp), %r14
.L12:
leal -5000(%r13), %ebx
movq 8(%rsp), %rax
leaq _ZZ4mainE1A(%rip), %rcx
leaq (%rax,%rcx), %r12
leaq _ZZ4mainE1B(%rip), %rcx
leaq (%rax,%rcx), %rbp
.L13:
pxor %xmm0, %xmm0
cvtsi2sdl %ebx, %xmm0
movq %r14, %rsi
movq %r15, %rdi
call sincos@PLT
movsd 16(%rsp), %xmm0
movsd 24(%rsp), %xmm1
mulsd %xmm1, %xmm1
cvtsd2ss %xmm1, %xmm1
movss %xmm1, (%r12)
mulsd %xmm0, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 0(%rbp)
addl $1, %ebx
addq $4, %r12
addq $4, %rbp
cmpl %r13d, %ebx
jne .L13
addl $1, %r13d
addq $20000, 8(%rsp)
cmpl $10000, %r13d
jne .L12
leaq 40(%rsp), %rdi
movl $100000000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $100000000, %edx
leaq _ZZ4mainE1A(%rip), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
leaq 48(%rsp), %rdi
movl $100000000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $100000000, %edx
leaq _ZZ4mainE1B(%rip), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
leaq 56(%rsp), %rdi
movl $100000000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $100000000, %edx
leaq _ZZ4mainE1C(%rip), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 64(%rsp)
movl $1, 68(%rsp)
movl $40, 76(%rsp)
movl $5000, 80(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 76(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L15:
movl $2, %ecx
movl $100000000, %edx
movq 40(%rsp), %rsi
leaq _ZZ4mainE1A(%rip), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $100000000, %edx
movq 48(%rsp), %rsi
leaq _ZZ4mainE1B(%rip), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $100000000, %edx
movq 56(%rsp), %rsi
leaq _ZZ4mainE1C(%rip), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 20000(%rbx), %rdx
leaq 100020000(%rbx), %rcx
pxor %xmm0, %xmm0
.L16:
leaq -20000(%rdx), %rax
.L17:
pxor %xmm1, %xmm1
cvtss2sd (%rax), %xmm1
addsd %xmm1, %xmm0
addq $4, %rax
cmpq %rdx, %rax
jne .L17
addq $20000, %rdx
cmpq %rcx, %rdx
jne .L16
divsd .LC1(%rip), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z46__device_stub__Z14_auto_kernel_0PA5000_fS0_S0_PA5000_fS0_S0_
jmp .L15
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC4:
.string "_Z14_auto_kernel_0PA5000_fS0_S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z14_auto_kernel_0PA5000_fS0_S0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZZ4mainE1C
.comm _ZZ4mainE1C,100000000,32
.local _ZZ4mainE1B
.comm _ZZ4mainE1B,100000000,32
.local _ZZ4mainE1A
.comm _ZZ4mainE1A,100000000,32
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1098372996
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrix_addition.hip"
.globl _Z29__device_stub___auto_kernel_0PA5000_fS0_S0_ # -- Begin function _Z29__device_stub___auto_kernel_0PA5000_fS0_S0_
.p2align 4, 0x90
.type _Z29__device_stub___auto_kernel_0PA5000_fS0_S0_,@function
_Z29__device_stub___auto_kernel_0PA5000_fS0_S0_: # @_Z29__device_stub___auto_kernel_0PA5000_fS0_S0_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14_auto_kernel_0PA5000_fS0_S0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z29__device_stub___auto_kernel_0PA5000_fS0_S0_, .Lfunc_end0-_Z29__device_stub___auto_kernel_0PA5000_fS0_S0_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x4177d78400000000 # double 2.5E+7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $136, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $1, %ebx
xorl %r14d, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_1: # %.preheader40
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
leal (%r14,%r12), %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
callq sin
movsd %xmm0, (%rsp) # 8-byte Spill
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq sin
mulsd (%rsp), %xmm0 # 8-byte Folded Reload
cvtsd2ss %xmm0, %xmm0
movss %xmm0, _ZZ4mainE1A(%r15,%r12,4)
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq cos
movsd %xmm0, (%rsp) # 8-byte Spill
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq cos
mulsd (%rsp), %xmm0 # 8-byte Folded Reload
cvtsd2ss %xmm0, %xmm0
movss %xmm0, _ZZ4mainE1B(%r15,%r12,4)
incq %r12
cmpq $5000, %r12 # imm = 0x1388
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %rbx
addq $20000, %r15 # imm = 0x4E20
incq %r14
cmpq $5001, %rbx # imm = 0x1389
jne .LBB1_1
# %bb.4:
leaq 32(%rsp), %rdi
movl $100000000, %esi # imm = 0x5F5E100
callq hipMalloc
movq 32(%rsp), %rdi
movl $_ZZ4mainE1A, %esi
movl $100000000, %edx # imm = 0x5F5E100
movl $1, %ecx
callq hipMemcpy
leaq 24(%rsp), %rdi
movl $100000000, %esi # imm = 0x5F5E100
callq hipMalloc
movq 24(%rsp), %rdi
movl $_ZZ4mainE1B, %esi
movl $100000000, %edx # imm = 0x5F5E100
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
movl $100000000, %esi # imm = 0x5F5E100
callq hipMalloc
movq 16(%rsp), %rdi
movl $_ZZ4mainE1C, %ebx
movl $_ZZ4mainE1C, %esi
movl $100000000, %edx # imm = 0x5F5E100
movl $1, %ecx
callq hipMemcpy
movabsq $21474836480040, %rdi # imm = 0x138800000028
movabsq $4294967424, %rdx # imm = 0x100000080
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z14_auto_kernel_0PA5000_fS0_S0_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 32(%rsp), %rsi
movl $_ZZ4mainE1A, %edi
movl $100000000, %edx # imm = 0x5F5E100
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rsi
movl $_ZZ4mainE1B, %edi
movl $100000000, %edx # imm = 0x5F5E100
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rsi
movl $_ZZ4mainE1C, %edi
movl $100000000, %edx # imm = 0x5F5E100
movl $2, %ecx
callq hipMemcpy
xorps %xmm0, %xmm0
movl $1, %eax
.p2align 4, 0x90
.LBB1_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_8: # Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
addsd %xmm1, %xmm0
incq %rcx
cmpq $5000, %rcx # imm = 0x1388
jne .LBB1_8
# %bb.9: # in Loop: Header=BB1_7 Depth=1
incq %rax
addq $20000, %rbx # imm = 0x4E20
cmpq $5001, %rax # imm = 0x1389
jne .LBB1_7
# %bb.10:
divsd .LCPI1_0(%rip), %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14_auto_kernel_0PA5000_fS0_S0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14_auto_kernel_0PA5000_fS0_S0_,@object # @_Z14_auto_kernel_0PA5000_fS0_S0_
.section .rodata,"a",@progbits
.globl _Z14_auto_kernel_0PA5000_fS0_S0_
.p2align 3, 0x0
_Z14_auto_kernel_0PA5000_fS0_S0_:
.quad _Z29__device_stub___auto_kernel_0PA5000_fS0_S0_
.size _Z14_auto_kernel_0PA5000_fS0_S0_, 8
.type _ZZ4mainE1A,@object # @_ZZ4mainE1A
.local _ZZ4mainE1A
.comm _ZZ4mainE1A,100000000,16
.type _ZZ4mainE1B,@object # @_ZZ4mainE1B
.local _ZZ4mainE1B
.comm _ZZ4mainE1B,100000000,16
.type _ZZ4mainE1C,@object # @_ZZ4mainE1C
.local _ZZ4mainE1C
.comm _ZZ4mainE1C,100000000,16
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Result (Should be close to 1.00) : %f\n"
.size .L.str, 39
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14_auto_kernel_0PA5000_fS0_S0_"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub___auto_kernel_0PA5000_fS0_S0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14_auto_kernel_0PA5000_fS0_S0_
.addrsig_sym _ZZ4mainE1A
.addrsig_sym _ZZ4mainE1B
.addrsig_sym _ZZ4mainE1C
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__device__ int getTid()
{
int bid = blockIdx.y * gridDim.x + blockIdx.x;
int tid = threadIdx.y * blockDim.x + threadIdx.x;
int tPB = blockDim.x * blockDim.y ;
int fin = bid*tPB+tid;
return fin;
}
__global__ void mulElement(int *a ,int *b , int *c , int ha ,int wa)
{
int th = getTid();
if(th<(ha*wa))
{
c[th] = a[th]+b[th];
}
}
int main(void)
{
int *a,*b,*t,i,j;
int *d_a,*d_b,*d_t;
int ha , wa;
printf("Enter the dimensions of first matrix \n ");
scanf("%d %d",&ha,&wa);
int size1 = sizeof(int)*ha*wa;
a = (int*)malloc(size1);
b = (int*)malloc(size1);
t = (int*)malloc(size1);
printf("Enter input matrix 1 : \n");
for(i = 0;i<ha*wa;i++)
scanf("%d",&a[i]);
printf("Enter input matrix 2 : \n");
for(i = 0;i<ha*wa;i++)
scanf("%d",&b[i]);
cudaMalloc((void**)&d_a,size1);
cudaMalloc((void**)&d_b,size1);
cudaMalloc((void**)&d_t,size1);
cudaMemcpy(d_a,a,size1,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,b,size1,cudaMemcpyHostToDevice);
int gx,gy,bx,by;
printf("Enter the dimension of the grid \n");
scanf("%d %d",&gx,&gy);
bx = ceil((double)ha/gx);
by = ceil((double)wa/gy);
printf("The dimensions of block are : \n %d %d \n",bx,by);
dim3 grid(gx,gy);
dim3 block(bx,by);
mulElement<<<grid,block>>>(d_a,d_b,d_t,ha,wa);
cudaMemcpy(t,d_t,size1,cudaMemcpyDeviceToHost);
printf("Result vector is :\n");
for(i = 0;i<ha;i++)
{
for(j = 0;j<wa;j++)
printf("%d ",t[i*wa+j]);
printf("\n");
}
getchar();
cudaFree(d_a);
cudaFree(d_t);
return 0;
} | code for sm_80
Function : _Z10mulElementPiS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002200 */
/*0060*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ea20000002100 */
/*0070*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0080*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x002fc800078e0205 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x004fca00078e0207 */
/*00a0*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00e0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00f0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0207 */
/*0100*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0207 */
/*0130*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*0140*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__device__ int getTid()
{
int bid = blockIdx.y * gridDim.x + blockIdx.x;
int tid = threadIdx.y * blockDim.x + threadIdx.x;
int tPB = blockDim.x * blockDim.y ;
int fin = bid*tPB+tid;
return fin;
}
__global__ void mulElement(int *a ,int *b , int *c , int ha ,int wa)
{
int th = getTid();
if(th<(ha*wa))
{
c[th] = a[th]+b[th];
}
}
int main(void)
{
int *a,*b,*t,i,j;
int *d_a,*d_b,*d_t;
int ha , wa;
printf("Enter the dimensions of first matrix \n ");
scanf("%d %d",&ha,&wa);
int size1 = sizeof(int)*ha*wa;
a = (int*)malloc(size1);
b = (int*)malloc(size1);
t = (int*)malloc(size1);
printf("Enter input matrix 1 : \n");
for(i = 0;i<ha*wa;i++)
scanf("%d",&a[i]);
printf("Enter input matrix 2 : \n");
for(i = 0;i<ha*wa;i++)
scanf("%d",&b[i]);
cudaMalloc((void**)&d_a,size1);
cudaMalloc((void**)&d_b,size1);
cudaMalloc((void**)&d_t,size1);
cudaMemcpy(d_a,a,size1,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,b,size1,cudaMemcpyHostToDevice);
int gx,gy,bx,by;
printf("Enter the dimension of the grid \n");
scanf("%d %d",&gx,&gy);
bx = ceil((double)ha/gx);
by = ceil((double)wa/gy);
printf("The dimensions of block are : \n %d %d \n",bx,by);
dim3 grid(gx,gy);
dim3 block(bx,by);
mulElement<<<grid,block>>>(d_a,d_b,d_t,ha,wa);
cudaMemcpy(t,d_t,size1,cudaMemcpyDeviceToHost);
printf("Result vector is :\n");
for(i = 0;i<ha;i++)
{
for(j = 0;j<wa;j++)
printf("%d ",t[i*wa+j]);
printf("\n");
}
getchar();
cudaFree(d_a);
cudaFree(d_t);
return 0;
} | .file "tmpxft_0004b99d_00000000-6_sample.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6getTidv
.type _Z6getTidv, @function
_Z6getTidv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z6getTidv, .-_Z6getTidv
.globl _Z36__device_stub__Z10mulElementPiS_S_iiPiS_S_ii
.type _Z36__device_stub__Z10mulElementPiS_S_iiPiS_S_ii, @function
_Z36__device_stub__Z10mulElementPiS_S_iiPiS_S_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10mulElementPiS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z36__device_stub__Z10mulElementPiS_S_iiPiS_S_ii, .-_Z36__device_stub__Z10mulElementPiS_S_iiPiS_S_ii
.globl _Z10mulElementPiS_S_ii
.type _Z10mulElementPiS_S_ii, @function
_Z10mulElementPiS_S_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z10mulElementPiS_S_iiPiS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z10mulElementPiS_S_ii, .-_Z10mulElementPiS_S_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Enter the dimensions of first matrix \n "
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%d %d"
.LC2:
.string "Enter input matrix 1 : \n"
.LC3:
.string "%d"
.LC4:
.string "Enter input matrix 2 : \n"
.section .rodata.str1.8
.align 8
.LC5:
.string "Enter the dimension of the grid \n"
.align 8
.LC9:
.string "The dimensions of block are : \n %d %d \n"
.section .rodata.str1.1
.LC10:
.string "Result vector is :\n"
.LC11:
.string "%d "
.LC12:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 28(%rsp), %rdx
leaq 24(%rsp), %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 28(%rsp), %r13d
imull 24(%rsp), %r13d
sall $2, %r13d
movslq %r13d, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %r14
movq %r13, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 24(%rsp), %eax
imull 28(%rsp), %eax
testl %eax, %eax
jle .L14
movq %r14, %r12
movl $0, %ebp
leaq .LC3(%rip), %r15
.L15:
movq %r12, %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebp
addq $4, %r12
movl 24(%rsp), %eax
imull 28(%rsp), %eax
cmpl %ebp, %eax
jg .L15
.L14:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 24(%rsp), %eax
imull 28(%rsp), %eax
testl %eax, %eax
jle .L16
movq 8(%rsp), %r12
movl $0, %ebp
leaq .LC3(%rip), %r15
.L17:
movq %r12, %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebp
addq $4, %r12
movl 24(%rsp), %eax
imull 28(%rsp), %eax
cmpl %ebp, %eax
jg .L17
.L16:
leaq 40(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %r14, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq 8(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 36(%rsp), %rdx
leaq 32(%rsp), %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
pxor %xmm0, %xmm0
cvtsi2sdl 24(%rsp), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdl 32(%rsp), %xmm1
divsd %xmm1, %xmm0
movapd %xmm0, %xmm3
movsd .LC13(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC6(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L18
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC8(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L18:
cvttsd2sil %xmm3, %ebp
pxor %xmm0, %xmm0
cvtsi2sdl 28(%rsp), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdl 36(%rsp), %xmm1
divsd %xmm1, %xmm0
movapd %xmm0, %xmm3
movsd .LC13(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC6(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L19
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC8(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L19:
cvttsd2sil %xmm3, %r12d
movl %r12d, %ecx
movl %ebp, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 32(%rsp), %eax
movl %eax, 64(%rsp)
movl 36(%rsp), %eax
movl %eax, 68(%rsp)
movl %ebp, 76(%rsp)
movl %r12d, 80(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L20:
movl $2, %ecx
movq %r13, %rdx
movq 56(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r12d
leaq .LC11(%rip), %r13
leaq .LC12(%rip), %r14
cmpl $0, 24(%rsp)
jg .L21
.L22:
movq stdin(%rip), %rdi
call getc@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L35
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movl 28(%rsp), %r8d
movl 24(%rsp), %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z36__device_stub__Z10mulElementPiS_S_iiPiS_S_ii
jmp .L20
.L23:
imull %r12d, %eax
addl %ebp, %eax
cltq
movl (%rbx,%rax,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebp
movl 28(%rsp), %eax
cmpl %ebp, %eax
jg .L23
.L24:
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r12d
cmpl %r12d, 24(%rsp)
jle .L22
.L21:
movl 28(%rsp), %eax
movl $0, %ebp
testl %eax, %eax
jg .L23
jmp .L24
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC14:
.string "_Z10mulElementPiS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z10mulElementPiS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC6:
.long 0
.long 1127219200
.align 8
.LC8:
.long 0
.long 1072693248
.align 8
.LC13:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__device__ int getTid()
{
int bid = blockIdx.y * gridDim.x + blockIdx.x;
int tid = threadIdx.y * blockDim.x + threadIdx.x;
int tPB = blockDim.x * blockDim.y ;
int fin = bid*tPB+tid;
return fin;
}
__global__ void mulElement(int *a ,int *b , int *c , int ha ,int wa)
{
int th = getTid();
if(th<(ha*wa))
{
c[th] = a[th]+b[th];
}
}
int main(void)
{
int *a,*b,*t,i,j;
int *d_a,*d_b,*d_t;
int ha , wa;
printf("Enter the dimensions of first matrix \n ");
scanf("%d %d",&ha,&wa);
int size1 = sizeof(int)*ha*wa;
a = (int*)malloc(size1);
b = (int*)malloc(size1);
t = (int*)malloc(size1);
printf("Enter input matrix 1 : \n");
for(i = 0;i<ha*wa;i++)
scanf("%d",&a[i]);
printf("Enter input matrix 2 : \n");
for(i = 0;i<ha*wa;i++)
scanf("%d",&b[i]);
cudaMalloc((void**)&d_a,size1);
cudaMalloc((void**)&d_b,size1);
cudaMalloc((void**)&d_t,size1);
cudaMemcpy(d_a,a,size1,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,b,size1,cudaMemcpyHostToDevice);
int gx,gy,bx,by;
printf("Enter the dimension of the grid \n");
scanf("%d %d",&gx,&gy);
bx = ceil((double)ha/gx);
by = ceil((double)wa/gy);
printf("The dimensions of block are : \n %d %d \n",bx,by);
dim3 grid(gx,gy);
dim3 block(bx,by);
mulElement<<<grid,block>>>(d_a,d_b,d_t,ha,wa);
cudaMemcpy(t,d_t,size1,cudaMemcpyDeviceToHost);
printf("Result vector is :\n");
for(i = 0;i<ha;i++)
{
for(j = 0;j<wa;j++)
printf("%d ",t[i*wa+j]);
printf("\n");
}
getchar();
cudaFree(d_a);
cudaFree(d_t);
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__device__ int getTid()
{
int bid = blockIdx.y * gridDim.x + blockIdx.x;
int tid = threadIdx.y * blockDim.x + threadIdx.x;
int tPB = blockDim.x * blockDim.y ;
int fin = bid*tPB+tid;
return fin;
}
__global__ void mulElement(int *a ,int *b , int *c , int ha ,int wa)
{
int th = getTid();
if(th<(ha*wa))
{
c[th] = a[th]+b[th];
}
}
int main(void)
{
int *a,*b,*t,i,j;
int *d_a,*d_b,*d_t;
int ha , wa;
printf("Enter the dimensions of first matrix \n ");
scanf("%d %d",&ha,&wa);
int size1 = sizeof(int)*ha*wa;
a = (int*)malloc(size1);
b = (int*)malloc(size1);
t = (int*)malloc(size1);
printf("Enter input matrix 1 : \n");
for(i = 0;i<ha*wa;i++)
scanf("%d",&a[i]);
printf("Enter input matrix 2 : \n");
for(i = 0;i<ha*wa;i++)
scanf("%d",&b[i]);
hipMalloc((void**)&d_a,size1);
hipMalloc((void**)&d_b,size1);
hipMalloc((void**)&d_t,size1);
hipMemcpy(d_a,a,size1,hipMemcpyHostToDevice);
hipMemcpy(d_b,b,size1,hipMemcpyHostToDevice);
int gx,gy,bx,by;
printf("Enter the dimension of the grid \n");
scanf("%d %d",&gx,&gy);
bx = ceil((double)ha/gx);
by = ceil((double)wa/gy);
printf("The dimensions of block are : \n %d %d \n",bx,by);
dim3 grid(gx,gy);
dim3 block(bx,by);
mulElement<<<grid,block>>>(d_a,d_b,d_t,ha,wa);
hipMemcpy(t,d_t,size1,hipMemcpyDeviceToHost);
printf("Result vector is :\n");
for(i = 0;i<ha;i++)
{
for(j = 0;j<wa;j++)
printf("%d ",t[i*wa+j]);
printf("\n");
}
getchar();
hipFree(d_a);
hipFree(d_t);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__device__ int getTid()
{
int bid = blockIdx.y * gridDim.x + blockIdx.x;
int tid = threadIdx.y * blockDim.x + threadIdx.x;
int tPB = blockDim.x * blockDim.y ;
int fin = bid*tPB+tid;
return fin;
}
__global__ void mulElement(int *a ,int *b , int *c , int ha ,int wa)
{
int th = getTid();
if(th<(ha*wa))
{
c[th] = a[th]+b[th];
}
}
int main(void)
{
int *a,*b,*t,i,j;
int *d_a,*d_b,*d_t;
int ha , wa;
printf("Enter the dimensions of first matrix \n ");
scanf("%d %d",&ha,&wa);
int size1 = sizeof(int)*ha*wa;
a = (int*)malloc(size1);
b = (int*)malloc(size1);
t = (int*)malloc(size1);
printf("Enter input matrix 1 : \n");
for(i = 0;i<ha*wa;i++)
scanf("%d",&a[i]);
printf("Enter input matrix 2 : \n");
for(i = 0;i<ha*wa;i++)
scanf("%d",&b[i]);
hipMalloc((void**)&d_a,size1);
hipMalloc((void**)&d_b,size1);
hipMalloc((void**)&d_t,size1);
hipMemcpy(d_a,a,size1,hipMemcpyHostToDevice);
hipMemcpy(d_b,b,size1,hipMemcpyHostToDevice);
int gx,gy,bx,by;
printf("Enter the dimension of the grid \n");
scanf("%d %d",&gx,&gy);
bx = ceil((double)ha/gx);
by = ceil((double)wa/gy);
printf("The dimensions of block are : \n %d %d \n",bx,by);
dim3 grid(gx,gy);
dim3 block(bx,by);
mulElement<<<grid,block>>>(d_a,d_b,d_t,ha,wa);
hipMemcpy(t,d_t,size1,hipMemcpyDeviceToHost);
printf("Result vector is :\n");
for(i = 0;i<ha;i++)
{
for(j = 0;j<wa;j++)
printf("%d ",t[i*wa+j]);
printf("\n");
}
getchar();
hipFree(d_a);
hipFree(d_t);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10mulElementPiS_S_ii
.globl _Z10mulElementPiS_S_ii
.p2align 8
.type _Z10mulElementPiS_S_ii,@function
_Z10mulElementPiS_S_ii:
s_load_b32 s4, s[0:1], 0x20
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_load_b32 s5, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_mul_i32 s6, s4, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s6, s6, s14
s_cmp_lt_u32 s14, s4
s_cselect_b32 s4, 12, 18
v_mov_b32_e32 v1, s4
global_load_u16 v4, v1, s[2:3]
s_load_b64 s[2:3], s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
s_lshr_b32 s4, s5, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s6, s4, v[1:2]
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s3, s2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v2, v4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10mulElementPiS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10mulElementPiS_S_ii, .Lfunc_end0-_Z10mulElementPiS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10mulElementPiS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10mulElementPiS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__device__ int getTid()
{
int bid = blockIdx.y * gridDim.x + blockIdx.x;
int tid = threadIdx.y * blockDim.x + threadIdx.x;
int tPB = blockDim.x * blockDim.y ;
int fin = bid*tPB+tid;
return fin;
}
__global__ void mulElement(int *a ,int *b , int *c , int ha ,int wa)
{
int th = getTid();
if(th<(ha*wa))
{
c[th] = a[th]+b[th];
}
}
int main(void)
{
int *a,*b,*t,i,j;
int *d_a,*d_b,*d_t;
int ha , wa;
printf("Enter the dimensions of first matrix \n ");
scanf("%d %d",&ha,&wa);
int size1 = sizeof(int)*ha*wa;
a = (int*)malloc(size1);
b = (int*)malloc(size1);
t = (int*)malloc(size1);
printf("Enter input matrix 1 : \n");
for(i = 0;i<ha*wa;i++)
scanf("%d",&a[i]);
printf("Enter input matrix 2 : \n");
for(i = 0;i<ha*wa;i++)
scanf("%d",&b[i]);
hipMalloc((void**)&d_a,size1);
hipMalloc((void**)&d_b,size1);
hipMalloc((void**)&d_t,size1);
hipMemcpy(d_a,a,size1,hipMemcpyHostToDevice);
hipMemcpy(d_b,b,size1,hipMemcpyHostToDevice);
int gx,gy,bx,by;
printf("Enter the dimension of the grid \n");
scanf("%d %d",&gx,&gy);
bx = ceil((double)ha/gx);
by = ceil((double)wa/gy);
printf("The dimensions of block are : \n %d %d \n",bx,by);
dim3 grid(gx,gy);
dim3 block(bx,by);
mulElement<<<grid,block>>>(d_a,d_b,d_t,ha,wa);
hipMemcpy(t,d_t,size1,hipMemcpyDeviceToHost);
printf("Result vector is :\n");
for(i = 0;i<ha;i++)
{
for(j = 0;j<wa;j++)
printf("%d ",t[i*wa+j]);
printf("\n");
}
getchar();
hipFree(d_a);
hipFree(d_t);
return 0;
} | .text
.file "sample.hip"
.globl _Z25__device_stub__mulElementPiS_S_ii # -- Begin function _Z25__device_stub__mulElementPiS_S_ii
.p2align 4, 0x90
.type _Z25__device_stub__mulElementPiS_S_ii,@function
_Z25__device_stub__mulElementPiS_S_ii: # @_Z25__device_stub__mulElementPiS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10mulElementPiS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__mulElementPiS_S_ii, .Lfunc_end0-_Z25__device_stub__mulElementPiS_S_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 12(%rsp), %rsi
leaq 8(%rsp), %rdx
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 12(%rsp), %eax
imull 8(%rsp), %eax
shll $2, %eax
movslq %eax, %r14
movq %r14, %rdi
callq malloc
movq %rax, %r12
movq %r14, %rdi
callq malloc
movq %rax, %r15
movq %r14, %rdi
callq malloc
movq %rax, %rbx
movl $.Lstr, %edi
callq puts@PLT
movl 8(%rsp), %eax
imull 12(%rsp), %eax
testl %eax, %eax
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movq %r12, %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.3, %edi
movq %r13, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %rbp
movslq 12(%rsp), %rax
movslq 8(%rsp), %rcx
imulq %rax, %rcx
addq $4, %r13
cmpq %rcx, %rbp
jl .LBB1_2
.LBB1_3: # %._crit_edge
movl $.Lstr.1, %edi
callq puts@PLT
movl 8(%rsp), %eax
imull 12(%rsp), %eax
testl %eax, %eax
jle .LBB1_6
# %bb.4: # %.lr.ph46.preheader
movq %r15, %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_5: # %.lr.ph46
# =>This Inner Loop Header: Depth=1
movl $.L.str.3, %edi
movq %r13, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %rbp
movslq 12(%rsp), %rax
movslq 8(%rsp), %rcx
imulq %rax, %rcx
addq $4, %r13
cmpq %rcx, %rbp
jl .LBB1_5
.LBB1_6: # %._crit_edge47
leaq 32(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl $.Lstr.2, %edi
callq puts@PLT
leaq 20(%rsp), %rsi
leaq 16(%rsp), %rdx
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
cvtsi2sdl 12(%rsp), %xmm0
cvtsi2sdl 20(%rsp), %xmm1
divsd %xmm1, %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %r15d
xorps %xmm0, %xmm0
cvtsi2sdl 8(%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdl 16(%rsp), %xmm1
divsd %xmm1, %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %r12d
movl $.L.str.6, %edi
movl %r15d, %esi
movl %r12d, %edx
xorl %eax, %eax
callq printf
movl 20(%rsp), %eax
movl 16(%rsp), %edi
shlq $32, %rdi
orq %rax, %rdi
shlq $32, %r12
orq %r15, %r12
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 32(%rsp), %rax
movq 48(%rsp), %rcx
movq 24(%rsp), %rdx
movl 12(%rsp), %esi
movl 8(%rsp), %edi
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl %esi, 44(%rsp)
movl %edi, 40(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 44(%rsp), %rax
movq %rax, 152(%rsp)
leaq 40(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z10mulElementPiS_S_ii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
movq 24(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.3, %edi
callq puts@PLT
cmpl $0, 12(%rsp)
jle .LBB1_14
# %bb.9: # %.preheader.preheader
xorl %ebp, %ebp
jmp .LBB1_10
.p2align 4, 0x90
.LBB1_13: # %._crit_edge50
# in Loop: Header=BB1_10 Depth=1
movl $10, %edi
callq putchar@PLT
incl %ebp
cmpl 12(%rsp), %ebp
jge .LBB1_14
.LBB1_10: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_12 Depth 2
movl 8(%rsp), %eax
testl %eax, %eax
jle .LBB1_13
# %bb.11: # %.lr.ph49.preheader
# in Loop: Header=BB1_10 Depth=1
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_12: # %.lr.ph49
# Parent Loop BB1_10 Depth=1
# => This Inner Loop Header: Depth=2
imull %ebp, %eax
cltq
addq %r14, %rax
movl (%rbx,%rax,4), %esi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movl 8(%rsp), %eax
incq %r14
cmpl %eax, %r14d
jl .LBB1_12
jmp .LBB1_13
.LBB1_14: # %._crit_edge52
movq stdin(%rip), %rdi
callq getc
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10mulElementPiS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10mulElementPiS_S_ii,@object # @_Z10mulElementPiS_S_ii
.section .rodata,"a",@progbits
.globl _Z10mulElementPiS_S_ii
.p2align 3, 0x0
_Z10mulElementPiS_S_ii:
.quad _Z25__device_stub__mulElementPiS_S_ii
.size _Z10mulElementPiS_S_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter the dimensions of first matrix \n "
.size .L.str, 40
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d %d"
.size .L.str.1, 6
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d"
.size .L.str.3, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "The dimensions of block are : \n %d %d \n"
.size .L.str.6, 40
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%d "
.size .L.str.8, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10mulElementPiS_S_ii"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Enter input matrix 1 : "
.size .Lstr, 24
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Enter input matrix 2 : "
.size .Lstr.1, 24
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Enter the dimension of the grid "
.size .Lstr.2, 33
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Result vector is :"
.size .Lstr.3, 19
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__mulElementPiS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10mulElementPiS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10mulElementPiS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002200 */
/*0060*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ea20000002100 */
/*0070*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0080*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x002fc800078e0205 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x004fca00078e0207 */
/*00a0*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00e0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00f0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0207 */
/*0100*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0207 */
/*0130*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*0140*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10mulElementPiS_S_ii
.globl _Z10mulElementPiS_S_ii
.p2align 8
.type _Z10mulElementPiS_S_ii,@function
_Z10mulElementPiS_S_ii:
s_load_b32 s4, s[0:1], 0x20
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_load_b32 s5, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_mul_i32 s6, s4, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s6, s6, s14
s_cmp_lt_u32 s14, s4
s_cselect_b32 s4, 12, 18
v_mov_b32_e32 v1, s4
global_load_u16 v4, v1, s[2:3]
s_load_b64 s[2:3], s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
s_lshr_b32 s4, s5, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s6, s4, v[1:2]
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s3, s2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v2, v4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10mulElementPiS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10mulElementPiS_S_ii, .Lfunc_end0-_Z10mulElementPiS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10mulElementPiS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10mulElementPiS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004b99d_00000000-6_sample.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6getTidv
.type _Z6getTidv, @function
_Z6getTidv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z6getTidv, .-_Z6getTidv
.globl _Z36__device_stub__Z10mulElementPiS_S_iiPiS_S_ii
.type _Z36__device_stub__Z10mulElementPiS_S_iiPiS_S_ii, @function
_Z36__device_stub__Z10mulElementPiS_S_iiPiS_S_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10mulElementPiS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z36__device_stub__Z10mulElementPiS_S_iiPiS_S_ii, .-_Z36__device_stub__Z10mulElementPiS_S_iiPiS_S_ii
.globl _Z10mulElementPiS_S_ii
.type _Z10mulElementPiS_S_ii, @function
_Z10mulElementPiS_S_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z10mulElementPiS_S_iiPiS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z10mulElementPiS_S_ii, .-_Z10mulElementPiS_S_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Enter the dimensions of first matrix \n "
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%d %d"
.LC2:
.string "Enter input matrix 1 : \n"
.LC3:
.string "%d"
.LC4:
.string "Enter input matrix 2 : \n"
.section .rodata.str1.8
.align 8
.LC5:
.string "Enter the dimension of the grid \n"
.align 8
.LC9:
.string "The dimensions of block are : \n %d %d \n"
.section .rodata.str1.1
.LC10:
.string "Result vector is :\n"
.LC11:
.string "%d "
.LC12:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 28(%rsp), %rdx
leaq 24(%rsp), %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 28(%rsp), %r13d
imull 24(%rsp), %r13d
sall $2, %r13d
movslq %r13d, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %r14
movq %r13, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 24(%rsp), %eax
imull 28(%rsp), %eax
testl %eax, %eax
jle .L14
movq %r14, %r12
movl $0, %ebp
leaq .LC3(%rip), %r15
.L15:
movq %r12, %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebp
addq $4, %r12
movl 24(%rsp), %eax
imull 28(%rsp), %eax
cmpl %ebp, %eax
jg .L15
.L14:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 24(%rsp), %eax
imull 28(%rsp), %eax
testl %eax, %eax
jle .L16
movq 8(%rsp), %r12
movl $0, %ebp
leaq .LC3(%rip), %r15
.L17:
movq %r12, %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebp
addq $4, %r12
movl 24(%rsp), %eax
imull 28(%rsp), %eax
cmpl %ebp, %eax
jg .L17
.L16:
leaq 40(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %r14, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq 8(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 36(%rsp), %rdx
leaq 32(%rsp), %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
pxor %xmm0, %xmm0
cvtsi2sdl 24(%rsp), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdl 32(%rsp), %xmm1
divsd %xmm1, %xmm0
movapd %xmm0, %xmm3
movsd .LC13(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC6(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L18
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC8(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L18:
cvttsd2sil %xmm3, %ebp
pxor %xmm0, %xmm0
cvtsi2sdl 28(%rsp), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdl 36(%rsp), %xmm1
divsd %xmm1, %xmm0
movapd %xmm0, %xmm3
movsd .LC13(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC6(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L19
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC8(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L19:
cvttsd2sil %xmm3, %r12d
movl %r12d, %ecx
movl %ebp, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 32(%rsp), %eax
movl %eax, 64(%rsp)
movl 36(%rsp), %eax
movl %eax, 68(%rsp)
movl %ebp, 76(%rsp)
movl %r12d, 80(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L20:
movl $2, %ecx
movq %r13, %rdx
movq 56(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r12d
leaq .LC11(%rip), %r13
leaq .LC12(%rip), %r14
cmpl $0, 24(%rsp)
jg .L21
.L22:
movq stdin(%rip), %rdi
call getc@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L35
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movl 28(%rsp), %r8d
movl 24(%rsp), %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z36__device_stub__Z10mulElementPiS_S_iiPiS_S_ii
jmp .L20
.L23:
imull %r12d, %eax
addl %ebp, %eax
cltq
movl (%rbx,%rax,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebp
movl 28(%rsp), %eax
cmpl %ebp, %eax
jg .L23
.L24:
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r12d
cmpl %r12d, 24(%rsp)
jle .L22
.L21:
movl 28(%rsp), %eax
movl $0, %ebp
testl %eax, %eax
jg .L23
jmp .L24
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC14:
.string "_Z10mulElementPiS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z10mulElementPiS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC6:
.long 0
.long 1127219200
.align 8
.LC8:
.long 0
.long 1072693248
.align 8
.LC13:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sample.hip"
.globl _Z25__device_stub__mulElementPiS_S_ii # -- Begin function _Z25__device_stub__mulElementPiS_S_ii
.p2align 4, 0x90
.type _Z25__device_stub__mulElementPiS_S_ii,@function
_Z25__device_stub__mulElementPiS_S_ii: # @_Z25__device_stub__mulElementPiS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10mulElementPiS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__mulElementPiS_S_ii, .Lfunc_end0-_Z25__device_stub__mulElementPiS_S_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 12(%rsp), %rsi
leaq 8(%rsp), %rdx
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 12(%rsp), %eax
imull 8(%rsp), %eax
shll $2, %eax
movslq %eax, %r14
movq %r14, %rdi
callq malloc
movq %rax, %r12
movq %r14, %rdi
callq malloc
movq %rax, %r15
movq %r14, %rdi
callq malloc
movq %rax, %rbx
movl $.Lstr, %edi
callq puts@PLT
movl 8(%rsp), %eax
imull 12(%rsp), %eax
testl %eax, %eax
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movq %r12, %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.3, %edi
movq %r13, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %rbp
movslq 12(%rsp), %rax
movslq 8(%rsp), %rcx
imulq %rax, %rcx
addq $4, %r13
cmpq %rcx, %rbp
jl .LBB1_2
.LBB1_3: # %._crit_edge
movl $.Lstr.1, %edi
callq puts@PLT
movl 8(%rsp), %eax
imull 12(%rsp), %eax
testl %eax, %eax
jle .LBB1_6
# %bb.4: # %.lr.ph46.preheader
movq %r15, %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_5: # %.lr.ph46
# =>This Inner Loop Header: Depth=1
movl $.L.str.3, %edi
movq %r13, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %rbp
movslq 12(%rsp), %rax
movslq 8(%rsp), %rcx
imulq %rax, %rcx
addq $4, %r13
cmpq %rcx, %rbp
jl .LBB1_5
.LBB1_6: # %._crit_edge47
leaq 32(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl $.Lstr.2, %edi
callq puts@PLT
leaq 20(%rsp), %rsi
leaq 16(%rsp), %rdx
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
cvtsi2sdl 12(%rsp), %xmm0
cvtsi2sdl 20(%rsp), %xmm1
divsd %xmm1, %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %r15d
xorps %xmm0, %xmm0
cvtsi2sdl 8(%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdl 16(%rsp), %xmm1
divsd %xmm1, %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %r12d
movl $.L.str.6, %edi
movl %r15d, %esi
movl %r12d, %edx
xorl %eax, %eax
callq printf
movl 20(%rsp), %eax
movl 16(%rsp), %edi
shlq $32, %rdi
orq %rax, %rdi
shlq $32, %r12
orq %r15, %r12
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 32(%rsp), %rax
movq 48(%rsp), %rcx
movq 24(%rsp), %rdx
movl 12(%rsp), %esi
movl 8(%rsp), %edi
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl %esi, 44(%rsp)
movl %edi, 40(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 44(%rsp), %rax
movq %rax, 152(%rsp)
leaq 40(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z10mulElementPiS_S_ii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
movq 24(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.3, %edi
callq puts@PLT
cmpl $0, 12(%rsp)
jle .LBB1_14
# %bb.9: # %.preheader.preheader
xorl %ebp, %ebp
jmp .LBB1_10
.p2align 4, 0x90
.LBB1_13: # %._crit_edge50
# in Loop: Header=BB1_10 Depth=1
movl $10, %edi
callq putchar@PLT
incl %ebp
cmpl 12(%rsp), %ebp
jge .LBB1_14
.LBB1_10: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_12 Depth 2
movl 8(%rsp), %eax
testl %eax, %eax
jle .LBB1_13
# %bb.11: # %.lr.ph49.preheader
# in Loop: Header=BB1_10 Depth=1
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_12: # %.lr.ph49
# Parent Loop BB1_10 Depth=1
# => This Inner Loop Header: Depth=2
imull %ebp, %eax
cltq
addq %r14, %rax
movl (%rbx,%rax,4), %esi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movl 8(%rsp), %eax
incq %r14
cmpl %eax, %r14d
jl .LBB1_12
jmp .LBB1_13
.LBB1_14: # %._crit_edge52
movq stdin(%rip), %rdi
callq getc
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10mulElementPiS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10mulElementPiS_S_ii,@object # @_Z10mulElementPiS_S_ii
.section .rodata,"a",@progbits
.globl _Z10mulElementPiS_S_ii
.p2align 3, 0x0
_Z10mulElementPiS_S_ii:
.quad _Z25__device_stub__mulElementPiS_S_ii
.size _Z10mulElementPiS_S_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter the dimensions of first matrix \n "
.size .L.str, 40
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d %d"
.size .L.str.1, 6
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d"
.size .L.str.3, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "The dimensions of block are : \n %d %d \n"
.size .L.str.6, 40
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%d "
.size .L.str.8, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10mulElementPiS_S_ii"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Enter input matrix 1 : "
.size .Lstr, 24
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Enter input matrix 2 : "
.size .Lstr.1, 24
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Enter the dimension of the grid "
.size .Lstr.2, 33
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Result vector is :"
.size .Lstr.3, 19
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__mulElementPiS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10mulElementPiS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <cstring>
#include <algorithm>
using namespace std;
int a[35];
//【方法1】排序後取中間那一個。
int median(int i){
int b[3] = {a[i-1], a[i-2], a[i-3]};
sort(b, b+3);
return b[1];
}
int main() {
ios_base::sync_with_stdio(false);
cin.tie(0);
int n;
while (cin >> n){
for (int i=0; i<n; i++){
cin >> a[i];
}
for (int i=3; i<n; i++){
if (abs(a[i] - a[i-1]) < 5) continue;
a[i] = median(i);
}
for (int i=0; i<n; i++)
cout << a[i] << ' ';
cout << '\n';
}
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <cstring>
#include <algorithm>
using namespace std;
int a[35];
//【方法1】排序後取中間那一個。
int median(int i){
int b[3] = {a[i-1], a[i-2], a[i-3]};
sort(b, b+3);
return b[1];
}
int main() {
ios_base::sync_with_stdio(false);
cin.tie(0);
int n;
while (cin >> n){
for (int i=0; i<n; i++){
cin >> a[i];
}
for (int i=3; i<n; i++){
if (abs(a[i] - a[i-1]) < 5) continue;
a[i] = median(i);
}
for (int i=0; i<n; i++)
cout << a[i] << ' ';
cout << '\n';
}
return 0;
} | .file "tmpxft_000f40b1_00000000-6_Untitled-1.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3927:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3927:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3950:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3950:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZSt25__unguarded_linear_insertIPiN9__gnu_cxx5__ops14_Val_less_iterEEvT_T0_,"axG",@progbits,_ZSt25__unguarded_linear_insertIPiN9__gnu_cxx5__ops14_Val_less_iterEEvT_T0_,comdat
.weak _ZSt25__unguarded_linear_insertIPiN9__gnu_cxx5__ops14_Val_less_iterEEvT_T0_
.type _ZSt25__unguarded_linear_insertIPiN9__gnu_cxx5__ops14_Val_less_iterEEvT_T0_, @function
_ZSt25__unguarded_linear_insertIPiN9__gnu_cxx5__ops14_Val_less_iterEEvT_T0_:
.LFB4578:
.cfi_startproc
endbr64
movl (%rdi), %ecx
leaq -4(%rdi), %rax
movl -4(%rdi), %edx
cmpl %edx, %ecx
jge .L6
.L7:
movl %edx, 4(%rax)
movq %rax, %rdi
subq $4, %rax
movl (%rax), %edx
cmpl %edx, %ecx
jl .L7
.L6:
movl %ecx, (%rdi)
ret
.cfi_endproc
.LFE4578:
.size _ZSt25__unguarded_linear_insertIPiN9__gnu_cxx5__ops14_Val_less_iterEEvT_T0_, .-_ZSt25__unguarded_linear_insertIPiN9__gnu_cxx5__ops14_Val_less_iterEEvT_T0_
.section .text._ZSt16__insertion_sortIPiN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_,"axG",@progbits,_ZSt16__insertion_sortIPiN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_,comdat
.weak _ZSt16__insertion_sortIPiN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_
.type _ZSt16__insertion_sortIPiN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_, @function
_ZSt16__insertion_sortIPiN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_:
.LFB4548:
.cfi_startproc
endbr64
cmpq %rsi, %rdi
je .L18
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %rbp
movq %rsi, %r13
leaq 4(%rdi), %rbx
cmpq %rbx, %rsi
je .L9
movl $4, %r14d
jmp .L15
.L12:
je .L21
.L13:
movl %r12d, 0(%rbp)
.L14:
addq $4, %rbx
cmpq %rbx, %r13
je .L9
.L15:
movl (%rbx), %r12d
movl 0(%rbp), %eax
cmpl %r12d, %eax
jle .L11
movq %rbx, %rdx
subq %rbp, %rdx
cmpq $4, %rdx
jle .L12
movq %r14, %rdi
subq %rdx, %rdi
addq %rbx, %rdi
movq %rbp, %rsi
call memmove@PLT
jmp .L13
.L21:
movl %eax, (%rbx)
jmp .L13
.L11:
movq %rbx, %rdi
call _ZSt25__unguarded_linear_insertIPiN9__gnu_cxx5__ops14_Val_less_iterEEvT_T0_
jmp .L14
.L9:
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
ret
.cfi_endproc
.LFE4548:
.size _ZSt16__insertion_sortIPiN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_, .-_ZSt16__insertion_sortIPiN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_
.section .text._ZSt13__adjust_heapIPiliN9__gnu_cxx5__ops15_Iter_less_iterEEvT_T0_S5_T1_T2_,"axG",@progbits,_ZSt13__adjust_heapIPiliN9__gnu_cxx5__ops15_Iter_less_iterEEvT_T0_S5_T1_T2_,comdat
.weak _ZSt13__adjust_heapIPiliN9__gnu_cxx5__ops15_Iter_less_iterEEvT_T0_S5_T1_T2_
.type _ZSt13__adjust_heapIPiliN9__gnu_cxx5__ops15_Iter_less_iterEEvT_T0_S5_T1_T2_, @function
_ZSt13__adjust_heapIPiliN9__gnu_cxx5__ops15_Iter_less_iterEEvT_T0_S5_T1_T2_:
.LFB4600:
.cfi_startproc
endbr64
movq %rsi, %r8
movl %ecx, %r9d
leaq -1(%rdx), %rax
movq %rax, %r10
shrq $63, %r10
addq %rax, %r10
sarq %r10
cmpq %r10, %rsi
jl .L25
movq %rsi, %rax
testb $1, %dl
jne .L27
movq %r8, %rax
jmp .L29
.L24:
movl (%rdi,%rax,4), %ecx
movl %ecx, (%rdi,%rsi,4)
cmpq %r10, %rax
jge .L34
movq %rax, %rsi
.L25:
leaq 1(%rsi), %rcx
leaq (%rcx,%rcx), %rax
movl -4(%rdi,%rcx,8), %r11d
cmpl %r11d, (%rdi,%rcx,8)
jge .L24
subq $1, %rax
jmp .L24
.L34:
testb $1, %dl
jne .L26
.L29:
subq $2, %rdx
movq %rdx, %rcx
shrq $63, %rcx
addq %rcx, %rdx
sarq %rdx
cmpq %rax, %rdx
je .L35
.L26:
leaq -1(%rax), %rdx
movq %rdx, %rcx
shrq $63, %rcx
addq %rdx, %rcx
sarq %rcx
cmpq %r8, %rax
jg .L28
jmp .L27
.L35:
leaq 2(%rax,%rax), %rdx
movl -4(%rdi,%rdx,4), %ecx
movl %ecx, (%rdi,%rax,4)
leaq -1(%rdx), %rax
jmp .L26
.L31:
movq %rdx, %rcx
.L28:
movl (%rdi,%rcx,4), %edx
cmpl %edx, %r9d
jle .L27
movl %edx, (%rdi,%rax,4)
leaq -1(%rcx), %rdx
movq %rdx, %rax
shrq $63, %rax
addq %rdx, %rax
sarq %rax
movq %rax, %rdx
movq %rcx, %rax
cmpq %rcx, %r8
jl .L31
.L27:
movl %r9d, (%rdi,%rax,4)
ret
.cfi_endproc
.LFE4600:
.size _ZSt13__adjust_heapIPiliN9__gnu_cxx5__ops15_Iter_less_iterEEvT_T0_S5_T1_T2_, .-_ZSt13__adjust_heapIPiliN9__gnu_cxx5__ops15_Iter_less_iterEEvT_T0_S5_T1_T2_
.section .text._ZSt16__introsort_loopIPilN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_T1_,"axG",@progbits,_ZSt16__introsort_loopIPilN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_T1_,comdat
.weak _ZSt16__introsort_loopIPilN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_T1_
.type _ZSt16__introsort_loopIPilN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_T1_, @function
_ZSt16__introsort_loopIPilN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_T1_:
.LFB4484:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
movq %rsi, %rax
subq %rdi, %rax
cmpq $64, %rax
jle .L36
movq %rsi, %rdi
movq %rdx, %r12
testq %rdx, %rdx
jne .L39
movq %rdi, %rbx
.L56:
sarq $2, %rax
movq %rax, %r12
leaq -2(%rax), %rax
movq %rax, %r13
shrq $63, %r13
addq %rax, %r13
sarq %r13
jmp .L40
.L64:
subq $1, %r13
.L40:
movl 0(%rbp,%r13,4), %ecx
movq %r12, %rdx
movq %r13, %rsi
movq %rbp, %rdi
call _ZSt13__adjust_heapIPiliN9__gnu_cxx5__ops15_Iter_less_iterEEvT_T0_S5_T1_T2_
testq %r13, %r13
jne .L64
movq %rbx, %rax
subq %rbp, %rax
cmpq $4, %rax
jle .L36
.L41:
subq $4, %rbx
movl (%rbx), %ecx
movl 0(%rbp), %eax
movl %eax, (%rbx)
movq %rbx, %r12
subq %rbp, %r12
movq %r12, %rdx
sarq $2, %rdx
movl $0, %esi
movq %rbp, %rdi
call _ZSt13__adjust_heapIPiliN9__gnu_cxx5__ops15_Iter_less_iterEEvT_T0_S5_T1_T2_
cmpq $4, %r12
jg .L41
.L36:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
cmpl %esi, %edx
jge .L46
movl 0(%rbp), %eax
movl %esi, 0(%rbp)
movl %eax, -4(%rdi)
jmp .L47
.L46:
movl 0(%rbp), %eax
movl %edx, 0(%rbp)
movl %eax, 4(%rbp)
jmp .L47
.L43:
movl -4(%rdi), %esi
cmpl %esi, %edx
jge .L48
movl 0(%rbp), %eax
movl %edx, 0(%rbp)
movl %eax, 4(%rbp)
jmp .L47
.L48:
cmpl %esi, %eax
jge .L49
movl 0(%rbp), %eax
movl %esi, 0(%rbp)
movl %eax, -4(%rdi)
jmp .L47
.L49:
movl 0(%rbp), %edx
movl %eax, 0(%rbp)
movl %edx, (%rcx)
jmp .L47
.L65:
movq %r12, %rdx
movq %rdi, %rsi
movq %rbx, %rdi
call _ZSt16__introsort_loopIPilN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_T1_
movq %rbx, %rax
subq %rbp, %rax
cmpq $64, %rax
jle .L36
testq %r12, %r12
je .L56
movq %rbx, %rdi
.L39:
subq $1, %r12
movq %rax, %rdx
sarq $2, %rdx
shrq $63, %rax
addq %rdx, %rax
sarq %rax
leaq 0(%rbp,%rax,4), %rcx
leaq 4(%rbp), %rbx
movl 4(%rbp), %edx
movl (%rcx), %eax
cmpl %eax, %edx
jge .L43
movl -4(%rdi), %esi
cmpl %esi, %eax
jge .L44
movl 0(%rbp), %edx
movl %eax, 0(%rbp)
movl %edx, (%rcx)
.L47:
movq %rdi, %rsi
.L45:
movl (%rbx), %ecx
movl 0(%rbp), %edx
cmpl %edx, %ecx
jge .L50
.L51:
addq $4, %rbx
movl (%rbx), %ecx
cmpl %edx, %ecx
jl .L51
.L50:
leaq -4(%rsi), %rax
movl -4(%rsi), %esi
cmpl %edx, %esi
jle .L52
.L53:
subq $4, %rax
movl (%rax), %esi
cmpl %edx, %esi
jg .L53
.L52:
cmpq %rax, %rbx
jnb .L65
movl %esi, (%rbx)
movl %ecx, (%rax)
addq $4, %rbx
movq %rax, %rsi
jmp .L45
.cfi_endproc
.LFE4484:
.size _ZSt16__introsort_loopIPilN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_T1_, .-_ZSt16__introsort_loopIPilN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_T1_
.text
.globl _Z6mediani
.type _Z6mediani, @function
_Z6mediani:
.LFB3923:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq a(%rip), %rax
leal -1(%rdi), %edx
movslq %edx, %rdx
movl (%rax,%rdx,4), %edx
movl %edx, 12(%rsp)
leal -2(%rdi), %edx
movslq %edx, %rdx
movl (%rax,%rdx,4), %edx
movl %edx, 16(%rsp)
subl $3, %edi
movslq %edi, %rdi
movl (%rax,%rdi,4), %eax
movl %eax, 20(%rsp)
leaq 12(%rsp), %rbx
leaq 24(%rsp), %rbp
movl $2, %edx
movq %rbp, %rsi
movq %rbx, %rdi
call _ZSt16__introsort_loopIPilN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_T1_
movq %rbp, %rsi
movq %rbx, %rdi
call _ZSt16__insertion_sortIPiN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_
movl 16(%rsp), %eax
movq 24(%rsp), %rdx
subq %fs:40, %rdx
jne .L69
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L69:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3923:
.size _Z6mediani, .-_Z6mediani
.globl main
.type main, @function
main:
.LFB3924:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $16, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movl $0, %edi
call _ZNSt8ios_base15sync_with_stdioEb@PLT
movq $0, 232+_ZSt3cin(%rip)
leaq _ZSt3cin(%rip), %rbp
leaq a(%rip), %r13
leaq 3(%rsp), %r14
jmp .L71
.L74:
addl $1, %r12d
addq $4, %rbx
cmpl %r12d, 4(%rsp)
jle .L73
.L75:
movl (%rbx), %eax
subl -4(%rbx), %eax
addl $4, %eax
cmpl $8, %eax
jbe .L74
movl %r12d, %edi
call _Z6mediani
movl %eax, (%rbx)
jmp .L74
.L73:
cmpl $0, 4(%rsp)
jle .L76
movl $0, %ebx
leaq _ZSt4cout(%rip), %r12
jmp .L79
.L77:
movl $32, %esi
call _ZNSo3putEc@PLT
.L78:
addq $1, %rbx
cmpl %ebx, 4(%rsp)
jle .L76
.L79:
movl 0(%r13,%rbx,4), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movb $32, 3(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L77
movl $1, %edx
movq %r14, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L78
.L76:
movb $10, 3(%rsp)
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
cmpq $0, 16(%rdx,%rax)
je .L80
movl $1, %edx
movq %r14, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L71:
leaq 4(%rsp), %rsi
movq %rbp, %rdi
call _ZNSirsERi@PLT
movq (%rax), %rdx
movq -24(%rdx), %rdx
movl 32(%rax,%rdx), %ebx
andl $5, %ebx
jne .L82
leaq a(%rip), %r12
cmpl $0, 4(%rsp)
jle .L76
.L72:
movq %r12, %rsi
movq %rbp, %rdi
call _ZNSirsERi@PLT
addl $1, %ebx
movl 4(%rsp), %eax
addq $4, %r12
cmpl %ebx, %eax
jg .L72
cmpl $3, %eax
jle .L73
leaq 12+a(%rip), %rbx
movl $3, %r12d
jmp .L75
.L80:
movl $10, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
jmp .L71
.L82:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L90
movl $0, %eax
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L90:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3924:
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl a
.bss
.align 32
.type a, @object
.size a, 140
a:
.zero 140
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cstring>
#include <algorithm>
using namespace std;
int a[35];
//【方法1】排序後取中間那一個。
int median(int i){
int b[3] = {a[i-1], a[i-2], a[i-3]};
sort(b, b+3);
return b[1];
}
int main() {
ios_base::sync_with_stdio(false);
cin.tie(0);
int n;
while (cin >> n){
for (int i=0; i<n; i++){
cin >> a[i];
}
for (int i=3; i<n; i++){
if (abs(a[i] - a[i-1]) < 5) continue;
a[i] = median(i);
}
for (int i=0; i<n; i++)
cout << a[i] << ' ';
cout << '\n';
}
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstring>
#include <algorithm>
using namespace std;
int a[35];
//【方法1】排序後取中間那一個。
int median(int i){
int b[3] = {a[i-1], a[i-2], a[i-3]};
sort(b, b+3);
return b[1];
}
int main() {
ios_base::sync_with_stdio(false);
cin.tie(0);
int n;
while (cin >> n){
for (int i=0; i<n; i++){
cin >> a[i];
}
for (int i=3; i<n; i++){
if (abs(a[i] - a[i-1]) < 5) continue;
a[i] = median(i);
}
for (int i=0; i<n; i++)
cout << a[i] << ' ';
cout << '\n';
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstring>
#include <algorithm>
using namespace std;
int a[35];
//【方法1】排序後取中間那一個。
int median(int i){
int b[3] = {a[i-1], a[i-2], a[i-3]};
sort(b, b+3);
return b[1];
}
int main() {
ios_base::sync_with_stdio(false);
cin.tie(0);
int n;
while (cin >> n){
for (int i=0; i<n; i++){
cin >> a[i];
}
for (int i=3; i<n; i++){
if (abs(a[i] - a[i-1]) < 5) continue;
a[i] = median(i);
}
for (int i=0; i<n; i++)
cout << a[i] << ' ';
cout << '\n';
}
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstring>
#include <algorithm>
using namespace std;
int a[35];
//【方法1】排序後取中間那一個。
int median(int i){
int b[3] = {a[i-1], a[i-2], a[i-3]};
sort(b, b+3);
return b[1];
}
int main() {
ios_base::sync_with_stdio(false);
cin.tie(0);
int n;
while (cin >> n){
for (int i=0; i<n; i++){
cin >> a[i];
}
for (int i=3; i<n; i++){
if (abs(a[i] - a[i-1]) < 5) continue;
a[i] = median(i);
}
for (int i=0; i<n; i++)
cout << a[i] << ' ';
cout << '\n';
}
return 0;
} | .text
.file "Untitled-1.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z6mediani # -- Begin function _Z6mediani
.p2align 4, 0x90
.type _Z6mediani,@function
_Z6mediani: # @_Z6mediani
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movslq %edi, %rax
movl a-4(,%rax,4), %ecx
movl %ecx, 12(%rsp)
leaq 16(%rsp), %rbx
movl a-8(,%rax,4), %ecx
movl %ecx, 16(%rsp)
movl a-12(,%rax,4), %eax
movl %eax, 20(%rsp)
leaq 12(%rsp), %r14
movl $4, %r15d
movq %rbx, %r12
movq %r14, %rax
jmp .LBB0_1
.p2align 4, 0x90
.LBB0_10: # %_ZSt25__unguarded_linear_insertIPiN9__gnu_cxx5__ops14_Val_less_iterEEvT_T0_.exit.i19.i
# in Loop: Header=BB0_1 Depth=1
movl %ebp, (%rcx)
.LBB0_11: # in Loop: Header=BB0_1 Depth=1
addq $4, %r15
addq $4, %r12
movq %r13, %rax
cmpq $12, %r15
je .LBB0_12
.LBB0_1: # %.lr.ph.i16.i
# =>This Loop Header: Depth=1
# Child Loop BB0_9 Depth 2
leaq (%rsp,%r15), %r13
addq $12, %r13
movl 12(%rsp,%r15), %ebp
movl 12(%rsp), %ecx
cmpl %ecx, %ebp
jge .LBB0_7
# %bb.2: # in Loop: Header=BB0_1 Depth=1
cmpq $5, %r15
jb .LBB0_4
# %bb.3: # in Loop: Header=BB0_1 Depth=1
movq %rbx, %rdi
movq %r14, %rsi
movq %r15, %rdx
callq memmove@PLT
movl %ebp, 12(%rsp)
jmp .LBB0_11
.p2align 4, 0x90
.LBB0_7: # in Loop: Header=BB0_1 Depth=1
movl (%rax), %eax
movq %r13, %rcx
cmpl %eax, %ebp
jge .LBB0_10
# %bb.8: # %.lr.ph.i.i23.i.preheader
# in Loop: Header=BB0_1 Depth=1
movq %r12, %rcx
.p2align 4, 0x90
.LBB0_9: # %.lr.ph.i.i23.i
# Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
movl %eax, (%rcx)
movl -8(%rcx), %eax
addq $-4, %rcx
cmpl %eax, %ebp
jl .LBB0_9
jmp .LBB0_10
.LBB0_4: # in Loop: Header=BB0_1 Depth=1
cmpq $4, %r15
jne .LBB0_6
# %bb.5: # in Loop: Header=BB0_1 Depth=1
movl %ecx, 4(%rax)
.LBB0_6: # %_ZSt13move_backwardIPiS0_ET0_T_S2_S1_.exit.i27.i
# in Loop: Header=BB0_1 Depth=1
movl %ebp, 12(%rsp)
jmp .LBB0_11
.LBB0_12: # %_ZSt22__final_insertion_sortIPiN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_.exit
movl 16(%rsp), %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z6mediani, .Lfunc_end0-_Z6mediani
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %edi, %edi
callq _ZNSt8ios_base15sync_with_stdioEb
movq _ZSt3cin(%rip), %rax
movq -24(%rax), %rax
movq $0, _ZSt3cin+216(%rax)
leaq 8(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movq (%rax), %rcx
movq -24(%rcx), %rcx
testb $5, 32(%rax,%rcx)
je .LBB1_1
.LBB1_30: # %._crit_edge26
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_1: # %.preheader19.lr.ph
.cfi_def_cfa_offset 80
leaq 12(%rsp), %r14
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_28: # in Loop: Header=BB1_2 Depth=1
movl $_ZSt4cout, %edi
movl $10, %esi
callq _ZNSo3putEc
.LBB1_29: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
# in Loop: Header=BB1_2 Depth=1
movl $_ZSt3cin, %edi
leaq 8(%rsp), %rsi
callq _ZNSirsERi
movq (%rax), %rcx
movq -24(%rcx), %rcx
testb $5, 32(%rax,%rcx)
jne .LBB1_30
.LBB1_2: # %.preheader19
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
# Child Loop BB1_7 Depth 2
# Child Loop BB1_9 Depth 3
# Child Loop BB1_21 Depth 4
# Child Loop BB1_14 Depth 2
cmpl $0, 8(%rsp)
jle .LBB1_5
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB1_2 Depth=1
movl $a, %r12d
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movl $_ZSt3cin, %edi
movq %r12, %rsi
callq _ZNSirsERi
incq %rbx
movslq 8(%rsp), %rax
addq $4, %r12
cmpq %rax, %rbx
jl .LBB1_4
.LBB1_5: # %.preheader18
# in Loop: Header=BB1_2 Depth=1
cmpl $4, 8(%rsp)
jl .LBB1_12
# %bb.6: # %.lr.ph22.preheader
# in Loop: Header=BB1_2 Depth=1
movl $3, %r13d
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_24: # %_Z6mediani.exit
# in Loop: Header=BB1_7 Depth=2
movl 16(%rsp), %eax
movl %eax, a(,%r13,4)
.LBB1_25: # in Loop: Header=BB1_7 Depth=2
incq %r13
movslq 8(%rsp), %rax
cmpq %rax, %r13
jge .LBB1_12
.LBB1_7: # %.lr.ph22
# Parent Loop BB1_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_9 Depth 3
# Child Loop BB1_21 Depth 4
movl a(,%r13,4), %ecx
movl a-4(,%r13,4), %eax
subl %eax, %ecx
movl %ecx, %edx
negl %edx
cmovsl %ecx, %edx
cmpl $5, %edx
jb .LBB1_25
# %bb.8: # in Loop: Header=BB1_7 Depth=2
movl %eax, 12(%rsp)
movl a-8(,%r13,4), %eax
movl %eax, 16(%rsp)
movl a-12(,%r13,4), %eax
movl %eax, 20(%rsp)
movl $4, %r12d
leaq 16(%rsp), %rbp
movq %r14, %rax
jmp .LBB1_9
.p2align 4, 0x90
.LBB1_22: # %_ZSt25__unguarded_linear_insertIPiN9__gnu_cxx5__ops14_Val_less_iterEEvT_T0_.exit.i19.i.i
# in Loop: Header=BB1_9 Depth=3
movl %ebx, (%rcx)
.LBB1_23: # in Loop: Header=BB1_9 Depth=3
addq $4, %r12
addq $4, %rbp
movq %r15, %rax
cmpq $12, %r12
je .LBB1_24
.LBB1_9: # %.lr.ph.i16.i.i
# Parent Loop BB1_2 Depth=1
# Parent Loop BB1_7 Depth=2
# => This Loop Header: Depth=3
# Child Loop BB1_21 Depth 4
leaq (%rsp,%r12), %r15
addq $12, %r15
movl 12(%rsp,%r12), %ebx
movl 12(%rsp), %ecx
cmpl %ecx, %ebx
jge .LBB1_19
# %bb.10: # in Loop: Header=BB1_9 Depth=3
cmpq $5, %r12
jb .LBB1_16
# %bb.11: # in Loop: Header=BB1_9 Depth=3
leaq 16(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
callq memmove@PLT
movl %ebx, 12(%rsp)
jmp .LBB1_23
.p2align 4, 0x90
.LBB1_19: # in Loop: Header=BB1_9 Depth=3
movl (%rax), %eax
movq %r15, %rcx
cmpl %eax, %ebx
jge .LBB1_22
# %bb.20: # %.lr.ph.i.i23.i.i.preheader
# in Loop: Header=BB1_9 Depth=3
movq %rbp, %rcx
.p2align 4, 0x90
.LBB1_21: # %.lr.ph.i.i23.i.i
# Parent Loop BB1_2 Depth=1
# Parent Loop BB1_7 Depth=2
# Parent Loop BB1_9 Depth=3
# => This Inner Loop Header: Depth=4
movl %eax, (%rcx)
movl -8(%rcx), %eax
addq $-4, %rcx
cmpl %eax, %ebx
jl .LBB1_21
jmp .LBB1_22
.LBB1_16: # in Loop: Header=BB1_9 Depth=3
cmpq $4, %r12
jne .LBB1_18
# %bb.17: # in Loop: Header=BB1_9 Depth=3
movl %ecx, 4(%rax)
.LBB1_18: # %_ZSt13move_backwardIPiS0_ET0_T_S2_S1_.exit.i27.i.i
# in Loop: Header=BB1_9 Depth=3
movl %ebx, 12(%rsp)
jmp .LBB1_23
.p2align 4, 0x90
.LBB1_12: # %.preheader
# in Loop: Header=BB1_2 Depth=1
cmpl $0, 8(%rsp)
jle .LBB1_26
# %bb.13: # %.lr.ph24.preheader
# in Loop: Header=BB1_2 Depth=1
xorl %ebx, %ebx
jmp .LBB1_14
.p2align 4, 0x90
.LBB1_31: # in Loop: Header=BB1_14 Depth=2
movq %rax, %rdi
movl $32, %esi
callq _ZNSo3putEc
.LBB1_32: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit17
# in Loop: Header=BB1_14 Depth=2
incq %rbx
movslq 8(%rsp), %rax
cmpq %rax, %rbx
jge .LBB1_26
.LBB1_14: # %.lr.ph24
# Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movl a(,%rbx,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movb $32, 12(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB1_31
# %bb.15: # in Loop: Header=BB1_14 Depth=2
movl $1, %edx
movq %rax, %rdi
movq %r14, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_32
.p2align 4, 0x90
.LBB1_26: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movb $10, 12(%rsp)
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
cmpq $0, _ZSt4cout+16(%rax)
je .LBB1_28
# %bb.27: # in Loop: Header=BB1_2 Depth=1
movl $_ZSt4cout, %edi
movl $1, %edx
movq %r14, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_29
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type a,@object # @a
.bss
.globl a
.p2align 4, 0x0
a:
.zero 140
.size a, 140
.type __hip_cuid_,@object # @__hip_cuid_
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym a
.addrsig_sym _ZSt3cin
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f40b1_00000000-6_Untitled-1.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3927:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3927:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3950:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3950:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZSt25__unguarded_linear_insertIPiN9__gnu_cxx5__ops14_Val_less_iterEEvT_T0_,"axG",@progbits,_ZSt25__unguarded_linear_insertIPiN9__gnu_cxx5__ops14_Val_less_iterEEvT_T0_,comdat
.weak _ZSt25__unguarded_linear_insertIPiN9__gnu_cxx5__ops14_Val_less_iterEEvT_T0_
.type _ZSt25__unguarded_linear_insertIPiN9__gnu_cxx5__ops14_Val_less_iterEEvT_T0_, @function
_ZSt25__unguarded_linear_insertIPiN9__gnu_cxx5__ops14_Val_less_iterEEvT_T0_:
.LFB4578:
.cfi_startproc
endbr64
movl (%rdi), %ecx
leaq -4(%rdi), %rax
movl -4(%rdi), %edx
cmpl %edx, %ecx
jge .L6
.L7:
movl %edx, 4(%rax)
movq %rax, %rdi
subq $4, %rax
movl (%rax), %edx
cmpl %edx, %ecx
jl .L7
.L6:
movl %ecx, (%rdi)
ret
.cfi_endproc
.LFE4578:
.size _ZSt25__unguarded_linear_insertIPiN9__gnu_cxx5__ops14_Val_less_iterEEvT_T0_, .-_ZSt25__unguarded_linear_insertIPiN9__gnu_cxx5__ops14_Val_less_iterEEvT_T0_
.section .text._ZSt16__insertion_sortIPiN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_,"axG",@progbits,_ZSt16__insertion_sortIPiN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_,comdat
.weak _ZSt16__insertion_sortIPiN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_
.type _ZSt16__insertion_sortIPiN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_, @function
_ZSt16__insertion_sortIPiN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_:
.LFB4548:
.cfi_startproc
endbr64
cmpq %rsi, %rdi
je .L18
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %rbp
movq %rsi, %r13
leaq 4(%rdi), %rbx
cmpq %rbx, %rsi
je .L9
movl $4, %r14d
jmp .L15
.L12:
je .L21
.L13:
movl %r12d, 0(%rbp)
.L14:
addq $4, %rbx
cmpq %rbx, %r13
je .L9
.L15:
movl (%rbx), %r12d
movl 0(%rbp), %eax
cmpl %r12d, %eax
jle .L11
movq %rbx, %rdx
subq %rbp, %rdx
cmpq $4, %rdx
jle .L12
movq %r14, %rdi
subq %rdx, %rdi
addq %rbx, %rdi
movq %rbp, %rsi
call memmove@PLT
jmp .L13
.L21:
movl %eax, (%rbx)
jmp .L13
.L11:
movq %rbx, %rdi
call _ZSt25__unguarded_linear_insertIPiN9__gnu_cxx5__ops14_Val_less_iterEEvT_T0_
jmp .L14
.L9:
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
ret
.cfi_endproc
.LFE4548:
.size _ZSt16__insertion_sortIPiN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_, .-_ZSt16__insertion_sortIPiN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_
.section .text._ZSt13__adjust_heapIPiliN9__gnu_cxx5__ops15_Iter_less_iterEEvT_T0_S5_T1_T2_,"axG",@progbits,_ZSt13__adjust_heapIPiliN9__gnu_cxx5__ops15_Iter_less_iterEEvT_T0_S5_T1_T2_,comdat
.weak _ZSt13__adjust_heapIPiliN9__gnu_cxx5__ops15_Iter_less_iterEEvT_T0_S5_T1_T2_
.type _ZSt13__adjust_heapIPiliN9__gnu_cxx5__ops15_Iter_less_iterEEvT_T0_S5_T1_T2_, @function
_ZSt13__adjust_heapIPiliN9__gnu_cxx5__ops15_Iter_less_iterEEvT_T0_S5_T1_T2_:
.LFB4600:
.cfi_startproc
endbr64
movq %rsi, %r8
movl %ecx, %r9d
leaq -1(%rdx), %rax
movq %rax, %r10
shrq $63, %r10
addq %rax, %r10
sarq %r10
cmpq %r10, %rsi
jl .L25
movq %rsi, %rax
testb $1, %dl
jne .L27
movq %r8, %rax
jmp .L29
.L24:
movl (%rdi,%rax,4), %ecx
movl %ecx, (%rdi,%rsi,4)
cmpq %r10, %rax
jge .L34
movq %rax, %rsi
.L25:
leaq 1(%rsi), %rcx
leaq (%rcx,%rcx), %rax
movl -4(%rdi,%rcx,8), %r11d
cmpl %r11d, (%rdi,%rcx,8)
jge .L24
subq $1, %rax
jmp .L24
.L34:
testb $1, %dl
jne .L26
.L29:
subq $2, %rdx
movq %rdx, %rcx
shrq $63, %rcx
addq %rcx, %rdx
sarq %rdx
cmpq %rax, %rdx
je .L35
.L26:
leaq -1(%rax), %rdx
movq %rdx, %rcx
shrq $63, %rcx
addq %rdx, %rcx
sarq %rcx
cmpq %r8, %rax
jg .L28
jmp .L27
.L35:
leaq 2(%rax,%rax), %rdx
movl -4(%rdi,%rdx,4), %ecx
movl %ecx, (%rdi,%rax,4)
leaq -1(%rdx), %rax
jmp .L26
.L31:
movq %rdx, %rcx
.L28:
movl (%rdi,%rcx,4), %edx
cmpl %edx, %r9d
jle .L27
movl %edx, (%rdi,%rax,4)
leaq -1(%rcx), %rdx
movq %rdx, %rax
shrq $63, %rax
addq %rdx, %rax
sarq %rax
movq %rax, %rdx
movq %rcx, %rax
cmpq %rcx, %r8
jl .L31
.L27:
movl %r9d, (%rdi,%rax,4)
ret
.cfi_endproc
.LFE4600:
.size _ZSt13__adjust_heapIPiliN9__gnu_cxx5__ops15_Iter_less_iterEEvT_T0_S5_T1_T2_, .-_ZSt13__adjust_heapIPiliN9__gnu_cxx5__ops15_Iter_less_iterEEvT_T0_S5_T1_T2_
.section .text._ZSt16__introsort_loopIPilN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_T1_,"axG",@progbits,_ZSt16__introsort_loopIPilN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_T1_,comdat
.weak _ZSt16__introsort_loopIPilN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_T1_
.type _ZSt16__introsort_loopIPilN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_T1_, @function
_ZSt16__introsort_loopIPilN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_T1_:
.LFB4484:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
movq %rsi, %rax
subq %rdi, %rax
cmpq $64, %rax
jle .L36
movq %rsi, %rdi
movq %rdx, %r12
testq %rdx, %rdx
jne .L39
movq %rdi, %rbx
.L56:
sarq $2, %rax
movq %rax, %r12
leaq -2(%rax), %rax
movq %rax, %r13
shrq $63, %r13
addq %rax, %r13
sarq %r13
jmp .L40
.L64:
subq $1, %r13
.L40:
movl 0(%rbp,%r13,4), %ecx
movq %r12, %rdx
movq %r13, %rsi
movq %rbp, %rdi
call _ZSt13__adjust_heapIPiliN9__gnu_cxx5__ops15_Iter_less_iterEEvT_T0_S5_T1_T2_
testq %r13, %r13
jne .L64
movq %rbx, %rax
subq %rbp, %rax
cmpq $4, %rax
jle .L36
.L41:
subq $4, %rbx
movl (%rbx), %ecx
movl 0(%rbp), %eax
movl %eax, (%rbx)
movq %rbx, %r12
subq %rbp, %r12
movq %r12, %rdx
sarq $2, %rdx
movl $0, %esi
movq %rbp, %rdi
call _ZSt13__adjust_heapIPiliN9__gnu_cxx5__ops15_Iter_less_iterEEvT_T0_S5_T1_T2_
cmpq $4, %r12
jg .L41
.L36:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
cmpl %esi, %edx
jge .L46
movl 0(%rbp), %eax
movl %esi, 0(%rbp)
movl %eax, -4(%rdi)
jmp .L47
.L46:
movl 0(%rbp), %eax
movl %edx, 0(%rbp)
movl %eax, 4(%rbp)
jmp .L47
.L43:
movl -4(%rdi), %esi
cmpl %esi, %edx
jge .L48
movl 0(%rbp), %eax
movl %edx, 0(%rbp)
movl %eax, 4(%rbp)
jmp .L47
.L48:
cmpl %esi, %eax
jge .L49
movl 0(%rbp), %eax
movl %esi, 0(%rbp)
movl %eax, -4(%rdi)
jmp .L47
.L49:
movl 0(%rbp), %edx
movl %eax, 0(%rbp)
movl %edx, (%rcx)
jmp .L47
.L65:
movq %r12, %rdx
movq %rdi, %rsi
movq %rbx, %rdi
call _ZSt16__introsort_loopIPilN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_T1_
movq %rbx, %rax
subq %rbp, %rax
cmpq $64, %rax
jle .L36
testq %r12, %r12
je .L56
movq %rbx, %rdi
.L39:
subq $1, %r12
movq %rax, %rdx
sarq $2, %rdx
shrq $63, %rax
addq %rdx, %rax
sarq %rax
leaq 0(%rbp,%rax,4), %rcx
leaq 4(%rbp), %rbx
movl 4(%rbp), %edx
movl (%rcx), %eax
cmpl %eax, %edx
jge .L43
movl -4(%rdi), %esi
cmpl %esi, %eax
jge .L44
movl 0(%rbp), %edx
movl %eax, 0(%rbp)
movl %edx, (%rcx)
.L47:
movq %rdi, %rsi
.L45:
movl (%rbx), %ecx
movl 0(%rbp), %edx
cmpl %edx, %ecx
jge .L50
.L51:
addq $4, %rbx
movl (%rbx), %ecx
cmpl %edx, %ecx
jl .L51
.L50:
leaq -4(%rsi), %rax
movl -4(%rsi), %esi
cmpl %edx, %esi
jle .L52
.L53:
subq $4, %rax
movl (%rax), %esi
cmpl %edx, %esi
jg .L53
.L52:
cmpq %rax, %rbx
jnb .L65
movl %esi, (%rbx)
movl %ecx, (%rax)
addq $4, %rbx
movq %rax, %rsi
jmp .L45
.cfi_endproc
.LFE4484:
.size _ZSt16__introsort_loopIPilN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_T1_, .-_ZSt16__introsort_loopIPilN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_T1_
.text
.globl _Z6mediani
.type _Z6mediani, @function
_Z6mediani:
.LFB3923:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq a(%rip), %rax
leal -1(%rdi), %edx
movslq %edx, %rdx
movl (%rax,%rdx,4), %edx
movl %edx, 12(%rsp)
leal -2(%rdi), %edx
movslq %edx, %rdx
movl (%rax,%rdx,4), %edx
movl %edx, 16(%rsp)
subl $3, %edi
movslq %edi, %rdi
movl (%rax,%rdi,4), %eax
movl %eax, 20(%rsp)
leaq 12(%rsp), %rbx
leaq 24(%rsp), %rbp
movl $2, %edx
movq %rbp, %rsi
movq %rbx, %rdi
call _ZSt16__introsort_loopIPilN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_T1_
movq %rbp, %rsi
movq %rbx, %rdi
call _ZSt16__insertion_sortIPiN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_
movl 16(%rsp), %eax
movq 24(%rsp), %rdx
subq %fs:40, %rdx
jne .L69
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L69:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3923:
.size _Z6mediani, .-_Z6mediani
.globl main
.type main, @function
main:
.LFB3924:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $16, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movl $0, %edi
call _ZNSt8ios_base15sync_with_stdioEb@PLT
movq $0, 232+_ZSt3cin(%rip)
leaq _ZSt3cin(%rip), %rbp
leaq a(%rip), %r13
leaq 3(%rsp), %r14
jmp .L71
.L74:
addl $1, %r12d
addq $4, %rbx
cmpl %r12d, 4(%rsp)
jle .L73
.L75:
movl (%rbx), %eax
subl -4(%rbx), %eax
addl $4, %eax
cmpl $8, %eax
jbe .L74
movl %r12d, %edi
call _Z6mediani
movl %eax, (%rbx)
jmp .L74
.L73:
cmpl $0, 4(%rsp)
jle .L76
movl $0, %ebx
leaq _ZSt4cout(%rip), %r12
jmp .L79
.L77:
movl $32, %esi
call _ZNSo3putEc@PLT
.L78:
addq $1, %rbx
cmpl %ebx, 4(%rsp)
jle .L76
.L79:
movl 0(%r13,%rbx,4), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movb $32, 3(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L77
movl $1, %edx
movq %r14, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L78
.L76:
movb $10, 3(%rsp)
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
cmpq $0, 16(%rdx,%rax)
je .L80
movl $1, %edx
movq %r14, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L71:
leaq 4(%rsp), %rsi
movq %rbp, %rdi
call _ZNSirsERi@PLT
movq (%rax), %rdx
movq -24(%rdx), %rdx
movl 32(%rax,%rdx), %ebx
andl $5, %ebx
jne .L82
leaq a(%rip), %r12
cmpl $0, 4(%rsp)
jle .L76
.L72:
movq %r12, %rsi
movq %rbp, %rdi
call _ZNSirsERi@PLT
addl $1, %ebx
movl 4(%rsp), %eax
addq $4, %r12
cmpl %ebx, %eax
jg .L72
cmpl $3, %eax
jle .L73
leaq 12+a(%rip), %rbx
movl $3, %r12d
jmp .L75
.L80:
movl $10, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
jmp .L71
.L82:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L90
movl $0, %eax
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L90:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3924:
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl a
.bss
.align 32
.type a, @object
.size a, 140
a:
.zero 140
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Untitled-1.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z6mediani # -- Begin function _Z6mediani
.p2align 4, 0x90
.type _Z6mediani,@function
_Z6mediani: # @_Z6mediani
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movslq %edi, %rax
movl a-4(,%rax,4), %ecx
movl %ecx, 12(%rsp)
leaq 16(%rsp), %rbx
movl a-8(,%rax,4), %ecx
movl %ecx, 16(%rsp)
movl a-12(,%rax,4), %eax
movl %eax, 20(%rsp)
leaq 12(%rsp), %r14
movl $4, %r15d
movq %rbx, %r12
movq %r14, %rax
jmp .LBB0_1
.p2align 4, 0x90
.LBB0_10: # %_ZSt25__unguarded_linear_insertIPiN9__gnu_cxx5__ops14_Val_less_iterEEvT_T0_.exit.i19.i
# in Loop: Header=BB0_1 Depth=1
movl %ebp, (%rcx)
.LBB0_11: # in Loop: Header=BB0_1 Depth=1
addq $4, %r15
addq $4, %r12
movq %r13, %rax
cmpq $12, %r15
je .LBB0_12
.LBB0_1: # %.lr.ph.i16.i
# =>This Loop Header: Depth=1
# Child Loop BB0_9 Depth 2
leaq (%rsp,%r15), %r13
addq $12, %r13
movl 12(%rsp,%r15), %ebp
movl 12(%rsp), %ecx
cmpl %ecx, %ebp
jge .LBB0_7
# %bb.2: # in Loop: Header=BB0_1 Depth=1
cmpq $5, %r15
jb .LBB0_4
# %bb.3: # in Loop: Header=BB0_1 Depth=1
movq %rbx, %rdi
movq %r14, %rsi
movq %r15, %rdx
callq memmove@PLT
movl %ebp, 12(%rsp)
jmp .LBB0_11
.p2align 4, 0x90
.LBB0_7: # in Loop: Header=BB0_1 Depth=1
movl (%rax), %eax
movq %r13, %rcx
cmpl %eax, %ebp
jge .LBB0_10
# %bb.8: # %.lr.ph.i.i23.i.preheader
# in Loop: Header=BB0_1 Depth=1
movq %r12, %rcx
.p2align 4, 0x90
.LBB0_9: # %.lr.ph.i.i23.i
# Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
movl %eax, (%rcx)
movl -8(%rcx), %eax
addq $-4, %rcx
cmpl %eax, %ebp
jl .LBB0_9
jmp .LBB0_10
.LBB0_4: # in Loop: Header=BB0_1 Depth=1
cmpq $4, %r15
jne .LBB0_6
# %bb.5: # in Loop: Header=BB0_1 Depth=1
movl %ecx, 4(%rax)
.LBB0_6: # %_ZSt13move_backwardIPiS0_ET0_T_S2_S1_.exit.i27.i
# in Loop: Header=BB0_1 Depth=1
movl %ebp, 12(%rsp)
jmp .LBB0_11
.LBB0_12: # %_ZSt22__final_insertion_sortIPiN9__gnu_cxx5__ops15_Iter_less_iterEEvT_S4_T0_.exit
movl 16(%rsp), %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z6mediani, .Lfunc_end0-_Z6mediani
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %edi, %edi
callq _ZNSt8ios_base15sync_with_stdioEb
movq _ZSt3cin(%rip), %rax
movq -24(%rax), %rax
movq $0, _ZSt3cin+216(%rax)
leaq 8(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movq (%rax), %rcx
movq -24(%rcx), %rcx
testb $5, 32(%rax,%rcx)
je .LBB1_1
.LBB1_30: # %._crit_edge26
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_1: # %.preheader19.lr.ph
.cfi_def_cfa_offset 80
leaq 12(%rsp), %r14
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_28: # in Loop: Header=BB1_2 Depth=1
movl $_ZSt4cout, %edi
movl $10, %esi
callq _ZNSo3putEc
.LBB1_29: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
# in Loop: Header=BB1_2 Depth=1
movl $_ZSt3cin, %edi
leaq 8(%rsp), %rsi
callq _ZNSirsERi
movq (%rax), %rcx
movq -24(%rcx), %rcx
testb $5, 32(%rax,%rcx)
jne .LBB1_30
.LBB1_2: # %.preheader19
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
# Child Loop BB1_7 Depth 2
# Child Loop BB1_9 Depth 3
# Child Loop BB1_21 Depth 4
# Child Loop BB1_14 Depth 2
cmpl $0, 8(%rsp)
jle .LBB1_5
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB1_2 Depth=1
movl $a, %r12d
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movl $_ZSt3cin, %edi
movq %r12, %rsi
callq _ZNSirsERi
incq %rbx
movslq 8(%rsp), %rax
addq $4, %r12
cmpq %rax, %rbx
jl .LBB1_4
.LBB1_5: # %.preheader18
# in Loop: Header=BB1_2 Depth=1
cmpl $4, 8(%rsp)
jl .LBB1_12
# %bb.6: # %.lr.ph22.preheader
# in Loop: Header=BB1_2 Depth=1
movl $3, %r13d
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_24: # %_Z6mediani.exit
# in Loop: Header=BB1_7 Depth=2
movl 16(%rsp), %eax
movl %eax, a(,%r13,4)
.LBB1_25: # in Loop: Header=BB1_7 Depth=2
incq %r13
movslq 8(%rsp), %rax
cmpq %rax, %r13
jge .LBB1_12
.LBB1_7: # %.lr.ph22
# Parent Loop BB1_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_9 Depth 3
# Child Loop BB1_21 Depth 4
movl a(,%r13,4), %ecx
movl a-4(,%r13,4), %eax
subl %eax, %ecx
movl %ecx, %edx
negl %edx
cmovsl %ecx, %edx
cmpl $5, %edx
jb .LBB1_25
# %bb.8: # in Loop: Header=BB1_7 Depth=2
movl %eax, 12(%rsp)
movl a-8(,%r13,4), %eax
movl %eax, 16(%rsp)
movl a-12(,%r13,4), %eax
movl %eax, 20(%rsp)
movl $4, %r12d
leaq 16(%rsp), %rbp
movq %r14, %rax
jmp .LBB1_9
.p2align 4, 0x90
.LBB1_22: # %_ZSt25__unguarded_linear_insertIPiN9__gnu_cxx5__ops14_Val_less_iterEEvT_T0_.exit.i19.i.i
# in Loop: Header=BB1_9 Depth=3
movl %ebx, (%rcx)
.LBB1_23: # in Loop: Header=BB1_9 Depth=3
addq $4, %r12
addq $4, %rbp
movq %r15, %rax
cmpq $12, %r12
je .LBB1_24
.LBB1_9: # %.lr.ph.i16.i.i
# Parent Loop BB1_2 Depth=1
# Parent Loop BB1_7 Depth=2
# => This Loop Header: Depth=3
# Child Loop BB1_21 Depth 4
leaq (%rsp,%r12), %r15
addq $12, %r15
movl 12(%rsp,%r12), %ebx
movl 12(%rsp), %ecx
cmpl %ecx, %ebx
jge .LBB1_19
# %bb.10: # in Loop: Header=BB1_9 Depth=3
cmpq $5, %r12
jb .LBB1_16
# %bb.11: # in Loop: Header=BB1_9 Depth=3
leaq 16(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
callq memmove@PLT
movl %ebx, 12(%rsp)
jmp .LBB1_23
.p2align 4, 0x90
.LBB1_19: # in Loop: Header=BB1_9 Depth=3
movl (%rax), %eax
movq %r15, %rcx
cmpl %eax, %ebx
jge .LBB1_22
# %bb.20: # %.lr.ph.i.i23.i.i.preheader
# in Loop: Header=BB1_9 Depth=3
movq %rbp, %rcx
.p2align 4, 0x90
.LBB1_21: # %.lr.ph.i.i23.i.i
# Parent Loop BB1_2 Depth=1
# Parent Loop BB1_7 Depth=2
# Parent Loop BB1_9 Depth=3
# => This Inner Loop Header: Depth=4
movl %eax, (%rcx)
movl -8(%rcx), %eax
addq $-4, %rcx
cmpl %eax, %ebx
jl .LBB1_21
jmp .LBB1_22
.LBB1_16: # in Loop: Header=BB1_9 Depth=3
cmpq $4, %r12
jne .LBB1_18
# %bb.17: # in Loop: Header=BB1_9 Depth=3
movl %ecx, 4(%rax)
.LBB1_18: # %_ZSt13move_backwardIPiS0_ET0_T_S2_S1_.exit.i27.i.i
# in Loop: Header=BB1_9 Depth=3
movl %ebx, 12(%rsp)
jmp .LBB1_23
.p2align 4, 0x90
.LBB1_12: # %.preheader
# in Loop: Header=BB1_2 Depth=1
cmpl $0, 8(%rsp)
jle .LBB1_26
# %bb.13: # %.lr.ph24.preheader
# in Loop: Header=BB1_2 Depth=1
xorl %ebx, %ebx
jmp .LBB1_14
.p2align 4, 0x90
.LBB1_31: # in Loop: Header=BB1_14 Depth=2
movq %rax, %rdi
movl $32, %esi
callq _ZNSo3putEc
.LBB1_32: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit17
# in Loop: Header=BB1_14 Depth=2
incq %rbx
movslq 8(%rsp), %rax
cmpq %rax, %rbx
jge .LBB1_26
.LBB1_14: # %.lr.ph24
# Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movl a(,%rbx,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movb $32, 12(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB1_31
# %bb.15: # in Loop: Header=BB1_14 Depth=2
movl $1, %edx
movq %rax, %rdi
movq %r14, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_32
.p2align 4, 0x90
.LBB1_26: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movb $10, 12(%rsp)
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
cmpq $0, _ZSt4cout+16(%rax)
je .LBB1_28
# %bb.27: # in Loop: Header=BB1_2 Depth=1
movl $_ZSt4cout, %edi
movl $1, %edx
movq %r14, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_29
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type a,@object # @a
.bss
.globl a
.p2align 4, 0x0
a:
.zero 140
.size a, 140
.type __hip_cuid_,@object # @__hip_cuid_
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym a
.addrsig_sym _ZSt3cin
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // 相关 CUDA 库
#include "cuda_runtime.h"
#include "cuda.h"
#include "device_launch_parameters.h"
#include <iostream>
#include <stdio.h>
using namespace std;
const int N = 100;
// 块数
const int BLOCK_data = 3;
// 各块中的线程数
const int THREAD_data = 10;
// CUDA初始化函数
bool InitCUDA()
{
int deviceCount;
// 获取显示设备数
cudaGetDeviceCount (&deviceCount);
if (deviceCount == 0)
{
cout << "找不到设备" << endl;
return EXIT_FAILURE;
}
int i;
for (i=0; i<deviceCount; i++)
{
cudaDeviceProp prop;
if (cudaGetDeviceProperties(&prop,i)==cudaSuccess) // 获取设备属性
{
if (prop.major>=1) //cuda计算能力
{
break;
}
}
}
if (i==deviceCount)
{
cout << "找不到支持 CUDA 计算的设备" << endl;
return EXIT_FAILURE;
}
cudaSetDevice(i); // 选定使用的显示设备
return EXIT_SUCCESS;
}
// 此函数在主机端调用，设备端执行。
__global__
static void Sum (int *data,int *result)
{
// 取得线程号
const int tid = threadIdx.x;
// 获得块号
const int bid = blockIdx.x;
int sum = 0;
// 有点像网格计算的思路
for (int i=bid*THREAD_data+tid; i<N; i+=BLOCK_data*THREAD_data)
{
sum += data[i];
}
// result 数组存放各个线程的计算结果
result[bid*THREAD_data+tid] = sum;
}
int main ()
{
// 初始化 CUDA 编译环境
if (InitCUDA()) {
return EXIT_FAILURE;
}
cout << "成功建立 CUDA 计算环境" << endl << endl;
// 建立，初始化，打印测试数组
int *data = new int [N];
cout << "测试矩阵: " << endl;
for (int i=0; i<N; i++)
{
data[i] = rand()%10;
cout << data[i] << " ";
if ((i+1)%10 == 0) cout << endl;
}
cout << endl;
int *gpudata, *result;
// 在显存中为计算对象开辟空间
cudaMalloc ((void**)&gpudata, sizeof(int)*N);
// 在显存中为结果对象开辟空间
cudaMalloc ((void**)&result, sizeof(int)*BLOCK_data*THREAD_data);
// 将数组数据传输进显存
cudaMemcpy (gpudata, data, sizeof(int)*N, cudaMemcpyHostToDevice);
// 调用 kernel 函数 - 此函数可以根据显存地址以及自身的块号，线程号处理数据。
Sum<<<BLOCK_data,THREAD_data,0>>> (gpudata,result);
// 在内存中为计算对象开辟空间
int *sumArray = new int[THREAD_data*BLOCK_data];
// 从显存获取处理的结果
cudaMemcpy (sumArray, result, sizeof(int)*THREAD_data*BLOCK_data, cudaMemcpyDeviceToHost);
// 释放显存
cudaFree (gpudata);
cudaFree (result);
// 计算 GPU 每个线程计算出来和的总和
int final_sum=0;
for (int i=0; i<THREAD_data*BLOCK_data; i++)
{
final_sum += sumArray[i];
}
cout << "GPU 求和结果为: " << final_sum << endl;
// 使用 CPU 对矩阵进行求和并将结果对照
final_sum = 0;
for (int i=0; i<N; i++)
{
final_sum += data[i];
}
cout << "CPU 求和结果为: " << final_sum << endl;
return 0;
} | code for sm_80
Function : _Z3SumPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B2, 0x7e0 ; /* 0x000007a000027945 */
/* 0x000fe20003800000 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R0, R3, 0xa, R4 ; /* 0x0000000a03007824 */
/* 0x001fca00078e0204 */
/*0070*/ ISETP.GT.AND P0, PT, R0, 0x63, PT ; /* 0x000000630000780c */
/* 0x000fda0003f04270 */
/*0080*/ @P0 BRA 0x7d0 ; /* 0x0000074000000947 */
/* 0x000fea0003800000 */
/*0090*/ IMNMX R2, R0, 0x46, !PT ; /* 0x0000004600027817 */
/* 0x000fe20007800200 */
/*00a0*/ BSSY B1, 0x700 ; /* 0x0000065000017945 */
/* 0x000fe20003800000 */
/*00b0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe400078e00ff */
/*00c0*/ IADD3 R2, -R4, 0x1d, R2 ; /* 0x0000001d04027810 */
/* 0x000fe20007ffe102 */
/*00d0*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0000 */
/*00e0*/ IMAD R4, R3, -0xa, R2 ; /* 0xfffffff603047824 */
/* 0x000fc800078e0202 */
/*00f0*/ IMAD.WIDE.U32 R2, R4.reuse, -0x77777777, RZ ; /* 0x8888888904027825 */
/* 0x040fe200078e00ff */
/*0100*/ ISETP.GE.U32.AND P0, PT, R4, 0x5a, PT ; /* 0x0000005a0400780c */
/* 0x000fc80003f06070 */
/*0110*/ SHF.R.U32.HI R9, RZ, 0x4, R3 ; /* 0x00000004ff097819 */
/* 0x000fc80000011603 */
/*0120*/ IADD3 R4, R9, 0x1, RZ ; /* 0x0000000109047810 */
/* 0x000fc80007ffe0ff */
/*0130*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe200078ec0ff */
/*0140*/ @!P0 BRA 0x6f0 ; /* 0x000005a000008947 */
/* 0x000fea0003800000 */
/*0150*/ IMAD.IADD R6, R9, 0x1, -R4 ; /* 0x0000000109067824 */
/* 0x000fe200078e0a04 */
/*0160*/ BSSY B0, 0x610 ; /* 0x000004a000007945 */
/* 0x000fe20003800000 */
/*0170*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*0180*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*0190*/ ISETP.GT.AND P0, PT, R6, -0x1, PT ; /* 0xffffffff0600780c */
/* 0x000fe20003f04270 */
/*01a0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0203 */
/*01b0*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*01c0*/ IADD3 R2, P1, R2, 0xf0, RZ ; /* 0x000000f002027810 */
/* 0x000fca0007f3e0ff */
/*01d0*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fe400008e0603 */
/*01e0*/ @!P0 BRA 0x600 ; /* 0x0000041000008947 */
/* 0x000fea0003800000 */
/*01f0*/ IADD3 R8, R6, 0x1, RZ ; /* 0x0000000106087810 */
/* 0x000fe20007ffe0ff */
/*0200*/ BSSY B3, 0x450 ; /* 0x0000024000037945 */
/* 0x000fe20003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*0220*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fda0003f24270 */
/*0230*/ @!P1 BRA 0x440 ; /* 0x0000020000009947 */
/* 0x000fea0003800000 */
/*0240*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0250*/ LDG.E R12, [R2.64+-0xf0] ; /* 0xffff1004020c7981 */
/* 0x000ea8000c1e1900 */
/*0260*/ LDG.E R13, [R2.64+-0x78] ; /* 0xffff8804020d7981 */
/* 0x000ea8000c1e1900 */
/*0270*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x0000e8000c1e1900 */
/*0280*/ LDG.E R14, [R2.64+0x78] ; /* 0x00007804020e7981 */
/* 0x0000e8000c1e1900 */
/*0290*/ LDG.E R17, [R2.64+0xf0] ; /* 0x0000f00402117981 */
/* 0x000128000c1e1900 */
/*02a0*/ LDG.E R16, [R2.64+0x168] ; /* 0x0001680402107981 */
/* 0x000128000c1e1900 */
/*02b0*/ LDG.E R19, [R2.64+0x1e0] ; /* 0x0001e00402137981 */
/* 0x000168000c1e1900 */
/*02c0*/ LDG.E R18, [R2.64+0x258] ; /* 0x0002580402127981 */
/* 0x000168000c1e1900 */
/*02d0*/ LDG.E R21, [R2.64+0x2d0] ; /* 0x0002d00402157981 */
/* 0x000168000c1e1900 */
/*02e0*/ LDG.E R20, [R2.64+0x348] ; /* 0x0003480402147981 */
/* 0x000168000c1e1900 */
/*02f0*/ LDG.E R23, [R2.64+0x3c0] ; /* 0x0003c00402177981 */
/* 0x000168000c1e1900 */
/*0300*/ LDG.E R22, [R2.64+0x438] ; /* 0x0004380402167981 */
/* 0x000168000c1e1900 */
/*0310*/ LDG.E R11, [R2.64+0x4b0] ; /* 0x0004b004020b7981 */
/* 0x000168000c1e1900 */
/*0320*/ LDG.E R10, [R2.64+0x528] ; /* 0x00052804020a7981 */
/* 0x000168000c1e1900 */
/*0330*/ LDG.E R9, [R2.64+0x5a0] ; /* 0x0005a00402097981 */
/* 0x000168000c1e1900 */
/*0340*/ LDG.E R8, [R2.64+0x618] ; /* 0x0006180402087981 */
/* 0x000162000c1e1900 */
/*0350*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc40007ffe0ff */
/*0360*/ IADD3 R7, R7, 0x1e0, RZ ; /* 0x000001e007077810 */
/* 0x000fe40007ffe0ff */
/*0370*/ ISETP.GT.AND P1, PT, R6, 0xb, PT ; /* 0x0000000b0600780c */
/* 0x000fe40003f24270 */
/*0380*/ IADD3 R12, R13, R12, R5 ; /* 0x0000000c0d0c7210 */
/* 0x004fe40007ffe005 */
/*0390*/ IADD3 R13, P2, R2, 0x780, RZ ; /* 0x00000780020d7810 */
/* 0x000fca0007f5e0ff */
/*03a0*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x001fe200010e0603 */
/*03b0*/ IADD3 R12, R14, R15, R12 ; /* 0x0000000f0e0c7210 */
/* 0x008fe20007ffe00c */
/*03c0*/ IMAD.MOV.U32 R2, RZ, RZ, R13 ; /* 0x000000ffff027224 */
/* 0x000fc600078e000d */
/*03d0*/ IADD3 R12, R16, R17, R12 ; /* 0x00000011100c7210 */
/* 0x010fc80007ffe00c */
/*03e0*/ IADD3 R12, R18, R19, R12 ; /* 0x00000013120c7210 */
/* 0x020fc80007ffe00c */
/*03f0*/ IADD3 R12, R20, R21, R12 ; /* 0x00000015140c7210 */
/* 0x000fc80007ffe00c */
/*0400*/ IADD3 R12, R22, R23, R12 ; /* 0x00000017160c7210 */
/* 0x000fc80007ffe00c */
/*0410*/ IADD3 R10, R10, R11, R12 ; /* 0x0000000b0a0a7210 */
/* 0x000fc80007ffe00c */
/*0420*/ IADD3 R5, R8, R9, R10 ; /* 0x0000000908057210 */
/* 0x000fe20007ffe00a */
/*0430*/ @P1 BRA 0x250 ; /* 0xfffffe1000001947 */
/* 0x000fea000383ffff */
/*0440*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0450*/ IADD3 R8, R6, 0x1, RZ ; /* 0x0000000106087810 */
/* 0x000fe20007ffe0ff */
/*0460*/ BSSY B3, 0x5d0 ; /* 0x0000016000037945 */
/* 0x000fe60003800000 */
/*0470*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*0480*/ @!P1 BRA 0x5c0 ; /* 0x0000013000009947 */
/* 0x000fea0003800000 */
/*0490*/ LDG.E R8, [R2.64+-0xf0] ; /* 0xffff100402087981 */
/* 0x000ea8000c1e1900 */
/*04a0*/ LDG.E R9, [R2.64+-0x78] ; /* 0xffff880402097981 */
/* 0x000ea8000c1e1900 */
/*04b0*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x0000e8000c1e1900 */
/*04c0*/ LDG.E R10, [R2.64+0x78] ; /* 0x00007804020a7981 */
/* 0x0000e8000c1e1900 */
/*04d0*/ LDG.E R13, [R2.64+0xf0] ; /* 0x0000f004020d7981 */
/* 0x000128000c1e1900 */
/*04e0*/ LDG.E R12, [R2.64+0x168] ; /* 0x00016804020c7981 */
/* 0x000128000c1e1900 */
/*04f0*/ LDG.E R15, [R2.64+0x1e0] ; /* 0x0001e004020f7981 */
/* 0x000168000c1e1900 */
/*0500*/ LDG.E R14, [R2.64+0x258] ; /* 0x00025804020e7981 */
/* 0x000162000c1e1900 */
/*0510*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0520*/ IADD3 R7, R7, 0xf0, RZ ; /* 0x000000f007077810 */
/* 0x000fe40007ffe0ff */
/*0530*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe40007ffe0ff */
/*0540*/ IADD3 R8, R9, R8, R5 ; /* 0x0000000809087210 */
/* 0x004fe40007ffe005 */
/*0550*/ IADD3 R9, P1, R2, 0x3c0, RZ ; /* 0x000003c002097810 */
/* 0x000fca0007f3e0ff */
/*0560*/ IMAD.MOV.U32 R2, RZ, RZ, R9 ; /* 0x000000ffff027224 */
/* 0x001fe200078e0009 */
/*0570*/ IADD3 R8, R10, R11, R8 ; /* 0x0000000b0a087210 */
/* 0x008fe20007ffe008 */
/*0580*/ IMAD.X R10, RZ, RZ, R3, P1 ; /* 0x000000ffff0a7224 */
/* 0x000fc800008e0603 */
/*0590*/ IMAD.MOV.U32 R3, RZ, RZ, R10 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000a */
/*05a0*/ IADD3 R8, R12, R13, R8 ; /* 0x0000000d0c087210 */
/* 0x010fc80007ffe008 */
/*05b0*/ IADD3 R5, R14, R15, R8 ; /* 0x0000000f0e057210 */
/* 0x020fe40007ffe008 */
/*05c0*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*05d0*/ ISETP.NE.OR P0, PT, R6, -0x1, P0 ; /* 0xffffffff0600780c */
/* 0x000fda0000705670 */
/*05e0*/ @!P0 BREAK B0 ; /* 0x0000000000008942 */
/* 0x000fe20003800000 */
/*05f0*/ @!P0 BRA 0x6f0 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0600*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0610*/ LDG.E R8, [R2.64+-0xf0] ; /* 0xffff100402087981 */
/* 0x0000a8000c1e1900 */
/*0620*/ LDG.E R9, [R2.64+-0x78] ; /* 0xffff880402097981 */
/* 0x0000a8000c1e1900 */
/*0630*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x0000e8000c1e1900 */
/*0640*/ LDG.E R11, [R2.64+0x78] ; /* 0x00007804020b7981 */
/* 0x0000e2000c1e1900 */
/*0650*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc40007ffe0ff */
/*0660*/ IADD3 R12, P1, R2, 0x1e0, RZ ; /* 0x000001e0020c7810 */
/* 0x000fe40007f3e0ff */
/*0670*/ ISETP.NE.AND P0, PT, R6, -0x1, PT ; /* 0xffffffff0600780c */
/* 0x000fe40003f05270 */
/*0680*/ IADD3 R7, R7, 0x78, RZ ; /* 0x0000007807077810 */
/* 0x000fe20007ffe0ff */
/*0690*/ IMAD.X R13, RZ, RZ, R3, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe400008e0603 */
/*06a0*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x001fe400078e000c */
/*06b0*/ IMAD.MOV.U32 R3, RZ, RZ, R13 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000d */
/*06c0*/ IADD3 R5, R9, R8, R5 ; /* 0x0000000809057210 */
/* 0x004fc80007ffe005 */
/*06d0*/ IADD3 R5, R11, R10, R5 ; /* 0x0000000a0b057210 */
/* 0x008fe20007ffe005 */
/*06e0*/ @P0 BRA 0x610 ; /* 0xffffff2000000947 */
/* 0x000fea000383ffff */
/*06f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0700*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0710*/ @!P0 BRA 0x7d0 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0720*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc800078e00ff */
/*0730*/ IMAD.WIDE R2, R7, R2, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x000fc800078e0202 */
/*0740*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fc800078e0002 */
/*0750*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fcc00078e0006 */
/*0760*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x0000a2000c1e1900 */
/*0770*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0780*/ IADD3 R6, P1, R6, 0x78, RZ ; /* 0x0000007806067810 */
/* 0x000fe40007f3e0ff */
/*0790*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*07a0*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x001fe400008e0603 */
/*07b0*/ IMAD.IADD R5, R2, 0x1, R5 ; /* 0x0000000102057824 */
/* 0x004fd000078e0205 */
/*07c0*/ @P0 BRA 0x750 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*07d0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*07e0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*07f0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0800*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0203 */
/*0810*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0820*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0830*/ BRA 0x830; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
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