system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/execution_policy.h>
#include <thrust/transform.h>
struct TenX {
__host__ __device__ int operator() (int x) const {
return x*10;
}
} myFunctor;
void hostVectors() {
thrust::host_vector<int> vec1(4), vec2(4);
printf("Host\n");
for (size_t i=0; i < vec1.size(); i++) vec1[i] = i;
thrust::transform(vec1.begin(), vec1.end(), vec2.begin(), myFunctor);
for (size_t i=0; i < vec1.size(); i++) {
printf("%d\t%d\n", vec1[i], vec2[i]);
}
}
void deviceVectors() {
thrust::host_vector<int> vec1(4), vec2(4);
thrust::device_vector<int> vec1_dev(4), vec2_dev(4);
printf("Device\n");
for (size_t i=0; i < vec1.size(); i++) vec1[i] = i;
vec1_dev = vec1;
thrust::transform(vec1_dev.begin(), vec1_dev.end(), vec2_dev.begin(),
myFunctor);
vec2 = vec2_dev;
for (size_t i=0; i < vec1.size(); i++) {
printf("%d\t%d\n", vec1[i], vec2[i]);
}
}
void deviceVectorDevPointers() {
thrust::host_vector<int> vec1(4), vec2(4);
thrust::device_vector<int> vec1_dev(4), vec2_dev(4);
thrust::device_ptr<int> vec1_dev_start(thrust::raw_pointer_cast(&vec1_dev[0]));
thrust::device_ptr<int> vec2_dev_start(thrust::raw_pointer_cast(&vec2_dev[0]));
printf("Device device pointers\n");
for (size_t i=0; i < vec1.size(); i++) vec1[i] = i;
vec1_dev = vec1;
thrust::transform(thrust::device, vec1_dev_start, vec1_dev_start + 4,
vec2_dev_start, myFunctor);
vec2 = vec2_dev;
for (size_t i=0; i < vec1.size(); i++) {
printf("%d\t%d\n", vec1[i], vec2[i]);
}
}
void deviceVectorPointers() {
thrust::host_vector<int> vec1(4), vec2(4);
thrust::device_vector<int> vec1_dev(4), vec2_dev(4);
int *vec1_dev_start = thrust::raw_pointer_cast(&vec1_dev[0]);
int *vec2_dev_start = thrust::raw_pointer_cast(&vec2_dev[0]);
printf("Device pointers\n");
for (size_t i=0; i < vec1.size(); i++) vec1[i] = i;
vec1_dev = vec1;
thrust::transform(thrust::device, vec1_dev_start, vec1_dev_start + 4,
vec2_dev_start, myFunctor);
vec2 = vec2_dev;
for (size_t i=0; i < vec1.size(); i++) {
printf("%d\t%d\n", vec1[i], vec2[i]);
}
}
void deviceVecToPointerToDevPointer() {
thrust::host_vector<int> vec1(4), vec2(4);
thrust::device_vector<int> vec1_dev(4), vec2_dev(4);
int *vec1_dev_start = thrust::raw_pointer_cast(&vec1_dev[0]);
int *vec2_dev_start = thrust::raw_pointer_cast(&vec2_dev[0]);
thrust::device_ptr<int> vec1_dev_ptr(vec1_dev_start);
thrust::device_ptr<int> vec2_dev_ptr(vec2_dev_start);
printf("Device vec->ptr->devptr\n");
for (size_t i=0; i < vec1.size(); i++) vec1[i] = i;
vec1_dev = vec1;
thrust::transform(thrust::device, vec1_dev_ptr, vec1_dev_ptr + 4,
vec2_dev_ptr, myFunctor);
vec2 = vec2_dev;
for (size_t i=0; i < vec1.size(); i++) {
printf("%d\t%d\n", vec1[i], vec2[i]);
}
}
int main() {
hostVectors();
deviceVectors();
deviceVectorDevPointers();
deviceVectorPointers();
deviceVecToPointerToDevPointer();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_:
s_load_b128 s[4:7], s[0:1], 0x10
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x8
v_lshlrev_b32_e32 v0, 2, v0
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
v_add_co_u32 v0, s0, s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
v_mov_b32_e32 v2, s6
flat_store_b32 v[0:1], v2
.LBB0_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,comdat
.Lfunc_end0:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_, .Lfunc_end0-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_NS3_14no_stencil_tagE4TenXNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_NS3_14no_stencil_tagE4TenXNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_NS3_14no_stencil_tagE4TenXNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_NS3_14no_stencil_tagE4TenXNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_NS3_14no_stencil_tagE4TenXNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_NS3_14no_stencil_tagE4TenXNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_:
s_load_b128 s[4:7], s[0:1], 0x18
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x0
v_add_co_u32 v0, s0, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s3, 0, s0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
flat_load_b32 v2, v[2:3]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mul_lo_u32 v2, v2, 10
flat_store_b32 v[0:1], v2
.LBB1_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_NS3_14no_stencil_tagE4TenXNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_NS3_14no_stencil_tagE4TenXNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_NS3_14no_stencil_tagE4TenXNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_,comdat
.Lfunc_end1:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_NS3_14no_stencil_tagE4TenXNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_, .Lfunc_end1-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_NS3_14no_stencil_tagE4TenXNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_10device_ptrIiEES6_NS3_14no_stencil_tagE4TenXNS3_21always_true_predicateEEElLj1EEEvT0_T1_SC_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_10device_ptrIiEES6_NS3_14no_stencil_tagE4TenXNS3_21always_true_predicateEEElLj1EEEvT0_T1_SC_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_10device_ptrIiEES6_NS3_14no_stencil_tagE4TenXNS3_21always_true_predicateEEElLj1EEEvT0_T1_SC_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_10device_ptrIiEES6_NS3_14no_stencil_tagE4TenXNS3_21always_true_predicateEEElLj1EEEvT0_T1_SC_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_10device_ptrIiEES6_NS3_14no_stencil_tagE4TenXNS3_21always_true_predicateEEElLj1EEEvT0_T1_SC_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_10device_ptrIiEES6_NS3_14no_stencil_tagE4TenXNS3_21always_true_predicateEEElLj1EEEvT0_T1_SC_:
s_load_b128 s[4:7], s[0:1], 0x18
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB2_2
s_load_b128 s[4:7], s[0:1], 0x0
v_add_co_u32 v0, s0, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s3, 0, s0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
flat_load_b32 v2, v[2:3]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mul_lo_u32 v2, v2, 10
flat_store_b32 v[0:1], v2
.LBB2_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_10device_ptrIiEES6_NS3_14no_stencil_tagE4TenXNS3_21always_true_predicateEEElLj1EEEvT0_T1_SC_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_10device_ptrIiEES6_NS3_14no_stencil_tagE4TenXNS3_21always_true_predicateEEElLj1EEEvT0_T1_SC_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_10device_ptrIiEES6_NS3_14no_stencil_tagE4TenXNS3_21always_true_predicateEEElLj1EEEvT0_T1_SC_,comdat
.Lfunc_end2:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_10device_ptrIiEES6_NS3_14no_stencil_tagE4TenXNS3_21always_true_predicateEEElLj1EEEvT0_T1_SC_, .Lfunc_end2-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_10device_ptrIiEES6_NS3_14no_stencil_tagE4TenXNS3_21always_true_predicateEEElLj1EEEvT0_T1_SC_
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fIPiS5_NS3_14no_stencil_tagE4TenXNS3_21always_true_predicateEEElLj1EEEvT0_T1_SB_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fIPiS5_NS3_14no_stencil_tagE4TenXNS3_21always_true_predicateEEElLj1EEEvT0_T1_SB_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fIPiS5_NS3_14no_stencil_tagE4TenXNS3_21always_true_predicateEEElLj1EEEvT0_T1_SB_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fIPiS5_NS3_14no_stencil_tagE4TenXNS3_21always_true_predicateEEElLj1EEEvT0_T1_SB_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fIPiS5_NS3_14no_stencil_tagE4TenXNS3_21always_true_predicateEEElLj1EEEvT0_T1_SB_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fIPiS5_NS3_14no_stencil_tagE4TenXNS3_21always_true_predicateEEElLj1EEEvT0_T1_SB_:
s_load_b128 s[4:7], s[0:1], 0x18
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB3_2
s_load_b128 s[4:7], s[0:1], 0x0
v_add_co_u32 v0, s0, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s3, 0, s0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v2, 10
global_store_b32 v[0:1], v2, off
.LBB3_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fIPiS5_NS3_14no_stencil_tagE4TenXNS3_21always_true_predicateEEElLj1EEEvT0_T1_SB_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fIPiS5_NS3_14no_stencil_tagE4TenXNS3_21always_true_predicateEEElLj1EEEvT0_T1_SB_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fIPiS5_NS3_14no_stencil_tagE4TenXNS3_21always_true_predicateEEElLj1EEEvT0_T1_SB_,comdat
.Lfunc_end3:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fIPiS5_NS3_14no_stencil_tagE4TenXNS3_21always_true_predicateEEElLj1EEEvT0_T1_SB_, .Lfunc_end3-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fIPiS5_NS3_14no_stencil_tagE4TenXNS3_21always_true_predicateEEElLj1EEEvT0_T1_SB_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 24
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_NS3_14no_stencil_tagE4TenXNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_NS3_14no_stencil_tagE4TenXNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 24
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_10device_ptrIiEES6_NS3_14no_stencil_tagE4TenXNS3_21always_true_predicateEEElLj1EEEvT0_T1_SC_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_10device_ptrIiEES6_NS3_14no_stencil_tagE4TenXNS3_21always_true_predicateEEElLj1EEEvT0_T1_SC_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 24
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fIPiS5_NS3_14no_stencil_tagE4TenXNS3_21always_true_predicateEEElLj1EEEvT0_T1_SB_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fIPiS5_NS3_14no_stencil_tagE4TenXNS3_21always_true_predicateEEElLj1EEEvT0_T1_SB_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**************************************************
*******PROGRAM FOR ARRAY REDUCTION IN CUDA*********
***************************************************
* EXTERNAL PROGRAMS INCLUDED: *
* *
* SUMS UPTO 2^24 INTS BEFORE REACHING BLOCK LIMIT *
* ARRAY MUST CONTAIN POWER OF TWO ELEMENTS *
* PROGRAM INCLUDES INTS,FLOATS AND DOUBS *
* *
* Call INTS: cuda_asum_intm(ipt/opt array, N#s) *
* Call FLTS: cuda_asum_fltm(ipt/opt array, N#s) *
* Call DOUBS: cuda_asum_doubm(ipt/opt array, N#s) *
* *
***************************************************/
// *** INCLUDED LIBRARIES*** //
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <cuda.h>
// ***CUDA ERROR HANDLER*** //
#define CUDA_CALL(x) do { if((x) != cudaSuccess) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
// ********************************************************************* //
// **********************INTEGER ARRAY SUMMATION************************ //
// ********************************************************************* //
// ****************************************** //
// ***INTEGERS DEVICE SIDE KERNEL PROGRAM**** //
// ****************************************** //
template <unsigned int blockSize>
__global__ void cuda_asum_int(int *d_idat, int *d_odat)
{
extern __shared__ int sdata[];
//LOAD ELEMENT FROM GLOBAL TO SHARED MEM
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * (blockDim.x * 2) + tid;
sdata[tid] = d_idat[i] + d_idat[i + blockDim.x];
__syncthreads();
//REDUCTION
if (blockSize >= 512)
{
if (tid < 256) {sdata[tid] += sdata[tid + 256];} __syncthreads();
}
if (blockSize >= 256)
{
if (tid < 128) {sdata[tid] += sdata[tid + 128];} __syncthreads();
}
if (blockSize >= 128)
{
if (tid < 64) {sdata[tid] += sdata[tid + 64];} __syncthreads();
}
if (tid < 32)
{
if (blockSize >= 64) sdata[tid] += sdata[tid + 32];
if (blockSize >= 32) sdata[tid] += sdata[tid + 16];
if (blockSize >= 16) sdata[tid] += sdata[tid + 8];
if (blockSize >= 8) sdata[tid] += sdata[tid + 4];
if (blockSize >= 4) sdata[tid] += sdata[tid + 2];
if (blockSize >= 2) sdata[tid] += sdata[tid + 1];
}
//WRITE RESULT TO GLOB MEM
if(tid == 0) d_odat[blockIdx.x] = sdata[0];
}
// ****************************************** //
// ***INTS HOST SIDE KERNEL CALLER PROGRAM*** //
// ****************************************** //
//DEVICE ARRAY (d_idat) NEEDS TO BE DEFINED IN PARENT PROGRAM
extern void cuda_asum_intm(int *d_idat, int N_elem) //sqrt(N_elem) must be an int
{
//THREAD AND BLOCK SIZES
unsigned int THREAD_SIZE = 512/2;
unsigned int BLOCK_SIZE = N_elem/512;
unsigned int FINAL_THREAD;
if (N_elem > 512)
{
//SUM THE ARRAY THROUGH MULTIPLE KERNEL CALLS
while(BLOCK_SIZE > 1)
{
//RUN REDUCTIONS
switch (THREAD_SIZE)
{
case 512:
cuda_asum_int<512><<<BLOCK_SIZE,THREAD_SIZE,512*sizeof(int)>>>(d_idat,d_idat); break;
case 256:
cuda_asum_int<256><<<BLOCK_SIZE,THREAD_SIZE,256*sizeof(int)>>>(d_idat,d_idat); break;
case 128:
cuda_asum_int<128><<<BLOCK_SIZE,THREAD_SIZE,128*sizeof(int)>>>(d_idat,d_idat); break;
case 64:
cuda_asum_int< 64><<<BLOCK_SIZE,THREAD_SIZE,64*sizeof(int)>>>(d_idat,d_idat); break;
case 32:
cuda_asum_int< 32><<<BLOCK_SIZE,THREAD_SIZE,32*sizeof(int)>>>(d_idat,d_idat); break;
case 16:
cuda_asum_int< 16><<<BLOCK_SIZE,THREAD_SIZE,16*sizeof(int)>>>(d_idat,d_idat); break;
case 8:
cuda_asum_int< 8><<<BLOCK_SIZE,THREAD_SIZE,8*sizeof(int)>>>(d_idat,d_idat); break;
case 4:
cuda_asum_int< 4><<<BLOCK_SIZE,THREAD_SIZE,4*sizeof(int)>>>(d_idat,d_idat); break;
case 2:
cuda_asum_int< 2><<<BLOCK_SIZE,THREAD_SIZE,2*sizeof(int)>>>(d_idat,d_idat); break;
case 1:
cuda_asum_int< 1><<<BLOCK_SIZE,THREAD_SIZE,1*sizeof(int)>>>(d_idat,d_idat); break;
}
//cuda_asum_int<<<BLOCK_SIZE,THREAD_SIZE,512*sizeof(int)>>>(d_idat,d_idat);
FINAL_THREAD = BLOCK_SIZE;
BLOCK_SIZE = BLOCK_SIZE/512;
}
} else {
FINAL_THREAD = (unsigned int)N_elem;
}
THREAD_SIZE = FINAL_THREAD/2;
BLOCK_SIZE = 1;
//RUN REDUCTIONS
switch (THREAD_SIZE)
{
case 512:
cuda_asum_int<512><<<BLOCK_SIZE,THREAD_SIZE,512*sizeof(int)>>>(d_idat,d_idat); break;
case 256:
cuda_asum_int<256><<<BLOCK_SIZE,THREAD_SIZE,256*sizeof(int)>>>(d_idat,d_idat); break;
case 128:
cuda_asum_int<128><<<BLOCK_SIZE,THREAD_SIZE,128*sizeof(int)>>>(d_idat,d_idat); break;
case 64:
cuda_asum_int< 64><<<BLOCK_SIZE,THREAD_SIZE,64*sizeof(int)>>>(d_idat,d_idat); break;
case 32:
cuda_asum_int< 32><<<BLOCK_SIZE,THREAD_SIZE,32*sizeof(int)>>>(d_idat,d_idat); break;
case 16:
cuda_asum_int< 16><<<BLOCK_SIZE,THREAD_SIZE,16*sizeof(int)>>>(d_idat,d_idat); break;
case 8:
cuda_asum_int< 8><<<BLOCK_SIZE,THREAD_SIZE,8*sizeof(int)>>>(d_idat,d_idat); break;
case 4:
cuda_asum_int< 4><<<BLOCK_SIZE,THREAD_SIZE,4*sizeof(int)>>>(d_idat,d_idat); break;
case 2:
cuda_asum_int< 2><<<BLOCK_SIZE,THREAD_SIZE,2*sizeof(int)>>>(d_idat,d_idat); break;
case 1:
cuda_asum_int< 1><<<BLOCK_SIZE,THREAD_SIZE,1*sizeof(int)>>>(d_idat,d_idat); break;
}
}
// ********************************************************************* //
// ************************FLOAT ARRAY SUMMATION************************ //
// ********************************************************************* //
// ****************************************** //
// ****FLOATS DEVICE SIDE KERNEL PROGRAM***** //
// ****************************************** //
template <unsigned int blockSizeflt>
__global__ void cuda_asum_flt(float *d_idat, float *d_odat)
{
extern __shared__ float sdataf[];
//LOAD ELEMENT FROM GLOBAL TO SHARED MEM
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * (blockDim.x * 2) + tid;
sdataf[tid] = d_idat[i] + d_idat[i + blockDim.x];
__syncthreads();
//REDUCTION
if (blockSizeflt >= 1024)
{
if (tid < 512) {sdataf[tid] += sdataf[tid + 512];} __syncthreads();
}
if (blockSizeflt >= 512)
{
if (tid < 256) {sdataf[tid] += sdataf[tid + 256];} __syncthreads();
}
if (blockSizeflt >= 256)
{
if (tid < 128) {sdataf[tid] += sdataf[tid + 128];} __syncthreads();
}
if (tid < 64)
{
if (blockSizeflt >= 128) sdataf[tid] += sdataf[tid + 64];__syncthreads();
if (blockSizeflt >= 64) sdataf[tid] += sdataf[tid + 32];__syncthreads();
if (blockSizeflt >= 32) sdataf[tid] += sdataf[tid + 16];__syncthreads();
if (blockSizeflt >= 16) sdataf[tid] += sdataf[tid + 8];__syncthreads();
if (blockSizeflt >= 8) sdataf[tid] += sdataf[tid + 4];__syncthreads();
if (blockSizeflt >= 4) sdataf[tid] += sdataf[tid + 2];__syncthreads();
if (blockSizeflt >= 2) sdataf[tid] += sdataf[tid + 1];__syncthreads();
}
//WRITE RESULT TO GLOB MEM
if(tid == 0) d_odat[blockIdx.x] = sdataf[0];
}
// ****************************************** //
// **FLOATS HOST SIDE KERNEL CALLER PROGRAM** //
// ****************************************** //
//DEVICE ARRAY (d_idat) NEEDS TO BE DEFINED IN PARENT PROGRAM
extern void cuda_asum_fltm(float *d_idat, int N_elem,int MAX_THREADS) //sqrt(N_elem) must be an int
{
//THREAD AND BLOCK SIZES
unsigned int THREAD_SIZE = MAX_THREADS;
unsigned int BLOCK_SIZE = N_elem/(MAX_THREADS*2);
unsigned int FINAL_THREAD;
if (N_elem > THREAD_SIZE)
{
//SUM THE ARRAY THROUGH MULTIPLE KERNEL CALLS
while(BLOCK_SIZE > 1)
{
//RUN REDUCTIONS
switch (THREAD_SIZE)
{
case 1024:
cuda_asum_flt<1024><<<BLOCK_SIZE,THREAD_SIZE,1024*sizeof(int)>>>(d_idat,d_idat); break;
case 512:
cuda_asum_flt<512><<<BLOCK_SIZE,THREAD_SIZE,512*sizeof(int)>>>(d_idat,d_idat); break;
case 256:
cuda_asum_flt<256><<<BLOCK_SIZE,THREAD_SIZE,256*sizeof(int)>>>(d_idat,d_idat); break;
case 128:
cuda_asum_flt<128><<<BLOCK_SIZE,THREAD_SIZE,128*sizeof(int)>>>(d_idat,d_idat); break;
case 64:
cuda_asum_flt< 64><<<BLOCK_SIZE,THREAD_SIZE,64*sizeof(int)>>>(d_idat,d_idat); break;
case 32:
cuda_asum_flt< 32><<<BLOCK_SIZE,THREAD_SIZE,32*sizeof(int)>>>(d_idat,d_idat); break;
case 16:
cuda_asum_flt< 16><<<BLOCK_SIZE,THREAD_SIZE,16*sizeof(int)>>>(d_idat,d_idat); break;
case 8:
cuda_asum_flt< 8><<<BLOCK_SIZE,THREAD_SIZE,8*sizeof(int)>>>(d_idat,d_idat); break;
case 4:
cuda_asum_flt< 4><<<BLOCK_SIZE,THREAD_SIZE,4*sizeof(int)>>>(d_idat,d_idat); break;
case 2:
cuda_asum_flt< 2><<<BLOCK_SIZE,THREAD_SIZE,2*sizeof(int)>>>(d_idat,d_idat); break;
case 1:
cuda_asum_flt< 1><<<BLOCK_SIZE,THREAD_SIZE,1*sizeof(int)>>>(d_idat,d_idat); break;
}
FINAL_THREAD = BLOCK_SIZE;
BLOCK_SIZE = BLOCK_SIZE/1024;
}
} else {
FINAL_THREAD = (unsigned int)N_elem/2;
}
THREAD_SIZE = FINAL_THREAD/2;
BLOCK_SIZE = 1;
//RUN REDUCTIONS
switch (THREAD_SIZE)
{
case 1024:
cuda_asum_flt<1024><<<BLOCK_SIZE,THREAD_SIZE,1024*sizeof(int)>>>(d_idat,d_idat); break;
case 512:
cuda_asum_flt<512><<<BLOCK_SIZE,THREAD_SIZE,512*sizeof(int)>>>(d_idat,d_idat); break;
case 256:
cuda_asum_flt<256><<<BLOCK_SIZE,THREAD_SIZE,256*sizeof(int)>>>(d_idat,d_idat); break;
case 128:
cuda_asum_flt<128><<<BLOCK_SIZE,THREAD_SIZE,128*sizeof(int)>>>(d_idat,d_idat); break;
case 64:
cuda_asum_flt< 64><<<BLOCK_SIZE,THREAD_SIZE,64*sizeof(int)>>>(d_idat,d_idat); break;
case 32:
cuda_asum_flt< 32><<<BLOCK_SIZE,THREAD_SIZE,32*sizeof(int)>>>(d_idat,d_idat); break;
case 16:
cuda_asum_flt< 16><<<BLOCK_SIZE,THREAD_SIZE,16*sizeof(int)>>>(d_idat,d_idat); break;
case 8:
cuda_asum_flt< 8><<<BLOCK_SIZE,THREAD_SIZE,8*sizeof(int)>>>(d_idat,d_idat); break;
case 4:
cuda_asum_flt< 4><<<BLOCK_SIZE,THREAD_SIZE,4*sizeof(int)>>>(d_idat,d_idat); break;
case 2:
cuda_asum_flt< 2><<<BLOCK_SIZE,THREAD_SIZE,2*sizeof(int)>>>(d_idat,d_idat); break;
case 1:
cuda_asum_flt< 1><<<BLOCK_SIZE,THREAD_SIZE,1*sizeof(int)>>>(d_idat,d_idat); break;
}
}
// ********************************************************************* //
// ***********************DOUBLE ARRAY SUMMATION************************ //
// ********************************************************************* //
// ****************************************** //
// ****DOUBLES DEVICE SIDE KERNEL PROGRAM**** //
// ****************************************** //
template <unsigned int blockSizedoub>
__global__ void cuda_asum_doub(double *d_idat, double *d_odat)
{
extern __shared__ double sdatad[];
//LOAD ELEMENT FROM GLOBAL TO SHARED MEM
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * (blockDim.x * 2) + tid;
sdatad[tid] = d_idat[i] + d_idat[i + blockDim.x];
__syncthreads();
//REDUCTION
if (blockSizedoub >= 512)
{
if (tid < 256) {sdatad[tid] += sdatad[tid + 256];} __syncthreads();
}
if (blockSizedoub >= 256)
{
if (tid < 128) {sdatad[tid] += sdatad[tid + 128];} __syncthreads();
}
if (blockSizedoub >= 128)
{
if (tid < 64) {sdatad[tid] += sdatad[tid + 64];} __syncthreads();
}
if (tid < 32)
{
if (blockSizedoub >= 64) sdatad[tid] += sdatad[tid + 32];
if (blockSizedoub >= 32) sdatad[tid] += sdatad[tid + 16];
if (blockSizedoub >= 16) sdatad[tid] += sdatad[tid + 8];
if (blockSizedoub >= 8) sdatad[tid] += sdatad[tid + 4];
if (blockSizedoub >= 4) sdatad[tid] += sdatad[tid + 2];
if (blockSizedoub >= 2) sdatad[tid] += sdatad[tid + 1];
}
//WRITE RESULT TO GLOB MEM
if(tid == 0) d_odat[blockIdx.x] = sdatad[0];
}
// ****************************************** //
// *DOUBLES HOST SIDE KERNEL CALLER PROGRAM** //
// ****************************************** //
//DEVICE ARRAY (d_idat) NEEDS TO BE DEFINED IN PARENT PROGRAM
extern void cuda_asum_doubm(double *d_idat, double N_elem) //sqrt(N_elem) must be an int
{
//THREAD AND BLOCK SIZES
unsigned int THREAD_SIZE = 512/2;
unsigned int BLOCK_SIZE = N_elem/512;
unsigned int FINAL_THREAD;
if (N_elem > 512)
{
//SUM THE ARRAY THROUGH MULTIPLE KERNEL CALLS
while(BLOCK_SIZE > 1)
{
//RUN REDUCTIONS
switch (THREAD_SIZE)
{
case 512:
cuda_asum_doub<512><<<BLOCK_SIZE,THREAD_SIZE,512*sizeof(double)>>>(d_idat,d_idat); break;
case 256:
cuda_asum_doub<256><<<BLOCK_SIZE,THREAD_SIZE,256*sizeof(double)>>>(d_idat,d_idat); break;
case 128:
cuda_asum_doub<128><<<BLOCK_SIZE,THREAD_SIZE,128*sizeof(double)>>>(d_idat,d_idat); break;
case 64:
cuda_asum_doub< 64><<<BLOCK_SIZE,THREAD_SIZE,64*sizeof(double)>>>(d_idat,d_idat); break;
case 32:
cuda_asum_doub< 32><<<BLOCK_SIZE,THREAD_SIZE,32*sizeof(double)>>>(d_idat,d_idat); break;
case 16:
cuda_asum_doub< 16><<<BLOCK_SIZE,THREAD_SIZE,16*sizeof(double)>>>(d_idat,d_idat); break;
case 8:
cuda_asum_doub< 8><<<BLOCK_SIZE,THREAD_SIZE,8*sizeof(double)>>>(d_idat,d_idat); break;
case 4:
cuda_asum_doub< 4><<<BLOCK_SIZE,THREAD_SIZE,4*sizeof(double)>>>(d_idat,d_idat); break;
case 2:
cuda_asum_doub< 2><<<BLOCK_SIZE,THREAD_SIZE,2*sizeof(double)>>>(d_idat,d_idat); break;
case 1:
cuda_asum_doub< 1><<<BLOCK_SIZE,THREAD_SIZE,1*sizeof(double)>>>(d_idat,d_idat); break;
}
//cuda_asum_int<<<BLOCK_SIZE,THREAD_SIZE,512*sizeof(int)>>>(d_idat,d_idat);
FINAL_THREAD = BLOCK_SIZE;
BLOCK_SIZE = BLOCK_SIZE/512;
}
} else {
FINAL_THREAD = (unsigned int)N_elem;
}
// THIS SECTION BEGINS WITH THREADS NEEDED ARE LESS THAN MAXIMUM BLOCK SIZE
THREAD_SIZE = FINAL_THREAD/2;
BLOCK_SIZE = 1;
//RUN REDUCTIONS
switch (THREAD_SIZE)
{
case 512:
cuda_asum_doub<512><<<BLOCK_SIZE,THREAD_SIZE,512*sizeof(double)>>>(d_idat,d_idat); break;
case 256:
cuda_asum_doub<256><<<BLOCK_SIZE,THREAD_SIZE,256*sizeof(double)>>>(d_idat,d_idat); break;
case 128:
cuda_asum_doub<128><<<BLOCK_SIZE,THREAD_SIZE,128*sizeof(double)>>>(d_idat,d_idat); break;
case 64:
cuda_asum_doub< 64><<<BLOCK_SIZE,THREAD_SIZE,64*sizeof(double)>>>(d_idat,d_idat); break;
case 32:
cuda_asum_doub< 32><<<BLOCK_SIZE,THREAD_SIZE,32*sizeof(double)>>>(d_idat,d_idat); break;
case 16:
cuda_asum_doub< 16><<<BLOCK_SIZE,THREAD_SIZE,16*sizeof(double)>>>(d_idat,d_idat); break;
case 8:
cuda_asum_doub< 8><<<BLOCK_SIZE,THREAD_SIZE,8*sizeof(double)>>>(d_idat,d_idat); break;
case 4:
cuda_asum_doub< 4><<<BLOCK_SIZE,THREAD_SIZE,4*sizeof(double)>>>(d_idat,d_idat); break;
case 2:
cuda_asum_doub< 2><<<BLOCK_SIZE,THREAD_SIZE,2*sizeof(double)>>>(d_idat,d_idat); break;
case 1:
cuda_asum_doub< 1><<<BLOCK_SIZE,THREAD_SIZE,1*sizeof(double)>>>(d_idat,d_idat); break;
}
} | /**************************************************
*******PROGRAM FOR ARRAY REDUCTION IN CUDA*********
***************************************************
* EXTERNAL PROGRAMS INCLUDED: *
* *
* SUMS UPTO 2^24 INTS BEFORE REACHING BLOCK LIMIT *
* ARRAY MUST CONTAIN POWER OF TWO ELEMENTS *
* PROGRAM INCLUDES INTS,FLOATS AND DOUBS *
* *
* Call INTS: cuda_asum_intm(ipt/opt array, N#s) *
* Call FLTS: cuda_asum_fltm(ipt/opt array, N#s) *
* Call DOUBS: cuda_asum_doubm(ipt/opt array, N#s) *
* *
***************************************************/
// *** INCLUDED LIBRARIES*** //
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <hip/hip_runtime.h>
// ***CUDA ERROR HANDLER*** //
#define CUDA_CALL(x) do { if((x) != hipSuccess) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
// ********************************************************************* //
// **********************INTEGER ARRAY SUMMATION************************ //
// ********************************************************************* //
// ****************************************** //
// ***INTEGERS DEVICE SIDE KERNEL PROGRAM**** //
// ****************************************** //
template <unsigned int blockSize>
__global__ void cuda_asum_int(int *d_idat, int *d_odat)
{
extern __shared__ int sdata[];
//LOAD ELEMENT FROM GLOBAL TO SHARED MEM
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * (blockDim.x * 2) + tid;
sdata[tid] = d_idat[i] + d_idat[i + blockDim.x];
__syncthreads();
//REDUCTION
if (blockSize >= 512)
{
if (tid < 256) {sdata[tid] += sdata[tid + 256];} __syncthreads();
}
if (blockSize >= 256)
{
if (tid < 128) {sdata[tid] += sdata[tid + 128];} __syncthreads();
}
if (blockSize >= 128)
{
if (tid < 64) {sdata[tid] += sdata[tid + 64];} __syncthreads();
}
if (tid < 32)
{
if (blockSize >= 64) sdata[tid] += sdata[tid + 32];
if (blockSize >= 32) sdata[tid] += sdata[tid + 16];
if (blockSize >= 16) sdata[tid] += sdata[tid + 8];
if (blockSize >= 8) sdata[tid] += sdata[tid + 4];
if (blockSize >= 4) sdata[tid] += sdata[tid + 2];
if (blockSize >= 2) sdata[tid] += sdata[tid + 1];
}
//WRITE RESULT TO GLOB MEM
if(tid == 0) d_odat[blockIdx.x] = sdata[0];
}
// ****************************************** //
// ***INTS HOST SIDE KERNEL CALLER PROGRAM*** //
// ****************************************** //
//DEVICE ARRAY (d_idat) NEEDS TO BE DEFINED IN PARENT PROGRAM
extern void cuda_asum_intm(int *d_idat, int N_elem) //sqrt(N_elem) must be an int
{
//THREAD AND BLOCK SIZES
unsigned int THREAD_SIZE = 512/2;
unsigned int BLOCK_SIZE = N_elem/512;
unsigned int FINAL_THREAD;
if (N_elem > 512)
{
//SUM THE ARRAY THROUGH MULTIPLE KERNEL CALLS
while(BLOCK_SIZE > 1)
{
//RUN REDUCTIONS
switch (THREAD_SIZE)
{
case 512:
cuda_asum_int<512><<<BLOCK_SIZE,THREAD_SIZE,512*sizeof(int)>>>(d_idat,d_idat); break;
case 256:
cuda_asum_int<256><<<BLOCK_SIZE,THREAD_SIZE,256*sizeof(int)>>>(d_idat,d_idat); break;
case 128:
cuda_asum_int<128><<<BLOCK_SIZE,THREAD_SIZE,128*sizeof(int)>>>(d_idat,d_idat); break;
case 64:
cuda_asum_int< 64><<<BLOCK_SIZE,THREAD_SIZE,64*sizeof(int)>>>(d_idat,d_idat); break;
case 32:
cuda_asum_int< 32><<<BLOCK_SIZE,THREAD_SIZE,32*sizeof(int)>>>(d_idat,d_idat); break;
case 16:
cuda_asum_int< 16><<<BLOCK_SIZE,THREAD_SIZE,16*sizeof(int)>>>(d_idat,d_idat); break;
case 8:
cuda_asum_int< 8><<<BLOCK_SIZE,THREAD_SIZE,8*sizeof(int)>>>(d_idat,d_idat); break;
case 4:
cuda_asum_int< 4><<<BLOCK_SIZE,THREAD_SIZE,4*sizeof(int)>>>(d_idat,d_idat); break;
case 2:
cuda_asum_int< 2><<<BLOCK_SIZE,THREAD_SIZE,2*sizeof(int)>>>(d_idat,d_idat); break;
case 1:
cuda_asum_int< 1><<<BLOCK_SIZE,THREAD_SIZE,1*sizeof(int)>>>(d_idat,d_idat); break;
}
//cuda_asum_int<<<BLOCK_SIZE,THREAD_SIZE,512*sizeof(int)>>>(d_idat,d_idat);
FINAL_THREAD = BLOCK_SIZE;
BLOCK_SIZE = BLOCK_SIZE/512;
}
} else {
FINAL_THREAD = (unsigned int)N_elem;
}
THREAD_SIZE = FINAL_THREAD/2;
BLOCK_SIZE = 1;
//RUN REDUCTIONS
switch (THREAD_SIZE)
{
case 512:
cuda_asum_int<512><<<BLOCK_SIZE,THREAD_SIZE,512*sizeof(int)>>>(d_idat,d_idat); break;
case 256:
cuda_asum_int<256><<<BLOCK_SIZE,THREAD_SIZE,256*sizeof(int)>>>(d_idat,d_idat); break;
case 128:
cuda_asum_int<128><<<BLOCK_SIZE,THREAD_SIZE,128*sizeof(int)>>>(d_idat,d_idat); break;
case 64:
cuda_asum_int< 64><<<BLOCK_SIZE,THREAD_SIZE,64*sizeof(int)>>>(d_idat,d_idat); break;
case 32:
cuda_asum_int< 32><<<BLOCK_SIZE,THREAD_SIZE,32*sizeof(int)>>>(d_idat,d_idat); break;
case 16:
cuda_asum_int< 16><<<BLOCK_SIZE,THREAD_SIZE,16*sizeof(int)>>>(d_idat,d_idat); break;
case 8:
cuda_asum_int< 8><<<BLOCK_SIZE,THREAD_SIZE,8*sizeof(int)>>>(d_idat,d_idat); break;
case 4:
cuda_asum_int< 4><<<BLOCK_SIZE,THREAD_SIZE,4*sizeof(int)>>>(d_idat,d_idat); break;
case 2:
cuda_asum_int< 2><<<BLOCK_SIZE,THREAD_SIZE,2*sizeof(int)>>>(d_idat,d_idat); break;
case 1:
cuda_asum_int< 1><<<BLOCK_SIZE,THREAD_SIZE,1*sizeof(int)>>>(d_idat,d_idat); break;
}
}
// ********************************************************************* //
// ************************FLOAT ARRAY SUMMATION************************ //
// ********************************************************************* //
// ****************************************** //
// ****FLOATS DEVICE SIDE KERNEL PROGRAM***** //
// ****************************************** //
template <unsigned int blockSizeflt>
__global__ void cuda_asum_flt(float *d_idat, float *d_odat)
{
extern __shared__ float sdataf[];
//LOAD ELEMENT FROM GLOBAL TO SHARED MEM
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * (blockDim.x * 2) + tid;
sdataf[tid] = d_idat[i] + d_idat[i + blockDim.x];
__syncthreads();
//REDUCTION
if (blockSizeflt >= 1024)
{
if (tid < 512) {sdataf[tid] += sdataf[tid + 512];} __syncthreads();
}
if (blockSizeflt >= 512)
{
if (tid < 256) {sdataf[tid] += sdataf[tid + 256];} __syncthreads();
}
if (blockSizeflt >= 256)
{
if (tid < 128) {sdataf[tid] += sdataf[tid + 128];} __syncthreads();
}
if (tid < 64)
{
if (blockSizeflt >= 128) sdataf[tid] += sdataf[tid + 64];__syncthreads();
if (blockSizeflt >= 64) sdataf[tid] += sdataf[tid + 32];__syncthreads();
if (blockSizeflt >= 32) sdataf[tid] += sdataf[tid + 16];__syncthreads();
if (blockSizeflt >= 16) sdataf[tid] += sdataf[tid + 8];__syncthreads();
if (blockSizeflt >= 8) sdataf[tid] += sdataf[tid + 4];__syncthreads();
if (blockSizeflt >= 4) sdataf[tid] += sdataf[tid + 2];__syncthreads();
if (blockSizeflt >= 2) sdataf[tid] += sdataf[tid + 1];__syncthreads();
}
//WRITE RESULT TO GLOB MEM
if(tid == 0) d_odat[blockIdx.x] = sdataf[0];
}
// ****************************************** //
// **FLOATS HOST SIDE KERNEL CALLER PROGRAM** //
// ****************************************** //
//DEVICE ARRAY (d_idat) NEEDS TO BE DEFINED IN PARENT PROGRAM
extern void cuda_asum_fltm(float *d_idat, int N_elem,int MAX_THREADS) //sqrt(N_elem) must be an int
{
//THREAD AND BLOCK SIZES
unsigned int THREAD_SIZE = MAX_THREADS;
unsigned int BLOCK_SIZE = N_elem/(MAX_THREADS*2);
unsigned int FINAL_THREAD;
if (N_elem > THREAD_SIZE)
{
//SUM THE ARRAY THROUGH MULTIPLE KERNEL CALLS
while(BLOCK_SIZE > 1)
{
//RUN REDUCTIONS
switch (THREAD_SIZE)
{
case 1024:
cuda_asum_flt<1024><<<BLOCK_SIZE,THREAD_SIZE,1024*sizeof(int)>>>(d_idat,d_idat); break;
case 512:
cuda_asum_flt<512><<<BLOCK_SIZE,THREAD_SIZE,512*sizeof(int)>>>(d_idat,d_idat); break;
case 256:
cuda_asum_flt<256><<<BLOCK_SIZE,THREAD_SIZE,256*sizeof(int)>>>(d_idat,d_idat); break;
case 128:
cuda_asum_flt<128><<<BLOCK_SIZE,THREAD_SIZE,128*sizeof(int)>>>(d_idat,d_idat); break;
case 64:
cuda_asum_flt< 64><<<BLOCK_SIZE,THREAD_SIZE,64*sizeof(int)>>>(d_idat,d_idat); break;
case 32:
cuda_asum_flt< 32><<<BLOCK_SIZE,THREAD_SIZE,32*sizeof(int)>>>(d_idat,d_idat); break;
case 16:
cuda_asum_flt< 16><<<BLOCK_SIZE,THREAD_SIZE,16*sizeof(int)>>>(d_idat,d_idat); break;
case 8:
cuda_asum_flt< 8><<<BLOCK_SIZE,THREAD_SIZE,8*sizeof(int)>>>(d_idat,d_idat); break;
case 4:
cuda_asum_flt< 4><<<BLOCK_SIZE,THREAD_SIZE,4*sizeof(int)>>>(d_idat,d_idat); break;
case 2:
cuda_asum_flt< 2><<<BLOCK_SIZE,THREAD_SIZE,2*sizeof(int)>>>(d_idat,d_idat); break;
case 1:
cuda_asum_flt< 1><<<BLOCK_SIZE,THREAD_SIZE,1*sizeof(int)>>>(d_idat,d_idat); break;
}
FINAL_THREAD = BLOCK_SIZE;
BLOCK_SIZE = BLOCK_SIZE/1024;
}
} else {
FINAL_THREAD = (unsigned int)N_elem/2;
}
THREAD_SIZE = FINAL_THREAD/2;
BLOCK_SIZE = 1;
//RUN REDUCTIONS
switch (THREAD_SIZE)
{
case 1024:
cuda_asum_flt<1024><<<BLOCK_SIZE,THREAD_SIZE,1024*sizeof(int)>>>(d_idat,d_idat); break;
case 512:
cuda_asum_flt<512><<<BLOCK_SIZE,THREAD_SIZE,512*sizeof(int)>>>(d_idat,d_idat); break;
case 256:
cuda_asum_flt<256><<<BLOCK_SIZE,THREAD_SIZE,256*sizeof(int)>>>(d_idat,d_idat); break;
case 128:
cuda_asum_flt<128><<<BLOCK_SIZE,THREAD_SIZE,128*sizeof(int)>>>(d_idat,d_idat); break;
case 64:
cuda_asum_flt< 64><<<BLOCK_SIZE,THREAD_SIZE,64*sizeof(int)>>>(d_idat,d_idat); break;
case 32:
cuda_asum_flt< 32><<<BLOCK_SIZE,THREAD_SIZE,32*sizeof(int)>>>(d_idat,d_idat); break;
case 16:
cuda_asum_flt< 16><<<BLOCK_SIZE,THREAD_SIZE,16*sizeof(int)>>>(d_idat,d_idat); break;
case 8:
cuda_asum_flt< 8><<<BLOCK_SIZE,THREAD_SIZE,8*sizeof(int)>>>(d_idat,d_idat); break;
case 4:
cuda_asum_flt< 4><<<BLOCK_SIZE,THREAD_SIZE,4*sizeof(int)>>>(d_idat,d_idat); break;
case 2:
cuda_asum_flt< 2><<<BLOCK_SIZE,THREAD_SIZE,2*sizeof(int)>>>(d_idat,d_idat); break;
case 1:
cuda_asum_flt< 1><<<BLOCK_SIZE,THREAD_SIZE,1*sizeof(int)>>>(d_idat,d_idat); break;
}
}
// ********************************************************************* //
// ***********************DOUBLE ARRAY SUMMATION************************ //
// ********************************************************************* //
// ****************************************** //
// ****DOUBLES DEVICE SIDE KERNEL PROGRAM**** //
// ****************************************** //
template <unsigned int blockSizedoub>
__global__ void cuda_asum_doub(double *d_idat, double *d_odat)
{
extern __shared__ double sdatad[];
//LOAD ELEMENT FROM GLOBAL TO SHARED MEM
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * (blockDim.x * 2) + tid;
sdatad[tid] = d_idat[i] + d_idat[i + blockDim.x];
__syncthreads();
//REDUCTION
if (blockSizedoub >= 512)
{
if (tid < 256) {sdatad[tid] += sdatad[tid + 256];} __syncthreads();
}
if (blockSizedoub >= 256)
{
if (tid < 128) {sdatad[tid] += sdatad[tid + 128];} __syncthreads();
}
if (blockSizedoub >= 128)
{
if (tid < 64) {sdatad[tid] += sdatad[tid + 64];} __syncthreads();
}
if (tid < 32)
{
if (blockSizedoub >= 64) sdatad[tid] += sdatad[tid + 32];
if (blockSizedoub >= 32) sdatad[tid] += sdatad[tid + 16];
if (blockSizedoub >= 16) sdatad[tid] += sdatad[tid + 8];
if (blockSizedoub >= 8) sdatad[tid] += sdatad[tid + 4];
if (blockSizedoub >= 4) sdatad[tid] += sdatad[tid + 2];
if (blockSizedoub >= 2) sdatad[tid] += sdatad[tid + 1];
}
//WRITE RESULT TO GLOB MEM
if(tid == 0) d_odat[blockIdx.x] = sdatad[0];
}
// ****************************************** //
// *DOUBLES HOST SIDE KERNEL CALLER PROGRAM** //
// ****************************************** //
//DEVICE ARRAY (d_idat) NEEDS TO BE DEFINED IN PARENT PROGRAM
extern void cuda_asum_doubm(double *d_idat, double N_elem) //sqrt(N_elem) must be an int
{
//THREAD AND BLOCK SIZES
unsigned int THREAD_SIZE = 512/2;
unsigned int BLOCK_SIZE = N_elem/512;
unsigned int FINAL_THREAD;
if (N_elem > 512)
{
//SUM THE ARRAY THROUGH MULTIPLE KERNEL CALLS
while(BLOCK_SIZE > 1)
{
//RUN REDUCTIONS
switch (THREAD_SIZE)
{
case 512:
cuda_asum_doub<512><<<BLOCK_SIZE,THREAD_SIZE,512*sizeof(double)>>>(d_idat,d_idat); break;
case 256:
cuda_asum_doub<256><<<BLOCK_SIZE,THREAD_SIZE,256*sizeof(double)>>>(d_idat,d_idat); break;
case 128:
cuda_asum_doub<128><<<BLOCK_SIZE,THREAD_SIZE,128*sizeof(double)>>>(d_idat,d_idat); break;
case 64:
cuda_asum_doub< 64><<<BLOCK_SIZE,THREAD_SIZE,64*sizeof(double)>>>(d_idat,d_idat); break;
case 32:
cuda_asum_doub< 32><<<BLOCK_SIZE,THREAD_SIZE,32*sizeof(double)>>>(d_idat,d_idat); break;
case 16:
cuda_asum_doub< 16><<<BLOCK_SIZE,THREAD_SIZE,16*sizeof(double)>>>(d_idat,d_idat); break;
case 8:
cuda_asum_doub< 8><<<BLOCK_SIZE,THREAD_SIZE,8*sizeof(double)>>>(d_idat,d_idat); break;
case 4:
cuda_asum_doub< 4><<<BLOCK_SIZE,THREAD_SIZE,4*sizeof(double)>>>(d_idat,d_idat); break;
case 2:
cuda_asum_doub< 2><<<BLOCK_SIZE,THREAD_SIZE,2*sizeof(double)>>>(d_idat,d_idat); break;
case 1:
cuda_asum_doub< 1><<<BLOCK_SIZE,THREAD_SIZE,1*sizeof(double)>>>(d_idat,d_idat); break;
}
//cuda_asum_int<<<BLOCK_SIZE,THREAD_SIZE,512*sizeof(int)>>>(d_idat,d_idat);
FINAL_THREAD = BLOCK_SIZE;
BLOCK_SIZE = BLOCK_SIZE/512;
}
} else {
FINAL_THREAD = (unsigned int)N_elem;
}
// THIS SECTION BEGINS WITH THREADS NEEDED ARE LESS THAN MAXIMUM BLOCK SIZE
THREAD_SIZE = FINAL_THREAD/2;
BLOCK_SIZE = 1;
//RUN REDUCTIONS
switch (THREAD_SIZE)
{
case 512:
cuda_asum_doub<512><<<BLOCK_SIZE,THREAD_SIZE,512*sizeof(double)>>>(d_idat,d_idat); break;
case 256:
cuda_asum_doub<256><<<BLOCK_SIZE,THREAD_SIZE,256*sizeof(double)>>>(d_idat,d_idat); break;
case 128:
cuda_asum_doub<128><<<BLOCK_SIZE,THREAD_SIZE,128*sizeof(double)>>>(d_idat,d_idat); break;
case 64:
cuda_asum_doub< 64><<<BLOCK_SIZE,THREAD_SIZE,64*sizeof(double)>>>(d_idat,d_idat); break;
case 32:
cuda_asum_doub< 32><<<BLOCK_SIZE,THREAD_SIZE,32*sizeof(double)>>>(d_idat,d_idat); break;
case 16:
cuda_asum_doub< 16><<<BLOCK_SIZE,THREAD_SIZE,16*sizeof(double)>>>(d_idat,d_idat); break;
case 8:
cuda_asum_doub< 8><<<BLOCK_SIZE,THREAD_SIZE,8*sizeof(double)>>>(d_idat,d_idat); break;
case 4:
cuda_asum_doub< 4><<<BLOCK_SIZE,THREAD_SIZE,4*sizeof(double)>>>(d_idat,d_idat); break;
case 2:
cuda_asum_doub< 2><<<BLOCK_SIZE,THREAD_SIZE,2*sizeof(double)>>>(d_idat,d_idat); break;
case 1:
cuda_asum_doub< 1><<<BLOCK_SIZE,THREAD_SIZE,1*sizeof(double)>>>(d_idat,d_idat); break;
}
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define N (4096*4096)
#define HILOS_POR_BLOQUE 512
__global__ void sumaenlagpu(int *a, int *b, int *c, int n){
int index = threadIdx.x + blockIdx.x*blockDim.x;
if (index < n){
c[index] = a[index] + b[index];
}
} | code for sm_80
Function : _Z11sumaenlagpuPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define N (4096*4096)
#define HILOS_POR_BLOQUE 512
__global__ void sumaenlagpu(int *a, int *b, int *c, int n){
int index = threadIdx.x + blockIdx.x*blockDim.x;
if (index < n){
c[index] = a[index] + b[index];
}
} | .file "tmpxft_001a7056_00000000-6_sumaenlagpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z11sumaenlagpuPiS_S_iPiS_S_i
.type _Z36__device_stub__Z11sumaenlagpuPiS_S_iPiS_S_i, @function
_Z36__device_stub__Z11sumaenlagpuPiS_S_iPiS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11sumaenlagpuPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z11sumaenlagpuPiS_S_iPiS_S_i, .-_Z36__device_stub__Z11sumaenlagpuPiS_S_iPiS_S_i
.globl _Z11sumaenlagpuPiS_S_i
.type _Z11sumaenlagpuPiS_S_i, @function
_Z11sumaenlagpuPiS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z11sumaenlagpuPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11sumaenlagpuPiS_S_i, .-_Z11sumaenlagpuPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11sumaenlagpuPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11sumaenlagpuPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define N (4096*4096)
#define HILOS_POR_BLOQUE 512
__global__ void sumaenlagpu(int *a, int *b, int *c, int n){
int index = threadIdx.x + blockIdx.x*blockDim.x;
if (index < n){
c[index] = a[index] + b[index];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define N (4096*4096)
#define HILOS_POR_BLOQUE 512
__global__ void sumaenlagpu(int *a, int *b, int *c, int n){
int index = threadIdx.x + blockIdx.x*blockDim.x;
if (index < n){
c[index] = a[index] + b[index];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define N (4096*4096)
#define HILOS_POR_BLOQUE 512
__global__ void sumaenlagpu(int *a, int *b, int *c, int n){
int index = threadIdx.x + blockIdx.x*blockDim.x;
if (index < n){
c[index] = a[index] + b[index];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11sumaenlagpuPiS_S_i
.globl _Z11sumaenlagpuPiS_S_i
.p2align 8
.type _Z11sumaenlagpuPiS_S_i,@function
_Z11sumaenlagpuPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11sumaenlagpuPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11sumaenlagpuPiS_S_i, .Lfunc_end0-_Z11sumaenlagpuPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11sumaenlagpuPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11sumaenlagpuPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define N (4096*4096)
#define HILOS_POR_BLOQUE 512
__global__ void sumaenlagpu(int *a, int *b, int *c, int n){
int index = threadIdx.x + blockIdx.x*blockDim.x;
if (index < n){
c[index] = a[index] + b[index];
}
} | .text
.file "sumaenlagpu.hip"
.globl _Z26__device_stub__sumaenlagpuPiS_S_i # -- Begin function _Z26__device_stub__sumaenlagpuPiS_S_i
.p2align 4, 0x90
.type _Z26__device_stub__sumaenlagpuPiS_S_i,@function
_Z26__device_stub__sumaenlagpuPiS_S_i: # @_Z26__device_stub__sumaenlagpuPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11sumaenlagpuPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__sumaenlagpuPiS_S_i, .Lfunc_end0-_Z26__device_stub__sumaenlagpuPiS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11sumaenlagpuPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11sumaenlagpuPiS_S_i,@object # @_Z11sumaenlagpuPiS_S_i
.section .rodata,"a",@progbits
.globl _Z11sumaenlagpuPiS_S_i
.p2align 3, 0x0
_Z11sumaenlagpuPiS_S_i:
.quad _Z26__device_stub__sumaenlagpuPiS_S_i
.size _Z11sumaenlagpuPiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11sumaenlagpuPiS_S_i"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__sumaenlagpuPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11sumaenlagpuPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11sumaenlagpuPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11sumaenlagpuPiS_S_i
.globl _Z11sumaenlagpuPiS_S_i
.p2align 8
.type _Z11sumaenlagpuPiS_S_i,@function
_Z11sumaenlagpuPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11sumaenlagpuPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11sumaenlagpuPiS_S_i, .Lfunc_end0-_Z11sumaenlagpuPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11sumaenlagpuPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11sumaenlagpuPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a7056_00000000-6_sumaenlagpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z11sumaenlagpuPiS_S_iPiS_S_i
.type _Z36__device_stub__Z11sumaenlagpuPiS_S_iPiS_S_i, @function
_Z36__device_stub__Z11sumaenlagpuPiS_S_iPiS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11sumaenlagpuPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z11sumaenlagpuPiS_S_iPiS_S_i, .-_Z36__device_stub__Z11sumaenlagpuPiS_S_iPiS_S_i
.globl _Z11sumaenlagpuPiS_S_i
.type _Z11sumaenlagpuPiS_S_i, @function
_Z11sumaenlagpuPiS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z11sumaenlagpuPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11sumaenlagpuPiS_S_i, .-_Z11sumaenlagpuPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11sumaenlagpuPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11sumaenlagpuPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sumaenlagpu.hip"
.globl _Z26__device_stub__sumaenlagpuPiS_S_i # -- Begin function _Z26__device_stub__sumaenlagpuPiS_S_i
.p2align 4, 0x90
.type _Z26__device_stub__sumaenlagpuPiS_S_i,@function
_Z26__device_stub__sumaenlagpuPiS_S_i: # @_Z26__device_stub__sumaenlagpuPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11sumaenlagpuPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__sumaenlagpuPiS_S_i, .Lfunc_end0-_Z26__device_stub__sumaenlagpuPiS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11sumaenlagpuPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11sumaenlagpuPiS_S_i,@object # @_Z11sumaenlagpuPiS_S_i
.section .rodata,"a",@progbits
.globl _Z11sumaenlagpuPiS_S_i
.p2align 3, 0x0
_Z11sumaenlagpuPiS_S_i:
.quad _Z26__device_stub__sumaenlagpuPiS_S_i
.size _Z11sumaenlagpuPiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11sumaenlagpuPiS_S_i"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__sumaenlagpuPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11sumaenlagpuPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cstdio>
#include <string>
#include <cassert>
#include <iostream>
#include <cstddef>
#include <vector>
#define uint8_t unsigned char
#define uint16_t unsigned short
#define uint32_t unsigned int
#define uint64_t unsigned long long
using namespace std;
//
// DEFAULt functions for work with cuda
//
#define CSC(call) do { \
cudaError_t res = call; \
if (res != cudaSuccess) { \
fprintf(stderr, "CUDA Error in %s:%d: %s\n", __FILE__, __LINE__, cudaGetErrorString(res)); \
exit(0); \
} \
} while (0)
cudaEvent_t start, stop;
float t;
void time_start() {
CSC(cudaEventCreate(&start));
CSC(cudaEventCreate(&stop));
CSC(cudaEventRecord(start, 0));
}
void time_end() {
CSC(cudaGetLastError());
CSC(cudaEventRecord(stop, 0));
CSC(cudaEventSynchronize(stop));
CSC(cudaEventElapsedTime(&t, start, stop));
printf("time = %f\n", t);
CSC(cudaEventDestroy(start));
CSC(cudaEventDestroy(stop));
}
double minor3x3(double m[3][3], int i, int j) {
double arr[4];
int len = 0;
for (int row = 0; row < 3; row++) {
for (int col = 0; col < 3; col++) {
if (col == j || row == i) continue;
arr[len++] = m[row][col];
}
}
return arr[0] * arr[3] - arr[1] * arr[2];
}
double cof3x3(double m[3][3], int i, int j) {
double mr = minor3x3(m, i, j);
if ((i+j) % 2 == 1)
mr *= -1;
return mr;
}
double det3x3(double m[3][3]) {
double res = 0;
for (int col = 0; col < 3; col++) {
res += m[0][col] * cof3x3(m, 0, col);
}
return res;
}
class IMG {
public:
uint32_t w;
uint32_t h;
uint64_t size;
uchar4 *data;
IMG() : w(0), h(0), size(0), data(NULL) {}
IMG(string path) {
FILE *fin = fopen(path.c_str(), "rb");
if (!fin) {
cout << "Wrong file name " << path << "!\n";
return;
}
fread(&w, sizeof(uint32_t), 1, fin);
fread(&h, sizeof(uint32_t), 1, fin);
size = w * h;
data = new uchar4[size];
fread(data, sizeof(uchar4), size, fin);
fclose(fin);
}
~IMG() {
if (data != NULL) {
delete[] data;
}
}
void toFile(string path) {
FILE *fout = fopen(path.c_str(), "wb");
if (!fout) {
cout << "Wrong file name " << path << "!\n";
return;
}
fwrite(&w, sizeof(uint32_t), 1, fout);
fwrite(&h, sizeof(uint32_t), 1, fout);
fwrite(data, sizeof(uchar4), size, fout);
fclose(fout);
}
};
//
// main programm
//
#define pixel uchar4
#define p(x, y) data[y*w + x]
vector<vector<pixel> > cls;
__constant__ double GPU_AVG[50][3];
__constant__ double GPU_INVERT_COV[50][3][3];
__device__ double mahalanobis(const pixel p, int ci) {
double v[3] = {p.x - GPU_AVG[ci][0],
p.y - GPU_AVG[ci][1],
p.z - GPU_AVG[ci][2]
};
double tmp[3] = {0, 0, 0}, res = 0;
for (int i = 0; i < 3; ++i) {
for (int j = 0; j < 3; ++j) {
tmp[i] += v[j] * GPU_INVERT_COV[ci][j][i];
}
res -= tmp[i] * v[i];
}
return res;
}
__device__ void classify(pixel &p, int cnum) {
double mx = mahalanobis(p, 0);
p.w = 0;
for (char ci = 1; ci < cnum; ++ci) {
double tmp = mahalanobis(p, ci);
if (tmp > mx) {
mx = tmp;
p.w = ci;
}
}
}
__global__ void kernel(uchar4 *data, uint32_t w, uint32_t h, int cnum) {
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int idy = blockDim.y * blockIdx.y + threadIdx.y;
int offsetx = blockDim.x * gridDim.x;
int offsety = blockDim.y * gridDim.y;
for (int x = idx; x < w; x += offsetx) {
for (int y = idy; y < h; y += offsety) {
classify(p(x, y), cnum);
}
}
}
int main() {
int cnum = 0;
string in, out;
cin >> in >> out >> cnum;
cls.resize(cnum, vector<pixel>());
double cavg[cnum][3];
double ccov[cnum][3][3];
memset(cavg, 0, sizeof(double) * cnum * 3);
memset(ccov, 0, sizeof(double) * cnum * 9);
IMG img(in);
uint32_t w = img.w;
for (int i = 0; i < cnum; ++i) {
int csize, x, y;
cin >> csize;
for (int j = 0; j < csize; ++j) {
cin >> x >> y;
pixel p = img.p(x, y);
cls[i].push_back(p);
cavg[i][0] += p.x;
cavg[i][1] += p.y;
cavg[i][2] += p.z;
}
for (int j = 0; j < 3; ++j) cavg[i][j] /= csize;
}
for (int c = 0; c < cnum; ++c) {
int csize = cls[c].size();
for (int i = 0; i < csize; ++i) {
pixel p = cls[c][i];
double coeff[3] = {p.x - cavg[c][0],
p.y - cavg[c][1],
p.z - cavg[c][2]
};
for (int r = 0; r < 3; ++r) {
for (int s = 0; s < 3; ++s) {
ccov[c][r][s] += coeff[r] * coeff[s];
}
}
}
for (int r = 0; r < 3; ++r) {
for (int s = 0; s < 3; ++s) {
ccov[c][r][s] /= csize - 1;
}
}
double det = det3x3(ccov[c]);
double icov[3][3];
for (int r = 0; r < 3; ++r) {
for (int s = 0; s < 3; ++s) {
if (det == 0) {
icov[s][r] = (r == s ? 1 : 0);
} else {
icov[s][r] = cof3x3(ccov[c], r, s) / det;
}
}
}
for (int r = 0; r < 3; ++r) {
for (int s = 0; s < 3; ++s) {
ccov[c][r][s] = icov[r][s];
}
}
}
uchar4 *result;
CSC(cudaMemcpyToSymbol(GPU_AVG, cavg, sizeof(double) * cnum * 3));
CSC(cudaMemcpyToSymbol(GPU_INVERT_COV, ccov, sizeof(double) * cnum * 9));
CSC(cudaMalloc(&result, sizeof(uchar4) * img.size));
CSC(cudaMemcpy(result, img.data, sizeof(uchar4) * img.size, cudaMemcpyHostToDevice));
kernel<<<dim3(16, 16), dim3(16, 16)>>>(result, img.w, img.h, cnum);
CSC(cudaMemcpy(img.data, result, sizeof(uchar4) * img.size, cudaMemcpyDeviceToHost));
CSC(cudaFree(result));
img.toFile(out);
} | code for sm_80
Function : _Z6kernelP6uchar4jji
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e620000002600 */
/*0040*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fc600078e0203 */
/*0050*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002200 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06070 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ ULDC UR5, c[0x0][0x170] ; /* 0x00005c0000057ab9 */
/* 0x002fe20000000800 */
/*0090*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fe200078e0203 */
/*00a0*/ UIADD3 UR4, UR5, -0x1, URZ ; /* 0xffffffff05047890 */
/* 0x000fe4000fffe03f */
/*00b0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*00c0*/ ULOP3.LUT UR4, UR4, 0x1, URZ, 0xc0, !UPT ; /* 0x0000000104047892 */
/* 0x000fc8000f8ec03f */
/*00d0*/ UIADD3 UR5, -UR4, UR5, URZ ; /* 0x0000000504057290 */
/* 0x000fe4000fffe13f */
/*00e0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fe20003f06070 */
/*00f0*/ BSSY B0, 0xb90 ; /* 0x00000a9000007945 */
/* 0x000fd80003800000 */
/*0100*/ @P0 BRA 0xb80 ; /* 0x00000a7000000947 */
/* 0x003fea0003800000 */
/*0110*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff037624 */
/* 0x000fca00078e00ff */
/*0120*/ ISETP.GT.AND P0, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fda0003f04270 */
/*0130*/ @P0 BRA 0x1e0 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0140*/ MOV R3, R0 ; /* 0x0000000000037202 */
/* 0x000fe20000000f00 */
/*0150*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0160*/ MOV R6, c[0x0][0x4] ; /* 0x0000010000067a02 */
/* 0x000fc60000000f00 */
/*0170*/ IMAD R4, R3, c[0x0][0x168], R2 ; /* 0x00005a0003047a24 */
/* 0x000fe400078e0202 */
/*0180*/ IMAD R3, R6, c[0x0][0x10], R3 ; /* 0x0000040006037a24 */
/* 0x000fe400078e0203 */
/*0190*/ IMAD.WIDE.U32 R4, R4, R7, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc600078e0007 */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x16c], PT ; /* 0x00005b0003007a0c */
/* 0x000fe40003f06070 */
/*01b0*/ STG.E.U8 [R4.64+0x3], RZ ; /* 0x000003ff04007986 */
/* 0x0001f6000c101106 */
/*01c0*/ @!P0 BRA 0x170 ; /* 0xffffffa000008947 */
/* 0x001fea000383ffff */
/*01d0*/ BRA 0xb80 ; /* 0x000009a000007947 */
/* 0x000fea0003800000 */
/*01e0*/ IMAD.MOV.U32 R3, RZ, RZ, R0 ; /* 0x000000ffff037224 */
/* 0x000fc600078e0000 */
/*01f0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x001fe200000001ff */
/*0200*/ IMAD R6, R3, c[0x0][0x168], R2 ; /* 0x00005a0003067a24 */
/* 0x000fd200078e0202 */
/*0210*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fca00078e0007 */
/*0220*/ LDG.E R18, [R6.64] ; /* 0x0000000606127981 */
/* 0x000ea2000c1e1900 */
/*0230*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fc6000bf05270 */
/*0240*/ STG.E.U8 [R6.64+0x3], RZ ; /* 0x000003ff06007986 */
/* 0x0001e2000c101106 */
/*0250*/ I2F.F64.U8 R4, R18 ; /* 0x0000001200047312 */
/* 0x006e700000001800 */
/*0260*/ I2F.F64.U8 R8, R18.B1 ; /* 0x1000001200087312 */
/* 0x000eb00000001800 */
/*0270*/ I2F.F64.U8 R12, R18.B2 ; /* 0x20000012000c7312 */
/* 0x000ee20000001800 */
/*0280*/ DADD R10, R4, -c[0x3][0x0] ; /* 0x80c00000040a7629 */
/* 0x002e4c0000000000 */
/*0290*/ DFMA R14, R10, c[0x3][0x4b0], RZ ; /* 0x00c12c000a0e7a2b */
/* 0x002fc800000000ff */
/*02a0*/ DADD R4, R8, -c[0x3][0x8] ; /* 0x80c0020008047629 */
/* 0x004e480000000000 */
/*02b0*/ DFMA R16, R10, c[0x3][0x4c0], RZ ; /* 0x00c130000a107a2b */
/* 0x000fc800000000ff */
/*02c0*/ DADD R8, R12, -c[0x3][0x10] ; /* 0x80c004000c087629 */
/* 0x008fc80000000000 */
/*02d0*/ DFMA R14, R4, c[0x3][0x4c8], R14 ; /* 0x00c13200040e7a2b */
/* 0x002e48000000000e */
/*02e0*/ DFMA R12, R10, c[0x3][0x4b8], RZ ; /* 0x00c12e000a0c7a2b */
/* 0x000e8800000000ff */
/*02f0*/ DFMA R14, R8, c[0x3][0x4e0], R14 ; /* 0x00c13800080e7a2b */
/* 0x002e48000000000e */
/*0300*/ DFMA R12, R4, c[0x3][0x4d0], R12 ; /* 0x00c13400040c7a2b */
/* 0x004e88000000000c */
/*0310*/ DFMA R14, -R10, R14, RZ ; /* 0x0000000e0a0e722b */
/* 0x0023e400000001ff */
/*0320*/ MOV R11, c[0x0][0x170] ; /* 0x00005c00000b7a02 */
/* 0x002fe20000000f00 */
/*0330*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x4] ; /* 0x00000100ff0a7624 */
/* 0x000fe200078e00ff */
/*0340*/ DFMA R12, R8, c[0x3][0x4e8], R12 ; /* 0x00c13a00080c7a2b */
/* 0x004e64000000000c */
/*0350*/ ISETP.NE.AND P2, PT, R11, 0x2, PT ; /* 0x000000020b00780c */
/* 0x000fe20003f45270 */
/*0360*/ IMAD R3, R10, c[0x0][0x10], R3 ; /* 0x000004000a037a24 */
/* 0x000fe200078e0203 */
/*0370*/ DFMA R16, R4, c[0x3][0x4d8], R16 ; /* 0x00c1360004107a2b */
/* 0x000e880000000010 */
/*0380*/ DFMA R12, -R4, R12, R14 ; /* 0x0000000c040c722b */
/* 0x0023e2000000010e */
/*0390*/ ISETP.GE.U32.AND P1, PT, R3, c[0x0][0x16c], PT ; /* 0x00005b0003007a0c */
/* 0x000fe20003f26070 */
/*03a0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x002fe400078e00ff */
/*03b0*/ DFMA R16, R8, c[0x3][0x4f0], R16 ; /* 0x00c13c0008107a2b */
/* 0x004e4c0000000010 */
/*03c0*/ DFMA R8, -R8, R16, R12 ; /* 0x000000100808722b */
/* 0x002062000000010c */
/*03d0*/ @!P2 BRA 0x900 ; /* 0x000005200000a947 */
/* 0x000fea0003800000 */
/*03e0*/ MOV R4, 0x1 ; /* 0x0000000100047802 */
/* 0x000fe20000000f00 */
/*03f0*/ IMAD.U32 R5, RZ, RZ, UR5 ; /* 0x00000005ff057e24 */
/* 0x000fc8000f8e00ff */
/*0400*/ LDG.E R34, [R6.64] ; /* 0x0000000606227981 */
/* 0x000ea2000c1e1900 */
/*0410*/ LOP3.LUT R10, R4, 0xffff, RZ, 0xc0, !PT ; /* 0x0000ffff040a7812 */
/* 0x000fc800078ec0ff */
/*0420*/ PRMT R33, R10, 0x8880, RZ ; /* 0x000088800a217816 */
/* 0x000fe400000000ff */
/*0430*/ MOV R10, 0x48 ; /* 0x00000048000a7802 */
/* 0x000fc60000000f00 */
/*0440*/ IMAD R32, R33.reuse, 0x18, RZ ; /* 0x0000001821207824 */
/* 0x040fe400078e02ff */
/*0450*/ IMAD R33, R33, R10, c[0x2][0x0] ; /* 0x0080000021217624 */
/* 0x000fe400078e020a */
/*0460*/ LDC.64 R28, c[0x3][R32] ; /* 0x00c00000201c7b82 */
/* 0x000ef00000000a00 */
/*0470*/ LDC.64 R30, c[0x3][R33] ; /* 0x00c00000211e7b82 */
/* 0x000f300000000a00 */
/*0480*/ LDC.64 R20, c[0x3][R32+0x8] ; /* 0x00c0020020147b82 */
/* 0x000f700000000a00 */
/*0490*/ LDC.64 R26, c[0x3][R33+0x18] ; /* 0x00c00600211a7b82 */
/* 0x001e300000000a00 */
/*04a0*/ LDC.64 R24, c[0x3][R33+0x8] ; /* 0x00c0020021187b82 */
/* 0x000e700000000a00 */
/*04b0*/ LDC.64 R16, c[0x3][R32+0x10] ; /* 0x00c0040020107b82 */
/* 0x001e300000000a00 */
/*04c0*/ LDC.64 R18, c[0x3][R33+0x30] ; /* 0x00c00c0021127b82 */
/* 0x000e300000000a00 */
/*04d0*/ LDC.64 R22, c[0x3][R33+0x20] ; /* 0x00c0080021167b82 */
/* 0x000e220000000a00 */
/*04e0*/ I2F.F64.U8 R10, R34 ; /* 0x00000022000a7312 */
/* 0x004ef00000001800 */
/*04f0*/ I2F.F64.U8 R12, R34.B1 ; /* 0x10000022000c7312 */
/* 0x000f620000001800 */
/*0500*/ DADD R28, R10, -R28 ; /* 0x000000000a1c7229 */
/* 0x008f0e000000081c */
/*0510*/ I2F.F64.U8 R14, R34.B2 ; /* 0x20000022000e7312 */
/* 0x000e220000001800 */
/*0520*/ DFMA R30, R28, R30, RZ ; /* 0x0000001e1c1e722b */
/* 0x010fc800000000ff */
/*0530*/ DADD R20, R12, -R20 ; /* 0x000000000c147229 */
/* 0x020e880000000814 */
/*0540*/ DFMA R24, R28, R24, RZ ; /* 0x000000181c18722b */
/* 0x002e4800000000ff */
/*0550*/ DFMA R26, R20, R26, R30 ; /* 0x0000001a141a722b */
/* 0x0045e4000000001e */
/*0560*/ LDC.64 R30, c[0x3][R33+0x10] ; /* 0x00c00400211e7b82 */
/* 0x004ea40000000a00 */
/*0570*/ DADD R16, R14, -R16 ; /* 0x000000000e107229 */
/* 0x001e080000000810 */
/*0580*/ DFMA R22, R20, R22, R24 ; /* 0x000000161416722b */
/* 0x0023e40000000018 */
/*0590*/ LDC.64 R24, c[0x3][R33+0x38] ; /* 0x00c00e0021187b82 */
/* 0x002e640000000a00 */
/*05a0*/ DFMA R18, R16, R18, R26 ; /* 0x000000121012722b */
/* 0x0010cc000000001a */
/*05b0*/ LDC.64 R26, c[0x3][R33+0x28] ; /* 0x00c00a00211a7b82 */
/* 0x001e220000000a00 */
/*05c0*/ DFMA R18, -R28, R18, RZ ; /* 0x000000121c12722b */
/* 0x008fc800000001ff */
/*05d0*/ DFMA R30, R28, R30, RZ ; /* 0x0000001e1c1e722b */
/* 0x0045c600000000ff */
/*05e0*/ LDC.64 R28, c[0x3][R33+0x40] ; /* 0x00c01000211c7b82 */
/* 0x004ea20000000a00 */
/*05f0*/ DFMA R22, R16, R24, R22 ; /* 0x000000181016722b */
/* 0x002e4c0000000016 */
/*0600*/ DFMA R18, -R20, R22, R18 ; /* 0x000000161412722b */
/* 0x002fc80000000112 */
/*0610*/ DFMA R26, R20, R26, R30 ; /* 0x0000001a141a722b */
/* 0x001e8c000000001e */
/*0620*/ DFMA R26, R16, R28, R26 ; /* 0x0000001c101a722b */
/* 0x004e0c000000001a */
/*0630*/ DFMA R16, -R16, R26, R18 ; /* 0x0000001a1010722b */
/* 0x001e0c0000000112 */
/*0640*/ DSETP.GT.AND P2, PT, R16, R8, PT ; /* 0x000000081000722a */
/* 0x001e1c0003f44000 */
/*0650*/ @P2 STG.E.U8 [R6.64+0x3], R4 ; /* 0x0000030406002986 */
/* 0x0011e8000c101106 */
/*0660*/ @P2 LDG.E R34, [R6.64] ; /* 0x0000000606222981 */
/* 0x000ea2000c1e1900 */
/*0670*/ LDC.64 R28, c[0x3][R32+0x18] ; /* 0x00c00600201c7b82 */
/* 0x000e620000000a00 */
/*0680*/ @P2 IMAD.MOV.U32 R8, RZ, RZ, R16 ; /* 0x000000ffff082224 */
/* 0x000fe200078e0010 */
/*0690*/ @P2 MOV R9, R17 ; /* 0x0000001100092202 */
/* 0x000fe40000000f00 */
/*06a0*/ IADD3 R5, R5, -0x2, RZ ; /* 0xfffffffe05057810 */
/* 0x000fc80007ffe0ff */
/*06b0*/ LDC.64 R24, c[0x3][R32+0x28] ; /* 0x00c00a0020187b82 */
/* 0x000ee20000000a00 */
/*06c0*/ ISETP.NE.AND P3, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fce0003f65270 */
/*06d0*/ LDC.64 R26, c[0x3][R32+0x20] ; /* 0x00c00800201a7b82 */
/* 0x000f300000000a00 */
/*06e0*/ LDC.64 R22, c[0x3][R33+0x48] ; /* 0x00c0120021167b82 */
/* 0x000f700000000a00 */
/*06f0*/ LDC.64 R18, c[0x3][R33+0x60] ; /* 0x00c0180021127b82 */
/* 0x000e300000000a00 */
/*0700*/ LDC.64 R20, c[0x3][R33+0x78] ; /* 0x00c01e0021147b82 */
/* 0x000e220000000a00 */
/*0710*/ @P2 I2F.F64.U8 R10, R34 ; /* 0x00000022000a2312 */
/* 0x004e700000001800 */
/*0720*/ @P2 I2F.F64.U8 R14, R34.B2 ; /* 0x20000022000e2312 */
/* 0x000ef00000001800 */
/*0730*/ @P2 I2F.F64.U8 R12, R34.B1 ; /* 0x10000022000c2312 */
/* 0x000f220000001800 */
/*0740*/ DADD R10, -R28, R10 ; /* 0x000000001c0a7229 */
/* 0x002344000000010a */
/*0750*/ LDC.64 R28, c[0x3][R33+0x80] ; /* 0x00c02000211c7b82 */
/* 0x002e680000000a00 */
/*0760*/ DFMA R30, R10, R22, RZ ; /* 0x000000160a1e722b */
/* 0x0205c800000000ff */
/*0770*/ DADD R14, -R24, R14 ; /* 0x00000000180e7229 */
/* 0x0087e2000000010e */
/*0780*/ LDC.64 R22, c[0x3][R33+0x58] ; /* 0x00c0160021167b82 */
/* 0x004ea60000000a00 */
/*0790*/ DADD R12, -R26, R12 ; /* 0x000000001a0c7229 */
/* 0x010e0a000000010c */
/*07a0*/ LDC.64 R24, c[0x3][R33+0x50] ; /* 0x00c0140021187b82 */
/* 0x008ee20000000a00 */
/*07b0*/ DFMA R30, R12, R18, R30 ; /* 0x000000120c1e722b */
/* 0x001e0e000000001e */
/*07c0*/ LDC.64 R26, c[0x3][R33+0x68] ; /* 0x00c01a00211a7b82 */
/* 0x000f220000000a00 */
/*07d0*/ DFMA R20, R14, R20, R30 ; /* 0x000000140e14722b */
/* 0x001e0c000000001e */
/*07e0*/ DFMA R20, -R10.reuse, R20, RZ ; /* 0x000000140a14722b */
/* 0x041fe200000001ff */
/*07f0*/ LDC.64 R18, c[0x3][R33+0x70] ; /* 0x00c01c0021127b82 */
/* 0x000e260000000a00 */
/*0800*/ DFMA R22, R10, R22, RZ ; /* 0x000000160a16722b */
/* 0x004fca00000000ff */
/*0810*/ LDC.64 R30, c[0x3][R33+0x88] ; /* 0x00c02200211e7b82 */
/* 0x000ea20000000a00 */
/*0820*/ DFMA R24, R10, R24, RZ ; /* 0x000000180a18722b */
/* 0x008f0c00000000ff */
/*0830*/ DFMA R24, R12, R26, R24 ; /* 0x0000001a0c18722b */
/* 0x010e4c0000000018 */
/*0840*/ DFMA R24, R14, R28, R24 ; /* 0x0000001c0e18722b */
/* 0x002e480000000018 */
/*0850*/ DFMA R18, R12, R18, R22 ; /* 0x000000120c12722b */
/* 0x001e880000000016 */
/*0860*/ DFMA R20, -R12, R24, R20 ; /* 0x000000180c14722b */
/* 0x002fc80000000114 */
/*0870*/ DFMA R18, R14, R30, R18 ; /* 0x0000001e0e12722b */
/* 0x004e0c0000000012 */
/*0880*/ DFMA R18, -R14, R18, R20 ; /* 0x000000120e12722b */
/* 0x001e0c0000000114 */
/*0890*/ DSETP.GT.AND P2, PT, R18, R8, PT ; /* 0x000000081200722a */
/* 0x001e1c0003f44000 */
/*08a0*/ @P2 IADD3 R11, R4.reuse, 0x1, RZ ; /* 0x00000001040b2810 */
/* 0x041fe20007ffe0ff */
/*08b0*/ @P2 IMAD.MOV.U32 R8, RZ, RZ, R18 ; /* 0x000000ffff082224 */
/* 0x000fe200078e0012 */
/*08c0*/ IADD3 R4, R4, 0x2, RZ ; /* 0x0000000204047810 */
/* 0x000fe40007ffe0ff */
/*08d0*/ @P2 MOV R9, R19 ; /* 0x0000001300092202 */
/* 0x000fe20000000f00 */
/*08e0*/ @P2 STG.E.U8 [R6.64+0x3], R11 ; /* 0x0000030b06002986 */
/* 0x0001e2000c101106 */
/*08f0*/ @P3 BRA 0x400 ; /* 0xfffffb0000003947 */
/* 0x000fea000383ffff */
/*0900*/ @!P0 BRA 0xb70 ; /* 0x0000026000008947 */
/* 0x000fea0003800000 */
/*0910*/ LDG.E R35, [R6.64] ; /* 0x0000000606237981 */
/* 0x000ea2000c1e1900 */
/*0920*/ LOP3.LUT R5, R4, 0xffff, RZ, 0xc0, !PT ; /* 0x0000ffff04057812 */
/* 0x000fe200078ec0ff */
/*0930*/ IMAD.MOV.U32 R14, RZ, RZ, 0x48 ; /* 0x00000048ff0e7424 */
/* 0x000fc600078e00ff */
/*0940*/ PRMT R5, R5, 0x8880, RZ ; /* 0x0000888005057816 */
/* 0x000fca00000000ff */
/*0950*/ IMAD R34, R5.reuse, 0x18, RZ ; /* 0x0000001805227824 */
/* 0x040fe400078e02ff */
/*0960*/ IMAD R5, R5, R14, c[0x2][0x0] ; /* 0x0080000005057624 */
/* 0x000fe400078e020e */
/*0970*/ LDC.64 R10, c[0x3][R34] ; /* 0x00c00000220a7b82 */
/* 0x001e300000000a00 */
/*0980*/ LDC.64 R12, c[0x3][R34+0x8] ; /* 0x00c00200220c7b82 */
/* 0x000ef00000000a00 */
/*0990*/ LDC.64 R32, c[0x3][R5] ; /* 0x00c0000005207b82 */
/* 0x000f300000000a00 */
/*09a0*/ LDC.64 R30, c[0x3][R5+0x18] ; /* 0x00c00600051e7b82 */
/* 0x000f700000000a00 */
/*09b0*/ LDC.64 R16, c[0x3][R34+0x10] ; /* 0x00c0040022107b82 */
/* 0x000e700000000a00 */
/*09c0*/ LDC.64 R26, c[0x3][R5+0x30] ; /* 0x00c00c00051a7b82 */
/* 0x000e300000000a00 */
/*09d0*/ LDC.64 R24, c[0x3][R5+0x20] ; /* 0x00c0080005187b82 */
/* 0x000e300000000a00 */
/*09e0*/ LDC.64 R20, c[0x3][R5+0x28] ; /* 0x00c00a0005147b82 */
/* 0x000e300000000a00 */
/*09f0*/ LDC.64 R18, c[0x3][R5+0x38] ; /* 0x00c00e0005127b82 */
/* 0x000e220000000a00 */
/*0a00*/ I2F.F64.U8 R22, R35 ; /* 0x0000002300167312 */
/* 0x004e300000001800 */
/*0a10*/ I2F.F64.U8 R14, R35.B1 ; /* 0x10000023000e7312 */
/* 0x000ee20000001800 */
/*0a20*/ DADD R22, R22, -R10 ; /* 0x0000000016167229 */
/* 0x00110e000000080a */
/*0a30*/ I2F.F64.U8 R28, R35.B2 ; /* 0x20000023001c7312 */
/* 0x000e620000001800 */
/*0a40*/ LDC.64 R10, c[0x3][R5+0x8] ; /* 0x00c00200050a7b82 */
/* 0x001e220000000a00 */
/*0a50*/ DFMA R32, R22, R32, RZ ; /* 0x000000201620722b */
/* 0x010fc800000000ff */
/*0a60*/ DADD R12, R14, -R12 ; /* 0x000000000e0c7229 */
/* 0x008546000000080c */
/*0a70*/ LDC.64 R14, c[0x3][R5+0x10] ; /* 0x00c00400050e7b82 */
/* 0x004ea60000000a00 */
/*0a80*/ DFMA R30, R12, R30, R32 ; /* 0x0000001e0c1e722b */
/* 0x0207ca0000000020 */
/*0a90*/ LDC.64 R32, c[0x3][R5+0x40] ; /* 0x00c0100005207b82 */
/* 0x008ee20000000a00 */
/*0aa0*/ DADD R16, R28, -R16 ; /* 0x000000001c107229 */
/* 0x002e480000000810 */
/*0ab0*/ DFMA R10, R22, R10, RZ ; /* 0x0000000a160a722b */
/* 0x001e0800000000ff */
/*0ac0*/ DFMA R26, R16, R26, R30 ; /* 0x0000001a101a722b */
/* 0x002e48000000001e */
/*0ad0*/ DFMA R10, R12, R24, R10 ; /* 0x000000180c0a722b */
/* 0x001fc8000000000a */
/*0ae0*/ DFMA R14, R22, R14, RZ ; /* 0x0000000e160e722b */
/* 0x004e0800000000ff */
/*0af0*/ DFMA R26, -R22, R26, RZ ; /* 0x0000001a161a722b */
/* 0x002fc800000001ff */
/*0b00*/ DFMA R14, R12, R20, R14 ; /* 0x000000140c0e722b */
/* 0x001ec8000000000e */
/*0b10*/ DFMA R10, R16, R18, R10 ; /* 0x00000012100a722b */
/* 0x000e08000000000a */
/*0b20*/ DFMA R14, R16, R32, R14 ; /* 0x00000020100e722b */
/* 0x008fc8000000000e */
/*0b30*/ DFMA R10, -R12, R10, R26 ; /* 0x0000000a0c0a722b */
/* 0x001e0c000000011a */
/*0b40*/ DFMA R10, -R16, R14, R10 ; /* 0x0000000e100a722b */
/* 0x001e0c000000010a */
/*0b50*/ DSETP.GT.AND P0, PT, R10, R8, PT ; /* 0x000000080a00722a */
/* 0x001e1c0003f04000 */
/*0b60*/ @P0 STG.E.U8 [R6.64+0x3], R4 ; /* 0x0000030406000986 */
/* 0x0011e4000c101106 */
/*0b70*/ @!P1 BRA 0x1f0 ; /* 0xfffff67000009947 */
/* 0x000fea000383ffff */
/*0b80*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0b90*/ MOV R3, c[0x0][0x0] ; /* 0x0000000000037a02 */
/* 0x000fca0000000f00 */
/*0ba0*/ IMAD R2, R3, c[0x0][0xc], R2 ; /* 0x0000030003027a24 */
/* 0x000fca00078e0202 */
/*0bb0*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06070 */
/*0bc0*/ @!P0 BRA 0xe0 ; /* 0xfffff51000008947 */
/* 0x000fea000383ffff */
/*0bd0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0be0*/ BRA 0xbe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cstdio>
#include <string>
#include <cassert>
#include <iostream>
#include <cstddef>
#include <vector>
#define uint8_t unsigned char
#define uint16_t unsigned short
#define uint32_t unsigned int
#define uint64_t unsigned long long
using namespace std;
//
// DEFAULt functions for work with cuda
//
#define CSC(call) do { \
cudaError_t res = call; \
if (res != cudaSuccess) { \
fprintf(stderr, "CUDA Error in %s:%d: %s\n", __FILE__, __LINE__, cudaGetErrorString(res)); \
exit(0); \
} \
} while (0)
cudaEvent_t start, stop;
float t;
void time_start() {
CSC(cudaEventCreate(&start));
CSC(cudaEventCreate(&stop));
CSC(cudaEventRecord(start, 0));
}
void time_end() {
CSC(cudaGetLastError());
CSC(cudaEventRecord(stop, 0));
CSC(cudaEventSynchronize(stop));
CSC(cudaEventElapsedTime(&t, start, stop));
printf("time = %f\n", t);
CSC(cudaEventDestroy(start));
CSC(cudaEventDestroy(stop));
}
double minor3x3(double m[3][3], int i, int j) {
double arr[4];
int len = 0;
for (int row = 0; row < 3; row++) {
for (int col = 0; col < 3; col++) {
if (col == j || row == i) continue;
arr[len++] = m[row][col];
}
}
return arr[0] * arr[3] - arr[1] * arr[2];
}
double cof3x3(double m[3][3], int i, int j) {
double mr = minor3x3(m, i, j);
if ((i+j) % 2 == 1)
mr *= -1;
return mr;
}
double det3x3(double m[3][3]) {
double res = 0;
for (int col = 0; col < 3; col++) {
res += m[0][col] * cof3x3(m, 0, col);
}
return res;
}
class IMG {
public:
uint32_t w;
uint32_t h;
uint64_t size;
uchar4 *data;
IMG() : w(0), h(0), size(0), data(NULL) {}
IMG(string path) {
FILE *fin = fopen(path.c_str(), "rb");
if (!fin) {
cout << "Wrong file name " << path << "!\n";
return;
}
fread(&w, sizeof(uint32_t), 1, fin);
fread(&h, sizeof(uint32_t), 1, fin);
size = w * h;
data = new uchar4[size];
fread(data, sizeof(uchar4), size, fin);
fclose(fin);
}
~IMG() {
if (data != NULL) {
delete[] data;
}
}
void toFile(string path) {
FILE *fout = fopen(path.c_str(), "wb");
if (!fout) {
cout << "Wrong file name " << path << "!\n";
return;
}
fwrite(&w, sizeof(uint32_t), 1, fout);
fwrite(&h, sizeof(uint32_t), 1, fout);
fwrite(data, sizeof(uchar4), size, fout);
fclose(fout);
}
};
//
// main programm
//
#define pixel uchar4
#define p(x, y) data[y*w + x]
vector<vector<pixel> > cls;
__constant__ double GPU_AVG[50][3];
__constant__ double GPU_INVERT_COV[50][3][3];
__device__ double mahalanobis(const pixel p, int ci) {
double v[3] = {p.x - GPU_AVG[ci][0],
p.y - GPU_AVG[ci][1],
p.z - GPU_AVG[ci][2]
};
double tmp[3] = {0, 0, 0}, res = 0;
for (int i = 0; i < 3; ++i) {
for (int j = 0; j < 3; ++j) {
tmp[i] += v[j] * GPU_INVERT_COV[ci][j][i];
}
res -= tmp[i] * v[i];
}
return res;
}
__device__ void classify(pixel &p, int cnum) {
double mx = mahalanobis(p, 0);
p.w = 0;
for (char ci = 1; ci < cnum; ++ci) {
double tmp = mahalanobis(p, ci);
if (tmp > mx) {
mx = tmp;
p.w = ci;
}
}
}
__global__ void kernel(uchar4 *data, uint32_t w, uint32_t h, int cnum) {
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int idy = blockDim.y * blockIdx.y + threadIdx.y;
int offsetx = blockDim.x * gridDim.x;
int offsety = blockDim.y * gridDim.y;
for (int x = idx; x < w; x += offsetx) {
for (int y = idy; y < h; y += offsety) {
classify(p(x, y), cnum);
}
}
}
int main() {
int cnum = 0;
string in, out;
cin >> in >> out >> cnum;
cls.resize(cnum, vector<pixel>());
double cavg[cnum][3];
double ccov[cnum][3][3];
memset(cavg, 0, sizeof(double) * cnum * 3);
memset(ccov, 0, sizeof(double) * cnum * 9);
IMG img(in);
uint32_t w = img.w;
for (int i = 0; i < cnum; ++i) {
int csize, x, y;
cin >> csize;
for (int j = 0; j < csize; ++j) {
cin >> x >> y;
pixel p = img.p(x, y);
cls[i].push_back(p);
cavg[i][0] += p.x;
cavg[i][1] += p.y;
cavg[i][2] += p.z;
}
for (int j = 0; j < 3; ++j) cavg[i][j] /= csize;
}
for (int c = 0; c < cnum; ++c) {
int csize = cls[c].size();
for (int i = 0; i < csize; ++i) {
pixel p = cls[c][i];
double coeff[3] = {p.x - cavg[c][0],
p.y - cavg[c][1],
p.z - cavg[c][2]
};
for (int r = 0; r < 3; ++r) {
for (int s = 0; s < 3; ++s) {
ccov[c][r][s] += coeff[r] * coeff[s];
}
}
}
for (int r = 0; r < 3; ++r) {
for (int s = 0; s < 3; ++s) {
ccov[c][r][s] /= csize - 1;
}
}
double det = det3x3(ccov[c]);
double icov[3][3];
for (int r = 0; r < 3; ++r) {
for (int s = 0; s < 3; ++s) {
if (det == 0) {
icov[s][r] = (r == s ? 1 : 0);
} else {
icov[s][r] = cof3x3(ccov[c], r, s) / det;
}
}
}
for (int r = 0; r < 3; ++r) {
for (int s = 0; s < 3; ++s) {
ccov[c][r][s] = icov[r][s];
}
}
}
uchar4 *result;
CSC(cudaMemcpyToSymbol(GPU_AVG, cavg, sizeof(double) * cnum * 3));
CSC(cudaMemcpyToSymbol(GPU_INVERT_COV, ccov, sizeof(double) * cnum * 9));
CSC(cudaMalloc(&result, sizeof(uchar4) * img.size));
CSC(cudaMemcpy(result, img.data, sizeof(uchar4) * img.size, cudaMemcpyHostToDevice));
kernel<<<dim3(16, 16), dim3(16, 16)>>>(result, img.w, img.h, cnum);
CSC(cudaMemcpy(img.data, result, sizeof(uchar4) * img.size, cudaMemcpyDeviceToHost));
CSC(cudaFree(result));
img.toFile(out);
} | #include <hip/hip_runtime.h>
#include <cstdio>
#include <string>
#include <cassert>
#include <iostream>
#include <cstddef>
#include <vector>
#define uint8_t unsigned char
#define uint16_t unsigned short
#define uint32_t unsigned int
#define uint64_t unsigned long long
using namespace std;
//
// DEFAULt functions for work with cuda
//
#define CSC(call) do { \
hipError_t res = call; \
if (res != hipSuccess) { \
fprintf(stderr, "CUDA Error in %s:%d: %s\n", __FILE__, __LINE__, hipGetErrorString(res)); \
exit(0); \
} \
} while (0)
hipEvent_t start, stop;
float t;
void time_start() {
CSC(hipEventCreate(&start));
CSC(hipEventCreate(&stop));
CSC(hipEventRecord(start, 0));
}
void time_end() {
CSC(hipGetLastError());
CSC(hipEventRecord(stop, 0));
CSC(hipEventSynchronize(stop));
CSC(hipEventElapsedTime(&t, start, stop));
printf("time = %f\n", t);
CSC(hipEventDestroy(start));
CSC(hipEventDestroy(stop));
}
double minor3x3(double m[3][3], int i, int j) {
double arr[4];
int len = 0;
for (int row = 0; row < 3; row++) {
for (int col = 0; col < 3; col++) {
if (col == j || row == i) continue;
arr[len++] = m[row][col];
}
}
return arr[0] * arr[3] - arr[1] * arr[2];
}
double cof3x3(double m[3][3], int i, int j) {
double mr = minor3x3(m, i, j);
if ((i+j) % 2 == 1)
mr *= -1;
return mr;
}
double det3x3(double m[3][3]) {
double res = 0;
for (int col = 0; col < 3; col++) {
res += m[0][col] * cof3x3(m, 0, col);
}
return res;
}
class IMG {
public:
uint32_t w;
uint32_t h;
uint64_t size;
uchar4 *data;
IMG() : w(0), h(0), size(0), data(NULL) {}
IMG(string path) {
FILE *fin = fopen(path.c_str(), "rb");
if (!fin) {
cout << "Wrong file name " << path << "!\n";
return;
}
fread(&w, sizeof(uint32_t), 1, fin);
fread(&h, sizeof(uint32_t), 1, fin);
size = w * h;
data = new uchar4[size];
fread(data, sizeof(uchar4), size, fin);
fclose(fin);
}
~IMG() {
if (data != NULL) {
delete[] data;
}
}
void toFile(string path) {
FILE *fout = fopen(path.c_str(), "wb");
if (!fout) {
cout << "Wrong file name " << path << "!\n";
return;
}
fwrite(&w, sizeof(uint32_t), 1, fout);
fwrite(&h, sizeof(uint32_t), 1, fout);
fwrite(data, sizeof(uchar4), size, fout);
fclose(fout);
}
};
//
// main programm
//
#define pixel uchar4
#define p(x, y) data[y*w + x]
vector<vector<pixel> > cls;
__constant__ double GPU_AVG[50][3];
__constant__ double GPU_INVERT_COV[50][3][3];
__device__ double mahalanobis(const pixel p, int ci) {
double v[3] = {p.x - GPU_AVG[ci][0],
p.y - GPU_AVG[ci][1],
p.z - GPU_AVG[ci][2]
};
double tmp[3] = {0, 0, 0}, res = 0;
for (int i = 0; i < 3; ++i) {
for (int j = 0; j < 3; ++j) {
tmp[i] += v[j] * GPU_INVERT_COV[ci][j][i];
}
res -= tmp[i] * v[i];
}
return res;
}
__device__ void classify(pixel &p, int cnum) {
double mx = mahalanobis(p, 0);
p.w = 0;
for (char ci = 1; ci < cnum; ++ci) {
double tmp = mahalanobis(p, ci);
if (tmp > mx) {
mx = tmp;
p.w = ci;
}
}
}
__global__ void kernel(uchar4 *data, uint32_t w, uint32_t h, int cnum) {
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int idy = blockDim.y * blockIdx.y + threadIdx.y;
int offsetx = blockDim.x * gridDim.x;
int offsety = blockDim.y * gridDim.y;
for (int x = idx; x < w; x += offsetx) {
for (int y = idy; y < h; y += offsety) {
classify(p(x, y), cnum);
}
}
}
int main() {
int cnum = 0;
string in, out;
cin >> in >> out >> cnum;
cls.resize(cnum, vector<pixel>());
double cavg[cnum][3];
double ccov[cnum][3][3];
memset(cavg, 0, sizeof(double) * cnum * 3);
memset(ccov, 0, sizeof(double) * cnum * 9);
IMG img(in);
uint32_t w = img.w;
for (int i = 0; i < cnum; ++i) {
int csize, x, y;
cin >> csize;
for (int j = 0; j < csize; ++j) {
cin >> x >> y;
pixel p = img.p(x, y);
cls[i].push_back(p);
cavg[i][0] += p.x;
cavg[i][1] += p.y;
cavg[i][2] += p.z;
}
for (int j = 0; j < 3; ++j) cavg[i][j] /= csize;
}
for (int c = 0; c < cnum; ++c) {
int csize = cls[c].size();
for (int i = 0; i < csize; ++i) {
pixel p = cls[c][i];
double coeff[3] = {p.x - cavg[c][0],
p.y - cavg[c][1],
p.z - cavg[c][2]
};
for (int r = 0; r < 3; ++r) {
for (int s = 0; s < 3; ++s) {
ccov[c][r][s] += coeff[r] * coeff[s];
}
}
}
for (int r = 0; r < 3; ++r) {
for (int s = 0; s < 3; ++s) {
ccov[c][r][s] /= csize - 1;
}
}
double det = det3x3(ccov[c]);
double icov[3][3];
for (int r = 0; r < 3; ++r) {
for (int s = 0; s < 3; ++s) {
if (det == 0) {
icov[s][r] = (r == s ? 1 : 0);
} else {
icov[s][r] = cof3x3(ccov[c], r, s) / det;
}
}
}
for (int r = 0; r < 3; ++r) {
for (int s = 0; s < 3; ++s) {
ccov[c][r][s] = icov[r][s];
}
}
}
uchar4 *result;
CSC(hipMemcpyToSymbol(HIP_SYMBOL(GPU_AVG), cavg, sizeof(double) * cnum * 3));
CSC(hipMemcpyToSymbol(HIP_SYMBOL(GPU_INVERT_COV), ccov, sizeof(double) * cnum * 9));
CSC(hipMalloc(&result, sizeof(uchar4) * img.size));
CSC(hipMemcpy(result, img.data, sizeof(uchar4) * img.size, hipMemcpyHostToDevice));
kernel<<<dim3(16, 16), dim3(16, 16)>>>(result, img.w, img.h, cnum);
CSC(hipMemcpy(img.data, result, sizeof(uchar4) * img.size, hipMemcpyDeviceToHost));
CSC(hipFree(result));
img.toFile(out);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
#include <string>
#include <cassert>
#include <iostream>
#include <cstddef>
#include <vector>
#define uint8_t unsigned char
#define uint16_t unsigned short
#define uint32_t unsigned int
#define uint64_t unsigned long long
using namespace std;
//
// DEFAULt functions for work with cuda
//
#define CSC(call) do { \
hipError_t res = call; \
if (res != hipSuccess) { \
fprintf(stderr, "CUDA Error in %s:%d: %s\n", __FILE__, __LINE__, hipGetErrorString(res)); \
exit(0); \
} \
} while (0)
hipEvent_t start, stop;
float t;
void time_start() {
CSC(hipEventCreate(&start));
CSC(hipEventCreate(&stop));
CSC(hipEventRecord(start, 0));
}
void time_end() {
CSC(hipGetLastError());
CSC(hipEventRecord(stop, 0));
CSC(hipEventSynchronize(stop));
CSC(hipEventElapsedTime(&t, start, stop));
printf("time = %f\n", t);
CSC(hipEventDestroy(start));
CSC(hipEventDestroy(stop));
}
double minor3x3(double m[3][3], int i, int j) {
double arr[4];
int len = 0;
for (int row = 0; row < 3; row++) {
for (int col = 0; col < 3; col++) {
if (col == j || row == i) continue;
arr[len++] = m[row][col];
}
}
return arr[0] * arr[3] - arr[1] * arr[2];
}
double cof3x3(double m[3][3], int i, int j) {
double mr = minor3x3(m, i, j);
if ((i+j) % 2 == 1)
mr *= -1;
return mr;
}
double det3x3(double m[3][3]) {
double res = 0;
for (int col = 0; col < 3; col++) {
res += m[0][col] * cof3x3(m, 0, col);
}
return res;
}
class IMG {
public:
uint32_t w;
uint32_t h;
uint64_t size;
uchar4 *data;
IMG() : w(0), h(0), size(0), data(NULL) {}
IMG(string path) {
FILE *fin = fopen(path.c_str(), "rb");
if (!fin) {
cout << "Wrong file name " << path << "!\n";
return;
}
fread(&w, sizeof(uint32_t), 1, fin);
fread(&h, sizeof(uint32_t), 1, fin);
size = w * h;
data = new uchar4[size];
fread(data, sizeof(uchar4), size, fin);
fclose(fin);
}
~IMG() {
if (data != NULL) {
delete[] data;
}
}
void toFile(string path) {
FILE *fout = fopen(path.c_str(), "wb");
if (!fout) {
cout << "Wrong file name " << path << "!\n";
return;
}
fwrite(&w, sizeof(uint32_t), 1, fout);
fwrite(&h, sizeof(uint32_t), 1, fout);
fwrite(data, sizeof(uchar4), size, fout);
fclose(fout);
}
};
//
// main programm
//
#define pixel uchar4
#define p(x, y) data[y*w + x]
vector<vector<pixel> > cls;
__constant__ double GPU_AVG[50][3];
__constant__ double GPU_INVERT_COV[50][3][3];
__device__ double mahalanobis(const pixel p, int ci) {
double v[3] = {p.x - GPU_AVG[ci][0],
p.y - GPU_AVG[ci][1],
p.z - GPU_AVG[ci][2]
};
double tmp[3] = {0, 0, 0}, res = 0;
for (int i = 0; i < 3; ++i) {
for (int j = 0; j < 3; ++j) {
tmp[i] += v[j] * GPU_INVERT_COV[ci][j][i];
}
res -= tmp[i] * v[i];
}
return res;
}
__device__ void classify(pixel &p, int cnum) {
double mx = mahalanobis(p, 0);
p.w = 0;
for (char ci = 1; ci < cnum; ++ci) {
double tmp = mahalanobis(p, ci);
if (tmp > mx) {
mx = tmp;
p.w = ci;
}
}
}
__global__ void kernel(uchar4 *data, uint32_t w, uint32_t h, int cnum) {
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int idy = blockDim.y * blockIdx.y + threadIdx.y;
int offsetx = blockDim.x * gridDim.x;
int offsety = blockDim.y * gridDim.y;
for (int x = idx; x < w; x += offsetx) {
for (int y = idy; y < h; y += offsety) {
classify(p(x, y), cnum);
}
}
}
int main() {
int cnum = 0;
string in, out;
cin >> in >> out >> cnum;
cls.resize(cnum, vector<pixel>());
double cavg[cnum][3];
double ccov[cnum][3][3];
memset(cavg, 0, sizeof(double) * cnum * 3);
memset(ccov, 0, sizeof(double) * cnum * 9);
IMG img(in);
uint32_t w = img.w;
for (int i = 0; i < cnum; ++i) {
int csize, x, y;
cin >> csize;
for (int j = 0; j < csize; ++j) {
cin >> x >> y;
pixel p = img.p(x, y);
cls[i].push_back(p);
cavg[i][0] += p.x;
cavg[i][1] += p.y;
cavg[i][2] += p.z;
}
for (int j = 0; j < 3; ++j) cavg[i][j] /= csize;
}
for (int c = 0; c < cnum; ++c) {
int csize = cls[c].size();
for (int i = 0; i < csize; ++i) {
pixel p = cls[c][i];
double coeff[3] = {p.x - cavg[c][0],
p.y - cavg[c][1],
p.z - cavg[c][2]
};
for (int r = 0; r < 3; ++r) {
for (int s = 0; s < 3; ++s) {
ccov[c][r][s] += coeff[r] * coeff[s];
}
}
}
for (int r = 0; r < 3; ++r) {
for (int s = 0; s < 3; ++s) {
ccov[c][r][s] /= csize - 1;
}
}
double det = det3x3(ccov[c]);
double icov[3][3];
for (int r = 0; r < 3; ++r) {
for (int s = 0; s < 3; ++s) {
if (det == 0) {
icov[s][r] = (r == s ? 1 : 0);
} else {
icov[s][r] = cof3x3(ccov[c], r, s) / det;
}
}
}
for (int r = 0; r < 3; ++r) {
for (int s = 0; s < 3; ++s) {
ccov[c][r][s] = icov[r][s];
}
}
}
uchar4 *result;
CSC(hipMemcpyToSymbol(HIP_SYMBOL(GPU_AVG), cavg, sizeof(double) * cnum * 3));
CSC(hipMemcpyToSymbol(HIP_SYMBOL(GPU_INVERT_COV), ccov, sizeof(double) * cnum * 9));
CSC(hipMalloc(&result, sizeof(uchar4) * img.size));
CSC(hipMemcpy(result, img.data, sizeof(uchar4) * img.size, hipMemcpyHostToDevice));
kernel<<<dim3(16, 16), dim3(16, 16)>>>(result, img.w, img.h, cnum);
CSC(hipMemcpy(img.data, result, sizeof(uchar4) * img.size, hipMemcpyDeviceToHost));
CSC(hipFree(result));
img.toFile(out);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelP15HIP_vector_typeIhLj4EEjji
.globl _Z6kernelP15HIP_vector_typeIhLj4EEjji
.p2align 8
.type _Z6kernelP15HIP_vector_typeIhLj4EEjji,@function
_Z6kernelP15HIP_vector_typeIhLj4EEjji:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s26, s[0:1], 0x8
v_and_b32_e32 v1, 0x3ff, v0
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[6:7], null, s14, s4, v[1:2]
v_cmpx_gt_u32_e64 s26, v6
s_cbranch_execz .LBB0_19
s_load_b32 s5, s[2:3], 0xc
s_load_b64 s[16:17], s[0:1], 0xc
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, GPU_AVG@rel32@lo+4
s_addc_u32 s7, s7, GPU_AVG@rel32@hi+12
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, GPU_AVG@rel32@lo+12
s_addc_u32 s9, s9, GPU_AVG@rel32@hi+20
s_getpc_b64 s[10:11]
s_add_u32 s10, s10, GPU_AVG@rel32@lo+20
s_addc_u32 s11, s11, GPU_AVG@rel32@hi+28
s_load_b64 s[12:13], s[2:3], 0x0
s_load_b64 s[18:19], s[0:1], 0x0
s_clause 0x2
s_load_b64 s[20:21], s[6:7], 0x0
s_load_b64 s[22:23], s[8:9], 0x0
s_load_b64 s[24:25], s[10:11], 0x0
v_bfe_u32 v0, v0, 10, 10
v_mov_b32_e32 v22, 0
s_mov_b32 s27, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s1, s5, 16
s_cmp_gt_i32 s17, 1
v_mad_u64_u32 v[7:8], null, s15, s1, v[0:1]
s_cselect_b32 s3, -1, 0
s_mul_i32 s14, s12, s4
s_mul_i32 s15, s13, s1
s_mov_b32 s4, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u32_e64 s0, s16, v7
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s28
v_add_nc_u32_e32 v6, s14, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_u32_e32 vcc_lo, s26, v6
s_or_b32 s27, vcc_lo, s27
s_and_not1_b32 exec_lo, exec_lo, s27
s_cbranch_execz .LBB0_19
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s28, s0
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v23, v7
s_mov_b32 s29, 0
s_branch .LBB0_6
.LBB0_5:
v_add_nc_u32_e32 v23, s15, v23
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_u32_e32 vcc_lo, s16, v23
s_or_b32 s29, vcc_lo, s29
s_and_not1_b32 exec_lo, exec_lo, s29
s_cbranch_execz .LBB0_2
.LBB0_6:
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v23, s26, v[6:7]
v_dual_mov_b32 v1, v22 :: v_dual_mov_b32 v10, 0
s_mov_b32 s5, s4
s_mov_b32 s6, s4
s_mov_b32 s7, s4
s_mov_b32 s8, s4
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_mov_b32 s9, s4
v_mov_b32_e32 v11, 0
s_getpc_b64 s[10:11]
s_add_u32 s10, s10, GPU_INVERT_COV@rel32@lo+4
s_addc_u32 s11, s11, GPU_INVERT_COV@rel32@hi+12
v_add_co_u32 v8, vcc_lo, s18, v0
v_add_co_ci_u32_e32 v9, vcc_lo, s19, v1, vcc_lo
global_load_b32 v0, v[8:9], off
s_waitcnt vmcnt(0)
v_and_b32_e32 v1, 0xff, v0
v_bfe_u32 v2, v0, 8, 8
v_bfe_u32 v4, v0, 16, 8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f64_i32_e32 v[0:1], v1
v_cvt_f64_i32_e32 v[2:3], v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f64_i32_e32 v[4:5], v4
v_add_f64 v[12:13], v[0:1], -s[20:21]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[14:15], v[2:3], -s[22:23]
v_add_f64 v[16:17], v[4:5], -s[24:25]
v_mov_b32_e32 v0, s4
v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v1, s5
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v3, s7
v_mov_b32_e32 v5, s9
s_mov_b32 s5, 0
.LBB0_7:
s_mov_b64 s[6:7], 0
s_mov_b64 s[8:9], s[10:11]
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_8:
s_load_b64 s[12:13], s[8:9], 0x0
s_cmp_eq_u32 s6, 1
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s6, 2
v_cndmask_b32_e32 v18, v13, v15, vcc_lo
s_cselect_b32 s1, -1, 0
s_cmp_eq_u32 s5, 1
v_cndmask_b32_e32 v20, v12, v14, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s5, 2
v_dual_cndmask_b32 v21, v1, v3 :: v_dual_cndmask_b32 v24, v0, v2
s_cselect_b32 s2, -1, 0
v_cndmask_b32_e64 v19, v18, v17, s1
v_cndmask_b32_e64 v18, v20, v16, s1
s_delay_alu instid0(VALU_DEP_3)
v_cndmask_b32_e64 v21, v21, v5, s2
v_cndmask_b32_e64 v20, v24, v4, s2
s_cmp_eq_u32 s5, 0
s_cselect_b32 s1, -1, 0
s_add_u32 s6, s6, 1
s_waitcnt lgkmcnt(0)
v_fma_f64 v[18:19], v[18:19], s[12:13], v[20:21]
s_addc_u32 s7, s7, 0
s_add_u32 s8, s8, 24
s_addc_u32 s9, s9, 0
s_cmp_eq_u32 s6, 3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v3, v3, v19, vcc_lo
v_cndmask_b32_e64 v5, v5, v19, s2
v_cndmask_b32_e64 v4, v4, v18, s2
v_cndmask_b32_e32 v2, v2, v18, vcc_lo
v_cndmask_b32_e64 v1, v1, v19, s1
v_cndmask_b32_e64 v0, v0, v18, s1
s_cbranch_scc0 .LBB0_8
s_set_inst_prefetch_distance 0x2
s_cmp_eq_u32 s5, 1
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s5, 2
v_cndmask_b32_e32 v20, v13, v15, vcc_lo
v_cndmask_b32_e32 v24, v12, v14, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_add_i32 s5, s5, 1
s_add_u32 s10, s10, 8
v_cndmask_b32_e32 v21, v20, v17, vcc_lo
v_cndmask_b32_e32 v20, v24, v16, vcc_lo
s_addc_u32 s11, s11, 0
s_cmp_eq_u32 s5, 3
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[10:11], -v[20:21], v[18:19], v[10:11]
s_cbranch_scc0 .LBB0_7
v_mov_b32_e32 v0, 0
s_and_not1_b32 vcc_lo, exec_lo, s3
global_store_b8 v[8:9], v0, off offset:3
s_cbranch_vccnz .LBB0_5
v_mov_b32_e32 v24, 1
s_branch .LBB0_13
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u16 v24, v24, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_bfe_i32 v0, v24, 0, 8
v_cmp_gt_i32_e32 vcc_lo, s17, v0
s_cbranch_vccz .LBB0_5
.LBB0_13:
global_load_b32 v0, v[8:9], off
v_readfirstlane_b32 s6, v24
s_mov_b32 s7, 0
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, GPU_INVERT_COV@rel32@lo+4
s_addc_u32 s9, s9, GPU_INVERT_COV@rel32@hi+12
v_mov_b32_e32 v18, 0
s_bfe_i64 s[10:11], s[6:7], 0x80000
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s2, s10, 0x48
s_mul_hi_i32 s1, s10, 0x48
s_add_u32 s6, s2, s8
s_mul_i32 s5, s10, 24
s_addc_u32 s7, s1, s9
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, GPU_AVG@rel32@lo+4
s_addc_u32 s9, s9, GPU_AVG@rel32@hi+12
s_mul_hi_i32 s1, s10, 24
s_add_u32 s8, s5, s8
s_addc_u32 s9, s1, s9
s_getpc_b64 s[10:11]
s_add_u32 s10, s10, GPU_AVG@rel32@lo+12
s_addc_u32 s11, s11, GPU_AVG@rel32@hi+20
s_add_u32 s10, s5, s10
s_addc_u32 s11, s1, s11
s_getpc_b64 s[12:13]
s_add_u32 s12, s12, GPU_AVG@rel32@lo+20
s_addc_u32 s13, s13, GPU_AVG@rel32@hi+28
s_add_u32 s12, s5, s12
s_addc_u32 s13, s1, s13
s_clause 0x2
s_load_b64 s[8:9], s[8:9], 0x0
s_load_b64 s[10:11], s[10:11], 0x0
s_load_b64 s[12:13], s[12:13], 0x0
s_waitcnt vmcnt(0)
v_and_b32_e32 v1, 0xff, v0
v_bfe_u32 v2, v0, 8, 8
v_bfe_u32 v4, v0, 16, 8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f64_i32_e32 v[0:1], v1
v_cvt_f64_i32_e32 v[2:3], v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cvt_f64_i32_e32 v[4:5], v4
s_waitcnt lgkmcnt(0)
v_add_f64 v[12:13], v[0:1], -s[8:9]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[14:15], v[2:3], -s[10:11]
v_add_f64 v[16:17], v[4:5], -s[12:13]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
s_mov_b32 s12, s8
s_mov_b32 s13, s8
v_dual_mov_b32 v19, 0 :: v_dual_mov_b32 v0, s8
v_dual_mov_b32 v1, s9 :: v_dual_mov_b32 v2, s10
v_dual_mov_b32 v3, s11 :: v_dual_mov_b32 v4, s12
v_mov_b32_e32 v5, s13
.LBB0_14:
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[6:7]
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_15:
s_load_b64 s[30:31], s[12:13], 0x0
s_cmp_eq_u32 s10, 1
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s10, 2
v_dual_cndmask_b32 v20, v13, v15 :: v_dual_cndmask_b32 v25, v12, v14
s_cselect_b32 s1, -1, 0
s_cmp_eq_u32 s8, 1
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s8, 2
v_dual_cndmask_b32 v26, v1, v3 :: v_dual_cndmask_b32 v27, v0, v2
s_cselect_b32 s2, -1, 0
v_cndmask_b32_e64 v21, v20, v17, s1
v_cndmask_b32_e64 v20, v25, v16, s1
s_delay_alu instid0(VALU_DEP_3)
v_cndmask_b32_e64 v26, v26, v5, s2
v_cndmask_b32_e64 v25, v27, v4, s2
s_cmp_eq_u32 s8, 0
s_cselect_b32 s1, -1, 0
s_add_u32 s10, s10, 1
s_waitcnt lgkmcnt(0)
v_fma_f64 v[20:21], v[20:21], s[30:31], v[25:26]
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 24
s_addc_u32 s13, s13, 0
s_cmp_eq_u32 s10, 3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v5, v5, v21, s2
v_cndmask_b32_e64 v4, v4, v20, s2
v_dual_cndmask_b32 v3, v3, v21 :: v_dual_cndmask_b32 v2, v2, v20
v_cndmask_b32_e64 v1, v1, v21, s1
v_cndmask_b32_e64 v0, v0, v20, s1
s_cbranch_scc0 .LBB0_15
s_set_inst_prefetch_distance 0x2
s_cmp_eq_u32 s8, 1
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s8, 2
v_cndmask_b32_e32 v25, v13, v15, vcc_lo
v_cndmask_b32_e32 v27, v12, v14, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_add_i32 s8, s8, 1
s_add_u32 s6, s6, 8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v26, v25, v17 :: v_dual_cndmask_b32 v25, v27, v16
s_addc_u32 s7, s7, 0
s_cmp_eq_u32 s8, 3
v_fma_f64 v[18:19], -v[25:26], v[20:21], v[18:19]
s_cbranch_scc0 .LBB0_14
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_f64_e32 v[18:19], v[10:11]
s_cbranch_execz .LBB0_12
v_dual_mov_b32 v10, v18 :: v_dual_mov_b32 v11, v19
global_store_b8 v[8:9], v24, off offset:3
s_branch .LBB0_12
.LBB0_19:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelP15HIP_vector_typeIhLj4EEjji
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 28
.amdhsa_next_free_sgpr 32
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelP15HIP_vector_typeIhLj4EEjji, .Lfunc_end0-_Z6kernelP15HIP_vector_typeIhLj4EEjji
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected GPU_AVG
.type GPU_AVG,@object
.section .bss,"aw",@nobits
.globl GPU_AVG
.p2align 4, 0x0
GPU_AVG:
.zero 1200
.size GPU_AVG, 1200
.protected GPU_INVERT_COV
.type GPU_INVERT_COV,@object
.globl GPU_INVERT_COV
.p2align 4, 0x0
GPU_INVERT_COV:
.zero 3600
.size GPU_INVERT_COV, 3600
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym GPU_AVG
.addrsig_sym GPU_INVERT_COV
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelP15HIP_vector_typeIhLj4EEjji
.private_segment_fixed_size: 0
.sgpr_count: 34
.sgpr_spill_count: 0
.symbol: _Z6kernelP15HIP_vector_typeIhLj4EEjji.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 28
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kernelP6uchar4jji
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e620000002600 */
/*0040*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fc600078e0203 */
/*0050*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002200 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06070 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ ULDC UR5, c[0x0][0x170] ; /* 0x00005c0000057ab9 */
/* 0x002fe20000000800 */
/*0090*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fe200078e0203 */
/*00a0*/ UIADD3 UR4, UR5, -0x1, URZ ; /* 0xffffffff05047890 */
/* 0x000fe4000fffe03f */
/*00b0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*00c0*/ ULOP3.LUT UR4, UR4, 0x1, URZ, 0xc0, !UPT ; /* 0x0000000104047892 */
/* 0x000fc8000f8ec03f */
/*00d0*/ UIADD3 UR5, -UR4, UR5, URZ ; /* 0x0000000504057290 */
/* 0x000fe4000fffe13f */
/*00e0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fe20003f06070 */
/*00f0*/ BSSY B0, 0xb90 ; /* 0x00000a9000007945 */
/* 0x000fd80003800000 */
/*0100*/ @P0 BRA 0xb80 ; /* 0x00000a7000000947 */
/* 0x003fea0003800000 */
/*0110*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff037624 */
/* 0x000fca00078e00ff */
/*0120*/ ISETP.GT.AND P0, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fda0003f04270 */
/*0130*/ @P0 BRA 0x1e0 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0140*/ MOV R3, R0 ; /* 0x0000000000037202 */
/* 0x000fe20000000f00 */
/*0150*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0160*/ MOV R6, c[0x0][0x4] ; /* 0x0000010000067a02 */
/* 0x000fc60000000f00 */
/*0170*/ IMAD R4, R3, c[0x0][0x168], R2 ; /* 0x00005a0003047a24 */
/* 0x000fe400078e0202 */
/*0180*/ IMAD R3, R6, c[0x0][0x10], R3 ; /* 0x0000040006037a24 */
/* 0x000fe400078e0203 */
/*0190*/ IMAD.WIDE.U32 R4, R4, R7, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc600078e0007 */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x16c], PT ; /* 0x00005b0003007a0c */
/* 0x000fe40003f06070 */
/*01b0*/ STG.E.U8 [R4.64+0x3], RZ ; /* 0x000003ff04007986 */
/* 0x0001f6000c101106 */
/*01c0*/ @!P0 BRA 0x170 ; /* 0xffffffa000008947 */
/* 0x001fea000383ffff */
/*01d0*/ BRA 0xb80 ; /* 0x000009a000007947 */
/* 0x000fea0003800000 */
/*01e0*/ IMAD.MOV.U32 R3, RZ, RZ, R0 ; /* 0x000000ffff037224 */
/* 0x000fc600078e0000 */
/*01f0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x001fe200000001ff */
/*0200*/ IMAD R6, R3, c[0x0][0x168], R2 ; /* 0x00005a0003067a24 */
/* 0x000fd200078e0202 */
/*0210*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fca00078e0007 */
/*0220*/ LDG.E R18, [R6.64] ; /* 0x0000000606127981 */
/* 0x000ea2000c1e1900 */
/*0230*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fc6000bf05270 */
/*0240*/ STG.E.U8 [R6.64+0x3], RZ ; /* 0x000003ff06007986 */
/* 0x0001e2000c101106 */
/*0250*/ I2F.F64.U8 R4, R18 ; /* 0x0000001200047312 */
/* 0x006e700000001800 */
/*0260*/ I2F.F64.U8 R8, R18.B1 ; /* 0x1000001200087312 */
/* 0x000eb00000001800 */
/*0270*/ I2F.F64.U8 R12, R18.B2 ; /* 0x20000012000c7312 */
/* 0x000ee20000001800 */
/*0280*/ DADD R10, R4, -c[0x3][0x0] ; /* 0x80c00000040a7629 */
/* 0x002e4c0000000000 */
/*0290*/ DFMA R14, R10, c[0x3][0x4b0], RZ ; /* 0x00c12c000a0e7a2b */
/* 0x002fc800000000ff */
/*02a0*/ DADD R4, R8, -c[0x3][0x8] ; /* 0x80c0020008047629 */
/* 0x004e480000000000 */
/*02b0*/ DFMA R16, R10, c[0x3][0x4c0], RZ ; /* 0x00c130000a107a2b */
/* 0x000fc800000000ff */
/*02c0*/ DADD R8, R12, -c[0x3][0x10] ; /* 0x80c004000c087629 */
/* 0x008fc80000000000 */
/*02d0*/ DFMA R14, R4, c[0x3][0x4c8], R14 ; /* 0x00c13200040e7a2b */
/* 0x002e48000000000e */
/*02e0*/ DFMA R12, R10, c[0x3][0x4b8], RZ ; /* 0x00c12e000a0c7a2b */
/* 0x000e8800000000ff */
/*02f0*/ DFMA R14, R8, c[0x3][0x4e0], R14 ; /* 0x00c13800080e7a2b */
/* 0x002e48000000000e */
/*0300*/ DFMA R12, R4, c[0x3][0x4d0], R12 ; /* 0x00c13400040c7a2b */
/* 0x004e88000000000c */
/*0310*/ DFMA R14, -R10, R14, RZ ; /* 0x0000000e0a0e722b */
/* 0x0023e400000001ff */
/*0320*/ MOV R11, c[0x0][0x170] ; /* 0x00005c00000b7a02 */
/* 0x002fe20000000f00 */
/*0330*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x4] ; /* 0x00000100ff0a7624 */
/* 0x000fe200078e00ff */
/*0340*/ DFMA R12, R8, c[0x3][0x4e8], R12 ; /* 0x00c13a00080c7a2b */
/* 0x004e64000000000c */
/*0350*/ ISETP.NE.AND P2, PT, R11, 0x2, PT ; /* 0x000000020b00780c */
/* 0x000fe20003f45270 */
/*0360*/ IMAD R3, R10, c[0x0][0x10], R3 ; /* 0x000004000a037a24 */
/* 0x000fe200078e0203 */
/*0370*/ DFMA R16, R4, c[0x3][0x4d8], R16 ; /* 0x00c1360004107a2b */
/* 0x000e880000000010 */
/*0380*/ DFMA R12, -R4, R12, R14 ; /* 0x0000000c040c722b */
/* 0x0023e2000000010e */
/*0390*/ ISETP.GE.U32.AND P1, PT, R3, c[0x0][0x16c], PT ; /* 0x00005b0003007a0c */
/* 0x000fe20003f26070 */
/*03a0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x002fe400078e00ff */
/*03b0*/ DFMA R16, R8, c[0x3][0x4f0], R16 ; /* 0x00c13c0008107a2b */
/* 0x004e4c0000000010 */
/*03c0*/ DFMA R8, -R8, R16, R12 ; /* 0x000000100808722b */
/* 0x002062000000010c */
/*03d0*/ @!P2 BRA 0x900 ; /* 0x000005200000a947 */
/* 0x000fea0003800000 */
/*03e0*/ MOV R4, 0x1 ; /* 0x0000000100047802 */
/* 0x000fe20000000f00 */
/*03f0*/ IMAD.U32 R5, RZ, RZ, UR5 ; /* 0x00000005ff057e24 */
/* 0x000fc8000f8e00ff */
/*0400*/ LDG.E R34, [R6.64] ; /* 0x0000000606227981 */
/* 0x000ea2000c1e1900 */
/*0410*/ LOP3.LUT R10, R4, 0xffff, RZ, 0xc0, !PT ; /* 0x0000ffff040a7812 */
/* 0x000fc800078ec0ff */
/*0420*/ PRMT R33, R10, 0x8880, RZ ; /* 0x000088800a217816 */
/* 0x000fe400000000ff */
/*0430*/ MOV R10, 0x48 ; /* 0x00000048000a7802 */
/* 0x000fc60000000f00 */
/*0440*/ IMAD R32, R33.reuse, 0x18, RZ ; /* 0x0000001821207824 */
/* 0x040fe400078e02ff */
/*0450*/ IMAD R33, R33, R10, c[0x2][0x0] ; /* 0x0080000021217624 */
/* 0x000fe400078e020a */
/*0460*/ LDC.64 R28, c[0x3][R32] ; /* 0x00c00000201c7b82 */
/* 0x000ef00000000a00 */
/*0470*/ LDC.64 R30, c[0x3][R33] ; /* 0x00c00000211e7b82 */
/* 0x000f300000000a00 */
/*0480*/ LDC.64 R20, c[0x3][R32+0x8] ; /* 0x00c0020020147b82 */
/* 0x000f700000000a00 */
/*0490*/ LDC.64 R26, c[0x3][R33+0x18] ; /* 0x00c00600211a7b82 */
/* 0x001e300000000a00 */
/*04a0*/ LDC.64 R24, c[0x3][R33+0x8] ; /* 0x00c0020021187b82 */
/* 0x000e700000000a00 */
/*04b0*/ LDC.64 R16, c[0x3][R32+0x10] ; /* 0x00c0040020107b82 */
/* 0x001e300000000a00 */
/*04c0*/ LDC.64 R18, c[0x3][R33+0x30] ; /* 0x00c00c0021127b82 */
/* 0x000e300000000a00 */
/*04d0*/ LDC.64 R22, c[0x3][R33+0x20] ; /* 0x00c0080021167b82 */
/* 0x000e220000000a00 */
/*04e0*/ I2F.F64.U8 R10, R34 ; /* 0x00000022000a7312 */
/* 0x004ef00000001800 */
/*04f0*/ I2F.F64.U8 R12, R34.B1 ; /* 0x10000022000c7312 */
/* 0x000f620000001800 */
/*0500*/ DADD R28, R10, -R28 ; /* 0x000000000a1c7229 */
/* 0x008f0e000000081c */
/*0510*/ I2F.F64.U8 R14, R34.B2 ; /* 0x20000022000e7312 */
/* 0x000e220000001800 */
/*0520*/ DFMA R30, R28, R30, RZ ; /* 0x0000001e1c1e722b */
/* 0x010fc800000000ff */
/*0530*/ DADD R20, R12, -R20 ; /* 0x000000000c147229 */
/* 0x020e880000000814 */
/*0540*/ DFMA R24, R28, R24, RZ ; /* 0x000000181c18722b */
/* 0x002e4800000000ff */
/*0550*/ DFMA R26, R20, R26, R30 ; /* 0x0000001a141a722b */
/* 0x0045e4000000001e */
/*0560*/ LDC.64 R30, c[0x3][R33+0x10] ; /* 0x00c00400211e7b82 */
/* 0x004ea40000000a00 */
/*0570*/ DADD R16, R14, -R16 ; /* 0x000000000e107229 */
/* 0x001e080000000810 */
/*0580*/ DFMA R22, R20, R22, R24 ; /* 0x000000161416722b */
/* 0x0023e40000000018 */
/*0590*/ LDC.64 R24, c[0x3][R33+0x38] ; /* 0x00c00e0021187b82 */
/* 0x002e640000000a00 */
/*05a0*/ DFMA R18, R16, R18, R26 ; /* 0x000000121012722b */
/* 0x0010cc000000001a */
/*05b0*/ LDC.64 R26, c[0x3][R33+0x28] ; /* 0x00c00a00211a7b82 */
/* 0x001e220000000a00 */
/*05c0*/ DFMA R18, -R28, R18, RZ ; /* 0x000000121c12722b */
/* 0x008fc800000001ff */
/*05d0*/ DFMA R30, R28, R30, RZ ; /* 0x0000001e1c1e722b */
/* 0x0045c600000000ff */
/*05e0*/ LDC.64 R28, c[0x3][R33+0x40] ; /* 0x00c01000211c7b82 */
/* 0x004ea20000000a00 */
/*05f0*/ DFMA R22, R16, R24, R22 ; /* 0x000000181016722b */
/* 0x002e4c0000000016 */
/*0600*/ DFMA R18, -R20, R22, R18 ; /* 0x000000161412722b */
/* 0x002fc80000000112 */
/*0610*/ DFMA R26, R20, R26, R30 ; /* 0x0000001a141a722b */
/* 0x001e8c000000001e */
/*0620*/ DFMA R26, R16, R28, R26 ; /* 0x0000001c101a722b */
/* 0x004e0c000000001a */
/*0630*/ DFMA R16, -R16, R26, R18 ; /* 0x0000001a1010722b */
/* 0x001e0c0000000112 */
/*0640*/ DSETP.GT.AND P2, PT, R16, R8, PT ; /* 0x000000081000722a */
/* 0x001e1c0003f44000 */
/*0650*/ @P2 STG.E.U8 [R6.64+0x3], R4 ; /* 0x0000030406002986 */
/* 0x0011e8000c101106 */
/*0660*/ @P2 LDG.E R34, [R6.64] ; /* 0x0000000606222981 */
/* 0x000ea2000c1e1900 */
/*0670*/ LDC.64 R28, c[0x3][R32+0x18] ; /* 0x00c00600201c7b82 */
/* 0x000e620000000a00 */
/*0680*/ @P2 IMAD.MOV.U32 R8, RZ, RZ, R16 ; /* 0x000000ffff082224 */
/* 0x000fe200078e0010 */
/*0690*/ @P2 MOV R9, R17 ; /* 0x0000001100092202 */
/* 0x000fe40000000f00 */
/*06a0*/ IADD3 R5, R5, -0x2, RZ ; /* 0xfffffffe05057810 */
/* 0x000fc80007ffe0ff */
/*06b0*/ LDC.64 R24, c[0x3][R32+0x28] ; /* 0x00c00a0020187b82 */
/* 0x000ee20000000a00 */
/*06c0*/ ISETP.NE.AND P3, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fce0003f65270 */
/*06d0*/ LDC.64 R26, c[0x3][R32+0x20] ; /* 0x00c00800201a7b82 */
/* 0x000f300000000a00 */
/*06e0*/ LDC.64 R22, c[0x3][R33+0x48] ; /* 0x00c0120021167b82 */
/* 0x000f700000000a00 */
/*06f0*/ LDC.64 R18, c[0x3][R33+0x60] ; /* 0x00c0180021127b82 */
/* 0x000e300000000a00 */
/*0700*/ LDC.64 R20, c[0x3][R33+0x78] ; /* 0x00c01e0021147b82 */
/* 0x000e220000000a00 */
/*0710*/ @P2 I2F.F64.U8 R10, R34 ; /* 0x00000022000a2312 */
/* 0x004e700000001800 */
/*0720*/ @P2 I2F.F64.U8 R14, R34.B2 ; /* 0x20000022000e2312 */
/* 0x000ef00000001800 */
/*0730*/ @P2 I2F.F64.U8 R12, R34.B1 ; /* 0x10000022000c2312 */
/* 0x000f220000001800 */
/*0740*/ DADD R10, -R28, R10 ; /* 0x000000001c0a7229 */
/* 0x002344000000010a */
/*0750*/ LDC.64 R28, c[0x3][R33+0x80] ; /* 0x00c02000211c7b82 */
/* 0x002e680000000a00 */
/*0760*/ DFMA R30, R10, R22, RZ ; /* 0x000000160a1e722b */
/* 0x0205c800000000ff */
/*0770*/ DADD R14, -R24, R14 ; /* 0x00000000180e7229 */
/* 0x0087e2000000010e */
/*0780*/ LDC.64 R22, c[0x3][R33+0x58] ; /* 0x00c0160021167b82 */
/* 0x004ea60000000a00 */
/*0790*/ DADD R12, -R26, R12 ; /* 0x000000001a0c7229 */
/* 0x010e0a000000010c */
/*07a0*/ LDC.64 R24, c[0x3][R33+0x50] ; /* 0x00c0140021187b82 */
/* 0x008ee20000000a00 */
/*07b0*/ DFMA R30, R12, R18, R30 ; /* 0x000000120c1e722b */
/* 0x001e0e000000001e */
/*07c0*/ LDC.64 R26, c[0x3][R33+0x68] ; /* 0x00c01a00211a7b82 */
/* 0x000f220000000a00 */
/*07d0*/ DFMA R20, R14, R20, R30 ; /* 0x000000140e14722b */
/* 0x001e0c000000001e */
/*07e0*/ DFMA R20, -R10.reuse, R20, RZ ; /* 0x000000140a14722b */
/* 0x041fe200000001ff */
/*07f0*/ LDC.64 R18, c[0x3][R33+0x70] ; /* 0x00c01c0021127b82 */
/* 0x000e260000000a00 */
/*0800*/ DFMA R22, R10, R22, RZ ; /* 0x000000160a16722b */
/* 0x004fca00000000ff */
/*0810*/ LDC.64 R30, c[0x3][R33+0x88] ; /* 0x00c02200211e7b82 */
/* 0x000ea20000000a00 */
/*0820*/ DFMA R24, R10, R24, RZ ; /* 0x000000180a18722b */
/* 0x008f0c00000000ff */
/*0830*/ DFMA R24, R12, R26, R24 ; /* 0x0000001a0c18722b */
/* 0x010e4c0000000018 */
/*0840*/ DFMA R24, R14, R28, R24 ; /* 0x0000001c0e18722b */
/* 0x002e480000000018 */
/*0850*/ DFMA R18, R12, R18, R22 ; /* 0x000000120c12722b */
/* 0x001e880000000016 */
/*0860*/ DFMA R20, -R12, R24, R20 ; /* 0x000000180c14722b */
/* 0x002fc80000000114 */
/*0870*/ DFMA R18, R14, R30, R18 ; /* 0x0000001e0e12722b */
/* 0x004e0c0000000012 */
/*0880*/ DFMA R18, -R14, R18, R20 ; /* 0x000000120e12722b */
/* 0x001e0c0000000114 */
/*0890*/ DSETP.GT.AND P2, PT, R18, R8, PT ; /* 0x000000081200722a */
/* 0x001e1c0003f44000 */
/*08a0*/ @P2 IADD3 R11, R4.reuse, 0x1, RZ ; /* 0x00000001040b2810 */
/* 0x041fe20007ffe0ff */
/*08b0*/ @P2 IMAD.MOV.U32 R8, RZ, RZ, R18 ; /* 0x000000ffff082224 */
/* 0x000fe200078e0012 */
/*08c0*/ IADD3 R4, R4, 0x2, RZ ; /* 0x0000000204047810 */
/* 0x000fe40007ffe0ff */
/*08d0*/ @P2 MOV R9, R19 ; /* 0x0000001300092202 */
/* 0x000fe20000000f00 */
/*08e0*/ @P2 STG.E.U8 [R6.64+0x3], R11 ; /* 0x0000030b06002986 */
/* 0x0001e2000c101106 */
/*08f0*/ @P3 BRA 0x400 ; /* 0xfffffb0000003947 */
/* 0x000fea000383ffff */
/*0900*/ @!P0 BRA 0xb70 ; /* 0x0000026000008947 */
/* 0x000fea0003800000 */
/*0910*/ LDG.E R35, [R6.64] ; /* 0x0000000606237981 */
/* 0x000ea2000c1e1900 */
/*0920*/ LOP3.LUT R5, R4, 0xffff, RZ, 0xc0, !PT ; /* 0x0000ffff04057812 */
/* 0x000fe200078ec0ff */
/*0930*/ IMAD.MOV.U32 R14, RZ, RZ, 0x48 ; /* 0x00000048ff0e7424 */
/* 0x000fc600078e00ff */
/*0940*/ PRMT R5, R5, 0x8880, RZ ; /* 0x0000888005057816 */
/* 0x000fca00000000ff */
/*0950*/ IMAD R34, R5.reuse, 0x18, RZ ; /* 0x0000001805227824 */
/* 0x040fe400078e02ff */
/*0960*/ IMAD R5, R5, R14, c[0x2][0x0] ; /* 0x0080000005057624 */
/* 0x000fe400078e020e */
/*0970*/ LDC.64 R10, c[0x3][R34] ; /* 0x00c00000220a7b82 */
/* 0x001e300000000a00 */
/*0980*/ LDC.64 R12, c[0x3][R34+0x8] ; /* 0x00c00200220c7b82 */
/* 0x000ef00000000a00 */
/*0990*/ LDC.64 R32, c[0x3][R5] ; /* 0x00c0000005207b82 */
/* 0x000f300000000a00 */
/*09a0*/ LDC.64 R30, c[0x3][R5+0x18] ; /* 0x00c00600051e7b82 */
/* 0x000f700000000a00 */
/*09b0*/ LDC.64 R16, c[0x3][R34+0x10] ; /* 0x00c0040022107b82 */
/* 0x000e700000000a00 */
/*09c0*/ LDC.64 R26, c[0x3][R5+0x30] ; /* 0x00c00c00051a7b82 */
/* 0x000e300000000a00 */
/*09d0*/ LDC.64 R24, c[0x3][R5+0x20] ; /* 0x00c0080005187b82 */
/* 0x000e300000000a00 */
/*09e0*/ LDC.64 R20, c[0x3][R5+0x28] ; /* 0x00c00a0005147b82 */
/* 0x000e300000000a00 */
/*09f0*/ LDC.64 R18, c[0x3][R5+0x38] ; /* 0x00c00e0005127b82 */
/* 0x000e220000000a00 */
/*0a00*/ I2F.F64.U8 R22, R35 ; /* 0x0000002300167312 */
/* 0x004e300000001800 */
/*0a10*/ I2F.F64.U8 R14, R35.B1 ; /* 0x10000023000e7312 */
/* 0x000ee20000001800 */
/*0a20*/ DADD R22, R22, -R10 ; /* 0x0000000016167229 */
/* 0x00110e000000080a */
/*0a30*/ I2F.F64.U8 R28, R35.B2 ; /* 0x20000023001c7312 */
/* 0x000e620000001800 */
/*0a40*/ LDC.64 R10, c[0x3][R5+0x8] ; /* 0x00c00200050a7b82 */
/* 0x001e220000000a00 */
/*0a50*/ DFMA R32, R22, R32, RZ ; /* 0x000000201620722b */
/* 0x010fc800000000ff */
/*0a60*/ DADD R12, R14, -R12 ; /* 0x000000000e0c7229 */
/* 0x008546000000080c */
/*0a70*/ LDC.64 R14, c[0x3][R5+0x10] ; /* 0x00c00400050e7b82 */
/* 0x004ea60000000a00 */
/*0a80*/ DFMA R30, R12, R30, R32 ; /* 0x0000001e0c1e722b */
/* 0x0207ca0000000020 */
/*0a90*/ LDC.64 R32, c[0x3][R5+0x40] ; /* 0x00c0100005207b82 */
/* 0x008ee20000000a00 */
/*0aa0*/ DADD R16, R28, -R16 ; /* 0x000000001c107229 */
/* 0x002e480000000810 */
/*0ab0*/ DFMA R10, R22, R10, RZ ; /* 0x0000000a160a722b */
/* 0x001e0800000000ff */
/*0ac0*/ DFMA R26, R16, R26, R30 ; /* 0x0000001a101a722b */
/* 0x002e48000000001e */
/*0ad0*/ DFMA R10, R12, R24, R10 ; /* 0x000000180c0a722b */
/* 0x001fc8000000000a */
/*0ae0*/ DFMA R14, R22, R14, RZ ; /* 0x0000000e160e722b */
/* 0x004e0800000000ff */
/*0af0*/ DFMA R26, -R22, R26, RZ ; /* 0x0000001a161a722b */
/* 0x002fc800000001ff */
/*0b00*/ DFMA R14, R12, R20, R14 ; /* 0x000000140c0e722b */
/* 0x001ec8000000000e */
/*0b10*/ DFMA R10, R16, R18, R10 ; /* 0x00000012100a722b */
/* 0x000e08000000000a */
/*0b20*/ DFMA R14, R16, R32, R14 ; /* 0x00000020100e722b */
/* 0x008fc8000000000e */
/*0b30*/ DFMA R10, -R12, R10, R26 ; /* 0x0000000a0c0a722b */
/* 0x001e0c000000011a */
/*0b40*/ DFMA R10, -R16, R14, R10 ; /* 0x0000000e100a722b */
/* 0x001e0c000000010a */
/*0b50*/ DSETP.GT.AND P0, PT, R10, R8, PT ; /* 0x000000080a00722a */
/* 0x001e1c0003f04000 */
/*0b60*/ @P0 STG.E.U8 [R6.64+0x3], R4 ; /* 0x0000030406000986 */
/* 0x0011e4000c101106 */
/*0b70*/ @!P1 BRA 0x1f0 ; /* 0xfffff67000009947 */
/* 0x000fea000383ffff */
/*0b80*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0b90*/ MOV R3, c[0x0][0x0] ; /* 0x0000000000037a02 */
/* 0x000fca0000000f00 */
/*0ba0*/ IMAD R2, R3, c[0x0][0xc], R2 ; /* 0x0000030003027a24 */
/* 0x000fca00078e0202 */
/*0bb0*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06070 */
/*0bc0*/ @!P0 BRA 0xe0 ; /* 0xfffff51000008947 */
/* 0x000fea000383ffff */
/*0bd0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0be0*/ BRA 0xbe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelP15HIP_vector_typeIhLj4EEjji
.globl _Z6kernelP15HIP_vector_typeIhLj4EEjji
.p2align 8
.type _Z6kernelP15HIP_vector_typeIhLj4EEjji,@function
_Z6kernelP15HIP_vector_typeIhLj4EEjji:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s26, s[0:1], 0x8
v_and_b32_e32 v1, 0x3ff, v0
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[6:7], null, s14, s4, v[1:2]
v_cmpx_gt_u32_e64 s26, v6
s_cbranch_execz .LBB0_19
s_load_b32 s5, s[2:3], 0xc
s_load_b64 s[16:17], s[0:1], 0xc
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, GPU_AVG@rel32@lo+4
s_addc_u32 s7, s7, GPU_AVG@rel32@hi+12
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, GPU_AVG@rel32@lo+12
s_addc_u32 s9, s9, GPU_AVG@rel32@hi+20
s_getpc_b64 s[10:11]
s_add_u32 s10, s10, GPU_AVG@rel32@lo+20
s_addc_u32 s11, s11, GPU_AVG@rel32@hi+28
s_load_b64 s[12:13], s[2:3], 0x0
s_load_b64 s[18:19], s[0:1], 0x0
s_clause 0x2
s_load_b64 s[20:21], s[6:7], 0x0
s_load_b64 s[22:23], s[8:9], 0x0
s_load_b64 s[24:25], s[10:11], 0x0
v_bfe_u32 v0, v0, 10, 10
v_mov_b32_e32 v22, 0
s_mov_b32 s27, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s1, s5, 16
s_cmp_gt_i32 s17, 1
v_mad_u64_u32 v[7:8], null, s15, s1, v[0:1]
s_cselect_b32 s3, -1, 0
s_mul_i32 s14, s12, s4
s_mul_i32 s15, s13, s1
s_mov_b32 s4, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u32_e64 s0, s16, v7
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s28
v_add_nc_u32_e32 v6, s14, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_u32_e32 vcc_lo, s26, v6
s_or_b32 s27, vcc_lo, s27
s_and_not1_b32 exec_lo, exec_lo, s27
s_cbranch_execz .LBB0_19
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s28, s0
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v23, v7
s_mov_b32 s29, 0
s_branch .LBB0_6
.LBB0_5:
v_add_nc_u32_e32 v23, s15, v23
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_u32_e32 vcc_lo, s16, v23
s_or_b32 s29, vcc_lo, s29
s_and_not1_b32 exec_lo, exec_lo, s29
s_cbranch_execz .LBB0_2
.LBB0_6:
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v23, s26, v[6:7]
v_dual_mov_b32 v1, v22 :: v_dual_mov_b32 v10, 0
s_mov_b32 s5, s4
s_mov_b32 s6, s4
s_mov_b32 s7, s4
s_mov_b32 s8, s4
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_mov_b32 s9, s4
v_mov_b32_e32 v11, 0
s_getpc_b64 s[10:11]
s_add_u32 s10, s10, GPU_INVERT_COV@rel32@lo+4
s_addc_u32 s11, s11, GPU_INVERT_COV@rel32@hi+12
v_add_co_u32 v8, vcc_lo, s18, v0
v_add_co_ci_u32_e32 v9, vcc_lo, s19, v1, vcc_lo
global_load_b32 v0, v[8:9], off
s_waitcnt vmcnt(0)
v_and_b32_e32 v1, 0xff, v0
v_bfe_u32 v2, v0, 8, 8
v_bfe_u32 v4, v0, 16, 8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f64_i32_e32 v[0:1], v1
v_cvt_f64_i32_e32 v[2:3], v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f64_i32_e32 v[4:5], v4
v_add_f64 v[12:13], v[0:1], -s[20:21]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[14:15], v[2:3], -s[22:23]
v_add_f64 v[16:17], v[4:5], -s[24:25]
v_mov_b32_e32 v0, s4
v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v1, s5
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v3, s7
v_mov_b32_e32 v5, s9
s_mov_b32 s5, 0
.LBB0_7:
s_mov_b64 s[6:7], 0
s_mov_b64 s[8:9], s[10:11]
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_8:
s_load_b64 s[12:13], s[8:9], 0x0
s_cmp_eq_u32 s6, 1
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s6, 2
v_cndmask_b32_e32 v18, v13, v15, vcc_lo
s_cselect_b32 s1, -1, 0
s_cmp_eq_u32 s5, 1
v_cndmask_b32_e32 v20, v12, v14, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s5, 2
v_dual_cndmask_b32 v21, v1, v3 :: v_dual_cndmask_b32 v24, v0, v2
s_cselect_b32 s2, -1, 0
v_cndmask_b32_e64 v19, v18, v17, s1
v_cndmask_b32_e64 v18, v20, v16, s1
s_delay_alu instid0(VALU_DEP_3)
v_cndmask_b32_e64 v21, v21, v5, s2
v_cndmask_b32_e64 v20, v24, v4, s2
s_cmp_eq_u32 s5, 0
s_cselect_b32 s1, -1, 0
s_add_u32 s6, s6, 1
s_waitcnt lgkmcnt(0)
v_fma_f64 v[18:19], v[18:19], s[12:13], v[20:21]
s_addc_u32 s7, s7, 0
s_add_u32 s8, s8, 24
s_addc_u32 s9, s9, 0
s_cmp_eq_u32 s6, 3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v3, v3, v19, vcc_lo
v_cndmask_b32_e64 v5, v5, v19, s2
v_cndmask_b32_e64 v4, v4, v18, s2
v_cndmask_b32_e32 v2, v2, v18, vcc_lo
v_cndmask_b32_e64 v1, v1, v19, s1
v_cndmask_b32_e64 v0, v0, v18, s1
s_cbranch_scc0 .LBB0_8
s_set_inst_prefetch_distance 0x2
s_cmp_eq_u32 s5, 1
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s5, 2
v_cndmask_b32_e32 v20, v13, v15, vcc_lo
v_cndmask_b32_e32 v24, v12, v14, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_add_i32 s5, s5, 1
s_add_u32 s10, s10, 8
v_cndmask_b32_e32 v21, v20, v17, vcc_lo
v_cndmask_b32_e32 v20, v24, v16, vcc_lo
s_addc_u32 s11, s11, 0
s_cmp_eq_u32 s5, 3
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[10:11], -v[20:21], v[18:19], v[10:11]
s_cbranch_scc0 .LBB0_7
v_mov_b32_e32 v0, 0
s_and_not1_b32 vcc_lo, exec_lo, s3
global_store_b8 v[8:9], v0, off offset:3
s_cbranch_vccnz .LBB0_5
v_mov_b32_e32 v24, 1
s_branch .LBB0_13
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u16 v24, v24, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_bfe_i32 v0, v24, 0, 8
v_cmp_gt_i32_e32 vcc_lo, s17, v0
s_cbranch_vccz .LBB0_5
.LBB0_13:
global_load_b32 v0, v[8:9], off
v_readfirstlane_b32 s6, v24
s_mov_b32 s7, 0
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, GPU_INVERT_COV@rel32@lo+4
s_addc_u32 s9, s9, GPU_INVERT_COV@rel32@hi+12
v_mov_b32_e32 v18, 0
s_bfe_i64 s[10:11], s[6:7], 0x80000
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s2, s10, 0x48
s_mul_hi_i32 s1, s10, 0x48
s_add_u32 s6, s2, s8
s_mul_i32 s5, s10, 24
s_addc_u32 s7, s1, s9
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, GPU_AVG@rel32@lo+4
s_addc_u32 s9, s9, GPU_AVG@rel32@hi+12
s_mul_hi_i32 s1, s10, 24
s_add_u32 s8, s5, s8
s_addc_u32 s9, s1, s9
s_getpc_b64 s[10:11]
s_add_u32 s10, s10, GPU_AVG@rel32@lo+12
s_addc_u32 s11, s11, GPU_AVG@rel32@hi+20
s_add_u32 s10, s5, s10
s_addc_u32 s11, s1, s11
s_getpc_b64 s[12:13]
s_add_u32 s12, s12, GPU_AVG@rel32@lo+20
s_addc_u32 s13, s13, GPU_AVG@rel32@hi+28
s_add_u32 s12, s5, s12
s_addc_u32 s13, s1, s13
s_clause 0x2
s_load_b64 s[8:9], s[8:9], 0x0
s_load_b64 s[10:11], s[10:11], 0x0
s_load_b64 s[12:13], s[12:13], 0x0
s_waitcnt vmcnt(0)
v_and_b32_e32 v1, 0xff, v0
v_bfe_u32 v2, v0, 8, 8
v_bfe_u32 v4, v0, 16, 8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f64_i32_e32 v[0:1], v1
v_cvt_f64_i32_e32 v[2:3], v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cvt_f64_i32_e32 v[4:5], v4
s_waitcnt lgkmcnt(0)
v_add_f64 v[12:13], v[0:1], -s[8:9]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[14:15], v[2:3], -s[10:11]
v_add_f64 v[16:17], v[4:5], -s[12:13]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
s_mov_b32 s12, s8
s_mov_b32 s13, s8
v_dual_mov_b32 v19, 0 :: v_dual_mov_b32 v0, s8
v_dual_mov_b32 v1, s9 :: v_dual_mov_b32 v2, s10
v_dual_mov_b32 v3, s11 :: v_dual_mov_b32 v4, s12
v_mov_b32_e32 v5, s13
.LBB0_14:
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[6:7]
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_15:
s_load_b64 s[30:31], s[12:13], 0x0
s_cmp_eq_u32 s10, 1
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s10, 2
v_dual_cndmask_b32 v20, v13, v15 :: v_dual_cndmask_b32 v25, v12, v14
s_cselect_b32 s1, -1, 0
s_cmp_eq_u32 s8, 1
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s8, 2
v_dual_cndmask_b32 v26, v1, v3 :: v_dual_cndmask_b32 v27, v0, v2
s_cselect_b32 s2, -1, 0
v_cndmask_b32_e64 v21, v20, v17, s1
v_cndmask_b32_e64 v20, v25, v16, s1
s_delay_alu instid0(VALU_DEP_3)
v_cndmask_b32_e64 v26, v26, v5, s2
v_cndmask_b32_e64 v25, v27, v4, s2
s_cmp_eq_u32 s8, 0
s_cselect_b32 s1, -1, 0
s_add_u32 s10, s10, 1
s_waitcnt lgkmcnt(0)
v_fma_f64 v[20:21], v[20:21], s[30:31], v[25:26]
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 24
s_addc_u32 s13, s13, 0
s_cmp_eq_u32 s10, 3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v5, v5, v21, s2
v_cndmask_b32_e64 v4, v4, v20, s2
v_dual_cndmask_b32 v3, v3, v21 :: v_dual_cndmask_b32 v2, v2, v20
v_cndmask_b32_e64 v1, v1, v21, s1
v_cndmask_b32_e64 v0, v0, v20, s1
s_cbranch_scc0 .LBB0_15
s_set_inst_prefetch_distance 0x2
s_cmp_eq_u32 s8, 1
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s8, 2
v_cndmask_b32_e32 v25, v13, v15, vcc_lo
v_cndmask_b32_e32 v27, v12, v14, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_add_i32 s8, s8, 1
s_add_u32 s6, s6, 8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v26, v25, v17 :: v_dual_cndmask_b32 v25, v27, v16
s_addc_u32 s7, s7, 0
s_cmp_eq_u32 s8, 3
v_fma_f64 v[18:19], -v[25:26], v[20:21], v[18:19]
s_cbranch_scc0 .LBB0_14
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_f64_e32 v[18:19], v[10:11]
s_cbranch_execz .LBB0_12
v_dual_mov_b32 v10, v18 :: v_dual_mov_b32 v11, v19
global_store_b8 v[8:9], v24, off offset:3
s_branch .LBB0_12
.LBB0_19:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelP15HIP_vector_typeIhLj4EEjji
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 28
.amdhsa_next_free_sgpr 32
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelP15HIP_vector_typeIhLj4EEjji, .Lfunc_end0-_Z6kernelP15HIP_vector_typeIhLj4EEjji
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected GPU_AVG
.type GPU_AVG,@object
.section .bss,"aw",@nobits
.globl GPU_AVG
.p2align 4, 0x0
GPU_AVG:
.zero 1200
.size GPU_AVG, 1200
.protected GPU_INVERT_COV
.type GPU_INVERT_COV,@object
.globl GPU_INVERT_COV
.p2align 4, 0x0
GPU_INVERT_COV:
.zero 3600
.size GPU_INVERT_COV, 3600
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym GPU_AVG
.addrsig_sym GPU_INVERT_COV
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelP15HIP_vector_typeIhLj4EEjji
.private_segment_fixed_size: 0
.sgpr_count: 34
.sgpr_spill_count: 0
.symbol: _Z6kernelP15HIP_vector_typeIhLj4EEjji.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 28
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
#include <numeric>
#include <math.h>
using namespace std;
__global__ void min(int* input, int n)
{
const int tid = threadIdx.x; //Index of the thread within the block
int step_size = 1;
int number_of_threads = blockDim.x; //Number of threads in thread block
while (number_of_threads > 0)
{
if (tid < number_of_threads)
{
const int fst = tid * step_size * 2;
const int snd = fst + step_size;
if(snd < n)
{
if(input[snd] < input[fst])
input[fst] = input[snd];
}
}
step_size <<= 1; //1 -> 2, 2 -> 4, 3->6; shift operator
if(number_of_threads == 1)
break;
number_of_threads = (int)ceil((float)number_of_threads/2.0); // divide number of threads by 2
__syncthreads();
}
}
int main()
{
int count;
int result;
int* d;
cout<<"\nEnter the number of elements : ";
cin>>count;
const int size = count * sizeof(int);
//when sizeof() is used with data types it simply returns the
// the amount of memory allocated to that data types
int *h;
h = new int[count];
cout<<"\nEnter the elements : \n";
for(int i=0;i<count;i++)
cin>>h[i];
cudaMalloc(&d, size);
cudaMemcpy(d, h, size, cudaMemcpyHostToDevice);
min <<<1, ceil((float)count/2.0) >>>(d , count);
cudaMemcpy(&result, d, sizeof(int), cudaMemcpyDeviceToHost);
cout << "Min is " << result << endl;
getchar();
cudaFree(d);
delete[] h;
return 0;
}
/*
PS D:\MyFiles\Projects\LP1-LabAsg\1-HPC> nvcc ParRedMin.cu -o ParRedMin
ParRedMin.cu
Creating library ParRedMin.lib and object ParRedMin.exp
PS D:\MyFiles\Projects\LP1-LabAsg\1-HPC> nvprof ./ParRedMin
Enter the number of elements : 4
Enter the elements :
1
2
3
67
==1876== NVPROF is profiling process 1876, command: ./ParRedMin
Min is 1
==1876== Profiling application: ./ParRedMin
==1876== Profiling result:
Type Time(%) Time Calls Avg Min Max Name
GPU activities: 59.68% 2.3680us 1 2.3680us 2.3680us 2.3680us min(int*, int)
25.81% 1.0240us 1 1.0240us 1.0240us 1.0240us [CUDA memcpy HtoD]
14.52% 576ns 1 576ns 576ns 576ns [CUDA memcpy DtoH]
API calls: 79.80% 172.77ms 1 172.77ms 172.77ms 172.77ms cudaMalloc
19.78% 42.826ms 1 42.826ms 42.826ms 42.826ms cuDevicePrimaryCtxRelease
0.13% 271.80us 97 2.8020us 100ns 172.50us cuDeviceGetAttribute
0.11% 245.30us 1 245.30us 245.30us 245.30us cudaLaunchKernel
0.07% 144.50us 1 144.50us 144.50us 144.50us cudaFree
0.05% 106.90us 2 53.450us 25.500us 81.400us cudaMemcpy
0.04% 89.600us 1 89.600us 89.600us 89.600us cuModuleUnload
0.01% 21.400us 1 21.400us 21.400us 21.400us cuDeviceTotalMem
0.00% 9.7000us 1 9.7000us 9.7000us 9.7000us cuDeviceGetPCIBusId
0.00% 1.9000us 3 633ns 200ns 900ns cuDeviceGetCount
0.00% 1.7000us 2 850ns 300ns 1.4000us cuDeviceGet
0.00% 900ns 1 900ns 900ns 900ns cuDeviceGetName
0.00% 300ns 1 300ns 300ns 300ns cuDeviceGetUuid
0.00% 300ns 1 300ns 300ns 300ns cuDeviceGetLuid
*/ | code for sm_80
Function : _Z3minPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0050*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0060*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe40000000000 */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.SHL.U32 R8, R7, 0x2, RZ ; /* 0x0000000207087824 */
/* 0x001fe400078e00ff */
/*0090*/ ISETP.GE.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fe20003f26270 */
/*00a0*/ BSSY B0, 0x190 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*00b0*/ ISETP.NE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fd60003f05270 */
/*00c0*/ @P1 BRA 0x180 ; /* 0x000000b000001947 */
/* 0x000fea0003800000 */
/*00d0*/ IMAD R5, R8, UR4, RZ ; /* 0x0000000408057c24 */
/* 0x000fca000f8e02ff */
/*00e0*/ IADD3 R3, R5, UR4, RZ ; /* 0x0000000405037c10 */
/* 0x000fc8000fffe0ff */
/*00f0*/ ISETP.GE.AND P1, PT, R3, c[0x0][0x168], PT ; /* 0x00005a0003007a0c */
/* 0x000fda0003f26270 */
/*0100*/ @P1 BRA 0x180 ; /* 0x0000007000001947 */
/* 0x000fea0003800000 */
/*0110*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fd400000001ff */
/*0120*/ IMAD.WIDE R2, R3, R4, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fc800078e0204 */
/*0130*/ IMAD.WIDE R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fe400078e0204 */
/*0140*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea8000c1e1900 */
/*0150*/ LDG.E R6, [R4.64] ; /* 0x0000000604067981 */
/* 0x000ea4000c1e1900 */
/*0160*/ ISETP.GE.AND P1, PT, R3, R6, PT ; /* 0x000000060300720c */
/* 0x004fda0003f26270 */
/*0170*/ @!P1 STG.E [R4.64], R3 ; /* 0x0000000304009986 */
/* 0x0001e4000c101906 */
/*0180*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0190*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*01a0*/ I2F R4, R0 ; /* 0x0000000000047306 */
/* 0x001e220000201400 */
/*01b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01c0*/ USHF.L.U32 UR4, UR4, 0x1, URZ ; /* 0x0000000104047899 */
/* 0x000fcc000800063f */
/*01d0*/ F2F.F64.F32 R2, R4 ; /* 0x0000000400027310 */
/* 0x001e240000201800 */
/*01e0*/ DMUL R2, R2, 0.5 ; /* 0x3fe0000002027828 */
/* 0x001e0c0000000000 */
/*01f0*/ F2I.F64.CEIL R0, R2 ; /* 0x0000000200007311 */
/* 0x001e240000309100 */
/*0200*/ ISETP.GT.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x001fda0003f04270 */
/*0210*/ @P0 BRA 0x90 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ BRA 0x230; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
#include <numeric>
#include <math.h>
using namespace std;
__global__ void min(int* input, int n)
{
const int tid = threadIdx.x; //Index of the thread within the block
int step_size = 1;
int number_of_threads = blockDim.x; //Number of threads in thread block
while (number_of_threads > 0)
{
if (tid < number_of_threads)
{
const int fst = tid * step_size * 2;
const int snd = fst + step_size;
if(snd < n)
{
if(input[snd] < input[fst])
input[fst] = input[snd];
}
}
step_size <<= 1; //1 -> 2, 2 -> 4, 3->6; shift operator
if(number_of_threads == 1)
break;
number_of_threads = (int)ceil((float)number_of_threads/2.0); // divide number of threads by 2
__syncthreads();
}
}
int main()
{
int count;
int result;
int* d;
cout<<"\nEnter the number of elements : ";
cin>>count;
const int size = count * sizeof(int);
//when sizeof() is used with data types it simply returns the
// the amount of memory allocated to that data types
int *h;
h = new int[count];
cout<<"\nEnter the elements : \n";
for(int i=0;i<count;i++)
cin>>h[i];
cudaMalloc(&d, size);
cudaMemcpy(d, h, size, cudaMemcpyHostToDevice);
min <<<1, ceil((float)count/2.0) >>>(d , count);
cudaMemcpy(&result, d, sizeof(int), cudaMemcpyDeviceToHost);
cout << "Min is " << result << endl;
getchar();
cudaFree(d);
delete[] h;
return 0;
}
/*
PS D:\MyFiles\Projects\LP1-LabAsg\1-HPC> nvcc ParRedMin.cu -o ParRedMin
ParRedMin.cu
Creating library ParRedMin.lib and object ParRedMin.exp
PS D:\MyFiles\Projects\LP1-LabAsg\1-HPC> nvprof ./ParRedMin
Enter the number of elements : 4
Enter the elements :
1
2
3
67
==1876== NVPROF is profiling process 1876, command: ./ParRedMin
Min is 1
==1876== Profiling application: ./ParRedMin
==1876== Profiling result:
Type Time(%) Time Calls Avg Min Max Name
GPU activities: 59.68% 2.3680us 1 2.3680us 2.3680us 2.3680us min(int*, int)
25.81% 1.0240us 1 1.0240us 1.0240us 1.0240us [CUDA memcpy HtoD]
14.52% 576ns 1 576ns 576ns 576ns [CUDA memcpy DtoH]
API calls: 79.80% 172.77ms 1 172.77ms 172.77ms 172.77ms cudaMalloc
19.78% 42.826ms 1 42.826ms 42.826ms 42.826ms cuDevicePrimaryCtxRelease
0.13% 271.80us 97 2.8020us 100ns 172.50us cuDeviceGetAttribute
0.11% 245.30us 1 245.30us 245.30us 245.30us cudaLaunchKernel
0.07% 144.50us 1 144.50us 144.50us 144.50us cudaFree
0.05% 106.90us 2 53.450us 25.500us 81.400us cudaMemcpy
0.04% 89.600us 1 89.600us 89.600us 89.600us cuModuleUnload
0.01% 21.400us 1 21.400us 21.400us 21.400us cuDeviceTotalMem
0.00% 9.7000us 1 9.7000us 9.7000us 9.7000us cuDeviceGetPCIBusId
0.00% 1.9000us 3 633ns 200ns 900ns cuDeviceGetCount
0.00% 1.7000us 2 850ns 300ns 1.4000us cuDeviceGet
0.00% 900ns 1 900ns 900ns 900ns cuDeviceGetName
0.00% 300ns 1 300ns 300ns 300ns cuDeviceGetUuid
0.00% 300ns 1 300ns 300ns 300ns cuDeviceGetLuid
*/ | .file "tmpxft_00127f6f_00000000-6_ParRedMin.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3711:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3711:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z3minPiiPii
.type _Z23__device_stub__Z3minPiiPii, @function
_Z23__device_stub__Z3minPiiPii:
.LFB3733:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3minPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3733:
.size _Z23__device_stub__Z3minPiiPii, .-_Z23__device_stub__Z3minPiiPii
.globl _Z3minPii
.type _Z3minPii, @function
_Z3minPii:
.LFB3734:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z3minPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3734:
.size _Z3minPii, .-_Z3minPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "\nEnter the number of elements : "
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\nEnter the elements : \n"
.LC6:
.string "Min is "
.text
.globl main
.type main, @function
main:
.LFB3708:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq 4(%rsp), %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSirsERi@PLT
movl 4(%rsp), %ebx
movslq %ebx, %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L12
leal 0(,%rbx,4), %r14d
salq $2, %rdi
call _Znam@PLT
movq %rax, %r13
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %r13, %rbp
movl $0, %ebx
leaq _ZSt3cin(%rip), %r12
cmpl $0, 4(%rsp)
jle .L14
.L16:
movq %rbp, %rsi
movq %r12, %rdi
call _ZNSirsERi@PLT
addl $1, %ebx
addq $4, %rbp
cmpl %ebx, 4(%rsp)
jg .L16
.L14:
movslq %r14d, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtsi2ssl 4(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
mulsd .LC2(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC7(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC3(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L17
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC5(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L17:
cvttsd2siq %xmm3, %rax
movl %eax, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L18:
leaq 28(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 28(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq stdin(%rip), %rdi
call getc@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call _ZdaPv@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
movq 40(%rsp), %rax
subq %fs:40, %rax
je .L15
call __stack_chk_fail@PLT
.L15:
call __cxa_throw_bad_array_new_length@PLT
.L23:
movl 4(%rsp), %esi
movq 8(%rsp), %rdi
call _Z23__device_stub__Z3minPiiPii
jmp .L18
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3708:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z3minPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3736:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z3minPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3736:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1071644672
.align 8
.LC3:
.long 0
.long 1127219200
.align 8
.LC5:
.long 0
.long 1072693248
.align 8
.LC7:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
#include <numeric>
#include <math.h>
using namespace std;
__global__ void min(int* input, int n)
{
const int tid = threadIdx.x; //Index of the thread within the block
int step_size = 1;
int number_of_threads = blockDim.x; //Number of threads in thread block
while (number_of_threads > 0)
{
if (tid < number_of_threads)
{
const int fst = tid * step_size * 2;
const int snd = fst + step_size;
if(snd < n)
{
if(input[snd] < input[fst])
input[fst] = input[snd];
}
}
step_size <<= 1; //1 -> 2, 2 -> 4, 3->6; shift operator
if(number_of_threads == 1)
break;
number_of_threads = (int)ceil((float)number_of_threads/2.0); // divide number of threads by 2
__syncthreads();
}
}
int main()
{
int count;
int result;
int* d;
cout<<"\nEnter the number of elements : ";
cin>>count;
const int size = count * sizeof(int);
//when sizeof() is used with data types it simply returns the
// the amount of memory allocated to that data types
int *h;
h = new int[count];
cout<<"\nEnter the elements : \n";
for(int i=0;i<count;i++)
cin>>h[i];
cudaMalloc(&d, size);
cudaMemcpy(d, h, size, cudaMemcpyHostToDevice);
min <<<1, ceil((float)count/2.0) >>>(d , count);
cudaMemcpy(&result, d, sizeof(int), cudaMemcpyDeviceToHost);
cout << "Min is " << result << endl;
getchar();
cudaFree(d);
delete[] h;
return 0;
}
/*
PS D:\MyFiles\Projects\LP1-LabAsg\1-HPC> nvcc ParRedMin.cu -o ParRedMin
ParRedMin.cu
Creating library ParRedMin.lib and object ParRedMin.exp
PS D:\MyFiles\Projects\LP1-LabAsg\1-HPC> nvprof ./ParRedMin
Enter the number of elements : 4
Enter the elements :
1
2
3
67
==1876== NVPROF is profiling process 1876, command: ./ParRedMin
Min is 1
==1876== Profiling application: ./ParRedMin
==1876== Profiling result:
Type Time(%) Time Calls Avg Min Max Name
GPU activities: 59.68% 2.3680us 1 2.3680us 2.3680us 2.3680us min(int*, int)
25.81% 1.0240us 1 1.0240us 1.0240us 1.0240us [CUDA memcpy HtoD]
14.52% 576ns 1 576ns 576ns 576ns [CUDA memcpy DtoH]
API calls: 79.80% 172.77ms 1 172.77ms 172.77ms 172.77ms cudaMalloc
19.78% 42.826ms 1 42.826ms 42.826ms 42.826ms cuDevicePrimaryCtxRelease
0.13% 271.80us 97 2.8020us 100ns 172.50us cuDeviceGetAttribute
0.11% 245.30us 1 245.30us 245.30us 245.30us cudaLaunchKernel
0.07% 144.50us 1 144.50us 144.50us 144.50us cudaFree
0.05% 106.90us 2 53.450us 25.500us 81.400us cudaMemcpy
0.04% 89.600us 1 89.600us 89.600us 89.600us cuModuleUnload
0.01% 21.400us 1 21.400us 21.400us 21.400us cuDeviceTotalMem
0.00% 9.7000us 1 9.7000us 9.7000us 9.7000us cuDeviceGetPCIBusId
0.00% 1.9000us 3 633ns 200ns 900ns cuDeviceGetCount
0.00% 1.7000us 2 850ns 300ns 1.4000us cuDeviceGet
0.00% 900ns 1 900ns 900ns 900ns cuDeviceGetName
0.00% 300ns 1 300ns 300ns 300ns cuDeviceGetUuid
0.00% 300ns 1 300ns 300ns 300ns cuDeviceGetLuid
*/ | #include "hip/hip_runtime.h"
#include <iostream>
#include <numeric>
#include <math.h>
using namespace std;
__global__ void min(int* input, int n)
{
const int tid = threadIdx.x; //Index of the thread within the block
int step_size = 1;
int number_of_threads = blockDim.x; //Number of threads in thread block
while (number_of_threads > 0)
{
if (tid < number_of_threads)
{
const int fst = tid * step_size * 2;
const int snd = fst + step_size;
if(snd < n)
{
if(input[snd] < input[fst])
input[fst] = input[snd];
}
}
step_size <<= 1; //1 -> 2, 2 -> 4, 3->6; shift operator
if(number_of_threads == 1)
break;
number_of_threads = (int)ceil((float)number_of_threads/2.0); // divide number of threads by 2
__syncthreads();
}
}
int main()
{
int count;
int result;
int* d;
cout<<"\nEnter the number of elements : ";
cin>>count;
const int size = count * sizeof(int);
//when sizeof() is used with data types it simply returns the
// the amount of memory allocated to that data types
int *h;
h = new int[count];
cout<<"\nEnter the elements : \n";
for(int i=0;i<count;i++)
cin>>h[i];
hipMalloc(&d, size);
hipMemcpy(d, h, size, hipMemcpyHostToDevice);
min <<<1, ceil((float)count/2.0) >>>(d , count);
hipMemcpy(&result, d, sizeof(int), hipMemcpyDeviceToHost);
cout << "Min is " << result << endl;
getchar();
hipFree(d);
delete[] h;
return 0;
}
/*
PS D:\MyFiles\Projects\LP1-LabAsg\1-HPC> nvcc ParRedMin.cu -o ParRedMin
ParRedMin.cu
Creating library ParRedMin.lib and object ParRedMin.exp
PS D:\MyFiles\Projects\LP1-LabAsg\1-HPC> nvprof ./ParRedMin
Enter the number of elements : 4
Enter the elements :
1
2
3
67
==1876== NVPROF is profiling process 1876, command: ./ParRedMin
Min is 1
==1876== Profiling application: ./ParRedMin
==1876== Profiling result:
Type Time(%) Time Calls Avg Min Max Name
GPU activities: 59.68% 2.3680us 1 2.3680us 2.3680us 2.3680us min(int*, int)
25.81% 1.0240us 1 1.0240us 1.0240us 1.0240us [CUDA memcpy HtoD]
14.52% 576ns 1 576ns 576ns 576ns [CUDA memcpy DtoH]
API calls: 79.80% 172.77ms 1 172.77ms 172.77ms 172.77ms cudaMalloc
19.78% 42.826ms 1 42.826ms 42.826ms 42.826ms cuDevicePrimaryCtxRelease
0.13% 271.80us 97 2.8020us 100ns 172.50us cuDeviceGetAttribute
0.11% 245.30us 1 245.30us 245.30us 245.30us cudaLaunchKernel
0.07% 144.50us 1 144.50us 144.50us 144.50us cudaFree
0.05% 106.90us 2 53.450us 25.500us 81.400us cudaMemcpy
0.04% 89.600us 1 89.600us 89.600us 89.600us cuModuleUnload
0.01% 21.400us 1 21.400us 21.400us 21.400us cuDeviceTotalMem
0.00% 9.7000us 1 9.7000us 9.7000us 9.7000us cuDeviceGetPCIBusId
0.00% 1.9000us 3 633ns 200ns 900ns cuDeviceGetCount
0.00% 1.7000us 2 850ns 300ns 1.4000us cuDeviceGet
0.00% 900ns 1 900ns 900ns 900ns cuDeviceGetName
0.00% 300ns 1 300ns 300ns 300ns cuDeviceGetUuid
0.00% 300ns 1 300ns 300ns 300ns cuDeviceGetLuid
*/ |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <iostream>
#include <numeric>
#include <math.h>
using namespace std;
__global__ void min(int* input, int n)
{
const int tid = threadIdx.x; //Index of the thread within the block
int step_size = 1;
int number_of_threads = blockDim.x; //Number of threads in thread block
while (number_of_threads > 0)
{
if (tid < number_of_threads)
{
const int fst = tid * step_size * 2;
const int snd = fst + step_size;
if(snd < n)
{
if(input[snd] < input[fst])
input[fst] = input[snd];
}
}
step_size <<= 1; //1 -> 2, 2 -> 4, 3->6; shift operator
if(number_of_threads == 1)
break;
number_of_threads = (int)ceil((float)number_of_threads/2.0); // divide number of threads by 2
__syncthreads();
}
}
int main()
{
int count;
int result;
int* d;
cout<<"\nEnter the number of elements : ";
cin>>count;
const int size = count * sizeof(int);
//when sizeof() is used with data types it simply returns the
// the amount of memory allocated to that data types
int *h;
h = new int[count];
cout<<"\nEnter the elements : \n";
for(int i=0;i<count;i++)
cin>>h[i];
hipMalloc(&d, size);
hipMemcpy(d, h, size, hipMemcpyHostToDevice);
min <<<1, ceil((float)count/2.0) >>>(d , count);
hipMemcpy(&result, d, sizeof(int), hipMemcpyDeviceToHost);
cout << "Min is " << result << endl;
getchar();
hipFree(d);
delete[] h;
return 0;
}
/*
PS D:\MyFiles\Projects\LP1-LabAsg\1-HPC> nvcc ParRedMin.cu -o ParRedMin
ParRedMin.cu
Creating library ParRedMin.lib and object ParRedMin.exp
PS D:\MyFiles\Projects\LP1-LabAsg\1-HPC> nvprof ./ParRedMin
Enter the number of elements : 4
Enter the elements :
1
2
3
67
==1876== NVPROF is profiling process 1876, command: ./ParRedMin
Min is 1
==1876== Profiling application: ./ParRedMin
==1876== Profiling result:
Type Time(%) Time Calls Avg Min Max Name
GPU activities: 59.68% 2.3680us 1 2.3680us 2.3680us 2.3680us min(int*, int)
25.81% 1.0240us 1 1.0240us 1.0240us 1.0240us [CUDA memcpy HtoD]
14.52% 576ns 1 576ns 576ns 576ns [CUDA memcpy DtoH]
API calls: 79.80% 172.77ms 1 172.77ms 172.77ms 172.77ms cudaMalloc
19.78% 42.826ms 1 42.826ms 42.826ms 42.826ms cuDevicePrimaryCtxRelease
0.13% 271.80us 97 2.8020us 100ns 172.50us cuDeviceGetAttribute
0.11% 245.30us 1 245.30us 245.30us 245.30us cudaLaunchKernel
0.07% 144.50us 1 144.50us 144.50us 144.50us cudaFree
0.05% 106.90us 2 53.450us 25.500us 81.400us cudaMemcpy
0.04% 89.600us 1 89.600us 89.600us 89.600us cuModuleUnload
0.01% 21.400us 1 21.400us 21.400us 21.400us cuDeviceTotalMem
0.00% 9.7000us 1 9.7000us 9.7000us 9.7000us cuDeviceGetPCIBusId
0.00% 1.9000us 3 633ns 200ns 900ns cuDeviceGetCount
0.00% 1.7000us 2 850ns 300ns 1.4000us cuDeviceGet
0.00% 900ns 1 900ns 900ns 900ns cuDeviceGetName
0.00% 300ns 1 300ns 300ns 300ns cuDeviceGetUuid
0.00% 300ns 1 300ns 300ns 300ns cuDeviceGetLuid
*/ | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3minPii
.globl _Z3minPii
.p2align 8
.type _Z3minPii,@function
_Z3minPii:
s_load_b32 s4, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
v_cmp_eq_u16_e64 s2, s4, 0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_9
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x8
s_and_b32 s1, 0xffff, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v6, s1 :: v_dual_lshlrev_b32 v5, 1, v0
s_mov_b32 s1, 1
s_branch .LBB0_3
.LBB0_2:
v_cvt_f32_i32_e32 v1, v6
s_lshl_b32 s1, s1, 1
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_cvt_f64_f32_e32 v[1:2], v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[1:2], v[1:2], 0.5
v_ceil_f64_e32 v[1:2], v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_i32_f64_e32 v6, v[1:2]
v_cmp_gt_i32_e64 s4, 1, v6
s_delay_alu instid0(VALU_DEP_1)
s_and_not1_b32 vcc_lo, exec_lo, s4
s_cbranch_vccz .LBB0_9
.LBB0_3:
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_u32_e64 v0, v6
s_cbranch_execz .LBB0_7
v_mul_lo_u32 v1, v5, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, s1, v1
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s0, v3
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v4, v[1:2], off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v3, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
global_store_b32 v[1:2], v3, off
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s4
v_cmp_eq_u32_e32 vcc_lo, 1, v6
s_cbranch_vccz .LBB0_2
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3minPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 5
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3minPii, .Lfunc_end0-_Z3minPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3minPii
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _Z3minPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <iostream>
#include <numeric>
#include <math.h>
using namespace std;
__global__ void min(int* input, int n)
{
const int tid = threadIdx.x; //Index of the thread within the block
int step_size = 1;
int number_of_threads = blockDim.x; //Number of threads in thread block
while (number_of_threads > 0)
{
if (tid < number_of_threads)
{
const int fst = tid * step_size * 2;
const int snd = fst + step_size;
if(snd < n)
{
if(input[snd] < input[fst])
input[fst] = input[snd];
}
}
step_size <<= 1; //1 -> 2, 2 -> 4, 3->6; shift operator
if(number_of_threads == 1)
break;
number_of_threads = (int)ceil((float)number_of_threads/2.0); // divide number of threads by 2
__syncthreads();
}
}
int main()
{
int count;
int result;
int* d;
cout<<"\nEnter the number of elements : ";
cin>>count;
const int size = count * sizeof(int);
//when sizeof() is used with data types it simply returns the
// the amount of memory allocated to that data types
int *h;
h = new int[count];
cout<<"\nEnter the elements : \n";
for(int i=0;i<count;i++)
cin>>h[i];
hipMalloc(&d, size);
hipMemcpy(d, h, size, hipMemcpyHostToDevice);
min <<<1, ceil((float)count/2.0) >>>(d , count);
hipMemcpy(&result, d, sizeof(int), hipMemcpyDeviceToHost);
cout << "Min is " << result << endl;
getchar();
hipFree(d);
delete[] h;
return 0;
}
/*
PS D:\MyFiles\Projects\LP1-LabAsg\1-HPC> nvcc ParRedMin.cu -o ParRedMin
ParRedMin.cu
Creating library ParRedMin.lib and object ParRedMin.exp
PS D:\MyFiles\Projects\LP1-LabAsg\1-HPC> nvprof ./ParRedMin
Enter the number of elements : 4
Enter the elements :
1
2
3
67
==1876== NVPROF is profiling process 1876, command: ./ParRedMin
Min is 1
==1876== Profiling application: ./ParRedMin
==1876== Profiling result:
Type Time(%) Time Calls Avg Min Max Name
GPU activities: 59.68% 2.3680us 1 2.3680us 2.3680us 2.3680us min(int*, int)
25.81% 1.0240us 1 1.0240us 1.0240us 1.0240us [CUDA memcpy HtoD]
14.52% 576ns 1 576ns 576ns 576ns [CUDA memcpy DtoH]
API calls: 79.80% 172.77ms 1 172.77ms 172.77ms 172.77ms cudaMalloc
19.78% 42.826ms 1 42.826ms 42.826ms 42.826ms cuDevicePrimaryCtxRelease
0.13% 271.80us 97 2.8020us 100ns 172.50us cuDeviceGetAttribute
0.11% 245.30us 1 245.30us 245.30us 245.30us cudaLaunchKernel
0.07% 144.50us 1 144.50us 144.50us 144.50us cudaFree
0.05% 106.90us 2 53.450us 25.500us 81.400us cudaMemcpy
0.04% 89.600us 1 89.600us 89.600us 89.600us cuModuleUnload
0.01% 21.400us 1 21.400us 21.400us 21.400us cuDeviceTotalMem
0.00% 9.7000us 1 9.7000us 9.7000us 9.7000us cuDeviceGetPCIBusId
0.00% 1.9000us 3 633ns 200ns 900ns cuDeviceGetCount
0.00% 1.7000us 2 850ns 300ns 1.4000us cuDeviceGet
0.00% 900ns 1 900ns 900ns 900ns cuDeviceGetName
0.00% 300ns 1 300ns 300ns 300ns cuDeviceGetUuid
0.00% 300ns 1 300ns 300ns 300ns cuDeviceGetLuid
*/ | .text
.file "ParRedMin.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__minPii # -- Begin function _Z18__device_stub__minPii
.p2align 4, 0x90
.type _Z18__device_stub__minPii,@function
_Z18__device_stub__minPii: # @_Z18__device_stub__minPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3minPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__minPii, .Lfunc_end0-_Z18__device_stub__minPii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3fe0000000000000 # double 0.5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $104, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $32, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 12(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movslq 12(%rsp), %rax
leal (,%rax,4), %ebp
leaq (,%rax,4), %rcx
testq %rax, %rax
movq $-1, %rdi
cmovnsq %rcx, %rdi
callq _Znam
movq %rax, %rbx
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
cmpl $0, 12(%rsp)
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
xorl %r15d, %r15d
movq %rbx, %r14
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $_ZSt3cin, %edi
movq %r14, %rsi
callq _ZNSirsERi
incq %r15
movslq 12(%rsp), %rax
addq $4, %r14
cmpq %rax, %r15
jl .LBB1_2
.LBB1_3: # %._crit_edge
movslq %ebp, %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
cvtsi2ssl 12(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rax
movl %eax, %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq 16(%rsp), %rax
movl 12(%rsp), %ecx
movq %rax, 96(%rsp)
movl %ecx, 28(%rsp)
leaq 96(%rsp), %rax
movq %rax, 32(%rsp)
leaq 28(%rsp), %rax
movq %rax, 40(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z3minPii, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
movq 16(%rsp), %rsi
leaq 32(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 32(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_10
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB1_8
# %bb.7:
movzbl 67(%r14), %ecx
jmp .LBB1_9
.LBB1_8:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq stdin(%rip), %rdi
callq getc
movq 16(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_10:
.cfi_def_cfa_offset 144
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3minPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3minPii,@object # @_Z3minPii
.section .rodata,"a",@progbits
.globl _Z3minPii
.p2align 3, 0x0
_Z3minPii:
.quad _Z18__device_stub__minPii
.size _Z3minPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nEnter the number of elements : "
.size .L.str, 33
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\nEnter the elements : \n"
.size .L.str.1, 24
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Min is "
.size .L.str.2, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3minPii"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__minPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3minPii
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3minPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0050*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0060*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe40000000000 */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.SHL.U32 R8, R7, 0x2, RZ ; /* 0x0000000207087824 */
/* 0x001fe400078e00ff */
/*0090*/ ISETP.GE.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fe20003f26270 */
/*00a0*/ BSSY B0, 0x190 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*00b0*/ ISETP.NE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fd60003f05270 */
/*00c0*/ @P1 BRA 0x180 ; /* 0x000000b000001947 */
/* 0x000fea0003800000 */
/*00d0*/ IMAD R5, R8, UR4, RZ ; /* 0x0000000408057c24 */
/* 0x000fca000f8e02ff */
/*00e0*/ IADD3 R3, R5, UR4, RZ ; /* 0x0000000405037c10 */
/* 0x000fc8000fffe0ff */
/*00f0*/ ISETP.GE.AND P1, PT, R3, c[0x0][0x168], PT ; /* 0x00005a0003007a0c */
/* 0x000fda0003f26270 */
/*0100*/ @P1 BRA 0x180 ; /* 0x0000007000001947 */
/* 0x000fea0003800000 */
/*0110*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fd400000001ff */
/*0120*/ IMAD.WIDE R2, R3, R4, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fc800078e0204 */
/*0130*/ IMAD.WIDE R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fe400078e0204 */
/*0140*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea8000c1e1900 */
/*0150*/ LDG.E R6, [R4.64] ; /* 0x0000000604067981 */
/* 0x000ea4000c1e1900 */
/*0160*/ ISETP.GE.AND P1, PT, R3, R6, PT ; /* 0x000000060300720c */
/* 0x004fda0003f26270 */
/*0170*/ @!P1 STG.E [R4.64], R3 ; /* 0x0000000304009986 */
/* 0x0001e4000c101906 */
/*0180*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0190*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*01a0*/ I2F R4, R0 ; /* 0x0000000000047306 */
/* 0x001e220000201400 */
/*01b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01c0*/ USHF.L.U32 UR4, UR4, 0x1, URZ ; /* 0x0000000104047899 */
/* 0x000fcc000800063f */
/*01d0*/ F2F.F64.F32 R2, R4 ; /* 0x0000000400027310 */
/* 0x001e240000201800 */
/*01e0*/ DMUL R2, R2, 0.5 ; /* 0x3fe0000002027828 */
/* 0x001e0c0000000000 */
/*01f0*/ F2I.F64.CEIL R0, R2 ; /* 0x0000000200007311 */
/* 0x001e240000309100 */
/*0200*/ ISETP.GT.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x001fda0003f04270 */
/*0210*/ @P0 BRA 0x90 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ BRA 0x230; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3minPii
.globl _Z3minPii
.p2align 8
.type _Z3minPii,@function
_Z3minPii:
s_load_b32 s4, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
v_cmp_eq_u16_e64 s2, s4, 0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_9
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x8
s_and_b32 s1, 0xffff, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v6, s1 :: v_dual_lshlrev_b32 v5, 1, v0
s_mov_b32 s1, 1
s_branch .LBB0_3
.LBB0_2:
v_cvt_f32_i32_e32 v1, v6
s_lshl_b32 s1, s1, 1
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_cvt_f64_f32_e32 v[1:2], v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[1:2], v[1:2], 0.5
v_ceil_f64_e32 v[1:2], v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_i32_f64_e32 v6, v[1:2]
v_cmp_gt_i32_e64 s4, 1, v6
s_delay_alu instid0(VALU_DEP_1)
s_and_not1_b32 vcc_lo, exec_lo, s4
s_cbranch_vccz .LBB0_9
.LBB0_3:
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_u32_e64 v0, v6
s_cbranch_execz .LBB0_7
v_mul_lo_u32 v1, v5, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, s1, v1
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s0, v3
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v4, v[1:2], off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v3, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
global_store_b32 v[1:2], v3, off
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s4
v_cmp_eq_u32_e32 vcc_lo, 1, v6
s_cbranch_vccz .LBB0_2
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3minPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 5
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3minPii, .Lfunc_end0-_Z3minPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3minPii
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _Z3minPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00127f6f_00000000-6_ParRedMin.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3711:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3711:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z3minPiiPii
.type _Z23__device_stub__Z3minPiiPii, @function
_Z23__device_stub__Z3minPiiPii:
.LFB3733:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3minPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3733:
.size _Z23__device_stub__Z3minPiiPii, .-_Z23__device_stub__Z3minPiiPii
.globl _Z3minPii
.type _Z3minPii, @function
_Z3minPii:
.LFB3734:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z3minPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3734:
.size _Z3minPii, .-_Z3minPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "\nEnter the number of elements : "
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\nEnter the elements : \n"
.LC6:
.string "Min is "
.text
.globl main
.type main, @function
main:
.LFB3708:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq 4(%rsp), %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSirsERi@PLT
movl 4(%rsp), %ebx
movslq %ebx, %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L12
leal 0(,%rbx,4), %r14d
salq $2, %rdi
call _Znam@PLT
movq %rax, %r13
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %r13, %rbp
movl $0, %ebx
leaq _ZSt3cin(%rip), %r12
cmpl $0, 4(%rsp)
jle .L14
.L16:
movq %rbp, %rsi
movq %r12, %rdi
call _ZNSirsERi@PLT
addl $1, %ebx
addq $4, %rbp
cmpl %ebx, 4(%rsp)
jg .L16
.L14:
movslq %r14d, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtsi2ssl 4(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
mulsd .LC2(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC7(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC3(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L17
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC5(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L17:
cvttsd2siq %xmm3, %rax
movl %eax, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L18:
leaq 28(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 28(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq stdin(%rip), %rdi
call getc@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call _ZdaPv@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
movq 40(%rsp), %rax
subq %fs:40, %rax
je .L15
call __stack_chk_fail@PLT
.L15:
call __cxa_throw_bad_array_new_length@PLT
.L23:
movl 4(%rsp), %esi
movq 8(%rsp), %rdi
call _Z23__device_stub__Z3minPiiPii
jmp .L18
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3708:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z3minPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3736:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z3minPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3736:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1071644672
.align 8
.LC3:
.long 0
.long 1127219200
.align 8
.LC5:
.long 0
.long 1072693248
.align 8
.LC7:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ParRedMin.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__minPii # -- Begin function _Z18__device_stub__minPii
.p2align 4, 0x90
.type _Z18__device_stub__minPii,@function
_Z18__device_stub__minPii: # @_Z18__device_stub__minPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3minPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__minPii, .Lfunc_end0-_Z18__device_stub__minPii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3fe0000000000000 # double 0.5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $104, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $32, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 12(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movslq 12(%rsp), %rax
leal (,%rax,4), %ebp
leaq (,%rax,4), %rcx
testq %rax, %rax
movq $-1, %rdi
cmovnsq %rcx, %rdi
callq _Znam
movq %rax, %rbx
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
cmpl $0, 12(%rsp)
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
xorl %r15d, %r15d
movq %rbx, %r14
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $_ZSt3cin, %edi
movq %r14, %rsi
callq _ZNSirsERi
incq %r15
movslq 12(%rsp), %rax
addq $4, %r14
cmpq %rax, %r15
jl .LBB1_2
.LBB1_3: # %._crit_edge
movslq %ebp, %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
cvtsi2ssl 12(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rax
movl %eax, %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq 16(%rsp), %rax
movl 12(%rsp), %ecx
movq %rax, 96(%rsp)
movl %ecx, 28(%rsp)
leaq 96(%rsp), %rax
movq %rax, 32(%rsp)
leaq 28(%rsp), %rax
movq %rax, 40(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z3minPii, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
movq 16(%rsp), %rsi
leaq 32(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 32(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_10
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB1_8
# %bb.7:
movzbl 67(%r14), %ecx
jmp .LBB1_9
.LBB1_8:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq stdin(%rip), %rdi
callq getc
movq 16(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_10:
.cfi_def_cfa_offset 144
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3minPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3minPii,@object # @_Z3minPii
.section .rodata,"a",@progbits
.globl _Z3minPii
.p2align 3, 0x0
_Z3minPii:
.quad _Z18__device_stub__minPii
.size _Z3minPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nEnter the number of elements : "
.size .L.str, 33
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\nEnter the elements : \n"
.size .L.str.1, 24
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Min is "
.size .L.str.2, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3minPii"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__minPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3minPii
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <chrono>
using namespace std::chrono;
using namespace std;
#define n (1 << 2)
__global__ void matrix_multiplication_kernel(int *d_a, int *d_b, int *d_c){
int i = blockIdx.y * blockDim.y + threadIdx.y;
int j = blockIdx.x * blockDim.x + threadIdx.x;
if(i >= n || j >= n) return;
d_c[i*n + j] = 0;
for(int k=0; k<n; k++){
d_c[i*n+j] += d_a[i*n+k] * d_b[k*n+j];
}
}
int main(){
size_t bytes = n*n*sizeof(int);
int *h_a, *h_b, *h_c;
h_a = (int*)malloc(bytes);
h_b = (int*)malloc(bytes);
h_c = (int*)malloc(bytes);
for(int i = 0; i < n*n; i++){
h_a[i] = i;
h_b[i] = i;
}
// for(int i = 0; i < n; i++){
// for(int j=0; j<n; j++){
// cout << h_a[i*n + j] << "\t";
// }
// cout << endl;
// }
// cout << "*" << endl;
// for(int i = 0; i < n; i++){
// for(int j=0; j<n; j++){
// cout << h_b[i*n + j] << "\t";
// }
// cout << endl;
// }
cout << "cpu: " << endl;
auto start = high_resolution_clock::now();
for(int i=0; i<n; i++){
for(int j=0; j<n; j++){
h_c[i*n + j] = 0;
for(int k=0; k<n; k++){
h_c[i*n+j] += h_a[i*n+k] * h_b[k*n+j];
}
}
}
auto stop = high_resolution_clock::now();
auto duration = duration_cast<microseconds>(stop - start);
cout << "cpu time: " << duration.count() << endl;
// for(int i = 0; i < n; i++){
// for(int j=0; j<n; j++){
// cout << h_c[i*n + j] << "\t";
// }
// cout << endl;
// }
cout << "gpu: " << endl;
start = high_resolution_clock::now();
int *h_d = (int*)malloc(bytes);
int *d_a, *d_b, *d_d;
cudaMalloc((void**) &d_a, bytes);
cudaMalloc((void**) &d_b, bytes);
cudaMalloc((void**) &d_d, bytes);
cudaMemcpy(d_a, h_a, bytes, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, bytes, cudaMemcpyHostToDevice);
int BLOCK_SIZE = 32;
int GRID_SIZE = (n/BLOCK_SIZE) + 1;
dim3 grid(GRID_SIZE, GRID_SIZE);
dim3 block(BLOCK_SIZE, BLOCK_SIZE);
matrix_multiplication_kernel<<<grid,block>>>(d_a,d_b,d_d);
cudaDeviceSynchronize();
cudaMemcpy(h_d, d_d, bytes, cudaMemcpyDeviceToHost);
for(int i = 0; i < n; i++){
for(int j=0; j<n; j++){
cout << h_d[i*n + j] << "\t";
}
cout << endl;
}
stop = high_resolution_clock::now();
duration = duration_cast<microseconds>(stop - start);
cout << "gpu time: " << duration.count() << endl;
bool error_occurred = false;
for(int i = 0; i < n; i++){
for(int j=0; j<n; j++){
if(h_d[i*n + j] - h_c[i*n + j] != 0){
cout << "Some error occurred" <<endl;
error_occurred = true;
}
}
}
if(error_occurred == false) cout << "No error" <<endl;
} | code for sm_80
Function : _Z28matrix_multiplication_kernelPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0030*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R5 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GT.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GT.OR P0, PT, R0, 0x3, P0 ; /* 0x000000030000780c */
/* 0x000fda0000704670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*00b0*/ SHF.L.U32 R5, R0, 0x2, RZ ; /* 0x0000000200057819 */
/* 0x000fe200000006ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00d0*/ IADD3 R2, R6, R5, RZ ; /* 0x0000000506027210 */
/* 0x000fca0007ffe0ff */
/*00e0*/ IMAD.WIDE R2, R2, R9, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fc800078e0209 */
/*00f0*/ IMAD.WIDE R6, R6, R9.reuse, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x080fe200078e0209 */
/*0100*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe6000c101904 */
/*0110*/ IMAD.WIDE R4, R5, R9, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fe200078e0209 */
/*0120*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */
/* 0x000ea8000c1e1900 */
/*0130*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea4000c1e1900 */
/*0140*/ IMAD R9, R0, R9, RZ ; /* 0x0000000900097224 */
/* 0x004fca00078e02ff */
/*0150*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*0160*/ LDG.E R0, [R6.64+0x10] ; /* 0x0000100406007981 */
/* 0x000ea8000c1e1900 */
/*0170*/ LDG.E R8, [R4.64+0x4] ; /* 0x0000040404087981 */
/* 0x000ea4000c1e1900 */
/*0180*/ IMAD R11, R0, R8, R9 ; /* 0x00000008000b7224 */
/* 0x004fca00078e0209 */
/*0190*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe8000c101904 */
/*01a0*/ LDG.E R0, [R6.64+0x20] ; /* 0x0000200406007981 */
/* 0x000ea8000c1e1900 */
/*01b0*/ LDG.E R8, [R4.64+0x8] ; /* 0x0000080404087981 */
/* 0x000ea4000c1e1900 */
/*01c0*/ IMAD R13, R0, R8, R11 ; /* 0x00000008000d7224 */
/* 0x004fca00078e020b */
/*01d0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x000fe8000c101904 */
/*01e0*/ LDG.E R0, [R6.64+0x30] ; /* 0x0000300406007981 */
/* 0x000e28000c1e1900 */
/*01f0*/ LDG.E R8, [R4.64+0xc] ; /* 0x00000c0404087981 */
/* 0x000e24000c1e1900 */
/*0200*/ IMAD R9, R0, R8, R13 ; /* 0x0000000800097224 */
/* 0x001fca00078e020d */
/*0210*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ BRA 0x230; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <chrono>
using namespace std::chrono;
using namespace std;
#define n (1 << 2)
__global__ void matrix_multiplication_kernel(int *d_a, int *d_b, int *d_c){
int i = blockIdx.y * blockDim.y + threadIdx.y;
int j = blockIdx.x * blockDim.x + threadIdx.x;
if(i >= n || j >= n) return;
d_c[i*n + j] = 0;
for(int k=0; k<n; k++){
d_c[i*n+j] += d_a[i*n+k] * d_b[k*n+j];
}
}
int main(){
size_t bytes = n*n*sizeof(int);
int *h_a, *h_b, *h_c;
h_a = (int*)malloc(bytes);
h_b = (int*)malloc(bytes);
h_c = (int*)malloc(bytes);
for(int i = 0; i < n*n; i++){
h_a[i] = i;
h_b[i] = i;
}
// for(int i = 0; i < n; i++){
// for(int j=0; j<n; j++){
// cout << h_a[i*n + j] << "\t";
// }
// cout << endl;
// }
// cout << "*" << endl;
// for(int i = 0; i < n; i++){
// for(int j=0; j<n; j++){
// cout << h_b[i*n + j] << "\t";
// }
// cout << endl;
// }
cout << "cpu: " << endl;
auto start = high_resolution_clock::now();
for(int i=0; i<n; i++){
for(int j=0; j<n; j++){
h_c[i*n + j] = 0;
for(int k=0; k<n; k++){
h_c[i*n+j] += h_a[i*n+k] * h_b[k*n+j];
}
}
}
auto stop = high_resolution_clock::now();
auto duration = duration_cast<microseconds>(stop - start);
cout << "cpu time: " << duration.count() << endl;
// for(int i = 0; i < n; i++){
// for(int j=0; j<n; j++){
// cout << h_c[i*n + j] << "\t";
// }
// cout << endl;
// }
cout << "gpu: " << endl;
start = high_resolution_clock::now();
int *h_d = (int*)malloc(bytes);
int *d_a, *d_b, *d_d;
cudaMalloc((void**) &d_a, bytes);
cudaMalloc((void**) &d_b, bytes);
cudaMalloc((void**) &d_d, bytes);
cudaMemcpy(d_a, h_a, bytes, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, bytes, cudaMemcpyHostToDevice);
int BLOCK_SIZE = 32;
int GRID_SIZE = (n/BLOCK_SIZE) + 1;
dim3 grid(GRID_SIZE, GRID_SIZE);
dim3 block(BLOCK_SIZE, BLOCK_SIZE);
matrix_multiplication_kernel<<<grid,block>>>(d_a,d_b,d_d);
cudaDeviceSynchronize();
cudaMemcpy(h_d, d_d, bytes, cudaMemcpyDeviceToHost);
for(int i = 0; i < n; i++){
for(int j=0; j<n; j++){
cout << h_d[i*n + j] << "\t";
}
cout << endl;
}
stop = high_resolution_clock::now();
duration = duration_cast<microseconds>(stop - start);
cout << "gpu time: " << duration.count() << endl;
bool error_occurred = false;
for(int i = 0; i < n; i++){
for(int j=0; j<n; j++){
if(h_d[i*n + j] - h_c[i*n + j] != 0){
cout << "Some error occurred" <<endl;
error_occurred = true;
}
}
}
if(error_occurred == false) cout << "No error" <<endl;
} | .file "tmpxft_0004fad7_00000000-6_matrix_multiplication.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3774:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3774:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z52__device_stub__Z28matrix_multiplication_kernelPiS_S_PiS_S_
.type _Z52__device_stub__Z28matrix_multiplication_kernelPiS_S_PiS_S_, @function
_Z52__device_stub__Z28matrix_multiplication_kernelPiS_S_PiS_S_:
.LFB3796:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z28matrix_multiplication_kernelPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3796:
.size _Z52__device_stub__Z28matrix_multiplication_kernelPiS_S_PiS_S_, .-_Z52__device_stub__Z28matrix_multiplication_kernelPiS_S_PiS_S_
.globl _Z28matrix_multiplication_kernelPiS_S_
.type _Z28matrix_multiplication_kernelPiS_S_, @function
_Z28matrix_multiplication_kernelPiS_S_:
.LFB3797:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z28matrix_multiplication_kernelPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3797:
.size _Z28matrix_multiplication_kernelPiS_S_, .-_Z28matrix_multiplication_kernelPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "cpu: "
.LC1:
.string "cpu time: "
.LC2:
.string "gpu: "
.LC3:
.string "\t"
.LC4:
.string "gpu time: "
.LC5:
.string "Some error occurred"
.LC6:
.string "No error"
.text
.globl main
.type main, @function
main:
.LFB3768:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $64, %edi
call malloc@PLT
movq %rax, %r12
movl $64, %edi
call malloc@PLT
movq %rax, %rbx
movl $64, %edi
call malloc@PLT
movq %rax, %r14
movl $0, %eax
.L12:
movl %eax, (%r12,%rax,4)
movl %eax, (%rbx,%rax,4)
addq $1, %rax
cmpq $16, %rax
jne .L12
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbp
movq %r12, %r11
movq %r14, %r13
movl $0, %r15d
.L13:
leaq 64(%rbx), %rdi
movq %r14, %r9
movl $0, %r8d
.L15:
movq %r9, %r10
leaq -64(%rdi), %rax
movq %r11, %rcx
movl $0, %esi
.L14:
movl (%rcx), %edx
imull (%rax), %edx
addl %edx, %esi
addq $4, %rcx
addq $16, %rax
cmpq %rdi, %rax
jne .L14
movl %esi, (%r10)
addl $1, %r8d
addq $4, %r9
addq $4, %rdi
cmpl $4, %r8d
jne .L15
addq $16, %r11
addl $4, %r15d
addq $16, %r14
cmpl $16, %r15d
jne .L13
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %rbp, %rax
movq %rax, %rcx
movabsq $2361183241434822607, %rdx
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
subq %rcx, %rdx
movq %rdx, %rbp
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %r14
movq %r14, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC2(%rip), %rsi
movq %r14, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, 8(%rsp)
movl $64, %edi
call malloc@PLT
movq %rax, %rbp
leaq 24(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $64, %edx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $64, %edx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $32, 60(%rsp)
movl $32, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L41
.L17:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $64, %edx
movq 40(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq %rbp, %r14
addq $16, %rbp
movl $0, 4(%rsp)
leaq _ZSt4cout(%rip), %r12
leaq .LC3(%rip), %r15
jmp .L18
.L41:
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z52__device_stub__Z28matrix_multiplication_kernelPiS_S_PiS_S_
jmp .L17
.L43:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L42
call _ZSt16__throw_bad_castv@PLT
.L42:
call __stack_chk_fail@PLT
.L22:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
.L23:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $4, 4(%rsp)
movl 4(%rsp), %eax
addq $16, %rbp
cmpl $16, %eax
je .L24
.L18:
leaq -16(%rbp), %rbx
.L19:
movl (%rbx), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r15, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L19
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %rbx
testq %rbx, %rbx
je .L43
cmpb $0, 56(%rbx)
je .L22
movzbl 67(%rbx), %esi
jmp .L23
.L24:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq 8(%rsp), %rbx
subq %rbx, %rax
movq %rax, %rcx
movabsq $2361183241434822607, %rdx
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
movq %rdx, %rbx
subq %rcx, %rbx
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %r15d
movl $0, %eax
leaq _ZSt4cout(%rip), %r12
jmp .L25
.L46:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L44
call _ZSt16__throw_bad_castv@PLT
.L44:
call __stack_chk_fail@PLT
.L29:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
.L30:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $1, %eax
.L26:
addq $4, %rbx
cmpq $16, %rbx
je .L45
.L31:
movl 0(%r13,%rbx), %ecx
cmpl %ecx, (%r14,%rbx)
je .L26
movl $19, %edx
leaq .LC5(%rip), %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %rbp
testq %rbp, %rbp
je .L46
cmpb $0, 56(%rbp)
je .L29
movzbl 67(%rbp), %esi
jmp .L30
.L45:
addl $4, %r15d
addq $16, %r14
addq $16, %r13
cmpl $16, %r15d
je .L32
.L25:
movl $0, %ebx
jmp .L31
.L32:
testb %al, %al
je .L47
.L33:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L48
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L33
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3768:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "_Z28matrix_multiplication_kernelPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3799:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z28matrix_multiplication_kernelPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3799:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <chrono>
using namespace std::chrono;
using namespace std;
#define n (1 << 2)
__global__ void matrix_multiplication_kernel(int *d_a, int *d_b, int *d_c){
int i = blockIdx.y * blockDim.y + threadIdx.y;
int j = blockIdx.x * blockDim.x + threadIdx.x;
if(i >= n || j >= n) return;
d_c[i*n + j] = 0;
for(int k=0; k<n; k++){
d_c[i*n+j] += d_a[i*n+k] * d_b[k*n+j];
}
}
int main(){
size_t bytes = n*n*sizeof(int);
int *h_a, *h_b, *h_c;
h_a = (int*)malloc(bytes);
h_b = (int*)malloc(bytes);
h_c = (int*)malloc(bytes);
for(int i = 0; i < n*n; i++){
h_a[i] = i;
h_b[i] = i;
}
// for(int i = 0; i < n; i++){
// for(int j=0; j<n; j++){
// cout << h_a[i*n + j] << "\t";
// }
// cout << endl;
// }
// cout << "*" << endl;
// for(int i = 0; i < n; i++){
// for(int j=0; j<n; j++){
// cout << h_b[i*n + j] << "\t";
// }
// cout << endl;
// }
cout << "cpu: " << endl;
auto start = high_resolution_clock::now();
for(int i=0; i<n; i++){
for(int j=0; j<n; j++){
h_c[i*n + j] = 0;
for(int k=0; k<n; k++){
h_c[i*n+j] += h_a[i*n+k] * h_b[k*n+j];
}
}
}
auto stop = high_resolution_clock::now();
auto duration = duration_cast<microseconds>(stop - start);
cout << "cpu time: " << duration.count() << endl;
// for(int i = 0; i < n; i++){
// for(int j=0; j<n; j++){
// cout << h_c[i*n + j] << "\t";
// }
// cout << endl;
// }
cout << "gpu: " << endl;
start = high_resolution_clock::now();
int *h_d = (int*)malloc(bytes);
int *d_a, *d_b, *d_d;
cudaMalloc((void**) &d_a, bytes);
cudaMalloc((void**) &d_b, bytes);
cudaMalloc((void**) &d_d, bytes);
cudaMemcpy(d_a, h_a, bytes, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, bytes, cudaMemcpyHostToDevice);
int BLOCK_SIZE = 32;
int GRID_SIZE = (n/BLOCK_SIZE) + 1;
dim3 grid(GRID_SIZE, GRID_SIZE);
dim3 block(BLOCK_SIZE, BLOCK_SIZE);
matrix_multiplication_kernel<<<grid,block>>>(d_a,d_b,d_d);
cudaDeviceSynchronize();
cudaMemcpy(h_d, d_d, bytes, cudaMemcpyDeviceToHost);
for(int i = 0; i < n; i++){
for(int j=0; j<n; j++){
cout << h_d[i*n + j] << "\t";
}
cout << endl;
}
stop = high_resolution_clock::now();
duration = duration_cast<microseconds>(stop - start);
cout << "gpu time: " << duration.count() << endl;
bool error_occurred = false;
for(int i = 0; i < n; i++){
for(int j=0; j<n; j++){
if(h_d[i*n + j] - h_c[i*n + j] != 0){
cout << "Some error occurred" <<endl;
error_occurred = true;
}
}
}
if(error_occurred == false) cout << "No error" <<endl;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <chrono>
using namespace std::chrono;
using namespace std;
#define n (1 << 2)
__global__ void matrix_multiplication_kernel(int *d_a, int *d_b, int *d_c){
int i = blockIdx.y * blockDim.y + threadIdx.y;
int j = blockIdx.x * blockDim.x + threadIdx.x;
if(i >= n || j >= n) return;
d_c[i*n + j] = 0;
for(int k=0; k<n; k++){
d_c[i*n+j] += d_a[i*n+k] * d_b[k*n+j];
}
}
int main(){
size_t bytes = n*n*sizeof(int);
int *h_a, *h_b, *h_c;
h_a = (int*)malloc(bytes);
h_b = (int*)malloc(bytes);
h_c = (int*)malloc(bytes);
for(int i = 0; i < n*n; i++){
h_a[i] = i;
h_b[i] = i;
}
// for(int i = 0; i < n; i++){
// for(int j=0; j<n; j++){
// cout << h_a[i*n + j] << "\t";
// }
// cout << endl;
// }
// cout << "*" << endl;
// for(int i = 0; i < n; i++){
// for(int j=0; j<n; j++){
// cout << h_b[i*n + j] << "\t";
// }
// cout << endl;
// }
cout << "cpu: " << endl;
auto start = high_resolution_clock::now();
for(int i=0; i<n; i++){
for(int j=0; j<n; j++){
h_c[i*n + j] = 0;
for(int k=0; k<n; k++){
h_c[i*n+j] += h_a[i*n+k] * h_b[k*n+j];
}
}
}
auto stop = high_resolution_clock::now();
auto duration = duration_cast<microseconds>(stop - start);
cout << "cpu time: " << duration.count() << endl;
// for(int i = 0; i < n; i++){
// for(int j=0; j<n; j++){
// cout << h_c[i*n + j] << "\t";
// }
// cout << endl;
// }
cout << "gpu: " << endl;
start = high_resolution_clock::now();
int *h_d = (int*)malloc(bytes);
int *d_a, *d_b, *d_d;
hipMalloc((void**) &d_a, bytes);
hipMalloc((void**) &d_b, bytes);
hipMalloc((void**) &d_d, bytes);
hipMemcpy(d_a, h_a, bytes, hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, bytes, hipMemcpyHostToDevice);
int BLOCK_SIZE = 32;
int GRID_SIZE = (n/BLOCK_SIZE) + 1;
dim3 grid(GRID_SIZE, GRID_SIZE);
dim3 block(BLOCK_SIZE, BLOCK_SIZE);
matrix_multiplication_kernel<<<grid,block>>>(d_a,d_b,d_d);
hipDeviceSynchronize();
hipMemcpy(h_d, d_d, bytes, hipMemcpyDeviceToHost);
for(int i = 0; i < n; i++){
for(int j=0; j<n; j++){
cout << h_d[i*n + j] << "\t";
}
cout << endl;
}
stop = high_resolution_clock::now();
duration = duration_cast<microseconds>(stop - start);
cout << "gpu time: " << duration.count() << endl;
bool error_occurred = false;
for(int i = 0; i < n; i++){
for(int j=0; j<n; j++){
if(h_d[i*n + j] - h_c[i*n + j] != 0){
cout << "Some error occurred" <<endl;
error_occurred = true;
}
}
}
if(error_occurred == false) cout << "No error" <<endl;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <chrono>
using namespace std::chrono;
using namespace std;
#define n (1 << 2)
__global__ void matrix_multiplication_kernel(int *d_a, int *d_b, int *d_c){
int i = blockIdx.y * blockDim.y + threadIdx.y;
int j = blockIdx.x * blockDim.x + threadIdx.x;
if(i >= n || j >= n) return;
d_c[i*n + j] = 0;
for(int k=0; k<n; k++){
d_c[i*n+j] += d_a[i*n+k] * d_b[k*n+j];
}
}
int main(){
size_t bytes = n*n*sizeof(int);
int *h_a, *h_b, *h_c;
h_a = (int*)malloc(bytes);
h_b = (int*)malloc(bytes);
h_c = (int*)malloc(bytes);
for(int i = 0; i < n*n; i++){
h_a[i] = i;
h_b[i] = i;
}
// for(int i = 0; i < n; i++){
// for(int j=0; j<n; j++){
// cout << h_a[i*n + j] << "\t";
// }
// cout << endl;
// }
// cout << "*" << endl;
// for(int i = 0; i < n; i++){
// for(int j=0; j<n; j++){
// cout << h_b[i*n + j] << "\t";
// }
// cout << endl;
// }
cout << "cpu: " << endl;
auto start = high_resolution_clock::now();
for(int i=0; i<n; i++){
for(int j=0; j<n; j++){
h_c[i*n + j] = 0;
for(int k=0; k<n; k++){
h_c[i*n+j] += h_a[i*n+k] * h_b[k*n+j];
}
}
}
auto stop = high_resolution_clock::now();
auto duration = duration_cast<microseconds>(stop - start);
cout << "cpu time: " << duration.count() << endl;
// for(int i = 0; i < n; i++){
// for(int j=0; j<n; j++){
// cout << h_c[i*n + j] << "\t";
// }
// cout << endl;
// }
cout << "gpu: " << endl;
start = high_resolution_clock::now();
int *h_d = (int*)malloc(bytes);
int *d_a, *d_b, *d_d;
hipMalloc((void**) &d_a, bytes);
hipMalloc((void**) &d_b, bytes);
hipMalloc((void**) &d_d, bytes);
hipMemcpy(d_a, h_a, bytes, hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, bytes, hipMemcpyHostToDevice);
int BLOCK_SIZE = 32;
int GRID_SIZE = (n/BLOCK_SIZE) + 1;
dim3 grid(GRID_SIZE, GRID_SIZE);
dim3 block(BLOCK_SIZE, BLOCK_SIZE);
matrix_multiplication_kernel<<<grid,block>>>(d_a,d_b,d_d);
hipDeviceSynchronize();
hipMemcpy(h_d, d_d, bytes, hipMemcpyDeviceToHost);
for(int i = 0; i < n; i++){
for(int j=0; j<n; j++){
cout << h_d[i*n + j] << "\t";
}
cout << endl;
}
stop = high_resolution_clock::now();
duration = duration_cast<microseconds>(stop - start);
cout << "gpu time: " << duration.count() << endl;
bool error_occurred = false;
for(int i = 0; i < n; i++){
for(int j=0; j<n; j++){
if(h_d[i*n + j] - h_c[i*n + j] != 0){
cout << "Some error occurred" <<endl;
error_occurred = true;
}
}
}
if(error_occurred == false) cout << "No error" <<endl;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z28matrix_multiplication_kernelPiS_S_
.globl _Z28matrix_multiplication_kernelPiS_S_
.p2align 8
.type _Z28matrix_multiplication_kernelPiS_S_,@function
_Z28matrix_multiplication_kernelPiS_S_:
s_load_b32 s2, s[0:1], 0x24
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
v_mad_u64_u32 v[0:1], null, s14, s2, v[4:5]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v1, v2, v0
v_cmpx_gt_i32_e32 4, v1
s_cbranch_execz .LBB0_3
v_lshlrev_b32_e32 v1, 2, v2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, v1, v0
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[1:2]
v_lshlrev_b64 v[4:5], 2, v[3:4]
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v1, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v7, vcc_lo
s_mov_b64 s[0:1], 0
global_store_b32 v[1:2], v3, off
.p2align 6
.LBB0_2:
v_add_nc_u32_e32 v6, s0, v0
v_add_co_u32 v8, vcc_lo, v4, s0
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s0, 16
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_load_b32 v8, v[8:9], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[6:7], null, v9, v8, v[3:4]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v3, v6
global_store_b32 v[1:2], v6, off
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z28matrix_multiplication_kernelPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z28matrix_multiplication_kernelPiS_S_, .Lfunc_end0-_Z28matrix_multiplication_kernelPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z28matrix_multiplication_kernelPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z28matrix_multiplication_kernelPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <chrono>
using namespace std::chrono;
using namespace std;
#define n (1 << 2)
__global__ void matrix_multiplication_kernel(int *d_a, int *d_b, int *d_c){
int i = blockIdx.y * blockDim.y + threadIdx.y;
int j = blockIdx.x * blockDim.x + threadIdx.x;
if(i >= n || j >= n) return;
d_c[i*n + j] = 0;
for(int k=0; k<n; k++){
d_c[i*n+j] += d_a[i*n+k] * d_b[k*n+j];
}
}
int main(){
size_t bytes = n*n*sizeof(int);
int *h_a, *h_b, *h_c;
h_a = (int*)malloc(bytes);
h_b = (int*)malloc(bytes);
h_c = (int*)malloc(bytes);
for(int i = 0; i < n*n; i++){
h_a[i] = i;
h_b[i] = i;
}
// for(int i = 0; i < n; i++){
// for(int j=0; j<n; j++){
// cout << h_a[i*n + j] << "\t";
// }
// cout << endl;
// }
// cout << "*" << endl;
// for(int i = 0; i < n; i++){
// for(int j=0; j<n; j++){
// cout << h_b[i*n + j] << "\t";
// }
// cout << endl;
// }
cout << "cpu: " << endl;
auto start = high_resolution_clock::now();
for(int i=0; i<n; i++){
for(int j=0; j<n; j++){
h_c[i*n + j] = 0;
for(int k=0; k<n; k++){
h_c[i*n+j] += h_a[i*n+k] * h_b[k*n+j];
}
}
}
auto stop = high_resolution_clock::now();
auto duration = duration_cast<microseconds>(stop - start);
cout << "cpu time: " << duration.count() << endl;
// for(int i = 0; i < n; i++){
// for(int j=0; j<n; j++){
// cout << h_c[i*n + j] << "\t";
// }
// cout << endl;
// }
cout << "gpu: " << endl;
start = high_resolution_clock::now();
int *h_d = (int*)malloc(bytes);
int *d_a, *d_b, *d_d;
hipMalloc((void**) &d_a, bytes);
hipMalloc((void**) &d_b, bytes);
hipMalloc((void**) &d_d, bytes);
hipMemcpy(d_a, h_a, bytes, hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, bytes, hipMemcpyHostToDevice);
int BLOCK_SIZE = 32;
int GRID_SIZE = (n/BLOCK_SIZE) + 1;
dim3 grid(GRID_SIZE, GRID_SIZE);
dim3 block(BLOCK_SIZE, BLOCK_SIZE);
matrix_multiplication_kernel<<<grid,block>>>(d_a,d_b,d_d);
hipDeviceSynchronize();
hipMemcpy(h_d, d_d, bytes, hipMemcpyDeviceToHost);
for(int i = 0; i < n; i++){
for(int j=0; j<n; j++){
cout << h_d[i*n + j] << "\t";
}
cout << endl;
}
stop = high_resolution_clock::now();
duration = duration_cast<microseconds>(stop - start);
cout << "gpu time: " << duration.count() << endl;
bool error_occurred = false;
for(int i = 0; i < n; i++){
for(int j=0; j<n; j++){
if(h_d[i*n + j] - h_c[i*n + j] != 0){
cout << "Some error occurred" <<endl;
error_occurred = true;
}
}
}
if(error_occurred == false) cout << "No error" <<endl;
} | .text
.file "matrix_multiplication.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z43__device_stub__matrix_multiplication_kernelPiS_S_ # -- Begin function _Z43__device_stub__matrix_multiplication_kernelPiS_S_
.p2align 4, 0x90
.type _Z43__device_stub__matrix_multiplication_kernelPiS_S_,@function
_Z43__device_stub__matrix_multiplication_kernelPiS_S_: # @_Z43__device_stub__matrix_multiplication_kernelPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z28matrix_multiplication_kernelPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z43__device_stub__matrix_multiplication_kernelPiS_S_, .Lfunc_end0-_Z43__device_stub__matrix_multiplication_kernelPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $64, %edi
callq malloc
movq %rax, %r12
movl $64, %edi
callq malloc
movq %rax, %r15
movl $64, %edi
callq malloc
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%r12,%rax,4)
movl %eax, (%r15,%rax,4)
incq %rax
cmpq $16, %rax
jne .LBB1_1
# %bb.2:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB1_51
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB1_5
# %bb.4:
movzbl 67(%r14), %eax
jmp .LBB1_6
.LBB1_5:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r13d, %r13d
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r14
movq %r12, %rax
.p2align 4, 0x90
.LBB1_7: # %.preheader123
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
# Child Loop BB1_9 Depth 3
leaq (,%r13,4), %rcx
movq %r15, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_8: # Parent Loop BB1_7 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_9 Depth 3
movq %rsi, %rdi
orq %rcx, %rdi
movl $0, (%rbx,%rdi,4)
xorl %r8d, %r8d
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB1_9: # Parent Loop BB1_7 Depth=1
# Parent Loop BB1_8 Depth=2
# => This Inner Loop Header: Depth=3
movl (%rdx,%r8,4), %r10d
imull (%rax,%r8), %r10d
addl %r10d, %r9d
addq $4, %r8
cmpq $16, %r8
jne .LBB1_9
# %bb.10: # in Loop: Header=BB1_8 Depth=2
movl %r9d, (%rbx,%rdi,4)
incq %rsi
addq $4, %rdx
cmpq $4, %rsi
jne .LBB1_8
# %bb.11: # in Loop: Header=BB1_7 Depth=1
incq %r13
addq $16, %rax
cmpq $4, %r13
jne .LBB1_7
# %bb.12:
callq _ZNSt6chrono3_V212system_clock3nowEv
subq %r14, %rax
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
imulq %rcx
movq %rdx, %r14
shrq $63, %r14
sarq $7, %rdx
addq %rdx, %r14
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movq %r14, %rsi
callq _ZNSo9_M_insertIlEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_51
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i83
cmpb $0, 56(%r14)
je .LBB1_15
# %bb.14:
movzbl 67(%r14), %ecx
jmp .LBB1_16
.LBB1_15:
movq %r14, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB1_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit86
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB1_51
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i88
cmpb $0, 56(%r14)
je .LBB1_19
# %bb.18:
movzbl 67(%r14), %eax
jmp .LBB1_20
.LBB1_19:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit91
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r13
movl $64, %edi
callq malloc
movq %rax, %rbp
leaq 16(%rsp), %rdi
movl $64, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movq %rsp, %rdi
movl $64, %esi
callq hipMalloc
movq 16(%rsp), %rdi
movl $64, %edx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $64, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_22
# %bb.21:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z28matrix_multiplication_kernelPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_22:
callq hipDeviceSynchronize
movq (%rsp), %rsi
movl $64, %edx
movq %rbp, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
movq %rbp, %r14
jmp .LBB1_23
.p2align 4, 0x90
.LBB1_38: # in Loop: Header=BB1_23 Depth=1
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_39: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit101
# in Loop: Header=BB1_23 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r12
addq $16, %r14
cmpq $4, %r12
je .LBB1_28
.LBB1_23: # %.preheader122
# =>This Loop Header: Depth=1
# Child Loop BB1_24 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_24: # Parent Loop BB1_23 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r15,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.3, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r15
cmpq $4, %r15
jne .LBB1_24
# %bb.25: # in Loop: Header=BB1_23 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB1_51
# %bb.26: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i98
# in Loop: Header=BB1_23 Depth=1
cmpb $0, 56(%r15)
je .LBB1_38
# %bb.27: # in Loop: Header=BB1_23 Depth=1
movzbl 67(%r15), %eax
jmp .LBB1_39
.LBB1_28:
callq _ZNSt6chrono3_V212system_clock3nowEv
subq %r13, %rax
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
imulq %rcx
movq %rdx, %r15
shrq $63, %r15
sarq $7, %rdx
addq %rdx, %r15
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movq %r15, %rsi
callq _ZNSo9_M_insertIlEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB1_51
# %bb.29: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i93
cmpb $0, 56(%r15)
je .LBB1_31
# %bb.30:
movzbl 67(%r15), %ecx
jmp .LBB1_32
.LBB1_31:
movq %r15, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_32: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit96
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r12d, %r12d
xorl %eax, %eax
jmp .LBB1_33
.p2align 4, 0x90
.LBB1_40: # in Loop: Header=BB1_33 Depth=1
incq %r12
addq $16, %rbx
addq $16, %rbp
cmpq $4, %r12
je .LBB1_41
.LBB1_33: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_34 Depth 2
xorl %r14d, %r14d
jmp .LBB1_34
.LBB1_45: # in Loop: Header=BB1_34 Depth=2
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_46: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit106
# in Loop: Header=BB1_34 Depth=2
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movb $1, %al
.LBB1_47: # in Loop: Header=BB1_34 Depth=2
incq %r14
cmpq $4, %r14
je .LBB1_40
.LBB1_34: # Parent Loop BB1_33 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbp,%r14,4), %ecx
cmpl (%rbx,%r14,4), %ecx
je .LBB1_47
# %bb.35: # in Loop: Header=BB1_34 Depth=2
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB1_51
# %bb.36: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i103
# in Loop: Header=BB1_34 Depth=2
cmpb $0, 56(%r15)
je .LBB1_45
# %bb.37: # in Loop: Header=BB1_34 Depth=2
movzbl 67(%r15), %eax
jmp .LBB1_46
.LBB1_41:
testb $1, %al
jne .LBB1_50
# %bb.42:
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_51
# %bb.43: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i108
cmpb $0, 56(%rbx)
je .LBB1_48
# %bb.44:
movzbl 67(%rbx), %eax
jmp .LBB1_49
.LBB1_48:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_49: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit111
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_50:
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_51:
.cfi_def_cfa_offset 176
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z28matrix_multiplication_kernelPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z28matrix_multiplication_kernelPiS_S_,@object # @_Z28matrix_multiplication_kernelPiS_S_
.section .rodata,"a",@progbits
.globl _Z28matrix_multiplication_kernelPiS_S_
.p2align 3, 0x0
_Z28matrix_multiplication_kernelPiS_S_:
.quad _Z43__device_stub__matrix_multiplication_kernelPiS_S_
.size _Z28matrix_multiplication_kernelPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "cpu: "
.size .L.str, 6
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "cpu time: "
.size .L.str.1, 11
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "gpu: "
.size .L.str.2, 6
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\t"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "gpu time: "
.size .L.str.4, 11
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Some error occurred"
.size .L.str.5, 20
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "No error"
.size .L.str.6, 9
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z28matrix_multiplication_kernelPiS_S_"
.size .L__unnamed_1, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z43__device_stub__matrix_multiplication_kernelPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z28matrix_multiplication_kernelPiS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z28matrix_multiplication_kernelPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0030*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R5 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GT.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GT.OR P0, PT, R0, 0x3, P0 ; /* 0x000000030000780c */
/* 0x000fda0000704670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*00b0*/ SHF.L.U32 R5, R0, 0x2, RZ ; /* 0x0000000200057819 */
/* 0x000fe200000006ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00d0*/ IADD3 R2, R6, R5, RZ ; /* 0x0000000506027210 */
/* 0x000fca0007ffe0ff */
/*00e0*/ IMAD.WIDE R2, R2, R9, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fc800078e0209 */
/*00f0*/ IMAD.WIDE R6, R6, R9.reuse, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x080fe200078e0209 */
/*0100*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe6000c101904 */
/*0110*/ IMAD.WIDE R4, R5, R9, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fe200078e0209 */
/*0120*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */
/* 0x000ea8000c1e1900 */
/*0130*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea4000c1e1900 */
/*0140*/ IMAD R9, R0, R9, RZ ; /* 0x0000000900097224 */
/* 0x004fca00078e02ff */
/*0150*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*0160*/ LDG.E R0, [R6.64+0x10] ; /* 0x0000100406007981 */
/* 0x000ea8000c1e1900 */
/*0170*/ LDG.E R8, [R4.64+0x4] ; /* 0x0000040404087981 */
/* 0x000ea4000c1e1900 */
/*0180*/ IMAD R11, R0, R8, R9 ; /* 0x00000008000b7224 */
/* 0x004fca00078e0209 */
/*0190*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe8000c101904 */
/*01a0*/ LDG.E R0, [R6.64+0x20] ; /* 0x0000200406007981 */
/* 0x000ea8000c1e1900 */
/*01b0*/ LDG.E R8, [R4.64+0x8] ; /* 0x0000080404087981 */
/* 0x000ea4000c1e1900 */
/*01c0*/ IMAD R13, R0, R8, R11 ; /* 0x00000008000d7224 */
/* 0x004fca00078e020b */
/*01d0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x000fe8000c101904 */
/*01e0*/ LDG.E R0, [R6.64+0x30] ; /* 0x0000300406007981 */
/* 0x000e28000c1e1900 */
/*01f0*/ LDG.E R8, [R4.64+0xc] ; /* 0x00000c0404087981 */
/* 0x000e24000c1e1900 */
/*0200*/ IMAD R9, R0, R8, R13 ; /* 0x0000000800097224 */
/* 0x001fca00078e020d */
/*0210*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ BRA 0x230; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z28matrix_multiplication_kernelPiS_S_
.globl _Z28matrix_multiplication_kernelPiS_S_
.p2align 8
.type _Z28matrix_multiplication_kernelPiS_S_,@function
_Z28matrix_multiplication_kernelPiS_S_:
s_load_b32 s2, s[0:1], 0x24
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
v_mad_u64_u32 v[0:1], null, s14, s2, v[4:5]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v1, v2, v0
v_cmpx_gt_i32_e32 4, v1
s_cbranch_execz .LBB0_3
v_lshlrev_b32_e32 v1, 2, v2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, v1, v0
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[1:2]
v_lshlrev_b64 v[4:5], 2, v[3:4]
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v1, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v7, vcc_lo
s_mov_b64 s[0:1], 0
global_store_b32 v[1:2], v3, off
.p2align 6
.LBB0_2:
v_add_nc_u32_e32 v6, s0, v0
v_add_co_u32 v8, vcc_lo, v4, s0
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s0, 16
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_load_b32 v8, v[8:9], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[6:7], null, v9, v8, v[3:4]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v3, v6
global_store_b32 v[1:2], v6, off
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z28matrix_multiplication_kernelPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z28matrix_multiplication_kernelPiS_S_, .Lfunc_end0-_Z28matrix_multiplication_kernelPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z28matrix_multiplication_kernelPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z28matrix_multiplication_kernelPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004fad7_00000000-6_matrix_multiplication.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3774:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3774:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z52__device_stub__Z28matrix_multiplication_kernelPiS_S_PiS_S_
.type _Z52__device_stub__Z28matrix_multiplication_kernelPiS_S_PiS_S_, @function
_Z52__device_stub__Z28matrix_multiplication_kernelPiS_S_PiS_S_:
.LFB3796:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z28matrix_multiplication_kernelPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3796:
.size _Z52__device_stub__Z28matrix_multiplication_kernelPiS_S_PiS_S_, .-_Z52__device_stub__Z28matrix_multiplication_kernelPiS_S_PiS_S_
.globl _Z28matrix_multiplication_kernelPiS_S_
.type _Z28matrix_multiplication_kernelPiS_S_, @function
_Z28matrix_multiplication_kernelPiS_S_:
.LFB3797:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z28matrix_multiplication_kernelPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3797:
.size _Z28matrix_multiplication_kernelPiS_S_, .-_Z28matrix_multiplication_kernelPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "cpu: "
.LC1:
.string "cpu time: "
.LC2:
.string "gpu: "
.LC3:
.string "\t"
.LC4:
.string "gpu time: "
.LC5:
.string "Some error occurred"
.LC6:
.string "No error"
.text
.globl main
.type main, @function
main:
.LFB3768:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $64, %edi
call malloc@PLT
movq %rax, %r12
movl $64, %edi
call malloc@PLT
movq %rax, %rbx
movl $64, %edi
call malloc@PLT
movq %rax, %r14
movl $0, %eax
.L12:
movl %eax, (%r12,%rax,4)
movl %eax, (%rbx,%rax,4)
addq $1, %rax
cmpq $16, %rax
jne .L12
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbp
movq %r12, %r11
movq %r14, %r13
movl $0, %r15d
.L13:
leaq 64(%rbx), %rdi
movq %r14, %r9
movl $0, %r8d
.L15:
movq %r9, %r10
leaq -64(%rdi), %rax
movq %r11, %rcx
movl $0, %esi
.L14:
movl (%rcx), %edx
imull (%rax), %edx
addl %edx, %esi
addq $4, %rcx
addq $16, %rax
cmpq %rdi, %rax
jne .L14
movl %esi, (%r10)
addl $1, %r8d
addq $4, %r9
addq $4, %rdi
cmpl $4, %r8d
jne .L15
addq $16, %r11
addl $4, %r15d
addq $16, %r14
cmpl $16, %r15d
jne .L13
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %rbp, %rax
movq %rax, %rcx
movabsq $2361183241434822607, %rdx
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
subq %rcx, %rdx
movq %rdx, %rbp
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %r14
movq %r14, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC2(%rip), %rsi
movq %r14, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, 8(%rsp)
movl $64, %edi
call malloc@PLT
movq %rax, %rbp
leaq 24(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $64, %edx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $64, %edx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $32, 60(%rsp)
movl $32, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L41
.L17:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $64, %edx
movq 40(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq %rbp, %r14
addq $16, %rbp
movl $0, 4(%rsp)
leaq _ZSt4cout(%rip), %r12
leaq .LC3(%rip), %r15
jmp .L18
.L41:
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z52__device_stub__Z28matrix_multiplication_kernelPiS_S_PiS_S_
jmp .L17
.L43:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L42
call _ZSt16__throw_bad_castv@PLT
.L42:
call __stack_chk_fail@PLT
.L22:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
.L23:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $4, 4(%rsp)
movl 4(%rsp), %eax
addq $16, %rbp
cmpl $16, %eax
je .L24
.L18:
leaq -16(%rbp), %rbx
.L19:
movl (%rbx), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r15, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L19
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %rbx
testq %rbx, %rbx
je .L43
cmpb $0, 56(%rbx)
je .L22
movzbl 67(%rbx), %esi
jmp .L23
.L24:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq 8(%rsp), %rbx
subq %rbx, %rax
movq %rax, %rcx
movabsq $2361183241434822607, %rdx
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
movq %rdx, %rbx
subq %rcx, %rbx
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %r15d
movl $0, %eax
leaq _ZSt4cout(%rip), %r12
jmp .L25
.L46:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L44
call _ZSt16__throw_bad_castv@PLT
.L44:
call __stack_chk_fail@PLT
.L29:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
.L30:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $1, %eax
.L26:
addq $4, %rbx
cmpq $16, %rbx
je .L45
.L31:
movl 0(%r13,%rbx), %ecx
cmpl %ecx, (%r14,%rbx)
je .L26
movl $19, %edx
leaq .LC5(%rip), %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %rbp
testq %rbp, %rbp
je .L46
cmpb $0, 56(%rbp)
je .L29
movzbl 67(%rbp), %esi
jmp .L30
.L45:
addl $4, %r15d
addq $16, %r14
addq $16, %r13
cmpl $16, %r15d
je .L32
.L25:
movl $0, %ebx
jmp .L31
.L32:
testb %al, %al
je .L47
.L33:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L48
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L33
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3768:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "_Z28matrix_multiplication_kernelPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3799:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z28matrix_multiplication_kernelPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3799:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrix_multiplication.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z43__device_stub__matrix_multiplication_kernelPiS_S_ # -- Begin function _Z43__device_stub__matrix_multiplication_kernelPiS_S_
.p2align 4, 0x90
.type _Z43__device_stub__matrix_multiplication_kernelPiS_S_,@function
_Z43__device_stub__matrix_multiplication_kernelPiS_S_: # @_Z43__device_stub__matrix_multiplication_kernelPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z28matrix_multiplication_kernelPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z43__device_stub__matrix_multiplication_kernelPiS_S_, .Lfunc_end0-_Z43__device_stub__matrix_multiplication_kernelPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $64, %edi
callq malloc
movq %rax, %r12
movl $64, %edi
callq malloc
movq %rax, %r15
movl $64, %edi
callq malloc
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%r12,%rax,4)
movl %eax, (%r15,%rax,4)
incq %rax
cmpq $16, %rax
jne .LBB1_1
# %bb.2:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB1_51
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB1_5
# %bb.4:
movzbl 67(%r14), %eax
jmp .LBB1_6
.LBB1_5:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r13d, %r13d
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r14
movq %r12, %rax
.p2align 4, 0x90
.LBB1_7: # %.preheader123
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
# Child Loop BB1_9 Depth 3
leaq (,%r13,4), %rcx
movq %r15, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_8: # Parent Loop BB1_7 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_9 Depth 3
movq %rsi, %rdi
orq %rcx, %rdi
movl $0, (%rbx,%rdi,4)
xorl %r8d, %r8d
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB1_9: # Parent Loop BB1_7 Depth=1
# Parent Loop BB1_8 Depth=2
# => This Inner Loop Header: Depth=3
movl (%rdx,%r8,4), %r10d
imull (%rax,%r8), %r10d
addl %r10d, %r9d
addq $4, %r8
cmpq $16, %r8
jne .LBB1_9
# %bb.10: # in Loop: Header=BB1_8 Depth=2
movl %r9d, (%rbx,%rdi,4)
incq %rsi
addq $4, %rdx
cmpq $4, %rsi
jne .LBB1_8
# %bb.11: # in Loop: Header=BB1_7 Depth=1
incq %r13
addq $16, %rax
cmpq $4, %r13
jne .LBB1_7
# %bb.12:
callq _ZNSt6chrono3_V212system_clock3nowEv
subq %r14, %rax
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
imulq %rcx
movq %rdx, %r14
shrq $63, %r14
sarq $7, %rdx
addq %rdx, %r14
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movq %r14, %rsi
callq _ZNSo9_M_insertIlEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_51
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i83
cmpb $0, 56(%r14)
je .LBB1_15
# %bb.14:
movzbl 67(%r14), %ecx
jmp .LBB1_16
.LBB1_15:
movq %r14, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB1_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit86
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB1_51
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i88
cmpb $0, 56(%r14)
je .LBB1_19
# %bb.18:
movzbl 67(%r14), %eax
jmp .LBB1_20
.LBB1_19:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit91
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r13
movl $64, %edi
callq malloc
movq %rax, %rbp
leaq 16(%rsp), %rdi
movl $64, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movq %rsp, %rdi
movl $64, %esi
callq hipMalloc
movq 16(%rsp), %rdi
movl $64, %edx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $64, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_22
# %bb.21:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z28matrix_multiplication_kernelPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_22:
callq hipDeviceSynchronize
movq (%rsp), %rsi
movl $64, %edx
movq %rbp, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
movq %rbp, %r14
jmp .LBB1_23
.p2align 4, 0x90
.LBB1_38: # in Loop: Header=BB1_23 Depth=1
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_39: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit101
# in Loop: Header=BB1_23 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r12
addq $16, %r14
cmpq $4, %r12
je .LBB1_28
.LBB1_23: # %.preheader122
# =>This Loop Header: Depth=1
# Child Loop BB1_24 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_24: # Parent Loop BB1_23 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r15,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.3, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r15
cmpq $4, %r15
jne .LBB1_24
# %bb.25: # in Loop: Header=BB1_23 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB1_51
# %bb.26: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i98
# in Loop: Header=BB1_23 Depth=1
cmpb $0, 56(%r15)
je .LBB1_38
# %bb.27: # in Loop: Header=BB1_23 Depth=1
movzbl 67(%r15), %eax
jmp .LBB1_39
.LBB1_28:
callq _ZNSt6chrono3_V212system_clock3nowEv
subq %r13, %rax
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
imulq %rcx
movq %rdx, %r15
shrq $63, %r15
sarq $7, %rdx
addq %rdx, %r15
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movq %r15, %rsi
callq _ZNSo9_M_insertIlEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB1_51
# %bb.29: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i93
cmpb $0, 56(%r15)
je .LBB1_31
# %bb.30:
movzbl 67(%r15), %ecx
jmp .LBB1_32
.LBB1_31:
movq %r15, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_32: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit96
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r12d, %r12d
xorl %eax, %eax
jmp .LBB1_33
.p2align 4, 0x90
.LBB1_40: # in Loop: Header=BB1_33 Depth=1
incq %r12
addq $16, %rbx
addq $16, %rbp
cmpq $4, %r12
je .LBB1_41
.LBB1_33: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_34 Depth 2
xorl %r14d, %r14d
jmp .LBB1_34
.LBB1_45: # in Loop: Header=BB1_34 Depth=2
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_46: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit106
# in Loop: Header=BB1_34 Depth=2
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movb $1, %al
.LBB1_47: # in Loop: Header=BB1_34 Depth=2
incq %r14
cmpq $4, %r14
je .LBB1_40
.LBB1_34: # Parent Loop BB1_33 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbp,%r14,4), %ecx
cmpl (%rbx,%r14,4), %ecx
je .LBB1_47
# %bb.35: # in Loop: Header=BB1_34 Depth=2
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB1_51
# %bb.36: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i103
# in Loop: Header=BB1_34 Depth=2
cmpb $0, 56(%r15)
je .LBB1_45
# %bb.37: # in Loop: Header=BB1_34 Depth=2
movzbl 67(%r15), %eax
jmp .LBB1_46
.LBB1_41:
testb $1, %al
jne .LBB1_50
# %bb.42:
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_51
# %bb.43: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i108
cmpb $0, 56(%rbx)
je .LBB1_48
# %bb.44:
movzbl 67(%rbx), %eax
jmp .LBB1_49
.LBB1_48:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_49: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit111
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_50:
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_51:
.cfi_def_cfa_offset 176
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z28matrix_multiplication_kernelPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z28matrix_multiplication_kernelPiS_S_,@object # @_Z28matrix_multiplication_kernelPiS_S_
.section .rodata,"a",@progbits
.globl _Z28matrix_multiplication_kernelPiS_S_
.p2align 3, 0x0
_Z28matrix_multiplication_kernelPiS_S_:
.quad _Z43__device_stub__matrix_multiplication_kernelPiS_S_
.size _Z28matrix_multiplication_kernelPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "cpu: "
.size .L.str, 6
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "cpu time: "
.size .L.str.1, 11
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "gpu: "
.size .L.str.2, 6
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\t"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "gpu time: "
.size .L.str.4, 11
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Some error occurred"
.size .L.str.5, 20
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "No error"
.size .L.str.6, 9
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z28matrix_multiplication_kernelPiS_S_"
.size .L__unnamed_1, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z43__device_stub__matrix_multiplication_kernelPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z28matrix_multiplication_kernelPiS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime.h>
#include <stdio.h>
__global__ void check_index()
{
printf("threadIdx: (%d,%d,%d) blockIdx: (%d,%d,%d) blockDim: (%d,%d,%d) gridDim: (%d,%d,%d)\n",
threadIdx.x, threadIdx.y, threadIdx.z,
blockIdx.x, blockIdx.y, blockIdx.z,
blockDim.x, blockDim.y, blockDim.z,
gridDim.x, gridDim.y, blockDim.z
);
}
int main( int argc, char **argv)
{
int Ndata = 10;
dim3 block(3);
dim3 grid( (Ndata+block.x-1)/block.x );
printf("grid: (%d,%d,%d)\n", grid.x, grid.y, grid.z);
printf("blocks: (%d,%d,%d)\n", block.x, block.y, block.z);
check_index<<<grid, block>>>();
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _Z11check_indexv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002500 */
/*0020*/ IADD3 R1, R1, -0x30, RZ ; /* 0xffffffd001017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0e7624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R18, c[0x0][0x10] ; /* 0x0000040000127a02 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R10, SR_TID.Z ; /* 0x00000000000a7919 */
/* 0x000e220000002300 */
/*0060*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x4] ; /* 0x00000100ff0f7624 */
/* 0x000fe200078e00ff */
/*0070*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0080*/ IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x8] ; /* 0x00000200ff107624 */
/* 0x000fe200078e00ff */
/*0090*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000e220000002200 */
/*00a0*/ IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff117624 */
/* 0x000fe200078e00ff */
/*00b0*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0002a20000000a00 */
/*00c0*/ IMAD.MOV.U32 R19, RZ, RZ, c[0x0][0x8] ; /* 0x00000200ff137624 */
/* 0x000fe200078e00ff */
/*00d0*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*00e0*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*00f0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0100*/ MOV R5, c[0x4][0xc] ; /* 0x0100030000057a02 */
/* 0x000fe20000000f00 */
/*0110*/ S2R R13, SR_CTAID.Z ; /* 0x00000000000d7919 */
/* 0x000ee40000002700 */
/*0120*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fc400000e06ff */
/*0130*/ S2R R12, SR_CTAID.Y ; /* 0x00000000000c7919 */
/* 0x000ee80000002600 */
/*0140*/ STL.128 [R1+0x20], R16 ; /* 0x0000201001007387 */
/* 0x0003e80000100c00 */
/*0150*/ STL.128 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0013e80000100c00 */
/*0160*/ STL.128 [R1+0x10], R12 ; /* 0x0000100c01007387 */
/* 0x0083e40000100c00 */
/*0170*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x006fe40000000000 */
/*0180*/ MOV R11, 0x1f0 ; /* 0x000001f0000b7802 */
/* 0x000fe40000000f00 */
/*0190*/ MOV R20, 0x170 ; /* 0x0000017000147802 */
/* 0x000fc40000000f00 */
/*01a0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*01b0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*01c0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*01d0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*01e0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x000fea0003c00000 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
#include <stdio.h>
__global__ void check_index()
{
printf("threadIdx: (%d,%d,%d) blockIdx: (%d,%d,%d) blockDim: (%d,%d,%d) gridDim: (%d,%d,%d)\n",
threadIdx.x, threadIdx.y, threadIdx.z,
blockIdx.x, blockIdx.y, blockIdx.z,
blockDim.x, blockDim.y, blockDim.z,
gridDim.x, gridDim.y, blockDim.z
);
}
int main( int argc, char **argv)
{
int Ndata = 10;
dim3 block(3);
dim3 grid( (Ndata+block.x-1)/block.x );
printf("grid: (%d,%d,%d)\n", grid.x, grid.y, grid.z);
printf("blocks: (%d,%d,%d)\n", block.x, block.y, block.z);
check_index<<<grid, block>>>();
cudaDeviceReset();
return 0;
} | .file "tmpxft_0016e689_00000000-6_04_check_dimensions.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z11check_indexvv
.type _Z30__device_stub__Z11check_indexvv, @function
_Z30__device_stub__Z11check_indexvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z11check_indexv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z11check_indexvv, .-_Z30__device_stub__Z11check_indexvv
.globl _Z11check_indexv
.type _Z11check_indexv, @function
_Z11check_indexv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z11check_indexvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11check_indexv, .-_Z11check_indexv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "grid: (%d,%d,%d)\n"
.LC1:
.string "blocks: (%d,%d,%d)\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, %r8d
movl $1, %ecx
movl $4, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %r8d
movl $1, %ecx
movl $3, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4, 20(%rsp)
movl $1, 24(%rsp)
movl $3, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z30__device_stub__Z11check_indexvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z11check_indexv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z11check_indexv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
#include <stdio.h>
__global__ void check_index()
{
printf("threadIdx: (%d,%d,%d) blockIdx: (%d,%d,%d) blockDim: (%d,%d,%d) gridDim: (%d,%d,%d)\n",
threadIdx.x, threadIdx.y, threadIdx.z,
blockIdx.x, blockIdx.y, blockIdx.z,
blockDim.x, blockDim.y, blockDim.z,
gridDim.x, gridDim.y, blockDim.z
);
}
int main( int argc, char **argv)
{
int Ndata = 10;
dim3 block(3);
dim3 grid( (Ndata+block.x-1)/block.x );
printf("grid: (%d,%d,%d)\n", grid.x, grid.y, grid.z);
printf("blocks: (%d,%d,%d)\n", block.x, block.y, block.z);
check_index<<<grid, block>>>();
cudaDeviceReset();
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void check_index()
{
printf("threadIdx: (%d,%d,%d) blockIdx: (%d,%d,%d) blockDim: (%d,%d,%d) gridDim: (%d,%d,%d)\n",
threadIdx.x, threadIdx.y, threadIdx.z,
blockIdx.x, blockIdx.y, blockIdx.z,
blockDim.x, blockDim.y, blockDim.z,
gridDim.x, gridDim.y, blockDim.z
);
}
int main( int argc, char **argv)
{
int Ndata = 10;
dim3 block(3);
dim3 grid( (Ndata+block.x-1)/block.x );
printf("grid: (%d,%d,%d)\n", grid.x, grid.y, grid.z);
printf("blocks: (%d,%d,%d)\n", block.x, block.y, block.z);
check_index<<<grid, block>>>();
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void check_index()
{
printf("threadIdx: (%d,%d,%d) blockIdx: (%d,%d,%d) blockDim: (%d,%d,%d) gridDim: (%d,%d,%d)\n",
threadIdx.x, threadIdx.y, threadIdx.z,
blockIdx.x, blockIdx.y, blockIdx.z,
blockDim.x, blockDim.y, blockDim.z,
gridDim.x, gridDim.y, blockDim.z
);
}
int main( int argc, char **argv)
{
int Ndata = 10;
dim3 block(3);
dim3 grid( (Ndata+block.x-1)/block.x );
printf("grid: (%d,%d,%d)\n", grid.x, grid.y, grid.z);
printf("blocks: (%d,%d,%d)\n", block.x, block.y, block.z);
check_index<<<grid, block>>>();
hipDeviceReset();
return 0;
} | .text
.file "04_check_dimensions.hip"
.globl _Z26__device_stub__check_indexv # -- Begin function _Z26__device_stub__check_indexv
.p2align 4, 0x90
.type _Z26__device_stub__check_indexv,@function
_Z26__device_stub__check_indexv: # @_Z26__device_stub__check_indexv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z11check_indexv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z26__device_stub__check_indexv, .Lfunc_end0-_Z26__device_stub__check_indexv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.L.str, %edi
movl $4, %esi
movl $1, %edx
movl $1, %ecx
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $3, %esi
movl $1, %edx
movl $1, %ecx
xorl %eax, %eax
callq printf
movabsq $4294967299, %rdx # imm = 0x100000003
leaq 1(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z11check_indexv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11check_indexv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11check_indexv,@object # @_Z11check_indexv
.section .rodata,"a",@progbits
.globl _Z11check_indexv
.p2align 3, 0x0
_Z11check_indexv:
.quad _Z26__device_stub__check_indexv
.size _Z11check_indexv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "grid: (%d,%d,%d)\n"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "blocks: (%d,%d,%d)\n"
.size .L.str.1, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11check_indexv"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__check_indexv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11check_indexv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016e689_00000000-6_04_check_dimensions.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z11check_indexvv
.type _Z30__device_stub__Z11check_indexvv, @function
_Z30__device_stub__Z11check_indexvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z11check_indexv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z11check_indexvv, .-_Z30__device_stub__Z11check_indexvv
.globl _Z11check_indexv
.type _Z11check_indexv, @function
_Z11check_indexv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z11check_indexvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11check_indexv, .-_Z11check_indexv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "grid: (%d,%d,%d)\n"
.LC1:
.string "blocks: (%d,%d,%d)\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, %r8d
movl $1, %ecx
movl $4, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %r8d
movl $1, %ecx
movl $3, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4, 20(%rsp)
movl $1, 24(%rsp)
movl $3, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z30__device_stub__Z11check_indexvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z11check_indexv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z11check_indexv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "04_check_dimensions.hip"
.globl _Z26__device_stub__check_indexv # -- Begin function _Z26__device_stub__check_indexv
.p2align 4, 0x90
.type _Z26__device_stub__check_indexv,@function
_Z26__device_stub__check_indexv: # @_Z26__device_stub__check_indexv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z11check_indexv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z26__device_stub__check_indexv, .Lfunc_end0-_Z26__device_stub__check_indexv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.L.str, %edi
movl $4, %esi
movl $1, %edx
movl $1, %ecx
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $3, %esi
movl $1, %edx
movl $1, %ecx
xorl %eax, %eax
callq printf
movabsq $4294967299, %rdx # imm = 0x100000003
leaq 1(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z11check_indexv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11check_indexv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11check_indexv,@object # @_Z11check_indexv
.section .rodata,"a",@progbits
.globl _Z11check_indexv
.p2align 3, 0x0
_Z11check_indexv:
.quad _Z26__device_stub__check_indexv
.size _Z11check_indexv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "grid: (%d,%d,%d)\n"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "blocks: (%d,%d,%d)\n"
.size .L.str.1, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11check_indexv"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__check_indexv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11check_indexv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<time.h>
#include<cuda.h>
#include<stdlib.h>
__global__ void max_value(int *a, int *b) // kernel subroutine called from the host cpu to the gpu device
{
int i = threadIdx.x; // getting the thread id
*b = a[0]; // equating the value of the address in c to a predefined value in a matrix.
if(a[i] > *b) // getting the value from the address of c variable.
{
*b = a[i];
}
}
int main(int argc, char *argv[])
{
if(argc == 3)
{
int arr_size = atoi(argv[1]);
int rem = atoi(argv[2]);
srand(time(NULL)); // seed entry for max randomness
int a[arr_size];
int b;
int *dev_a,*dev_b; // gpu parameters
cudaMalloc((void **) &dev_a,arr_size*sizeof(int));
cudaMalloc((void **) &dev_b,sizeof(int));
for(int i=0;i<arr_size;i++)
{
a[i] = rand() % rem + i;
}
cudaMemcpy(dev_a,a,arr_size*sizeof(int),cudaMemcpyHostToDevice); // sending the array into gpu memory.
max_value<<<1,arr_size>>>(dev_a,dev_b);
cudaMemcpy(&b,dev_b,sizeof(int),cudaMemcpyDeviceToHost);
printf("\nmax = %d ",b);
cudaFree(dev_a); // Free the allocated memory
cudaFree(dev_b);
}
else if(argc > 3){
printf("Too many args to be parsed\n");
}
else
{
printf("one argument required\n");
}
return 0;
} | code for sm_80
Function : _Z9max_valuePiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0040*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0050*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0060*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe40000000f00 */
/*0070*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0080*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fe20000000f00 */
/*0090*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x001fc800078e0207 */
/*00a0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe8000c101904 */
/*00b0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ IMNMX R9, R3, R6, !PT ; /* 0x0000000603097217 */
/* 0x004fca0007800200 */
/*00d0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<time.h>
#include<cuda.h>
#include<stdlib.h>
__global__ void max_value(int *a, int *b) // kernel subroutine called from the host cpu to the gpu device
{
int i = threadIdx.x; // getting the thread id
*b = a[0]; // equating the value of the address in c to a predefined value in a matrix.
if(a[i] > *b) // getting the value from the address of c variable.
{
*b = a[i];
}
}
int main(int argc, char *argv[])
{
if(argc == 3)
{
int arr_size = atoi(argv[1]);
int rem = atoi(argv[2]);
srand(time(NULL)); // seed entry for max randomness
int a[arr_size];
int b;
int *dev_a,*dev_b; // gpu parameters
cudaMalloc((void **) &dev_a,arr_size*sizeof(int));
cudaMalloc((void **) &dev_b,sizeof(int));
for(int i=0;i<arr_size;i++)
{
a[i] = rand() % rem + i;
}
cudaMemcpy(dev_a,a,arr_size*sizeof(int),cudaMemcpyHostToDevice); // sending the array into gpu memory.
max_value<<<1,arr_size>>>(dev_a,dev_b);
cudaMemcpy(&b,dev_b,sizeof(int),cudaMemcpyDeviceToHost);
printf("\nmax = %d ",b);
cudaFree(dev_a); // Free the allocated memory
cudaFree(dev_b);
}
else if(argc > 3){
printf("Too many args to be parsed\n");
}
else
{
printf("one argument required\n");
}
return 0;
} | .file "tmpxft_000d5b25_00000000-6_max_value.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z9max_valuePiS_PiS_
.type _Z30__device_stub__Z9max_valuePiS_PiS_, @function
_Z30__device_stub__Z9max_valuePiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9max_valuePiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z9max_valuePiS_PiS_, .-_Z30__device_stub__Z9max_valuePiS_PiS_
.globl _Z9max_valuePiS_
.type _Z9max_valuePiS_, @function
_Z9max_valuePiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9max_valuePiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9max_valuePiS_, .-_Z9max_valuePiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\nmax = %d "
.LC1:
.string "Too many args to be parsed\n"
.LC2:
.string "one argument required\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $72, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
cmpl $3, %edi
je .L24
jle .L20
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L19:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L24:
.cfi_restore_state
movq %rsi, %rbx
movq %rsp, -112(%rbp)
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %r12d
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movslq %r15d, %rax
salq $2, %rax
movq %rax, -104(%rbp)
addq $15, %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L13:
cmpq %rdx, %rsp
je .L14
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L13
.L14:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L15
orq $0, -8(%rsp,%rax)
.L15:
movq %rsp, %r13
leaq -96(%rbp), %rdi
movq -104(%rbp), %rsi
call cudaMalloc@PLT
leaq -88(%rbp), %rdi
movl $4, %esi
call cudaMalloc@PLT
testl %r15d, %r15d
jle .L16
leal -1(%r15), %r14d
movl $0, %ebx
.L17:
call rand@PLT
cltd
idivl %r12d
addl %ebx, %edx
movl %edx, 0(%r13,%rbx,4)
movq %rbx, %rax
addq $1, %rbx
cmpq %r14, %rax
jne .L17
.L16:
movl $1, %ecx
movq -104(%rbp), %rdx
movq %r13, %rsi
movq -96(%rbp), %rdi
call cudaMemcpy@PLT
movl %r15d, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl $1, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L18:
leaq -68(%rbp), %rdi
movl $2, %ecx
movl $4, %edx
movq -88(%rbp), %rsi
call cudaMemcpy@PLT
movl -68(%rbp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq -96(%rbp), %rdi
call cudaFree@PLT
movq -88(%rbp), %rdi
call cudaFree@PLT
movq -112(%rbp), %rsp
jmp .L19
.L26:
movq -88(%rbp), %rsi
movq -96(%rbp), %rdi
call _Z30__device_stub__Z9max_valuePiS_PiS_
jmp .L18
.L20:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L19
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z9max_valuePiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z9max_valuePiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<time.h>
#include<cuda.h>
#include<stdlib.h>
__global__ void max_value(int *a, int *b) // kernel subroutine called from the host cpu to the gpu device
{
int i = threadIdx.x; // getting the thread id
*b = a[0]; // equating the value of the address in c to a predefined value in a matrix.
if(a[i] > *b) // getting the value from the address of c variable.
{
*b = a[i];
}
}
int main(int argc, char *argv[])
{
if(argc == 3)
{
int arr_size = atoi(argv[1]);
int rem = atoi(argv[2]);
srand(time(NULL)); // seed entry for max randomness
int a[arr_size];
int b;
int *dev_a,*dev_b; // gpu parameters
cudaMalloc((void **) &dev_a,arr_size*sizeof(int));
cudaMalloc((void **) &dev_b,sizeof(int));
for(int i=0;i<arr_size;i++)
{
a[i] = rand() % rem + i;
}
cudaMemcpy(dev_a,a,arr_size*sizeof(int),cudaMemcpyHostToDevice); // sending the array into gpu memory.
max_value<<<1,arr_size>>>(dev_a,dev_b);
cudaMemcpy(&b,dev_b,sizeof(int),cudaMemcpyDeviceToHost);
printf("\nmax = %d ",b);
cudaFree(dev_a); // Free the allocated memory
cudaFree(dev_b);
}
else if(argc > 3){
printf("Too many args to be parsed\n");
}
else
{
printf("one argument required\n");
}
return 0;
} | #include<stdio.h>
#include<time.h>
#include<hip/hip_runtime.h>
#include<stdlib.h>
__global__ void max_value(int *a, int *b) // kernel subroutine called from the host cpu to the gpu device
{
int i = threadIdx.x; // getting the thread id
*b = a[0]; // equating the value of the address in c to a predefined value in a matrix.
if(a[i] > *b) // getting the value from the address of c variable.
{
*b = a[i];
}
}
int main(int argc, char *argv[])
{
if(argc == 3)
{
int arr_size = atoi(argv[1]);
int rem = atoi(argv[2]);
srand(time(NULL)); // seed entry for max randomness
int a[arr_size];
int b;
int *dev_a,*dev_b; // gpu parameters
hipMalloc((void **) &dev_a,arr_size*sizeof(int));
hipMalloc((void **) &dev_b,sizeof(int));
for(int i=0;i<arr_size;i++)
{
a[i] = rand() % rem + i;
}
hipMemcpy(dev_a,a,arr_size*sizeof(int),hipMemcpyHostToDevice); // sending the array into gpu memory.
max_value<<<1,arr_size>>>(dev_a,dev_b);
hipMemcpy(&b,dev_b,sizeof(int),hipMemcpyDeviceToHost);
printf("\nmax = %d ",b);
hipFree(dev_a); // Free the allocated memory
hipFree(dev_b);
}
else if(argc > 3){
printf("Too many args to be parsed\n");
}
else
{
printf("one argument required\n");
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include<stdio.h>
#include<time.h>
#include<hip/hip_runtime.h>
#include<stdlib.h>
__global__ void max_value(int *a, int *b) // kernel subroutine called from the host cpu to the gpu device
{
int i = threadIdx.x; // getting the thread id
*b = a[0]; // equating the value of the address in c to a predefined value in a matrix.
if(a[i] > *b) // getting the value from the address of c variable.
{
*b = a[i];
}
}
int main(int argc, char *argv[])
{
if(argc == 3)
{
int arr_size = atoi(argv[1]);
int rem = atoi(argv[2]);
srand(time(NULL)); // seed entry for max randomness
int a[arr_size];
int b;
int *dev_a,*dev_b; // gpu parameters
hipMalloc((void **) &dev_a,arr_size*sizeof(int));
hipMalloc((void **) &dev_b,sizeof(int));
for(int i=0;i<arr_size;i++)
{
a[i] = rand() % rem + i;
}
hipMemcpy(dev_a,a,arr_size*sizeof(int),hipMemcpyHostToDevice); // sending the array into gpu memory.
max_value<<<1,arr_size>>>(dev_a,dev_b);
hipMemcpy(&b,dev_b,sizeof(int),hipMemcpyDeviceToHost);
printf("\nmax = %d ",b);
hipFree(dev_a); // Free the allocated memory
hipFree(dev_b);
}
else if(argc > 3){
printf("Too many args to be parsed\n");
}
else
{
printf("one argument required\n");
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9max_valuePiS_
.globl _Z9max_valuePiS_
.p2align 8
.type _Z9max_valuePiS_,@function
_Z9max_valuePiS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_load_b32 s4, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s4
global_store_b32 v1, v2, s[2:3]
global_load_b32 v0, v0, s[0:1]
s_waitcnt vmcnt(0)
v_max_i32_e32 v0, s4, v0
global_store_b32 v1, v0, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9max_valuePiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 5
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9max_valuePiS_, .Lfunc_end0-_Z9max_valuePiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9max_valuePiS_
.private_segment_fixed_size: 0
.sgpr_count: 5
.sgpr_spill_count: 0
.symbol: _Z9max_valuePiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<stdio.h>
#include<time.h>
#include<hip/hip_runtime.h>
#include<stdlib.h>
__global__ void max_value(int *a, int *b) // kernel subroutine called from the host cpu to the gpu device
{
int i = threadIdx.x; // getting the thread id
*b = a[0]; // equating the value of the address in c to a predefined value in a matrix.
if(a[i] > *b) // getting the value from the address of c variable.
{
*b = a[i];
}
}
int main(int argc, char *argv[])
{
if(argc == 3)
{
int arr_size = atoi(argv[1]);
int rem = atoi(argv[2]);
srand(time(NULL)); // seed entry for max randomness
int a[arr_size];
int b;
int *dev_a,*dev_b; // gpu parameters
hipMalloc((void **) &dev_a,arr_size*sizeof(int));
hipMalloc((void **) &dev_b,sizeof(int));
for(int i=0;i<arr_size;i++)
{
a[i] = rand() % rem + i;
}
hipMemcpy(dev_a,a,arr_size*sizeof(int),hipMemcpyHostToDevice); // sending the array into gpu memory.
max_value<<<1,arr_size>>>(dev_a,dev_b);
hipMemcpy(&b,dev_b,sizeof(int),hipMemcpyDeviceToHost);
printf("\nmax = %d ",b);
hipFree(dev_a); // Free the allocated memory
hipFree(dev_b);
}
else if(argc > 3){
printf("Too many args to be parsed\n");
}
else
{
printf("one argument required\n");
}
return 0;
} | .text
.file "max_value.hip"
.globl _Z24__device_stub__max_valuePiS_ # -- Begin function _Z24__device_stub__max_valuePiS_
.p2align 4, 0x90
.type _Z24__device_stub__max_valuePiS_,@function
_Z24__device_stub__max_valuePiS_: # @_Z24__device_stub__max_valuePiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9max_valuePiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__max_valuePiS_, .Lfunc_end0-_Z24__device_stub__max_valuePiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $120, %rsp
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
cmpl $3, %edi
jne .LBB1_7
# %bb.1:
movq 8(%rsi), %rdi
movq %rsi, %rbx
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movq %rsp, -96(%rbp) # 8-byte Spill
movl %r12d, %ebx
leaq 15(,%rbx,4), %rax
andq $-16, %rax
movq %rsp, %r15
subq %rax, %r15
movq %r15, %rsp
movslq %r12d, %r13
leaq (,%r13,4), %rsi
leaq -56(%rbp), %rdi
movq %rsi, -88(%rbp) # 8-byte Spill
callq hipMalloc
leaq -48(%rbp), %rdi
movl $4, %esi
callq hipMalloc
testl %r13d, %r13d
jle .LBB1_4
# %bb.2: # %.lr.ph.preheader
movl %r12d, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltd
idivl %r14d
addl %r13d, %edx
movl %edx, (%r15,%r13,4)
incq %r13
cmpq %r13, %r12
jne .LBB1_3
.LBB1_4: # %._crit_edge
movq -56(%rbp), %rdi
movq %r15, %rsi
movq -88(%rbp), %rdx # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rbx
orq $1, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq -56(%rbp), %rax
movq -48(%rbp), %rcx
movq %rax, -160(%rbp)
movq %rcx, -152(%rbp)
leaq -160(%rbp), %rax
movq %rax, -80(%rbp)
leaq -152(%rbp), %rax
movq %rax, -72(%rbp)
leaq -144(%rbp), %rdi
leaq -128(%rbp), %rsi
leaq -112(%rbp), %rdx
leaq -104(%rbp), %rcx
callq __hipPopCallConfiguration
movq -144(%rbp), %rsi
movl -136(%rbp), %edx
movq -128(%rbp), %rcx
movl -120(%rbp), %r8d
leaq -80(%rbp), %r9
movl $_Z9max_valuePiS_, %edi
pushq -104(%rbp)
pushq -112(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB1_6:
movq -48(%rbp), %rsi
leaq -80(%rbp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl -80(%rbp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq -56(%rbp), %rdi
callq hipFree
movq -48(%rbp), %rdi
callq hipFree
movq -96(%rbp), %rsp # 8-byte Reload
jmp .LBB1_11
.LBB1_7:
jle .LBB1_9
# %bb.8:
movl $.Lstr.1, %edi
jmp .LBB1_10
.LBB1_9:
movl $.Lstr, %edi
.LBB1_10:
callq puts@PLT
.LBB1_11:
xorl %eax, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9max_valuePiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9max_valuePiS_,@object # @_Z9max_valuePiS_
.section .rodata,"a",@progbits
.globl _Z9max_valuePiS_
.p2align 3, 0x0
_Z9max_valuePiS_:
.quad _Z24__device_stub__max_valuePiS_
.size _Z9max_valuePiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nmax = %d "
.size .L.str, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9max_valuePiS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "one argument required"
.size .Lstr, 22
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Too many args to be parsed"
.size .Lstr.1, 27
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__max_valuePiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9max_valuePiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9max_valuePiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0040*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0050*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0060*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe40000000f00 */
/*0070*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0080*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fe20000000f00 */
/*0090*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x001fc800078e0207 */
/*00a0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe8000c101904 */
/*00b0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ IMNMX R9, R3, R6, !PT ; /* 0x0000000603097217 */
/* 0x004fca0007800200 */
/*00d0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9max_valuePiS_
.globl _Z9max_valuePiS_
.p2align 8
.type _Z9max_valuePiS_,@function
_Z9max_valuePiS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_load_b32 s4, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s4
global_store_b32 v1, v2, s[2:3]
global_load_b32 v0, v0, s[0:1]
s_waitcnt vmcnt(0)
v_max_i32_e32 v0, s4, v0
global_store_b32 v1, v0, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9max_valuePiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 5
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9max_valuePiS_, .Lfunc_end0-_Z9max_valuePiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9max_valuePiS_
.private_segment_fixed_size: 0
.sgpr_count: 5
.sgpr_spill_count: 0
.symbol: _Z9max_valuePiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d5b25_00000000-6_max_value.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z9max_valuePiS_PiS_
.type _Z30__device_stub__Z9max_valuePiS_PiS_, @function
_Z30__device_stub__Z9max_valuePiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9max_valuePiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z9max_valuePiS_PiS_, .-_Z30__device_stub__Z9max_valuePiS_PiS_
.globl _Z9max_valuePiS_
.type _Z9max_valuePiS_, @function
_Z9max_valuePiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9max_valuePiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9max_valuePiS_, .-_Z9max_valuePiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\nmax = %d "
.LC1:
.string "Too many args to be parsed\n"
.LC2:
.string "one argument required\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $72, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
cmpl $3, %edi
je .L24
jle .L20
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L19:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L24:
.cfi_restore_state
movq %rsi, %rbx
movq %rsp, -112(%rbp)
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %r12d
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movslq %r15d, %rax
salq $2, %rax
movq %rax, -104(%rbp)
addq $15, %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L13:
cmpq %rdx, %rsp
je .L14
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L13
.L14:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L15
orq $0, -8(%rsp,%rax)
.L15:
movq %rsp, %r13
leaq -96(%rbp), %rdi
movq -104(%rbp), %rsi
call cudaMalloc@PLT
leaq -88(%rbp), %rdi
movl $4, %esi
call cudaMalloc@PLT
testl %r15d, %r15d
jle .L16
leal -1(%r15), %r14d
movl $0, %ebx
.L17:
call rand@PLT
cltd
idivl %r12d
addl %ebx, %edx
movl %edx, 0(%r13,%rbx,4)
movq %rbx, %rax
addq $1, %rbx
cmpq %r14, %rax
jne .L17
.L16:
movl $1, %ecx
movq -104(%rbp), %rdx
movq %r13, %rsi
movq -96(%rbp), %rdi
call cudaMemcpy@PLT
movl %r15d, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl $1, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L18:
leaq -68(%rbp), %rdi
movl $2, %ecx
movl $4, %edx
movq -88(%rbp), %rsi
call cudaMemcpy@PLT
movl -68(%rbp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq -96(%rbp), %rdi
call cudaFree@PLT
movq -88(%rbp), %rdi
call cudaFree@PLT
movq -112(%rbp), %rsp
jmp .L19
.L26:
movq -88(%rbp), %rsi
movq -96(%rbp), %rdi
call _Z30__device_stub__Z9max_valuePiS_PiS_
jmp .L18
.L20:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L19
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z9max_valuePiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z9max_valuePiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "max_value.hip"
.globl _Z24__device_stub__max_valuePiS_ # -- Begin function _Z24__device_stub__max_valuePiS_
.p2align 4, 0x90
.type _Z24__device_stub__max_valuePiS_,@function
_Z24__device_stub__max_valuePiS_: # @_Z24__device_stub__max_valuePiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9max_valuePiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__max_valuePiS_, .Lfunc_end0-_Z24__device_stub__max_valuePiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $120, %rsp
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
cmpl $3, %edi
jne .LBB1_7
# %bb.1:
movq 8(%rsi), %rdi
movq %rsi, %rbx
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movq %rsp, -96(%rbp) # 8-byte Spill
movl %r12d, %ebx
leaq 15(,%rbx,4), %rax
andq $-16, %rax
movq %rsp, %r15
subq %rax, %r15
movq %r15, %rsp
movslq %r12d, %r13
leaq (,%r13,4), %rsi
leaq -56(%rbp), %rdi
movq %rsi, -88(%rbp) # 8-byte Spill
callq hipMalloc
leaq -48(%rbp), %rdi
movl $4, %esi
callq hipMalloc
testl %r13d, %r13d
jle .LBB1_4
# %bb.2: # %.lr.ph.preheader
movl %r12d, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltd
idivl %r14d
addl %r13d, %edx
movl %edx, (%r15,%r13,4)
incq %r13
cmpq %r13, %r12
jne .LBB1_3
.LBB1_4: # %._crit_edge
movq -56(%rbp), %rdi
movq %r15, %rsi
movq -88(%rbp), %rdx # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rbx
orq $1, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq -56(%rbp), %rax
movq -48(%rbp), %rcx
movq %rax, -160(%rbp)
movq %rcx, -152(%rbp)
leaq -160(%rbp), %rax
movq %rax, -80(%rbp)
leaq -152(%rbp), %rax
movq %rax, -72(%rbp)
leaq -144(%rbp), %rdi
leaq -128(%rbp), %rsi
leaq -112(%rbp), %rdx
leaq -104(%rbp), %rcx
callq __hipPopCallConfiguration
movq -144(%rbp), %rsi
movl -136(%rbp), %edx
movq -128(%rbp), %rcx
movl -120(%rbp), %r8d
leaq -80(%rbp), %r9
movl $_Z9max_valuePiS_, %edi
pushq -104(%rbp)
pushq -112(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB1_6:
movq -48(%rbp), %rsi
leaq -80(%rbp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl -80(%rbp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq -56(%rbp), %rdi
callq hipFree
movq -48(%rbp), %rdi
callq hipFree
movq -96(%rbp), %rsp # 8-byte Reload
jmp .LBB1_11
.LBB1_7:
jle .LBB1_9
# %bb.8:
movl $.Lstr.1, %edi
jmp .LBB1_10
.LBB1_9:
movl $.Lstr, %edi
.LBB1_10:
callq puts@PLT
.LBB1_11:
xorl %eax, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9max_valuePiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9max_valuePiS_,@object # @_Z9max_valuePiS_
.section .rodata,"a",@progbits
.globl _Z9max_valuePiS_
.p2align 3, 0x0
_Z9max_valuePiS_:
.quad _Z24__device_stub__max_valuePiS_
.size _Z9max_valuePiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nmax = %d "
.size .L.str, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9max_valuePiS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "one argument required"
.size .Lstr, 22
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Too many args to be parsed"
.size .Lstr.1, 27
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__max_valuePiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9max_valuePiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<cuda.h>
#define N 1 //shift/key of cipher
__global__ void encrypt(char *a)
{
a[threadIdx.x]+=N;
if(a[threadIdx.x]>122)
a[threadIdx.x]=200-a[threadIdx.x];
}
__global__ void decrypt(char *a)
{
a[threadIdx.x]-=N;
if(a[threadIdx.x]<97)
a[threadIdx.x]=200-a[threadIdx.x];
}
int main()
{
char a[]="teststring",*b,*c;
c=(char*)malloc(sizeof(a));
cudaMalloc(&b,sizeof(a));
printf("Message : %s\n",a);
cudaMemcpy(b,a,sizeof(a),cudaMemcpyHostToDevice);
encrypt<<<1,sizeof(a)-1>>>(b);
cudaMemcpy(c,b,sizeof(a),cudaMemcpyDeviceToHost);
printf("Encrypted message is : %s\n",c);
decrypt<<<1,sizeof(a)-1>>>(b);
cudaMemcpy(c,b,sizeof(a),cudaMemcpyDeviceToHost);
printf("After decrypting, message is : %s\n",c);
} | code for sm_80
Function : _Z7decryptPc
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IADD3 R2, P0, R2, c[0x0][0x160], RZ ; /* 0x0000580002027a10 */
/* 0x001fca0007f1e0ff */
/*0040*/ IMAD.X R3, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff037624 */
/* 0x000fca00000e06ff */
/*0050*/ LDG.E.U8 R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1100 */
/*0060*/ IADD3 R5, R0, -0x1, RZ ; /* 0xffffffff00057810 */
/* 0x004fe20007ffe0ff */
/*0070*/ IMAD.MOV R0, RZ, RZ, -R0 ; /* 0x000000ffff007224 */
/* 0x000fc600078e0a00 */
/*0080*/ PRMT R4, R5, 0x8880, RZ ; /* 0x0000888005047816 */
/* 0x000fe400000000ff */
/*0090*/ PRMT R0, R0, 0x7710, RZ ; /* 0x0000771000007816 */
/* 0x000fe400000000ff */
/*00a0*/ ISETP.GE.AND P0, PT, R4, 0x61, PT ; /* 0x000000610400780c */
/* 0x000fda0003f06270 */
/*00b0*/ @!P0 IADD3 R5, R0, -0x37, RZ ; /* 0xffffffc900058810 */
/* 0x000fca0007ffe0ff */
/*00c0*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101104 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7encryptPc
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IADD3 R2, P0, R2, c[0x0][0x160], RZ ; /* 0x0000580002027a10 */
/* 0x001fca0007f1e0ff */
/*0040*/ IMAD.X R3, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff037624 */
/* 0x000fca00000e06ff */
/*0050*/ LDG.E.U8 R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1100 */
/*0060*/ IADD3 R5, R0, 0x1, RZ ; /* 0x0000000100057810 */
/* 0x004fe20007ffe0ff */
/*0070*/ IMAD.MOV R0, RZ, RZ, -R0 ; /* 0x000000ffff007224 */
/* 0x000fc600078e0a00 */
/*0080*/ PRMT R4, R5, 0x8880, RZ ; /* 0x0000888005047816 */
/* 0x000fe400000000ff */
/*0090*/ PRMT R0, R0, 0x7710, RZ ; /* 0x0000771000007816 */
/* 0x000fe400000000ff */
/*00a0*/ ISETP.GT.AND P0, PT, R4, 0x7a, PT ; /* 0x0000007a0400780c */
/* 0x000fda0003f04270 */
/*00b0*/ @P0 IADD3 R5, R0, -0x39, RZ ; /* 0xffffffc700050810 */
/* 0x000fca0007ffe0ff */
/*00c0*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101104 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<cuda.h>
#define N 1 //shift/key of cipher
__global__ void encrypt(char *a)
{
a[threadIdx.x]+=N;
if(a[threadIdx.x]>122)
a[threadIdx.x]=200-a[threadIdx.x];
}
__global__ void decrypt(char *a)
{
a[threadIdx.x]-=N;
if(a[threadIdx.x]<97)
a[threadIdx.x]=200-a[threadIdx.x];
}
int main()
{
char a[]="teststring",*b,*c;
c=(char*)malloc(sizeof(a));
cudaMalloc(&b,sizeof(a));
printf("Message : %s\n",a);
cudaMemcpy(b,a,sizeof(a),cudaMemcpyHostToDevice);
encrypt<<<1,sizeof(a)-1>>>(b);
cudaMemcpy(c,b,sizeof(a),cudaMemcpyDeviceToHost);
printf("Encrypted message is : %s\n",c);
decrypt<<<1,sizeof(a)-1>>>(b);
cudaMemcpy(c,b,sizeof(a),cudaMemcpyDeviceToHost);
printf("After decrypting, message is : %s\n",c);
} | .file "tmpxft_0018f681_00000000-6_caesar_cipher.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z7encryptPcPc
.type _Z26__device_stub__Z7encryptPcPc, @function
_Z26__device_stub__Z7encryptPcPc:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7encryptPc(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z7encryptPcPc, .-_Z26__device_stub__Z7encryptPcPc
.globl _Z7encryptPc
.type _Z7encryptPc, @function
_Z7encryptPc:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z7encryptPcPc
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7encryptPc, .-_Z7encryptPc
.globl _Z26__device_stub__Z7decryptPcPc
.type _Z26__device_stub__Z7decryptPcPc, @function
_Z26__device_stub__Z7decryptPcPc:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7decryptPc(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z26__device_stub__Z7decryptPcPc, .-_Z26__device_stub__Z7decryptPcPc
.globl _Z7decryptPc
.type _Z7decryptPc, @function
_Z7decryptPc:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z7decryptPcPc
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z7decryptPc, .-_Z7decryptPc
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Message : %s\n"
.LC1:
.string "Encrypted message is : %s\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "After decrypting, message is : %s\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movabsq $7598263560551228788, %rax
movq %rax, 45(%rsp)
movl $6778473, 52(%rsp)
movl $11, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $11, %esi
call cudaMalloc@PLT
leaq 45(%rsp), %rbp
movq %rbp, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movl $11, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $10, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movl $2, %ecx
movl $11, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $10, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movl $2, %ecx
movl $11, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z26__device_stub__Z7encryptPcPc
jmp .L20
.L25:
movq 8(%rsp), %rdi
call _Z26__device_stub__Z7decryptPcPc
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z7decryptPc"
.LC4:
.string "_Z7encryptPc"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z7decryptPc(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z7encryptPc(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<cuda.h>
#define N 1 //shift/key of cipher
__global__ void encrypt(char *a)
{
a[threadIdx.x]+=N;
if(a[threadIdx.x]>122)
a[threadIdx.x]=200-a[threadIdx.x];
}
__global__ void decrypt(char *a)
{
a[threadIdx.x]-=N;
if(a[threadIdx.x]<97)
a[threadIdx.x]=200-a[threadIdx.x];
}
int main()
{
char a[]="teststring",*b,*c;
c=(char*)malloc(sizeof(a));
cudaMalloc(&b,sizeof(a));
printf("Message : %s\n",a);
cudaMemcpy(b,a,sizeof(a),cudaMemcpyHostToDevice);
encrypt<<<1,sizeof(a)-1>>>(b);
cudaMemcpy(c,b,sizeof(a),cudaMemcpyDeviceToHost);
printf("Encrypted message is : %s\n",c);
decrypt<<<1,sizeof(a)-1>>>(b);
cudaMemcpy(c,b,sizeof(a),cudaMemcpyDeviceToHost);
printf("After decrypting, message is : %s\n",c);
} | #include<stdio.h>
#include<hip/hip_runtime.h>
#define N 1 //shift/key of cipher
__global__ void encrypt(char *a)
{
a[threadIdx.x]+=N;
if(a[threadIdx.x]>122)
a[threadIdx.x]=200-a[threadIdx.x];
}
__global__ void decrypt(char *a)
{
a[threadIdx.x]-=N;
if(a[threadIdx.x]<97)
a[threadIdx.x]=200-a[threadIdx.x];
}
int main()
{
char a[]="teststring",*b,*c;
c=(char*)malloc(sizeof(a));
hipMalloc(&b,sizeof(a));
printf("Message : %s\n",a);
hipMemcpy(b,a,sizeof(a),hipMemcpyHostToDevice);
encrypt<<<1,sizeof(a)-1>>>(b);
hipMemcpy(c,b,sizeof(a),hipMemcpyDeviceToHost);
printf("Encrypted message is : %s\n",c);
decrypt<<<1,sizeof(a)-1>>>(b);
hipMemcpy(c,b,sizeof(a),hipMemcpyDeviceToHost);
printf("After decrypting, message is : %s\n",c);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include<stdio.h>
#include<hip/hip_runtime.h>
#define N 1 //shift/key of cipher
__global__ void encrypt(char *a)
{
a[threadIdx.x]+=N;
if(a[threadIdx.x]>122)
a[threadIdx.x]=200-a[threadIdx.x];
}
__global__ void decrypt(char *a)
{
a[threadIdx.x]-=N;
if(a[threadIdx.x]<97)
a[threadIdx.x]=200-a[threadIdx.x];
}
int main()
{
char a[]="teststring",*b,*c;
c=(char*)malloc(sizeof(a));
hipMalloc(&b,sizeof(a));
printf("Message : %s\n",a);
hipMemcpy(b,a,sizeof(a),hipMemcpyHostToDevice);
encrypt<<<1,sizeof(a)-1>>>(b);
hipMemcpy(c,b,sizeof(a),hipMemcpyDeviceToHost);
printf("Encrypted message is : %s\n",c);
decrypt<<<1,sizeof(a)-1>>>(b);
hipMemcpy(c,b,sizeof(a),hipMemcpyDeviceToHost);
printf("After decrypting, message is : %s\n",c);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7encryptPc
.globl _Z7encryptPc
.p2align 8
.type _Z7encryptPc,@function
_Z7encryptPc:
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
global_load_u8 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u16 v2, v1, 1
v_sub_nc_u16 v1, 0xffc7, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_bfe_i32 v3, v2, 0, 8
v_cmp_lt_i16_e32 vcc_lo, 0x7a, v3
s_delay_alu instid0(VALU_DEP_3)
v_cndmask_b32_e32 v1, v2, v1, vcc_lo
global_store_b8 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7encryptPc
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 2
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7encryptPc, .Lfunc_end0-_Z7encryptPc
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7decryptPc
.globl _Z7decryptPc
.p2align 8
.type _Z7decryptPc,@function
_Z7decryptPc:
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
global_load_u8 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u16 v2, v1, -1
v_sub_nc_u16 v1, 0xffc9, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_bfe_i32 v3, v2, 0, 8
v_cmp_gt_i16_e32 vcc_lo, 0x61, v3
s_delay_alu instid0(VALU_DEP_3)
v_cndmask_b32_e32 v1, v2, v1, vcc_lo
global_store_b8 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7decryptPc
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 2
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7decryptPc, .Lfunc_end1-_Z7decryptPc
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7encryptPc
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z7encryptPc.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7decryptPc
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z7decryptPc.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<stdio.h>
#include<hip/hip_runtime.h>
#define N 1 //shift/key of cipher
__global__ void encrypt(char *a)
{
a[threadIdx.x]+=N;
if(a[threadIdx.x]>122)
a[threadIdx.x]=200-a[threadIdx.x];
}
__global__ void decrypt(char *a)
{
a[threadIdx.x]-=N;
if(a[threadIdx.x]<97)
a[threadIdx.x]=200-a[threadIdx.x];
}
int main()
{
char a[]="teststring",*b,*c;
c=(char*)malloc(sizeof(a));
hipMalloc(&b,sizeof(a));
printf("Message : %s\n",a);
hipMemcpy(b,a,sizeof(a),hipMemcpyHostToDevice);
encrypt<<<1,sizeof(a)-1>>>(b);
hipMemcpy(c,b,sizeof(a),hipMemcpyDeviceToHost);
printf("Encrypted message is : %s\n",c);
decrypt<<<1,sizeof(a)-1>>>(b);
hipMemcpy(c,b,sizeof(a),hipMemcpyDeviceToHost);
printf("After decrypting, message is : %s\n",c);
} | .text
.file "caesar_cipher.hip"
.globl _Z22__device_stub__encryptPc # -- Begin function _Z22__device_stub__encryptPc
.p2align 4, 0x90
.type _Z22__device_stub__encryptPc,@function
_Z22__device_stub__encryptPc: # @_Z22__device_stub__encryptPc
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z7encryptPc, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z22__device_stub__encryptPc, .Lfunc_end0-_Z22__device_stub__encryptPc
.cfi_endproc
# -- End function
.globl _Z22__device_stub__decryptPc # -- Begin function _Z22__device_stub__decryptPc
.p2align 4, 0x90
.type _Z22__device_stub__decryptPc,@function
_Z22__device_stub__decryptPc: # @_Z22__device_stub__decryptPc
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z7decryptPc, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z22__device_stub__decryptPc, .Lfunc_end1-_Z22__device_stub__decryptPc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $96, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movabsq $4294967297, %r14 # imm = 0x100000001
movabsq $7598263560551228788, %rax # imm = 0x6972747374736574
movq %rax, 85(%rsp)
movw $26478, 93(%rsp) # imm = 0x676E
movb $0, 95(%rsp)
movl $11, %edi
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $11, %esi
callq hipMalloc
leaq 85(%rsp), %r15
movl $.L.str, %edi
movq %r15, %rsi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
movl $11, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 9(%r14), %r15
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z7encryptPc, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq 8(%rsp), %rsi
movl $11, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z7decryptPc, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq 8(%rsp), %rsi
movl $11, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str.2, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7encryptPc, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7decryptPc, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7encryptPc,@object # @_Z7encryptPc
.section .rodata,"a",@progbits
.globl _Z7encryptPc
.p2align 3, 0x0
_Z7encryptPc:
.quad _Z22__device_stub__encryptPc
.size _Z7encryptPc, 8
.type _Z7decryptPc,@object # @_Z7decryptPc
.globl _Z7decryptPc
.p2align 3, 0x0
_Z7decryptPc:
.quad _Z22__device_stub__decryptPc
.size _Z7decryptPc, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Message : %s\n"
.size .L.str, 14
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Encrypted message is : %s\n"
.size .L.str.1, 27
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "After decrypting, message is : %s\n"
.size .L.str.2, 35
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7encryptPc"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7decryptPc"
.size .L__unnamed_2, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__encryptPc
.addrsig_sym _Z22__device_stub__decryptPc
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7encryptPc
.addrsig_sym _Z7decryptPc
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7decryptPc
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IADD3 R2, P0, R2, c[0x0][0x160], RZ ; /* 0x0000580002027a10 */
/* 0x001fca0007f1e0ff */
/*0040*/ IMAD.X R3, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff037624 */
/* 0x000fca00000e06ff */
/*0050*/ LDG.E.U8 R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1100 */
/*0060*/ IADD3 R5, R0, -0x1, RZ ; /* 0xffffffff00057810 */
/* 0x004fe20007ffe0ff */
/*0070*/ IMAD.MOV R0, RZ, RZ, -R0 ; /* 0x000000ffff007224 */
/* 0x000fc600078e0a00 */
/*0080*/ PRMT R4, R5, 0x8880, RZ ; /* 0x0000888005047816 */
/* 0x000fe400000000ff */
/*0090*/ PRMT R0, R0, 0x7710, RZ ; /* 0x0000771000007816 */
/* 0x000fe400000000ff */
/*00a0*/ ISETP.GE.AND P0, PT, R4, 0x61, PT ; /* 0x000000610400780c */
/* 0x000fda0003f06270 */
/*00b0*/ @!P0 IADD3 R5, R0, -0x37, RZ ; /* 0xffffffc900058810 */
/* 0x000fca0007ffe0ff */
/*00c0*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101104 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7encryptPc
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IADD3 R2, P0, R2, c[0x0][0x160], RZ ; /* 0x0000580002027a10 */
/* 0x001fca0007f1e0ff */
/*0040*/ IMAD.X R3, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff037624 */
/* 0x000fca00000e06ff */
/*0050*/ LDG.E.U8 R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1100 */
/*0060*/ IADD3 R5, R0, 0x1, RZ ; /* 0x0000000100057810 */
/* 0x004fe20007ffe0ff */
/*0070*/ IMAD.MOV R0, RZ, RZ, -R0 ; /* 0x000000ffff007224 */
/* 0x000fc600078e0a00 */
/*0080*/ PRMT R4, R5, 0x8880, RZ ; /* 0x0000888005047816 */
/* 0x000fe400000000ff */
/*0090*/ PRMT R0, R0, 0x7710, RZ ; /* 0x0000771000007816 */
/* 0x000fe400000000ff */
/*00a0*/ ISETP.GT.AND P0, PT, R4, 0x7a, PT ; /* 0x0000007a0400780c */
/* 0x000fda0003f04270 */
/*00b0*/ @P0 IADD3 R5, R0, -0x39, RZ ; /* 0xffffffc700050810 */
/* 0x000fca0007ffe0ff */
/*00c0*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101104 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7encryptPc
.globl _Z7encryptPc
.p2align 8
.type _Z7encryptPc,@function
_Z7encryptPc:
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
global_load_u8 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u16 v2, v1, 1
v_sub_nc_u16 v1, 0xffc7, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_bfe_i32 v3, v2, 0, 8
v_cmp_lt_i16_e32 vcc_lo, 0x7a, v3
s_delay_alu instid0(VALU_DEP_3)
v_cndmask_b32_e32 v1, v2, v1, vcc_lo
global_store_b8 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7encryptPc
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 2
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7encryptPc, .Lfunc_end0-_Z7encryptPc
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7decryptPc
.globl _Z7decryptPc
.p2align 8
.type _Z7decryptPc,@function
_Z7decryptPc:
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
global_load_u8 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u16 v2, v1, -1
v_sub_nc_u16 v1, 0xffc9, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_bfe_i32 v3, v2, 0, 8
v_cmp_gt_i16_e32 vcc_lo, 0x61, v3
s_delay_alu instid0(VALU_DEP_3)
v_cndmask_b32_e32 v1, v2, v1, vcc_lo
global_store_b8 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7decryptPc
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 2
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7decryptPc, .Lfunc_end1-_Z7decryptPc
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7encryptPc
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z7encryptPc.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7decryptPc
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z7decryptPc.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018f681_00000000-6_caesar_cipher.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z7encryptPcPc
.type _Z26__device_stub__Z7encryptPcPc, @function
_Z26__device_stub__Z7encryptPcPc:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7encryptPc(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z7encryptPcPc, .-_Z26__device_stub__Z7encryptPcPc
.globl _Z7encryptPc
.type _Z7encryptPc, @function
_Z7encryptPc:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z7encryptPcPc
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7encryptPc, .-_Z7encryptPc
.globl _Z26__device_stub__Z7decryptPcPc
.type _Z26__device_stub__Z7decryptPcPc, @function
_Z26__device_stub__Z7decryptPcPc:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7decryptPc(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z26__device_stub__Z7decryptPcPc, .-_Z26__device_stub__Z7decryptPcPc
.globl _Z7decryptPc
.type _Z7decryptPc, @function
_Z7decryptPc:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z7decryptPcPc
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z7decryptPc, .-_Z7decryptPc
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Message : %s\n"
.LC1:
.string "Encrypted message is : %s\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "After decrypting, message is : %s\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movabsq $7598263560551228788, %rax
movq %rax, 45(%rsp)
movl $6778473, 52(%rsp)
movl $11, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $11, %esi
call cudaMalloc@PLT
leaq 45(%rsp), %rbp
movq %rbp, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movl $11, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $10, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movl $2, %ecx
movl $11, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $10, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movl $2, %ecx
movl $11, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z26__device_stub__Z7encryptPcPc
jmp .L20
.L25:
movq 8(%rsp), %rdi
call _Z26__device_stub__Z7decryptPcPc
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z7decryptPc"
.LC4:
.string "_Z7encryptPc"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z7decryptPc(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z7encryptPc(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "caesar_cipher.hip"
.globl _Z22__device_stub__encryptPc # -- Begin function _Z22__device_stub__encryptPc
.p2align 4, 0x90
.type _Z22__device_stub__encryptPc,@function
_Z22__device_stub__encryptPc: # @_Z22__device_stub__encryptPc
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z7encryptPc, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z22__device_stub__encryptPc, .Lfunc_end0-_Z22__device_stub__encryptPc
.cfi_endproc
# -- End function
.globl _Z22__device_stub__decryptPc # -- Begin function _Z22__device_stub__decryptPc
.p2align 4, 0x90
.type _Z22__device_stub__decryptPc,@function
_Z22__device_stub__decryptPc: # @_Z22__device_stub__decryptPc
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z7decryptPc, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z22__device_stub__decryptPc, .Lfunc_end1-_Z22__device_stub__decryptPc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $96, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movabsq $4294967297, %r14 # imm = 0x100000001
movabsq $7598263560551228788, %rax # imm = 0x6972747374736574
movq %rax, 85(%rsp)
movw $26478, 93(%rsp) # imm = 0x676E
movb $0, 95(%rsp)
movl $11, %edi
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $11, %esi
callq hipMalloc
leaq 85(%rsp), %r15
movl $.L.str, %edi
movq %r15, %rsi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
movl $11, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 9(%r14), %r15
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z7encryptPc, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq 8(%rsp), %rsi
movl $11, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z7decryptPc, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq 8(%rsp), %rsi
movl $11, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str.2, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7encryptPc, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7decryptPc, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7encryptPc,@object # @_Z7encryptPc
.section .rodata,"a",@progbits
.globl _Z7encryptPc
.p2align 3, 0x0
_Z7encryptPc:
.quad _Z22__device_stub__encryptPc
.size _Z7encryptPc, 8
.type _Z7decryptPc,@object # @_Z7decryptPc
.globl _Z7decryptPc
.p2align 3, 0x0
_Z7decryptPc:
.quad _Z22__device_stub__decryptPc
.size _Z7decryptPc, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Message : %s\n"
.size .L.str, 14
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Encrypted message is : %s\n"
.size .L.str.1, 27
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "After decrypting, message is : %s\n"
.size .L.str.2, 35
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7encryptPc"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7decryptPc"
.size .L__unnamed_2, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__encryptPc
.addrsig_sym _Z22__device_stub__decryptPc
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7encryptPc
.addrsig_sym _Z7decryptPc
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* Copyright (C) 2010, Florian Kummer, Technische Universitaet Darmstadt, Fachgebiet fuer Stroemungsmechanik
*
* Use, modification and distribution is subject to the Boost Software
* License, Version 1.0. (See accompanying file LICENSE_1_0.txt or copy at
* http://www.boost.org/LICENSE_1_0.txt)
*
* Authors: Christoph Busold
*
*/
extern __shared__ char smem[];
extern "C" __global__ void sparseMultiply(double* values, int* colIdx, int* rowStart, double* result, double* x, double alpha, double beta, int size) {
// Dynamically allocated shared memory, should be BlockDim.x + 1 ints (see cuFuncSetSharedSize host code)
int* sharedRowStart = (int*)smem;
// Indices
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int tid = threadIdx.x;
double rowacc = 0.0;
// Each thread loads one element of rowStart
if(idx < size) {
sharedRowStart[tid] = rowStart[idx];
}
// The first thread loads additionally the next element, needed by the last thread
if(tid == 0) {
int loadIdx = min((blockIdx.x + 1) * blockDim.x, size);
int storIdx = size % blockDim.x > 0 && idx + blockDim.x >= size ? size % blockDim.x : blockDim.x;
sharedRowStart[storIdx] = rowStart[loadIdx];
}
__syncthreads();
if(idx < size) {
// Multiply and sum up data of this row
for(int i = sharedRowStart[tid]; i < sharedRowStart[tid + 1]; i++) {
rowacc += values[i] * x[colIdx[i]];
}
result[idx] = result[idx] * beta + rowacc * alpha;
}
}
extern "C" __global__ void accumulateExternal(double* data, int* indices, double* rcvBuffer, double alpha, int size) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(idx < size) {
data[indices[idx]] += rcvBuffer[idx] * alpha;
}
}
// In this kernel each block computes multiple cell rows
// IMPORTANT: All cell rows must have the same number of cells!
// Otherwise sync in kernel might fail, causing crash or incorrect behaviour!
extern "C" __global__ void blockMultiply2(double* cellData, double* xData, int* cellColIdx, double* result, double alpha, double beta, int cellsize, int cellrowsperblock, int cellsperrow, int stride, int size) {
// Dynamically allocated shared memory, should be blockDim.x doubles for xData
double* sharedData = (double*)smem;
// Start cell index of this thread
int* start = (int*)&sharedData[blockDim.x];
// Column of this thread's cell
int* colIdx = (int*)&start[cellrowsperblock];
// Global index
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int tid = threadIdx.x;
// Number of the cell this thread is in
int cellid = tid / cellsize;
// Thread index inside this cell
int cid = tid % cellsize;
double rowacc = 0.0;
double value;
// Load start index for every cell row in this block
if(tid < cellrowsperblock) {
start[tid] = (cellrowsperblock * blockIdx.x + tid) * cellsperrow;
}
__syncthreads();
// Loop over all cells, discard overlapping threads inside because of sync
for(int i = 0; i < cellsperrow; i++) {
// Load column index for every cell
if(tid < cellrowsperblock) {
colIdx[tid] = cellColIdx[start[tid] + i];
}
__syncthreads();
// No overlapping threads
if(idx < size) {
// Load x at colIdx location into shared memory
// colIdx * cellsize is the start index at this column
// cid is the row index of this thread
sharedData[tid] = xData[colIdx[cellid] * cellsize + cid];
}
__syncthreads();
// No overlapping threads
if(idx < size) {
// Loop over all columns of this cell
for(int col = 0; col < cellsize; col++) {
// Load value of this column
// cell * cellsize * cellsize is the start index of the current cell
// col * cellsize is the start index of the current column
// cid is the row index of this thread
value = cellData[(start[cellid] + i) * stride + col * cellsize + cid];
// Multiply value with x from sharedMemory
// cellid * cellsize is the offset for the cell this thread is in
// col is the column index of this loop cycle
rowacc += value * sharedData[cellid * cellsize + col];
}
}
__syncthreads();
}
// No overlapping threads
if(idx < size) {
// Write back result
result[idx] = result[idx] * beta + rowacc * alpha;
}
}
// In this kernel each block computes one cell row (block size equals cell size)
extern "C" __global__ void blockMultiply(double* cellData, double* xData, int* cellColIdx, int* cellRowStart, double* result, double dia, int cellsize, int size) {
double* sharedData = (double*)smem;
__shared__ int colIdx;
__shared__ int start;
__shared__ int end;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int tid = threadIdx.x;
double rowacc = 0.0;
double value;
if(tid == 0) {
start = cellRowStart[blockIdx.x ];
end = cellRowStart[blockIdx.x + 1];
}
__syncthreads();
for(int cell = start; cell < end; cell++) {
if(tid == 0) {
colIdx = cellColIdx[cell];
}
__syncthreads();
if(idx < size) {
sharedData[tid] = xData[colIdx * cellsize + tid];
}
__syncthreads();
if(idx < size) {
for(int col = 0; col < cellsize; col++) {
value = cellData[cell * cellsize * cellsize + col * cellsize + tid];
rowacc += value * sharedData[col];
}
}
}
if(idx < size) {
rowacc += dia * xData[idx];
result[idx] += rowacc;
}
}
// ELLPACKmod format
extern "C" __global__ void ellMultiply(double* valData, int* colIdxData, double* xData, double* result, double alpha, double beta, int size, int colCount, int valStride, int colStride) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
// Add offsets to the start of this block's value and column data pointers
valData += blockIdx.x * colCount * valStride;
colIdxData += blockIdx.x * colCount * colStride;
int valIdx;
int colIdx;
// No sync in this kernel, therefore overlapping threads are discarded here
if(idx < size) {
double rowacc = 0.0;
// Loop over all columns
for(int col = 0; col < colCount; col++) {
// Index of the value and column index to load
valIdx = col * valStride + threadIdx.x;
colIdx = col * colStride + threadIdx.x;
// Load value and multiply with x at column of this value
rowacc += valData[valIdx] * xData[colIdxData[colIdx]];
}
// Write result back
result[idx] = result[idx] * beta + rowacc * alpha;
}
}
// ManualCacheELLPACK format
extern "C" __global__ void mcellMultiply(double* valData, unsigned short* colIdxData, int* xSubStart, int* blockSubVector, double* xData, double* result, double alpha, double beta, int size, int colCount, int valStride, int colStride) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int tid = threadIdx.x;
// Add offsets to the start of this block's value and column data pointers
valData += blockIdx.x * colCount * valStride;
colIdxData += blockIdx.x * colCount * colStride;
double* xSub = (double*)smem;
__shared__ int xStart;
__shared__ int xLength;
int valIdx;
unsigned short colIdx;
if(tid == 0) {
xStart = xSubStart[blockIdx.x ];
xLength = xSubStart[blockIdx.x + 1] - xStart;
}
__syncthreads();
blockSubVector += xStart;
int ldIdx = tid;
while(ldIdx < xLength) {
xSub[ldIdx] = xData[blockSubVector[ldIdx]];
ldIdx += blockDim.x;
}
__syncthreads();
// No sync inside this loop, therefore overlapping threads are discarded here
if(idx < size) {
double rowacc = 0.0;
// Loop over all columns
for(int col = 0; col < colCount; col++) {
// Index of the value and column index to load
valIdx = col * valStride + tid;
colIdx = col * colStride + tid;
// Load value and multiply with x at column of this value
rowacc += valData[valIdx] * xSub[colIdxData[colIdx]];
}
// Write result back
result[idx] = result[idx] * beta + rowacc * alpha;
}
} | .file "tmpxft_000ed811_00000000-6_CudaMatrixKernelDP.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z14sparseMultiplyPdPiS0_S_S_ddiPdPiS0_S_S_ddi
.type _Z46__device_stub__Z14sparseMultiplyPdPiS0_S_S_ddiPdPiS0_S_S_ddi, @function
_Z46__device_stub__Z14sparseMultiplyPdPiS0_S_S_ddiPdPiS0_S_S_ddi:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movsd %xmm0, 16(%rsp)
movsd %xmm1, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 4(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq sparseMultiply(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z14sparseMultiplyPdPiS0_S_S_ddiPdPiS0_S_S_ddi, .-_Z46__device_stub__Z14sparseMultiplyPdPiS0_S_S_ddiPdPiS0_S_S_ddi
.globl sparseMultiply
.type sparseMultiply, @function
sparseMultiply:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z14sparseMultiplyPdPiS0_S_S_ddiPdPiS0_S_S_ddi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size sparseMultiply, .-sparseMultiply
.globl _Z44__device_stub__Z18accumulateExternalPdPiS_diPdPiS_di
.type _Z44__device_stub__Z18accumulateExternalPdPiS_diPdPiS_di, @function
_Z44__device_stub__Z18accumulateExternalPdPiS_diPdPiS_di:
.LFB2053:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movsd %xmm0, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq accumulateExternal(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z44__device_stub__Z18accumulateExternalPdPiS_diPdPiS_di, .-_Z44__device_stub__Z18accumulateExternalPdPiS_diPdPiS_di
.globl accumulateExternal
.type accumulateExternal, @function
accumulateExternal:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z18accumulateExternalPdPiS_diPdPiS_di
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size accumulateExternal, .-accumulateExternal
.globl _Z47__device_stub__Z14blockMultiply2PdS_PiS_ddiiiiiPdS_PiS_ddiiiii
.type _Z47__device_stub__Z14blockMultiply2PdS_PiS_ddiiiiiPdS_PiS_ddiiiii, @function
_Z47__device_stub__Z14blockMultiply2PdS_PiS_ddiiiiiPdS_PiS_ddiiiii:
.LFB2055:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movsd %xmm0, 24(%rsp)
movsd %xmm1, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
leaq 240(%rsp), %rax
movq %rax, 192(%rsp)
leaq 248(%rsp), %rax
movq %rax, 200(%rsp)
leaq 256(%rsp), %rax
movq %rax, 208(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq blockMultiply2(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z47__device_stub__Z14blockMultiply2PdS_PiS_ddiiiiiPdS_PiS_ddiiiii, .-_Z47__device_stub__Z14blockMultiply2PdS_PiS_ddiiiiiPdS_PiS_ddiiiii
.globl blockMultiply2
.type blockMultiply2, @function
blockMultiply2:
.LFB2056:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z47__device_stub__Z14blockMultiply2PdS_PiS_ddiiiiiPdS_PiS_ddiiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size blockMultiply2, .-blockMultiply2
.globl _Z45__device_stub__Z13blockMultiplyPdS_PiS0_S_diiPdS_PiS0_S_dii
.type _Z45__device_stub__Z13blockMultiplyPdS_PiS0_S_diiPdS_PiS0_S_dii, @function
_Z45__device_stub__Z13blockMultiplyPdS_PiS0_S_diiPdS_PiS0_S_dii:
.LFB2057:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movsd %xmm0, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 224(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq blockMultiply(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z45__device_stub__Z13blockMultiplyPdS_PiS0_S_diiPdS_PiS0_S_dii, .-_Z45__device_stub__Z13blockMultiplyPdS_PiS0_S_diiPdS_PiS0_S_dii
.globl blockMultiply
.type blockMultiply, @function
blockMultiply:
.LFB2058:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z45__device_stub__Z13blockMultiplyPdS_PiS0_S_diiPdS_PiS0_S_dii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size blockMultiply, .-blockMultiply
.globl _Z43__device_stub__Z11ellMultiplyPdPiS_S_ddiiiiPdPiS_S_ddiiii
.type _Z43__device_stub__Z11ellMultiplyPdPiS_S_ddiiiiPdPiS_S_ddiiii, @function
_Z43__device_stub__Z11ellMultiplyPdPiS_S_ddiiiiPdPiS_S_ddiiii:
.LFB2059:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movsd %xmm0, 24(%rsp)
movsd %xmm1, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
leaq 240(%rsp), %rax
movq %rax, 192(%rsp)
leaq 248(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq ellMultiply(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z43__device_stub__Z11ellMultiplyPdPiS_S_ddiiiiPdPiS_S_ddiiii, .-_Z43__device_stub__Z11ellMultiplyPdPiS_S_ddiiiiPdPiS_S_ddiiii
.globl ellMultiply
.type ellMultiply, @function
ellMultiply:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z43__device_stub__Z11ellMultiplyPdPiS_S_ddiiiiPdPiS_S_ddiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size ellMultiply, .-ellMultiply
.globl _Z50__device_stub__Z13mcellMultiplyPdPtPiS1_S_S_ddiiiiPdPtPiS1_S_S_ddiiii
.type _Z50__device_stub__Z13mcellMultiplyPdPtPiS1_S_S_ddiiiiPdPtPiS1_S_S_ddiiii, @function
_Z50__device_stub__Z13mcellMultiplyPdPtPiS1_S_S_ddiiiiPdPtPiS1_S_S_ddiiii:
.LFB2061:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movsd %xmm0, 8(%rsp)
movsd %xmm1, (%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movq %rsp, %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 264(%rsp), %rax
movq %rax, 200(%rsp)
leaq 272(%rsp), %rax
movq %rax, 208(%rsp)
leaq 280(%rsp), %rax
movq %rax, 216(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 264
pushq 72(%rsp)
.cfi_def_cfa_offset 272
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq mcellMultiply(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z50__device_stub__Z13mcellMultiplyPdPtPiS1_S_S_ddiiiiPdPtPiS1_S_S_ddiiii, .-_Z50__device_stub__Z13mcellMultiplyPdPtPiS1_S_S_ddiiiiPdPtPiS1_S_S_ddiiii
.globl mcellMultiply
.type mcellMultiply, @function
mcellMultiply:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z50__device_stub__Z13mcellMultiplyPdPtPiS1_S_S_ddiiiiPdPtPiS1_S_S_ddiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size mcellMultiply, .-mcellMultiply
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "mcellMultiply"
.LC1:
.string "ellMultiply"
.LC2:
.string "blockMultiply"
.LC3:
.string "blockMultiply2"
.LC4:
.string "accumulateExternal"
.LC5:
.string "sparseMultiply"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2064:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq mcellMultiply(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq ellMultiply(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq blockMultiply(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq blockMultiply2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq accumulateExternal(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq sparseMultiply(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Copyright (C) 2010, Florian Kummer, Technische Universitaet Darmstadt, Fachgebiet fuer Stroemungsmechanik
*
* Use, modification and distribution is subject to the Boost Software
* License, Version 1.0. (See accompanying file LICENSE_1_0.txt or copy at
* http://www.boost.org/LICENSE_1_0.txt)
*
* Authors: Christoph Busold
*
*/
extern __shared__ char smem[];
extern "C" __global__ void sparseMultiply(double* values, int* colIdx, int* rowStart, double* result, double* x, double alpha, double beta, int size) {
// Dynamically allocated shared memory, should be BlockDim.x + 1 ints (see cuFuncSetSharedSize host code)
int* sharedRowStart = (int*)smem;
// Indices
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int tid = threadIdx.x;
double rowacc = 0.0;
// Each thread loads one element of rowStart
if(idx < size) {
sharedRowStart[tid] = rowStart[idx];
}
// The first thread loads additionally the next element, needed by the last thread
if(tid == 0) {
int loadIdx = min((blockIdx.x + 1) * blockDim.x, size);
int storIdx = size % blockDim.x > 0 && idx + blockDim.x >= size ? size % blockDim.x : blockDim.x;
sharedRowStart[storIdx] = rowStart[loadIdx];
}
__syncthreads();
if(idx < size) {
// Multiply and sum up data of this row
for(int i = sharedRowStart[tid]; i < sharedRowStart[tid + 1]; i++) {
rowacc += values[i] * x[colIdx[i]];
}
result[idx] = result[idx] * beta + rowacc * alpha;
}
}
extern "C" __global__ void accumulateExternal(double* data, int* indices, double* rcvBuffer, double alpha, int size) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(idx < size) {
data[indices[idx]] += rcvBuffer[idx] * alpha;
}
}
// In this kernel each block computes multiple cell rows
// IMPORTANT: All cell rows must have the same number of cells!
// Otherwise sync in kernel might fail, causing crash or incorrect behaviour!
extern "C" __global__ void blockMultiply2(double* cellData, double* xData, int* cellColIdx, double* result, double alpha, double beta, int cellsize, int cellrowsperblock, int cellsperrow, int stride, int size) {
// Dynamically allocated shared memory, should be blockDim.x doubles for xData
double* sharedData = (double*)smem;
// Start cell index of this thread
int* start = (int*)&sharedData[blockDim.x];
// Column of this thread's cell
int* colIdx = (int*)&start[cellrowsperblock];
// Global index
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int tid = threadIdx.x;
// Number of the cell this thread is in
int cellid = tid / cellsize;
// Thread index inside this cell
int cid = tid % cellsize;
double rowacc = 0.0;
double value;
// Load start index for every cell row in this block
if(tid < cellrowsperblock) {
start[tid] = (cellrowsperblock * blockIdx.x + tid) * cellsperrow;
}
__syncthreads();
// Loop over all cells, discard overlapping threads inside because of sync
for(int i = 0; i < cellsperrow; i++) {
// Load column index for every cell
if(tid < cellrowsperblock) {
colIdx[tid] = cellColIdx[start[tid] + i];
}
__syncthreads();
// No overlapping threads
if(idx < size) {
// Load x at colIdx location into shared memory
// colIdx * cellsize is the start index at this column
// cid is the row index of this thread
sharedData[tid] = xData[colIdx[cellid] * cellsize + cid];
}
__syncthreads();
// No overlapping threads
if(idx < size) {
// Loop over all columns of this cell
for(int col = 0; col < cellsize; col++) {
// Load value of this column
// cell * cellsize * cellsize is the start index of the current cell
// col * cellsize is the start index of the current column
// cid is the row index of this thread
value = cellData[(start[cellid] + i) * stride + col * cellsize + cid];
// Multiply value with x from sharedMemory
// cellid * cellsize is the offset for the cell this thread is in
// col is the column index of this loop cycle
rowacc += value * sharedData[cellid * cellsize + col];
}
}
__syncthreads();
}
// No overlapping threads
if(idx < size) {
// Write back result
result[idx] = result[idx] * beta + rowacc * alpha;
}
}
// In this kernel each block computes one cell row (block size equals cell size)
extern "C" __global__ void blockMultiply(double* cellData, double* xData, int* cellColIdx, int* cellRowStart, double* result, double dia, int cellsize, int size) {
double* sharedData = (double*)smem;
__shared__ int colIdx;
__shared__ int start;
__shared__ int end;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int tid = threadIdx.x;
double rowacc = 0.0;
double value;
if(tid == 0) {
start = cellRowStart[blockIdx.x ];
end = cellRowStart[blockIdx.x + 1];
}
__syncthreads();
for(int cell = start; cell < end; cell++) {
if(tid == 0) {
colIdx = cellColIdx[cell];
}
__syncthreads();
if(idx < size) {
sharedData[tid] = xData[colIdx * cellsize + tid];
}
__syncthreads();
if(idx < size) {
for(int col = 0; col < cellsize; col++) {
value = cellData[cell * cellsize * cellsize + col * cellsize + tid];
rowacc += value * sharedData[col];
}
}
}
if(idx < size) {
rowacc += dia * xData[idx];
result[idx] += rowacc;
}
}
// ELLPACKmod format
extern "C" __global__ void ellMultiply(double* valData, int* colIdxData, double* xData, double* result, double alpha, double beta, int size, int colCount, int valStride, int colStride) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
// Add offsets to the start of this block's value and column data pointers
valData += blockIdx.x * colCount * valStride;
colIdxData += blockIdx.x * colCount * colStride;
int valIdx;
int colIdx;
// No sync in this kernel, therefore overlapping threads are discarded here
if(idx < size) {
double rowacc = 0.0;
// Loop over all columns
for(int col = 0; col < colCount; col++) {
// Index of the value and column index to load
valIdx = col * valStride + threadIdx.x;
colIdx = col * colStride + threadIdx.x;
// Load value and multiply with x at column of this value
rowacc += valData[valIdx] * xData[colIdxData[colIdx]];
}
// Write result back
result[idx] = result[idx] * beta + rowacc * alpha;
}
}
// ManualCacheELLPACK format
extern "C" __global__ void mcellMultiply(double* valData, unsigned short* colIdxData, int* xSubStart, int* blockSubVector, double* xData, double* result, double alpha, double beta, int size, int colCount, int valStride, int colStride) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int tid = threadIdx.x;
// Add offsets to the start of this block's value and column data pointers
valData += blockIdx.x * colCount * valStride;
colIdxData += blockIdx.x * colCount * colStride;
double* xSub = (double*)smem;
__shared__ int xStart;
__shared__ int xLength;
int valIdx;
unsigned short colIdx;
if(tid == 0) {
xStart = xSubStart[blockIdx.x ];
xLength = xSubStart[blockIdx.x + 1] - xStart;
}
__syncthreads();
blockSubVector += xStart;
int ldIdx = tid;
while(ldIdx < xLength) {
xSub[ldIdx] = xData[blockSubVector[ldIdx]];
ldIdx += blockDim.x;
}
__syncthreads();
// No sync inside this loop, therefore overlapping threads are discarded here
if(idx < size) {
double rowacc = 0.0;
// Loop over all columns
for(int col = 0; col < colCount; col++) {
// Index of the value and column index to load
valIdx = col * valStride + tid;
colIdx = col * colStride + tid;
// Load value and multiply with x at column of this value
rowacc += valData[valIdx] * xSub[colIdxData[colIdx]];
}
// Write result back
result[idx] = result[idx] * beta + rowacc * alpha;
}
} | #include <hip/hip_runtime.h>
/*
* Copyright (C) 2010, Florian Kummer, Technische Universitaet Darmstadt, Fachgebiet fuer Stroemungsmechanik
*
* Use, modification and distribution is subject to the Boost Software
* License, Version 1.0. (See accompanying file LICENSE_1_0.txt or copy at
* http://www.boost.org/LICENSE_1_0.txt)
*
* Authors: Christoph Busold
*
*/
extern __shared__ char smem[];
extern "C" __global__ void sparseMultiply(double* values, int* colIdx, int* rowStart, double* result, double* x, double alpha, double beta, int size) {
// Dynamically allocated shared memory, should be BlockDim.x + 1 ints (see cuFuncSetSharedSize host code)
int* sharedRowStart = (int*)smem;
// Indices
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int tid = threadIdx.x;
double rowacc = 0.0;
// Each thread loads one element of rowStart
if(idx < size) {
sharedRowStart[tid] = rowStart[idx];
}
// The first thread loads additionally the next element, needed by the last thread
if(tid == 0) {
int loadIdx = min((blockIdx.x + 1) * blockDim.x, size);
int storIdx = size % blockDim.x > 0 && idx + blockDim.x >= size ? size % blockDim.x : blockDim.x;
sharedRowStart[storIdx] = rowStart[loadIdx];
}
__syncthreads();
if(idx < size) {
// Multiply and sum up data of this row
for(int i = sharedRowStart[tid]; i < sharedRowStart[tid + 1]; i++) {
rowacc += values[i] * x[colIdx[i]];
}
result[idx] = result[idx] * beta + rowacc * alpha;
}
}
extern "C" __global__ void accumulateExternal(double* data, int* indices, double* rcvBuffer, double alpha, int size) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(idx < size) {
data[indices[idx]] += rcvBuffer[idx] * alpha;
}
}
// In this kernel each block computes multiple cell rows
// IMPORTANT: All cell rows must have the same number of cells!
// Otherwise sync in kernel might fail, causing crash or incorrect behaviour!
extern "C" __global__ void blockMultiply2(double* cellData, double* xData, int* cellColIdx, double* result, double alpha, double beta, int cellsize, int cellrowsperblock, int cellsperrow, int stride, int size) {
// Dynamically allocated shared memory, should be blockDim.x doubles for xData
double* sharedData = (double*)smem;
// Start cell index of this thread
int* start = (int*)&sharedData[blockDim.x];
// Column of this thread's cell
int* colIdx = (int*)&start[cellrowsperblock];
// Global index
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int tid = threadIdx.x;
// Number of the cell this thread is in
int cellid = tid / cellsize;
// Thread index inside this cell
int cid = tid % cellsize;
double rowacc = 0.0;
double value;
// Load start index for every cell row in this block
if(tid < cellrowsperblock) {
start[tid] = (cellrowsperblock * blockIdx.x + tid) * cellsperrow;
}
__syncthreads();
// Loop over all cells, discard overlapping threads inside because of sync
for(int i = 0; i < cellsperrow; i++) {
// Load column index for every cell
if(tid < cellrowsperblock) {
colIdx[tid] = cellColIdx[start[tid] + i];
}
__syncthreads();
// No overlapping threads
if(idx < size) {
// Load x at colIdx location into shared memory
// colIdx * cellsize is the start index at this column
// cid is the row index of this thread
sharedData[tid] = xData[colIdx[cellid] * cellsize + cid];
}
__syncthreads();
// No overlapping threads
if(idx < size) {
// Loop over all columns of this cell
for(int col = 0; col < cellsize; col++) {
// Load value of this column
// cell * cellsize * cellsize is the start index of the current cell
// col * cellsize is the start index of the current column
// cid is the row index of this thread
value = cellData[(start[cellid] + i) * stride + col * cellsize + cid];
// Multiply value with x from sharedMemory
// cellid * cellsize is the offset for the cell this thread is in
// col is the column index of this loop cycle
rowacc += value * sharedData[cellid * cellsize + col];
}
}
__syncthreads();
}
// No overlapping threads
if(idx < size) {
// Write back result
result[idx] = result[idx] * beta + rowacc * alpha;
}
}
// In this kernel each block computes one cell row (block size equals cell size)
extern "C" __global__ void blockMultiply(double* cellData, double* xData, int* cellColIdx, int* cellRowStart, double* result, double dia, int cellsize, int size) {
double* sharedData = (double*)smem;
__shared__ int colIdx;
__shared__ int start;
__shared__ int end;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int tid = threadIdx.x;
double rowacc = 0.0;
double value;
if(tid == 0) {
start = cellRowStart[blockIdx.x ];
end = cellRowStart[blockIdx.x + 1];
}
__syncthreads();
for(int cell = start; cell < end; cell++) {
if(tid == 0) {
colIdx = cellColIdx[cell];
}
__syncthreads();
if(idx < size) {
sharedData[tid] = xData[colIdx * cellsize + tid];
}
__syncthreads();
if(idx < size) {
for(int col = 0; col < cellsize; col++) {
value = cellData[cell * cellsize * cellsize + col * cellsize + tid];
rowacc += value * sharedData[col];
}
}
}
if(idx < size) {
rowacc += dia * xData[idx];
result[idx] += rowacc;
}
}
// ELLPACKmod format
extern "C" __global__ void ellMultiply(double* valData, int* colIdxData, double* xData, double* result, double alpha, double beta, int size, int colCount, int valStride, int colStride) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
// Add offsets to the start of this block's value and column data pointers
valData += blockIdx.x * colCount * valStride;
colIdxData += blockIdx.x * colCount * colStride;
int valIdx;
int colIdx;
// No sync in this kernel, therefore overlapping threads are discarded here
if(idx < size) {
double rowacc = 0.0;
// Loop over all columns
for(int col = 0; col < colCount; col++) {
// Index of the value and column index to load
valIdx = col * valStride + threadIdx.x;
colIdx = col * colStride + threadIdx.x;
// Load value and multiply with x at column of this value
rowacc += valData[valIdx] * xData[colIdxData[colIdx]];
}
// Write result back
result[idx] = result[idx] * beta + rowacc * alpha;
}
}
// ManualCacheELLPACK format
extern "C" __global__ void mcellMultiply(double* valData, unsigned short* colIdxData, int* xSubStart, int* blockSubVector, double* xData, double* result, double alpha, double beta, int size, int colCount, int valStride, int colStride) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int tid = threadIdx.x;
// Add offsets to the start of this block's value and column data pointers
valData += blockIdx.x * colCount * valStride;
colIdxData += blockIdx.x * colCount * colStride;
double* xSub = (double*)smem;
__shared__ int xStart;
__shared__ int xLength;
int valIdx;
unsigned short colIdx;
if(tid == 0) {
xStart = xSubStart[blockIdx.x ];
xLength = xSubStart[blockIdx.x + 1] - xStart;
}
__syncthreads();
blockSubVector += xStart;
int ldIdx = tid;
while(ldIdx < xLength) {
xSub[ldIdx] = xData[blockSubVector[ldIdx]];
ldIdx += blockDim.x;
}
__syncthreads();
// No sync inside this loop, therefore overlapping threads are discarded here
if(idx < size) {
double rowacc = 0.0;
// Loop over all columns
for(int col = 0; col < colCount; col++) {
// Index of the value and column index to load
valIdx = col * valStride + tid;
colIdx = col * colStride + tid;
// Load value and multiply with x at column of this value
rowacc += valData[valIdx] * xSub[colIdxData[colIdx]];
}
// Write result back
result[idx] = result[idx] * beta + rowacc * alpha;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*
* Copyright (C) 2010, Florian Kummer, Technische Universitaet Darmstadt, Fachgebiet fuer Stroemungsmechanik
*
* Use, modification and distribution is subject to the Boost Software
* License, Version 1.0. (See accompanying file LICENSE_1_0.txt or copy at
* http://www.boost.org/LICENSE_1_0.txt)
*
* Authors: Christoph Busold
*
*/
extern __shared__ char smem[];
extern "C" __global__ void sparseMultiply(double* values, int* colIdx, int* rowStart, double* result, double* x, double alpha, double beta, int size) {
// Dynamically allocated shared memory, should be BlockDim.x + 1 ints (see cuFuncSetSharedSize host code)
int* sharedRowStart = (int*)smem;
// Indices
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int tid = threadIdx.x;
double rowacc = 0.0;
// Each thread loads one element of rowStart
if(idx < size) {
sharedRowStart[tid] = rowStart[idx];
}
// The first thread loads additionally the next element, needed by the last thread
if(tid == 0) {
int loadIdx = min((blockIdx.x + 1) * blockDim.x, size);
int storIdx = size % blockDim.x > 0 && idx + blockDim.x >= size ? size % blockDim.x : blockDim.x;
sharedRowStart[storIdx] = rowStart[loadIdx];
}
__syncthreads();
if(idx < size) {
// Multiply and sum up data of this row
for(int i = sharedRowStart[tid]; i < sharedRowStart[tid + 1]; i++) {
rowacc += values[i] * x[colIdx[i]];
}
result[idx] = result[idx] * beta + rowacc * alpha;
}
}
extern "C" __global__ void accumulateExternal(double* data, int* indices, double* rcvBuffer, double alpha, int size) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(idx < size) {
data[indices[idx]] += rcvBuffer[idx] * alpha;
}
}
// In this kernel each block computes multiple cell rows
// IMPORTANT: All cell rows must have the same number of cells!
// Otherwise sync in kernel might fail, causing crash or incorrect behaviour!
extern "C" __global__ void blockMultiply2(double* cellData, double* xData, int* cellColIdx, double* result, double alpha, double beta, int cellsize, int cellrowsperblock, int cellsperrow, int stride, int size) {
// Dynamically allocated shared memory, should be blockDim.x doubles for xData
double* sharedData = (double*)smem;
// Start cell index of this thread
int* start = (int*)&sharedData[blockDim.x];
// Column of this thread's cell
int* colIdx = (int*)&start[cellrowsperblock];
// Global index
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int tid = threadIdx.x;
// Number of the cell this thread is in
int cellid = tid / cellsize;
// Thread index inside this cell
int cid = tid % cellsize;
double rowacc = 0.0;
double value;
// Load start index for every cell row in this block
if(tid < cellrowsperblock) {
start[tid] = (cellrowsperblock * blockIdx.x + tid) * cellsperrow;
}
__syncthreads();
// Loop over all cells, discard overlapping threads inside because of sync
for(int i = 0; i < cellsperrow; i++) {
// Load column index for every cell
if(tid < cellrowsperblock) {
colIdx[tid] = cellColIdx[start[tid] + i];
}
__syncthreads();
// No overlapping threads
if(idx < size) {
// Load x at colIdx location into shared memory
// colIdx * cellsize is the start index at this column
// cid is the row index of this thread
sharedData[tid] = xData[colIdx[cellid] * cellsize + cid];
}
__syncthreads();
// No overlapping threads
if(idx < size) {
// Loop over all columns of this cell
for(int col = 0; col < cellsize; col++) {
// Load value of this column
// cell * cellsize * cellsize is the start index of the current cell
// col * cellsize is the start index of the current column
// cid is the row index of this thread
value = cellData[(start[cellid] + i) * stride + col * cellsize + cid];
// Multiply value with x from sharedMemory
// cellid * cellsize is the offset for the cell this thread is in
// col is the column index of this loop cycle
rowacc += value * sharedData[cellid * cellsize + col];
}
}
__syncthreads();
}
// No overlapping threads
if(idx < size) {
// Write back result
result[idx] = result[idx] * beta + rowacc * alpha;
}
}
// In this kernel each block computes one cell row (block size equals cell size)
extern "C" __global__ void blockMultiply(double* cellData, double* xData, int* cellColIdx, int* cellRowStart, double* result, double dia, int cellsize, int size) {
double* sharedData = (double*)smem;
__shared__ int colIdx;
__shared__ int start;
__shared__ int end;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int tid = threadIdx.x;
double rowacc = 0.0;
double value;
if(tid == 0) {
start = cellRowStart[blockIdx.x ];
end = cellRowStart[blockIdx.x + 1];
}
__syncthreads();
for(int cell = start; cell < end; cell++) {
if(tid == 0) {
colIdx = cellColIdx[cell];
}
__syncthreads();
if(idx < size) {
sharedData[tid] = xData[colIdx * cellsize + tid];
}
__syncthreads();
if(idx < size) {
for(int col = 0; col < cellsize; col++) {
value = cellData[cell * cellsize * cellsize + col * cellsize + tid];
rowacc += value * sharedData[col];
}
}
}
if(idx < size) {
rowacc += dia * xData[idx];
result[idx] += rowacc;
}
}
// ELLPACKmod format
extern "C" __global__ void ellMultiply(double* valData, int* colIdxData, double* xData, double* result, double alpha, double beta, int size, int colCount, int valStride, int colStride) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
// Add offsets to the start of this block's value and column data pointers
valData += blockIdx.x * colCount * valStride;
colIdxData += blockIdx.x * colCount * colStride;
int valIdx;
int colIdx;
// No sync in this kernel, therefore overlapping threads are discarded here
if(idx < size) {
double rowacc = 0.0;
// Loop over all columns
for(int col = 0; col < colCount; col++) {
// Index of the value and column index to load
valIdx = col * valStride + threadIdx.x;
colIdx = col * colStride + threadIdx.x;
// Load value and multiply with x at column of this value
rowacc += valData[valIdx] * xData[colIdxData[colIdx]];
}
// Write result back
result[idx] = result[idx] * beta + rowacc * alpha;
}
}
// ManualCacheELLPACK format
extern "C" __global__ void mcellMultiply(double* valData, unsigned short* colIdxData, int* xSubStart, int* blockSubVector, double* xData, double* result, double alpha, double beta, int size, int colCount, int valStride, int colStride) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int tid = threadIdx.x;
// Add offsets to the start of this block's value and column data pointers
valData += blockIdx.x * colCount * valStride;
colIdxData += blockIdx.x * colCount * colStride;
double* xSub = (double*)smem;
__shared__ int xStart;
__shared__ int xLength;
int valIdx;
unsigned short colIdx;
if(tid == 0) {
xStart = xSubStart[blockIdx.x ];
xLength = xSubStart[blockIdx.x + 1] - xStart;
}
__syncthreads();
blockSubVector += xStart;
int ldIdx = tid;
while(ldIdx < xLength) {
xSub[ldIdx] = xData[blockSubVector[ldIdx]];
ldIdx += blockDim.x;
}
__syncthreads();
// No sync inside this loop, therefore overlapping threads are discarded here
if(idx < size) {
double rowacc = 0.0;
// Loop over all columns
for(int col = 0; col < colCount; col++) {
// Index of the value and column index to load
valIdx = col * valStride + tid;
colIdx = col * colStride + tid;
// Load value and multiply with x at column of this value
rowacc += valData[valIdx] * xSub[colIdxData[colIdx]];
}
// Write result back
result[idx] = result[idx] * beta + rowacc * alpha;
}
} | .text
.file "CudaMatrixKernelDP.hip"
.globl __device_stub__sparseMultiply # -- Begin function __device_stub__sparseMultiply
.p2align 4, 0x90
.type __device_stub__sparseMultiply,@function
__device_stub__sparseMultiply: # @__device_stub__sparseMultiply
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movsd %xmm0, 64(%rsp)
movsd %xmm1, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 4(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $sparseMultiply, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size __device_stub__sparseMultiply, .Lfunc_end0-__device_stub__sparseMultiply
.cfi_endproc
# -- End function
.globl __device_stub__accumulateExternal # -- Begin function __device_stub__accumulateExternal
.p2align 4, 0x90
.type __device_stub__accumulateExternal,@function
__device_stub__accumulateExternal: # @__device_stub__accumulateExternal
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movsd %xmm0, 64(%rsp)
movl %ecx, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $accumulateExternal, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end1:
.size __device_stub__accumulateExternal, .Lfunc_end1-__device_stub__accumulateExternal
.cfi_endproc
# -- End function
.globl __device_stub__blockMultiply2 # -- Begin function __device_stub__blockMultiply2
.p2align 4, 0x90
.type __device_stub__blockMultiply2,@function
__device_stub__blockMultiply2: # @__device_stub__blockMultiply2
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movsd %xmm0, 72(%rsp)
movsd %xmm1, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
leaq 208(%rsp), %rax
movq %rax, 176(%rsp)
leaq 216(%rsp), %rax
movq %rax, 184(%rsp)
leaq 224(%rsp), %rax
movq %rax, 192(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $blockMultiply2, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end2:
.size __device_stub__blockMultiply2, .Lfunc_end2-__device_stub__blockMultiply2
.cfi_endproc
# -- End function
.globl __device_stub__blockMultiply # -- Begin function __device_stub__blockMultiply
.p2align 4, 0x90
.type __device_stub__blockMultiply,@function
__device_stub__blockMultiply: # @__device_stub__blockMultiply
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movsd %xmm0, 64(%rsp)
movl %r9d, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 192(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $blockMultiply, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end3:
.size __device_stub__blockMultiply, .Lfunc_end3-__device_stub__blockMultiply
.cfi_endproc
# -- End function
.globl __device_stub__ellMultiply # -- Begin function __device_stub__ellMultiply
.p2align 4, 0x90
.type __device_stub__ellMultiply,@function
__device_stub__ellMultiply: # @__device_stub__ellMultiply
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movsd %xmm0, 72(%rsp)
movsd %xmm1, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
leaq 208(%rsp), %rax
movq %rax, 176(%rsp)
leaq 216(%rsp), %rax
movq %rax, 184(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $ellMultiply, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end4:
.size __device_stub__ellMultiply, .Lfunc_end4-__device_stub__ellMultiply
.cfi_endproc
# -- End function
.globl __device_stub__mcellMultiply # -- Begin function __device_stub__mcellMultiply
.p2align 4, 0x90
.type __device_stub__mcellMultiply,@function
__device_stub__mcellMultiply: # @__device_stub__mcellMultiply
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movsd %xmm0, 56(%rsp)
movsd %xmm1, 48(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 232(%rsp), %rax
movq %rax, 184(%rsp)
leaq 240(%rsp), %rax
movq %rax, 192(%rsp)
leaq 248(%rsp), %rax
movq %rax, 200(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 112(%rsp), %r9
movl $mcellMultiply, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end5:
.size __device_stub__mcellMultiply, .Lfunc_end5-__device_stub__mcellMultiply
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $sparseMultiply, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $accumulateExternal, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $blockMultiply2, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $blockMultiply, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $ellMultiply, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $mcellMultiply, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type sparseMultiply,@object # @sparseMultiply
.section .rodata,"a",@progbits
.globl sparseMultiply
.p2align 3, 0x0
sparseMultiply:
.quad __device_stub__sparseMultiply
.size sparseMultiply, 8
.type accumulateExternal,@object # @accumulateExternal
.globl accumulateExternal
.p2align 3, 0x0
accumulateExternal:
.quad __device_stub__accumulateExternal
.size accumulateExternal, 8
.type blockMultiply2,@object # @blockMultiply2
.globl blockMultiply2
.p2align 3, 0x0
blockMultiply2:
.quad __device_stub__blockMultiply2
.size blockMultiply2, 8
.type blockMultiply,@object # @blockMultiply
.globl blockMultiply
.p2align 3, 0x0
blockMultiply:
.quad __device_stub__blockMultiply
.size blockMultiply, 8
.type ellMultiply,@object # @ellMultiply
.globl ellMultiply
.p2align 3, 0x0
ellMultiply:
.quad __device_stub__ellMultiply
.size ellMultiply, 8
.type mcellMultiply,@object # @mcellMultiply
.globl mcellMultiply
.p2align 3, 0x0
mcellMultiply:
.quad __device_stub__mcellMultiply
.size mcellMultiply, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "sparseMultiply"
.size .L__unnamed_1, 15
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "accumulateExternal"
.size .L__unnamed_2, 19
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "blockMultiply2"
.size .L__unnamed_3, 15
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "blockMultiply"
.size .L__unnamed_4, 14
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "ellMultiply"
.size .L__unnamed_5, 12
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "mcellMultiply"
.size .L__unnamed_6, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__sparseMultiply
.addrsig_sym __device_stub__accumulateExternal
.addrsig_sym __device_stub__blockMultiply2
.addrsig_sym __device_stub__blockMultiply
.addrsig_sym __device_stub__ellMultiply
.addrsig_sym __device_stub__mcellMultiply
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym sparseMultiply
.addrsig_sym accumulateExternal
.addrsig_sym blockMultiply2
.addrsig_sym blockMultiply
.addrsig_sym ellMultiply
.addrsig_sym mcellMultiply
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ed811_00000000-6_CudaMatrixKernelDP.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z14sparseMultiplyPdPiS0_S_S_ddiPdPiS0_S_S_ddi
.type _Z46__device_stub__Z14sparseMultiplyPdPiS0_S_S_ddiPdPiS0_S_S_ddi, @function
_Z46__device_stub__Z14sparseMultiplyPdPiS0_S_S_ddiPdPiS0_S_S_ddi:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movsd %xmm0, 16(%rsp)
movsd %xmm1, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 4(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq sparseMultiply(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z14sparseMultiplyPdPiS0_S_S_ddiPdPiS0_S_S_ddi, .-_Z46__device_stub__Z14sparseMultiplyPdPiS0_S_S_ddiPdPiS0_S_S_ddi
.globl sparseMultiply
.type sparseMultiply, @function
sparseMultiply:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z14sparseMultiplyPdPiS0_S_S_ddiPdPiS0_S_S_ddi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size sparseMultiply, .-sparseMultiply
.globl _Z44__device_stub__Z18accumulateExternalPdPiS_diPdPiS_di
.type _Z44__device_stub__Z18accumulateExternalPdPiS_diPdPiS_di, @function
_Z44__device_stub__Z18accumulateExternalPdPiS_diPdPiS_di:
.LFB2053:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movsd %xmm0, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq accumulateExternal(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z44__device_stub__Z18accumulateExternalPdPiS_diPdPiS_di, .-_Z44__device_stub__Z18accumulateExternalPdPiS_diPdPiS_di
.globl accumulateExternal
.type accumulateExternal, @function
accumulateExternal:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z18accumulateExternalPdPiS_diPdPiS_di
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size accumulateExternal, .-accumulateExternal
.globl _Z47__device_stub__Z14blockMultiply2PdS_PiS_ddiiiiiPdS_PiS_ddiiiii
.type _Z47__device_stub__Z14blockMultiply2PdS_PiS_ddiiiiiPdS_PiS_ddiiiii, @function
_Z47__device_stub__Z14blockMultiply2PdS_PiS_ddiiiiiPdS_PiS_ddiiiii:
.LFB2055:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movsd %xmm0, 24(%rsp)
movsd %xmm1, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
leaq 240(%rsp), %rax
movq %rax, 192(%rsp)
leaq 248(%rsp), %rax
movq %rax, 200(%rsp)
leaq 256(%rsp), %rax
movq %rax, 208(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq blockMultiply2(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z47__device_stub__Z14blockMultiply2PdS_PiS_ddiiiiiPdS_PiS_ddiiiii, .-_Z47__device_stub__Z14blockMultiply2PdS_PiS_ddiiiiiPdS_PiS_ddiiiii
.globl blockMultiply2
.type blockMultiply2, @function
blockMultiply2:
.LFB2056:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z47__device_stub__Z14blockMultiply2PdS_PiS_ddiiiiiPdS_PiS_ddiiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size blockMultiply2, .-blockMultiply2
.globl _Z45__device_stub__Z13blockMultiplyPdS_PiS0_S_diiPdS_PiS0_S_dii
.type _Z45__device_stub__Z13blockMultiplyPdS_PiS0_S_diiPdS_PiS0_S_dii, @function
_Z45__device_stub__Z13blockMultiplyPdS_PiS0_S_diiPdS_PiS0_S_dii:
.LFB2057:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movsd %xmm0, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 224(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq blockMultiply(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z45__device_stub__Z13blockMultiplyPdS_PiS0_S_diiPdS_PiS0_S_dii, .-_Z45__device_stub__Z13blockMultiplyPdS_PiS0_S_diiPdS_PiS0_S_dii
.globl blockMultiply
.type blockMultiply, @function
blockMultiply:
.LFB2058:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z45__device_stub__Z13blockMultiplyPdS_PiS0_S_diiPdS_PiS0_S_dii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size blockMultiply, .-blockMultiply
.globl _Z43__device_stub__Z11ellMultiplyPdPiS_S_ddiiiiPdPiS_S_ddiiii
.type _Z43__device_stub__Z11ellMultiplyPdPiS_S_ddiiiiPdPiS_S_ddiiii, @function
_Z43__device_stub__Z11ellMultiplyPdPiS_S_ddiiiiPdPiS_S_ddiiii:
.LFB2059:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movsd %xmm0, 24(%rsp)
movsd %xmm1, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
leaq 240(%rsp), %rax
movq %rax, 192(%rsp)
leaq 248(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq ellMultiply(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z43__device_stub__Z11ellMultiplyPdPiS_S_ddiiiiPdPiS_S_ddiiii, .-_Z43__device_stub__Z11ellMultiplyPdPiS_S_ddiiiiPdPiS_S_ddiiii
.globl ellMultiply
.type ellMultiply, @function
ellMultiply:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z43__device_stub__Z11ellMultiplyPdPiS_S_ddiiiiPdPiS_S_ddiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size ellMultiply, .-ellMultiply
.globl _Z50__device_stub__Z13mcellMultiplyPdPtPiS1_S_S_ddiiiiPdPtPiS1_S_S_ddiiii
.type _Z50__device_stub__Z13mcellMultiplyPdPtPiS1_S_S_ddiiiiPdPtPiS1_S_S_ddiiii, @function
_Z50__device_stub__Z13mcellMultiplyPdPtPiS1_S_S_ddiiiiPdPtPiS1_S_S_ddiiii:
.LFB2061:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movsd %xmm0, 8(%rsp)
movsd %xmm1, (%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movq %rsp, %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 264(%rsp), %rax
movq %rax, 200(%rsp)
leaq 272(%rsp), %rax
movq %rax, 208(%rsp)
leaq 280(%rsp), %rax
movq %rax, 216(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 264
pushq 72(%rsp)
.cfi_def_cfa_offset 272
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq mcellMultiply(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z50__device_stub__Z13mcellMultiplyPdPtPiS1_S_S_ddiiiiPdPtPiS1_S_S_ddiiii, .-_Z50__device_stub__Z13mcellMultiplyPdPtPiS1_S_S_ddiiiiPdPtPiS1_S_S_ddiiii
.globl mcellMultiply
.type mcellMultiply, @function
mcellMultiply:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z50__device_stub__Z13mcellMultiplyPdPtPiS1_S_S_ddiiiiPdPtPiS1_S_S_ddiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size mcellMultiply, .-mcellMultiply
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "mcellMultiply"
.LC1:
.string "ellMultiply"
.LC2:
.string "blockMultiply"
.LC3:
.string "blockMultiply2"
.LC4:
.string "accumulateExternal"
.LC5:
.string "sparseMultiply"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2064:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq mcellMultiply(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq ellMultiply(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq blockMultiply(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq blockMultiply2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq accumulateExternal(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq sparseMultiply(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "CudaMatrixKernelDP.hip"
.globl __device_stub__sparseMultiply # -- Begin function __device_stub__sparseMultiply
.p2align 4, 0x90
.type __device_stub__sparseMultiply,@function
__device_stub__sparseMultiply: # @__device_stub__sparseMultiply
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movsd %xmm0, 64(%rsp)
movsd %xmm1, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 4(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $sparseMultiply, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size __device_stub__sparseMultiply, .Lfunc_end0-__device_stub__sparseMultiply
.cfi_endproc
# -- End function
.globl __device_stub__accumulateExternal # -- Begin function __device_stub__accumulateExternal
.p2align 4, 0x90
.type __device_stub__accumulateExternal,@function
__device_stub__accumulateExternal: # @__device_stub__accumulateExternal
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movsd %xmm0, 64(%rsp)
movl %ecx, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $accumulateExternal, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end1:
.size __device_stub__accumulateExternal, .Lfunc_end1-__device_stub__accumulateExternal
.cfi_endproc
# -- End function
.globl __device_stub__blockMultiply2 # -- Begin function __device_stub__blockMultiply2
.p2align 4, 0x90
.type __device_stub__blockMultiply2,@function
__device_stub__blockMultiply2: # @__device_stub__blockMultiply2
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movsd %xmm0, 72(%rsp)
movsd %xmm1, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
leaq 208(%rsp), %rax
movq %rax, 176(%rsp)
leaq 216(%rsp), %rax
movq %rax, 184(%rsp)
leaq 224(%rsp), %rax
movq %rax, 192(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $blockMultiply2, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end2:
.size __device_stub__blockMultiply2, .Lfunc_end2-__device_stub__blockMultiply2
.cfi_endproc
# -- End function
.globl __device_stub__blockMultiply # -- Begin function __device_stub__blockMultiply
.p2align 4, 0x90
.type __device_stub__blockMultiply,@function
__device_stub__blockMultiply: # @__device_stub__blockMultiply
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movsd %xmm0, 64(%rsp)
movl %r9d, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 192(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $blockMultiply, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end3:
.size __device_stub__blockMultiply, .Lfunc_end3-__device_stub__blockMultiply
.cfi_endproc
# -- End function
.globl __device_stub__ellMultiply # -- Begin function __device_stub__ellMultiply
.p2align 4, 0x90
.type __device_stub__ellMultiply,@function
__device_stub__ellMultiply: # @__device_stub__ellMultiply
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movsd %xmm0, 72(%rsp)
movsd %xmm1, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
leaq 208(%rsp), %rax
movq %rax, 176(%rsp)
leaq 216(%rsp), %rax
movq %rax, 184(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $ellMultiply, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end4:
.size __device_stub__ellMultiply, .Lfunc_end4-__device_stub__ellMultiply
.cfi_endproc
# -- End function
.globl __device_stub__mcellMultiply # -- Begin function __device_stub__mcellMultiply
.p2align 4, 0x90
.type __device_stub__mcellMultiply,@function
__device_stub__mcellMultiply: # @__device_stub__mcellMultiply
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movsd %xmm0, 56(%rsp)
movsd %xmm1, 48(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 232(%rsp), %rax
movq %rax, 184(%rsp)
leaq 240(%rsp), %rax
movq %rax, 192(%rsp)
leaq 248(%rsp), %rax
movq %rax, 200(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 112(%rsp), %r9
movl $mcellMultiply, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end5:
.size __device_stub__mcellMultiply, .Lfunc_end5-__device_stub__mcellMultiply
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $sparseMultiply, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $accumulateExternal, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $blockMultiply2, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $blockMultiply, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $ellMultiply, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $mcellMultiply, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type sparseMultiply,@object # @sparseMultiply
.section .rodata,"a",@progbits
.globl sparseMultiply
.p2align 3, 0x0
sparseMultiply:
.quad __device_stub__sparseMultiply
.size sparseMultiply, 8
.type accumulateExternal,@object # @accumulateExternal
.globl accumulateExternal
.p2align 3, 0x0
accumulateExternal:
.quad __device_stub__accumulateExternal
.size accumulateExternal, 8
.type blockMultiply2,@object # @blockMultiply2
.globl blockMultiply2
.p2align 3, 0x0
blockMultiply2:
.quad __device_stub__blockMultiply2
.size blockMultiply2, 8
.type blockMultiply,@object # @blockMultiply
.globl blockMultiply
.p2align 3, 0x0
blockMultiply:
.quad __device_stub__blockMultiply
.size blockMultiply, 8
.type ellMultiply,@object # @ellMultiply
.globl ellMultiply
.p2align 3, 0x0
ellMultiply:
.quad __device_stub__ellMultiply
.size ellMultiply, 8
.type mcellMultiply,@object # @mcellMultiply
.globl mcellMultiply
.p2align 3, 0x0
mcellMultiply:
.quad __device_stub__mcellMultiply
.size mcellMultiply, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "sparseMultiply"
.size .L__unnamed_1, 15
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "accumulateExternal"
.size .L__unnamed_2, 19
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "blockMultiply2"
.size .L__unnamed_3, 15
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "blockMultiply"
.size .L__unnamed_4, 14
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "ellMultiply"
.size .L__unnamed_5, 12
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "mcellMultiply"
.size .L__unnamed_6, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__sparseMultiply
.addrsig_sym __device_stub__accumulateExternal
.addrsig_sym __device_stub__blockMultiply2
.addrsig_sym __device_stub__blockMultiply
.addrsig_sym __device_stub__ellMultiply
.addrsig_sym __device_stub__mcellMultiply
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym sparseMultiply
.addrsig_sym accumulateExternal
.addrsig_sym blockMultiply2
.addrsig_sym blockMultiply
.addrsig_sym ellMultiply
.addrsig_sym mcellMultiply
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<math.h>
#include<cuda.h>
#define N 256
__global__ void matrix_vector_multi_gpu_1_2(float *A_d,float *B_d,float *C_d){
int i,j;
int N_start;
N_start=threadIdx.x*128;
for(j=N_start;j<N_start+128;j++){
A_d[j]=0.0;
for(i=0;i<N;i++){
A_d[j]=A_d[j]+B_d[j*N+i]*C_d[i];
}
}
}
int main(){
int i,j;
float A[N],B[N*N],C[N];
float *A_d,*B_d,*C_d;
dim3 blocks(1,1,1);
dim3 threads(2,1,1);
for(j=0;j<N;j++){
for(i=0;i<N;i++){
B[j*N+i]=((float)j)/256.0;
}
}
for(j=0;j<N;j++){
C[j]=1.0F;
}
cudaMalloc((void**)&A_d,N*sizeof(float));
cudaMalloc((void**)&B_d,N*N*sizeof(float));
cudaMalloc((void**)&C_d,N*sizeof(float));
cudaMemcpy(A_d,A,N*sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpy(B_d,B,N*N*sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpy(C_d,C,N*sizeof(float),cudaMemcpyHostToDevice);
matrix_vector_multi_gpu_1_2<<<blocks,threads>>>(A_d,B_d,C_d);
cudaMemcpy(A,A_d,N*sizeof(float),cudaMemcpyDeviceToHost);
for(j=0;j<N;j++){
printf("A[ %d ]=%f \n",j,A[j]);
}
cudaFree(A_d);
cudaFree(B_d);
cudaFree(C_d);
return 0;
} | code for sm_80
Function : _Z27matrix_vector_multi_gpu_1_2PfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIADD3 UR4, UP0, UR4, 0x20, URZ ; /* 0x0000002004047890 */
/* 0x000fe4000ff1e03f */
/*0040*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0050*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200087fe43f */
/*0060*/ SHF.L.U32 R0, R0, 0x7, RZ ; /* 0x0000000700007819 */
/* 0x001fc800000006ff */
/*0070*/ IADD3 R8, R0, 0x7f, RZ ; /* 0x0000007f00087810 */
/* 0x000fe40007ffe0ff */
/*0080*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x005fe200000001ff */
/*0090*/ MOV R4, UR4 ; /* 0x0000000400047c02 */
/* 0x000fe20008000f00 */
/*00a0*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fe200000001ff */
/*00b0*/ MOV R5, UR5 ; /* 0x0000000500057c02 */
/* 0x000fe40008000f00 */
/*00c0*/ SHF.L.U32 R7, R0.reuse, 0x8, RZ ; /* 0x0000000800077819 */
/* 0x040fe400000006ff */
/*00d0*/ ISETP.GE.AND P3, PT, R0.reuse, R8, PT ; /* 0x000000080000720c */
/* 0x040fe40003f66270 */
/*00e0*/ MOV R11, RZ ; /* 0x000000ff000b7202 */
/* 0x000fe20000000f00 */
/*00f0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fe200078e0203 */
/*0100*/ MOV R6, c[0x0][0x170] ; /* 0x00005c0000067a02 */
/* 0x000fc40000000f00 */
/*0110*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe20007ffe0ff */
/*0120*/ IMAD.WIDE R4, R7, 0x4, R4 ; /* 0x0000000407047825 */
/* 0x000fe200078e0204 */
/*0130*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e2000c101906 */
/*0140*/ MOV R7, c[0x0][0x174] ; /* 0x00005d0000077a02 */
/* 0x000fca0000000f00 */
/*0150*/ LDG.E R10, [R6.64] ; /* 0x00000006060a7981 */
/* 0x004ea8000c1e1900 */
/*0160*/ LDG.E R12, [R4.64+-0x20] ; /* 0xffffe006040c7981 */
/* 0x000ea4000c1e1900 */
/*0170*/ FFMA R11, R10, R12, R11 ; /* 0x0000000c0a0b7223 */
/* 0x004fca000000000b */
/*0180*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101906 */
/*0190*/ LDG.E R10, [R6.64+0x4] ; /* 0x00000406060a7981 */
/* 0x000ea8000c1e1900 */
/*01a0*/ LDG.E R12, [R4.64+-0x1c] ; /* 0xffffe406040c7981 */
/* 0x000ea4000c1e1900 */
/*01b0*/ FFMA R13, R10, R12, R11 ; /* 0x0000000c0a0d7223 */
/* 0x004fca000000000b */
/*01c0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101906 */
/*01d0*/ LDG.E R10, [R6.64+0x8] ; /* 0x00000806060a7981 */
/* 0x000ee8000c1e1900 */
/*01e0*/ LDG.E R12, [R4.64+-0x18] ; /* 0xffffe806040c7981 */
/* 0x000ee4000c1e1900 */
/*01f0*/ FFMA R15, R10, R12, R13 ; /* 0x0000000c0a0f7223 */
/* 0x008fca000000000d */
/*0200*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0007e8000c101906 */
/*0210*/ LDG.E R10, [R6.64+0xc] ; /* 0x00000c06060a7981 */
/* 0x000e68000c1e1900 */
/*0220*/ LDG.E R12, [R4.64+-0x14] ; /* 0xffffec06040c7981 */
/* 0x000e64000c1e1900 */
/*0230*/ FFMA R11, R10, R12, R15 ; /* 0x0000000c0a0b7223 */
/* 0x002fca000000000f */
/*0240*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101906 */
/*0250*/ LDG.E R10, [R6.64+0x10] ; /* 0x00001006060a7981 */
/* 0x000ea8000c1e1900 */
/*0260*/ LDG.E R12, [R4.64+-0x10] ; /* 0xfffff006040c7981 */
/* 0x000ea4000c1e1900 */
/*0270*/ FFMA R13, R10, R12, R11 ; /* 0x0000000c0a0d7223 */
/* 0x004fca000000000b */
/*0280*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101906 */
/*0290*/ LDG.E R10, [R6.64+0x14] ; /* 0x00001406060a7981 */
/* 0x000ee8000c1e1900 */
/*02a0*/ LDG.E R12, [R4.64+-0xc] ; /* 0xfffff406040c7981 */
/* 0x000ee4000c1e1900 */
/*02b0*/ FFMA R15, R10, R12, R13 ; /* 0x0000000c0a0f7223 */
/* 0x008fca000000000d */
/*02c0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0007e8000c101906 */
/*02d0*/ LDG.E R10, [R6.64+0x18] ; /* 0x00001806060a7981 */
/* 0x000e68000c1e1900 */
/*02e0*/ LDG.E R12, [R4.64+-0x8] ; /* 0xfffff806040c7981 */
/* 0x000e64000c1e1900 */
/*02f0*/ FFMA R11, R10, R12, R15 ; /* 0x0000000c0a0b7223 */
/* 0x002fca000000000f */
/*0300*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101906 */
/*0310*/ LDG.E R10, [R6.64+0x1c] ; /* 0x00001c06060a7981 */
/* 0x000ea8000c1e1900 */
/*0320*/ LDG.E R12, [R4.64+-0x4] ; /* 0xfffffc06040c7981 */
/* 0x000ea4000c1e1900 */
/*0330*/ FFMA R13, R10, R12, R11 ; /* 0x0000000c0a0d7223 */
/* 0x004fca000000000b */
/*0340*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101906 */
/*0350*/ LDG.E R10, [R6.64+0x20] ; /* 0x00002006060a7981 */
/* 0x000ee8000c1e1900 */
/*0360*/ LDG.E R12, [R4.64] ; /* 0x00000006040c7981 */
/* 0x000ee4000c1e1900 */
/*0370*/ FFMA R15, R10, R12, R13 ; /* 0x0000000c0a0f7223 */
/* 0x008fca000000000d */
/*0380*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0007e8000c101906 */
/*0390*/ LDG.E R10, [R6.64+0x24] ; /* 0x00002406060a7981 */
/* 0x000e68000c1e1900 */
/*03a0*/ LDG.E R12, [R4.64+0x4] ; /* 0x00000406040c7981 */
/* 0x000e64000c1e1900 */
/*03b0*/ FFMA R11, R10, R12, R15 ; /* 0x0000000c0a0b7223 */
/* 0x002fca000000000f */
/*03c0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101906 */
/*03d0*/ LDG.E R10, [R6.64+0x28] ; /* 0x00002806060a7981 */
/* 0x000ea8000c1e1900 */
/*03e0*/ LDG.E R12, [R4.64+0x8] ; /* 0x00000806040c7981 */
/* 0x000ea4000c1e1900 */
/*03f0*/ FFMA R13, R10, R12, R11 ; /* 0x0000000c0a0d7223 */
/* 0x004fca000000000b */
/*0400*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101906 */
/*0410*/ LDG.E R10, [R6.64+0x2c] ; /* 0x00002c06060a7981 */
/* 0x000ee8000c1e1900 */
/*0420*/ LDG.E R12, [R4.64+0xc] ; /* 0x00000c06040c7981 */
/* 0x000ee4000c1e1900 */
/*0430*/ FFMA R15, R10, R12, R13 ; /* 0x0000000c0a0f7223 */
/* 0x008fca000000000d */
/*0440*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0007e8000c101906 */
/*0450*/ LDG.E R10, [R6.64+0x30] ; /* 0x00003006060a7981 */
/* 0x000e68000c1e1900 */
/*0460*/ LDG.E R12, [R4.64+0x10] ; /* 0x00001006040c7981 */
/* 0x000e64000c1e1900 */
/*0470*/ FFMA R11, R10, R12, R15 ; /* 0x0000000c0a0b7223 */
/* 0x002fca000000000f */
/*0480*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101906 */
/*0490*/ LDG.E R10, [R6.64+0x34] ; /* 0x00003406060a7981 */
/* 0x000ea8000c1e1900 */
/*04a0*/ LDG.E R12, [R4.64+0x14] ; /* 0x00001406040c7981 */
/* 0x000ea4000c1e1900 */
/*04b0*/ FFMA R13, R10, R12, R11 ; /* 0x0000000c0a0d7223 */
/* 0x004fca000000000b */
/*04c0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101906 */
/*04d0*/ LDG.E R10, [R6.64+0x38] ; /* 0x00003806060a7981 */
/* 0x000ee8000c1e1900 */
/*04e0*/ LDG.E R12, [R4.64+0x18] ; /* 0x00001806040c7981 */
/* 0x000ee4000c1e1900 */
/*04f0*/ FFMA R15, R10, R12, R13 ; /* 0x0000000c0a0f7223 */
/* 0x008fca000000000d */
/*0500*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0005e8000c101906 */
/*0510*/ LDG.E R10, [R6.64+0x3c] ; /* 0x00003c06060a7981 */
/* 0x000668000c1e1900 */
/*0520*/ LDG.E R12, [R4.64+0x1c] ; /* 0x00001c06040c7981 */
/* 0x000862000c1e1900 */
/*0530*/ IADD3 R9, R9, 0x10, RZ ; /* 0x0000001009097810 */
/* 0x000fc80007ffe0ff */
/*0540*/ ISETP.NE.AND P0, PT, R9, 0x100, PT ; /* 0x000001000900780c */
/* 0x000fe40003f05270 */
/*0550*/ IADD3 R6, P2, R6, 0x40, RZ ; /* 0x0000004006067810 */
/* 0x008fe40007f5e0ff */
/*0560*/ IADD3 R4, P1, R4, 0x40, RZ ; /* 0x0000004004047810 */
/* 0x010fe40007f3e0ff */
/*0570*/ IADD3.X R7, RZ, R7, RZ, P2, !PT ; /* 0x00000007ff077210 */
/* 0x000fe400017fe4ff */
/*0580*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x000fe20000ffe4ff */
/*0590*/ FFMA R11, R10, R12, R15 ; /* 0x0000000c0a0b7223 */
/* 0x002fca000000000f */
/*05a0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e2000c101906 */
/*05b0*/ @P0 BRA 0x150 ; /* 0xfffffb9000000947 */
/* 0x000fea000383ffff */
/*05c0*/ @!P3 BRA 0x80 ; /* 0xfffffab00000b947 */
/* 0x000fea000383ffff */
/*05d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05e0*/ BRA 0x5e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<math.h>
#include<cuda.h>
#define N 256
__global__ void matrix_vector_multi_gpu_1_2(float *A_d,float *B_d,float *C_d){
int i,j;
int N_start;
N_start=threadIdx.x*128;
for(j=N_start;j<N_start+128;j++){
A_d[j]=0.0;
for(i=0;i<N;i++){
A_d[j]=A_d[j]+B_d[j*N+i]*C_d[i];
}
}
}
int main(){
int i,j;
float A[N],B[N*N],C[N];
float *A_d,*B_d,*C_d;
dim3 blocks(1,1,1);
dim3 threads(2,1,1);
for(j=0;j<N;j++){
for(i=0;i<N;i++){
B[j*N+i]=((float)j)/256.0;
}
}
for(j=0;j<N;j++){
C[j]=1.0F;
}
cudaMalloc((void**)&A_d,N*sizeof(float));
cudaMalloc((void**)&B_d,N*N*sizeof(float));
cudaMalloc((void**)&C_d,N*sizeof(float));
cudaMemcpy(A_d,A,N*sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpy(B_d,B,N*N*sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpy(C_d,C,N*sizeof(float),cudaMemcpyHostToDevice);
matrix_vector_multi_gpu_1_2<<<blocks,threads>>>(A_d,B_d,C_d);
cudaMemcpy(A,A_d,N*sizeof(float),cudaMemcpyDeviceToHost);
for(j=0;j<N;j++){
printf("A[ %d ]=%f \n",j,A[j]);
}
cudaFree(A_d);
cudaFree(B_d);
cudaFree(C_d);
return 0;
} | .file "tmpxft_001634ae_00000000-6_Matrix-cuda-2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z27matrix_vector_multi_gpu_1_2PfS_S_PfS_S_
.type _Z51__device_stub__Z27matrix_vector_multi_gpu_1_2PfS_S_PfS_S_, @function
_Z51__device_stub__Z27matrix_vector_multi_gpu_1_2PfS_S_PfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z27matrix_vector_multi_gpu_1_2PfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z51__device_stub__Z27matrix_vector_multi_gpu_1_2PfS_S_PfS_S_, .-_Z51__device_stub__Z27matrix_vector_multi_gpu_1_2PfS_S_PfS_S_
.globl _Z27matrix_vector_multi_gpu_1_2PfS_S_
.type _Z27matrix_vector_multi_gpu_1_2PfS_S_, @function
_Z27matrix_vector_multi_gpu_1_2PfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z27matrix_vector_multi_gpu_1_2PfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z27matrix_vector_multi_gpu_1_2PfS_S_, .-_Z27matrix_vector_multi_gpu_1_2PfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "A[ %d ]=%f \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
leaq -262144(%rsp), %r11
.cfi_def_cfa 11, 262168
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $2120, %rsp
.cfi_def_cfa_offset 264288
movq %fs:40, %rax
movq %rax, 264248(%rsp)
xorl %eax, %eax
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $2, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
leaq 3120(%rsp), %rdx
movl $0, %ecx
movss .LC0(%rip), %xmm1
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %ecx, %xmm0
mulss %xmm1, %xmm0
leaq -1024(%rdx), %rax
.L13:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L13
addl $1, %ecx
addq $1024, %rdx
cmpl $256, %ecx
jne .L12
leaq 1072(%rsp), %rax
leaq 2096(%rsp), %rdx
movss .LC1(%rip), %xmm0
.L15:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L15
movq %rsp, %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $262144, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $1024, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 2096(%rsp), %rsi
movl $1, %ecx
movl $262144, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 1072(%rsp), %rsi
movl $1, %ecx
movl $1024, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl 44(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movq 24(%rsp), %rdi
movl 32(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L16:
leaq 48(%rsp), %rdi
movl $2, %ecx
movl $1024, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC2(%rip), %rbp
.L17:
pxor %xmm0, %xmm0
cvtss2sd 48(%rsp,%rbx,4), %xmm0
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $256, %rbx
jne .L17
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 264248(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $264264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z51__device_stub__Z27matrix_vector_multi_gpu_1_2PfS_S_PfS_S_
jmp .L16
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "_Z27matrix_vector_multi_gpu_1_2PfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z27matrix_vector_multi_gpu_1_2PfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 998244352
.align 4
.LC1:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<math.h>
#include<cuda.h>
#define N 256
__global__ void matrix_vector_multi_gpu_1_2(float *A_d,float *B_d,float *C_d){
int i,j;
int N_start;
N_start=threadIdx.x*128;
for(j=N_start;j<N_start+128;j++){
A_d[j]=0.0;
for(i=0;i<N;i++){
A_d[j]=A_d[j]+B_d[j*N+i]*C_d[i];
}
}
}
int main(){
int i,j;
float A[N],B[N*N],C[N];
float *A_d,*B_d,*C_d;
dim3 blocks(1,1,1);
dim3 threads(2,1,1);
for(j=0;j<N;j++){
for(i=0;i<N;i++){
B[j*N+i]=((float)j)/256.0;
}
}
for(j=0;j<N;j++){
C[j]=1.0F;
}
cudaMalloc((void**)&A_d,N*sizeof(float));
cudaMalloc((void**)&B_d,N*N*sizeof(float));
cudaMalloc((void**)&C_d,N*sizeof(float));
cudaMemcpy(A_d,A,N*sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpy(B_d,B,N*N*sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpy(C_d,C,N*sizeof(float),cudaMemcpyHostToDevice);
matrix_vector_multi_gpu_1_2<<<blocks,threads>>>(A_d,B_d,C_d);
cudaMemcpy(A,A_d,N*sizeof(float),cudaMemcpyDeviceToHost);
for(j=0;j<N;j++){
printf("A[ %d ]=%f \n",j,A[j]);
}
cudaFree(A_d);
cudaFree(B_d);
cudaFree(C_d);
return 0;
} | #include<stdio.h>
#include<math.h>
#include<hip/hip_runtime.h>
#define N 256
__global__ void matrix_vector_multi_gpu_1_2(float *A_d,float *B_d,float *C_d){
int i,j;
int N_start;
N_start=threadIdx.x*128;
for(j=N_start;j<N_start+128;j++){
A_d[j]=0.0;
for(i=0;i<N;i++){
A_d[j]=A_d[j]+B_d[j*N+i]*C_d[i];
}
}
}
int main(){
int i,j;
float A[N],B[N*N],C[N];
float *A_d,*B_d,*C_d;
dim3 blocks(1,1,1);
dim3 threads(2,1,1);
for(j=0;j<N;j++){
for(i=0;i<N;i++){
B[j*N+i]=((float)j)/256.0;
}
}
for(j=0;j<N;j++){
C[j]=1.0F;
}
hipMalloc((void**)&A_d,N*sizeof(float));
hipMalloc((void**)&B_d,N*N*sizeof(float));
hipMalloc((void**)&C_d,N*sizeof(float));
hipMemcpy(A_d,A,N*sizeof(float),hipMemcpyHostToDevice);
hipMemcpy(B_d,B,N*N*sizeof(float),hipMemcpyHostToDevice);
hipMemcpy(C_d,C,N*sizeof(float),hipMemcpyHostToDevice);
matrix_vector_multi_gpu_1_2<<<blocks,threads>>>(A_d,B_d,C_d);
hipMemcpy(A,A_d,N*sizeof(float),hipMemcpyDeviceToHost);
for(j=0;j<N;j++){
printf("A[ %d ]=%f \n",j,A[j]);
}
hipFree(A_d);
hipFree(B_d);
hipFree(C_d);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include<stdio.h>
#include<math.h>
#include<hip/hip_runtime.h>
#define N 256
__global__ void matrix_vector_multi_gpu_1_2(float *A_d,float *B_d,float *C_d){
int i,j;
int N_start;
N_start=threadIdx.x*128;
for(j=N_start;j<N_start+128;j++){
A_d[j]=0.0;
for(i=0;i<N;i++){
A_d[j]=A_d[j]+B_d[j*N+i]*C_d[i];
}
}
}
int main(){
int i,j;
float A[N],B[N*N],C[N];
float *A_d,*B_d,*C_d;
dim3 blocks(1,1,1);
dim3 threads(2,1,1);
for(j=0;j<N;j++){
for(i=0;i<N;i++){
B[j*N+i]=((float)j)/256.0;
}
}
for(j=0;j<N;j++){
C[j]=1.0F;
}
hipMalloc((void**)&A_d,N*sizeof(float));
hipMalloc((void**)&B_d,N*N*sizeof(float));
hipMalloc((void**)&C_d,N*sizeof(float));
hipMemcpy(A_d,A,N*sizeof(float),hipMemcpyHostToDevice);
hipMemcpy(B_d,B,N*N*sizeof(float),hipMemcpyHostToDevice);
hipMemcpy(C_d,C,N*sizeof(float),hipMemcpyHostToDevice);
matrix_vector_multi_gpu_1_2<<<blocks,threads>>>(A_d,B_d,C_d);
hipMemcpy(A,A_d,N*sizeof(float),hipMemcpyDeviceToHost);
for(j=0;j<N;j++){
printf("A[ %d ]=%f \n",j,A[j]);
}
hipFree(A_d);
hipFree(B_d);
hipFree(C_d);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z27matrix_vector_multi_gpu_1_2PfS_S_
.globl _Z27matrix_vector_multi_gpu_1_2PfS_S_
.p2align 8
.type _Z27matrix_vector_multi_gpu_1_2PfS_S_,@function
_Z27matrix_vector_multi_gpu_1_2PfS_S_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_lshlrev_b32_e32 v3, 17, v0
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 7, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_or_b32_e32 v0, 0x7f, v1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, s0, s6, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, null, s7, 0, s0
s_mov_b32 s6, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_mov_b32_e32 v7, 0
s_mov_b64 s[0:1], 0
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_store_b32 v[3:4], v2, off
.LBB0_2:
v_add_co_u32 v8, vcc_lo, v5, s0
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v6, vcc_lo
s_add_u32 s8, s2, s0
s_addc_u32 s9, s3, s1
global_load_b32 v10, v2, s[8:9]
global_load_b32 v8, v[8:9], off
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmpk_lg_i32 s0, 0x400
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v7, v8, v10
global_store_b32 v[3:4], v7, off
s_cbranch_scc1 .LBB0_2
v_add_nc_u32_e32 v3, 1, v1
v_cmp_eq_u32_e32 vcc_lo, v1, v0
v_add_co_u32 v5, s0, v5, 0x400
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e64 v6, s0, 0, v6, s0
v_mov_b32_e32 v1, v3
s_or_b32 s6, vcc_lo, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_1
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z27matrix_vector_multi_gpu_1_2PfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 10
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z27matrix_vector_multi_gpu_1_2PfS_S_, .Lfunc_end0-_Z27matrix_vector_multi_gpu_1_2PfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z27matrix_vector_multi_gpu_1_2PfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z27matrix_vector_multi_gpu_1_2PfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<stdio.h>
#include<math.h>
#include<hip/hip_runtime.h>
#define N 256
__global__ void matrix_vector_multi_gpu_1_2(float *A_d,float *B_d,float *C_d){
int i,j;
int N_start;
N_start=threadIdx.x*128;
for(j=N_start;j<N_start+128;j++){
A_d[j]=0.0;
for(i=0;i<N;i++){
A_d[j]=A_d[j]+B_d[j*N+i]*C_d[i];
}
}
}
int main(){
int i,j;
float A[N],B[N*N],C[N];
float *A_d,*B_d,*C_d;
dim3 blocks(1,1,1);
dim3 threads(2,1,1);
for(j=0;j<N;j++){
for(i=0;i<N;i++){
B[j*N+i]=((float)j)/256.0;
}
}
for(j=0;j<N;j++){
C[j]=1.0F;
}
hipMalloc((void**)&A_d,N*sizeof(float));
hipMalloc((void**)&B_d,N*N*sizeof(float));
hipMalloc((void**)&C_d,N*sizeof(float));
hipMemcpy(A_d,A,N*sizeof(float),hipMemcpyHostToDevice);
hipMemcpy(B_d,B,N*N*sizeof(float),hipMemcpyHostToDevice);
hipMemcpy(C_d,C,N*sizeof(float),hipMemcpyHostToDevice);
matrix_vector_multi_gpu_1_2<<<blocks,threads>>>(A_d,B_d,C_d);
hipMemcpy(A,A_d,N*sizeof(float),hipMemcpyDeviceToHost);
for(j=0;j<N;j++){
printf("A[ %d ]=%f \n",j,A[j]);
}
hipFree(A_d);
hipFree(B_d);
hipFree(C_d);
return 0;
} | .text
.file "Matrix-cuda-2.hip"
.globl _Z42__device_stub__matrix_vector_multi_gpu_1_2PfS_S_ # -- Begin function _Z42__device_stub__matrix_vector_multi_gpu_1_2PfS_S_
.p2align 4, 0x90
.type _Z42__device_stub__matrix_vector_multi_gpu_1_2PfS_S_,@function
_Z42__device_stub__matrix_vector_multi_gpu_1_2PfS_S_: # @_Z42__device_stub__matrix_vector_multi_gpu_1_2PfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z27matrix_vector_multi_gpu_1_2PfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z42__device_stub__matrix_vector_multi_gpu_1_2PfS_S_, .Lfunc_end0-_Z42__device_stub__matrix_vector_multi_gpu_1_2PfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3f70000000000000 # double 0.00390625
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $264320, %rsp # imm = 0x40880
.cfi_def_cfa_offset 264336
.cfi_offset %rbx, -16
leaq 2176(%rsp), %rax
xorl %ecx, %ecx
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB1_1: # %.preheader23
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorps %xmm1, %xmm1
cvtsi2sd %ecx, %xmm1
mulsd %xmm0, %xmm1
cvtsd2ss %xmm1, %xmm1
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movss %xmm1, (%rax,%rdx,4)
incq %rdx
cmpq $256, %rdx # imm = 0x100
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %rcx
addq $1024, %rax # imm = 0x400
cmpq $256, %rcx # imm = 0x100
jne .LBB1_1
# %bb.4: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_5: # %.preheader
# =>This Inner Loop Header: Depth=1
movl $1065353216, 1152(%rsp,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $256, %rax # imm = 0x100
jne .LBB1_5
# %bb.6:
movq %rsp, %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
leaq 16(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movq (%rsp), %rdi
leaq 128(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 2176(%rsp), %rsi
movl $262144, %edx # imm = 0x40000
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 1152(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 1(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq (%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z27matrix_vector_multi_gpu_1_2PfS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
movq (%rsp), %rsi
leaq 128(%rsp), %rdi
movl $1024, %edx # imm = 0x400
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_9: # =>This Inner Loop Header: Depth=1
movss 128(%rsp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movl %ebx, %esi
movb $1, %al
callq printf
incq %rbx
cmpq $256, %rbx # imm = 0x100
jne .LBB1_9
# %bb.10:
movq (%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $264320, %rsp # imm = 0x40880
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27matrix_vector_multi_gpu_1_2PfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z27matrix_vector_multi_gpu_1_2PfS_S_,@object # @_Z27matrix_vector_multi_gpu_1_2PfS_S_
.section .rodata,"a",@progbits
.globl _Z27matrix_vector_multi_gpu_1_2PfS_S_
.p2align 3, 0x0
_Z27matrix_vector_multi_gpu_1_2PfS_S_:
.quad _Z42__device_stub__matrix_vector_multi_gpu_1_2PfS_S_
.size _Z27matrix_vector_multi_gpu_1_2PfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "A[ %d ]=%f \n"
.size .L.str, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z27matrix_vector_multi_gpu_1_2PfS_S_"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z42__device_stub__matrix_vector_multi_gpu_1_2PfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z27matrix_vector_multi_gpu_1_2PfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z27matrix_vector_multi_gpu_1_2PfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIADD3 UR4, UP0, UR4, 0x20, URZ ; /* 0x0000002004047890 */
/* 0x000fe4000ff1e03f */
/*0040*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0050*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200087fe43f */
/*0060*/ SHF.L.U32 R0, R0, 0x7, RZ ; /* 0x0000000700007819 */
/* 0x001fc800000006ff */
/*0070*/ IADD3 R8, R0, 0x7f, RZ ; /* 0x0000007f00087810 */
/* 0x000fe40007ffe0ff */
/*0080*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x005fe200000001ff */
/*0090*/ MOV R4, UR4 ; /* 0x0000000400047c02 */
/* 0x000fe20008000f00 */
/*00a0*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fe200000001ff */
/*00b0*/ MOV R5, UR5 ; /* 0x0000000500057c02 */
/* 0x000fe40008000f00 */
/*00c0*/ SHF.L.U32 R7, R0.reuse, 0x8, RZ ; /* 0x0000000800077819 */
/* 0x040fe400000006ff */
/*00d0*/ ISETP.GE.AND P3, PT, R0.reuse, R8, PT ; /* 0x000000080000720c */
/* 0x040fe40003f66270 */
/*00e0*/ MOV R11, RZ ; /* 0x000000ff000b7202 */
/* 0x000fe20000000f00 */
/*00f0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fe200078e0203 */
/*0100*/ MOV R6, c[0x0][0x170] ; /* 0x00005c0000067a02 */
/* 0x000fc40000000f00 */
/*0110*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe20007ffe0ff */
/*0120*/ IMAD.WIDE R4, R7, 0x4, R4 ; /* 0x0000000407047825 */
/* 0x000fe200078e0204 */
/*0130*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e2000c101906 */
/*0140*/ MOV R7, c[0x0][0x174] ; /* 0x00005d0000077a02 */
/* 0x000fca0000000f00 */
/*0150*/ LDG.E R10, [R6.64] ; /* 0x00000006060a7981 */
/* 0x004ea8000c1e1900 */
/*0160*/ LDG.E R12, [R4.64+-0x20] ; /* 0xffffe006040c7981 */
/* 0x000ea4000c1e1900 */
/*0170*/ FFMA R11, R10, R12, R11 ; /* 0x0000000c0a0b7223 */
/* 0x004fca000000000b */
/*0180*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101906 */
/*0190*/ LDG.E R10, [R6.64+0x4] ; /* 0x00000406060a7981 */
/* 0x000ea8000c1e1900 */
/*01a0*/ LDG.E R12, [R4.64+-0x1c] ; /* 0xffffe406040c7981 */
/* 0x000ea4000c1e1900 */
/*01b0*/ FFMA R13, R10, R12, R11 ; /* 0x0000000c0a0d7223 */
/* 0x004fca000000000b */
/*01c0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101906 */
/*01d0*/ LDG.E R10, [R6.64+0x8] ; /* 0x00000806060a7981 */
/* 0x000ee8000c1e1900 */
/*01e0*/ LDG.E R12, [R4.64+-0x18] ; /* 0xffffe806040c7981 */
/* 0x000ee4000c1e1900 */
/*01f0*/ FFMA R15, R10, R12, R13 ; /* 0x0000000c0a0f7223 */
/* 0x008fca000000000d */
/*0200*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0007e8000c101906 */
/*0210*/ LDG.E R10, [R6.64+0xc] ; /* 0x00000c06060a7981 */
/* 0x000e68000c1e1900 */
/*0220*/ LDG.E R12, [R4.64+-0x14] ; /* 0xffffec06040c7981 */
/* 0x000e64000c1e1900 */
/*0230*/ FFMA R11, R10, R12, R15 ; /* 0x0000000c0a0b7223 */
/* 0x002fca000000000f */
/*0240*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101906 */
/*0250*/ LDG.E R10, [R6.64+0x10] ; /* 0x00001006060a7981 */
/* 0x000ea8000c1e1900 */
/*0260*/ LDG.E R12, [R4.64+-0x10] ; /* 0xfffff006040c7981 */
/* 0x000ea4000c1e1900 */
/*0270*/ FFMA R13, R10, R12, R11 ; /* 0x0000000c0a0d7223 */
/* 0x004fca000000000b */
/*0280*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101906 */
/*0290*/ LDG.E R10, [R6.64+0x14] ; /* 0x00001406060a7981 */
/* 0x000ee8000c1e1900 */
/*02a0*/ LDG.E R12, [R4.64+-0xc] ; /* 0xfffff406040c7981 */
/* 0x000ee4000c1e1900 */
/*02b0*/ FFMA R15, R10, R12, R13 ; /* 0x0000000c0a0f7223 */
/* 0x008fca000000000d */
/*02c0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0007e8000c101906 */
/*02d0*/ LDG.E R10, [R6.64+0x18] ; /* 0x00001806060a7981 */
/* 0x000e68000c1e1900 */
/*02e0*/ LDG.E R12, [R4.64+-0x8] ; /* 0xfffff806040c7981 */
/* 0x000e64000c1e1900 */
/*02f0*/ FFMA R11, R10, R12, R15 ; /* 0x0000000c0a0b7223 */
/* 0x002fca000000000f */
/*0300*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101906 */
/*0310*/ LDG.E R10, [R6.64+0x1c] ; /* 0x00001c06060a7981 */
/* 0x000ea8000c1e1900 */
/*0320*/ LDG.E R12, [R4.64+-0x4] ; /* 0xfffffc06040c7981 */
/* 0x000ea4000c1e1900 */
/*0330*/ FFMA R13, R10, R12, R11 ; /* 0x0000000c0a0d7223 */
/* 0x004fca000000000b */
/*0340*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101906 */
/*0350*/ LDG.E R10, [R6.64+0x20] ; /* 0x00002006060a7981 */
/* 0x000ee8000c1e1900 */
/*0360*/ LDG.E R12, [R4.64] ; /* 0x00000006040c7981 */
/* 0x000ee4000c1e1900 */
/*0370*/ FFMA R15, R10, R12, R13 ; /* 0x0000000c0a0f7223 */
/* 0x008fca000000000d */
/*0380*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0007e8000c101906 */
/*0390*/ LDG.E R10, [R6.64+0x24] ; /* 0x00002406060a7981 */
/* 0x000e68000c1e1900 */
/*03a0*/ LDG.E R12, [R4.64+0x4] ; /* 0x00000406040c7981 */
/* 0x000e64000c1e1900 */
/*03b0*/ FFMA R11, R10, R12, R15 ; /* 0x0000000c0a0b7223 */
/* 0x002fca000000000f */
/*03c0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101906 */
/*03d0*/ LDG.E R10, [R6.64+0x28] ; /* 0x00002806060a7981 */
/* 0x000ea8000c1e1900 */
/*03e0*/ LDG.E R12, [R4.64+0x8] ; /* 0x00000806040c7981 */
/* 0x000ea4000c1e1900 */
/*03f0*/ FFMA R13, R10, R12, R11 ; /* 0x0000000c0a0d7223 */
/* 0x004fca000000000b */
/*0400*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101906 */
/*0410*/ LDG.E R10, [R6.64+0x2c] ; /* 0x00002c06060a7981 */
/* 0x000ee8000c1e1900 */
/*0420*/ LDG.E R12, [R4.64+0xc] ; /* 0x00000c06040c7981 */
/* 0x000ee4000c1e1900 */
/*0430*/ FFMA R15, R10, R12, R13 ; /* 0x0000000c0a0f7223 */
/* 0x008fca000000000d */
/*0440*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0007e8000c101906 */
/*0450*/ LDG.E R10, [R6.64+0x30] ; /* 0x00003006060a7981 */
/* 0x000e68000c1e1900 */
/*0460*/ LDG.E R12, [R4.64+0x10] ; /* 0x00001006040c7981 */
/* 0x000e64000c1e1900 */
/*0470*/ FFMA R11, R10, R12, R15 ; /* 0x0000000c0a0b7223 */
/* 0x002fca000000000f */
/*0480*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101906 */
/*0490*/ LDG.E R10, [R6.64+0x34] ; /* 0x00003406060a7981 */
/* 0x000ea8000c1e1900 */
/*04a0*/ LDG.E R12, [R4.64+0x14] ; /* 0x00001406040c7981 */
/* 0x000ea4000c1e1900 */
/*04b0*/ FFMA R13, R10, R12, R11 ; /* 0x0000000c0a0d7223 */
/* 0x004fca000000000b */
/*04c0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101906 */
/*04d0*/ LDG.E R10, [R6.64+0x38] ; /* 0x00003806060a7981 */
/* 0x000ee8000c1e1900 */
/*04e0*/ LDG.E R12, [R4.64+0x18] ; /* 0x00001806040c7981 */
/* 0x000ee4000c1e1900 */
/*04f0*/ FFMA R15, R10, R12, R13 ; /* 0x0000000c0a0f7223 */
/* 0x008fca000000000d */
/*0500*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0005e8000c101906 */
/*0510*/ LDG.E R10, [R6.64+0x3c] ; /* 0x00003c06060a7981 */
/* 0x000668000c1e1900 */
/*0520*/ LDG.E R12, [R4.64+0x1c] ; /* 0x00001c06040c7981 */
/* 0x000862000c1e1900 */
/*0530*/ IADD3 R9, R9, 0x10, RZ ; /* 0x0000001009097810 */
/* 0x000fc80007ffe0ff */
/*0540*/ ISETP.NE.AND P0, PT, R9, 0x100, PT ; /* 0x000001000900780c */
/* 0x000fe40003f05270 */
/*0550*/ IADD3 R6, P2, R6, 0x40, RZ ; /* 0x0000004006067810 */
/* 0x008fe40007f5e0ff */
/*0560*/ IADD3 R4, P1, R4, 0x40, RZ ; /* 0x0000004004047810 */
/* 0x010fe40007f3e0ff */
/*0570*/ IADD3.X R7, RZ, R7, RZ, P2, !PT ; /* 0x00000007ff077210 */
/* 0x000fe400017fe4ff */
/*0580*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x000fe20000ffe4ff */
/*0590*/ FFMA R11, R10, R12, R15 ; /* 0x0000000c0a0b7223 */
/* 0x002fca000000000f */
/*05a0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e2000c101906 */
/*05b0*/ @P0 BRA 0x150 ; /* 0xfffffb9000000947 */
/* 0x000fea000383ffff */
/*05c0*/ @!P3 BRA 0x80 ; /* 0xfffffab00000b947 */
/* 0x000fea000383ffff */
/*05d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05e0*/ BRA 0x5e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z27matrix_vector_multi_gpu_1_2PfS_S_
.globl _Z27matrix_vector_multi_gpu_1_2PfS_S_
.p2align 8
.type _Z27matrix_vector_multi_gpu_1_2PfS_S_,@function
_Z27matrix_vector_multi_gpu_1_2PfS_S_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_lshlrev_b32_e32 v3, 17, v0
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 7, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_or_b32_e32 v0, 0x7f, v1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, s0, s6, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, null, s7, 0, s0
s_mov_b32 s6, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_mov_b32_e32 v7, 0
s_mov_b64 s[0:1], 0
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_store_b32 v[3:4], v2, off
.LBB0_2:
v_add_co_u32 v8, vcc_lo, v5, s0
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v6, vcc_lo
s_add_u32 s8, s2, s0
s_addc_u32 s9, s3, s1
global_load_b32 v10, v2, s[8:9]
global_load_b32 v8, v[8:9], off
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmpk_lg_i32 s0, 0x400
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v7, v8, v10
global_store_b32 v[3:4], v7, off
s_cbranch_scc1 .LBB0_2
v_add_nc_u32_e32 v3, 1, v1
v_cmp_eq_u32_e32 vcc_lo, v1, v0
v_add_co_u32 v5, s0, v5, 0x400
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e64 v6, s0, 0, v6, s0
v_mov_b32_e32 v1, v3
s_or_b32 s6, vcc_lo, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_1
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z27matrix_vector_multi_gpu_1_2PfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 10
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z27matrix_vector_multi_gpu_1_2PfS_S_, .Lfunc_end0-_Z27matrix_vector_multi_gpu_1_2PfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z27matrix_vector_multi_gpu_1_2PfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z27matrix_vector_multi_gpu_1_2PfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001634ae_00000000-6_Matrix-cuda-2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z27matrix_vector_multi_gpu_1_2PfS_S_PfS_S_
.type _Z51__device_stub__Z27matrix_vector_multi_gpu_1_2PfS_S_PfS_S_, @function
_Z51__device_stub__Z27matrix_vector_multi_gpu_1_2PfS_S_PfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z27matrix_vector_multi_gpu_1_2PfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z51__device_stub__Z27matrix_vector_multi_gpu_1_2PfS_S_PfS_S_, .-_Z51__device_stub__Z27matrix_vector_multi_gpu_1_2PfS_S_PfS_S_
.globl _Z27matrix_vector_multi_gpu_1_2PfS_S_
.type _Z27matrix_vector_multi_gpu_1_2PfS_S_, @function
_Z27matrix_vector_multi_gpu_1_2PfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z27matrix_vector_multi_gpu_1_2PfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z27matrix_vector_multi_gpu_1_2PfS_S_, .-_Z27matrix_vector_multi_gpu_1_2PfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "A[ %d ]=%f \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
leaq -262144(%rsp), %r11
.cfi_def_cfa 11, 262168
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $2120, %rsp
.cfi_def_cfa_offset 264288
movq %fs:40, %rax
movq %rax, 264248(%rsp)
xorl %eax, %eax
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $2, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
leaq 3120(%rsp), %rdx
movl $0, %ecx
movss .LC0(%rip), %xmm1
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %ecx, %xmm0
mulss %xmm1, %xmm0
leaq -1024(%rdx), %rax
.L13:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L13
addl $1, %ecx
addq $1024, %rdx
cmpl $256, %ecx
jne .L12
leaq 1072(%rsp), %rax
leaq 2096(%rsp), %rdx
movss .LC1(%rip), %xmm0
.L15:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L15
movq %rsp, %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $262144, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $1024, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 2096(%rsp), %rsi
movl $1, %ecx
movl $262144, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 1072(%rsp), %rsi
movl $1, %ecx
movl $1024, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl 44(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movq 24(%rsp), %rdi
movl 32(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L16:
leaq 48(%rsp), %rdi
movl $2, %ecx
movl $1024, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC2(%rip), %rbp
.L17:
pxor %xmm0, %xmm0
cvtss2sd 48(%rsp,%rbx,4), %xmm0
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $256, %rbx
jne .L17
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 264248(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $264264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z51__device_stub__Z27matrix_vector_multi_gpu_1_2PfS_S_PfS_S_
jmp .L16
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "_Z27matrix_vector_multi_gpu_1_2PfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z27matrix_vector_multi_gpu_1_2PfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 998244352
.align 4
.LC1:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Matrix-cuda-2.hip"
.globl _Z42__device_stub__matrix_vector_multi_gpu_1_2PfS_S_ # -- Begin function _Z42__device_stub__matrix_vector_multi_gpu_1_2PfS_S_
.p2align 4, 0x90
.type _Z42__device_stub__matrix_vector_multi_gpu_1_2PfS_S_,@function
_Z42__device_stub__matrix_vector_multi_gpu_1_2PfS_S_: # @_Z42__device_stub__matrix_vector_multi_gpu_1_2PfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z27matrix_vector_multi_gpu_1_2PfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z42__device_stub__matrix_vector_multi_gpu_1_2PfS_S_, .Lfunc_end0-_Z42__device_stub__matrix_vector_multi_gpu_1_2PfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3f70000000000000 # double 0.00390625
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $264320, %rsp # imm = 0x40880
.cfi_def_cfa_offset 264336
.cfi_offset %rbx, -16
leaq 2176(%rsp), %rax
xorl %ecx, %ecx
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB1_1: # %.preheader23
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorps %xmm1, %xmm1
cvtsi2sd %ecx, %xmm1
mulsd %xmm0, %xmm1
cvtsd2ss %xmm1, %xmm1
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movss %xmm1, (%rax,%rdx,4)
incq %rdx
cmpq $256, %rdx # imm = 0x100
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %rcx
addq $1024, %rax # imm = 0x400
cmpq $256, %rcx # imm = 0x100
jne .LBB1_1
# %bb.4: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_5: # %.preheader
# =>This Inner Loop Header: Depth=1
movl $1065353216, 1152(%rsp,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $256, %rax # imm = 0x100
jne .LBB1_5
# %bb.6:
movq %rsp, %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
leaq 16(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movq (%rsp), %rdi
leaq 128(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 2176(%rsp), %rsi
movl $262144, %edx # imm = 0x40000
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 1152(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 1(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq (%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z27matrix_vector_multi_gpu_1_2PfS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
movq (%rsp), %rsi
leaq 128(%rsp), %rdi
movl $1024, %edx # imm = 0x400
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_9: # =>This Inner Loop Header: Depth=1
movss 128(%rsp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movl %ebx, %esi
movb $1, %al
callq printf
incq %rbx
cmpq $256, %rbx # imm = 0x100
jne .LBB1_9
# %bb.10:
movq (%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $264320, %rsp # imm = 0x40880
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27matrix_vector_multi_gpu_1_2PfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z27matrix_vector_multi_gpu_1_2PfS_S_,@object # @_Z27matrix_vector_multi_gpu_1_2PfS_S_
.section .rodata,"a",@progbits
.globl _Z27matrix_vector_multi_gpu_1_2PfS_S_
.p2align 3, 0x0
_Z27matrix_vector_multi_gpu_1_2PfS_S_:
.quad _Z42__device_stub__matrix_vector_multi_gpu_1_2PfS_S_
.size _Z27matrix_vector_multi_gpu_1_2PfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "A[ %d ]=%f \n"
.size .L.str, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z27matrix_vector_multi_gpu_1_2PfS_S_"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z42__device_stub__matrix_vector_multi_gpu_1_2PfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z27matrix_vector_multi_gpu_1_2PfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void gpu_init(int *mapad, int max, int size)
{
/*Identificaciones necesarios*/
int IDX_Thread = threadIdx.x;
int IDY_Thread = threadIdx.y;
int IDX_block = blockIdx.x;
int IDY_block = blockIdx.y;
int shapeGrid_X = gridDim.x;
int threads_per_block = blockDim.x * blockDim.y;
int position = threads_per_block * ((IDY_block * shapeGrid_X)+IDX_block)+((IDY_Thread*blockDim.x)+IDX_Thread);
if (position<size) mapad[position] = max;
} | code for sm_80
Function : _Z8gpu_initPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0030*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000e680000002200 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000ea20000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0xc], R5 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0205 */
/*0060*/ IMAD R0, R0, c[0x0][0x4], R7 ; /* 0x0000010000007a24 */
/* 0x002fc800078e0207 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x004fca00078e0203 */
/*0080*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*00b0*/ MOV R5, c[0x0][0x168] ; /* 0x00005a0000057a02 */
/* 0x000fe20000000f00 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*00e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void gpu_init(int *mapad, int max, int size)
{
/*Identificaciones necesarios*/
int IDX_Thread = threadIdx.x;
int IDY_Thread = threadIdx.y;
int IDX_block = blockIdx.x;
int IDY_block = blockIdx.y;
int shapeGrid_X = gridDim.x;
int threads_per_block = blockDim.x * blockDim.y;
int position = threads_per_block * ((IDY_block * shapeGrid_X)+IDX_block)+((IDY_Thread*blockDim.x)+IDX_Thread);
if (position<size) mapad[position] = max;
} | .file "tmpxft_0010c080_00000000-6_gpu_init.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z8gpu_initPiiiPiii
.type _Z29__device_stub__Z8gpu_initPiiiPiii, @function
_Z29__device_stub__Z8gpu_initPiiiPiii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8gpu_initPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z8gpu_initPiiiPiii, .-_Z29__device_stub__Z8gpu_initPiiiPiii
.globl _Z8gpu_initPiii
.type _Z8gpu_initPiii, @function
_Z8gpu_initPiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z8gpu_initPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8gpu_initPiii, .-_Z8gpu_initPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8gpu_initPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8gpu_initPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void gpu_init(int *mapad, int max, int size)
{
/*Identificaciones necesarios*/
int IDX_Thread = threadIdx.x;
int IDY_Thread = threadIdx.y;
int IDX_block = blockIdx.x;
int IDY_block = blockIdx.y;
int shapeGrid_X = gridDim.x;
int threads_per_block = blockDim.x * blockDim.y;
int position = threads_per_block * ((IDY_block * shapeGrid_X)+IDX_block)+((IDY_Thread*blockDim.x)+IDX_Thread);
if (position<size) mapad[position] = max;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gpu_init(int *mapad, int max, int size)
{
/*Identificaciones necesarios*/
int IDX_Thread = threadIdx.x;
int IDY_Thread = threadIdx.y;
int IDX_block = blockIdx.x;
int IDY_block = blockIdx.y;
int shapeGrid_X = gridDim.x;
int threads_per_block = blockDim.x * blockDim.y;
int position = threads_per_block * ((IDY_block * shapeGrid_X)+IDX_block)+((IDY_Thread*blockDim.x)+IDX_Thread);
if (position<size) mapad[position] = max;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gpu_init(int *mapad, int max, int size)
{
/*Identificaciones necesarios*/
int IDX_Thread = threadIdx.x;
int IDY_Thread = threadIdx.y;
int IDX_block = blockIdx.x;
int IDY_block = blockIdx.y;
int shapeGrid_X = gridDim.x;
int threads_per_block = blockDim.x * blockDim.y;
int position = threads_per_block * ((IDY_block * shapeGrid_X)+IDX_block)+((IDY_Thread*blockDim.x)+IDX_Thread);
if (position<size) mapad[position] = max;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8gpu_initPiii
.globl _Z8gpu_initPiii
.p2align 8
.type _Z8gpu_initPiii,@function
_Z8gpu_initPiii:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0xc
s_load_b32 s4, s[0:1], 0x1c
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_lshr_b32 s5, s4, 16
s_add_i32 s3, s3, s14
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s3, s5, v[1:2]
v_and_b32_e32 v3, 0x3ff, v0
s_and_b32 s3, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, v2, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x8
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_mov_b32_e32 v2, s0
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8gpu_initPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8gpu_initPiii, .Lfunc_end0-_Z8gpu_initPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8gpu_initPiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8gpu_initPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gpu_init(int *mapad, int max, int size)
{
/*Identificaciones necesarios*/
int IDX_Thread = threadIdx.x;
int IDY_Thread = threadIdx.y;
int IDX_block = blockIdx.x;
int IDY_block = blockIdx.y;
int shapeGrid_X = gridDim.x;
int threads_per_block = blockDim.x * blockDim.y;
int position = threads_per_block * ((IDY_block * shapeGrid_X)+IDX_block)+((IDY_Thread*blockDim.x)+IDX_Thread);
if (position<size) mapad[position] = max;
} | .text
.file "gpu_init.hip"
.globl _Z23__device_stub__gpu_initPiii # -- Begin function _Z23__device_stub__gpu_initPiii
.p2align 4, 0x90
.type _Z23__device_stub__gpu_initPiii,@function
_Z23__device_stub__gpu_initPiii: # @_Z23__device_stub__gpu_initPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8gpu_initPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z23__device_stub__gpu_initPiii, .Lfunc_end0-_Z23__device_stub__gpu_initPiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8gpu_initPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8gpu_initPiii,@object # @_Z8gpu_initPiii
.section .rodata,"a",@progbits
.globl _Z8gpu_initPiii
.p2align 3, 0x0
_Z8gpu_initPiii:
.quad _Z23__device_stub__gpu_initPiii
.size _Z8gpu_initPiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8gpu_initPiii"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__gpu_initPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8gpu_initPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8gpu_initPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0030*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000e680000002200 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000ea20000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0xc], R5 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0205 */
/*0060*/ IMAD R0, R0, c[0x0][0x4], R7 ; /* 0x0000010000007a24 */
/* 0x002fc800078e0207 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x004fca00078e0203 */
/*0080*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*00b0*/ MOV R5, c[0x0][0x168] ; /* 0x00005a0000057a02 */
/* 0x000fe20000000f00 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*00e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8gpu_initPiii
.globl _Z8gpu_initPiii
.p2align 8
.type _Z8gpu_initPiii,@function
_Z8gpu_initPiii:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0xc
s_load_b32 s4, s[0:1], 0x1c
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_lshr_b32 s5, s4, 16
s_add_i32 s3, s3, s14
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s3, s5, v[1:2]
v_and_b32_e32 v3, 0x3ff, v0
s_and_b32 s3, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, v2, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x8
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_mov_b32_e32 v2, s0
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8gpu_initPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8gpu_initPiii, .Lfunc_end0-_Z8gpu_initPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8gpu_initPiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8gpu_initPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010c080_00000000-6_gpu_init.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z8gpu_initPiiiPiii
.type _Z29__device_stub__Z8gpu_initPiiiPiii, @function
_Z29__device_stub__Z8gpu_initPiiiPiii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8gpu_initPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z8gpu_initPiiiPiii, .-_Z29__device_stub__Z8gpu_initPiiiPiii
.globl _Z8gpu_initPiii
.type _Z8gpu_initPiii, @function
_Z8gpu_initPiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z8gpu_initPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8gpu_initPiii, .-_Z8gpu_initPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8gpu_initPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8gpu_initPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gpu_init.hip"
.globl _Z23__device_stub__gpu_initPiii # -- Begin function _Z23__device_stub__gpu_initPiii
.p2align 4, 0x90
.type _Z23__device_stub__gpu_initPiii,@function
_Z23__device_stub__gpu_initPiii: # @_Z23__device_stub__gpu_initPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8gpu_initPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z23__device_stub__gpu_initPiii, .Lfunc_end0-_Z23__device_stub__gpu_initPiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8gpu_initPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8gpu_initPiii,@object # @_Z8gpu_initPiii
.section .rodata,"a",@progbits
.globl _Z8gpu_initPiii
.p2align 3, 0x0
_Z8gpu_initPiii:
.quad _Z23__device_stub__gpu_initPiii
.size _Z8gpu_initPiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8gpu_initPiii"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__gpu_initPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8gpu_initPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
// Kernel to add two integers
__global__ void add(int *a, int *b, int *c){
*c = *a + *b;
}
// Main program
int main(void){
int *a,*b,*c; // Host copies
int *a_dev,*b_dev,*c_dev; // Device copies
int size = sizeof(int);
// Allocate host memory
a = (int *) malloc (size);
b = (int *) malloc (size);
c = (int *) malloc (size);
// Allocate device memory
cudaMalloc( (void**)&a_dev, size);
cudaMalloc( (void**)&b_dev, size);
cudaMalloc( (void**)&c_dev, size);
// Initialize
*a = 1;
*b = 2;
// Copy inputs to device
cudaMemcpy( a_dev, a, size, cudaMemcpyHostToDevice );
cudaMemcpy( b_dev, b, size, cudaMemcpyHostToDevice );
// Launch kernel on device
add <<<1,1>>> (a_dev,b_dev,c_dev);
// Copy device result back to host
cudaMemcpy( c, c_dev, size, cudaMemcpyDeviceToHost );
// Print result
printf("%d\n",*c);
// Free device memory
cudaFree(a_dev);
cudaFree(b_dev);
cudaFree(c_dev);
// Free host memory
free(a);
free(b);
free(c);
return 0;
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fe20000000f00 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */
/* 0x000fe200078e00ff */
/*0090*/ MOV R7, c[0x0][0x174] ; /* 0x00005d0000077a02 */
/* 0x000fe40000000f00 */
/*00a0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00b0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
// Kernel to add two integers
__global__ void add(int *a, int *b, int *c){
*c = *a + *b;
}
// Main program
int main(void){
int *a,*b,*c; // Host copies
int *a_dev,*b_dev,*c_dev; // Device copies
int size = sizeof(int);
// Allocate host memory
a = (int *) malloc (size);
b = (int *) malloc (size);
c = (int *) malloc (size);
// Allocate device memory
cudaMalloc( (void**)&a_dev, size);
cudaMalloc( (void**)&b_dev, size);
cudaMalloc( (void**)&c_dev, size);
// Initialize
*a = 1;
*b = 2;
// Copy inputs to device
cudaMemcpy( a_dev, a, size, cudaMemcpyHostToDevice );
cudaMemcpy( b_dev, b, size, cudaMemcpyHostToDevice );
// Launch kernel on device
add <<<1,1>>> (a_dev,b_dev,c_dev);
// Copy device result back to host
cudaMemcpy( c, c_dev, size, cudaMemcpyDeviceToHost );
// Print result
printf("%d\n",*c);
// Free device memory
cudaFree(a_dev);
cudaFree(b_dev);
cudaFree(c_dev);
// Free host memory
free(a);
free(b);
free(c);
return 0;
} | .file "tmpxft_000b6f6e_00000000-6_sum_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4, %edi
call malloc@PLT
movq %rax, %r12
movl $4, %edi
call malloc@PLT
movq %rax, %rbp
movl $4, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, (%r12)
movl $2, 0(%rbp)
movl $1, %ecx
movl $4, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl (%rbx), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
// Kernel to add two integers
__global__ void add(int *a, int *b, int *c){
*c = *a + *b;
}
// Main program
int main(void){
int *a,*b,*c; // Host copies
int *a_dev,*b_dev,*c_dev; // Device copies
int size = sizeof(int);
// Allocate host memory
a = (int *) malloc (size);
b = (int *) malloc (size);
c = (int *) malloc (size);
// Allocate device memory
cudaMalloc( (void**)&a_dev, size);
cudaMalloc( (void**)&b_dev, size);
cudaMalloc( (void**)&c_dev, size);
// Initialize
*a = 1;
*b = 2;
// Copy inputs to device
cudaMemcpy( a_dev, a, size, cudaMemcpyHostToDevice );
cudaMemcpy( b_dev, b, size, cudaMemcpyHostToDevice );
// Launch kernel on device
add <<<1,1>>> (a_dev,b_dev,c_dev);
// Copy device result back to host
cudaMemcpy( c, c_dev, size, cudaMemcpyDeviceToHost );
// Print result
printf("%d\n",*c);
// Free device memory
cudaFree(a_dev);
cudaFree(b_dev);
cudaFree(c_dev);
// Free host memory
free(a);
free(b);
free(c);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
// Kernel to add two integers
__global__ void add(int *a, int *b, int *c){
*c = *a + *b;
}
// Main program
int main(void){
int *a,*b,*c; // Host copies
int *a_dev,*b_dev,*c_dev; // Device copies
int size = sizeof(int);
// Allocate host memory
a = (int *) malloc (size);
b = (int *) malloc (size);
c = (int *) malloc (size);
// Allocate device memory
hipMalloc( (void**)&a_dev, size);
hipMalloc( (void**)&b_dev, size);
hipMalloc( (void**)&c_dev, size);
// Initialize
*a = 1;
*b = 2;
// Copy inputs to device
hipMemcpy( a_dev, a, size, hipMemcpyHostToDevice );
hipMemcpy( b_dev, b, size, hipMemcpyHostToDevice );
// Launch kernel on device
add <<<1,1>>> (a_dev,b_dev,c_dev);
// Copy device result back to host
hipMemcpy( c, c_dev, size, hipMemcpyDeviceToHost );
// Print result
printf("%d\n",*c);
// Free device memory
hipFree(a_dev);
hipFree(b_dev);
hipFree(c_dev);
// Free host memory
free(a);
free(b);
free(c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
// Kernel to add two integers
__global__ void add(int *a, int *b, int *c){
*c = *a + *b;
}
// Main program
int main(void){
int *a,*b,*c; // Host copies
int *a_dev,*b_dev,*c_dev; // Device copies
int size = sizeof(int);
// Allocate host memory
a = (int *) malloc (size);
b = (int *) malloc (size);
c = (int *) malloc (size);
// Allocate device memory
hipMalloc( (void**)&a_dev, size);
hipMalloc( (void**)&b_dev, size);
hipMalloc( (void**)&c_dev, size);
// Initialize
*a = 1;
*b = 2;
// Copy inputs to device
hipMemcpy( a_dev, a, size, hipMemcpyHostToDevice );
hipMemcpy( b_dev, b, size, hipMemcpyHostToDevice );
// Launch kernel on device
add <<<1,1>>> (a_dev,b_dev,c_dev);
// Copy device result back to host
hipMemcpy( c, c_dev, size, hipMemcpyDeviceToHost );
// Print result
printf("%d\n",*c);
// Free device memory
hipFree(a_dev);
hipFree(b_dev);
hipFree(c_dev);
// Free host memory
free(a);
free(b);
free(c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[4:5], 0x0
s_load_b32 s3, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
// Kernel to add two integers
__global__ void add(int *a, int *b, int *c){
*c = *a + *b;
}
// Main program
int main(void){
int *a,*b,*c; // Host copies
int *a_dev,*b_dev,*c_dev; // Device copies
int size = sizeof(int);
// Allocate host memory
a = (int *) malloc (size);
b = (int *) malloc (size);
c = (int *) malloc (size);
// Allocate device memory
hipMalloc( (void**)&a_dev, size);
hipMalloc( (void**)&b_dev, size);
hipMalloc( (void**)&c_dev, size);
// Initialize
*a = 1;
*b = 2;
// Copy inputs to device
hipMemcpy( a_dev, a, size, hipMemcpyHostToDevice );
hipMemcpy( b_dev, b, size, hipMemcpyHostToDevice );
// Launch kernel on device
add <<<1,1>>> (a_dev,b_dev,c_dev);
// Copy device result back to host
hipMemcpy( c, c_dev, size, hipMemcpyDeviceToHost );
// Print result
printf("%d\n",*c);
// Free device memory
hipFree(a_dev);
hipFree(b_dev);
hipFree(c_dev);
// Free host memory
free(a);
free(b);
free(c);
return 0;
} | .text
.file "sum_gpu.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4, %edi
callq malloc
movq %rax, %rbx
movl $4, %edi
callq malloc
movq %rax, %r14
movl $4, %edi
callq malloc
movq %rax, %r15
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movl $1, (%rbx)
movl $2, (%r14)
movq 16(%rsp), %rdi
movl $4, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $4, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
movl $4, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl (%r15), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d\n"
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fe20000000f00 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */
/* 0x000fe200078e00ff */
/*0090*/ MOV R7, c[0x0][0x174] ; /* 0x00005d0000077a02 */
/* 0x000fe40000000f00 */
/*00a0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00b0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[4:5], 0x0
s_load_b32 s3, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b6f6e_00000000-6_sum_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4, %edi
call malloc@PLT
movq %rax, %r12
movl $4, %edi
call malloc@PLT
movq %rax, %rbp
movl $4, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, (%r12)
movl $2, 0(%rbp)
movl $1, %ecx
movl $4, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl (%rbx), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sum_gpu.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4, %edi
callq malloc
movq %rax, %rbx
movl $4, %edi
callq malloc
movq %rax, %r14
movl $4, %edi
callq malloc
movq %rax, %r15
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movl $1, (%rbx)
movl $2, (%r14)
movq 16(%rsp), %rdi
movl $4, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $4, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
movl $4, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl (%r15), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d\n"
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
*
* compiling:
* nvcc -lglut -LGLEW life.cuda.cu -o life
*
* for it's work:
* export LD_LIBRARY_PATH=:/usr/local/cuda/lib
* export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/usr/local/cuda/libnvvp/
*
* cuda-gdb
*/
#include <stdio.h>
#define uchar unsigned char
#define NUMBER_OF_THREADS 512
uchar * dev_array1;
uchar * dev_array2;
uint * dev_size_x;
uint * dev_size_y;
uint sizeX,sizeY;
// bad -> fix it
__global__ void kernel2(float * field1, float * field2, uchar4 * screen, int sizex, int sizey)
{
// int id = threadIdx.x + blockIdx.x*blockDim.x + threadIdx.y + blockIdx.y*blockDim.y;
int id = threadIdx.x+threadIdx.y;
int numberofneighbours=0;
numberofneighbours += *(field1 + id + 1);
numberofneighbours += *(field1 + id - 1);
numberofneighbours += *(field1 + id + sizey);
numberofneighbours += *(field1 + id - sizey);
numberofneighbours += *(field1 + id + sizey + 1);
numberofneighbours += *(field1 + id + sizey - 1);
numberofneighbours += *(field1 + id - sizey - 1);
numberofneighbours += *(field1 + id + sizey + 1);
// (screen + id)->x = numberofneighbours;
// (screen + id)->x = 1;
// *(field2 + id) = 1;
// if(*(field1 + id) == 1) *(field2 + id) = 1;
/*
switch(numberofneighbours)
{
case 3 : *(field2 + id) = 1;
(screen + id)->x = 0;
(screen + id)->y = 250;
(screen + id)->z = 0;
(screen + id)->w = 0;
break;
case 2 : if(*(field1 + id) == 1)
{
*(field2 + id) = 1;
(screen + id)->x = 0;
(screen + id)->y = 250;
(screen + id)->z = 0;
(screen + id)->w = 0;
}
else
{
*(field2 + id) = 0;
(screen + id)->x = 0;
(screen + id)->y = 0;
(screen + id)->z = 0;
(screen + id)->w = 0;
}
break;
default : *(field2 + id) = 0;
(screen + id)->x = 0;
(screen + id)->y = 0;
(screen + id)->z = 0;
(screen + id)->w = 0;
break;
}
*/
}
__global__ void kernel(uchar * array1, uchar * array2, uint size_x, uint size_y)
{
// int id = threadIdx.x*blockIdx.x+blockDim.x + threadIdx.y*blockIdx.y+blockDim.y;
int id = threadIdx.x+threadIdx.y;
if(id < size_x*size_y)
{
int numberofneighbours=0;
int num = 0;
// заменить на num += ...
if(*(array1 + id + 1) == 1) num++;
if(*(array1 + id - 1) == 1) num++;
if(*(array1 + id + size_y) == 1) num++;
if(*(array1 + id - size_y) == 1) num++;
if(*(array1 + id + size_y + 1) == 1) num++;
if(*(array1 + id + size_y - 1) == 1) num++;
if(*(array1 + id - size_y + 1) == 1) num++;
if(*(array1 + id - size_y - 1) == 1) num++;
switch(num)
{
case 3 : *(array2 + id) = 1; break;
case 2 : if(*(array1 + id) == 1) *(array2 + id) = 1; break;
default : *(array2 + id) = 0; break;
}
}
}
void initCuda(uchar * array1, uchar * array2, uint size_x, uint size_y)
{
sizeX = size_x;
sizeY = size_y;
cudaMalloc((void**)&dev_array1,sizeof(uchar)*size_x*size_y);
cudaMalloc((void**)&dev_array2,sizeof(uchar)*size_x*size_y);
cudaMalloc((void**)&dev_size_x,sizeof(uint));
cudaMalloc((void**)&dev_size_y,sizeof(uint));
cudaMemcpy(dev_array1,array1,sizeof(uchar)*size_x*size_y,cudaMemcpyHostToDevice);
cudaMemcpy(dev_size_x,&size_x,sizeof(uchar),cudaMemcpyHostToDevice);
cudaMemcpy(dev_size_y,&size_y,sizeof(uchar),cudaMemcpyHostToDevice);
cudaMemset(dev_array2,0,size_x*size_y);
}
void get_result(uchar * array)
{
cudaMemcpy(array,dev_array2,sizeX*sizeY*sizeof(uchar),cudaMemcpyDeviceToHost);
}
void cuda_run()
{
int threads = NUMBER_OF_THREADS;
int blocks = sizeX*sizeY/threads+1;
// kernel <<<blocks,threads>>>(dev_array1,dev_array2,dev_size_x,dev_size_y);
kernel <<<blocks,threads>>>(dev_array1,dev_array2,sizeX,sizeY);
}
void FreeCuda()
{
cudaFree(dev_array1);
cudaFree(dev_array2);
cudaFree(dev_size_x);
cudaFree(dev_size_y);
}
void check(uchar * array1, uchar * array2, uint * size_x, uint * size_y)
{
int num=0;
puts("<=================>\n");
printf("%u %u\n",*size_x,*size_y);
puts("<=================>\n");
for(int i=0;i<(*size_x * (*size_y));i++)
{
num = 0;
if(*(array1 + i + 1) == 1) num++;
if(*(array1 + i - 1) == 1) num++;
if(*(array1 + i + *size_y) == 1) num++;
if(*(array1 + i - *size_y) == 1) num++;
if(*(array1 + i + *size_y + 1) == 1) num++;
if(*(array1 + i + *size_y - 1) == 1) num++;
if(*(array1 + i - *size_y + 1) == 1) num++;
if(*(array1 + i - *size_y - 1) == 1) num++;
// *(array2 + i) = num;
switch(num)
{
case 3 : *(array2 + i) = 1; break;
case 2 : if(*(array1 + i) == 1) *(array2 + i) = 1; break;
default : *(array2 + i) = 0; break;
}
}
puts("<=================>\n");
}
#define cell_size 5
#define uchar unsigned char
#define screen_width 20
#define screen_height 20
int width = screen_width*cell_size; //770; //1024;
int height = screen_width*cell_size; //770; //768;
/*
int main()
{
// uchar field1[screen_width][screen_height];
// uchar field2[screen_width][screen_height];
uchar field1[screen_width*screen_height];
uchar field2[screen_width*screen_height];
for(int i=0;i<screen_width;i++)
{
for(int j=0;j<screen_height;j++)
{
field1[i+j*screen_width] = 0;
field2[i+j*screen_width] = 0;
}
}
field1[0+0*screen_width] = 1;
field1[0+1*screen_width] = 1;
field1[0+2*screen_width] = 1;
// field1[1][0] = 1;
field1[1+1*screen_width] = 1;
field1[3+3*screen_width] = 1;
field1[4+3*screen_width] = 1;
field1[10+5*screen_width] = 1;
field1[10+6*screen_width] = 1;
field1[11+5*screen_width] = 1;
field1[11+6*screen_width] = 1;
// field1[10][7] = 1;
for(int i=0;i<screen_width;i++)
{
for(int j=0;j<screen_height;j++)
{
if(field1[i+j*screen_width] == 1) printf("*");
else printf(".");
// printf("%c ",field1[i][j]);
}
printf("\n");
}
sizeX = 20;
sizeY = 20;
//=======================================================================
/*
check(field1,field2,&sizeX,&sizeY);
for(int i=0;i<screen_width;i++)
{
for(int j=0;j<screen_height;j++)
{
if(field2[i+j*screen_width] == 1) printf("*");
else printf("%i",(int) field2[i+j*screen_width]);
// printf("%c ",field2[i][j]);
}
printf("\n");
}
*/
//=======================================================================
/*
initCuda(&field1[0],&field2[0],screen_width,screen_height);
cuda_run();
get_result(&field2[0]);
puts("\n<==========>\n\n");
for(int i=0;i<screen_width;i++)
{
for(int j=0;j<screen_height;j++)
{
if(field2[i+j*screen_width] == 1) printf("*");
else printf("%i",(int) field2[i+j*screen_width]);
// printf("%c ",field2[i][j]);
}
printf("\n");
}
FreeCuda();
return 0;
}
*/
int main()
{
float * field1;
field1 = (float *) malloc(sizeof(float)*screen_width*screen_height);
uchar4 * screen;
screen = (uchar4 *) malloc(sizeof(uchar4)*screen_width*screen_height);
float * dev_field1;
float * dev_field2;
uchar4 * dev_screen;
*(field1 + 10) = 1;
field1[40] = 1;
field1[41] = 1;
field1[59] = 1;
field1[60] = 1;
field1[90] = 1;
field1[91] = 1;
field1[92] = 1;
for(int i=0;i<=400;i++)
{
printf("%i",(int) *(field1+i));
if(i % 19 == 0) printf("\n");
}
printf("\n");
cudaMalloc((void **)&dev_field1,sizeof(float)*screen_width*screen_height);
cudaMalloc((void **)&dev_field2,sizeof(float)*screen_width*screen_height);
cudaMalloc((void **)&dev_screen,sizeof(uchar4)*screen_width*screen_height);
cudaMemcpy(dev_field1,field1,sizeof(uchar4)*screen_width*screen_height,cudaMemcpyHostToDevice);
cudaMemset(dev_field2,8,sizeof(float)*screen_width*screen_height);
kernel2<<<10 , 10>>>(dev_field1,dev_field2,dev_screen,20,20);
float * field2;
field2 = (float *) malloc(sizeof(float)*screen_width*screen_height);
cudaMemcpy(field2,dev_field2,sizeof(float)*screen_width*screen_height,cudaMemcpyDeviceToHost);
cudaMemcpy(screen,dev_screen,sizeof(uchar4)*screen_width*screen_height,cudaMemcpyDeviceToHost);
cudaFree(dev_field1);
cudaFree(dev_field2);
cudaFree(dev_screen);
for(int i=0;i<400;i++)
{
printf("%i",(int) (screen+i)->x);
if(i % 19 == 0) printf("\n");
}
printf("\n");
for(int i=0;i<400;i++)
{
printf("%4i",(int) *(field2+i));
if(i % 19 == 0) printf("\n");
}
printf("\n");
free(field1);
free(field2);
free(screen);
} | code for sm_80
Function : _Z6kernelPhS_jj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_TID.Y ; /* 0x0000000000087919 */
/* 0x000e220000002200 */
/*0020*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff077624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0040*/ IMAD R3, R7, c[0x0][0x170], RZ ; /* 0x00005c0007037a24 */
/* 0x000fe400078e02ff */
/*0050*/ IMAD.IADD R8, R8, 0x1, R5 ; /* 0x0000000108087824 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fda0003f06070 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ SHF.R.S32.HI R0, RZ, 0x1f, R8 ; /* 0x0000001fff007819 */
/* 0x000fe20000011408 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IADD3 R2, P0, R8, c[0x0][0x160], RZ ; /* 0x0000580008027a10 */
/* 0x000fc80007f1e0ff */
/*00b0*/ IADD3.X R3, R0, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590000037a10 */
/* 0x000fe400007fe4ff */
/*00c0*/ IADD3 R4, P0, P1, R7, c[0x0][0x160], R8 ; /* 0x0000580007047a10 */
/* 0x000fc6000791e008 */
/*00d0*/ LDG.E.U8 R16, [R2.64+-0x1] ; /* 0xffffff0402107981 */
/* 0x000ea2000c1e1100 */
/*00e0*/ IADD3 R6, P2, P3, R8, c[0x0][0x160], -R7 ; /* 0x0000580008067a10 */
/* 0x000fe20007b5e807 */
/*00f0*/ IMAD.MOV.U32 R7, RZ, RZ, -0x1 ; /* 0xffffffffff077424 */
/* 0x000fe200078e00ff */
/*0100*/ IADD3.X R5, RZ, c[0x0][0x164], R0, P0, P1 ; /* 0x00005900ff057a10 */
/* 0x000fe200007e2400 */
/*0110*/ LDG.E.U8 R9, [R2.64+0x1] ; /* 0x0000010402097981 */
/* 0x000ee6000c1e1100 */
/*0120*/ IADD3.X R7, R0, c[0x0][0x164], R7, P2, P3 ; /* 0x0000590000077a10 */
/* 0x000fe200017e6407 */
/*0130*/ LDG.E.U8 R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000f28000c1e1100 */
/*0140*/ LDG.E.U8 R11, [R6.64] ; /* 0x00000004060b7981 */
/* 0x000f68000c1e1100 */
/*0150*/ LDG.E.U8 R12, [R4.64+0x1] ; /* 0x00000104040c7981 */
/* 0x000f68000c1e1100 */
/*0160*/ LDG.E.U8 R13, [R4.64+-0x1] ; /* 0xffffff04040d7981 */
/* 0x000168000c1e1100 */
/*0170*/ LDG.E.U8 R14, [R6.64+0x1] ; /* 0x00000104060e7981 */
/* 0x000f68000c1e1100 */
/*0180*/ LDG.E.U8 R15, [R6.64+-0x1] ; /* 0xffffff04060f7981 */
/* 0x000f62000c1e1100 */
/*0190*/ ISETP.NE.AND P1, PT, R16, 0x1, PT ; /* 0x000000011000780c */
/* 0x004fe20003f25270 */
/*01a0*/ IMAD.MOV.U32 R16, RZ, RZ, 0x2 ; /* 0x00000002ff107424 */
/* 0x000fe200078e00ff */
/*01b0*/ ISETP.NE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x008fc80003f05270 */
/*01c0*/ SEL R9, RZ, 0x1, P0 ; /* 0x00000001ff097807 */
/* 0x000fe40000000000 */
/*01d0*/ ISETP.NE.AND P2, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x010fca0003f45270 */
/*01e0*/ @!P1 SEL R9, R16, 0x1, !P0 ; /* 0x0000000110099807 */
/* 0x000fe40004000000 */
/*01f0*/ ISETP.NE.AND P0, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x020fe40003f05270 */
/*0200*/ SEL R10, RZ, 0x1, P2 ; /* 0x00000001ff0a7807 */
/* 0x000fe40001000000 */
/*0210*/ ISETP.NE.AND P1, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fc60003f25270 */
/*0220*/ IMAD.IADD R9, R9, 0x1, R10 ; /* 0x0000000109097824 */
/* 0x000fca00078e020a */
/*0230*/ IADD3 R4, R9, 0x1, RZ ; /* 0x0000000109047810 */
/* 0x001fe20007ffe0ff */
/*0240*/ @P0 IMAD.MOV R4, RZ, RZ, R9 ; /* 0x000000ffff040224 */
/* 0x000fe200078e0209 */
/*0250*/ ISETP.NE.AND P0, PT, R13, 0x1, PT ; /* 0x000000010d00780c */
/* 0x000fc80003f05270 */
/*0260*/ IADD3 R5, R4, 0x1, RZ ; /* 0x0000000104057810 */
/* 0x000fe20007ffe0ff */
/*0270*/ @P1 IMAD.MOV R5, RZ, RZ, R4 ; /* 0x000000ffff051224 */
/* 0x000fe200078e0204 */
/*0280*/ ISETP.NE.AND P1, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fc80003f25270 */
/*0290*/ IADD3 R4, R5, 0x1, RZ ; /* 0x0000000105047810 */
/* 0x000fc60007ffe0ff */
/*02a0*/ @P0 IMAD.MOV R4, RZ, RZ, R5 ; /* 0x000000ffff040224 */
/* 0x000fe200078e0205 */
/*02b0*/ ISETP.NE.AND P0, PT, R15, 0x1, PT ; /* 0x000000010f00780c */
/* 0x000fc80003f05270 */
/*02c0*/ IADD3 R5, R4, 0x1, RZ ; /* 0x0000000104057810 */
/* 0x000fe20007ffe0ff */
/*02d0*/ @P1 IMAD.MOV R5, RZ, RZ, R4 ; /* 0x000000ffff051224 */
/* 0x000fe200078e0204 */
/*02e0*/ IADD3 R4, P1, R8, c[0x0][0x168], RZ ; /* 0x00005a0008047a10 */
/* 0x000fc80007f3e0ff */
/*02f0*/ IADD3 R6, R5, 0x1, RZ ; /* 0x0000000105067810 */
/* 0x000fc60007ffe0ff */
/*0300*/ @P0 IMAD.MOV R6, RZ, RZ, R5 ; /* 0x000000ffff060224 */
/* 0x000fe200078e0205 */
/*0310*/ IADD3.X R5, R0, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0000057a10 */
/* 0x000fc80000ffe4ff */
/*0320*/ ISETP.NE.AND P0, PT, R6, 0x2, PT ; /* 0x000000020600780c */
/* 0x000fda0003f05270 */
/*0330*/ @!P0 BRA 0x3a0 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*0340*/ ISETP.NE.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe20003f05270 */
/*0350*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fd800078e00ff */
/*0360*/ @!P0 STG.E.U8 [R4.64], R2 ; /* 0x0000000204008986 */
/* 0x0001e2000c101104 */
/*0370*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0380*/ STG.E.U8 [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x000fe2000c101104 */
/*0390*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03a0*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1100 */
/*03b0*/ ISETP.NE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x004fda0003f05270 */
/*03c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*03d0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fca00078e00ff */
/*03e0*/ STG.E.U8 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x000fe2000c101104 */
/*03f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0400*/ BRA 0x400; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7kernel2PfS_P6uchar4ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
*
* compiling:
* nvcc -lglut -LGLEW life.cuda.cu -o life
*
* for it's work:
* export LD_LIBRARY_PATH=:/usr/local/cuda/lib
* export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/usr/local/cuda/libnvvp/
*
* cuda-gdb
*/
#include <stdio.h>
#define uchar unsigned char
#define NUMBER_OF_THREADS 512
uchar * dev_array1;
uchar * dev_array2;
uint * dev_size_x;
uint * dev_size_y;
uint sizeX,sizeY;
// bad -> fix it
__global__ void kernel2(float * field1, float * field2, uchar4 * screen, int sizex, int sizey)
{
// int id = threadIdx.x + blockIdx.x*blockDim.x + threadIdx.y + blockIdx.y*blockDim.y;
int id = threadIdx.x+threadIdx.y;
int numberofneighbours=0;
numberofneighbours += *(field1 + id + 1);
numberofneighbours += *(field1 + id - 1);
numberofneighbours += *(field1 + id + sizey);
numberofneighbours += *(field1 + id - sizey);
numberofneighbours += *(field1 + id + sizey + 1);
numberofneighbours += *(field1 + id + sizey - 1);
numberofneighbours += *(field1 + id - sizey - 1);
numberofneighbours += *(field1 + id + sizey + 1);
// (screen + id)->x = numberofneighbours;
// (screen + id)->x = 1;
// *(field2 + id) = 1;
// if(*(field1 + id) == 1) *(field2 + id) = 1;
/*
switch(numberofneighbours)
{
case 3 : *(field2 + id) = 1;
(screen + id)->x = 0;
(screen + id)->y = 250;
(screen + id)->z = 0;
(screen + id)->w = 0;
break;
case 2 : if(*(field1 + id) == 1)
{
*(field2 + id) = 1;
(screen + id)->x = 0;
(screen + id)->y = 250;
(screen + id)->z = 0;
(screen + id)->w = 0;
}
else
{
*(field2 + id) = 0;
(screen + id)->x = 0;
(screen + id)->y = 0;
(screen + id)->z = 0;
(screen + id)->w = 0;
}
break;
default : *(field2 + id) = 0;
(screen + id)->x = 0;
(screen + id)->y = 0;
(screen + id)->z = 0;
(screen + id)->w = 0;
break;
}
*/
}
__global__ void kernel(uchar * array1, uchar * array2, uint size_x, uint size_y)
{
// int id = threadIdx.x*blockIdx.x+blockDim.x + threadIdx.y*blockIdx.y+blockDim.y;
int id = threadIdx.x+threadIdx.y;
if(id < size_x*size_y)
{
int numberofneighbours=0;
int num = 0;
// заменить на num += ...
if(*(array1 + id + 1) == 1) num++;
if(*(array1 + id - 1) == 1) num++;
if(*(array1 + id + size_y) == 1) num++;
if(*(array1 + id - size_y) == 1) num++;
if(*(array1 + id + size_y + 1) == 1) num++;
if(*(array1 + id + size_y - 1) == 1) num++;
if(*(array1 + id - size_y + 1) == 1) num++;
if(*(array1 + id - size_y - 1) == 1) num++;
switch(num)
{
case 3 : *(array2 + id) = 1; break;
case 2 : if(*(array1 + id) == 1) *(array2 + id) = 1; break;
default : *(array2 + id) = 0; break;
}
}
}
void initCuda(uchar * array1, uchar * array2, uint size_x, uint size_y)
{
sizeX = size_x;
sizeY = size_y;
cudaMalloc((void**)&dev_array1,sizeof(uchar)*size_x*size_y);
cudaMalloc((void**)&dev_array2,sizeof(uchar)*size_x*size_y);
cudaMalloc((void**)&dev_size_x,sizeof(uint));
cudaMalloc((void**)&dev_size_y,sizeof(uint));
cudaMemcpy(dev_array1,array1,sizeof(uchar)*size_x*size_y,cudaMemcpyHostToDevice);
cudaMemcpy(dev_size_x,&size_x,sizeof(uchar),cudaMemcpyHostToDevice);
cudaMemcpy(dev_size_y,&size_y,sizeof(uchar),cudaMemcpyHostToDevice);
cudaMemset(dev_array2,0,size_x*size_y);
}
void get_result(uchar * array)
{
cudaMemcpy(array,dev_array2,sizeX*sizeY*sizeof(uchar),cudaMemcpyDeviceToHost);
}
void cuda_run()
{
int threads = NUMBER_OF_THREADS;
int blocks = sizeX*sizeY/threads+1;
// kernel <<<blocks,threads>>>(dev_array1,dev_array2,dev_size_x,dev_size_y);
kernel <<<blocks,threads>>>(dev_array1,dev_array2,sizeX,sizeY);
}
void FreeCuda()
{
cudaFree(dev_array1);
cudaFree(dev_array2);
cudaFree(dev_size_x);
cudaFree(dev_size_y);
}
void check(uchar * array1, uchar * array2, uint * size_x, uint * size_y)
{
int num=0;
puts("<=================>\n");
printf("%u %u\n",*size_x,*size_y);
puts("<=================>\n");
for(int i=0;i<(*size_x * (*size_y));i++)
{
num = 0;
if(*(array1 + i + 1) == 1) num++;
if(*(array1 + i - 1) == 1) num++;
if(*(array1 + i + *size_y) == 1) num++;
if(*(array1 + i - *size_y) == 1) num++;
if(*(array1 + i + *size_y + 1) == 1) num++;
if(*(array1 + i + *size_y - 1) == 1) num++;
if(*(array1 + i - *size_y + 1) == 1) num++;
if(*(array1 + i - *size_y - 1) == 1) num++;
// *(array2 + i) = num;
switch(num)
{
case 3 : *(array2 + i) = 1; break;
case 2 : if(*(array1 + i) == 1) *(array2 + i) = 1; break;
default : *(array2 + i) = 0; break;
}
}
puts("<=================>\n");
}
#define cell_size 5
#define uchar unsigned char
#define screen_width 20
#define screen_height 20
int width = screen_width*cell_size; //770; //1024;
int height = screen_width*cell_size; //770; //768;
/*
int main()
{
// uchar field1[screen_width][screen_height];
// uchar field2[screen_width][screen_height];
uchar field1[screen_width*screen_height];
uchar field2[screen_width*screen_height];
for(int i=0;i<screen_width;i++)
{
for(int j=0;j<screen_height;j++)
{
field1[i+j*screen_width] = 0;
field2[i+j*screen_width] = 0;
}
}
field1[0+0*screen_width] = 1;
field1[0+1*screen_width] = 1;
field1[0+2*screen_width] = 1;
// field1[1][0] = 1;
field1[1+1*screen_width] = 1;
field1[3+3*screen_width] = 1;
field1[4+3*screen_width] = 1;
field1[10+5*screen_width] = 1;
field1[10+6*screen_width] = 1;
field1[11+5*screen_width] = 1;
field1[11+6*screen_width] = 1;
// field1[10][7] = 1;
for(int i=0;i<screen_width;i++)
{
for(int j=0;j<screen_height;j++)
{
if(field1[i+j*screen_width] == 1) printf("*");
else printf(".");
// printf("%c ",field1[i][j]);
}
printf("\n");
}
sizeX = 20;
sizeY = 20;
//=======================================================================
/*
check(field1,field2,&sizeX,&sizeY);
for(int i=0;i<screen_width;i++)
{
for(int j=0;j<screen_height;j++)
{
if(field2[i+j*screen_width] == 1) printf("*");
else printf("%i",(int) field2[i+j*screen_width]);
// printf("%c ",field2[i][j]);
}
printf("\n");
}
*/
//=======================================================================
/*
initCuda(&field1[0],&field2[0],screen_width,screen_height);
cuda_run();
get_result(&field2[0]);
puts("\n<==========>\n\n");
for(int i=0;i<screen_width;i++)
{
for(int j=0;j<screen_height;j++)
{
if(field2[i+j*screen_width] == 1) printf("*");
else printf("%i",(int) field2[i+j*screen_width]);
// printf("%c ",field2[i][j]);
}
printf("\n");
}
FreeCuda();
return 0;
}
*/
int main()
{
float * field1;
field1 = (float *) malloc(sizeof(float)*screen_width*screen_height);
uchar4 * screen;
screen = (uchar4 *) malloc(sizeof(uchar4)*screen_width*screen_height);
float * dev_field1;
float * dev_field2;
uchar4 * dev_screen;
*(field1 + 10) = 1;
field1[40] = 1;
field1[41] = 1;
field1[59] = 1;
field1[60] = 1;
field1[90] = 1;
field1[91] = 1;
field1[92] = 1;
for(int i=0;i<=400;i++)
{
printf("%i",(int) *(field1+i));
if(i % 19 == 0) printf("\n");
}
printf("\n");
cudaMalloc((void **)&dev_field1,sizeof(float)*screen_width*screen_height);
cudaMalloc((void **)&dev_field2,sizeof(float)*screen_width*screen_height);
cudaMalloc((void **)&dev_screen,sizeof(uchar4)*screen_width*screen_height);
cudaMemcpy(dev_field1,field1,sizeof(uchar4)*screen_width*screen_height,cudaMemcpyHostToDevice);
cudaMemset(dev_field2,8,sizeof(float)*screen_width*screen_height);
kernel2<<<10 , 10>>>(dev_field1,dev_field2,dev_screen,20,20);
float * field2;
field2 = (float *) malloc(sizeof(float)*screen_width*screen_height);
cudaMemcpy(field2,dev_field2,sizeof(float)*screen_width*screen_height,cudaMemcpyDeviceToHost);
cudaMemcpy(screen,dev_screen,sizeof(uchar4)*screen_width*screen_height,cudaMemcpyDeviceToHost);
cudaFree(dev_field1);
cudaFree(dev_field2);
cudaFree(dev_screen);
for(int i=0;i<400;i++)
{
printf("%i",(int) (screen+i)->x);
if(i % 19 == 0) printf("\n");
}
printf("\n");
for(int i=0;i<400;i++)
{
printf("%4i",(int) *(field2+i));
if(i % 19 == 0) printf("\n");
}
printf("\n");
free(field1);
free(field2);
free(screen);
} | .file "tmpxft_000202b2_00000000-6_life.cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8initCudaPhS_jj
.type _Z8initCudaPhS_jj, @function
_Z8initCudaPhS_jj:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %edx, sizeX(%rip)
movl %ecx, sizeY(%rip)
movl %edx, %esi
movl %ecx, %eax
imulq %rax, %rsi
leaq dev_array1(%rip), %rdi
call cudaMalloc@PLT
movl 12(%rsp), %esi
movl 8(%rsp), %eax
imulq %rax, %rsi
leaq dev_array2(%rip), %rdi
call cudaMalloc@PLT
movl $4, %esi
leaq dev_size_x(%rip), %rdi
call cudaMalloc@PLT
movl $4, %esi
leaq dev_size_y(%rip), %rdi
call cudaMalloc@PLT
movl 12(%rsp), %edx
movl 8(%rsp), %eax
imulq %rax, %rdx
movl $1, %ecx
movq %rbx, %rsi
movq dev_array1(%rip), %rdi
call cudaMemcpy@PLT
leaq 12(%rsp), %rsi
movl $1, %ecx
movl $1, %edx
movq dev_size_x(%rip), %rdi
call cudaMemcpy@PLT
leaq 8(%rsp), %rsi
movl $1, %ecx
movl $1, %edx
movq dev_size_y(%rip), %rdi
call cudaMemcpy@PLT
movl 12(%rsp), %edx
imull 8(%rsp), %edx
movl $0, %esi
movq dev_array2(%rip), %rdi
call cudaMemset@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z8initCudaPhS_jj, .-_Z8initCudaPhS_jj
.globl _Z10get_resultPh
.type _Z10get_resultPh, @function
_Z10get_resultPh:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl sizeX(%rip), %edx
imull sizeY(%rip), %edx
movl $2, %ecx
movq dev_array2(%rip), %rsi
call cudaMemcpy@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z10get_resultPh, .-_Z10get_resultPh
.globl _Z8FreeCudav
.type _Z8FreeCudav, @function
_Z8FreeCudav:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq dev_array1(%rip), %rdi
call cudaFree@PLT
movq dev_array2(%rip), %rdi
call cudaFree@PLT
movq dev_size_x(%rip), %rdi
call cudaFree@PLT
movq dev_size_y(%rip), %rdi
call cudaFree@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z8FreeCudav, .-_Z8FreeCudav
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "<=================>\n"
.LC1:
.string "%u %u\n"
.text
.globl _Z5checkPhS_PjS0_
.type _Z5checkPhS_PjS0_, @function
_Z5checkPhS_PjS0_:
.LFB2061:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %rbx
movq %rsi, %r13
movq %rdx, %rbp
movq %rcx, %r12
leaq .LC0(%rip), %r14
movq %r14, %rdi
call puts@PLT
movl (%r12), %ecx
movl 0(%rbp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r14, %rdi
call puts@PLT
movl (%r12), %ecx
movl %ecx, %eax
imull 0(%rbp), %eax
testl %eax, %eax
je .L10
movl $0, %eax
jmp .L21
.L24:
addl $1, %edx
jmp .L11
.L25:
addl $1, %edx
jmp .L12
.L26:
addl $1, %edx
jmp .L13
.L27:
addl $1, %edx
jmp .L14
.L28:
addl $1, %edx
jmp .L15
.L29:
addl $1, %edx
jmp .L16
.L17:
cmpl $2, %edx
je .L18
cmpl $3, %edx
sete 0(%r13,%rax)
.L20:
movl (%r12), %ecx
addq $1, %rax
movl %ecx, %edx
imull 0(%rbp), %edx
cmpl %edx, %eax
jnb .L10
.L21:
cmpb $1, 1(%rbx,%rax)
sete %dl
movzbl %dl, %edx
cmpb $1, -1(%rbx,%rax)
je .L24
.L11:
movl %ecx, %ecx
leaq (%rcx,%rax), %rdi
cmpb $1, (%rbx,%rdi)
je .L25
.L12:
movq %rax, %rsi
subq %rcx, %rsi
cmpb $1, (%rbx,%rsi)
je .L26
.L13:
cmpb $1, 1(%rbx,%rdi)
je .L27
.L14:
cmpb $1, -1(%rbx,%rdi)
je .L28
.L15:
cmpb $1, 1(%rbx,%rsi)
je .L29
.L16:
cmpb $1, -1(%rbx,%rsi)
jne .L17
addl $1, %edx
jmp .L17
.L18:
cmpb $1, (%rbx,%rax)
jne .L20
movb $1, 0(%r13,%rax)
jmp .L20
.L10:
leaq .LC0(%rip), %rdi
call puts@PLT
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z5checkPhS_PjS0_, .-_Z5checkPhS_PjS0_
.globl _Z38__device_stub__Z7kernel2PfS_P6uchar4iiPfS_P6uchar4ii
.type _Z38__device_stub__Z7kernel2PfS_P6uchar4iiPfS_P6uchar4ii, @function
_Z38__device_stub__Z7kernel2PfS_P6uchar4iiPfS_P6uchar4ii:
.LFB2087:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L34
.L30:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L35
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7kernel2PfS_P6uchar4ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L30
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z38__device_stub__Z7kernel2PfS_P6uchar4iiPfS_P6uchar4ii, .-_Z38__device_stub__Z7kernel2PfS_P6uchar4iiPfS_P6uchar4ii
.globl _Z7kernel2PfS_P6uchar4ii
.type _Z7kernel2PfS_P6uchar4ii, @function
_Z7kernel2PfS_P6uchar4ii:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z7kernel2PfS_P6uchar4iiPfS_P6uchar4ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z7kernel2PfS_P6uchar4ii, .-_Z7kernel2PfS_P6uchar4ii
.section .rodata.str1.1
.LC3:
.string "%i"
.LC4:
.string "\n"
.LC5:
.string "%4i"
.text
.globl main
.type main, @function
main:
.LFB2062:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $1600, %edi
call malloc@PLT
movq %rax, %rbp
movl $1600, %edi
call malloc@PLT
movq %rax, %r12
movss .LC2(%rip), %xmm0
movss %xmm0, 40(%rbp)
movss %xmm0, 160(%rbp)
movss %xmm0, 164(%rbp)
movss %xmm0, 236(%rbp)
movss %xmm0, 240(%rbp)
movss %xmm0, 360(%rbp)
movss %xmm0, 364(%rbp)
movss %xmm0, 368(%rbp)
movl $0, %ebx
leaq .LC3(%rip), %r13
leaq .LC4(%rip), %r14
jmp .L40
.L39:
addq $1, %rbx
cmpq $401, %rbx
je .L51
.L40:
cvttss2sil 0(%rbp,%rbx,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %ebx, %rax
imulq $1808407283, %rax, %rax
sarq $35, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,8), %edx
leal (%rax,%rdx,2), %eax
cmpl %ebx, %eax
jne .L39
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L39
.L51:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 8(%rsp), %rdi
movl $1600, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $1600, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $1600, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $1600, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1600, %edx
movl $8, %esi
movq 16(%rsp), %rdi
call cudaMemset@PLT
movl $10, 44(%rsp)
movl $1, 48(%rsp)
movl $10, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L41:
movl $1600, %edi
call malloc@PLT
movq %rax, %r13
movl $2, %ecx
movl $1600, %edx
movq 16(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $1600, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movl $0, %ebx
leaq .LC3(%rip), %r14
leaq .LC4(%rip), %r15
jmp .L43
.L52:
movl $20, %r8d
movl $20, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z38__device_stub__Z7kernel2PfS_P6uchar4iiPfS_P6uchar4ii
jmp .L41
.L42:
addq $1, %rbx
cmpq $400, %rbx
je .L53
.L43:
movzbl (%r12,%rbx,4), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %ebx, %rax
imulq $1808407283, %rax, %rax
sarq $35, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,8), %edx
leal (%rax,%rdx,2), %eax
cmpl %ebx, %eax
jne .L42
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L42
.L53:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC5(%rip), %r14
leaq .LC4(%rip), %r15
jmp .L45
.L44:
addq $1, %rbx
cmpq $400, %rbx
je .L54
.L45:
cvttss2sil 0(%r13,%rbx,4), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %ebx, %rax
imulq $1808407283, %rax, %rax
sarq $35, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,8), %edx
leal (%rax,%rdx,2), %eax
cmpl %ebx, %eax
jne .L44
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L44
.L54:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L55
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size main, .-main
.globl _Z29__device_stub__Z6kernelPhS_jjPhS_jj
.type _Z29__device_stub__Z6kernelPhS_jjPhS_jj, @function
_Z29__device_stub__Z6kernelPhS_jjPhS_jj:
.LFB2089:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L60
.L56:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L61
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L60:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6kernelPhS_jj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L56
.L61:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z29__device_stub__Z6kernelPhS_jjPhS_jj, .-_Z29__device_stub__Z6kernelPhS_jjPhS_jj
.globl _Z6kernelPhS_jj
.type _Z6kernelPhS_jj, @function
_Z6kernelPhS_jj:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6kernelPhS_jjPhS_jj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z6kernelPhS_jj, .-_Z6kernelPhS_jj
.globl _Z8cuda_runv
.type _Z8cuda_runv, @function
_Z8cuda_runv:
.LFB2059:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl sizeX(%rip), %eax
imull sizeY(%rip), %eax
shrl $9, %eax
addl $1, %eax
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L67
.L64:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L67:
.cfi_restore_state
movl sizeY(%rip), %ecx
movl sizeX(%rip), %edx
movq dev_array2(%rip), %rsi
movq dev_array1(%rip), %rdi
call _Z29__device_stub__Z6kernelPhS_jjPhS_jj
jmp .L64
.cfi_endproc
.LFE2059:
.size _Z8cuda_runv, .-_Z8cuda_runv
.section .rodata.str1.1
.LC6:
.string "_Z6kernelPhS_jj"
.LC7:
.string "_Z7kernel2PfS_P6uchar4ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2092:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPhS_jj(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kernel2PfS_P6uchar4ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl height
.data
.align 4
.type height, @object
.size height, 4
height:
.long 100
.globl width
.align 4
.type width, @object
.size width, 4
width:
.long 100
.globl sizeY
.bss
.align 4
.type sizeY, @object
.size sizeY, 4
sizeY:
.zero 4
.globl sizeX
.align 4
.type sizeX, @object
.size sizeX, 4
sizeX:
.zero 4
.globl dev_size_y
.align 8
.type dev_size_y, @object
.size dev_size_y, 8
dev_size_y:
.zero 8
.globl dev_size_x
.align 8
.type dev_size_x, @object
.size dev_size_x, 8
dev_size_x:
.zero 8
.globl dev_array2
.align 8
.type dev_array2, @object
.size dev_array2, 8
dev_array2:
.zero 8
.globl dev_array1
.align 8
.type dev_array1, @object
.size dev_array1, 8
dev_array1:
.zero 8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
*
* compiling:
* nvcc -lglut -LGLEW life.cuda.cu -o life
*
* for it's work:
* export LD_LIBRARY_PATH=:/usr/local/cuda/lib
* export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/usr/local/cuda/libnvvp/
*
* cuda-gdb
*/
#include <stdio.h>
#define uchar unsigned char
#define NUMBER_OF_THREADS 512
uchar * dev_array1;
uchar * dev_array2;
uint * dev_size_x;
uint * dev_size_y;
uint sizeX,sizeY;
// bad -> fix it
__global__ void kernel2(float * field1, float * field2, uchar4 * screen, int sizex, int sizey)
{
// int id = threadIdx.x + blockIdx.x*blockDim.x + threadIdx.y + blockIdx.y*blockDim.y;
int id = threadIdx.x+threadIdx.y;
int numberofneighbours=0;
numberofneighbours += *(field1 + id + 1);
numberofneighbours += *(field1 + id - 1);
numberofneighbours += *(field1 + id + sizey);
numberofneighbours += *(field1 + id - sizey);
numberofneighbours += *(field1 + id + sizey + 1);
numberofneighbours += *(field1 + id + sizey - 1);
numberofneighbours += *(field1 + id - sizey - 1);
numberofneighbours += *(field1 + id + sizey + 1);
// (screen + id)->x = numberofneighbours;
// (screen + id)->x = 1;
// *(field2 + id) = 1;
// if(*(field1 + id) == 1) *(field2 + id) = 1;
/*
switch(numberofneighbours)
{
case 3 : *(field2 + id) = 1;
(screen + id)->x = 0;
(screen + id)->y = 250;
(screen + id)->z = 0;
(screen + id)->w = 0;
break;
case 2 : if(*(field1 + id) == 1)
{
*(field2 + id) = 1;
(screen + id)->x = 0;
(screen + id)->y = 250;
(screen + id)->z = 0;
(screen + id)->w = 0;
}
else
{
*(field2 + id) = 0;
(screen + id)->x = 0;
(screen + id)->y = 0;
(screen + id)->z = 0;
(screen + id)->w = 0;
}
break;
default : *(field2 + id) = 0;
(screen + id)->x = 0;
(screen + id)->y = 0;
(screen + id)->z = 0;
(screen + id)->w = 0;
break;
}
*/
}
__global__ void kernel(uchar * array1, uchar * array2, uint size_x, uint size_y)
{
// int id = threadIdx.x*blockIdx.x+blockDim.x + threadIdx.y*blockIdx.y+blockDim.y;
int id = threadIdx.x+threadIdx.y;
if(id < size_x*size_y)
{
int numberofneighbours=0;
int num = 0;
// заменить на num += ...
if(*(array1 + id + 1) == 1) num++;
if(*(array1 + id - 1) == 1) num++;
if(*(array1 + id + size_y) == 1) num++;
if(*(array1 + id - size_y) == 1) num++;
if(*(array1 + id + size_y + 1) == 1) num++;
if(*(array1 + id + size_y - 1) == 1) num++;
if(*(array1 + id - size_y + 1) == 1) num++;
if(*(array1 + id - size_y - 1) == 1) num++;
switch(num)
{
case 3 : *(array2 + id) = 1; break;
case 2 : if(*(array1 + id) == 1) *(array2 + id) = 1; break;
default : *(array2 + id) = 0; break;
}
}
}
void initCuda(uchar * array1, uchar * array2, uint size_x, uint size_y)
{
sizeX = size_x;
sizeY = size_y;
cudaMalloc((void**)&dev_array1,sizeof(uchar)*size_x*size_y);
cudaMalloc((void**)&dev_array2,sizeof(uchar)*size_x*size_y);
cudaMalloc((void**)&dev_size_x,sizeof(uint));
cudaMalloc((void**)&dev_size_y,sizeof(uint));
cudaMemcpy(dev_array1,array1,sizeof(uchar)*size_x*size_y,cudaMemcpyHostToDevice);
cudaMemcpy(dev_size_x,&size_x,sizeof(uchar),cudaMemcpyHostToDevice);
cudaMemcpy(dev_size_y,&size_y,sizeof(uchar),cudaMemcpyHostToDevice);
cudaMemset(dev_array2,0,size_x*size_y);
}
void get_result(uchar * array)
{
cudaMemcpy(array,dev_array2,sizeX*sizeY*sizeof(uchar),cudaMemcpyDeviceToHost);
}
void cuda_run()
{
int threads = NUMBER_OF_THREADS;
int blocks = sizeX*sizeY/threads+1;
// kernel <<<blocks,threads>>>(dev_array1,dev_array2,dev_size_x,dev_size_y);
kernel <<<blocks,threads>>>(dev_array1,dev_array2,sizeX,sizeY);
}
void FreeCuda()
{
cudaFree(dev_array1);
cudaFree(dev_array2);
cudaFree(dev_size_x);
cudaFree(dev_size_y);
}
void check(uchar * array1, uchar * array2, uint * size_x, uint * size_y)
{
int num=0;
puts("<=================>\n");
printf("%u %u\n",*size_x,*size_y);
puts("<=================>\n");
for(int i=0;i<(*size_x * (*size_y));i++)
{
num = 0;
if(*(array1 + i + 1) == 1) num++;
if(*(array1 + i - 1) == 1) num++;
if(*(array1 + i + *size_y) == 1) num++;
if(*(array1 + i - *size_y) == 1) num++;
if(*(array1 + i + *size_y + 1) == 1) num++;
if(*(array1 + i + *size_y - 1) == 1) num++;
if(*(array1 + i - *size_y + 1) == 1) num++;
if(*(array1 + i - *size_y - 1) == 1) num++;
// *(array2 + i) = num;
switch(num)
{
case 3 : *(array2 + i) = 1; break;
case 2 : if(*(array1 + i) == 1) *(array2 + i) = 1; break;
default : *(array2 + i) = 0; break;
}
}
puts("<=================>\n");
}
#define cell_size 5
#define uchar unsigned char
#define screen_width 20
#define screen_height 20
int width = screen_width*cell_size; //770; //1024;
int height = screen_width*cell_size; //770; //768;
/*
int main()
{
// uchar field1[screen_width][screen_height];
// uchar field2[screen_width][screen_height];
uchar field1[screen_width*screen_height];
uchar field2[screen_width*screen_height];
for(int i=0;i<screen_width;i++)
{
for(int j=0;j<screen_height;j++)
{
field1[i+j*screen_width] = 0;
field2[i+j*screen_width] = 0;
}
}
field1[0+0*screen_width] = 1;
field1[0+1*screen_width] = 1;
field1[0+2*screen_width] = 1;
// field1[1][0] = 1;
field1[1+1*screen_width] = 1;
field1[3+3*screen_width] = 1;
field1[4+3*screen_width] = 1;
field1[10+5*screen_width] = 1;
field1[10+6*screen_width] = 1;
field1[11+5*screen_width] = 1;
field1[11+6*screen_width] = 1;
// field1[10][7] = 1;
for(int i=0;i<screen_width;i++)
{
for(int j=0;j<screen_height;j++)
{
if(field1[i+j*screen_width] == 1) printf("*");
else printf(".");
// printf("%c ",field1[i][j]);
}
printf("\n");
}
sizeX = 20;
sizeY = 20;
//=======================================================================
/*
check(field1,field2,&sizeX,&sizeY);
for(int i=0;i<screen_width;i++)
{
for(int j=0;j<screen_height;j++)
{
if(field2[i+j*screen_width] == 1) printf("*");
else printf("%i",(int) field2[i+j*screen_width]);
// printf("%c ",field2[i][j]);
}
printf("\n");
}
*/
//=======================================================================
/*
initCuda(&field1[0],&field2[0],screen_width,screen_height);
cuda_run();
get_result(&field2[0]);
puts("\n<==========>\n\n");
for(int i=0;i<screen_width;i++)
{
for(int j=0;j<screen_height;j++)
{
if(field2[i+j*screen_width] == 1) printf("*");
else printf("%i",(int) field2[i+j*screen_width]);
// printf("%c ",field2[i][j]);
}
printf("\n");
}
FreeCuda();
return 0;
}
*/
int main()
{
float * field1;
field1 = (float *) malloc(sizeof(float)*screen_width*screen_height);
uchar4 * screen;
screen = (uchar4 *) malloc(sizeof(uchar4)*screen_width*screen_height);
float * dev_field1;
float * dev_field2;
uchar4 * dev_screen;
*(field1 + 10) = 1;
field1[40] = 1;
field1[41] = 1;
field1[59] = 1;
field1[60] = 1;
field1[90] = 1;
field1[91] = 1;
field1[92] = 1;
for(int i=0;i<=400;i++)
{
printf("%i",(int) *(field1+i));
if(i % 19 == 0) printf("\n");
}
printf("\n");
cudaMalloc((void **)&dev_field1,sizeof(float)*screen_width*screen_height);
cudaMalloc((void **)&dev_field2,sizeof(float)*screen_width*screen_height);
cudaMalloc((void **)&dev_screen,sizeof(uchar4)*screen_width*screen_height);
cudaMemcpy(dev_field1,field1,sizeof(uchar4)*screen_width*screen_height,cudaMemcpyHostToDevice);
cudaMemset(dev_field2,8,sizeof(float)*screen_width*screen_height);
kernel2<<<10 , 10>>>(dev_field1,dev_field2,dev_screen,20,20);
float * field2;
field2 = (float *) malloc(sizeof(float)*screen_width*screen_height);
cudaMemcpy(field2,dev_field2,sizeof(float)*screen_width*screen_height,cudaMemcpyDeviceToHost);
cudaMemcpy(screen,dev_screen,sizeof(uchar4)*screen_width*screen_height,cudaMemcpyDeviceToHost);
cudaFree(dev_field1);
cudaFree(dev_field2);
cudaFree(dev_screen);
for(int i=0;i<400;i++)
{
printf("%i",(int) (screen+i)->x);
if(i % 19 == 0) printf("\n");
}
printf("\n");
for(int i=0;i<400;i++)
{
printf("%4i",(int) *(field2+i));
if(i % 19 == 0) printf("\n");
}
printf("\n");
free(field1);
free(field2);
free(screen);
} | /*
*
* compiling:
* nvcc -lglut -LGLEW life.cuda.cu -o life
*
* for it's work:
* export LD_LIBRARY_PATH=:/usr/local/cuda/lib
* export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/usr/local/cuda/libnvvp/
*
* cuda-gdb
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#define uchar unsigned char
#define NUMBER_OF_THREADS 512
uchar * dev_array1;
uchar * dev_array2;
uint * dev_size_x;
uint * dev_size_y;
uint sizeX,sizeY;
// bad -> fix it
__global__ void kernel2(float * field1, float * field2, uchar4 * screen, int sizex, int sizey)
{
// int id = threadIdx.x + blockIdx.x*blockDim.x + threadIdx.y + blockIdx.y*blockDim.y;
int id = threadIdx.x+threadIdx.y;
int numberofneighbours=0;
numberofneighbours += *(field1 + id + 1);
numberofneighbours += *(field1 + id - 1);
numberofneighbours += *(field1 + id + sizey);
numberofneighbours += *(field1 + id - sizey);
numberofneighbours += *(field1 + id + sizey + 1);
numberofneighbours += *(field1 + id + sizey - 1);
numberofneighbours += *(field1 + id - sizey - 1);
numberofneighbours += *(field1 + id + sizey + 1);
// (screen + id)->x = numberofneighbours;
// (screen + id)->x = 1;
// *(field2 + id) = 1;
// if(*(field1 + id) == 1) *(field2 + id) = 1;
/*
switch(numberofneighbours)
{
case 3 : *(field2 + id) = 1;
(screen + id)->x = 0;
(screen + id)->y = 250;
(screen + id)->z = 0;
(screen + id)->w = 0;
break;
case 2 : if(*(field1 + id) == 1)
{
*(field2 + id) = 1;
(screen + id)->x = 0;
(screen + id)->y = 250;
(screen + id)->z = 0;
(screen + id)->w = 0;
}
else
{
*(field2 + id) = 0;
(screen + id)->x = 0;
(screen + id)->y = 0;
(screen + id)->z = 0;
(screen + id)->w = 0;
}
break;
default : *(field2 + id) = 0;
(screen + id)->x = 0;
(screen + id)->y = 0;
(screen + id)->z = 0;
(screen + id)->w = 0;
break;
}
*/
}
__global__ void kernel(uchar * array1, uchar * array2, uint size_x, uint size_y)
{
// int id = threadIdx.x*blockIdx.x+blockDim.x + threadIdx.y*blockIdx.y+blockDim.y;
int id = threadIdx.x+threadIdx.y;
if(id < size_x*size_y)
{
int numberofneighbours=0;
int num = 0;
// заменить на num += ...
if(*(array1 + id + 1) == 1) num++;
if(*(array1 + id - 1) == 1) num++;
if(*(array1 + id + size_y) == 1) num++;
if(*(array1 + id - size_y) == 1) num++;
if(*(array1 + id + size_y + 1) == 1) num++;
if(*(array1 + id + size_y - 1) == 1) num++;
if(*(array1 + id - size_y + 1) == 1) num++;
if(*(array1 + id - size_y - 1) == 1) num++;
switch(num)
{
case 3 : *(array2 + id) = 1; break;
case 2 : if(*(array1 + id) == 1) *(array2 + id) = 1; break;
default : *(array2 + id) = 0; break;
}
}
}
void initCuda(uchar * array1, uchar * array2, uint size_x, uint size_y)
{
sizeX = size_x;
sizeY = size_y;
hipMalloc((void**)&dev_array1,sizeof(uchar)*size_x*size_y);
hipMalloc((void**)&dev_array2,sizeof(uchar)*size_x*size_y);
hipMalloc((void**)&dev_size_x,sizeof(uint));
hipMalloc((void**)&dev_size_y,sizeof(uint));
hipMemcpy(dev_array1,array1,sizeof(uchar)*size_x*size_y,hipMemcpyHostToDevice);
hipMemcpy(dev_size_x,&size_x,sizeof(uchar),hipMemcpyHostToDevice);
hipMemcpy(dev_size_y,&size_y,sizeof(uchar),hipMemcpyHostToDevice);
hipMemset(dev_array2,0,size_x*size_y);
}
void get_result(uchar * array)
{
hipMemcpy(array,dev_array2,sizeX*sizeY*sizeof(uchar),hipMemcpyDeviceToHost);
}
void cuda_run()
{
int threads = NUMBER_OF_THREADS;
int blocks = sizeX*sizeY/threads+1;
// kernel <<<blocks,threads>>>(dev_array1,dev_array2,dev_size_x,dev_size_y);
kernel <<<blocks,threads>>>(dev_array1,dev_array2,sizeX,sizeY);
}
void FreeCuda()
{
hipFree(dev_array1);
hipFree(dev_array2);
hipFree(dev_size_x);
hipFree(dev_size_y);
}
void check(uchar * array1, uchar * array2, uint * size_x, uint * size_y)
{
int num=0;
puts("<=================>\n");
printf("%u %u\n",*size_x,*size_y);
puts("<=================>\n");
for(int i=0;i<(*size_x * (*size_y));i++)
{
num = 0;
if(*(array1 + i + 1) == 1) num++;
if(*(array1 + i - 1) == 1) num++;
if(*(array1 + i + *size_y) == 1) num++;
if(*(array1 + i - *size_y) == 1) num++;
if(*(array1 + i + *size_y + 1) == 1) num++;
if(*(array1 + i + *size_y - 1) == 1) num++;
if(*(array1 + i - *size_y + 1) == 1) num++;
if(*(array1 + i - *size_y - 1) == 1) num++;
// *(array2 + i) = num;
switch(num)
{
case 3 : *(array2 + i) = 1; break;
case 2 : if(*(array1 + i) == 1) *(array2 + i) = 1; break;
default : *(array2 + i) = 0; break;
}
}
puts("<=================>\n");
}
#define cell_size 5
#define uchar unsigned char
#define screen_width 20
#define screen_height 20
int width = screen_width*cell_size; //770; //1024;
int height = screen_width*cell_size; //770; //768;
/*
int main()
{
// uchar field1[screen_width][screen_height];
// uchar field2[screen_width][screen_height];
uchar field1[screen_width*screen_height];
uchar field2[screen_width*screen_height];
for(int i=0;i<screen_width;i++)
{
for(int j=0;j<screen_height;j++)
{
field1[i+j*screen_width] = 0;
field2[i+j*screen_width] = 0;
}
}
field1[0+0*screen_width] = 1;
field1[0+1*screen_width] = 1;
field1[0+2*screen_width] = 1;
// field1[1][0] = 1;
field1[1+1*screen_width] = 1;
field1[3+3*screen_width] = 1;
field1[4+3*screen_width] = 1;
field1[10+5*screen_width] = 1;
field1[10+6*screen_width] = 1;
field1[11+5*screen_width] = 1;
field1[11+6*screen_width] = 1;
// field1[10][7] = 1;
for(int i=0;i<screen_width;i++)
{
for(int j=0;j<screen_height;j++)
{
if(field1[i+j*screen_width] == 1) printf("*");
else printf(".");
// printf("%c ",field1[i][j]);
}
printf("\n");
}
sizeX = 20;
sizeY = 20;
//=======================================================================
/*
check(field1,field2,&sizeX,&sizeY);
for(int i=0;i<screen_width;i++)
{
for(int j=0;j<screen_height;j++)
{
if(field2[i+j*screen_width] == 1) printf("*");
else printf("%i",(int) field2[i+j*screen_width]);
// printf("%c ",field2[i][j]);
}
printf("\n");
}
*/
//=======================================================================
/*
initCuda(&field1[0],&field2[0],screen_width,screen_height);
cuda_run();
get_result(&field2[0]);
puts("\n<==========>\n\n");
for(int i=0;i<screen_width;i++)
{
for(int j=0;j<screen_height;j++)
{
if(field2[i+j*screen_width] == 1) printf("*");
else printf("%i",(int) field2[i+j*screen_width]);
// printf("%c ",field2[i][j]);
}
printf("\n");
}
FreeCuda();
return 0;
}
*/
int main()
{
float * field1;
field1 = (float *) malloc(sizeof(float)*screen_width*screen_height);
uchar4 * screen;
screen = (uchar4 *) malloc(sizeof(uchar4)*screen_width*screen_height);
float * dev_field1;
float * dev_field2;
uchar4 * dev_screen;
*(field1 + 10) = 1;
field1[40] = 1;
field1[41] = 1;
field1[59] = 1;
field1[60] = 1;
field1[90] = 1;
field1[91] = 1;
field1[92] = 1;
for(int i=0;i<=400;i++)
{
printf("%i",(int) *(field1+i));
if(i % 19 == 0) printf("\n");
}
printf("\n");
hipMalloc((void **)&dev_field1,sizeof(float)*screen_width*screen_height);
hipMalloc((void **)&dev_field2,sizeof(float)*screen_width*screen_height);
hipMalloc((void **)&dev_screen,sizeof(uchar4)*screen_width*screen_height);
hipMemcpy(dev_field1,field1,sizeof(uchar4)*screen_width*screen_height,hipMemcpyHostToDevice);
hipMemset(dev_field2,8,sizeof(float)*screen_width*screen_height);
kernel2<<<10 , 10>>>(dev_field1,dev_field2,dev_screen,20,20);
float * field2;
field2 = (float *) malloc(sizeof(float)*screen_width*screen_height);
hipMemcpy(field2,dev_field2,sizeof(float)*screen_width*screen_height,hipMemcpyDeviceToHost);
hipMemcpy(screen,dev_screen,sizeof(uchar4)*screen_width*screen_height,hipMemcpyDeviceToHost);
hipFree(dev_field1);
hipFree(dev_field2);
hipFree(dev_screen);
for(int i=0;i<400;i++)
{
printf("%i",(int) (screen+i)->x);
if(i % 19 == 0) printf("\n");
}
printf("\n");
for(int i=0;i<400;i++)
{
printf("%4i",(int) *(field2+i));
if(i % 19 == 0) printf("\n");
}
printf("\n");
free(field1);
free(field2);
free(screen);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
*
* compiling:
* nvcc -lglut -LGLEW life.cuda.cu -o life
*
* for it's work:
* export LD_LIBRARY_PATH=:/usr/local/cuda/lib
* export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/usr/local/cuda/libnvvp/
*
* cuda-gdb
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#define uchar unsigned char
#define NUMBER_OF_THREADS 512
uchar * dev_array1;
uchar * dev_array2;
uint * dev_size_x;
uint * dev_size_y;
uint sizeX,sizeY;
// bad -> fix it
__global__ void kernel2(float * field1, float * field2, uchar4 * screen, int sizex, int sizey)
{
// int id = threadIdx.x + blockIdx.x*blockDim.x + threadIdx.y + blockIdx.y*blockDim.y;
int id = threadIdx.x+threadIdx.y;
int numberofneighbours=0;
numberofneighbours += *(field1 + id + 1);
numberofneighbours += *(field1 + id - 1);
numberofneighbours += *(field1 + id + sizey);
numberofneighbours += *(field1 + id - sizey);
numberofneighbours += *(field1 + id + sizey + 1);
numberofneighbours += *(field1 + id + sizey - 1);
numberofneighbours += *(field1 + id - sizey - 1);
numberofneighbours += *(field1 + id + sizey + 1);
// (screen + id)->x = numberofneighbours;
// (screen + id)->x = 1;
// *(field2 + id) = 1;
// if(*(field1 + id) == 1) *(field2 + id) = 1;
/*
switch(numberofneighbours)
{
case 3 : *(field2 + id) = 1;
(screen + id)->x = 0;
(screen + id)->y = 250;
(screen + id)->z = 0;
(screen + id)->w = 0;
break;
case 2 : if(*(field1 + id) == 1)
{
*(field2 + id) = 1;
(screen + id)->x = 0;
(screen + id)->y = 250;
(screen + id)->z = 0;
(screen + id)->w = 0;
}
else
{
*(field2 + id) = 0;
(screen + id)->x = 0;
(screen + id)->y = 0;
(screen + id)->z = 0;
(screen + id)->w = 0;
}
break;
default : *(field2 + id) = 0;
(screen + id)->x = 0;
(screen + id)->y = 0;
(screen + id)->z = 0;
(screen + id)->w = 0;
break;
}
*/
}
__global__ void kernel(uchar * array1, uchar * array2, uint size_x, uint size_y)
{
// int id = threadIdx.x*blockIdx.x+blockDim.x + threadIdx.y*blockIdx.y+blockDim.y;
int id = threadIdx.x+threadIdx.y;
if(id < size_x*size_y)
{
int numberofneighbours=0;
int num = 0;
// заменить на num += ...
if(*(array1 + id + 1) == 1) num++;
if(*(array1 + id - 1) == 1) num++;
if(*(array1 + id + size_y) == 1) num++;
if(*(array1 + id - size_y) == 1) num++;
if(*(array1 + id + size_y + 1) == 1) num++;
if(*(array1 + id + size_y - 1) == 1) num++;
if(*(array1 + id - size_y + 1) == 1) num++;
if(*(array1 + id - size_y - 1) == 1) num++;
switch(num)
{
case 3 : *(array2 + id) = 1; break;
case 2 : if(*(array1 + id) == 1) *(array2 + id) = 1; break;
default : *(array2 + id) = 0; break;
}
}
}
void initCuda(uchar * array1, uchar * array2, uint size_x, uint size_y)
{
sizeX = size_x;
sizeY = size_y;
hipMalloc((void**)&dev_array1,sizeof(uchar)*size_x*size_y);
hipMalloc((void**)&dev_array2,sizeof(uchar)*size_x*size_y);
hipMalloc((void**)&dev_size_x,sizeof(uint));
hipMalloc((void**)&dev_size_y,sizeof(uint));
hipMemcpy(dev_array1,array1,sizeof(uchar)*size_x*size_y,hipMemcpyHostToDevice);
hipMemcpy(dev_size_x,&size_x,sizeof(uchar),hipMemcpyHostToDevice);
hipMemcpy(dev_size_y,&size_y,sizeof(uchar),hipMemcpyHostToDevice);
hipMemset(dev_array2,0,size_x*size_y);
}
void get_result(uchar * array)
{
hipMemcpy(array,dev_array2,sizeX*sizeY*sizeof(uchar),hipMemcpyDeviceToHost);
}
void cuda_run()
{
int threads = NUMBER_OF_THREADS;
int blocks = sizeX*sizeY/threads+1;
// kernel <<<blocks,threads>>>(dev_array1,dev_array2,dev_size_x,dev_size_y);
kernel <<<blocks,threads>>>(dev_array1,dev_array2,sizeX,sizeY);
}
void FreeCuda()
{
hipFree(dev_array1);
hipFree(dev_array2);
hipFree(dev_size_x);
hipFree(dev_size_y);
}
void check(uchar * array1, uchar * array2, uint * size_x, uint * size_y)
{
int num=0;
puts("<=================>\n");
printf("%u %u\n",*size_x,*size_y);
puts("<=================>\n");
for(int i=0;i<(*size_x * (*size_y));i++)
{
num = 0;
if(*(array1 + i + 1) == 1) num++;
if(*(array1 + i - 1) == 1) num++;
if(*(array1 + i + *size_y) == 1) num++;
if(*(array1 + i - *size_y) == 1) num++;
if(*(array1 + i + *size_y + 1) == 1) num++;
if(*(array1 + i + *size_y - 1) == 1) num++;
if(*(array1 + i - *size_y + 1) == 1) num++;
if(*(array1 + i - *size_y - 1) == 1) num++;
// *(array2 + i) = num;
switch(num)
{
case 3 : *(array2 + i) = 1; break;
case 2 : if(*(array1 + i) == 1) *(array2 + i) = 1; break;
default : *(array2 + i) = 0; break;
}
}
puts("<=================>\n");
}
#define cell_size 5
#define uchar unsigned char
#define screen_width 20
#define screen_height 20
int width = screen_width*cell_size; //770; //1024;
int height = screen_width*cell_size; //770; //768;
/*
int main()
{
// uchar field1[screen_width][screen_height];
// uchar field2[screen_width][screen_height];
uchar field1[screen_width*screen_height];
uchar field2[screen_width*screen_height];
for(int i=0;i<screen_width;i++)
{
for(int j=0;j<screen_height;j++)
{
field1[i+j*screen_width] = 0;
field2[i+j*screen_width] = 0;
}
}
field1[0+0*screen_width] = 1;
field1[0+1*screen_width] = 1;
field1[0+2*screen_width] = 1;
// field1[1][0] = 1;
field1[1+1*screen_width] = 1;
field1[3+3*screen_width] = 1;
field1[4+3*screen_width] = 1;
field1[10+5*screen_width] = 1;
field1[10+6*screen_width] = 1;
field1[11+5*screen_width] = 1;
field1[11+6*screen_width] = 1;
// field1[10][7] = 1;
for(int i=0;i<screen_width;i++)
{
for(int j=0;j<screen_height;j++)
{
if(field1[i+j*screen_width] == 1) printf("*");
else printf(".");
// printf("%c ",field1[i][j]);
}
printf("\n");
}
sizeX = 20;
sizeY = 20;
//=======================================================================
/*
check(field1,field2,&sizeX,&sizeY);
for(int i=0;i<screen_width;i++)
{
for(int j=0;j<screen_height;j++)
{
if(field2[i+j*screen_width] == 1) printf("*");
else printf("%i",(int) field2[i+j*screen_width]);
// printf("%c ",field2[i][j]);
}
printf("\n");
}
*/
//=======================================================================
/*
initCuda(&field1[0],&field2[0],screen_width,screen_height);
cuda_run();
get_result(&field2[0]);
puts("\n<==========>\n\n");
for(int i=0;i<screen_width;i++)
{
for(int j=0;j<screen_height;j++)
{
if(field2[i+j*screen_width] == 1) printf("*");
else printf("%i",(int) field2[i+j*screen_width]);
// printf("%c ",field2[i][j]);
}
printf("\n");
}
FreeCuda();
return 0;
}
*/
int main()
{
float * field1;
field1 = (float *) malloc(sizeof(float)*screen_width*screen_height);
uchar4 * screen;
screen = (uchar4 *) malloc(sizeof(uchar4)*screen_width*screen_height);
float * dev_field1;
float * dev_field2;
uchar4 * dev_screen;
*(field1 + 10) = 1;
field1[40] = 1;
field1[41] = 1;
field1[59] = 1;
field1[60] = 1;
field1[90] = 1;
field1[91] = 1;
field1[92] = 1;
for(int i=0;i<=400;i++)
{
printf("%i",(int) *(field1+i));
if(i % 19 == 0) printf("\n");
}
printf("\n");
hipMalloc((void **)&dev_field1,sizeof(float)*screen_width*screen_height);
hipMalloc((void **)&dev_field2,sizeof(float)*screen_width*screen_height);
hipMalloc((void **)&dev_screen,sizeof(uchar4)*screen_width*screen_height);
hipMemcpy(dev_field1,field1,sizeof(uchar4)*screen_width*screen_height,hipMemcpyHostToDevice);
hipMemset(dev_field2,8,sizeof(float)*screen_width*screen_height);
kernel2<<<10 , 10>>>(dev_field1,dev_field2,dev_screen,20,20);
float * field2;
field2 = (float *) malloc(sizeof(float)*screen_width*screen_height);
hipMemcpy(field2,dev_field2,sizeof(float)*screen_width*screen_height,hipMemcpyDeviceToHost);
hipMemcpy(screen,dev_screen,sizeof(uchar4)*screen_width*screen_height,hipMemcpyDeviceToHost);
hipFree(dev_field1);
hipFree(dev_field2);
hipFree(dev_screen);
for(int i=0;i<400;i++)
{
printf("%i",(int) (screen+i)->x);
if(i % 19 == 0) printf("\n");
}
printf("\n");
for(int i=0;i<400;i++)
{
printf("%4i",(int) *(field2+i));
if(i % 19 == 0) printf("\n");
}
printf("\n");
free(field1);
free(field2);
free(screen);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7kernel2PfS_P15HIP_vector_typeIhLj4EEii
.globl _Z7kernel2PfS_P15HIP_vector_typeIhLj4EEii
.p2align 8
.type _Z7kernel2PfS_P15HIP_vector_typeIhLj4EEii,@function
_Z7kernel2PfS_P15HIP_vector_typeIhLj4EEii:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7kernel2PfS_P15HIP_vector_typeIhLj4EEii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7kernel2PfS_P15HIP_vector_typeIhLj4EEii, .Lfunc_end0-_Z7kernel2PfS_P15HIP_vector_typeIhLj4EEii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z6kernelPhS_jj
.globl _Z6kernelPhS_jj
.p2align 8
.type _Z6kernelPhS_jj,@function
_Z6kernelPhS_jj:
s_load_b64 s[2:3], s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v2, v1, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s3, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s2, v2
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_11
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_u8 v7, v2, s[4:5] offset:1
global_load_u8 v8, v2, s[4:5] offset:-1
v_add_co_u32 v0, s2, s4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e64 v1, null, s5, 0, s2
s_mov_b32 s4, 1
v_add_co_u32 v3, vcc_lo, v0, s3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v1, vcc_lo
v_sub_co_u32 v5, vcc_lo, v0, s3
v_subrev_co_ci_u32_e32 v6, vcc_lo, 0, v1, vcc_lo
s_clause 0x5
global_load_u8 v9, v[3:4], off
global_load_u8 v10, v[3:4], off offset:1
global_load_u8 v11, v[5:6], off
global_load_u8 v12, v[5:6], off offset:1
global_load_u8 v5, v[5:6], off offset:-1
global_load_u8 v3, v[3:4], off offset:-1
s_mov_b32 s3, 0
s_mov_b32 s5, 0
s_mov_b32 s2, 0
s_waitcnt vmcnt(7)
v_cmp_eq_u16_e32 vcc_lo, 1, v7
v_cndmask_b32_e64 v4, 0, 1, vcc_lo
v_cndmask_b32_e64 v6, 1, 2, vcc_lo
s_waitcnt vmcnt(6)
v_cmp_eq_u16_e32 vcc_lo, 1, v8
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v4, v4, v6, vcc_lo
s_waitcnt vmcnt(5)
v_cmp_eq_u16_e32 vcc_lo, 1, v9
v_cndmask_b32_e64 v6, 0, 1, vcc_lo
s_waitcnt vmcnt(4)
v_cmp_eq_u16_e32 vcc_lo, 1, v10
v_cndmask_b32_e64 v7, 0, 1, vcc_lo
s_waitcnt vmcnt(3)
v_cmp_eq_u16_e32 vcc_lo, 1, v11
v_add_co_ci_u32_e32 v4, vcc_lo, v4, v6, vcc_lo
s_waitcnt vmcnt(0)
v_cmp_eq_u16_e32 vcc_lo, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, v4, v7, vcc_lo
v_cmp_eq_u16_e32 vcc_lo, 1, v12
v_cndmask_b32_e64 v4, 0, 1, vcc_lo
v_cmp_eq_u16_e32 vcc_lo, 1, v5
v_add_co_ci_u32_e32 v4, vcc_lo, v3, v4, vcc_lo
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_lt_i32_e32 2, v4
s_xor_b32 s6, exec_lo, s6
v_cmp_ne_u32_e32 vcc_lo, 3, v4
s_mov_b32 s2, exec_lo
s_and_b32 s5, vcc_lo, exec_lo
s_and_not1_saveexec_b32 s6, s6
v_cmp_ne_u32_e32 vcc_lo, 2, v4
s_and_not1_b32 s5, s5, exec_lo
s_mov_b32 s3, exec_lo
s_and_b32 s7, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s5, s5, s7
s_or_b32 exec_lo, exec_lo, s6
v_mov_b32_e32 v4, s4
s_and_saveexec_b32 s4, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s4, exec_lo, s4
v_mov_b32_e32 v4, 0
s_or_b32 s2, s2, exec_lo
s_and_not1_b32 s3, s3, exec_lo
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s4, s3
s_cbranch_execz .LBB1_9
global_load_u8 v0, v[0:1], off
v_mov_b32_e32 v4, 1
s_and_not1_b32 s2, s2, exec_lo
s_waitcnt vmcnt(0)
v_cmp_eq_u16_e32 vcc_lo, 1, v0
s_and_b32 s3, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s2, s2, s3
.LBB1_9:
s_or_b32 exec_lo, exec_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB1_11
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_b8 v[0:1], v4, off
.LBB1_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPhS_jj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z6kernelPhS_jj, .Lfunc_end1-_Z6kernelPhS_jj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7kernel2PfS_P15HIP_vector_typeIhLj4EEii
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z7kernel2PfS_P15HIP_vector_typeIhLj4EEii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPhS_jj
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z6kernelPhS_jj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
*
* compiling:
* nvcc -lglut -LGLEW life.cuda.cu -o life
*
* for it's work:
* export LD_LIBRARY_PATH=:/usr/local/cuda/lib
* export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/usr/local/cuda/libnvvp/
*
* cuda-gdb
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#define uchar unsigned char
#define NUMBER_OF_THREADS 512
uchar * dev_array1;
uchar * dev_array2;
uint * dev_size_x;
uint * dev_size_y;
uint sizeX,sizeY;
// bad -> fix it
__global__ void kernel2(float * field1, float * field2, uchar4 * screen, int sizex, int sizey)
{
// int id = threadIdx.x + blockIdx.x*blockDim.x + threadIdx.y + blockIdx.y*blockDim.y;
int id = threadIdx.x+threadIdx.y;
int numberofneighbours=0;
numberofneighbours += *(field1 + id + 1);
numberofneighbours += *(field1 + id - 1);
numberofneighbours += *(field1 + id + sizey);
numberofneighbours += *(field1 + id - sizey);
numberofneighbours += *(field1 + id + sizey + 1);
numberofneighbours += *(field1 + id + sizey - 1);
numberofneighbours += *(field1 + id - sizey - 1);
numberofneighbours += *(field1 + id + sizey + 1);
// (screen + id)->x = numberofneighbours;
// (screen + id)->x = 1;
// *(field2 + id) = 1;
// if(*(field1 + id) == 1) *(field2 + id) = 1;
/*
switch(numberofneighbours)
{
case 3 : *(field2 + id) = 1;
(screen + id)->x = 0;
(screen + id)->y = 250;
(screen + id)->z = 0;
(screen + id)->w = 0;
break;
case 2 : if(*(field1 + id) == 1)
{
*(field2 + id) = 1;
(screen + id)->x = 0;
(screen + id)->y = 250;
(screen + id)->z = 0;
(screen + id)->w = 0;
}
else
{
*(field2 + id) = 0;
(screen + id)->x = 0;
(screen + id)->y = 0;
(screen + id)->z = 0;
(screen + id)->w = 0;
}
break;
default : *(field2 + id) = 0;
(screen + id)->x = 0;
(screen + id)->y = 0;
(screen + id)->z = 0;
(screen + id)->w = 0;
break;
}
*/
}
__global__ void kernel(uchar * array1, uchar * array2, uint size_x, uint size_y)
{
// int id = threadIdx.x*blockIdx.x+blockDim.x + threadIdx.y*blockIdx.y+blockDim.y;
int id = threadIdx.x+threadIdx.y;
if(id < size_x*size_y)
{
int numberofneighbours=0;
int num = 0;
// заменить на num += ...
if(*(array1 + id + 1) == 1) num++;
if(*(array1 + id - 1) == 1) num++;
if(*(array1 + id + size_y) == 1) num++;
if(*(array1 + id - size_y) == 1) num++;
if(*(array1 + id + size_y + 1) == 1) num++;
if(*(array1 + id + size_y - 1) == 1) num++;
if(*(array1 + id - size_y + 1) == 1) num++;
if(*(array1 + id - size_y - 1) == 1) num++;
switch(num)
{
case 3 : *(array2 + id) = 1; break;
case 2 : if(*(array1 + id) == 1) *(array2 + id) = 1; break;
default : *(array2 + id) = 0; break;
}
}
}
void initCuda(uchar * array1, uchar * array2, uint size_x, uint size_y)
{
sizeX = size_x;
sizeY = size_y;
hipMalloc((void**)&dev_array1,sizeof(uchar)*size_x*size_y);
hipMalloc((void**)&dev_array2,sizeof(uchar)*size_x*size_y);
hipMalloc((void**)&dev_size_x,sizeof(uint));
hipMalloc((void**)&dev_size_y,sizeof(uint));
hipMemcpy(dev_array1,array1,sizeof(uchar)*size_x*size_y,hipMemcpyHostToDevice);
hipMemcpy(dev_size_x,&size_x,sizeof(uchar),hipMemcpyHostToDevice);
hipMemcpy(dev_size_y,&size_y,sizeof(uchar),hipMemcpyHostToDevice);
hipMemset(dev_array2,0,size_x*size_y);
}
void get_result(uchar * array)
{
hipMemcpy(array,dev_array2,sizeX*sizeY*sizeof(uchar),hipMemcpyDeviceToHost);
}
void cuda_run()
{
int threads = NUMBER_OF_THREADS;
int blocks = sizeX*sizeY/threads+1;
// kernel <<<blocks,threads>>>(dev_array1,dev_array2,dev_size_x,dev_size_y);
kernel <<<blocks,threads>>>(dev_array1,dev_array2,sizeX,sizeY);
}
void FreeCuda()
{
hipFree(dev_array1);
hipFree(dev_array2);
hipFree(dev_size_x);
hipFree(dev_size_y);
}
void check(uchar * array1, uchar * array2, uint * size_x, uint * size_y)
{
int num=0;
puts("<=================>\n");
printf("%u %u\n",*size_x,*size_y);
puts("<=================>\n");
for(int i=0;i<(*size_x * (*size_y));i++)
{
num = 0;
if(*(array1 + i + 1) == 1) num++;
if(*(array1 + i - 1) == 1) num++;
if(*(array1 + i + *size_y) == 1) num++;
if(*(array1 + i - *size_y) == 1) num++;
if(*(array1 + i + *size_y + 1) == 1) num++;
if(*(array1 + i + *size_y - 1) == 1) num++;
if(*(array1 + i - *size_y + 1) == 1) num++;
if(*(array1 + i - *size_y - 1) == 1) num++;
// *(array2 + i) = num;
switch(num)
{
case 3 : *(array2 + i) = 1; break;
case 2 : if(*(array1 + i) == 1) *(array2 + i) = 1; break;
default : *(array2 + i) = 0; break;
}
}
puts("<=================>\n");
}
#define cell_size 5
#define uchar unsigned char
#define screen_width 20
#define screen_height 20
int width = screen_width*cell_size; //770; //1024;
int height = screen_width*cell_size; //770; //768;
/*
int main()
{
// uchar field1[screen_width][screen_height];
// uchar field2[screen_width][screen_height];
uchar field1[screen_width*screen_height];
uchar field2[screen_width*screen_height];
for(int i=0;i<screen_width;i++)
{
for(int j=0;j<screen_height;j++)
{
field1[i+j*screen_width] = 0;
field2[i+j*screen_width] = 0;
}
}
field1[0+0*screen_width] = 1;
field1[0+1*screen_width] = 1;
field1[0+2*screen_width] = 1;
// field1[1][0] = 1;
field1[1+1*screen_width] = 1;
field1[3+3*screen_width] = 1;
field1[4+3*screen_width] = 1;
field1[10+5*screen_width] = 1;
field1[10+6*screen_width] = 1;
field1[11+5*screen_width] = 1;
field1[11+6*screen_width] = 1;
// field1[10][7] = 1;
for(int i=0;i<screen_width;i++)
{
for(int j=0;j<screen_height;j++)
{
if(field1[i+j*screen_width] == 1) printf("*");
else printf(".");
// printf("%c ",field1[i][j]);
}
printf("\n");
}
sizeX = 20;
sizeY = 20;
//=======================================================================
/*
check(field1,field2,&sizeX,&sizeY);
for(int i=0;i<screen_width;i++)
{
for(int j=0;j<screen_height;j++)
{
if(field2[i+j*screen_width] == 1) printf("*");
else printf("%i",(int) field2[i+j*screen_width]);
// printf("%c ",field2[i][j]);
}
printf("\n");
}
*/
//=======================================================================
/*
initCuda(&field1[0],&field2[0],screen_width,screen_height);
cuda_run();
get_result(&field2[0]);
puts("\n<==========>\n\n");
for(int i=0;i<screen_width;i++)
{
for(int j=0;j<screen_height;j++)
{
if(field2[i+j*screen_width] == 1) printf("*");
else printf("%i",(int) field2[i+j*screen_width]);
// printf("%c ",field2[i][j]);
}
printf("\n");
}
FreeCuda();
return 0;
}
*/
int main()
{
float * field1;
field1 = (float *) malloc(sizeof(float)*screen_width*screen_height);
uchar4 * screen;
screen = (uchar4 *) malloc(sizeof(uchar4)*screen_width*screen_height);
float * dev_field1;
float * dev_field2;
uchar4 * dev_screen;
*(field1 + 10) = 1;
field1[40] = 1;
field1[41] = 1;
field1[59] = 1;
field1[60] = 1;
field1[90] = 1;
field1[91] = 1;
field1[92] = 1;
for(int i=0;i<=400;i++)
{
printf("%i",(int) *(field1+i));
if(i % 19 == 0) printf("\n");
}
printf("\n");
hipMalloc((void **)&dev_field1,sizeof(float)*screen_width*screen_height);
hipMalloc((void **)&dev_field2,sizeof(float)*screen_width*screen_height);
hipMalloc((void **)&dev_screen,sizeof(uchar4)*screen_width*screen_height);
hipMemcpy(dev_field1,field1,sizeof(uchar4)*screen_width*screen_height,hipMemcpyHostToDevice);
hipMemset(dev_field2,8,sizeof(float)*screen_width*screen_height);
kernel2<<<10 , 10>>>(dev_field1,dev_field2,dev_screen,20,20);
float * field2;
field2 = (float *) malloc(sizeof(float)*screen_width*screen_height);
hipMemcpy(field2,dev_field2,sizeof(float)*screen_width*screen_height,hipMemcpyDeviceToHost);
hipMemcpy(screen,dev_screen,sizeof(uchar4)*screen_width*screen_height,hipMemcpyDeviceToHost);
hipFree(dev_field1);
hipFree(dev_field2);
hipFree(dev_screen);
for(int i=0;i<400;i++)
{
printf("%i",(int) (screen+i)->x);
if(i % 19 == 0) printf("\n");
}
printf("\n");
for(int i=0;i<400;i++)
{
printf("%4i",(int) *(field2+i));
if(i % 19 == 0) printf("\n");
}
printf("\n");
free(field1);
free(field2);
free(screen);
} | .text
.file "life.cuda.hip"
.globl _Z22__device_stub__kernel2PfS_P15HIP_vector_typeIhLj4EEii # -- Begin function _Z22__device_stub__kernel2PfS_P15HIP_vector_typeIhLj4EEii
.p2align 4, 0x90
.type _Z22__device_stub__kernel2PfS_P15HIP_vector_typeIhLj4EEii,@function
_Z22__device_stub__kernel2PfS_P15HIP_vector_typeIhLj4EEii: # @_Z22__device_stub__kernel2PfS_P15HIP_vector_typeIhLj4EEii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7kernel2PfS_P15HIP_vector_typeIhLj4EEii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__kernel2PfS_P15HIP_vector_typeIhLj4EEii, .Lfunc_end0-_Z22__device_stub__kernel2PfS_P15HIP_vector_typeIhLj4EEii
.cfi_endproc
# -- End function
.globl _Z21__device_stub__kernelPhS_jj # -- Begin function _Z21__device_stub__kernelPhS_jj
.p2align 4, 0x90
.type _Z21__device_stub__kernelPhS_jj,@function
_Z21__device_stub__kernelPhS_jj: # @_Z21__device_stub__kernelPhS_jj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelPhS_jj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z21__device_stub__kernelPhS_jj, .Lfunc_end1-_Z21__device_stub__kernelPhS_jj
.cfi_endproc
# -- End function
.globl _Z8initCudaPhS_jj # -- Begin function _Z8initCudaPhS_jj
.p2align 4, 0x90
.type _Z8initCudaPhS_jj,@function
_Z8initCudaPhS_jj: # @_Z8initCudaPhS_jj
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $16, %rsp
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -16
movq %rdi, %rbx
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %edx, sizeX(%rip)
movl %ecx, sizeY(%rip)
movl %edx, %eax
movl %ecx, %esi
imulq %rax, %rsi
movl $dev_array1, %edi
callq hipMalloc
movl 12(%rsp), %eax
movl 8(%rsp), %esi
imulq %rax, %rsi
movl $dev_array2, %edi
callq hipMalloc
movl $dev_size_x, %edi
movl $4, %esi
callq hipMalloc
movl $dev_size_y, %edi
movl $4, %esi
callq hipMalloc
movq dev_array1(%rip), %rdi
movl 12(%rsp), %eax
movl 8(%rsp), %edx
imulq %rax, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq dev_size_x(%rip), %rdi
leaq 12(%rsp), %rsi
movl $1, %edx
movl $1, %ecx
callq hipMemcpy
movq dev_size_y(%rip), %rdi
leaq 8(%rsp), %rsi
movl $1, %edx
movl $1, %ecx
callq hipMemcpy
movq dev_array2(%rip), %rdi
movl 8(%rsp), %edx
imull 12(%rsp), %edx
xorl %esi, %esi
callq hipMemset
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z8initCudaPhS_jj, .Lfunc_end2-_Z8initCudaPhS_jj
.cfi_endproc
# -- End function
.globl _Z10get_resultPh # -- Begin function _Z10get_resultPh
.p2align 4, 0x90
.type _Z10get_resultPh,@function
_Z10get_resultPh: # @_Z10get_resultPh
.cfi_startproc
# %bb.0:
movq dev_array2(%rip), %rsi
movl sizeY(%rip), %edx
imull sizeX(%rip), %edx
movl $2, %ecx
jmp hipMemcpy # TAILCALL
.Lfunc_end3:
.size _Z10get_resultPh, .Lfunc_end3-_Z10get_resultPh
.cfi_endproc
# -- End function
.globl _Z8cuda_runv # -- Begin function _Z8cuda_runv
.p2align 4, 0x90
.type _Z8cuda_runv,@function
_Z8cuda_runv: # @_Z8cuda_runv
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl sizeY(%rip), %eax
imull sizeX(%rip), %eax
shrl $9, %eax
movabsq $4294967296, %rdx # imm = 0x100000000
leaq (%rdx,%rax), %rdi
incq %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB4_1
# %bb.2:
addq $120, %rsp
.cfi_def_cfa_offset 8
retq
.LBB4_1:
.cfi_def_cfa_offset 128
movq dev_array1(%rip), %rax
movq dev_array2(%rip), %rcx
movl sizeX(%rip), %edx
movl sizeY(%rip), %esi
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movl %edx, 12(%rsp)
movl %esi, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelPhS_jj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
addq $120, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z8cuda_runv, .Lfunc_end4-_Z8cuda_runv
.cfi_endproc
# -- End function
.globl _Z8FreeCudav # -- Begin function _Z8FreeCudav
.p2align 4, 0x90
.type _Z8FreeCudav,@function
_Z8FreeCudav: # @_Z8FreeCudav
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq dev_array1(%rip), %rdi
callq hipFree
movq dev_array2(%rip), %rdi
callq hipFree
movq dev_size_x(%rip), %rdi
callq hipFree
movq dev_size_y(%rip), %rdi
popq %rax
.cfi_def_cfa_offset 8
jmp hipFree # TAILCALL
.Lfunc_end5:
.size _Z8FreeCudav, .Lfunc_end5-_Z8FreeCudav
.cfi_endproc
# -- End function
.globl _Z5checkPhS_PjS0_ # -- Begin function _Z5checkPhS_PjS0_
.p2align 4, 0x90
.type _Z5checkPhS_PjS0_,@function
_Z5checkPhS_PjS0_: # @_Z5checkPhS_PjS0_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rcx, %rbx
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
movl $.L.str, %edi
callq puts
movl (%r14), %esi
movl (%rbx), %edx
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl $.L.str, %edi
callq puts
movl (%rbx), %ecx
movl (%r14), %eax
imull %ecx, %eax
testl %eax, %eax
je .LBB6_8
# %bb.1: # %.lr.ph.preheader
xorl %eax, %eax
jmp .LBB6_2
.p2align 4, 0x90
.LBB6_5: # in Loop: Header=BB6_2 Depth=1
xorl %ecx, %ecx
.LBB6_6: # %.sink.split
# in Loop: Header=BB6_2 Depth=1
movb %cl, (%r15,%rax)
.LBB6_7: # in Loop: Header=BB6_2 Depth=1
incq %rax
movl (%rbx), %ecx
movl (%r14), %edx
imull %ecx, %edx
cmpq %rdx, %rax
jae .LBB6_8
.LBB6_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
leaq (%r12,%rax), %rdx
xorl %esi, %esi
cmpb $1, 1(%r12,%rax)
sete %sil
leal 1(%rsi), %edi
cmpb $1, -1(%r12,%rax)
cmovnel %esi, %edi
movl %ecx, %r8d
xorl %r9d, %r9d
cmpb $1, (%r8,%rdx)
sete %r9b
movq %rdx, %rsi
subq %r8, %rsi
xorl %ecx, %ecx
cmpb $1, (%rsi)
sete %cl
addl %r9d, %ecx
addl %edi, %ecx
xorl %edi, %edi
cmpb $1, 1(%r8,%rdx)
sete %dil
xorl %r9d, %r9d
cmpb $1, -1(%r8,%rdx)
sete %r9b
addl %edi, %r9d
xorl %edi, %edi
cmpb $1, 1(%rsi)
sete %dil
addl %r9d, %edi
xorl %edx, %edx
cmpb $1, -1(%rsi)
sete %dl
addl %edi, %edx
addl %ecx, %edx
movb $1, %cl
cmpl $3, %edx
je .LBB6_6
# %bb.3: # %.lr.ph
# in Loop: Header=BB6_2 Depth=1
cmpl $2, %edx
jne .LBB6_5
# %bb.4: # in Loop: Header=BB6_2 Depth=1
cmpb $1, (%r12,%rax)
je .LBB6_6
jmp .LBB6_7
.LBB6_8: # %._crit_edge
movl $.L.str, %edi
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp puts # TAILCALL
.Lfunc_end6:
.size _Z5checkPhS_PjS0_, .Lfunc_end6-_Z5checkPhS_PjS0_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $1600, %edi # imm = 0x640
callq malloc
movq %rax, %r14
movl $1600, %edi # imm = 0x640
callq malloc
movq %rax, 16(%rsp) # 8-byte Spill
movl $1065353216, 40(%r14) # imm = 0x3F800000
movabsq $4575657222473777152, %rax # imm = 0x3F8000003F800000
movq %rax, 160(%r14)
movq %rax, 236(%r14)
movq %rax, 360(%r14)
movl $1065353216, 368(%r14) # imm = 0x3F800000
movq $-1604, %r15 # imm = 0xF9BC
movl $2938661835, %r12d # imm = 0xAF286BCB
xorl %ebp, %ebp
xorl %r13d, %r13d
jmp .LBB7_1
.p2align 4, 0x90
.LBB7_3: # in Loop: Header=BB7_1 Depth=1
decl %r13d
incl %ebp
addq $4, %r15
je .LBB7_4
.LBB7_1: # =>This Inner Loop Header: Depth=1
movl %ebp, %eax
imulq %r12, %rax
shrq $32, %rax
movl %ebp, %ecx
subl %eax, %ecx
shrl %ecx
addl %eax, %ecx
shrl $4, %ecx
leal (%rcx,%rcx,8), %eax
leal (%rcx,%rax,2), %ebx
cvttss2si 1604(%r14,%r15), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
addl %r13d, %ebx
jne .LBB7_3
# %bb.2: # in Loop: Header=BB7_1 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB7_3
.LBB7_4:
movl $10, %edi
callq putchar@PLT
leaq 32(%rsp), %rdi
movl $1600, %esi # imm = 0x640
callq hipMalloc
leaq 8(%rsp), %rdi
movl $1600, %esi # imm = 0x640
callq hipMalloc
leaq 24(%rsp), %rdi
movl $1600, %esi # imm = 0x640
callq hipMalloc
movq 32(%rsp), %rdi
movl $1600, %edx # imm = 0x640
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $1600, %edx # imm = 0x640
movl $8, %esi
callq hipMemset
movabsq $4294967306, %rdi # imm = 0x10000000A
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_6
# %bb.5:
movq 32(%rsp), %rax
movq 8(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl $20, 44(%rsp)
movl $20, 40(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 44(%rsp), %rax
movq %rax, 152(%rsp)
leaq 40(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z7kernel2PfS_P15HIP_vector_typeIhLj4EEii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_6:
movq %r14, 48(%rsp) # 8-byte Spill
movl $1600, %edi # imm = 0x640
callq malloc
movq %rax, %r15
movq 8(%rsp), %rsi
movl $1600, %edx # imm = 0x640
movq %rax, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rsi
movl $1600, %edx # imm = 0x640
movq 16(%rsp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq $-1600, %r12 # imm = 0xF9C0
movl $2938661835, %r13d # imm = 0xAF286BCB
xorl %ebp, %ebp
xorl %ebx, %ebx
jmp .LBB7_7
.p2align 4, 0x90
.LBB7_9: # in Loop: Header=BB7_7 Depth=1
decl %ebx
incl %ebp
addq $4, %r12
je .LBB7_10
.LBB7_7: # =>This Inner Loop Header: Depth=1
movl %ebp, %eax
imulq %r13, %rax
shrq $32, %rax
movl %ebp, %ecx
subl %eax, %ecx
shrl %ecx
addl %eax, %ecx
shrl $4, %ecx
leal (%rcx,%rcx,8), %eax
leal (%rcx,%rax,2), %r14d
movq 16(%rsp), %rax # 8-byte Reload
movzbl 1600(%rax,%r12), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
addl %ebx, %r14d
jne .LBB7_9
# %bb.8: # in Loop: Header=BB7_7 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB7_9
.LBB7_10:
movl $10, %edi
callq putchar@PLT
movq $-1600, %r12 # imm = 0xF9C0
movl $2938661835, %r13d # imm = 0xAF286BCB
xorl %ebp, %ebp
xorl %ebx, %ebx
jmp .LBB7_11
.p2align 4, 0x90
.LBB7_13: # in Loop: Header=BB7_11 Depth=1
decl %ebx
incl %ebp
addq $4, %r12
je .LBB7_14
.LBB7_11: # =>This Inner Loop Header: Depth=1
movl %ebp, %eax
imulq %r13, %rax
shrq $32, %rax
movl %ebp, %ecx
subl %eax, %ecx
shrl %ecx
addl %eax, %ecx
shrl $4, %ecx
leal (%rcx,%rcx,8), %eax
leal (%rcx,%rax,2), %r14d
cvttss2si 1600(%r15,%r12), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
addl %ebx, %r14d
jne .LBB7_13
# %bb.12: # in Loop: Header=BB7_11 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB7_13
.LBB7_14:
movl $10, %edi
callq putchar@PLT
movq 48(%rsp), %rdi # 8-byte Reload
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi # 8-byte Reload
callq free
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size main, .Lfunc_end7-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kernel2PfS_P15HIP_vector_typeIhLj4EEii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPhS_jj, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type dev_array1,@object # @dev_array1
.bss
.globl dev_array1
.p2align 3, 0x0
dev_array1:
.quad 0
.size dev_array1, 8
.type dev_array2,@object # @dev_array2
.globl dev_array2
.p2align 3, 0x0
dev_array2:
.quad 0
.size dev_array2, 8
.type dev_size_x,@object # @dev_size_x
.globl dev_size_x
.p2align 3, 0x0
dev_size_x:
.quad 0
.size dev_size_x, 8
.type dev_size_y,@object # @dev_size_y
.globl dev_size_y
.p2align 3, 0x0
dev_size_y:
.quad 0
.size dev_size_y, 8
.type sizeX,@object # @sizeX
.globl sizeX
.p2align 2, 0x0
sizeX:
.long 0 # 0x0
.size sizeX, 4
.type sizeY,@object # @sizeY
.globl sizeY
.p2align 2, 0x0
sizeY:
.long 0 # 0x0
.size sizeY, 4
.type _Z7kernel2PfS_P15HIP_vector_typeIhLj4EEii,@object # @_Z7kernel2PfS_P15HIP_vector_typeIhLj4EEii
.section .rodata,"a",@progbits
.globl _Z7kernel2PfS_P15HIP_vector_typeIhLj4EEii
.p2align 3, 0x0
_Z7kernel2PfS_P15HIP_vector_typeIhLj4EEii:
.quad _Z22__device_stub__kernel2PfS_P15HIP_vector_typeIhLj4EEii
.size _Z7kernel2PfS_P15HIP_vector_typeIhLj4EEii, 8
.type _Z6kernelPhS_jj,@object # @_Z6kernelPhS_jj
.globl _Z6kernelPhS_jj
.p2align 3, 0x0
_Z6kernelPhS_jj:
.quad _Z21__device_stub__kernelPhS_jj
.size _Z6kernelPhS_jj, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "<=================>\n"
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%u %u\n"
.size .L.str.1, 7
.type width,@object # @width
.data
.globl width
.p2align 2, 0x0
width:
.long 100 # 0x64
.size width, 4
.type height,@object # @height
.globl height
.p2align 2, 0x0
height:
.long 100 # 0x64
.size height, 4
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "%i"
.size .L.str.2, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%4i"
.size .L.str.4, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7kernel2PfS_P15HIP_vector_typeIhLj4EEii"
.size .L__unnamed_1, 42
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z6kernelPhS_jj"
.size .L__unnamed_2, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__kernel2PfS_P15HIP_vector_typeIhLj4EEii
.addrsig_sym _Z21__device_stub__kernelPhS_jj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym dev_array1
.addrsig_sym dev_array2
.addrsig_sym dev_size_x
.addrsig_sym dev_size_y
.addrsig_sym _Z7kernel2PfS_P15HIP_vector_typeIhLj4EEii
.addrsig_sym _Z6kernelPhS_jj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kernelPhS_jj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_TID.Y ; /* 0x0000000000087919 */
/* 0x000e220000002200 */
/*0020*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff077624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0040*/ IMAD R3, R7, c[0x0][0x170], RZ ; /* 0x00005c0007037a24 */
/* 0x000fe400078e02ff */
/*0050*/ IMAD.IADD R8, R8, 0x1, R5 ; /* 0x0000000108087824 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fda0003f06070 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ SHF.R.S32.HI R0, RZ, 0x1f, R8 ; /* 0x0000001fff007819 */
/* 0x000fe20000011408 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IADD3 R2, P0, R8, c[0x0][0x160], RZ ; /* 0x0000580008027a10 */
/* 0x000fc80007f1e0ff */
/*00b0*/ IADD3.X R3, R0, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590000037a10 */
/* 0x000fe400007fe4ff */
/*00c0*/ IADD3 R4, P0, P1, R7, c[0x0][0x160], R8 ; /* 0x0000580007047a10 */
/* 0x000fc6000791e008 */
/*00d0*/ LDG.E.U8 R16, [R2.64+-0x1] ; /* 0xffffff0402107981 */
/* 0x000ea2000c1e1100 */
/*00e0*/ IADD3 R6, P2, P3, R8, c[0x0][0x160], -R7 ; /* 0x0000580008067a10 */
/* 0x000fe20007b5e807 */
/*00f0*/ IMAD.MOV.U32 R7, RZ, RZ, -0x1 ; /* 0xffffffffff077424 */
/* 0x000fe200078e00ff */
/*0100*/ IADD3.X R5, RZ, c[0x0][0x164], R0, P0, P1 ; /* 0x00005900ff057a10 */
/* 0x000fe200007e2400 */
/*0110*/ LDG.E.U8 R9, [R2.64+0x1] ; /* 0x0000010402097981 */
/* 0x000ee6000c1e1100 */
/*0120*/ IADD3.X R7, R0, c[0x0][0x164], R7, P2, P3 ; /* 0x0000590000077a10 */
/* 0x000fe200017e6407 */
/*0130*/ LDG.E.U8 R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000f28000c1e1100 */
/*0140*/ LDG.E.U8 R11, [R6.64] ; /* 0x00000004060b7981 */
/* 0x000f68000c1e1100 */
/*0150*/ LDG.E.U8 R12, [R4.64+0x1] ; /* 0x00000104040c7981 */
/* 0x000f68000c1e1100 */
/*0160*/ LDG.E.U8 R13, [R4.64+-0x1] ; /* 0xffffff04040d7981 */
/* 0x000168000c1e1100 */
/*0170*/ LDG.E.U8 R14, [R6.64+0x1] ; /* 0x00000104060e7981 */
/* 0x000f68000c1e1100 */
/*0180*/ LDG.E.U8 R15, [R6.64+-0x1] ; /* 0xffffff04060f7981 */
/* 0x000f62000c1e1100 */
/*0190*/ ISETP.NE.AND P1, PT, R16, 0x1, PT ; /* 0x000000011000780c */
/* 0x004fe20003f25270 */
/*01a0*/ IMAD.MOV.U32 R16, RZ, RZ, 0x2 ; /* 0x00000002ff107424 */
/* 0x000fe200078e00ff */
/*01b0*/ ISETP.NE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x008fc80003f05270 */
/*01c0*/ SEL R9, RZ, 0x1, P0 ; /* 0x00000001ff097807 */
/* 0x000fe40000000000 */
/*01d0*/ ISETP.NE.AND P2, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x010fca0003f45270 */
/*01e0*/ @!P1 SEL R9, R16, 0x1, !P0 ; /* 0x0000000110099807 */
/* 0x000fe40004000000 */
/*01f0*/ ISETP.NE.AND P0, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x020fe40003f05270 */
/*0200*/ SEL R10, RZ, 0x1, P2 ; /* 0x00000001ff0a7807 */
/* 0x000fe40001000000 */
/*0210*/ ISETP.NE.AND P1, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fc60003f25270 */
/*0220*/ IMAD.IADD R9, R9, 0x1, R10 ; /* 0x0000000109097824 */
/* 0x000fca00078e020a */
/*0230*/ IADD3 R4, R9, 0x1, RZ ; /* 0x0000000109047810 */
/* 0x001fe20007ffe0ff */
/*0240*/ @P0 IMAD.MOV R4, RZ, RZ, R9 ; /* 0x000000ffff040224 */
/* 0x000fe200078e0209 */
/*0250*/ ISETP.NE.AND P0, PT, R13, 0x1, PT ; /* 0x000000010d00780c */
/* 0x000fc80003f05270 */
/*0260*/ IADD3 R5, R4, 0x1, RZ ; /* 0x0000000104057810 */
/* 0x000fe20007ffe0ff */
/*0270*/ @P1 IMAD.MOV R5, RZ, RZ, R4 ; /* 0x000000ffff051224 */
/* 0x000fe200078e0204 */
/*0280*/ ISETP.NE.AND P1, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fc80003f25270 */
/*0290*/ IADD3 R4, R5, 0x1, RZ ; /* 0x0000000105047810 */
/* 0x000fc60007ffe0ff */
/*02a0*/ @P0 IMAD.MOV R4, RZ, RZ, R5 ; /* 0x000000ffff040224 */
/* 0x000fe200078e0205 */
/*02b0*/ ISETP.NE.AND P0, PT, R15, 0x1, PT ; /* 0x000000010f00780c */
/* 0x000fc80003f05270 */
/*02c0*/ IADD3 R5, R4, 0x1, RZ ; /* 0x0000000104057810 */
/* 0x000fe20007ffe0ff */
/*02d0*/ @P1 IMAD.MOV R5, RZ, RZ, R4 ; /* 0x000000ffff051224 */
/* 0x000fe200078e0204 */
/*02e0*/ IADD3 R4, P1, R8, c[0x0][0x168], RZ ; /* 0x00005a0008047a10 */
/* 0x000fc80007f3e0ff */
/*02f0*/ IADD3 R6, R5, 0x1, RZ ; /* 0x0000000105067810 */
/* 0x000fc60007ffe0ff */
/*0300*/ @P0 IMAD.MOV R6, RZ, RZ, R5 ; /* 0x000000ffff060224 */
/* 0x000fe200078e0205 */
/*0310*/ IADD3.X R5, R0, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0000057a10 */
/* 0x000fc80000ffe4ff */
/*0320*/ ISETP.NE.AND P0, PT, R6, 0x2, PT ; /* 0x000000020600780c */
/* 0x000fda0003f05270 */
/*0330*/ @!P0 BRA 0x3a0 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*0340*/ ISETP.NE.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe20003f05270 */
/*0350*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fd800078e00ff */
/*0360*/ @!P0 STG.E.U8 [R4.64], R2 ; /* 0x0000000204008986 */
/* 0x0001e2000c101104 */
/*0370*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0380*/ STG.E.U8 [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x000fe2000c101104 */
/*0390*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03a0*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1100 */
/*03b0*/ ISETP.NE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x004fda0003f05270 */
/*03c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*03d0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fca00078e00ff */
/*03e0*/ STG.E.U8 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x000fe2000c101104 */
/*03f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0400*/ BRA 0x400; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7kernel2PfS_P6uchar4ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7kernel2PfS_P15HIP_vector_typeIhLj4EEii
.globl _Z7kernel2PfS_P15HIP_vector_typeIhLj4EEii
.p2align 8
.type _Z7kernel2PfS_P15HIP_vector_typeIhLj4EEii,@function
_Z7kernel2PfS_P15HIP_vector_typeIhLj4EEii:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7kernel2PfS_P15HIP_vector_typeIhLj4EEii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7kernel2PfS_P15HIP_vector_typeIhLj4EEii, .Lfunc_end0-_Z7kernel2PfS_P15HIP_vector_typeIhLj4EEii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z6kernelPhS_jj
.globl _Z6kernelPhS_jj
.p2align 8
.type _Z6kernelPhS_jj,@function
_Z6kernelPhS_jj:
s_load_b64 s[2:3], s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v2, v1, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s3, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s2, v2
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_11
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_u8 v7, v2, s[4:5] offset:1
global_load_u8 v8, v2, s[4:5] offset:-1
v_add_co_u32 v0, s2, s4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e64 v1, null, s5, 0, s2
s_mov_b32 s4, 1
v_add_co_u32 v3, vcc_lo, v0, s3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v1, vcc_lo
v_sub_co_u32 v5, vcc_lo, v0, s3
v_subrev_co_ci_u32_e32 v6, vcc_lo, 0, v1, vcc_lo
s_clause 0x5
global_load_u8 v9, v[3:4], off
global_load_u8 v10, v[3:4], off offset:1
global_load_u8 v11, v[5:6], off
global_load_u8 v12, v[5:6], off offset:1
global_load_u8 v5, v[5:6], off offset:-1
global_load_u8 v3, v[3:4], off offset:-1
s_mov_b32 s3, 0
s_mov_b32 s5, 0
s_mov_b32 s2, 0
s_waitcnt vmcnt(7)
v_cmp_eq_u16_e32 vcc_lo, 1, v7
v_cndmask_b32_e64 v4, 0, 1, vcc_lo
v_cndmask_b32_e64 v6, 1, 2, vcc_lo
s_waitcnt vmcnt(6)
v_cmp_eq_u16_e32 vcc_lo, 1, v8
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v4, v4, v6, vcc_lo
s_waitcnt vmcnt(5)
v_cmp_eq_u16_e32 vcc_lo, 1, v9
v_cndmask_b32_e64 v6, 0, 1, vcc_lo
s_waitcnt vmcnt(4)
v_cmp_eq_u16_e32 vcc_lo, 1, v10
v_cndmask_b32_e64 v7, 0, 1, vcc_lo
s_waitcnt vmcnt(3)
v_cmp_eq_u16_e32 vcc_lo, 1, v11
v_add_co_ci_u32_e32 v4, vcc_lo, v4, v6, vcc_lo
s_waitcnt vmcnt(0)
v_cmp_eq_u16_e32 vcc_lo, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, v4, v7, vcc_lo
v_cmp_eq_u16_e32 vcc_lo, 1, v12
v_cndmask_b32_e64 v4, 0, 1, vcc_lo
v_cmp_eq_u16_e32 vcc_lo, 1, v5
v_add_co_ci_u32_e32 v4, vcc_lo, v3, v4, vcc_lo
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_lt_i32_e32 2, v4
s_xor_b32 s6, exec_lo, s6
v_cmp_ne_u32_e32 vcc_lo, 3, v4
s_mov_b32 s2, exec_lo
s_and_b32 s5, vcc_lo, exec_lo
s_and_not1_saveexec_b32 s6, s6
v_cmp_ne_u32_e32 vcc_lo, 2, v4
s_and_not1_b32 s5, s5, exec_lo
s_mov_b32 s3, exec_lo
s_and_b32 s7, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s5, s5, s7
s_or_b32 exec_lo, exec_lo, s6
v_mov_b32_e32 v4, s4
s_and_saveexec_b32 s4, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s4, exec_lo, s4
v_mov_b32_e32 v4, 0
s_or_b32 s2, s2, exec_lo
s_and_not1_b32 s3, s3, exec_lo
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s4, s3
s_cbranch_execz .LBB1_9
global_load_u8 v0, v[0:1], off
v_mov_b32_e32 v4, 1
s_and_not1_b32 s2, s2, exec_lo
s_waitcnt vmcnt(0)
v_cmp_eq_u16_e32 vcc_lo, 1, v0
s_and_b32 s3, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s2, s2, s3
.LBB1_9:
s_or_b32 exec_lo, exec_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB1_11
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_b8 v[0:1], v4, off
.LBB1_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPhS_jj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z6kernelPhS_jj, .Lfunc_end1-_Z6kernelPhS_jj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7kernel2PfS_P15HIP_vector_typeIhLj4EEii
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z7kernel2PfS_P15HIP_vector_typeIhLj4EEii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPhS_jj
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z6kernelPhS_jj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000202b2_00000000-6_life.cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8initCudaPhS_jj
.type _Z8initCudaPhS_jj, @function
_Z8initCudaPhS_jj:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %edx, sizeX(%rip)
movl %ecx, sizeY(%rip)
movl %edx, %esi
movl %ecx, %eax
imulq %rax, %rsi
leaq dev_array1(%rip), %rdi
call cudaMalloc@PLT
movl 12(%rsp), %esi
movl 8(%rsp), %eax
imulq %rax, %rsi
leaq dev_array2(%rip), %rdi
call cudaMalloc@PLT
movl $4, %esi
leaq dev_size_x(%rip), %rdi
call cudaMalloc@PLT
movl $4, %esi
leaq dev_size_y(%rip), %rdi
call cudaMalloc@PLT
movl 12(%rsp), %edx
movl 8(%rsp), %eax
imulq %rax, %rdx
movl $1, %ecx
movq %rbx, %rsi
movq dev_array1(%rip), %rdi
call cudaMemcpy@PLT
leaq 12(%rsp), %rsi
movl $1, %ecx
movl $1, %edx
movq dev_size_x(%rip), %rdi
call cudaMemcpy@PLT
leaq 8(%rsp), %rsi
movl $1, %ecx
movl $1, %edx
movq dev_size_y(%rip), %rdi
call cudaMemcpy@PLT
movl 12(%rsp), %edx
imull 8(%rsp), %edx
movl $0, %esi
movq dev_array2(%rip), %rdi
call cudaMemset@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z8initCudaPhS_jj, .-_Z8initCudaPhS_jj
.globl _Z10get_resultPh
.type _Z10get_resultPh, @function
_Z10get_resultPh:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl sizeX(%rip), %edx
imull sizeY(%rip), %edx
movl $2, %ecx
movq dev_array2(%rip), %rsi
call cudaMemcpy@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z10get_resultPh, .-_Z10get_resultPh
.globl _Z8FreeCudav
.type _Z8FreeCudav, @function
_Z8FreeCudav:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq dev_array1(%rip), %rdi
call cudaFree@PLT
movq dev_array2(%rip), %rdi
call cudaFree@PLT
movq dev_size_x(%rip), %rdi
call cudaFree@PLT
movq dev_size_y(%rip), %rdi
call cudaFree@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z8FreeCudav, .-_Z8FreeCudav
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "<=================>\n"
.LC1:
.string "%u %u\n"
.text
.globl _Z5checkPhS_PjS0_
.type _Z5checkPhS_PjS0_, @function
_Z5checkPhS_PjS0_:
.LFB2061:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %rbx
movq %rsi, %r13
movq %rdx, %rbp
movq %rcx, %r12
leaq .LC0(%rip), %r14
movq %r14, %rdi
call puts@PLT
movl (%r12), %ecx
movl 0(%rbp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r14, %rdi
call puts@PLT
movl (%r12), %ecx
movl %ecx, %eax
imull 0(%rbp), %eax
testl %eax, %eax
je .L10
movl $0, %eax
jmp .L21
.L24:
addl $1, %edx
jmp .L11
.L25:
addl $1, %edx
jmp .L12
.L26:
addl $1, %edx
jmp .L13
.L27:
addl $1, %edx
jmp .L14
.L28:
addl $1, %edx
jmp .L15
.L29:
addl $1, %edx
jmp .L16
.L17:
cmpl $2, %edx
je .L18
cmpl $3, %edx
sete 0(%r13,%rax)
.L20:
movl (%r12), %ecx
addq $1, %rax
movl %ecx, %edx
imull 0(%rbp), %edx
cmpl %edx, %eax
jnb .L10
.L21:
cmpb $1, 1(%rbx,%rax)
sete %dl
movzbl %dl, %edx
cmpb $1, -1(%rbx,%rax)
je .L24
.L11:
movl %ecx, %ecx
leaq (%rcx,%rax), %rdi
cmpb $1, (%rbx,%rdi)
je .L25
.L12:
movq %rax, %rsi
subq %rcx, %rsi
cmpb $1, (%rbx,%rsi)
je .L26
.L13:
cmpb $1, 1(%rbx,%rdi)
je .L27
.L14:
cmpb $1, -1(%rbx,%rdi)
je .L28
.L15:
cmpb $1, 1(%rbx,%rsi)
je .L29
.L16:
cmpb $1, -1(%rbx,%rsi)
jne .L17
addl $1, %edx
jmp .L17
.L18:
cmpb $1, (%rbx,%rax)
jne .L20
movb $1, 0(%r13,%rax)
jmp .L20
.L10:
leaq .LC0(%rip), %rdi
call puts@PLT
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z5checkPhS_PjS0_, .-_Z5checkPhS_PjS0_
.globl _Z38__device_stub__Z7kernel2PfS_P6uchar4iiPfS_P6uchar4ii
.type _Z38__device_stub__Z7kernel2PfS_P6uchar4iiPfS_P6uchar4ii, @function
_Z38__device_stub__Z7kernel2PfS_P6uchar4iiPfS_P6uchar4ii:
.LFB2087:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L34
.L30:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L35
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7kernel2PfS_P6uchar4ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L30
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z38__device_stub__Z7kernel2PfS_P6uchar4iiPfS_P6uchar4ii, .-_Z38__device_stub__Z7kernel2PfS_P6uchar4iiPfS_P6uchar4ii
.globl _Z7kernel2PfS_P6uchar4ii
.type _Z7kernel2PfS_P6uchar4ii, @function
_Z7kernel2PfS_P6uchar4ii:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z7kernel2PfS_P6uchar4iiPfS_P6uchar4ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z7kernel2PfS_P6uchar4ii, .-_Z7kernel2PfS_P6uchar4ii
.section .rodata.str1.1
.LC3:
.string "%i"
.LC4:
.string "\n"
.LC5:
.string "%4i"
.text
.globl main
.type main, @function
main:
.LFB2062:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $1600, %edi
call malloc@PLT
movq %rax, %rbp
movl $1600, %edi
call malloc@PLT
movq %rax, %r12
movss .LC2(%rip), %xmm0
movss %xmm0, 40(%rbp)
movss %xmm0, 160(%rbp)
movss %xmm0, 164(%rbp)
movss %xmm0, 236(%rbp)
movss %xmm0, 240(%rbp)
movss %xmm0, 360(%rbp)
movss %xmm0, 364(%rbp)
movss %xmm0, 368(%rbp)
movl $0, %ebx
leaq .LC3(%rip), %r13
leaq .LC4(%rip), %r14
jmp .L40
.L39:
addq $1, %rbx
cmpq $401, %rbx
je .L51
.L40:
cvttss2sil 0(%rbp,%rbx,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %ebx, %rax
imulq $1808407283, %rax, %rax
sarq $35, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,8), %edx
leal (%rax,%rdx,2), %eax
cmpl %ebx, %eax
jne .L39
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L39
.L51:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 8(%rsp), %rdi
movl $1600, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $1600, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $1600, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $1600, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1600, %edx
movl $8, %esi
movq 16(%rsp), %rdi
call cudaMemset@PLT
movl $10, 44(%rsp)
movl $1, 48(%rsp)
movl $10, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L41:
movl $1600, %edi
call malloc@PLT
movq %rax, %r13
movl $2, %ecx
movl $1600, %edx
movq 16(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $1600, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movl $0, %ebx
leaq .LC3(%rip), %r14
leaq .LC4(%rip), %r15
jmp .L43
.L52:
movl $20, %r8d
movl $20, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z38__device_stub__Z7kernel2PfS_P6uchar4iiPfS_P6uchar4ii
jmp .L41
.L42:
addq $1, %rbx
cmpq $400, %rbx
je .L53
.L43:
movzbl (%r12,%rbx,4), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %ebx, %rax
imulq $1808407283, %rax, %rax
sarq $35, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,8), %edx
leal (%rax,%rdx,2), %eax
cmpl %ebx, %eax
jne .L42
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L42
.L53:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC5(%rip), %r14
leaq .LC4(%rip), %r15
jmp .L45
.L44:
addq $1, %rbx
cmpq $400, %rbx
je .L54
.L45:
cvttss2sil 0(%r13,%rbx,4), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %ebx, %rax
imulq $1808407283, %rax, %rax
sarq $35, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,8), %edx
leal (%rax,%rdx,2), %eax
cmpl %ebx, %eax
jne .L44
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L44
.L54:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L55
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size main, .-main
.globl _Z29__device_stub__Z6kernelPhS_jjPhS_jj
.type _Z29__device_stub__Z6kernelPhS_jjPhS_jj, @function
_Z29__device_stub__Z6kernelPhS_jjPhS_jj:
.LFB2089:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L60
.L56:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L61
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L60:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6kernelPhS_jj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L56
.L61:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z29__device_stub__Z6kernelPhS_jjPhS_jj, .-_Z29__device_stub__Z6kernelPhS_jjPhS_jj
.globl _Z6kernelPhS_jj
.type _Z6kernelPhS_jj, @function
_Z6kernelPhS_jj:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6kernelPhS_jjPhS_jj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z6kernelPhS_jj, .-_Z6kernelPhS_jj
.globl _Z8cuda_runv
.type _Z8cuda_runv, @function
_Z8cuda_runv:
.LFB2059:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl sizeX(%rip), %eax
imull sizeY(%rip), %eax
shrl $9, %eax
addl $1, %eax
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L67
.L64:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L67:
.cfi_restore_state
movl sizeY(%rip), %ecx
movl sizeX(%rip), %edx
movq dev_array2(%rip), %rsi
movq dev_array1(%rip), %rdi
call _Z29__device_stub__Z6kernelPhS_jjPhS_jj
jmp .L64
.cfi_endproc
.LFE2059:
.size _Z8cuda_runv, .-_Z8cuda_runv
.section .rodata.str1.1
.LC6:
.string "_Z6kernelPhS_jj"
.LC7:
.string "_Z7kernel2PfS_P6uchar4ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2092:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPhS_jj(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kernel2PfS_P6uchar4ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl height
.data
.align 4
.type height, @object
.size height, 4
height:
.long 100
.globl width
.align 4
.type width, @object
.size width, 4
width:
.long 100
.globl sizeY
.bss
.align 4
.type sizeY, @object
.size sizeY, 4
sizeY:
.zero 4
.globl sizeX
.align 4
.type sizeX, @object
.size sizeX, 4
sizeX:
.zero 4
.globl dev_size_y
.align 8
.type dev_size_y, @object
.size dev_size_y, 8
dev_size_y:
.zero 8
.globl dev_size_x
.align 8
.type dev_size_x, @object
.size dev_size_x, 8
dev_size_x:
.zero 8
.globl dev_array2
.align 8
.type dev_array2, @object
.size dev_array2, 8
dev_array2:
.zero 8
.globl dev_array1
.align 8
.type dev_array1, @object
.size dev_array1, 8
dev_array1:
.zero 8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "life.cuda.hip"
.globl _Z22__device_stub__kernel2PfS_P15HIP_vector_typeIhLj4EEii # -- Begin function _Z22__device_stub__kernel2PfS_P15HIP_vector_typeIhLj4EEii
.p2align 4, 0x90
.type _Z22__device_stub__kernel2PfS_P15HIP_vector_typeIhLj4EEii,@function
_Z22__device_stub__kernel2PfS_P15HIP_vector_typeIhLj4EEii: # @_Z22__device_stub__kernel2PfS_P15HIP_vector_typeIhLj4EEii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7kernel2PfS_P15HIP_vector_typeIhLj4EEii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__kernel2PfS_P15HIP_vector_typeIhLj4EEii, .Lfunc_end0-_Z22__device_stub__kernel2PfS_P15HIP_vector_typeIhLj4EEii
.cfi_endproc
# -- End function
.globl _Z21__device_stub__kernelPhS_jj # -- Begin function _Z21__device_stub__kernelPhS_jj
.p2align 4, 0x90
.type _Z21__device_stub__kernelPhS_jj,@function
_Z21__device_stub__kernelPhS_jj: # @_Z21__device_stub__kernelPhS_jj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelPhS_jj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z21__device_stub__kernelPhS_jj, .Lfunc_end1-_Z21__device_stub__kernelPhS_jj
.cfi_endproc
# -- End function
.globl _Z8initCudaPhS_jj # -- Begin function _Z8initCudaPhS_jj
.p2align 4, 0x90
.type _Z8initCudaPhS_jj,@function
_Z8initCudaPhS_jj: # @_Z8initCudaPhS_jj
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $16, %rsp
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -16
movq %rdi, %rbx
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %edx, sizeX(%rip)
movl %ecx, sizeY(%rip)
movl %edx, %eax
movl %ecx, %esi
imulq %rax, %rsi
movl $dev_array1, %edi
callq hipMalloc
movl 12(%rsp), %eax
movl 8(%rsp), %esi
imulq %rax, %rsi
movl $dev_array2, %edi
callq hipMalloc
movl $dev_size_x, %edi
movl $4, %esi
callq hipMalloc
movl $dev_size_y, %edi
movl $4, %esi
callq hipMalloc
movq dev_array1(%rip), %rdi
movl 12(%rsp), %eax
movl 8(%rsp), %edx
imulq %rax, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq dev_size_x(%rip), %rdi
leaq 12(%rsp), %rsi
movl $1, %edx
movl $1, %ecx
callq hipMemcpy
movq dev_size_y(%rip), %rdi
leaq 8(%rsp), %rsi
movl $1, %edx
movl $1, %ecx
callq hipMemcpy
movq dev_array2(%rip), %rdi
movl 8(%rsp), %edx
imull 12(%rsp), %edx
xorl %esi, %esi
callq hipMemset
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z8initCudaPhS_jj, .Lfunc_end2-_Z8initCudaPhS_jj
.cfi_endproc
# -- End function
.globl _Z10get_resultPh # -- Begin function _Z10get_resultPh
.p2align 4, 0x90
.type _Z10get_resultPh,@function
_Z10get_resultPh: # @_Z10get_resultPh
.cfi_startproc
# %bb.0:
movq dev_array2(%rip), %rsi
movl sizeY(%rip), %edx
imull sizeX(%rip), %edx
movl $2, %ecx
jmp hipMemcpy # TAILCALL
.Lfunc_end3:
.size _Z10get_resultPh, .Lfunc_end3-_Z10get_resultPh
.cfi_endproc
# -- End function
.globl _Z8cuda_runv # -- Begin function _Z8cuda_runv
.p2align 4, 0x90
.type _Z8cuda_runv,@function
_Z8cuda_runv: # @_Z8cuda_runv
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl sizeY(%rip), %eax
imull sizeX(%rip), %eax
shrl $9, %eax
movabsq $4294967296, %rdx # imm = 0x100000000
leaq (%rdx,%rax), %rdi
incq %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB4_1
# %bb.2:
addq $120, %rsp
.cfi_def_cfa_offset 8
retq
.LBB4_1:
.cfi_def_cfa_offset 128
movq dev_array1(%rip), %rax
movq dev_array2(%rip), %rcx
movl sizeX(%rip), %edx
movl sizeY(%rip), %esi
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movl %edx, 12(%rsp)
movl %esi, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelPhS_jj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
addq $120, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z8cuda_runv, .Lfunc_end4-_Z8cuda_runv
.cfi_endproc
# -- End function
.globl _Z8FreeCudav # -- Begin function _Z8FreeCudav
.p2align 4, 0x90
.type _Z8FreeCudav,@function
_Z8FreeCudav: # @_Z8FreeCudav
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq dev_array1(%rip), %rdi
callq hipFree
movq dev_array2(%rip), %rdi
callq hipFree
movq dev_size_x(%rip), %rdi
callq hipFree
movq dev_size_y(%rip), %rdi
popq %rax
.cfi_def_cfa_offset 8
jmp hipFree # TAILCALL
.Lfunc_end5:
.size _Z8FreeCudav, .Lfunc_end5-_Z8FreeCudav
.cfi_endproc
# -- End function
.globl _Z5checkPhS_PjS0_ # -- Begin function _Z5checkPhS_PjS0_
.p2align 4, 0x90
.type _Z5checkPhS_PjS0_,@function
_Z5checkPhS_PjS0_: # @_Z5checkPhS_PjS0_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rcx, %rbx
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
movl $.L.str, %edi
callq puts
movl (%r14), %esi
movl (%rbx), %edx
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl $.L.str, %edi
callq puts
movl (%rbx), %ecx
movl (%r14), %eax
imull %ecx, %eax
testl %eax, %eax
je .LBB6_8
# %bb.1: # %.lr.ph.preheader
xorl %eax, %eax
jmp .LBB6_2
.p2align 4, 0x90
.LBB6_5: # in Loop: Header=BB6_2 Depth=1
xorl %ecx, %ecx
.LBB6_6: # %.sink.split
# in Loop: Header=BB6_2 Depth=1
movb %cl, (%r15,%rax)
.LBB6_7: # in Loop: Header=BB6_2 Depth=1
incq %rax
movl (%rbx), %ecx
movl (%r14), %edx
imull %ecx, %edx
cmpq %rdx, %rax
jae .LBB6_8
.LBB6_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
leaq (%r12,%rax), %rdx
xorl %esi, %esi
cmpb $1, 1(%r12,%rax)
sete %sil
leal 1(%rsi), %edi
cmpb $1, -1(%r12,%rax)
cmovnel %esi, %edi
movl %ecx, %r8d
xorl %r9d, %r9d
cmpb $1, (%r8,%rdx)
sete %r9b
movq %rdx, %rsi
subq %r8, %rsi
xorl %ecx, %ecx
cmpb $1, (%rsi)
sete %cl
addl %r9d, %ecx
addl %edi, %ecx
xorl %edi, %edi
cmpb $1, 1(%r8,%rdx)
sete %dil
xorl %r9d, %r9d
cmpb $1, -1(%r8,%rdx)
sete %r9b
addl %edi, %r9d
xorl %edi, %edi
cmpb $1, 1(%rsi)
sete %dil
addl %r9d, %edi
xorl %edx, %edx
cmpb $1, -1(%rsi)
sete %dl
addl %edi, %edx
addl %ecx, %edx
movb $1, %cl
cmpl $3, %edx
je .LBB6_6
# %bb.3: # %.lr.ph
# in Loop: Header=BB6_2 Depth=1
cmpl $2, %edx
jne .LBB6_5
# %bb.4: # in Loop: Header=BB6_2 Depth=1
cmpb $1, (%r12,%rax)
je .LBB6_6
jmp .LBB6_7
.LBB6_8: # %._crit_edge
movl $.L.str, %edi
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp puts # TAILCALL
.Lfunc_end6:
.size _Z5checkPhS_PjS0_, .Lfunc_end6-_Z5checkPhS_PjS0_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $1600, %edi # imm = 0x640
callq malloc
movq %rax, %r14
movl $1600, %edi # imm = 0x640
callq malloc
movq %rax, 16(%rsp) # 8-byte Spill
movl $1065353216, 40(%r14) # imm = 0x3F800000
movabsq $4575657222473777152, %rax # imm = 0x3F8000003F800000
movq %rax, 160(%r14)
movq %rax, 236(%r14)
movq %rax, 360(%r14)
movl $1065353216, 368(%r14) # imm = 0x3F800000
movq $-1604, %r15 # imm = 0xF9BC
movl $2938661835, %r12d # imm = 0xAF286BCB
xorl %ebp, %ebp
xorl %r13d, %r13d
jmp .LBB7_1
.p2align 4, 0x90
.LBB7_3: # in Loop: Header=BB7_1 Depth=1
decl %r13d
incl %ebp
addq $4, %r15
je .LBB7_4
.LBB7_1: # =>This Inner Loop Header: Depth=1
movl %ebp, %eax
imulq %r12, %rax
shrq $32, %rax
movl %ebp, %ecx
subl %eax, %ecx
shrl %ecx
addl %eax, %ecx
shrl $4, %ecx
leal (%rcx,%rcx,8), %eax
leal (%rcx,%rax,2), %ebx
cvttss2si 1604(%r14,%r15), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
addl %r13d, %ebx
jne .LBB7_3
# %bb.2: # in Loop: Header=BB7_1 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB7_3
.LBB7_4:
movl $10, %edi
callq putchar@PLT
leaq 32(%rsp), %rdi
movl $1600, %esi # imm = 0x640
callq hipMalloc
leaq 8(%rsp), %rdi
movl $1600, %esi # imm = 0x640
callq hipMalloc
leaq 24(%rsp), %rdi
movl $1600, %esi # imm = 0x640
callq hipMalloc
movq 32(%rsp), %rdi
movl $1600, %edx # imm = 0x640
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $1600, %edx # imm = 0x640
movl $8, %esi
callq hipMemset
movabsq $4294967306, %rdi # imm = 0x10000000A
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_6
# %bb.5:
movq 32(%rsp), %rax
movq 8(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl $20, 44(%rsp)
movl $20, 40(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 44(%rsp), %rax
movq %rax, 152(%rsp)
leaq 40(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z7kernel2PfS_P15HIP_vector_typeIhLj4EEii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_6:
movq %r14, 48(%rsp) # 8-byte Spill
movl $1600, %edi # imm = 0x640
callq malloc
movq %rax, %r15
movq 8(%rsp), %rsi
movl $1600, %edx # imm = 0x640
movq %rax, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rsi
movl $1600, %edx # imm = 0x640
movq 16(%rsp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq $-1600, %r12 # imm = 0xF9C0
movl $2938661835, %r13d # imm = 0xAF286BCB
xorl %ebp, %ebp
xorl %ebx, %ebx
jmp .LBB7_7
.p2align 4, 0x90
.LBB7_9: # in Loop: Header=BB7_7 Depth=1
decl %ebx
incl %ebp
addq $4, %r12
je .LBB7_10
.LBB7_7: # =>This Inner Loop Header: Depth=1
movl %ebp, %eax
imulq %r13, %rax
shrq $32, %rax
movl %ebp, %ecx
subl %eax, %ecx
shrl %ecx
addl %eax, %ecx
shrl $4, %ecx
leal (%rcx,%rcx,8), %eax
leal (%rcx,%rax,2), %r14d
movq 16(%rsp), %rax # 8-byte Reload
movzbl 1600(%rax,%r12), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
addl %ebx, %r14d
jne .LBB7_9
# %bb.8: # in Loop: Header=BB7_7 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB7_9
.LBB7_10:
movl $10, %edi
callq putchar@PLT
movq $-1600, %r12 # imm = 0xF9C0
movl $2938661835, %r13d # imm = 0xAF286BCB
xorl %ebp, %ebp
xorl %ebx, %ebx
jmp .LBB7_11
.p2align 4, 0x90
.LBB7_13: # in Loop: Header=BB7_11 Depth=1
decl %ebx
incl %ebp
addq $4, %r12
je .LBB7_14
.LBB7_11: # =>This Inner Loop Header: Depth=1
movl %ebp, %eax
imulq %r13, %rax
shrq $32, %rax
movl %ebp, %ecx
subl %eax, %ecx
shrl %ecx
addl %eax, %ecx
shrl $4, %ecx
leal (%rcx,%rcx,8), %eax
leal (%rcx,%rax,2), %r14d
cvttss2si 1600(%r15,%r12), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
addl %ebx, %r14d
jne .LBB7_13
# %bb.12: # in Loop: Header=BB7_11 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB7_13
.LBB7_14:
movl $10, %edi
callq putchar@PLT
movq 48(%rsp), %rdi # 8-byte Reload
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi # 8-byte Reload
callq free
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size main, .Lfunc_end7-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kernel2PfS_P15HIP_vector_typeIhLj4EEii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPhS_jj, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type dev_array1,@object # @dev_array1
.bss
.globl dev_array1
.p2align 3, 0x0
dev_array1:
.quad 0
.size dev_array1, 8
.type dev_array2,@object # @dev_array2
.globl dev_array2
.p2align 3, 0x0
dev_array2:
.quad 0
.size dev_array2, 8
.type dev_size_x,@object # @dev_size_x
.globl dev_size_x
.p2align 3, 0x0
dev_size_x:
.quad 0
.size dev_size_x, 8
.type dev_size_y,@object # @dev_size_y
.globl dev_size_y
.p2align 3, 0x0
dev_size_y:
.quad 0
.size dev_size_y, 8
.type sizeX,@object # @sizeX
.globl sizeX
.p2align 2, 0x0
sizeX:
.long 0 # 0x0
.size sizeX, 4
.type sizeY,@object # @sizeY
.globl sizeY
.p2align 2, 0x0
sizeY:
.long 0 # 0x0
.size sizeY, 4
.type _Z7kernel2PfS_P15HIP_vector_typeIhLj4EEii,@object # @_Z7kernel2PfS_P15HIP_vector_typeIhLj4EEii
.section .rodata,"a",@progbits
.globl _Z7kernel2PfS_P15HIP_vector_typeIhLj4EEii
.p2align 3, 0x0
_Z7kernel2PfS_P15HIP_vector_typeIhLj4EEii:
.quad _Z22__device_stub__kernel2PfS_P15HIP_vector_typeIhLj4EEii
.size _Z7kernel2PfS_P15HIP_vector_typeIhLj4EEii, 8
.type _Z6kernelPhS_jj,@object # @_Z6kernelPhS_jj
.globl _Z6kernelPhS_jj
.p2align 3, 0x0
_Z6kernelPhS_jj:
.quad _Z21__device_stub__kernelPhS_jj
.size _Z6kernelPhS_jj, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "<=================>\n"
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%u %u\n"
.size .L.str.1, 7
.type width,@object # @width
.data
.globl width
.p2align 2, 0x0
width:
.long 100 # 0x64
.size width, 4
.type height,@object # @height
.globl height
.p2align 2, 0x0
height:
.long 100 # 0x64
.size height, 4
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "%i"
.size .L.str.2, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%4i"
.size .L.str.4, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7kernel2PfS_P15HIP_vector_typeIhLj4EEii"
.size .L__unnamed_1, 42
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z6kernelPhS_jj"
.size .L__unnamed_2, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__kernel2PfS_P15HIP_vector_typeIhLj4EEii
.addrsig_sym _Z21__device_stub__kernelPhS_jj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym dev_array1
.addrsig_sym dev_array2
.addrsig_sym dev_size_x
.addrsig_sym dev_size_y
.addrsig_sym _Z7kernel2PfS_P15HIP_vector_typeIhLj4EEii
.addrsig_sym _Z6kernelPhS_jj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void rotateArray(int *c, int numThreads)
{
int nextIndex = (threadIdx.x + 1)%numThreads;
int val = c[nextIndex];
__syncthreads();
c[threadIdx.x] = val;
} | code for sm_80
Function : _Z11rotateArrayPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ I2F.U32.RP R4, c[0x0][0x168] ; /* 0x00005a0000047b06 */
/* 0x000e220000209000 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0030*/ ISETP.NE.U32.AND P1, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe20003f25070 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fca0000000a00 */
/*0050*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e220000001000 */
/*0060*/ IADD3 R0, R5, 0x1, RZ ; /* 0x0000000105007810 */
/* 0x002fe40007ffe0ff */
/*0070*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fe20007ffe0ff */
/*0080*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*0090*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe200078e00ff */
/*00b0*/ IADD3 R7, RZ, -R3, RZ ; /* 0x80000003ff077210 */
/* 0x002fca0007ffe0ff */
/*00c0*/ IMAD R7, R7, c[0x0][0x168], RZ ; /* 0x00005a0007077a24 */
/* 0x000fc800078e02ff */
/*00d0*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*00e0*/ IMAD.HI.U32 R3, R3, R0, RZ ; /* 0x0000000003037227 */
/* 0x000fca00078e00ff */
/*00f0*/ IADD3 R3, -R3, RZ, RZ ; /* 0x000000ff03037210 */
/* 0x000fca0007ffe1ff */
/*0100*/ IMAD R0, R3, c[0x0][0x168], R0 ; /* 0x00005a0003007a24 */
/* 0x000fca00078e0200 */
/*0110*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06070 */
/*0120*/ @P0 IADD3 R0, R0, -c[0x0][0x168], RZ ; /* 0x80005a0000000a10 */
/* 0x000fc80007ffe0ff */
/*0130*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06070 */
/*0140*/ @P0 IADD3 R0, R0, -c[0x0][0x168], RZ ; /* 0x80005a0000000a10 */
/* 0x000fe40007ffe0ff */
/*0150*/ @!P1 LOP3.LUT R0, RZ, c[0x0][0x168], RZ, 0x33, !PT ; /* 0x00005a00ff009a12 */
/* 0x000fca00078e33ff */
/*0160*/ IMAD.WIDE R2, R0, R4, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0204 */
/*0170*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0180*/ IMAD.WIDE.U32 R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fc600078e0004 */
/*0190*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01a0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void rotateArray(int *c, int numThreads)
{
int nextIndex = (threadIdx.x + 1)%numThreads;
int val = c[nextIndex];
__syncthreads();
c[threadIdx.x] = val;
} | .file "tmpxft_001a5bd6_00000000-6_rotateArray.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z11rotateArrayPiiPii
.type _Z32__device_stub__Z11rotateArrayPiiPii, @function
_Z32__device_stub__Z11rotateArrayPiiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11rotateArrayPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z11rotateArrayPiiPii, .-_Z32__device_stub__Z11rotateArrayPiiPii
.globl _Z11rotateArrayPii
.type _Z11rotateArrayPii, @function
_Z11rotateArrayPii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z11rotateArrayPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11rotateArrayPii, .-_Z11rotateArrayPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11rotateArrayPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11rotateArrayPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void rotateArray(int *c, int numThreads)
{
int nextIndex = (threadIdx.x + 1)%numThreads;
int val = c[nextIndex];
__syncthreads();
c[threadIdx.x] = val;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void rotateArray(int *c, int numThreads)
{
int nextIndex = (threadIdx.x + 1)%numThreads;
int val = c[nextIndex];
__syncthreads();
c[threadIdx.x] = val;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void rotateArray(int *c, int numThreads)
{
int nextIndex = (threadIdx.x + 1)%numThreads;
int val = c[nextIndex];
__syncthreads();
c[threadIdx.x] = val;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11rotateArrayPii
.globl _Z11rotateArrayPii
.p2align 8
.type _Z11rotateArrayPii,@function
_Z11rotateArrayPii:
s_load_b32 s2, s[0:1], 0x8
v_add_nc_u32_e32 v3, 1, v0
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v1, s2
s_sub_i32 s3, 0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s3, v1
v_mul_hi_u32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v1, v2
v_mul_hi_u32 v1, v3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v1, s2
v_sub_nc_u32_e32 v1, v3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v2, s2, v1
v_cmp_le_u32_e32 vcc_lo, s2, v1
v_dual_cndmask_b32 v1, v1, v2 :: v_dual_mov_b32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v3, s2, v1
v_cmp_le_u32_e32 vcc_lo, s2, v1
v_cndmask_b32_e32 v1, v1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
s_barrier
buffer_gl0_inv
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11rotateArrayPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 4
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11rotateArrayPii, .Lfunc_end0-_Z11rotateArrayPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11rotateArrayPii
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z11rotateArrayPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void rotateArray(int *c, int numThreads)
{
int nextIndex = (threadIdx.x + 1)%numThreads;
int val = c[nextIndex];
__syncthreads();
c[threadIdx.x] = val;
} | .text
.file "rotateArray.hip"
.globl _Z26__device_stub__rotateArrayPii # -- Begin function _Z26__device_stub__rotateArrayPii
.p2align 4, 0x90
.type _Z26__device_stub__rotateArrayPii,@function
_Z26__device_stub__rotateArrayPii: # @_Z26__device_stub__rotateArrayPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11rotateArrayPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__rotateArrayPii, .Lfunc_end0-_Z26__device_stub__rotateArrayPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11rotateArrayPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11rotateArrayPii,@object # @_Z11rotateArrayPii
.section .rodata,"a",@progbits
.globl _Z11rotateArrayPii
.p2align 3, 0x0
_Z11rotateArrayPii:
.quad _Z26__device_stub__rotateArrayPii
.size _Z11rotateArrayPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11rotateArrayPii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__rotateArrayPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11rotateArrayPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11rotateArrayPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ I2F.U32.RP R4, c[0x0][0x168] ; /* 0x00005a0000047b06 */
/* 0x000e220000209000 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0030*/ ISETP.NE.U32.AND P1, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe20003f25070 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fca0000000a00 */
/*0050*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e220000001000 */
/*0060*/ IADD3 R0, R5, 0x1, RZ ; /* 0x0000000105007810 */
/* 0x002fe40007ffe0ff */
/*0070*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fe20007ffe0ff */
/*0080*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*0090*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe200078e00ff */
/*00b0*/ IADD3 R7, RZ, -R3, RZ ; /* 0x80000003ff077210 */
/* 0x002fca0007ffe0ff */
/*00c0*/ IMAD R7, R7, c[0x0][0x168], RZ ; /* 0x00005a0007077a24 */
/* 0x000fc800078e02ff */
/*00d0*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*00e0*/ IMAD.HI.U32 R3, R3, R0, RZ ; /* 0x0000000003037227 */
/* 0x000fca00078e00ff */
/*00f0*/ IADD3 R3, -R3, RZ, RZ ; /* 0x000000ff03037210 */
/* 0x000fca0007ffe1ff */
/*0100*/ IMAD R0, R3, c[0x0][0x168], R0 ; /* 0x00005a0003007a24 */
/* 0x000fca00078e0200 */
/*0110*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06070 */
/*0120*/ @P0 IADD3 R0, R0, -c[0x0][0x168], RZ ; /* 0x80005a0000000a10 */
/* 0x000fc80007ffe0ff */
/*0130*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06070 */
/*0140*/ @P0 IADD3 R0, R0, -c[0x0][0x168], RZ ; /* 0x80005a0000000a10 */
/* 0x000fe40007ffe0ff */
/*0150*/ @!P1 LOP3.LUT R0, RZ, c[0x0][0x168], RZ, 0x33, !PT ; /* 0x00005a00ff009a12 */
/* 0x000fca00078e33ff */
/*0160*/ IMAD.WIDE R2, R0, R4, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0204 */
/*0170*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0180*/ IMAD.WIDE.U32 R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fc600078e0004 */
/*0190*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01a0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11rotateArrayPii
.globl _Z11rotateArrayPii
.p2align 8
.type _Z11rotateArrayPii,@function
_Z11rotateArrayPii:
s_load_b32 s2, s[0:1], 0x8
v_add_nc_u32_e32 v3, 1, v0
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v1, s2
s_sub_i32 s3, 0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s3, v1
v_mul_hi_u32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v1, v2
v_mul_hi_u32 v1, v3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v1, s2
v_sub_nc_u32_e32 v1, v3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v2, s2, v1
v_cmp_le_u32_e32 vcc_lo, s2, v1
v_dual_cndmask_b32 v1, v1, v2 :: v_dual_mov_b32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v3, s2, v1
v_cmp_le_u32_e32 vcc_lo, s2, v1
v_cndmask_b32_e32 v1, v1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
s_barrier
buffer_gl0_inv
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11rotateArrayPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 4
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11rotateArrayPii, .Lfunc_end0-_Z11rotateArrayPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11rotateArrayPii
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z11rotateArrayPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a5bd6_00000000-6_rotateArray.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z11rotateArrayPiiPii
.type _Z32__device_stub__Z11rotateArrayPiiPii, @function
_Z32__device_stub__Z11rotateArrayPiiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11rotateArrayPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z11rotateArrayPiiPii, .-_Z32__device_stub__Z11rotateArrayPiiPii
.globl _Z11rotateArrayPii
.type _Z11rotateArrayPii, @function
_Z11rotateArrayPii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z11rotateArrayPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11rotateArrayPii, .-_Z11rotateArrayPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11rotateArrayPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11rotateArrayPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "rotateArray.hip"
.globl _Z26__device_stub__rotateArrayPii # -- Begin function _Z26__device_stub__rotateArrayPii
.p2align 4, 0x90
.type _Z26__device_stub__rotateArrayPii,@function
_Z26__device_stub__rotateArrayPii: # @_Z26__device_stub__rotateArrayPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11rotateArrayPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__rotateArrayPii, .Lfunc_end0-_Z26__device_stub__rotateArrayPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11rotateArrayPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11rotateArrayPii,@object # @_Z11rotateArrayPii
.section .rodata,"a",@progbits
.globl _Z11rotateArrayPii
.p2align 3, 0x0
_Z11rotateArrayPii:
.quad _Z26__device_stub__rotateArrayPii
.size _Z11rotateArrayPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11rotateArrayPii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__rotateArrayPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11rotateArrayPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //#include "../include/clion_cuda.h"
#include <iostream>
#include <stdio.h>
#include <cuda_runtime.h>
__global__
void add_f(float *array) {
int k = blockIdx.x * blockDim.x + threadIdx.x;
array[k] = 10.0;
}
int main() {
int blocks = 1024;
int thread_pre_blocks = 30;
float *array_host = new float[blocks * thread_pre_blocks];
float *array_device=0;
std::cout << "before" << std::endl;
cudaMalloc((void**)&array_device, blocks * thread_pre_blocks);
add_f<<<blocks,thread_pre_blocks>>>(array_device);
cudaMemcpy(array_device, array_host, blocks * thread_pre_blocks, cudaMemcpyDeviceToHost);
for (int i(0); i < blocks * thread_pre_blocks; ++i) {
std::cout << array_host[i] << std::endl;
}
std::cout << "end" << std::endl;
cudaFree(array_device);
} | code for sm_80
Function : _Z5add_fPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R7, 0x41200000 ; /* 0x4120000000077802 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0070*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0205 */
/*0080*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //#include "../include/clion_cuda.h"
#include <iostream>
#include <stdio.h>
#include <cuda_runtime.h>
__global__
void add_f(float *array) {
int k = blockIdx.x * blockDim.x + threadIdx.x;
array[k] = 10.0;
}
int main() {
int blocks = 1024;
int thread_pre_blocks = 30;
float *array_host = new float[blocks * thread_pre_blocks];
float *array_device=0;
std::cout << "before" << std::endl;
cudaMalloc((void**)&array_device, blocks * thread_pre_blocks);
add_f<<<blocks,thread_pre_blocks>>>(array_device);
cudaMemcpy(array_device, array_host, blocks * thread_pre_blocks, cudaMemcpyDeviceToHost);
for (int i(0); i < blocks * thread_pre_blocks; ++i) {
std::cout << array_host[i] << std::endl;
}
std::cout << "end" << std::endl;
cudaFree(array_device);
} | .file "tmpxft_00053e2f_00000000-6_test_cu.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z5add_fPfPf
.type _Z24__device_stub__Z5add_fPfPf, @function
_Z24__device_stub__Z5add_fPfPf:
.LFB3694:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z5add_fPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z24__device_stub__Z5add_fPfPf, .-_Z24__device_stub__Z5add_fPfPf
.globl _Z5add_fPf
.type _Z5add_fPf, @function
_Z5add_fPf:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z5add_fPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z5add_fPf, .-_Z5add_fPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "before"
.LC1:
.string "end"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $122880, %edi
call _Znam@PLT
movq %rax, %r13
movq $0, 8(%rsp)
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 8(%rsp), %rdi
movl $30720, %esi
call cudaMalloc@PLT
movl $30, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1024, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L12:
movl $2, %ecx
movl $30720, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movq %r13, %r12
addq $122880, %r13
leaq _ZSt4cout(%rip), %r14
jmp .L17
.L21:
movq 8(%rsp), %rdi
call _Z24__device_stub__Z5add_fPfPf
jmp .L12
.L24:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L22
call _ZSt16__throw_bad_castv@PLT
.L22:
call __stack_chk_fail@PLT
.L25:
movzbl 67(%rbp), %esi
.L16:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $4, %r12
cmpq %r12, %r13
je .L23
.L17:
pxor %xmm0, %xmm0
cvtss2sd (%r12), %xmm0
movq %r14, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L24
cmpb $0, 56(%rbp)
jne .L25
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L16
.L23:
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z5add_fPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z5add_fPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //#include "../include/clion_cuda.h"
#include <iostream>
#include <stdio.h>
#include <cuda_runtime.h>
__global__
void add_f(float *array) {
int k = blockIdx.x * blockDim.x + threadIdx.x;
array[k] = 10.0;
}
int main() {
int blocks = 1024;
int thread_pre_blocks = 30;
float *array_host = new float[blocks * thread_pre_blocks];
float *array_device=0;
std::cout << "before" << std::endl;
cudaMalloc((void**)&array_device, blocks * thread_pre_blocks);
add_f<<<blocks,thread_pre_blocks>>>(array_device);
cudaMemcpy(array_device, array_host, blocks * thread_pre_blocks, cudaMemcpyDeviceToHost);
for (int i(0); i < blocks * thread_pre_blocks; ++i) {
std::cout << array_host[i] << std::endl;
}
std::cout << "end" << std::endl;
cudaFree(array_device);
} | //#include "../include/clion_cuda.h"
#include <iostream>
#include <stdio.h>
#include <hip/hip_runtime.h>
__global__
void add_f(float *array) {
int k = blockIdx.x * blockDim.x + threadIdx.x;
array[k] = 10.0;
}
int main() {
int blocks = 1024;
int thread_pre_blocks = 30;
float *array_host = new float[blocks * thread_pre_blocks];
float *array_device=0;
std::cout << "before" << std::endl;
hipMalloc((void**)&array_device, blocks * thread_pre_blocks);
add_f<<<blocks,thread_pre_blocks>>>(array_device);
hipMemcpy(array_device, array_host, blocks * thread_pre_blocks, hipMemcpyDeviceToHost);
for (int i(0); i < blocks * thread_pre_blocks; ++i) {
std::cout << array_host[i] << std::endl;
}
std::cout << "end" << std::endl;
hipFree(array_device);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //#include "../include/clion_cuda.h"
#include <iostream>
#include <stdio.h>
#include <hip/hip_runtime.h>
__global__
void add_f(float *array) {
int k = blockIdx.x * blockDim.x + threadIdx.x;
array[k] = 10.0;
}
int main() {
int blocks = 1024;
int thread_pre_blocks = 30;
float *array_host = new float[blocks * thread_pre_blocks];
float *array_device=0;
std::cout << "before" << std::endl;
hipMalloc((void**)&array_device, blocks * thread_pre_blocks);
add_f<<<blocks,thread_pre_blocks>>>(array_device);
hipMemcpy(array_device, array_host, blocks * thread_pre_blocks, hipMemcpyDeviceToHost);
for (int i(0); i < blocks * thread_pre_blocks; ++i) {
std::cout << array_host[i] << std::endl;
}
std::cout << "end" << std::endl;
hipFree(array_device);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5add_fPf
.globl _Z5add_fPf
.p2align 8
.type _Z5add_fPf,@function
_Z5add_fPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 0x41200000
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5add_fPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5add_fPf, .Lfunc_end0-_Z5add_fPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5add_fPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5add_fPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //#include "../include/clion_cuda.h"
#include <iostream>
#include <stdio.h>
#include <hip/hip_runtime.h>
__global__
void add_f(float *array) {
int k = blockIdx.x * blockDim.x + threadIdx.x;
array[k] = 10.0;
}
int main() {
int blocks = 1024;
int thread_pre_blocks = 30;
float *array_host = new float[blocks * thread_pre_blocks];
float *array_device=0;
std::cout << "before" << std::endl;
hipMalloc((void**)&array_device, blocks * thread_pre_blocks);
add_f<<<blocks,thread_pre_blocks>>>(array_device);
hipMemcpy(array_device, array_host, blocks * thread_pre_blocks, hipMemcpyDeviceToHost);
for (int i(0); i < blocks * thread_pre_blocks; ++i) {
std::cout << array_host[i] << std::endl;
}
std::cout << "end" << std::endl;
hipFree(array_device);
} | .text
.file "test_cu.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z20__device_stub__add_fPf # -- Begin function _Z20__device_stub__add_fPf
.p2align 4, 0x90
.type _Z20__device_stub__add_fPf,@function
_Z20__device_stub__add_fPf: # @_Z20__device_stub__add_fPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z5add_fPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z20__device_stub__add_fPf, .Lfunc_end0-_Z20__device_stub__add_fPf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $88, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $122880, %edi # imm = 0x1E000
callq _Znam
movq %rax, %rbx
movq $0, 8(%rsp)
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB1_17
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB1_3
# %bb.2:
movzbl 67(%r14), %eax
jmp .LBB1_4
.LBB1_3:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 8(%rsp), %rdi
movl $30720, %esi # imm = 0x7800
callq hipMalloc
movabsq $4294967326, %rdx # imm = 0x10000001E
leaq 994(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z5add_fPf, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 8(%rsp), %rdi
movl $30720, %edx # imm = 0x7800
movq %rbx, %rsi
movl $2, %ecx
callq hipMemcpy
xorl %r15d, %r15d
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_15: # in Loop: Header=BB1_7 Depth=1
movq %r14, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB1_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit26
# in Loop: Header=BB1_7 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r15
cmpq $30720, %r15 # imm = 0x7800
je .LBB1_10
.LBB1_7: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_17
# %bb.8: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i23
# in Loop: Header=BB1_7 Depth=1
cmpb $0, 56(%r14)
je .LBB1_15
# %bb.9: # in Loop: Header=BB1_7 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB1_16
.LBB1_10:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $3, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_17
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i18
cmpb $0, 56(%rbx)
je .LBB1_13
# %bb.12:
movzbl 67(%rbx), %eax
jmp .LBB1_14
.LBB1_13:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit21
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_17:
.cfi_def_cfa_offset 128
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5add_fPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5add_fPf,@object # @_Z5add_fPf
.section .rodata,"a",@progbits
.globl _Z5add_fPf
.p2align 3, 0x0
_Z5add_fPf:
.quad _Z20__device_stub__add_fPf
.size _Z5add_fPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "before"
.size .L.str, 7
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "end"
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5add_fPf"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__add_fPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5add_fPf
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5add_fPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R7, 0x41200000 ; /* 0x4120000000077802 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0070*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0205 */
/*0080*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5add_fPf
.globl _Z5add_fPf
.p2align 8
.type _Z5add_fPf,@function
_Z5add_fPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 0x41200000
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5add_fPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5add_fPf, .Lfunc_end0-_Z5add_fPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5add_fPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5add_fPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00053e2f_00000000-6_test_cu.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z5add_fPfPf
.type _Z24__device_stub__Z5add_fPfPf, @function
_Z24__device_stub__Z5add_fPfPf:
.LFB3694:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z5add_fPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z24__device_stub__Z5add_fPfPf, .-_Z24__device_stub__Z5add_fPfPf
.globl _Z5add_fPf
.type _Z5add_fPf, @function
_Z5add_fPf:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z5add_fPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z5add_fPf, .-_Z5add_fPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "before"
.LC1:
.string "end"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $122880, %edi
call _Znam@PLT
movq %rax, %r13
movq $0, 8(%rsp)
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 8(%rsp), %rdi
movl $30720, %esi
call cudaMalloc@PLT
movl $30, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1024, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L12:
movl $2, %ecx
movl $30720, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movq %r13, %r12
addq $122880, %r13
leaq _ZSt4cout(%rip), %r14
jmp .L17
.L21:
movq 8(%rsp), %rdi
call _Z24__device_stub__Z5add_fPfPf
jmp .L12
.L24:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L22
call _ZSt16__throw_bad_castv@PLT
.L22:
call __stack_chk_fail@PLT
.L25:
movzbl 67(%rbp), %esi
.L16:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $4, %r12
cmpq %r12, %r13
je .L23
.L17:
pxor %xmm0, %xmm0
cvtss2sd (%r12), %xmm0
movq %r14, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L24
cmpb $0, 56(%rbp)
jne .L25
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L16
.L23:
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z5add_fPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z5add_fPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test_cu.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z20__device_stub__add_fPf # -- Begin function _Z20__device_stub__add_fPf
.p2align 4, 0x90
.type _Z20__device_stub__add_fPf,@function
_Z20__device_stub__add_fPf: # @_Z20__device_stub__add_fPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z5add_fPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z20__device_stub__add_fPf, .Lfunc_end0-_Z20__device_stub__add_fPf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $88, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $122880, %edi # imm = 0x1E000
callq _Znam
movq %rax, %rbx
movq $0, 8(%rsp)
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB1_17
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB1_3
# %bb.2:
movzbl 67(%r14), %eax
jmp .LBB1_4
.LBB1_3:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 8(%rsp), %rdi
movl $30720, %esi # imm = 0x7800
callq hipMalloc
movabsq $4294967326, %rdx # imm = 0x10000001E
leaq 994(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z5add_fPf, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 8(%rsp), %rdi
movl $30720, %edx # imm = 0x7800
movq %rbx, %rsi
movl $2, %ecx
callq hipMemcpy
xorl %r15d, %r15d
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_15: # in Loop: Header=BB1_7 Depth=1
movq %r14, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB1_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit26
# in Loop: Header=BB1_7 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r15
cmpq $30720, %r15 # imm = 0x7800
je .LBB1_10
.LBB1_7: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_17
# %bb.8: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i23
# in Loop: Header=BB1_7 Depth=1
cmpb $0, 56(%r14)
je .LBB1_15
# %bb.9: # in Loop: Header=BB1_7 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB1_16
.LBB1_10:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $3, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_17
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i18
cmpb $0, 56(%rbx)
je .LBB1_13
# %bb.12:
movzbl 67(%rbx), %eax
jmp .LBB1_14
.LBB1_13:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit21
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_17:
.cfi_def_cfa_offset 128
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5add_fPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5add_fPf,@object # @_Z5add_fPf
.section .rodata,"a",@progbits
.globl _Z5add_fPf
.p2align 3, 0x0
_Z5add_fPf:
.quad _Z20__device_stub__add_fPf
.size _Z5add_fPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "before"
.size .L.str, 7
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "end"
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5add_fPf"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__add_fPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5add_fPf
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void toOneChannel(unsigned char *data, int width, int height, int components)
{
int column = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
if (row >= height || column >= width)
return;
unsigned char * threadData = data + (components * (column + row * width));
for (int i = 0; i < components - 1; i++)
{
threadData[i] = 0;
}
} | code for sm_80
Function : _Z12toOneChannelPhiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x16c], PT ; /* 0x00005b0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x168], P0 ; /* 0x00005a0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe400078e00ff */
/*00b0*/ IMAD R0, R3, c[0x0][0x168], R0 ; /* 0x00005a0003007a24 */
/* 0x000fc600078e0200 */
/*00c0*/ ISETP.GE.AND P0, PT, R2, 0x2, PT ; /* 0x000000020200780c */
/* 0x000fda0003f06270 */
/*00d0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00e0*/ IADD3 R3, R2, -0x2, RZ ; /* 0xfffffffe02037810 */
/* 0x000fe20007ffe0ff */
/*00f0*/ IMAD R0, R0, c[0x0][0x170], RZ ; /* 0x00005c0000007a24 */
/* 0x000fe200078e02ff */
/*0100*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe20007ffe0ff */
/*0110*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0120*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe20003f06070 */
/*0130*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*0140*/ LOP3.LUT R4, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302047812 */
/* 0x000fe400078ec0ff */
/*0150*/ SHF.R.S32.HI R7, RZ, 0x1f, R0 ; /* 0x0000001fff077819 */
/* 0x000fd20000011400 */
/*0160*/ @!P0 BRA 0x5b0 ; /* 0x0000044000008947 */
/* 0x000fea0003800000 */
/*0170*/ IADD3 R6, -R4, c[0x0][0x170], RZ ; /* 0x00005c0004067a10 */
/* 0x000fe20007ffe1ff */
/*0180*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*0190*/ IADD3 R2, P1, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fe40007f3e0ff */
/*01a0*/ ISETP.GT.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe40003f04270 */
/*01b0*/ IADD3 R2, P2, R2, 0x3, RZ ; /* 0x0000000302027810 */
/* 0x000fc80007f5e0ff */
/*01c0*/ IADD3.X R3, RZ, c[0x0][0x164], R7, P2, P1 ; /* 0x00005900ff037a10 */
/* 0x000fce00017e2407 */
/*01d0*/ @!P0 BRA 0x4f0 ; /* 0x0000031000008947 */
/* 0x000fea0003800000 */
/*01e0*/ IADD3 R8, R6, -0x1, RZ ; /* 0xffffffff06087810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*0200*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fda0003f24270 */
/*0210*/ @!P1 BRA 0x3b0 ; /* 0x0000019000009947 */
/* 0x000fea0003800000 */
/*0220*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0230*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fe20007ffe0ff */
/*0240*/ STG.E.U8 [R2.64+-0x3], RZ ; /* 0xfffffdff02007986 */
/* 0x000fe2000c101104 */
/*0250*/ IADD3 R8, P2, R2, 0x10, RZ ; /* 0x0000001002087810 */
/* 0x000fe40007f5e0ff */
/*0260*/ ISETP.GT.AND P1, PT, R6, 0xd, PT ; /* 0x0000000d0600780c */
/* 0x000fe20003f24270 */
/*0270*/ STG.E.U8 [R2.64+-0x2], RZ ; /* 0xfffffeff02007986 */
/* 0x000fe2000c101104 */
/*0280*/ IADD3 R5, R5, 0x10, RZ ; /* 0x0000001005057810 */
/* 0x000fe20007ffe0ff */
/*0290*/ IMAD.X R9, RZ, RZ, R3, P2 ; /* 0x000000ffff097224 */
/* 0x000fe400010e0603 */
/*02a0*/ STG.E.U8 [R2.64+-0x1], RZ ; /* 0xffffffff02007986 */
/* 0x000fe8000c101104 */
/*02b0*/ STG.E.U8 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe8000c101104 */
/*02c0*/ STG.E.U8 [R2.64+0x1], RZ ; /* 0x000001ff02007986 */
/* 0x000fe8000c101104 */
/*02d0*/ STG.E.U8 [R2.64+0x2], RZ ; /* 0x000002ff02007986 */
/* 0x000fe8000c101104 */
/*02e0*/ STG.E.U8 [R2.64+0x3], RZ ; /* 0x000003ff02007986 */
/* 0x000fe8000c101104 */
/*02f0*/ STG.E.U8 [R2.64+0x4], RZ ; /* 0x000004ff02007986 */
/* 0x000fe8000c101104 */
/*0300*/ STG.E.U8 [R2.64+0x5], RZ ; /* 0x000005ff02007986 */
/* 0x000fe8000c101104 */
/*0310*/ STG.E.U8 [R2.64+0x6], RZ ; /* 0x000006ff02007986 */
/* 0x000fe8000c101104 */
/*0320*/ STG.E.U8 [R2.64+0x7], RZ ; /* 0x000007ff02007986 */
/* 0x000fe8000c101104 */
/*0330*/ STG.E.U8 [R2.64+0x8], RZ ; /* 0x000008ff02007986 */
/* 0x000fe8000c101104 */
/*0340*/ STG.E.U8 [R2.64+0x9], RZ ; /* 0x000009ff02007986 */
/* 0x000fe8000c101104 */
/*0350*/ STG.E.U8 [R2.64+0xa], RZ ; /* 0x00000aff02007986 */
/* 0x000fe8000c101104 */
/*0360*/ STG.E.U8 [R2.64+0xb], RZ ; /* 0x00000bff02007986 */
/* 0x000fe8000c101104 */
/*0370*/ STG.E.U8 [R2.64+0xc], RZ ; /* 0x00000cff02007986 */
/* 0x0001e4000c101104 */
/*0380*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0008 */
/*0390*/ IMAD.MOV.U32 R3, RZ, RZ, R9 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0009 */
/*03a0*/ @P1 BRA 0x230 ; /* 0xfffffe8000001947 */
/* 0x000fea000383ffff */
/*03b0*/ IADD3 R8, R6, -0x1, RZ ; /* 0xffffffff06087810 */
/* 0x000fc80007ffe0ff */
/*03c0*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*03d0*/ @!P1 BRA 0x4d0 ; /* 0x000000f000009947 */
/* 0x000fea0003800000 */
/*03e0*/ IADD3 R8, P1, R2, 0x8, RZ ; /* 0x0000000802087810 */
/* 0x000fe20007f3e0ff */
/*03f0*/ STG.E.U8 [R2.64+-0x3], RZ ; /* 0xfffffdff02007986 */
/* 0x000fe2000c101104 */
/*0400*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0410*/ IADD3 R5, R5, 0x8, RZ ; /* 0x0000000805057810 */
/* 0x000fe20007ffe0ff */
/*0420*/ IMAD.X R9, RZ, RZ, R3, P1 ; /* 0x000000ffff097224 */
/* 0x000fe200008e0603 */
/*0430*/ STG.E.U8 [R2.64+-0x2], RZ ; /* 0xfffffeff02007986 */
/* 0x000fe2000c101104 */
/*0440*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fc60007ffe0ff */
/*0450*/ STG.E.U8 [R2.64+-0x1], RZ ; /* 0xffffffff02007986 */
/* 0x000fe8000c101104 */
/*0460*/ STG.E.U8 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe8000c101104 */
/*0470*/ STG.E.U8 [R2.64+0x1], RZ ; /* 0x000001ff02007986 */
/* 0x000fe8000c101104 */
/*0480*/ STG.E.U8 [R2.64+0x2], RZ ; /* 0x000002ff02007986 */
/* 0x000fe8000c101104 */
/*0490*/ STG.E.U8 [R2.64+0x3], RZ ; /* 0x000003ff02007986 */
/* 0x000fe8000c101104 */
/*04a0*/ STG.E.U8 [R2.64+0x4], RZ ; /* 0x000004ff02007986 */
/* 0x0001e4000c101104 */
/*04b0*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0008 */
/*04c0*/ IMAD.MOV.U32 R3, RZ, RZ, R9 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0009 */
/*04d0*/ ISETP.NE.OR P0, PT, R6, 0x1, P0 ; /* 0x000000010600780c */
/* 0x000fda0000705670 */
/*04e0*/ @!P0 BRA 0x5b0 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*04f0*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fe20007ffe0ff */
/*0500*/ STG.E.U8 [R2.64+-0x3], RZ ; /* 0xfffffdff02007986 */
/* 0x000fe2000c101104 */
/*0510*/ IADD3 R8, P1, R2, 0x4, RZ ; /* 0x0000000402087810 */
/* 0x000fe40007f3e0ff */
/*0520*/ ISETP.NE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe20003f05270 */
/*0530*/ STG.E.U8 [R2.64+-0x2], RZ ; /* 0xfffffeff02007986 */
/* 0x000fe2000c101104 */
/*0540*/ IADD3 R5, R5, 0x4, RZ ; /* 0x0000000405057810 */
/* 0x000fe20007ffe0ff */
/*0550*/ IMAD.X R9, RZ, RZ, R3, P1 ; /* 0x000000ffff097224 */
/* 0x000fe400008e0603 */
/*0560*/ STG.E.U8 [R2.64+-0x1], RZ ; /* 0xffffffff02007986 */
/* 0x000fe8000c101104 */
/*0570*/ STG.E.U8 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e4000c101104 */
/*0580*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0008 */
/*0590*/ IMAD.MOV.U32 R3, RZ, RZ, R9 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0009 */
/*05a0*/ @P0 BRA 0x4f0 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*05b0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*05c0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*05d0*/ IADD3 R2, P0, P1, R5, c[0x0][0x160], R0 ; /* 0x0000580005027a10 */
/* 0x000fe4000791e000 */
/*05e0*/ SHF.R.S32.HI R0, RZ, 0x1f, R5 ; /* 0x0000001fff007819 */
/* 0x000fc80000011405 */
/*05f0*/ IADD3.X R3, R0, c[0x0][0x164], R7, P0, P1 ; /* 0x0000590000037a10 */
/* 0x000fc800007e2407 */
/*0600*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe20007ffe0ff */
/*0610*/ STG.E.U8 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e6000c101104 */
/*0620*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f05270 */
/*0630*/ IADD3 R2, P1, R2, 0x1, RZ ; /* 0x0000000102027810 */
/* 0x001fca0007f3e0ff */
/*0640*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fcc00008e0603 */
/*0650*/ @P0 BRA 0x600 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*0660*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0670*/ BRA 0x670; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void toOneChannel(unsigned char *data, int width, int height, int components)
{
int column = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
if (row >= height || column >= width)
return;
unsigned char * threadData = data + (components * (column + row * width));
for (int i = 0; i < components - 1; i++)
{
threadData[i] = 0;
}
} | .file "tmpxft_00056bc3_00000000-6_toOneChannel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z12toOneChannelPhiiiPhiii
.type _Z35__device_stub__Z12toOneChannelPhiiiPhiii, @function
_Z35__device_stub__Z12toOneChannelPhiiiPhiii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12toOneChannelPhiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z12toOneChannelPhiiiPhiii, .-_Z35__device_stub__Z12toOneChannelPhiiiPhiii
.globl _Z12toOneChannelPhiii
.type _Z12toOneChannelPhiii, @function
_Z12toOneChannelPhiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z12toOneChannelPhiiiPhiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12toOneChannelPhiii, .-_Z12toOneChannelPhiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12toOneChannelPhiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12toOneChannelPhiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void toOneChannel(unsigned char *data, int width, int height, int components)
{
int column = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
if (row >= height || column >= width)
return;
unsigned char * threadData = data + (components * (column + row * width));
for (int i = 0; i < components - 1; i++)
{
threadData[i] = 0;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void toOneChannel(unsigned char *data, int width, int height, int components)
{
int column = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
if (row >= height || column >= width)
return;
unsigned char * threadData = data + (components * (column + row * width));
for (int i = 0; i < components - 1; i++)
{
threadData[i] = 0;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void toOneChannel(unsigned char *data, int width, int height, int components)
{
int column = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
if (row >= height || column >= width)
return;
unsigned char * threadData = data + (components * (column + row * width));
for (int i = 0; i < components - 1; i++)
{
threadData[i] = 0;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12toOneChannelPhiii
.globl _Z12toOneChannelPhiii
.p2align 8
.type _Z12toOneChannelPhiii,@function
_Z12toOneChannelPhiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x8
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s15, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s5, v0
v_cmp_gt_i32_e64 s2, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_4
s_load_b32 s2, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 2
s_cbranch_scc1 .LBB0_4
s_load_b64 s[0:1], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v0, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v0, v2, s2
v_mov_b32_e32 v2, 0
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_add_i32 s0, s2, -1
.LBB0_3:
global_store_b8 v[0:1], v2, off
v_add_co_u32 v0, vcc_lo, v0, 1
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_add_i32 s0, s0, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s0, 0
s_cbranch_scc1 .LBB0_3
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12toOneChannelPhiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12toOneChannelPhiii, .Lfunc_end0-_Z12toOneChannelPhiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12toOneChannelPhiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12toOneChannelPhiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void toOneChannel(unsigned char *data, int width, int height, int components)
{
int column = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
if (row >= height || column >= width)
return;
unsigned char * threadData = data + (components * (column + row * width));
for (int i = 0; i < components - 1; i++)
{
threadData[i] = 0;
}
} | .text
.file "toOneChannel.hip"
.globl _Z27__device_stub__toOneChannelPhiii # -- Begin function _Z27__device_stub__toOneChannelPhiii
.p2align 4, 0x90
.type _Z27__device_stub__toOneChannelPhiii,@function
_Z27__device_stub__toOneChannelPhiii: # @_Z27__device_stub__toOneChannelPhiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12toOneChannelPhiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__toOneChannelPhiii, .Lfunc_end0-_Z27__device_stub__toOneChannelPhiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12toOneChannelPhiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12toOneChannelPhiii,@object # @_Z12toOneChannelPhiii
.section .rodata,"a",@progbits
.globl _Z12toOneChannelPhiii
.p2align 3, 0x0
_Z12toOneChannelPhiii:
.quad _Z27__device_stub__toOneChannelPhiii
.size _Z12toOneChannelPhiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12toOneChannelPhiii"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__toOneChannelPhiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12toOneChannelPhiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12toOneChannelPhiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x16c], PT ; /* 0x00005b0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x168], P0 ; /* 0x00005a0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe400078e00ff */
/*00b0*/ IMAD R0, R3, c[0x0][0x168], R0 ; /* 0x00005a0003007a24 */
/* 0x000fc600078e0200 */
/*00c0*/ ISETP.GE.AND P0, PT, R2, 0x2, PT ; /* 0x000000020200780c */
/* 0x000fda0003f06270 */
/*00d0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00e0*/ IADD3 R3, R2, -0x2, RZ ; /* 0xfffffffe02037810 */
/* 0x000fe20007ffe0ff */
/*00f0*/ IMAD R0, R0, c[0x0][0x170], RZ ; /* 0x00005c0000007a24 */
/* 0x000fe200078e02ff */
/*0100*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe20007ffe0ff */
/*0110*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0120*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe20003f06070 */
/*0130*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*0140*/ LOP3.LUT R4, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302047812 */
/* 0x000fe400078ec0ff */
/*0150*/ SHF.R.S32.HI R7, RZ, 0x1f, R0 ; /* 0x0000001fff077819 */
/* 0x000fd20000011400 */
/*0160*/ @!P0 BRA 0x5b0 ; /* 0x0000044000008947 */
/* 0x000fea0003800000 */
/*0170*/ IADD3 R6, -R4, c[0x0][0x170], RZ ; /* 0x00005c0004067a10 */
/* 0x000fe20007ffe1ff */
/*0180*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*0190*/ IADD3 R2, P1, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fe40007f3e0ff */
/*01a0*/ ISETP.GT.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe40003f04270 */
/*01b0*/ IADD3 R2, P2, R2, 0x3, RZ ; /* 0x0000000302027810 */
/* 0x000fc80007f5e0ff */
/*01c0*/ IADD3.X R3, RZ, c[0x0][0x164], R7, P2, P1 ; /* 0x00005900ff037a10 */
/* 0x000fce00017e2407 */
/*01d0*/ @!P0 BRA 0x4f0 ; /* 0x0000031000008947 */
/* 0x000fea0003800000 */
/*01e0*/ IADD3 R8, R6, -0x1, RZ ; /* 0xffffffff06087810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*0200*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fda0003f24270 */
/*0210*/ @!P1 BRA 0x3b0 ; /* 0x0000019000009947 */
/* 0x000fea0003800000 */
/*0220*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0230*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fe20007ffe0ff */
/*0240*/ STG.E.U8 [R2.64+-0x3], RZ ; /* 0xfffffdff02007986 */
/* 0x000fe2000c101104 */
/*0250*/ IADD3 R8, P2, R2, 0x10, RZ ; /* 0x0000001002087810 */
/* 0x000fe40007f5e0ff */
/*0260*/ ISETP.GT.AND P1, PT, R6, 0xd, PT ; /* 0x0000000d0600780c */
/* 0x000fe20003f24270 */
/*0270*/ STG.E.U8 [R2.64+-0x2], RZ ; /* 0xfffffeff02007986 */
/* 0x000fe2000c101104 */
/*0280*/ IADD3 R5, R5, 0x10, RZ ; /* 0x0000001005057810 */
/* 0x000fe20007ffe0ff */
/*0290*/ IMAD.X R9, RZ, RZ, R3, P2 ; /* 0x000000ffff097224 */
/* 0x000fe400010e0603 */
/*02a0*/ STG.E.U8 [R2.64+-0x1], RZ ; /* 0xffffffff02007986 */
/* 0x000fe8000c101104 */
/*02b0*/ STG.E.U8 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe8000c101104 */
/*02c0*/ STG.E.U8 [R2.64+0x1], RZ ; /* 0x000001ff02007986 */
/* 0x000fe8000c101104 */
/*02d0*/ STG.E.U8 [R2.64+0x2], RZ ; /* 0x000002ff02007986 */
/* 0x000fe8000c101104 */
/*02e0*/ STG.E.U8 [R2.64+0x3], RZ ; /* 0x000003ff02007986 */
/* 0x000fe8000c101104 */
/*02f0*/ STG.E.U8 [R2.64+0x4], RZ ; /* 0x000004ff02007986 */
/* 0x000fe8000c101104 */
/*0300*/ STG.E.U8 [R2.64+0x5], RZ ; /* 0x000005ff02007986 */
/* 0x000fe8000c101104 */
/*0310*/ STG.E.U8 [R2.64+0x6], RZ ; /* 0x000006ff02007986 */
/* 0x000fe8000c101104 */
/*0320*/ STG.E.U8 [R2.64+0x7], RZ ; /* 0x000007ff02007986 */
/* 0x000fe8000c101104 */
/*0330*/ STG.E.U8 [R2.64+0x8], RZ ; /* 0x000008ff02007986 */
/* 0x000fe8000c101104 */
/*0340*/ STG.E.U8 [R2.64+0x9], RZ ; /* 0x000009ff02007986 */
/* 0x000fe8000c101104 */
/*0350*/ STG.E.U8 [R2.64+0xa], RZ ; /* 0x00000aff02007986 */
/* 0x000fe8000c101104 */
/*0360*/ STG.E.U8 [R2.64+0xb], RZ ; /* 0x00000bff02007986 */
/* 0x000fe8000c101104 */
/*0370*/ STG.E.U8 [R2.64+0xc], RZ ; /* 0x00000cff02007986 */
/* 0x0001e4000c101104 */
/*0380*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0008 */
/*0390*/ IMAD.MOV.U32 R3, RZ, RZ, R9 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0009 */
/*03a0*/ @P1 BRA 0x230 ; /* 0xfffffe8000001947 */
/* 0x000fea000383ffff */
/*03b0*/ IADD3 R8, R6, -0x1, RZ ; /* 0xffffffff06087810 */
/* 0x000fc80007ffe0ff */
/*03c0*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*03d0*/ @!P1 BRA 0x4d0 ; /* 0x000000f000009947 */
/* 0x000fea0003800000 */
/*03e0*/ IADD3 R8, P1, R2, 0x8, RZ ; /* 0x0000000802087810 */
/* 0x000fe20007f3e0ff */
/*03f0*/ STG.E.U8 [R2.64+-0x3], RZ ; /* 0xfffffdff02007986 */
/* 0x000fe2000c101104 */
/*0400*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0410*/ IADD3 R5, R5, 0x8, RZ ; /* 0x0000000805057810 */
/* 0x000fe20007ffe0ff */
/*0420*/ IMAD.X R9, RZ, RZ, R3, P1 ; /* 0x000000ffff097224 */
/* 0x000fe200008e0603 */
/*0430*/ STG.E.U8 [R2.64+-0x2], RZ ; /* 0xfffffeff02007986 */
/* 0x000fe2000c101104 */
/*0440*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fc60007ffe0ff */
/*0450*/ STG.E.U8 [R2.64+-0x1], RZ ; /* 0xffffffff02007986 */
/* 0x000fe8000c101104 */
/*0460*/ STG.E.U8 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe8000c101104 */
/*0470*/ STG.E.U8 [R2.64+0x1], RZ ; /* 0x000001ff02007986 */
/* 0x000fe8000c101104 */
/*0480*/ STG.E.U8 [R2.64+0x2], RZ ; /* 0x000002ff02007986 */
/* 0x000fe8000c101104 */
/*0490*/ STG.E.U8 [R2.64+0x3], RZ ; /* 0x000003ff02007986 */
/* 0x000fe8000c101104 */
/*04a0*/ STG.E.U8 [R2.64+0x4], RZ ; /* 0x000004ff02007986 */
/* 0x0001e4000c101104 */
/*04b0*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0008 */
/*04c0*/ IMAD.MOV.U32 R3, RZ, RZ, R9 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0009 */
/*04d0*/ ISETP.NE.OR P0, PT, R6, 0x1, P0 ; /* 0x000000010600780c */
/* 0x000fda0000705670 */
/*04e0*/ @!P0 BRA 0x5b0 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*04f0*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fe20007ffe0ff */
/*0500*/ STG.E.U8 [R2.64+-0x3], RZ ; /* 0xfffffdff02007986 */
/* 0x000fe2000c101104 */
/*0510*/ IADD3 R8, P1, R2, 0x4, RZ ; /* 0x0000000402087810 */
/* 0x000fe40007f3e0ff */
/*0520*/ ISETP.NE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe20003f05270 */
/*0530*/ STG.E.U8 [R2.64+-0x2], RZ ; /* 0xfffffeff02007986 */
/* 0x000fe2000c101104 */
/*0540*/ IADD3 R5, R5, 0x4, RZ ; /* 0x0000000405057810 */
/* 0x000fe20007ffe0ff */
/*0550*/ IMAD.X R9, RZ, RZ, R3, P1 ; /* 0x000000ffff097224 */
/* 0x000fe400008e0603 */
/*0560*/ STG.E.U8 [R2.64+-0x1], RZ ; /* 0xffffffff02007986 */
/* 0x000fe8000c101104 */
/*0570*/ STG.E.U8 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e4000c101104 */
/*0580*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0008 */
/*0590*/ IMAD.MOV.U32 R3, RZ, RZ, R9 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0009 */
/*05a0*/ @P0 BRA 0x4f0 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*05b0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*05c0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*05d0*/ IADD3 R2, P0, P1, R5, c[0x0][0x160], R0 ; /* 0x0000580005027a10 */
/* 0x000fe4000791e000 */
/*05e0*/ SHF.R.S32.HI R0, RZ, 0x1f, R5 ; /* 0x0000001fff007819 */
/* 0x000fc80000011405 */
/*05f0*/ IADD3.X R3, R0, c[0x0][0x164], R7, P0, P1 ; /* 0x0000590000037a10 */
/* 0x000fc800007e2407 */
/*0600*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe20007ffe0ff */
/*0610*/ STG.E.U8 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e6000c101104 */
/*0620*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f05270 */
/*0630*/ IADD3 R2, P1, R2, 0x1, RZ ; /* 0x0000000102027810 */
/* 0x001fca0007f3e0ff */
/*0640*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fcc00008e0603 */
/*0650*/ @P0 BRA 0x600 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*0660*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0670*/ BRA 0x670; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12toOneChannelPhiii
.globl _Z12toOneChannelPhiii
.p2align 8
.type _Z12toOneChannelPhiii,@function
_Z12toOneChannelPhiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x8
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s15, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s5, v0
v_cmp_gt_i32_e64 s2, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_4
s_load_b32 s2, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 2
s_cbranch_scc1 .LBB0_4
s_load_b64 s[0:1], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v0, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v0, v2, s2
v_mov_b32_e32 v2, 0
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_add_i32 s0, s2, -1
.LBB0_3:
global_store_b8 v[0:1], v2, off
v_add_co_u32 v0, vcc_lo, v0, 1
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_add_i32 s0, s0, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s0, 0
s_cbranch_scc1 .LBB0_3
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12toOneChannelPhiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12toOneChannelPhiii, .Lfunc_end0-_Z12toOneChannelPhiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12toOneChannelPhiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12toOneChannelPhiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00056bc3_00000000-6_toOneChannel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z12toOneChannelPhiiiPhiii
.type _Z35__device_stub__Z12toOneChannelPhiiiPhiii, @function
_Z35__device_stub__Z12toOneChannelPhiiiPhiii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12toOneChannelPhiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z12toOneChannelPhiiiPhiii, .-_Z35__device_stub__Z12toOneChannelPhiiiPhiii
.globl _Z12toOneChannelPhiii
.type _Z12toOneChannelPhiii, @function
_Z12toOneChannelPhiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z12toOneChannelPhiiiPhiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12toOneChannelPhiii, .-_Z12toOneChannelPhiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12toOneChannelPhiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12toOneChannelPhiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "toOneChannel.hip"
.globl _Z27__device_stub__toOneChannelPhiii # -- Begin function _Z27__device_stub__toOneChannelPhiii
.p2align 4, 0x90
.type _Z27__device_stub__toOneChannelPhiii,@function
_Z27__device_stub__toOneChannelPhiii: # @_Z27__device_stub__toOneChannelPhiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12toOneChannelPhiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__toOneChannelPhiii, .Lfunc_end0-_Z27__device_stub__toOneChannelPhiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12toOneChannelPhiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12toOneChannelPhiii,@object # @_Z12toOneChannelPhiii
.section .rodata,"a",@progbits
.globl _Z12toOneChannelPhiii
.p2align 3, 0x0
_Z12toOneChannelPhiii:
.quad _Z27__device_stub__toOneChannelPhiii
.size _Z12toOneChannelPhiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12toOneChannelPhiii"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__toOneChannelPhiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12toOneChannelPhiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //xfail:BOOGIE_ERROR
//--blockDim=32 --gridDim=64 --no-inline
//error: possible write-write race on
#include <stdio.h>
#include "cuda.h"
#include <assert.h>
#define M 2//32
#define N 4//64
__global__ void foo(int* p) {
__shared__ unsigned char x[N];
for (unsigned int i=0; i<(N/4); i++) {
((unsigned int*)x)[i] = 1;//0;
}
/*
for (int i = 0; i < N/4; i++) {
p[i] = x[i];
}
*/
} | code for sm_80
Function : _Z3fooPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
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