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You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
// 相关 CUDA 库 #include "cuda_runtime.h" #include "cuda.h" #include "device_launch_parameters.h" #include <iostream> #include <stdio.h> using namespace std; const int N = 100; // 块数 const int BLOCK_data = 3; // 各块中的线程数 const int THREAD_data = 10; // CUDA初始化函数 bool InitCUDA() { int deviceCount; // 获取显示设备数 cudaGetDeviceCount (&deviceCount); if (deviceCount == 0) { cout << "找不到设备" << endl; return EXIT_FAILURE; } int i; for (i=0; i<deviceCount; i++) { cudaDeviceProp prop; if (cudaGetDeviceProperties(&prop,i)==cudaSuccess) // 获取设备属性 { if (prop.major>=1) //cuda计算能力 { break; } } } if (i==deviceCount) { cout << "找不到支持 CUDA 计算的设备" << endl; return EXIT_FAILURE; } cudaSetDevice(i); // 选定使用的显示设备 return EXIT_SUCCESS; } // 此函数在主机端调用，设备端执行。 __global__ static void Sum (int *data,int *result) { // 取得线程号 const int tid = threadIdx.x; // 获得块号 const int bid = blockIdx.x; int sum = 0; // 有点像网格计算的思路 for (int i=bid*THREAD_data+tid; i<N; i+=BLOCK_data*THREAD_data) { sum += data[i]; } // result 数组存放各个线程的计算结果 result[bid*THREAD_data+tid] = sum; } int main () { // 初始化 CUDA 编译环境 if (InitCUDA()) { return EXIT_FAILURE; } cout << "成功建立 CUDA 计算环境" << endl << endl; // 建立，初始化，打印测试数组 int *data = new int [N]; cout << "测试矩阵: " << endl; for (int i=0; i<N; i++) { data[i] = rand()%10; cout << data[i] << " "; if ((i+1)%10 == 0) cout << endl; } cout << endl; int *gpudata, *result; // 在显存中为计算对象开辟空间 cudaMalloc ((void**)&gpudata, sizeof(int)*N); // 在显存中为结果对象开辟空间 cudaMalloc ((void**)&result, sizeof(int)*BLOCK_data*THREAD_data); // 将数组数据传输进显存 cudaMemcpy (gpudata, data, sizeof(int)*N, cudaMemcpyHostToDevice); // 调用 kernel 函数 - 此函数可以根据显存地址以及自身的块号，线程号处理数据。 Sum<<<BLOCK_data,THREAD_data,0>>> (gpudata,result); // 在内存中为计算对象开辟空间 int *sumArray = new int[THREAD_data*BLOCK_data]; // 从显存获取处理的结果 cudaMemcpy (sumArray, result, sizeof(int)*THREAD_data*BLOCK_data, cudaMemcpyDeviceToHost); // 释放显存 cudaFree (gpudata); cudaFree (result); // 计算 GPU 每个线程计算出来和的总和 int final_sum=0; for (int i=0; i<THREAD_data*BLOCK_data; i++) { final_sum += sumArray[i]; } cout << "GPU 求和结果为: " << final_sum << endl; // 使用 CPU 对矩阵进行求和并将结果对照 final_sum = 0; for (int i=0; i<N; i++) { final_sum += data[i]; } cout << "CPU 求和结果为: " << final_sum << endl; return 0; }
.file "tmpxft_000da7c6_00000000-6_array_sum.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .type _ZL3SumPiS_, @function _ZL3SumPiS_: .LFB3696: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax movq %rdi, (%rsp) movq %rsi, 8(%rsp) movq %rsp, %rax movq %rax, 80(%rsp) leaq 8(%rsp), %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L5 .L1: movq 104(%rsp), %rax subq %fs:40, %rax jne .L6 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L5: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _ZL3SumPiS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L1 .L6: call __stack_chk_fail@PLT .cfi_endproc .LFE3696: .size _ZL3SumPiS_, .-_ZL3SumPiS_ .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3673: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3673: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "\346\211\276\344\270\215\345\210\260\350\256\276\345\244\207" .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC1: .string "\346\211\276\344\270\215\345\210\260\346\224\257\346\214\201 CUDA \350\256\241\347\256\227\347\232\204\350\256\276\345\244\207" .text .globl _Z8InitCUDAv .type _Z8InitCUDAv, @function _Z8InitCUDAv: .LFB3669: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $1064, %rsp .cfi_def_cfa_offset 1088 movq %fs:40, %rax movq %rax, 1048(%rsp) xorl %eax, %eax leaq 12(%rsp), %rdi call cudaGetDeviceCount@PLT movl 12(%rsp), %eax testl %eax, %eax je .L30 movl $0, %ebx leaq 16(%rsp), %rbp jg .L18 jmp .L20 .L30: movl $15, %edx leaq .LC0(%rip), %rsi leaq _ZSt4cout(%rip), %rbx movq %rbx, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %rbx testq %rbx, %rbx je .L31 cmpb $0, 56(%rbx) je .L13 movzbl 67(%rbx), %eax .L14: movsbl %al, %esi leaq _ZSt4cout(%rip), %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT movl $1, %eax jmp .L9 .L31: movq 1048(%rsp), %rax subq %fs:40, %rax jne .L32 call _ZSt16__throw_bad_castv@PLT .L32: call __stack_chk_fail@PLT .L13: movq %rbx, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq (%rbx), %rax movl $10, %esi movq %rbx, %rdi call *48(%rax) jmp .L14 .L16: addl $1, %ebx cmpl %ebx, 12(%rsp) jle .L19 .L18: movl %ebx, %esi movq %rbp, %rdi call cudaGetDeviceProperties_v2@PLT testl %eax, %eax jne .L16 cmpl $0, 376(%rsp) jle .L16 .L19: cmpl %ebx, 12(%rsp) je .L33 .L20: movl %ebx, %edi call cudaSetDevice@PLT movl $0, %eax .L9: movq 1048(%rsp), %rdx subq %fs:40, %rdx jne .L34 addq $1064, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L33: .cfi_restore_state movl $36, %edx leaq .LC1(%rip), %rsi leaq _ZSt4cout(%rip), %rbx movq %rbx, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %rbx testq %rbx, %rbx je .L35 cmpb $0, 56(%rbx) je .L23 movzbl 67(%rbx), %esi .L24: movsbl %sil, %esi leaq _ZSt4cout(%rip), %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT movl $1, %eax jmp .L9 .L35: movq 1048(%rsp), %rax subq %fs:40, %rax jne .L36 call _ZSt16__throw_bad_castv@PLT .L36: call __stack_chk_fail@PLT .L23: movq %rbx, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq (%rbx), %rax movl $10, %esi movq %rbx, %rdi call *48(%rax) movl %eax, %esi jmp .L24 .L34: call __stack_chk_fail@PLT .cfi_endproc .LFE3669: .size _Z8InitCUDAv, .-_Z8InitCUDAv .section .rodata.str1.8 .align 8 .LC2: .string "\346\210\220\345\212\237\345\273\272\347\253\213 CUDA \350\256\241\347\256\227\347\216\257\345\242\203" .section .rodata.str1.1 .LC3: .string "\346\265\213\350\257\225\347\237\251\351\230\265: " .LC4: .string " " .LC5: .string "GPU \346\261\202\345\222\214\347\273\223\346\236\234\344\270\272: " .LC6: .string "CPU \346\261\202\345\222\214\347\273\223\346\236\234\344\270\272: " .text .globl main .type main, @function main: .LFB3670: .cfi_startproc endbr64 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 subq $48, %rsp .cfi_def_cfa_offset 96 movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax call _Z8InitCUDAv movl %eax, %edx movl $1, %eax testb %dl, %dl je .L54 .L37: movq 40(%rsp), %rdx subq %fs:40, %rdx jne .L55 addq $48, %rsp .cfi_remember_state .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .L54: .cfi_restore_state leaq .LC2(%rip), %rsi leaq _ZSt4cout(%rip), %rbx movq %rbx, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movl $400, %edi call _Znam@PLT movq %rax, %rbp leaq .LC3(%rip), %rsi movq %rbx, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movl $1, %ebx leaq _ZSt4cout(%rip), %r12 leaq .LC4(%rip), %r13 jmp .L44 .L58: movq 40(%rsp), %rax subq %fs:40, %rax jne .L56 call _ZSt16__throw_bad_castv@PLT .L56: call __stack_chk_fail@PLT .L42: movq %r14, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq (%r14), %rax movl $10, %esi movq %r14, %rdi call *48(%rax) movl %eax, %esi .L43: movsbl %sil, %esi movq %r12, %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT .L39: addq $1, %rbx cmpq $101, %rbx je .L57 .L44: call rand@PLT movslq %eax, %rsi imulq $1717986919, %rsi, %rsi sarq $34, %rsi cltd subl %edx, %esi leal (%rsi,%rsi,4), %edx addl %edx, %edx subl %edx, %eax movl %eax, %esi movl %eax, -4(%rbp,%rbx,4) movq %r12, %rdi call _ZNSolsEi@PLT movq %rax, %rdi movl $1, %edx movq %r13, %rsi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movslq %ebx, %rax imulq $1717986919, %rax, %rax sarq $34, %rax movl %ebx, %edx sarl $31, %edx subl %edx, %eax leal (%rax,%rax,4), %eax addl %eax, %eax cmpl %ebx, %eax jne .L39 movq (%r12), %rax movq -24(%rax), %rax movq 240(%r12,%rax), %r14 testq %r14, %r14 je .L58 cmpb $0, 56(%r14) je .L42 movzbl 67(%r14), %esi jmp .L43 .L57: leaq _ZSt4cout(%rip), %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movq %rsp, %rdi movl $400, %esi call cudaMalloc@PLT leaq 8(%rsp), %rdi movl $120, %esi call cudaMalloc@PLT movl $1, %ecx movl $400, %edx movq %rbp, %rsi movq (%rsp), %rdi call cudaMemcpy@PLT movl $10, 28(%rsp) movl $1, 32(%rsp) movl $3, 16(%rsp) movl $1, 20(%rsp) movl $0, %r9d movl $0, %r8d movq 28(%rsp), %rdx movl $1, %ecx movq 16(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L59 .L45: movl $120, %edi call _Znam@PLT movq %rax, %rbx movl $2, %ecx movl $120, %edx movq 8(%rsp), %rsi movq %rax, %rdi call cudaMemcpy@PLT movq (%rsp), %rdi call cudaFree@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq %rbx, %rax leaq 120(%rbx), %rcx movl $0, %edx .L46: movl %edx, %ebx addl (%rax), %ebx movl %ebx, %edx addq $4, %rax cmpq %rcx, %rax jne .L46 leaq .LC5(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi movl %ebx, %esi call _ZNSolsEi@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movq %rbp, %rax addq $400, %rbp movl $0, %edx .L47: movl %edx, %ebx addl (%rax), %ebx movl %ebx, %edx addq $4, %rax cmpq %rax, %rbp jne .L47 leaq .LC6(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi movl %ebx, %esi call _ZNSolsEi@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movl $0, %eax jmp .L37 .L59: movq 8(%rsp), %rsi movq (%rsp), %rdi call _ZL3SumPiS_ jmp .L45 .L55: call __stack_chk_fail@PLT .cfi_endproc .LFE3670: .size main, .-main .section .rodata.str1.1 .LC7: .string "_Z3SumPiS_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3698: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC7(%rip), %rdx movq %rdx, %rcx leaq _ZL3SumPiS_(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3698: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
// 相关 CUDA 库 #include "cuda_runtime.h" #include "cuda.h" #include "device_launch_parameters.h" #include <iostream> #include <stdio.h> using namespace std; const int N = 100; // 块数 const int BLOCK_data = 3; // 各块中的线程数 const int THREAD_data = 10; // CUDA初始化函数 bool InitCUDA() { int deviceCount; // 获取显示设备数 cudaGetDeviceCount (&deviceCount); if (deviceCount == 0) { cout << "找不到设备" << endl; return EXIT_FAILURE; } int i; for (i=0; i<deviceCount; i++) { cudaDeviceProp prop; if (cudaGetDeviceProperties(&prop,i)==cudaSuccess) // 获取设备属性 { if (prop.major>=1) //cuda计算能力 { break; } } } if (i==deviceCount) { cout << "找不到支持 CUDA 计算的设备" << endl; return EXIT_FAILURE; } cudaSetDevice(i); // 选定使用的显示设备 return EXIT_SUCCESS; } // 此函数在主机端调用，设备端执行。 __global__ static void Sum (int *data,int *result) { // 取得线程号 const int tid = threadIdx.x; // 获得块号 const int bid = blockIdx.x; int sum = 0; // 有点像网格计算的思路 for (int i=bid*THREAD_data+tid; i<N; i+=BLOCK_data*THREAD_data) { sum += data[i]; } // result 数组存放各个线程的计算结果 result[bid*THREAD_data+tid] = sum; } int main () { // 初始化 CUDA 编译环境 if (InitCUDA()) { return EXIT_FAILURE; } cout << "成功建立 CUDA 计算环境" << endl << endl; // 建立，初始化，打印测试数组 int *data = new int [N]; cout << "测试矩阵: " << endl; for (int i=0; i<N; i++) { data[i] = rand()%10; cout << data[i] << " "; if ((i+1)%10 == 0) cout << endl; } cout << endl; int *gpudata, *result; // 在显存中为计算对象开辟空间 cudaMalloc ((void**)&gpudata, sizeof(int)*N); // 在显存中为结果对象开辟空间 cudaMalloc ((void**)&result, sizeof(int)*BLOCK_data*THREAD_data); // 将数组数据传输进显存 cudaMemcpy (gpudata, data, sizeof(int)*N, cudaMemcpyHostToDevice); // 调用 kernel 函数 - 此函数可以根据显存地址以及自身的块号，线程号处理数据。 Sum<<<BLOCK_data,THREAD_data,0>>> (gpudata,result); // 在内存中为计算对象开辟空间 int *sumArray = new int[THREAD_data*BLOCK_data]; // 从显存获取处理的结果 cudaMemcpy (sumArray, result, sizeof(int)*THREAD_data*BLOCK_data, cudaMemcpyDeviceToHost); // 释放显存 cudaFree (gpudata); cudaFree (result); // 计算 GPU 每个线程计算出来和的总和 int final_sum=0; for (int i=0; i<THREAD_data*BLOCK_data; i++) { final_sum += sumArray[i]; } cout << "GPU 求和结果为: " << final_sum << endl; // 使用 CPU 对矩阵进行求和并将结果对照 final_sum = 0; for (int i=0; i<N; i++) { final_sum += data[i]; } cout << "CPU 求和结果为: " << final_sum << endl; return 0; }
// 相关 CUDA 库 #include "hip/hip_runtime.h" #include <iostream> #include <stdio.h> using namespace std; const int N = 100; // 块数 const int BLOCK_data = 3; // 各块中的线程数 const int THREAD_data = 10; // CUDA初始化函数 bool InitCUDA() { int deviceCount; // 获取显示设备数 hipGetDeviceCount (&deviceCount); if (deviceCount == 0) { cout << "找不到设备" << endl; return EXIT_FAILURE; } int i; for (i=0; i<deviceCount; i++) { hipDeviceProp_t prop; if (hipGetDeviceProperties(&prop,i)==hipSuccess) // 获取设备属性 { if (prop.major>=1) //cuda计算能力 { break; } } } if (i==deviceCount) { cout << "找不到支持 CUDA 计算的设备" << endl; return EXIT_FAILURE; } hipSetDevice(i); // 选定使用的显示设备 return EXIT_SUCCESS; } // 此函数在主机端调用，设备端执行。 __global__ static void Sum (int *data,int *result) { // 取得线程号 const int tid = threadIdx.x; // 获得块号 const int bid = blockIdx.x; int sum = 0; // 有点像网格计算的思路 for (int i=bid*THREAD_data+tid; i<N; i+=BLOCK_data*THREAD_data) { sum += data[i]; } // result 数组存放各个线程的计算结果 result[bid*THREAD_data+tid] = sum; } int main () { // 初始化 CUDA 编译环境 if (InitCUDA()) { return EXIT_FAILURE; } cout << "成功建立 CUDA 计算环境" << endl << endl; // 建立，初始化，打印测试数组 int *data = new int [N]; cout << "测试矩阵: " << endl; for (int i=0; i<N; i++) { data[i] = rand()%10; cout << data[i] << " "; if ((i+1)%10 == 0) cout << endl; } cout << endl; int *gpudata, *result; // 在显存中为计算对象开辟空间 hipMalloc ((void**)&gpudata, sizeof(int)*N); // 在显存中为结果对象开辟空间 hipMalloc ((void**)&result, sizeof(int)*BLOCK_data*THREAD_data); // 将数组数据传输进显存 hipMemcpy (gpudata, data, sizeof(int)*N, hipMemcpyHostToDevice); // 调用 kernel 函数 - 此函数可以根据显存地址以及自身的块号，线程号处理数据。 Sum<<<BLOCK_data,THREAD_data,0>>> (gpudata,result); // 在内存中为计算对象开辟空间 int *sumArray = new int[THREAD_data*BLOCK_data]; // 从显存获取处理的结果 hipMemcpy (sumArray, result, sizeof(int)*THREAD_data*BLOCK_data, hipMemcpyDeviceToHost); // 释放显存 hipFree (gpudata); hipFree (result); // 计算 GPU 每个线程计算出来和的总和 int final_sum=0; for (int i=0; i<THREAD_data*BLOCK_data; i++) { final_sum += sumArray[i]; } cout << "GPU 求和结果为: " << final_sum << endl; // 使用 CPU 对矩阵进行求和并将结果对照 final_sum = 0; for (int i=0; i<N; i++) { final_sum += data[i]; } cout << "CPU 求和结果为: " << final_sum << endl; return 0; }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
// 相关 CUDA 库 #include "hip/hip_runtime.h" #include <iostream> #include <stdio.h> using namespace std; const int N = 100; // 块数 const int BLOCK_data = 3; // 各块中的线程数 const int THREAD_data = 10; // CUDA初始化函数 bool InitCUDA() { int deviceCount; // 获取显示设备数 hipGetDeviceCount (&deviceCount); if (deviceCount == 0) { cout << "找不到设备" << endl; return EXIT_FAILURE; } int i; for (i=0; i<deviceCount; i++) { hipDeviceProp_t prop; if (hipGetDeviceProperties(&prop,i)==hipSuccess) // 获取设备属性 { if (prop.major>=1) //cuda计算能力 { break; } } } if (i==deviceCount) { cout << "找不到支持 CUDA 计算的设备" << endl; return EXIT_FAILURE; } hipSetDevice(i); // 选定使用的显示设备 return EXIT_SUCCESS; } // 此函数在主机端调用，设备端执行。 __global__ static void Sum (int *data,int *result) { // 取得线程号 const int tid = threadIdx.x; // 获得块号 const int bid = blockIdx.x; int sum = 0; // 有点像网格计算的思路 for (int i=bid*THREAD_data+tid; i<N; i+=BLOCK_data*THREAD_data) { sum += data[i]; } // result 数组存放各个线程的计算结果 result[bid*THREAD_data+tid] = sum; } int main () { // 初始化 CUDA 编译环境 if (InitCUDA()) { return EXIT_FAILURE; } cout << "成功建立 CUDA 计算环境" << endl << endl; // 建立，初始化，打印测试数组 int *data = new int [N]; cout << "测试矩阵: " << endl; for (int i=0; i<N; i++) { data[i] = rand()%10; cout << data[i] << " "; if ((i+1)%10 == 0) cout << endl; } cout << endl; int *gpudata, *result; // 在显存中为计算对象开辟空间 hipMalloc ((void**)&gpudata, sizeof(int)*N); // 在显存中为结果对象开辟空间 hipMalloc ((void**)&result, sizeof(int)*BLOCK_data*THREAD_data); // 将数组数据传输进显存 hipMemcpy (gpudata, data, sizeof(int)*N, hipMemcpyHostToDevice); // 调用 kernel 函数 - 此函数可以根据显存地址以及自身的块号，线程号处理数据。 Sum<<<BLOCK_data,THREAD_data,0>>> (gpudata,result); // 在内存中为计算对象开辟空间 int *sumArray = new int[THREAD_data*BLOCK_data]; // 从显存获取处理的结果 hipMemcpy (sumArray, result, sizeof(int)*THREAD_data*BLOCK_data, hipMemcpyDeviceToHost); // 释放显存 hipFree (gpudata); hipFree (result); // 计算 GPU 每个线程计算出来和的总和 int final_sum=0; for (int i=0; i<THREAD_data*BLOCK_data; i++) { final_sum += sumArray[i]; } cout << "GPU 求和结果为: " << final_sum << endl; // 使用 CPU 对矩阵进行求和并将结果对照 final_sum = 0; for (int i=0; i<N; i++) { final_sum += data[i]; } cout << "CPU 求和结果为: " << final_sum << endl; return 0; }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .section .text._ZL3SumPiS_,"axG",@progbits,_ZL3SumPiS_,comdat .globl _ZL3SumPiS_ .p2align 8 .type _ZL3SumPiS_,@function _ZL3SumPiS_: s_mul_i32 s15, s15, 10 s_mov_b32 s3, exec_lo v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v1, s15, v0 s_delay_alu instid0(VALU_DEP_1) v_cmpx_gt_i32_e32 0x64, v1 s_cbranch_execz .LBB0_4 s_load_b64 s[4:5], s[0:1], 0x0 s_ashr_i32 s2, s15, 31 v_add_co_u32 v2, s6, s15, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_add_co_ci_u32_e64 v3, null, s2, 0, s6 v_add3_u32 v0, v0, s15, 0xffffffe2 v_mov_b32_e32 v4, 0 v_lshlrev_b64 v[2:3], 2, v[2:3] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v2, vcc_lo, s4, v2 v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo s_mov_b32 s4, 0 .LBB0_2: global_load_b32 v5, v[2:3], off v_add_nc_u32_e32 v0, 30, v0 v_add_co_u32 v2, vcc_lo, v2, 0x78 v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_lt_i32_e64 s2, 0x45, v0 s_or_b32 s4, s2, s4 s_waitcnt vmcnt(0) v_add_nc_u32_e32 v4, v5, v4 s_and_not1_b32 exec_lo, exec_lo, s4 s_cbranch_execnz .LBB0_2 s_or_b32 exec_lo, exec_lo, s4 .LBB0_4: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) s_or_b32 exec_lo, exec_lo, s3 s_load_b64 s[0:1], s[0:1], 0x8 v_ashrrev_i32_e32 v2, 31, v1 v_lshlrev_b64 v[0:1], 2, v[1:2] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, s0, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo global_store_b32 v[0:1], v4, off s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _ZL3SumPiS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 16 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 6 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .section .text._ZL3SumPiS_,"axG",@progbits,_ZL3SumPiS_,comdat .Lfunc_end0: .size _ZL3SumPiS_, .Lfunc_end0-_ZL3SumPiS_ .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 16 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _ZL3SumPiS_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _ZL3SumPiS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 6 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
// 相关 CUDA 库 #include "hip/hip_runtime.h" #include <iostream> #include <stdio.h> using namespace std; const int N = 100; // 块数 const int BLOCK_data = 3; // 各块中的线程数 const int THREAD_data = 10; // CUDA初始化函数 bool InitCUDA() { int deviceCount; // 获取显示设备数 hipGetDeviceCount (&deviceCount); if (deviceCount == 0) { cout << "找不到设备" << endl; return EXIT_FAILURE; } int i; for (i=0; i<deviceCount; i++) { hipDeviceProp_t prop; if (hipGetDeviceProperties(&prop,i)==hipSuccess) // 获取设备属性 { if (prop.major>=1) //cuda计算能力 { break; } } } if (i==deviceCount) { cout << "找不到支持 CUDA 计算的设备" << endl; return EXIT_FAILURE; } hipSetDevice(i); // 选定使用的显示设备 return EXIT_SUCCESS; } // 此函数在主机端调用，设备端执行。 __global__ static void Sum (int *data,int *result) { // 取得线程号 const int tid = threadIdx.x; // 获得块号 const int bid = blockIdx.x; int sum = 0; // 有点像网格计算的思路 for (int i=bid*THREAD_data+tid; i<N; i+=BLOCK_data*THREAD_data) { sum += data[i]; } // result 数组存放各个线程的计算结果 result[bid*THREAD_data+tid] = sum; } int main () { // 初始化 CUDA 编译环境 if (InitCUDA()) { return EXIT_FAILURE; } cout << "成功建立 CUDA 计算环境" << endl << endl; // 建立，初始化，打印测试数组 int *data = new int [N]; cout << "测试矩阵: " << endl; for (int i=0; i<N; i++) { data[i] = rand()%10; cout << data[i] << " "; if ((i+1)%10 == 0) cout << endl; } cout << endl; int *gpudata, *result; // 在显存中为计算对象开辟空间 hipMalloc ((void**)&gpudata, sizeof(int)*N); // 在显存中为结果对象开辟空间 hipMalloc ((void**)&result, sizeof(int)*BLOCK_data*THREAD_data); // 将数组数据传输进显存 hipMemcpy (gpudata, data, sizeof(int)*N, hipMemcpyHostToDevice); // 调用 kernel 函数 - 此函数可以根据显存地址以及自身的块号，线程号处理数据。 Sum<<<BLOCK_data,THREAD_data,0>>> (gpudata,result); // 在内存中为计算对象开辟空间 int *sumArray = new int[THREAD_data*BLOCK_data]; // 从显存获取处理的结果 hipMemcpy (sumArray, result, sizeof(int)*THREAD_data*BLOCK_data, hipMemcpyDeviceToHost); // 释放显存 hipFree (gpudata); hipFree (result); // 计算 GPU 每个线程计算出来和的总和 int final_sum=0; for (int i=0; i<THREAD_data*BLOCK_data; i++) { final_sum += sumArray[i]; } cout << "GPU 求和结果为: " << final_sum << endl; // 使用 CPU 对矩阵进行求和并将结果对照 final_sum = 0; for (int i=0; i<N; i++) { final_sum += data[i]; } cout << "CPU 求和结果为: " << final_sum << endl; return 0; }
.text .file "array_sum.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z8InitCUDAv # -- Begin function _Z8InitCUDAv .p2align 4, 0x90 .type _Z8InitCUDAv,@function _Z8InitCUDAv: # @_Z8InitCUDAv .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 subq $1480, %rsp # imm = 0x5C8 .cfi_def_cfa_offset 1504 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 leaq 4(%rsp), %rdi callq hipGetDeviceCount cmpl $0, 4(%rsp) je .LBB0_10 # %bb.1: # %.preheader cmpl $0, 4(%rsp) jle .LBB0_15 # %bb.2: # %.lr.ph xorl %ebx, %ebx leaq 8(%rsp), %r14 jmp .LBB0_4 .p2align 4, 0x90 .LBB0_3: # in Loop: Header=BB0_4 Depth=1 incl %ebx cmpl 4(%rsp), %ebx jge .LBB0_6 .LBB0_4: # =>This Inner Loop Header: Depth=1 movq %r14, %rdi movl %ebx, %esi callq hipGetDevicePropertiesR0600 testl %eax, %eax jne .LBB0_3 # %bb.5: # in Loop: Header=BB0_4 Depth=1 cmpl $0, 368(%rsp) jle .LBB0_3 .LBB0_6: # %._crit_edge cmpl 4(%rsp), %ebx jne .LBB0_16 .LBB0_7: movl $_ZSt4cout, %edi movl $.L.str.1, %esi movl $36, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %rbx testq %rbx, %rbx je .LBB0_18 # %bb.8: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i11 cmpb $0, 56(%rbx) jne .LBB0_12 .LBB0_13: movq %rbx, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%rbx), %rax movq %rbx, %rdi movl $10, %esi callq *48(%rax) jmp .LBB0_14 .LBB0_10: movl $_ZSt4cout, %edi movl $.L.str, %esi movl $15, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %rbx testq %rbx, %rbx je .LBB0_18 # %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i cmpb $0, 56(%rbx) je .LBB0_13 .LBB0_12: movzbl 67(%rbx), %eax .LBB0_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movb $1, %al jmp .LBB0_17 .LBB0_15: xorl %ebx, %ebx cmpl 4(%rsp), %ebx je .LBB0_7 .LBB0_16: movl %ebx, %edi callq hipSetDevice xorl %eax, %eax .LBB0_17: # kill: def $al killed $al killed $eax addq $1480, %rsp # imm = 0x5C8 .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .LBB0_18: .cfi_def_cfa_offset 1504 callq _ZSt16__throw_bad_castv .Lfunc_end0: .size _Z8InitCUDAv, .Lfunc_end0-_Z8InitCUDAv .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $96, %rsp .cfi_def_cfa_offset 144 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl $1, %ebx callq _Z8InitCUDAv testb %al, %al jne .LBB1_40 # %bb.1: movl $_ZSt4cout, %edi movl $.L.str.2, %esi movl $30, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %rbx testq %rbx, %rbx je .LBB1_41 # %bb.2: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i cmpb $0, 56(%rbx) je .LBB1_4 # %bb.3: movzbl 67(%rbx), %eax jmp .LBB1_5 .LBB1_4: movq %rbx, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%rbx), %rax movq %rbx, %rdi movl $10, %esi callq *48(%rax) .LBB1_5: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movq (%rax), %rcx movq -24(%rcx), %rcx movq 240(%rax,%rcx), %rbx testq %rbx, %rbx je .LBB1_41 # %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i28 cmpb $0, 56(%rbx) je .LBB1_8 # %bb.7: movzbl 67(%rbx), %ecx jmp .LBB1_9 .LBB1_8: movq %rbx, %rdi movq %rax, %r14 callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%rbx), %rax movq %rbx, %rdi movl $10, %esi callq *48(%rax) movl %eax, %ecx movq %r14, %rax .LBB1_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit31 movsbl %cl, %esi movq %rax, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $400, %edi # imm = 0x190 callq _Znam movq %rax, %rbx movl $_ZSt4cout, %edi movl $.L.str.3, %esi movl $14, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %r14 testq %r14, %r14 je .LBB1_41 # %bb.10: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i33 cmpb $0, 56(%r14) je .LBB1_12 # %bb.11: movzbl 67(%r14), %eax jmp .LBB1_13 .LBB1_12: movq %r14, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r14), %rax movq %r14, %rdi movl $10, %esi callq *48(%rax) .LBB1_13: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit36 movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $1, %ebp xorl %r15d, %r15d movl $3435973837, %r12d # imm = 0xCCCCCCCD jmp .LBB1_14 .LBB1_29: # in Loop: Header=BB1_14 Depth=1 movq %r14, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r14), %rax movq %r14, %rdi movl $10, %esi callq *48(%rax) .LBB1_30: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit46 # in Loop: Header=BB1_14 Depth=1 movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv .LBB1_31: # in Loop: Header=BB1_14 Depth=1 incq %r15 incl %ebp cmpq $100, %r15 je .LBB1_18 .LBB1_14: # =>This Inner Loop Header: Depth=1 movl %ebp, %eax imulq %r12, %rax shrq $35, %rax leal (%rax,%rax,4), %eax leal -1(,%rax,2), %r14d callq rand movslq %eax, %rsi imulq $1717986919, %rsi, %rax # imm = 0x66666667 movq %rax, %rcx shrq $63, %rcx sarq $34, %rax addl %ecx, %eax addl %eax, %eax leal (%rax,%rax,4), %eax subl %eax, %esi movl %esi, (%rbx,%r15,4) movl $_ZSt4cout, %edi # kill: def $esi killed $esi killed $rsi callq _ZNSolsEi movl $.L.str.4, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l cmpl %r15d, %r14d jne .LBB1_31 # %bb.15: # in Loop: Header=BB1_14 Depth=1 movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %r14 testq %r14, %r14 je .LBB1_41 # %bb.16: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i43 # in Loop: Header=BB1_14 Depth=1 cmpb $0, 56(%r14) je .LBB1_29 # %bb.17: # in Loop: Header=BB1_14 Depth=1 movzbl 67(%r14), %eax jmp .LBB1_30 .LBB1_18: movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %r14 testq %r14, %r14 je .LBB1_41 # %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i38 cmpb $0, 56(%r14) je .LBB1_21 # %bb.20: movzbl 67(%r14), %eax jmp .LBB1_22 .LBB1_21: movq %r14, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r14), %rax movq %r14, %rdi movl $10, %esi callq *48(%rax) .LBB1_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit41 movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv leaq 8(%rsp), %rdi movl $400, %esi # imm = 0x190 callq hipMalloc movq %rsp, %rdi movl $120, %esi callq hipMalloc movq 8(%rsp), %rdi movl $400, %edx # imm = 0x190 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy movabsq $4294967299, %rdi # imm = 0x100000003 leaq 7(%rdi), %rdx xorl %r14d, %r14d movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_24 # %bb.23: movq 8(%rsp), %rax movq (%rsp), %rcx movq %rax, 72(%rsp) movq %rcx, 64(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_ZL3SumPiS_, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_24: movl $120, %edi callq _Znam movq %rax, %r15 movq (%rsp), %rsi movl $120, %edx movq %rax, %rdi movl $2, %ecx callq hipMemcpy movq 8(%rsp), %rdi callq hipFree movq (%rsp), %rdi callq hipFree xorl %eax, %eax .p2align 4, 0x90 .LBB1_25: # =>This Inner Loop Header: Depth=1 addl (%r15,%rax,4), %r14d incq %rax cmpq $30, %rax jne .LBB1_25 # %bb.26: movl $_ZSt4cout, %edi movl $.L.str.5, %esi movl $21, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cout, %edi movl %r14d, %esi callq _ZNSolsEi movq (%rax), %rcx movq -24(%rcx), %rcx movq 240(%rax,%rcx), %r14 testq %r14, %r14 je .LBB1_41 # %bb.27: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i48 cmpb $0, 56(%r14) je .LBB1_32 # %bb.28: movzbl 67(%r14), %ecx jmp .LBB1_33 .LBB1_32: movq %r14, %rdi movq %rax, %r15 callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r14), %rax movq %r14, %rdi movl $10, %esi callq *48(%rax) movl %eax, %ecx movq %r15, %rax .LBB1_33: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit51 movsbl %cl, %esi movq %rax, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv xorl %eax, %eax xorl %ebp, %ebp .p2align 4, 0x90 .LBB1_34: # =>This Inner Loop Header: Depth=1 addl (%rbx,%rax,4), %ebp incq %rax cmpq $100, %rax jne .LBB1_34 # %bb.35: movl $_ZSt4cout, %edi movl $.L.str.6, %esi movl $21, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cout, %edi movl %ebp, %esi callq _ZNSolsEi movq (%rax), %rcx movq -24(%rcx), %rcx movq 240(%rax,%rcx), %rbx testq %rbx, %rbx je .LBB1_41 # %bb.36: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i53 cmpb $0, 56(%rbx) je .LBB1_38 # %bb.37: movzbl 67(%rbx), %ecx jmp .LBB1_39 .LBB1_38: movq %rbx, %rdi movq %rax, %r14 callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%rbx), %rax movq %rbx, %rdi movl $10, %esi callq *48(%rax) movl %eax, %ecx movq %r14, %rax .LBB1_39: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit56 movsbl %cl, %esi movq %rax, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv xorl %ebx, %ebx .LBB1_40: movl %ebx, %eax addq $96, %rsp .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB1_41: .cfi_def_cfa_offset 144 callq _ZSt16__throw_bad_castv .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function _ZL18__device_stub__SumPiS_ .type _ZL18__device_stub__SumPiS_,@function _ZL18__device_stub__SumPiS_: # @_ZL18__device_stub__SumPiS_ .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_ZL3SumPiS_, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end2: .size _ZL18__device_stub__SumPiS_, .Lfunc_end2-_ZL18__device_stub__SumPiS_ .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_ZL3SumPiS_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "\346\211\276\344\270\215\345\210\260\350\256\276\345\244\207" .size .L.str, 16 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "\346\211\276\344\270\215\345\210\260\346\224\257\346\214\201 CUDA \350\256\241\347\256\227\347\232\204\350\256\276\345\244\207" .size .L.str.1, 37 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "\346\210\220\345\212\237\345\273\272\347\253\213 CUDA \350\256\241\347\256\227\347\216\257\345\242\203" .size .L.str.2, 31 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "\346\265\213\350\257\225\347\237\251\351\230\265: " .size .L.str.3, 15 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz " " .size .L.str.4, 2 .type _ZL3SumPiS_,@object # @_ZL3SumPiS_ .section .rodata,"a",@progbits .p2align 3, 0x0 _ZL3SumPiS_: .quad _ZL18__device_stub__SumPiS_ .size _ZL3SumPiS_, 8 .type .L.str.5,@object # @.str.5 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.5: .asciz "GPU \346\261\202\345\222\214\347\273\223\346\236\234\344\270\272: " .size .L.str.5, 22 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "CPU \346\261\202\345\222\214\347\273\223\346\236\234\344\270\272: " .size .L.str.6, 22 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_ZL3SumPiS_" .size .L__unnamed_1, 12 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _ZL18__device_stub__SumPiS_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _ZSt4cout .addrsig_sym _ZL3SumPiS_ .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z3SumPiS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */ /* 0x000e220000002500 */ /*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fe20000000a00 */ /*0030*/ BSSY B2, 0x7e0 ; /* 0x000007a000027945 */ /* 0x000fe20003800000 */ /*0040*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */ /* 0x000fe200078e00ff */ /*0050*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */ /* 0x000e240000002100 */ /*0060*/ IMAD R0, R3, 0xa, R4 ; /* 0x0000000a03007824 */ /* 0x001fca00078e0204 */ /*0070*/ ISETP.GT.AND P0, PT, R0, 0x63, PT ; /* 0x000000630000780c */ /* 0x000fda0003f04270 */ /*0080*/ @P0 BRA 0x7d0 ; /* 0x0000074000000947 */ /* 0x000fea0003800000 */ /*0090*/ IMNMX R2, R0, 0x46, !PT ; /* 0x0000004600027817 */ /* 0x000fe20007800200 */ /*00a0*/ BSSY B1, 0x700 ; /* 0x0000065000017945 */ /* 0x000fe20003800000 */ /*00b0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */ /* 0x000fe400078e00ff */ /*00c0*/ IADD3 R2, -R4, 0x1d, R2 ; /* 0x0000001d04027810 */ /* 0x000fe20007ffe102 */ /*00d0*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */ /* 0x000fc800078e0000 */ /*00e0*/ IMAD R4, R3, -0xa, R2 ; /* 0xfffffff603047824 */ /* 0x000fc800078e0202 */ /*00f0*/ IMAD.WIDE.U32 R2, R4.reuse, -0x77777777, RZ ; /* 0x8888888904027825 */ /* 0x040fe200078e00ff */ /*0100*/ ISETP.GE.U32.AND P0, PT, R4, 0x5a, PT ; /* 0x0000005a0400780c */ /* 0x000fc80003f06070 */ /*0110*/ SHF.R.U32.HI R9, RZ, 0x4, R3 ; /* 0x00000004ff097819 */ /* 0x000fc80000011603 */ /*0120*/ IADD3 R4, R9, 0x1, RZ ; /* 0x0000000109047810 */ /* 0x000fc80007ffe0ff */ /*0130*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */ /* 0x000fe200078ec0ff */ /*0140*/ @!P0 BRA 0x6f0 ; /* 0x000005a000008947 */ /* 0x000fea0003800000 */ /*0150*/ IMAD.IADD R6, R9, 0x1, -R4 ; /* 0x0000000109067824 */ /* 0x000fe200078e0a04 */ /*0160*/ BSSY B0, 0x610 ; /* 0x000004a000007945 */ /* 0x000fe20003800000 */ /*0170*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */ /* 0x000fe400078e00ff */ /*0180*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */ /* 0x000fe200078e00ff */ /*0190*/ ISETP.GT.AND P0, PT, R6, -0x1, PT ; /* 0xffffffff0600780c */ /* 0x000fe20003f04270 */ /*01a0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */ /* 0x000fc800078e0203 */ /*01b0*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */ /* 0x000fe200078e0000 */ /*01c0*/ IADD3 R2, P1, R2, 0xf0, RZ ; /* 0x000000f002027810 */ /* 0x000fca0007f3e0ff */ /*01d0*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */ /* 0x000fe400008e0603 */ /*01e0*/ @!P0 BRA 0x600 ; /* 0x0000041000008947 */ /* 0x000fea0003800000 */ /*01f0*/ IADD3 R8, R6, 0x1, RZ ; /* 0x0000000106087810 */ /* 0x000fe20007ffe0ff */ /*0200*/ BSSY B3, 0x450 ; /* 0x0000024000037945 */ /* 0x000fe20003800000 */ /*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */ /* 0x000fe40003f0f070 */ /*0220*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */ /* 0x000fda0003f24270 */ /*0230*/ @!P1 BRA 0x440 ; /* 0x0000020000009947 */ /* 0x000fea0003800000 */ /*0240*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe40003f0e170 */ /*0250*/ LDG.E R12, [R2.64+-0xf0] ; /* 0xffff1004020c7981 */ /* 0x000ea8000c1e1900 */ /*0260*/ LDG.E R13, [R2.64+-0x78] ; /* 0xffff8804020d7981 */ /* 0x000ea8000c1e1900 */ /*0270*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */ /* 0x0000e8000c1e1900 */ /*0280*/ LDG.E R14, [R2.64+0x78] ; /* 0x00007804020e7981 */ /* 0x0000e8000c1e1900 */ /*0290*/ LDG.E R17, [R2.64+0xf0] ; /* 0x0000f00402117981 */ /* 0x000128000c1e1900 */ /*02a0*/ LDG.E R16, [R2.64+0x168] ; /* 0x0001680402107981 */ /* 0x000128000c1e1900 */ /*02b0*/ LDG.E R19, [R2.64+0x1e0] ; /* 0x0001e00402137981 */ /* 0x000168000c1e1900 */ /*02c0*/ LDG.E R18, [R2.64+0x258] ; /* 0x0002580402127981 */ /* 0x000168000c1e1900 */ /*02d0*/ LDG.E R21, [R2.64+0x2d0] ; /* 0x0002d00402157981 */ /* 0x000168000c1e1900 */ /*02e0*/ LDG.E R20, [R2.64+0x348] ; /* 0x0003480402147981 */ /* 0x000168000c1e1900 */ /*02f0*/ LDG.E R23, [R2.64+0x3c0] ; /* 0x0003c00402177981 */ /* 0x000168000c1e1900 */ /*0300*/ LDG.E R22, [R2.64+0x438] ; /* 0x0004380402167981 */ /* 0x000168000c1e1900 */ /*0310*/ LDG.E R11, [R2.64+0x4b0] ; /* 0x0004b004020b7981 */ /* 0x000168000c1e1900 */ /*0320*/ LDG.E R10, [R2.64+0x528] ; /* 0x00052804020a7981 */ /* 0x000168000c1e1900 */ /*0330*/ LDG.E R9, [R2.64+0x5a0] ; /* 0x0005a00402097981 */ /* 0x000168000c1e1900 */ /*0340*/ LDG.E R8, [R2.64+0x618] ; /* 0x0006180402087981 */ /* 0x000162000c1e1900 */ /*0350*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */ /* 0x000fc40007ffe0ff */ /*0360*/ IADD3 R7, R7, 0x1e0, RZ ; /* 0x000001e007077810 */ /* 0x000fe40007ffe0ff */ /*0370*/ ISETP.GT.AND P1, PT, R6, 0xb, PT ; /* 0x0000000b0600780c */ /* 0x000fe40003f24270 */ /*0380*/ IADD3 R12, R13, R12, R5 ; /* 0x0000000c0d0c7210 */ /* 0x004fe40007ffe005 */ /*0390*/ IADD3 R13, P2, R2, 0x780, RZ ; /* 0x00000780020d7810 */ /* 0x000fca0007f5e0ff */ /*03a0*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */ /* 0x001fe200010e0603 */ /*03b0*/ IADD3 R12, R14, R15, R12 ; /* 0x0000000f0e0c7210 */ /* 0x008fe20007ffe00c */ /*03c0*/ IMAD.MOV.U32 R2, RZ, RZ, R13 ; /* 0x000000ffff027224 */ /* 0x000fc600078e000d */ /*03d0*/ IADD3 R12, R16, R17, R12 ; /* 0x00000011100c7210 */ /* 0x010fc80007ffe00c */ /*03e0*/ IADD3 R12, R18, R19, R12 ; /* 0x00000013120c7210 */ /* 0x020fc80007ffe00c */ /*03f0*/ IADD3 R12, R20, R21, R12 ; /* 0x00000015140c7210 */ /* 0x000fc80007ffe00c */ /*0400*/ IADD3 R12, R22, R23, R12 ; /* 0x00000017160c7210 */ /* 0x000fc80007ffe00c */ /*0410*/ IADD3 R10, R10, R11, R12 ; /* 0x0000000b0a0a7210 */ /* 0x000fc80007ffe00c */ /*0420*/ IADD3 R5, R8, R9, R10 ; /* 0x0000000908057210 */ /* 0x000fe20007ffe00a */ /*0430*/ @P1 BRA 0x250 ; /* 0xfffffe1000001947 */ /* 0x000fea000383ffff */ /*0440*/ BSYNC B3 ; /* 0x0000000000037941 */ /* 0x000fea0003800000 */ /*0450*/ IADD3 R8, R6, 0x1, RZ ; /* 0x0000000106087810 */ /* 0x000fe20007ffe0ff */ /*0460*/ BSSY B3, 0x5d0 ; /* 0x0000016000037945 */ /* 0x000fe60003800000 */ /*0470*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */ /* 0x000fda0003f24270 */ /*0480*/ @!P1 BRA 0x5c0 ; /* 0x0000013000009947 */ /* 0x000fea0003800000 */ /*0490*/ LDG.E R8, [R2.64+-0xf0] ; /* 0xffff100402087981 */ /* 0x000ea8000c1e1900 */ /*04a0*/ LDG.E R9, [R2.64+-0x78] ; /* 0xffff880402097981 */ /* 0x000ea8000c1e1900 */ /*04b0*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */ /* 0x0000e8000c1e1900 */ /*04c0*/ LDG.E R10, [R2.64+0x78] ; /* 0x00007804020a7981 */ /* 0x0000e8000c1e1900 */ /*04d0*/ LDG.E R13, [R2.64+0xf0] ; /* 0x0000f004020d7981 */ /* 0x000128000c1e1900 */ /*04e0*/ LDG.E R12, [R2.64+0x168] ; /* 0x00016804020c7981 */ /* 0x000128000c1e1900 */ /*04f0*/ LDG.E R15, [R2.64+0x1e0] ; /* 0x0001e004020f7981 */ /* 0x000168000c1e1900 */ /*0500*/ LDG.E R14, [R2.64+0x258] ; /* 0x00025804020e7981 */ /* 0x000162000c1e1900 */ /*0510*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */ /* 0x000fc40003f0e170 */ /*0520*/ IADD3 R7, R7, 0xf0, RZ ; /* 0x000000f007077810 */ /* 0x000fe40007ffe0ff */ /*0530*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */ /* 0x000fe40007ffe0ff */ /*0540*/ IADD3 R8, R9, R8, R5 ; /* 0x0000000809087210 */ /* 0x004fe40007ffe005 */ /*0550*/ IADD3 R9, P1, R2, 0x3c0, RZ ; /* 0x000003c002097810 */ /* 0x000fca0007f3e0ff */ /*0560*/ IMAD.MOV.U32 R2, RZ, RZ, R9 ; /* 0x000000ffff027224 */ /* 0x001fe200078e0009 */ /*0570*/ IADD3 R8, R10, R11, R8 ; /* 0x0000000b0a087210 */ /* 0x008fe20007ffe008 */ /*0580*/ IMAD.X R10, RZ, RZ, R3, P1 ; /* 0x000000ffff0a7224 */ /* 0x000fc800008e0603 */ /*0590*/ IMAD.MOV.U32 R3, RZ, RZ, R10 ; /* 0x000000ffff037224 */ /* 0x000fe200078e000a */ /*05a0*/ IADD3 R8, R12, R13, R8 ; /* 0x0000000d0c087210 */ /* 0x010fc80007ffe008 */ /*05b0*/ IADD3 R5, R14, R15, R8 ; /* 0x0000000f0e057210 */ /* 0x020fe40007ffe008 */ /*05c0*/ BSYNC B3 ; /* 0x0000000000037941 */ /* 0x000fea0003800000 */ /*05d0*/ ISETP.NE.OR P0, PT, R6, -0x1, P0 ; /* 0xffffffff0600780c */ /* 0x000fda0000705670 */ /*05e0*/ @!P0 BREAK B0 ; /* 0x0000000000008942 */ /* 0x000fe20003800000 */ /*05f0*/ @!P0 BRA 0x6f0 ; /* 0x000000f000008947 */ /* 0x000fea0003800000 */ /*0600*/ BSYNC B0 ; /* 0x0000000000007941 */ /* 0x000fea0003800000 */ /*0610*/ LDG.E R8, [R2.64+-0xf0] ; /* 0xffff100402087981 */ /* 0x0000a8000c1e1900 */ /*0620*/ LDG.E R9, [R2.64+-0x78] ; /* 0xffff880402097981 */ /* 0x0000a8000c1e1900 */ /*0630*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */ /* 0x0000e8000c1e1900 */ /*0640*/ LDG.E R11, [R2.64+0x78] ; /* 0x00007804020b7981 */ /* 0x0000e2000c1e1900 */ /*0650*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */ /* 0x000fc40007ffe0ff */ /*0660*/ IADD3 R12, P1, R2, 0x1e0, RZ ; /* 0x000001e0020c7810 */ /* 0x000fe40007f3e0ff */ /*0670*/ ISETP.NE.AND P0, PT, R6, -0x1, PT ; /* 0xffffffff0600780c */ /* 0x000fe40003f05270 */ /*0680*/ IADD3 R7, R7, 0x78, RZ ; /* 0x0000007807077810 */ /* 0x000fe20007ffe0ff */ /*0690*/ IMAD.X R13, RZ, RZ, R3, P1 ; /* 0x000000ffff0d7224 */ /* 0x000fe400008e0603 */ /*06a0*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */ /* 0x001fe400078e000c */ /*06b0*/ IMAD.MOV.U32 R3, RZ, RZ, R13 ; /* 0x000000ffff037224 */ /* 0x000fe200078e000d */ /*06c0*/ IADD3 R5, R9, R8, R5 ; /* 0x0000000809057210 */ /* 0x004fc80007ffe005 */ /*06d0*/ IADD3 R5, R11, R10, R5 ; /* 0x0000000a0b057210 */ /* 0x008fe20007ffe005 */ /*06e0*/ @P0 BRA 0x610 ; /* 0xffffff2000000947 */ /* 0x000fea000383ffff */ /*06f0*/ BSYNC B1 ; /* 0x0000000000017941 */ /* 0x000fea0003800000 */ /*0700*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */ /* 0x000fda0003f05270 */ /*0710*/ @!P0 BRA 0x7d0 ; /* 0x000000b000008947 */ /* 0x000fea0003800000 */ /*0720*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */ /* 0x000fc800078e00ff */ /*0730*/ IMAD.WIDE R2, R7, R2, c[0x0][0x160] ; /* 0x0000580007027625 */ /* 0x000fc800078e0202 */ /*0740*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */ /* 0x000fc800078e0002 */ /*0750*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */ /* 0x000fcc00078e0006 */ /*0760*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */ /* 0x0000a2000c1e1900 */ /*0770*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */ /* 0x000fe40007ffe0ff */ /*0780*/ IADD3 R6, P1, R6, 0x78, RZ ; /* 0x0000007806067810 */ /* 0x000fe40007f3e0ff */ /*0790*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */ /* 0x000fc60003f05270 */ /*07a0*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */ /* 0x001fe400008e0603 */ /*07b0*/ IMAD.IADD R5, R2, 0x1, R5 ; /* 0x0000000102057824 */ /* 0x004fd000078e0205 */ /*07c0*/ @P0 BRA 0x750 ; /* 0xffffff8000000947 */ /* 0x000fea000383ffff */ /*07d0*/ BSYNC B2 ; /* 0x0000000000027941 */ /* 0x000fea0003800000 */ /*07e0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */ /* 0x000fe20003800000 */ /*07f0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */ /* 0x000fc800078e00ff */ /*0800*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */ /* 0x000fca00078e0203 */ /*0810*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */ /* 0x000fe2000c101904 */ /*0820*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0830*/ BRA 0x830; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0840*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0850*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0860*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0870*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0880*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0890*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*08a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*08b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*08c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*08d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*08e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*08f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .section .text._ZL3SumPiS_,"axG",@progbits,_ZL3SumPiS_,comdat .globl _ZL3SumPiS_ .p2align 8 .type _ZL3SumPiS_,@function _ZL3SumPiS_: s_mul_i32 s15, s15, 10 s_mov_b32 s3, exec_lo v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v1, s15, v0 s_delay_alu instid0(VALU_DEP_1) v_cmpx_gt_i32_e32 0x64, v1 s_cbranch_execz .LBB0_4 s_load_b64 s[4:5], s[0:1], 0x0 s_ashr_i32 s2, s15, 31 v_add_co_u32 v2, s6, s15, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_add_co_ci_u32_e64 v3, null, s2, 0, s6 v_add3_u32 v0, v0, s15, 0xffffffe2 v_mov_b32_e32 v4, 0 v_lshlrev_b64 v[2:3], 2, v[2:3] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v2, vcc_lo, s4, v2 v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo s_mov_b32 s4, 0 .LBB0_2: global_load_b32 v5, v[2:3], off v_add_nc_u32_e32 v0, 30, v0 v_add_co_u32 v2, vcc_lo, v2, 0x78 v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_lt_i32_e64 s2, 0x45, v0 s_or_b32 s4, s2, s4 s_waitcnt vmcnt(0) v_add_nc_u32_e32 v4, v5, v4 s_and_not1_b32 exec_lo, exec_lo, s4 s_cbranch_execnz .LBB0_2 s_or_b32 exec_lo, exec_lo, s4 .LBB0_4: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) s_or_b32 exec_lo, exec_lo, s3 s_load_b64 s[0:1], s[0:1], 0x8 v_ashrrev_i32_e32 v2, 31, v1 v_lshlrev_b64 v[0:1], 2, v[1:2] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, s0, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo global_store_b32 v[0:1], v4, off s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _ZL3SumPiS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 16 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 6 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .section .text._ZL3SumPiS_,"axG",@progbits,_ZL3SumPiS_,comdat .Lfunc_end0: .size _ZL3SumPiS_, .Lfunc_end0-_ZL3SumPiS_ .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 16 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _ZL3SumPiS_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _ZL3SumPiS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 6 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_000da7c6_00000000-6_array_sum.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .type _ZL3SumPiS_, @function _ZL3SumPiS_: .LFB3696: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax movq %rdi, (%rsp) movq %rsi, 8(%rsp) movq %rsp, %rax movq %rax, 80(%rsp) leaq 8(%rsp), %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L5 .L1: movq 104(%rsp), %rax subq %fs:40, %rax jne .L6 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L5: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _ZL3SumPiS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L1 .L6: call __stack_chk_fail@PLT .cfi_endproc .LFE3696: .size _ZL3SumPiS_, .-_ZL3SumPiS_ .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3673: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3673: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "\346\211\276\344\270\215\345\210\260\350\256\276\345\244\207" .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC1: .string "\346\211\276\344\270\215\345\210\260\346\224\257\346\214\201 CUDA \350\256\241\347\256\227\347\232\204\350\256\276\345\244\207" .text .globl _Z8InitCUDAv .type _Z8InitCUDAv, @function _Z8InitCUDAv: .LFB3669: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $1064, %rsp .cfi_def_cfa_offset 1088 movq %fs:40, %rax movq %rax, 1048(%rsp) xorl %eax, %eax leaq 12(%rsp), %rdi call cudaGetDeviceCount@PLT movl 12(%rsp), %eax testl %eax, %eax je .L30 movl $0, %ebx leaq 16(%rsp), %rbp jg .L18 jmp .L20 .L30: movl $15, %edx leaq .LC0(%rip), %rsi leaq _ZSt4cout(%rip), %rbx movq %rbx, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %rbx testq %rbx, %rbx je .L31 cmpb $0, 56(%rbx) je .L13 movzbl 67(%rbx), %eax .L14: movsbl %al, %esi leaq _ZSt4cout(%rip), %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT movl $1, %eax jmp .L9 .L31: movq 1048(%rsp), %rax subq %fs:40, %rax jne .L32 call _ZSt16__throw_bad_castv@PLT .L32: call __stack_chk_fail@PLT .L13: movq %rbx, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq (%rbx), %rax movl $10, %esi movq %rbx, %rdi call *48(%rax) jmp .L14 .L16: addl $1, %ebx cmpl %ebx, 12(%rsp) jle .L19 .L18: movl %ebx, %esi movq %rbp, %rdi call cudaGetDeviceProperties_v2@PLT testl %eax, %eax jne .L16 cmpl $0, 376(%rsp) jle .L16 .L19: cmpl %ebx, 12(%rsp) je .L33 .L20: movl %ebx, %edi call cudaSetDevice@PLT movl $0, %eax .L9: movq 1048(%rsp), %rdx subq %fs:40, %rdx jne .L34 addq $1064, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L33: .cfi_restore_state movl $36, %edx leaq .LC1(%rip), %rsi leaq _ZSt4cout(%rip), %rbx movq %rbx, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %rbx testq %rbx, %rbx je .L35 cmpb $0, 56(%rbx) je .L23 movzbl 67(%rbx), %esi .L24: movsbl %sil, %esi leaq _ZSt4cout(%rip), %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT movl $1, %eax jmp .L9 .L35: movq 1048(%rsp), %rax subq %fs:40, %rax jne .L36 call _ZSt16__throw_bad_castv@PLT .L36: call __stack_chk_fail@PLT .L23: movq %rbx, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq (%rbx), %rax movl $10, %esi movq %rbx, %rdi call *48(%rax) movl %eax, %esi jmp .L24 .L34: call __stack_chk_fail@PLT .cfi_endproc .LFE3669: .size _Z8InitCUDAv, .-_Z8InitCUDAv .section .rodata.str1.8 .align 8 .LC2: .string "\346\210\220\345\212\237\345\273\272\347\253\213 CUDA \350\256\241\347\256\227\347\216\257\345\242\203" .section .rodata.str1.1 .LC3: .string "\346\265\213\350\257\225\347\237\251\351\230\265: " .LC4: .string " " .LC5: .string "GPU \346\261\202\345\222\214\347\273\223\346\236\234\344\270\272: " .LC6: .string "CPU \346\261\202\345\222\214\347\273\223\346\236\234\344\270\272: " .text .globl main .type main, @function main: .LFB3670: .cfi_startproc endbr64 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 subq $48, %rsp .cfi_def_cfa_offset 96 movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax call _Z8InitCUDAv movl %eax, %edx movl $1, %eax testb %dl, %dl je .L54 .L37: movq 40(%rsp), %rdx subq %fs:40, %rdx jne .L55 addq $48, %rsp .cfi_remember_state .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .L54: .cfi_restore_state leaq .LC2(%rip), %rsi leaq _ZSt4cout(%rip), %rbx movq %rbx, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movl $400, %edi call _Znam@PLT movq %rax, %rbp leaq .LC3(%rip), %rsi movq %rbx, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movl $1, %ebx leaq _ZSt4cout(%rip), %r12 leaq .LC4(%rip), %r13 jmp .L44 .L58: movq 40(%rsp), %rax subq %fs:40, %rax jne .L56 call _ZSt16__throw_bad_castv@PLT .L56: call __stack_chk_fail@PLT .L42: movq %r14, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq (%r14), %rax movl $10, %esi movq %r14, %rdi call *48(%rax) movl %eax, %esi .L43: movsbl %sil, %esi movq %r12, %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT .L39: addq $1, %rbx cmpq $101, %rbx je .L57 .L44: call rand@PLT movslq %eax, %rsi imulq $1717986919, %rsi, %rsi sarq $34, %rsi cltd subl %edx, %esi leal (%rsi,%rsi,4), %edx addl %edx, %edx subl %edx, %eax movl %eax, %esi movl %eax, -4(%rbp,%rbx,4) movq %r12, %rdi call _ZNSolsEi@PLT movq %rax, %rdi movl $1, %edx movq %r13, %rsi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movslq %ebx, %rax imulq $1717986919, %rax, %rax sarq $34, %rax movl %ebx, %edx sarl $31, %edx subl %edx, %eax leal (%rax,%rax,4), %eax addl %eax, %eax cmpl %ebx, %eax jne .L39 movq (%r12), %rax movq -24(%rax), %rax movq 240(%r12,%rax), %r14 testq %r14, %r14 je .L58 cmpb $0, 56(%r14) je .L42 movzbl 67(%r14), %esi jmp .L43 .L57: leaq _ZSt4cout(%rip), %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movq %rsp, %rdi movl $400, %esi call cudaMalloc@PLT leaq 8(%rsp), %rdi movl $120, %esi call cudaMalloc@PLT movl $1, %ecx movl $400, %edx movq %rbp, %rsi movq (%rsp), %rdi call cudaMemcpy@PLT movl $10, 28(%rsp) movl $1, 32(%rsp) movl $3, 16(%rsp) movl $1, 20(%rsp) movl $0, %r9d movl $0, %r8d movq 28(%rsp), %rdx movl $1, %ecx movq 16(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L59 .L45: movl $120, %edi call _Znam@PLT movq %rax, %rbx movl $2, %ecx movl $120, %edx movq 8(%rsp), %rsi movq %rax, %rdi call cudaMemcpy@PLT movq (%rsp), %rdi call cudaFree@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq %rbx, %rax leaq 120(%rbx), %rcx movl $0, %edx .L46: movl %edx, %ebx addl (%rax), %ebx movl %ebx, %edx addq $4, %rax cmpq %rcx, %rax jne .L46 leaq .LC5(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi movl %ebx, %esi call _ZNSolsEi@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movq %rbp, %rax addq $400, %rbp movl $0, %edx .L47: movl %edx, %ebx addl (%rax), %ebx movl %ebx, %edx addq $4, %rax cmpq %rax, %rbp jne .L47 leaq .LC6(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi movl %ebx, %esi call _ZNSolsEi@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movl $0, %eax jmp .L37 .L59: movq 8(%rsp), %rsi movq (%rsp), %rdi call _ZL3SumPiS_ jmp .L45 .L55: call __stack_chk_fail@PLT .cfi_endproc .LFE3670: .size main, .-main .section .rodata.str1.1 .LC7: .string "_Z3SumPiS_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3698: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC7(%rip), %rdx movq %rdx, %rcx leaq _ZL3SumPiS_(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3698: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "array_sum.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z8InitCUDAv # -- Begin function _Z8InitCUDAv .p2align 4, 0x90 .type _Z8InitCUDAv,@function _Z8InitCUDAv: # @_Z8InitCUDAv .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 subq $1480, %rsp # imm = 0x5C8 .cfi_def_cfa_offset 1504 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 leaq 4(%rsp), %rdi callq hipGetDeviceCount cmpl $0, 4(%rsp) je .LBB0_10 # %bb.1: # %.preheader cmpl $0, 4(%rsp) jle .LBB0_15 # %bb.2: # %.lr.ph xorl %ebx, %ebx leaq 8(%rsp), %r14 jmp .LBB0_4 .p2align 4, 0x90 .LBB0_3: # in Loop: Header=BB0_4 Depth=1 incl %ebx cmpl 4(%rsp), %ebx jge .LBB0_6 .LBB0_4: # =>This Inner Loop Header: Depth=1 movq %r14, %rdi movl %ebx, %esi callq hipGetDevicePropertiesR0600 testl %eax, %eax jne .LBB0_3 # %bb.5: # in Loop: Header=BB0_4 Depth=1 cmpl $0, 368(%rsp) jle .LBB0_3 .LBB0_6: # %._crit_edge cmpl 4(%rsp), %ebx jne .LBB0_16 .LBB0_7: movl $_ZSt4cout, %edi movl $.L.str.1, %esi movl $36, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %rbx testq %rbx, %rbx je .LBB0_18 # %bb.8: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i11 cmpb $0, 56(%rbx) jne .LBB0_12 .LBB0_13: movq %rbx, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%rbx), %rax movq %rbx, %rdi movl $10, %esi callq *48(%rax) jmp .LBB0_14 .LBB0_10: movl $_ZSt4cout, %edi movl $.L.str, %esi movl $15, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %rbx testq %rbx, %rbx je .LBB0_18 # %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i cmpb $0, 56(%rbx) je .LBB0_13 .LBB0_12: movzbl 67(%rbx), %eax .LBB0_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movb $1, %al jmp .LBB0_17 .LBB0_15: xorl %ebx, %ebx cmpl 4(%rsp), %ebx je .LBB0_7 .LBB0_16: movl %ebx, %edi callq hipSetDevice xorl %eax, %eax .LBB0_17: # kill: def $al killed $al killed $eax addq $1480, %rsp # imm = 0x5C8 .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .LBB0_18: .cfi_def_cfa_offset 1504 callq _ZSt16__throw_bad_castv .Lfunc_end0: .size _Z8InitCUDAv, .Lfunc_end0-_Z8InitCUDAv .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $96, %rsp .cfi_def_cfa_offset 144 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl $1, %ebx callq _Z8InitCUDAv testb %al, %al jne .LBB1_40 # %bb.1: movl $_ZSt4cout, %edi movl $.L.str.2, %esi movl $30, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %rbx testq %rbx, %rbx je .LBB1_41 # %bb.2: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i cmpb $0, 56(%rbx) je .LBB1_4 # %bb.3: movzbl 67(%rbx), %eax jmp .LBB1_5 .LBB1_4: movq %rbx, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%rbx), %rax movq %rbx, %rdi movl $10, %esi callq *48(%rax) .LBB1_5: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movq (%rax), %rcx movq -24(%rcx), %rcx movq 240(%rax,%rcx), %rbx testq %rbx, %rbx je .LBB1_41 # %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i28 cmpb $0, 56(%rbx) je .LBB1_8 # %bb.7: movzbl 67(%rbx), %ecx jmp .LBB1_9 .LBB1_8: movq %rbx, %rdi movq %rax, %r14 callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%rbx), %rax movq %rbx, %rdi movl $10, %esi callq *48(%rax) movl %eax, %ecx movq %r14, %rax .LBB1_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit31 movsbl %cl, %esi movq %rax, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $400, %edi # imm = 0x190 callq _Znam movq %rax, %rbx movl $_ZSt4cout, %edi movl $.L.str.3, %esi movl $14, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %r14 testq %r14, %r14 je .LBB1_41 # %bb.10: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i33 cmpb $0, 56(%r14) je .LBB1_12 # %bb.11: movzbl 67(%r14), %eax jmp .LBB1_13 .LBB1_12: movq %r14, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r14), %rax movq %r14, %rdi movl $10, %esi callq *48(%rax) .LBB1_13: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit36 movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movl $1, %ebp xorl %r15d, %r15d movl $3435973837, %r12d # imm = 0xCCCCCCCD jmp .LBB1_14 .LBB1_29: # in Loop: Header=BB1_14 Depth=1 movq %r14, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r14), %rax movq %r14, %rdi movl $10, %esi callq *48(%rax) .LBB1_30: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit46 # in Loop: Header=BB1_14 Depth=1 movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv .LBB1_31: # in Loop: Header=BB1_14 Depth=1 incq %r15 incl %ebp cmpq $100, %r15 je .LBB1_18 .LBB1_14: # =>This Inner Loop Header: Depth=1 movl %ebp, %eax imulq %r12, %rax shrq $35, %rax leal (%rax,%rax,4), %eax leal -1(,%rax,2), %r14d callq rand movslq %eax, %rsi imulq $1717986919, %rsi, %rax # imm = 0x66666667 movq %rax, %rcx shrq $63, %rcx sarq $34, %rax addl %ecx, %eax addl %eax, %eax leal (%rax,%rax,4), %eax subl %eax, %esi movl %esi, (%rbx,%r15,4) movl $_ZSt4cout, %edi # kill: def $esi killed $esi killed $rsi callq _ZNSolsEi movl $.L.str.4, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l cmpl %r15d, %r14d jne .LBB1_31 # %bb.15: # in Loop: Header=BB1_14 Depth=1 movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %r14 testq %r14, %r14 je .LBB1_41 # %bb.16: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i43 # in Loop: Header=BB1_14 Depth=1 cmpb $0, 56(%r14) je .LBB1_29 # %bb.17: # in Loop: Header=BB1_14 Depth=1 movzbl 67(%r14), %eax jmp .LBB1_30 .LBB1_18: movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %r14 testq %r14, %r14 je .LBB1_41 # %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i38 cmpb $0, 56(%r14) je .LBB1_21 # %bb.20: movzbl 67(%r14), %eax jmp .LBB1_22 .LBB1_21: movq %r14, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r14), %rax movq %r14, %rdi movl $10, %esi callq *48(%rax) .LBB1_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit41 movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv leaq 8(%rsp), %rdi movl $400, %esi # imm = 0x190 callq hipMalloc movq %rsp, %rdi movl $120, %esi callq hipMalloc movq 8(%rsp), %rdi movl $400, %edx # imm = 0x190 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy movabsq $4294967299, %rdi # imm = 0x100000003 leaq 7(%rdi), %rdx xorl %r14d, %r14d movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_24 # %bb.23: movq 8(%rsp), %rax movq (%rsp), %rcx movq %rax, 72(%rsp) movq %rcx, 64(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_ZL3SumPiS_, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_24: movl $120, %edi callq _Znam movq %rax, %r15 movq (%rsp), %rsi movl $120, %edx movq %rax, %rdi movl $2, %ecx callq hipMemcpy movq 8(%rsp), %rdi callq hipFree movq (%rsp), %rdi callq hipFree xorl %eax, %eax .p2align 4, 0x90 .LBB1_25: # =>This Inner Loop Header: Depth=1 addl (%r15,%rax,4), %r14d incq %rax cmpq $30, %rax jne .LBB1_25 # %bb.26: movl $_ZSt4cout, %edi movl $.L.str.5, %esi movl $21, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cout, %edi movl %r14d, %esi callq _ZNSolsEi movq (%rax), %rcx movq -24(%rcx), %rcx movq 240(%rax,%rcx), %r14 testq %r14, %r14 je .LBB1_41 # %bb.27: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i48 cmpb $0, 56(%r14) je .LBB1_32 # %bb.28: movzbl 67(%r14), %ecx jmp .LBB1_33 .LBB1_32: movq %r14, %rdi movq %rax, %r15 callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r14), %rax movq %r14, %rdi movl $10, %esi callq *48(%rax) movl %eax, %ecx movq %r15, %rax .LBB1_33: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit51 movsbl %cl, %esi movq %rax, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv xorl %eax, %eax xorl %ebp, %ebp .p2align 4, 0x90 .LBB1_34: # =>This Inner Loop Header: Depth=1 addl (%rbx,%rax,4), %ebp incq %rax cmpq $100, %rax jne .LBB1_34 # %bb.35: movl $_ZSt4cout, %edi movl $.L.str.6, %esi movl $21, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cout, %edi movl %ebp, %esi callq _ZNSolsEi movq (%rax), %rcx movq -24(%rcx), %rcx movq 240(%rax,%rcx), %rbx testq %rbx, %rbx je .LBB1_41 # %bb.36: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i53 cmpb $0, 56(%rbx) je .LBB1_38 # %bb.37: movzbl 67(%rbx), %ecx jmp .LBB1_39 .LBB1_38: movq %rbx, %rdi movq %rax, %r14 callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%rbx), %rax movq %rbx, %rdi movl $10, %esi callq *48(%rax) movl %eax, %ecx movq %r14, %rax .LBB1_39: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit56 movsbl %cl, %esi movq %rax, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv xorl %ebx, %ebx .LBB1_40: movl %ebx, %eax addq $96, %rsp .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB1_41: .cfi_def_cfa_offset 144 callq _ZSt16__throw_bad_castv .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function _ZL18__device_stub__SumPiS_ .type _ZL18__device_stub__SumPiS_,@function _ZL18__device_stub__SumPiS_: # @_ZL18__device_stub__SumPiS_ .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_ZL3SumPiS_, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end2: .size _ZL18__device_stub__SumPiS_, .Lfunc_end2-_ZL18__device_stub__SumPiS_ .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_ZL3SumPiS_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "\346\211\276\344\270\215\345\210\260\350\256\276\345\244\207" .size .L.str, 16 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "\346\211\276\344\270\215\345\210\260\346\224\257\346\214\201 CUDA \350\256\241\347\256\227\347\232\204\350\256\276\345\244\207" .size .L.str.1, 37 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "\346\210\220\345\212\237\345\273\272\347\253\213 CUDA \350\256\241\347\256\227\347\216\257\345\242\203" .size .L.str.2, 31 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "\346\265\213\350\257\225\347\237\251\351\230\265: " .size .L.str.3, 15 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz " " .size .L.str.4, 2 .type _ZL3SumPiS_,@object # @_ZL3SumPiS_ .section .rodata,"a",@progbits .p2align 3, 0x0 _ZL3SumPiS_: .quad _ZL18__device_stub__SumPiS_ .size _ZL3SumPiS_, 8 .type .L.str.5,@object # @.str.5 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.5: .asciz "GPU \346\261\202\345\222\214\347\273\223\346\236\234\344\270\272: " .size .L.str.5, 22 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "CPU \346\261\202\345\222\214\347\273\223\346\236\234\344\270\272: " .size .L.str.6, 22 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_ZL3SumPiS_" .size .L__unnamed_1, 12 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _ZL18__device_stub__SumPiS_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _ZSt4cout .addrsig_sym _ZL3SumPiS_ .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include <stdio.h> __global__ void square(float* d_out, float* d_in){ int idx = threadIdx.x; float f = d_in[idx]; d_out[idx] = f * f; } int main(int argc, char ** argv){ const int ARRAY_SIZE = 64; const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float); // Generate input array on the host float h_in[ARRAY_SIZE]; for (int i = 0; i < ARRAY_SIZE; i++){ h_in[i] = float(i); } float h_out[ARRAY_SIZE]; // Declare GPU memory pointers float* d_in; float* d_out; // Allocate GPU memory cudaMalloc((void **) &d_in, ARRAY_BYTES); cudaMalloc((void **) &d_out, ARRAY_BYTES); /* * cudaMalloc() needs to modify the given pointer (the pointer itself * not what the pointer points to), so you need to pass "void**" which * is a pointer to the pointer. */ // Transfer the array to the GPU cudaMemcpy(d_in, h_in, ARRAY_BYTES, cudaMemcpyHostToDevice); // Launch the kernel square<<<1, ARRAY_SIZE>>>(d_out, d_in); // Copy back the result array to the CPU cudaMemcpy(h_out, d_out, ARRAY_BYTES, cudaMemcpyDeviceToHost); // Print out the resulting array for (int i = 0; i < ARRAY_SIZE; i++){ printf("%f", h_out[i]); printf(((i % 4) != 3) ? "\t" : "\n"); } // Free GPU memory allocation cudaFree(d_in); cudaFree(d_out); return 0; }
code for sm_80 Function : _Z6squarePfS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */ /* 0x000e220000002100 */ /*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */ /* 0x000fe200000001ff */ /*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fd20000000a00 */ /*0040*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */ /* 0x001fcc00078e0205 */ /*0050*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */ /* 0x000ea2000c1e1900 */ /*0060*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */ /* 0x000fc800078e0205 */ /*0070*/ FMUL R7, R2, R2 ; /* 0x0000000202077220 */ /* 0x004fca0000400000 */ /*0080*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */ /* 0x000fe2000c101904 */ /*0090*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*00b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0100*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0110*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0120*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0130*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0140*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0150*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0160*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0170*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include <stdio.h> __global__ void square(float* d_out, float* d_in){ int idx = threadIdx.x; float f = d_in[idx]; d_out[idx] = f * f; } int main(int argc, char ** argv){ const int ARRAY_SIZE = 64; const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float); // Generate input array on the host float h_in[ARRAY_SIZE]; for (int i = 0; i < ARRAY_SIZE; i++){ h_in[i] = float(i); } float h_out[ARRAY_SIZE]; // Declare GPU memory pointers float* d_in; float* d_out; // Allocate GPU memory cudaMalloc((void **) &d_in, ARRAY_BYTES); cudaMalloc((void **) &d_out, ARRAY_BYTES); /* * cudaMalloc() needs to modify the given pointer (the pointer itself * not what the pointer points to), so you need to pass "void**" which * is a pointer to the pointer. */ // Transfer the array to the GPU cudaMemcpy(d_in, h_in, ARRAY_BYTES, cudaMemcpyHostToDevice); // Launch the kernel square<<<1, ARRAY_SIZE>>>(d_out, d_in); // Copy back the result array to the CPU cudaMemcpy(h_out, d_out, ARRAY_BYTES, cudaMemcpyDeviceToHost); // Print out the resulting array for (int i = 0; i < ARRAY_SIZE; i++){ printf("%f", h_out[i]); printf(((i % 4) != 3) ? "\t" : "\n"); } // Free GPU memory allocation cudaFree(d_in); cudaFree(d_out); return 0; }
.file "tmpxft_00137629_00000000-6_square.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z27__device_stub__Z6squarePfS_PfS_ .type _Z27__device_stub__Z6squarePfS_PfS_, @function _Z27__device_stub__Z6squarePfS_PfS_: .LFB2082: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movq %rsi, (%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) movq %rsp, %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 104(%rsp), %rax subq %fs:40, %rax jne .L8 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z6squarePfS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2082: .size _Z27__device_stub__Z6squarePfS_PfS_, .-_Z27__device_stub__Z6squarePfS_PfS_ .globl _Z6squarePfS_ .type _Z6squarePfS_, @function _Z6squarePfS_: .LFB2083: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z27__device_stub__Z6squarePfS_PfS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2083: .size _Z6squarePfS_, .-_Z6squarePfS_ .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "\t" .LC1: .string "\n" .LC2: .string "%f" .text .globl main .type main, @function main: .LFB2057: .cfi_startproc endbr64 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 subq $576, %rsp .cfi_def_cfa_offset 624 movq %fs:40, %rax movq %rax, 568(%rsp) xorl %eax, %eax .L12: pxor %xmm0, %xmm0 cvtsi2ssl %eax, %xmm0 movss %xmm0, 48(%rsp,%rax,4) addq $1, %rax cmpq $64, %rax jne .L12 leaq 8(%rsp), %rdi movl $256, %esi call cudaMalloc@PLT leaq 16(%rsp), %rdi movl $256, %esi call cudaMalloc@PLT leaq 48(%rsp), %rsi movl $1, %ecx movl $256, %edx movq 8(%rsp), %rdi call cudaMemcpy@PLT movl $64, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 24(%rsp) movl $1, 28(%rsp) movl $1, 32(%rsp) movl $0, %r9d movl $0, %r8d movq 36(%rsp), %rdx movl $1, %ecx movq 24(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L21 .L13: leaq 304(%rsp), %rdi movl $2, %ecx movl $256, %edx movq 16(%rsp), %rsi call cudaMemcpy@PLT movl $0, %ebx leaq 304(%rsp), %r14 leaq .LC2(%rip), %r13 leaq .LC1(%rip), %r12 leaq .LC0(%rip), %rbp .L15: pxor %xmm0, %xmm0 cvtss2sd (%r14,%rbx,4), %xmm0 movq %r13, %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT movl %ebx, %edx sarl $31, %edx shrl $30, %edx leal (%rdx,%rbx), %eax andl $3, %eax subl %edx, %eax cmpl $3, %eax movq %rbp, %rsi cmove %r12, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $1, %rbx cmpq $64, %rbx jne .L15 movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 568(%rsp), %rax subq %fs:40, %rax jne .L22 movl $0, %eax addq $576, %rsp .cfi_remember_state .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .L21: .cfi_restore_state movq 8(%rsp), %rsi movq 16(%rsp), %rdi call _Z27__device_stub__Z6squarePfS_PfS_ jmp .L13 .L22: call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size main, .-main .section .rodata.str1.1 .LC3: .string "_Z6squarePfS_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC3(%rip), %rdx movq %rdx, %rcx leaq _Z6squarePfS_(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include <stdio.h> __global__ void square(float* d_out, float* d_in){ int idx = threadIdx.x; float f = d_in[idx]; d_out[idx] = f * f; } int main(int argc, char ** argv){ const int ARRAY_SIZE = 64; const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float); // Generate input array on the host float h_in[ARRAY_SIZE]; for (int i = 0; i < ARRAY_SIZE; i++){ h_in[i] = float(i); } float h_out[ARRAY_SIZE]; // Declare GPU memory pointers float* d_in; float* d_out; // Allocate GPU memory cudaMalloc((void **) &d_in, ARRAY_BYTES); cudaMalloc((void **) &d_out, ARRAY_BYTES); /* * cudaMalloc() needs to modify the given pointer (the pointer itself * not what the pointer points to), so you need to pass "void**" which * is a pointer to the pointer. */ // Transfer the array to the GPU cudaMemcpy(d_in, h_in, ARRAY_BYTES, cudaMemcpyHostToDevice); // Launch the kernel square<<<1, ARRAY_SIZE>>>(d_out, d_in); // Copy back the result array to the CPU cudaMemcpy(h_out, d_out, ARRAY_BYTES, cudaMemcpyDeviceToHost); // Print out the resulting array for (int i = 0; i < ARRAY_SIZE; i++){ printf("%f", h_out[i]); printf(((i % 4) != 3) ? "\t" : "\n"); } // Free GPU memory allocation cudaFree(d_in); cudaFree(d_out); return 0; }
#include <hip/hip_runtime.h> #include <stdio.h> __global__ void square(float* d_out, float* d_in){ int idx = threadIdx.x; float f = d_in[idx]; d_out[idx] = f * f; } int main(int argc, char ** argv){ const int ARRAY_SIZE = 64; const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float); // Generate input array on the host float h_in[ARRAY_SIZE]; for (int i = 0; i < ARRAY_SIZE; i++){ h_in[i] = float(i); } float h_out[ARRAY_SIZE]; // Declare GPU memory pointers float* d_in; float* d_out; // Allocate GPU memory hipMalloc((void **) &d_in, ARRAY_BYTES); hipMalloc((void **) &d_out, ARRAY_BYTES); /* * cudaMalloc() needs to modify the given pointer (the pointer itself * not what the pointer points to), so you need to pass "void**" which * is a pointer to the pointer. */ // Transfer the array to the GPU hipMemcpy(d_in, h_in, ARRAY_BYTES, hipMemcpyHostToDevice); // Launch the kernel square<<<1, ARRAY_SIZE>>>(d_out, d_in); // Copy back the result array to the CPU hipMemcpy(h_out, d_out, ARRAY_BYTES, hipMemcpyDeviceToHost); // Print out the resulting array for (int i = 0; i < ARRAY_SIZE; i++){ printf("%f", h_out[i]); printf(((i % 4) != 3) ? "\t" : "\n"); } // Free GPU memory allocation hipFree(d_in); hipFree(d_out); return 0; }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <hip/hip_runtime.h> #include <stdio.h> __global__ void square(float* d_out, float* d_in){ int idx = threadIdx.x; float f = d_in[idx]; d_out[idx] = f * f; } int main(int argc, char ** argv){ const int ARRAY_SIZE = 64; const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float); // Generate input array on the host float h_in[ARRAY_SIZE]; for (int i = 0; i < ARRAY_SIZE; i++){ h_in[i] = float(i); } float h_out[ARRAY_SIZE]; // Declare GPU memory pointers float* d_in; float* d_out; // Allocate GPU memory hipMalloc((void **) &d_in, ARRAY_BYTES); hipMalloc((void **) &d_out, ARRAY_BYTES); /* * cudaMalloc() needs to modify the given pointer (the pointer itself * not what the pointer points to), so you need to pass "void**" which * is a pointer to the pointer. */ // Transfer the array to the GPU hipMemcpy(d_in, h_in, ARRAY_BYTES, hipMemcpyHostToDevice); // Launch the kernel square<<<1, ARRAY_SIZE>>>(d_out, d_in); // Copy back the result array to the CPU hipMemcpy(h_out, d_out, ARRAY_BYTES, hipMemcpyDeviceToHost); // Print out the resulting array for (int i = 0; i < ARRAY_SIZE; i++){ printf("%f", h_out[i]); printf(((i % 4) != 3) ? "\t" : "\n"); } // Free GPU memory allocation hipFree(d_in); hipFree(d_out); return 0; }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z6squarePfS_ .globl _Z6squarePfS_ .p2align 8 .type _Z6squarePfS_,@function _Z6squarePfS_: s_load_b128 s[0:3], s[0:1], 0x0 v_lshlrev_b32_e32 v0, 2, v0 s_waitcnt lgkmcnt(0) global_load_b32 v1, v0, s[2:3] s_waitcnt vmcnt(0) v_mul_f32_e32 v1, v1, v1 global_store_b32 v0, v1, s[0:1] s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z6squarePfS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 16 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 2 .amdhsa_next_free_sgpr 4 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z6squarePfS_, .Lfunc_end0-_Z6squarePfS_ .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 16 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z6squarePfS_ .private_segment_fixed_size: 0 .sgpr_count: 4 .sgpr_spill_count: 0 .symbol: _Z6squarePfS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 2 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <hip/hip_runtime.h> #include <stdio.h> __global__ void square(float* d_out, float* d_in){ int idx = threadIdx.x; float f = d_in[idx]; d_out[idx] = f * f; } int main(int argc, char ** argv){ const int ARRAY_SIZE = 64; const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float); // Generate input array on the host float h_in[ARRAY_SIZE]; for (int i = 0; i < ARRAY_SIZE; i++){ h_in[i] = float(i); } float h_out[ARRAY_SIZE]; // Declare GPU memory pointers float* d_in; float* d_out; // Allocate GPU memory hipMalloc((void **) &d_in, ARRAY_BYTES); hipMalloc((void **) &d_out, ARRAY_BYTES); /* * cudaMalloc() needs to modify the given pointer (the pointer itself * not what the pointer points to), so you need to pass "void**" which * is a pointer to the pointer. */ // Transfer the array to the GPU hipMemcpy(d_in, h_in, ARRAY_BYTES, hipMemcpyHostToDevice); // Launch the kernel square<<<1, ARRAY_SIZE>>>(d_out, d_in); // Copy back the result array to the CPU hipMemcpy(h_out, d_out, ARRAY_BYTES, hipMemcpyDeviceToHost); // Print out the resulting array for (int i = 0; i < ARRAY_SIZE; i++){ printf("%f", h_out[i]); printf(((i % 4) != 3) ? "\t" : "\n"); } // Free GPU memory allocation hipFree(d_in); hipFree(d_out); return 0; }
.text .file "square.hip" .globl _Z21__device_stub__squarePfS_ # -- Begin function _Z21__device_stub__squarePfS_ .p2align 4, 0x90 .type _Z21__device_stub__squarePfS_,@function _Z21__device_stub__squarePfS_: # @_Z21__device_stub__squarePfS_ .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z6squarePfS_, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end0: .size _Z21__device_stub__squarePfS_, .Lfunc_end0-_Z21__device_stub__squarePfS_ .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 subq $600, %rsp # imm = 0x258 .cfi_def_cfa_offset 624 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 xorl %eax, %eax .p2align 4, 0x90 .LBB1_1: # =>This Inner Loop Header: Depth=1 xorps %xmm0, %xmm0 cvtsi2ss %eax, %xmm0 movss %xmm0, 336(%rsp,%rax,4) incq %rax cmpq $64, %rax jne .LBB1_1 # %bb.2: leaq 8(%rsp), %rdi movl $256, %esi # imm = 0x100 callq hipMalloc movq %rsp, %rdi movl $256, %esi # imm = 0x100 callq hipMalloc movq 8(%rsp), %rdi leaq 336(%rsp), %rsi movl $256, %edx # imm = 0x100 movl $1, %ecx callq hipMemcpy movabsq $4294967297, %rdi # imm = 0x100000001 leaq 63(%rdi), %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_4 # %bb.3: movq (%rsp), %rax movq 8(%rsp), %rcx movq %rax, 72(%rsp) movq %rcx, 64(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z6squarePfS_, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_4: movq (%rsp), %rsi leaq 80(%rsp), %rdi movl $256, %edx # imm = 0x100 movl $2, %ecx callq hipMemcpy movl $.L.str.2, %ebx xorl %r14d, %r14d .p2align 4, 0x90 .LBB1_5: # =>This Inner Loop Header: Depth=1 movss 80(%rsp,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 movl $.L.str, %edi movb $1, %al callq printf movl %r14d, %eax notl %eax testb $3, %al movl $.L.str.1, %edi cmoveq %rbx, %rdi xorl %eax, %eax callq printf incq %r14 cmpq $64, %r14 jne .LBB1_5 # %bb.6: movq 8(%rsp), %rdi callq hipFree movq (%rsp), %rdi callq hipFree xorl %eax, %eax addq $600, %rsp # imm = 0x258 .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z6squarePfS_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z6squarePfS_,@object # @_Z6squarePfS_ .section .rodata,"a",@progbits .globl _Z6squarePfS_ .p2align 3, 0x0 _Z6squarePfS_: .quad _Z21__device_stub__squarePfS_ .size _Z6squarePfS_, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "%f" .size .L.str, 3 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "\t" .size .L.str.1, 2 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "\n" .size .L.str.2, 2 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z6squarePfS_" .size .L__unnamed_1, 14 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z21__device_stub__squarePfS_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z6squarePfS_ .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z6squarePfS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */ /* 0x000e220000002100 */ /*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */ /* 0x000fe200000001ff */ /*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fd20000000a00 */ /*0040*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */ /* 0x001fcc00078e0205 */ /*0050*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */ /* 0x000ea2000c1e1900 */ /*0060*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */ /* 0x000fc800078e0205 */ /*0070*/ FMUL R7, R2, R2 ; /* 0x0000000202077220 */ /* 0x004fca0000400000 */ /*0080*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */ /* 0x000fe2000c101904 */ /*0090*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*00b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0100*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0110*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0120*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0130*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0140*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0150*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0160*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0170*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z6squarePfS_ .globl _Z6squarePfS_ .p2align 8 .type _Z6squarePfS_,@function _Z6squarePfS_: s_load_b128 s[0:3], s[0:1], 0x0 v_lshlrev_b32_e32 v0, 2, v0 s_waitcnt lgkmcnt(0) global_load_b32 v1, v0, s[2:3] s_waitcnt vmcnt(0) v_mul_f32_e32 v1, v1, v1 global_store_b32 v0, v1, s[0:1] s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z6squarePfS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 16 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 2 .amdhsa_next_free_sgpr 4 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z6squarePfS_, .Lfunc_end0-_Z6squarePfS_ .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 16 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z6squarePfS_ .private_segment_fixed_size: 0 .sgpr_count: 4 .sgpr_spill_count: 0 .symbol: _Z6squarePfS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 2 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_00137629_00000000-6_square.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z27__device_stub__Z6squarePfS_PfS_ .type _Z27__device_stub__Z6squarePfS_PfS_, @function _Z27__device_stub__Z6squarePfS_PfS_: .LFB2082: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movq %rsi, (%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) movq %rsp, %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 104(%rsp), %rax subq %fs:40, %rax jne .L8 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z6squarePfS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2082: .size _Z27__device_stub__Z6squarePfS_PfS_, .-_Z27__device_stub__Z6squarePfS_PfS_ .globl _Z6squarePfS_ .type _Z6squarePfS_, @function _Z6squarePfS_: .LFB2083: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z27__device_stub__Z6squarePfS_PfS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2083: .size _Z6squarePfS_, .-_Z6squarePfS_ .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "\t" .LC1: .string "\n" .LC2: .string "%f" .text .globl main .type main, @function main: .LFB2057: .cfi_startproc endbr64 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 subq $576, %rsp .cfi_def_cfa_offset 624 movq %fs:40, %rax movq %rax, 568(%rsp) xorl %eax, %eax .L12: pxor %xmm0, %xmm0 cvtsi2ssl %eax, %xmm0 movss %xmm0, 48(%rsp,%rax,4) addq $1, %rax cmpq $64, %rax jne .L12 leaq 8(%rsp), %rdi movl $256, %esi call cudaMalloc@PLT leaq 16(%rsp), %rdi movl $256, %esi call cudaMalloc@PLT leaq 48(%rsp), %rsi movl $1, %ecx movl $256, %edx movq 8(%rsp), %rdi call cudaMemcpy@PLT movl $64, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 24(%rsp) movl $1, 28(%rsp) movl $1, 32(%rsp) movl $0, %r9d movl $0, %r8d movq 36(%rsp), %rdx movl $1, %ecx movq 24(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L21 .L13: leaq 304(%rsp), %rdi movl $2, %ecx movl $256, %edx movq 16(%rsp), %rsi call cudaMemcpy@PLT movl $0, %ebx leaq 304(%rsp), %r14 leaq .LC2(%rip), %r13 leaq .LC1(%rip), %r12 leaq .LC0(%rip), %rbp .L15: pxor %xmm0, %xmm0 cvtss2sd (%r14,%rbx,4), %xmm0 movq %r13, %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT movl %ebx, %edx sarl $31, %edx shrl $30, %edx leal (%rdx,%rbx), %eax andl $3, %eax subl %edx, %eax cmpl $3, %eax movq %rbp, %rsi cmove %r12, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $1, %rbx cmpq $64, %rbx jne .L15 movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 568(%rsp), %rax subq %fs:40, %rax jne .L22 movl $0, %eax addq $576, %rsp .cfi_remember_state .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .L21: .cfi_restore_state movq 8(%rsp), %rsi movq 16(%rsp), %rdi call _Z27__device_stub__Z6squarePfS_PfS_ jmp .L13 .L22: call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size main, .-main .section .rodata.str1.1 .LC3: .string "_Z6squarePfS_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC3(%rip), %rdx movq %rdx, %rcx leaq _Z6squarePfS_(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "square.hip" .globl _Z21__device_stub__squarePfS_ # -- Begin function _Z21__device_stub__squarePfS_ .p2align 4, 0x90 .type _Z21__device_stub__squarePfS_,@function _Z21__device_stub__squarePfS_: # @_Z21__device_stub__squarePfS_ .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z6squarePfS_, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end0: .size _Z21__device_stub__squarePfS_, .Lfunc_end0-_Z21__device_stub__squarePfS_ .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 subq $600, %rsp # imm = 0x258 .cfi_def_cfa_offset 624 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 xorl %eax, %eax .p2align 4, 0x90 .LBB1_1: # =>This Inner Loop Header: Depth=1 xorps %xmm0, %xmm0 cvtsi2ss %eax, %xmm0 movss %xmm0, 336(%rsp,%rax,4) incq %rax cmpq $64, %rax jne .LBB1_1 # %bb.2: leaq 8(%rsp), %rdi movl $256, %esi # imm = 0x100 callq hipMalloc movq %rsp, %rdi movl $256, %esi # imm = 0x100 callq hipMalloc movq 8(%rsp), %rdi leaq 336(%rsp), %rsi movl $256, %edx # imm = 0x100 movl $1, %ecx callq hipMemcpy movabsq $4294967297, %rdi # imm = 0x100000001 leaq 63(%rdi), %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_4 # %bb.3: movq (%rsp), %rax movq 8(%rsp), %rcx movq %rax, 72(%rsp) movq %rcx, 64(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z6squarePfS_, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_4: movq (%rsp), %rsi leaq 80(%rsp), %rdi movl $256, %edx # imm = 0x100 movl $2, %ecx callq hipMemcpy movl $.L.str.2, %ebx xorl %r14d, %r14d .p2align 4, 0x90 .LBB1_5: # =>This Inner Loop Header: Depth=1 movss 80(%rsp,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 movl $.L.str, %edi movb $1, %al callq printf movl %r14d, %eax notl %eax testb $3, %al movl $.L.str.1, %edi cmoveq %rbx, %rdi xorl %eax, %eax callq printf incq %r14 cmpq $64, %r14 jne .LBB1_5 # %bb.6: movq 8(%rsp), %rdi callq hipFree movq (%rsp), %rdi callq hipFree xorl %eax, %eax addq $600, %rsp # imm = 0x258 .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z6squarePfS_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z6squarePfS_,@object # @_Z6squarePfS_ .section .rodata,"a",@progbits .globl _Z6squarePfS_ .p2align 3, 0x0 _Z6squarePfS_: .quad _Z21__device_stub__squarePfS_ .size _Z6squarePfS_, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "%f" .size .L.str, 3 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "\t" .size .L.str.1, 2 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "\n" .size .L.str.2, 2 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z6squarePfS_" .size .L__unnamed_1, 14 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z21__device_stub__squarePfS_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z6squarePfS_ .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include <stdio.h> #include <cuda.h> __global__ void cuda_hello(void) { // print a character buffer from the GPU! printf("Hello, world!\n"); } int main(void) { printf("Calling cuda_hello...\n"); // call the CUDA kernel from the GPU cuda_hello<<<1,1>>>(); // wait for the kernel to finish cudaDeviceSynchronize(); printf("...device synchronized.\n"); return 0; }
code for sm_80 Function : _Z10cuda_hellov .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */ /* 0x000fe20000000f00 */ /*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */ /* 0x000fe200078e00ff */ /*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */ /* 0x000fe2000001ff00 */ /*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */ /* 0x000fe200078e00ff */ /*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */ /* 0x00006c0000000a00 */ /*0060*/ LEPC R8 ; /* 0x000000000008734e */ /* 0x000fe40000000000 */ /*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */ /* 0x000fe40000000f00 */ /*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */ /* 0x000fe40000000f00 */ /*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */ /* 0x000fe40000000f00 */ /*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */ /* 0x001fc40000000f00 */ /*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */ /* 0x000fc8000791e108 */ /*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */ /* 0x000fc800007e2509 */ /*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */ /* 0x002fea0003c00000 */ /*00e0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0100*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0110*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0120*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0130*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0140*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0150*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0160*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0170*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include <stdio.h> #include <cuda.h> __global__ void cuda_hello(void) { // print a character buffer from the GPU! printf("Hello, world!\n"); } int main(void) { printf("Calling cuda_hello...\n"); // call the CUDA kernel from the GPU cuda_hello<<<1,1>>>(); // wait for the kernel to finish cudaDeviceSynchronize(); printf("...device synchronized.\n"); return 0; }
.file "tmpxft_0001ac5c_00000000-6_hello-part1.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z29__device_stub__Z10cuda_hellovv .type _Z29__device_stub__Z10cuda_hellovv, @function _Z29__device_stub__Z10cuda_hellovv: .LFB2082: .cfi_startproc endbr64 subq $88, %rsp .cfi_def_cfa_offset 96 movq %fs:40, %rax movq %rax, 72(%rsp) xorl %eax, %eax movl $1, 16(%rsp) movl $1, 20(%rsp) movl $1, 24(%rsp) movl $1, 28(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) leaq 8(%rsp), %rcx movq %rsp, %rdx leaq 28(%rsp), %rsi leaq 16(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 72(%rsp), %rax subq %fs:40, %rax jne .L8 addq $88, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 8(%rsp) .cfi_def_cfa_offset 104 pushq 8(%rsp) .cfi_def_cfa_offset 112 leaq 80(%rsp), %r9 movq 44(%rsp), %rcx movl 52(%rsp), %r8d movq 32(%rsp), %rsi movl 40(%rsp), %edx leaq _Z10cuda_hellov(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 96 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2082: .size _Z29__device_stub__Z10cuda_hellovv, .-_Z29__device_stub__Z10cuda_hellovv .globl _Z10cuda_hellov .type _Z10cuda_hellov, @function _Z10cuda_hellov: .LFB2083: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z29__device_stub__Z10cuda_hellovv addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2083: .size _Z10cuda_hellov, .-_Z10cuda_hellov .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "Calling cuda_hello...\n" .LC1: .string "...device synchronized.\n" .text .globl main .type main, @function main: .LFB2057: .cfi_startproc endbr64 subq $40, %rsp .cfi_def_cfa_offset 48 leaq .LC0(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $1, 20(%rsp) movl $1, 24(%rsp) movl $1, 8(%rsp) movl $1, 12(%rsp) movl $0, %r9d movl $0, %r8d movq 20(%rsp), %rdx movl $1, %ecx movq 8(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L14 .L12: call cudaDeviceSynchronize@PLT leaq .LC1(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $0, %eax addq $40, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L14: .cfi_restore_state call _Z29__device_stub__Z10cuda_hellovv jmp .L12 .cfi_endproc .LFE2057: .size main, .-main .section .rodata.str1.1 .LC2: .string "_Z10cuda_hellov" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC2(%rip), %rdx movq %rdx, %rcx leaq _Z10cuda_hellov(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include <stdio.h> #include <cuda.h> __global__ void cuda_hello(void) { // print a character buffer from the GPU! printf("Hello, world!\n"); } int main(void) { printf("Calling cuda_hello...\n"); // call the CUDA kernel from the GPU cuda_hello<<<1,1>>>(); // wait for the kernel to finish cudaDeviceSynchronize(); printf("...device synchronized.\n"); return 0; }
#include <stdio.h> #include <hip/hip_runtime.h> __global__ void cuda_hello(void) { // print a character buffer from the GPU! printf("Hello, world!\n"); } int main(void) { printf("Calling cuda_hello...\n"); // call the CUDA kernel from the GPU cuda_hello<<<1,1>>>(); // wait for the kernel to finish hipDeviceSynchronize(); printf("...device synchronized.\n"); return 0; }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <stdio.h> #include <hip/hip_runtime.h> __global__ void cuda_hello(void) { // print a character buffer from the GPU! printf("Hello, world!\n"); } int main(void) { printf("Calling cuda_hello...\n"); // call the CUDA kernel from the GPU cuda_hello<<<1,1>>>(); // wait for the kernel to finish hipDeviceSynchronize(); printf("...device synchronized.\n"); return 0; }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z10cuda_hellov .globl _Z10cuda_hellov .p2align 8 .type _Z10cuda_hellov,@function _Z10cuda_hellov: s_load_b64 s[2:3], s[0:1], 0x50 v_mbcnt_lo_u32_b32 v20, -1, 0 v_mov_b32_e32 v6, 0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20 v_readfirstlane_b32 s0, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_eq_u32_e64 s0, s0, v4 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_6 v_mov_b32_e32 v0, 0 s_mov_b32 s4, exec_lo s_waitcnt lgkmcnt(0) global_load_b64 v[8:9], v0, s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[1:2], v0, s[2:3] offset:40 global_load_b64 v[5:6], v0, s[2:3] s_waitcnt vmcnt(1) v_and_b32_e32 v1, v1, v8 v_and_b32_e32 v2, v2, v9 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_hi_u32 v3, v1, 24 v_mul_lo_u32 v2, v2, 24 v_mul_lo_u32 v1, v1, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v2, v3, v2 s_waitcnt vmcnt(0) v_add_co_u32 v1, vcc_lo, v5, v1 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo global_load_b64 v[6:7], v[1:2], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[6:7], v[8:9] s_cbranch_execz .LBB0_5 s_mov_b32 s5, 0 .p2align 6 .LBB0_3: s_sleep 1 s_clause 0x1 global_load_b64 v[1:2], v0, s[2:3] offset:40 global_load_b64 v[10:11], v0, s[2:3] v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v1, v1, v8 v_and_b32_e32 v7, v2, v9 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11] v_mov_b32_e32 v1, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2] v_mov_b32_e32 v6, v2 global_load_b64 v[6:7], v[5:6], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9] s_or_b32 s5, vcc_lo, s5 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s5 s_cbranch_execnz .LBB0_3 s_or_b32 exec_lo, exec_lo, s5 .LBB0_5: s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s4 .LBB0_6: s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s1 v_mov_b32_e32 v5, 0 v_readfirstlane_b32 s4, v6 v_readfirstlane_b32 s5, v7 s_mov_b32 s8, exec_lo s_waitcnt lgkmcnt(0) s_clause 0x1 global_load_b64 v[8:9], v5, s[2:3] offset:40 global_load_b128 v[0:3], v5, s[2:3] s_waitcnt vmcnt(1) v_readfirstlane_b32 s6, v8 v_readfirstlane_b32 s7, v9 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[6:7], s[4:5], s[6:7] s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_8 v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0 s_mul_i32 s8, s7, 24 s_mul_hi_u32 s9, s6, 24 v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1 s_add_i32 s9, s9, s8 s_mul_i32 s8, s6, 24 s_waitcnt vmcnt(0) v_add_co_u32 v10, vcc_lo, v0, s8 v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo global_store_b128 v[10:11], v[6:9], off offset:8 .LBB0_8: s_or_b32 exec_lo, exec_lo, s1 s_lshl_b64 s[8:9], s[6:7], 12 v_lshlrev_b64 v[4:5], 6, v[4:5] s_waitcnt vmcnt(0) v_add_co_u32 v2, vcc_lo, v2, s8 v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo v_mov_b32_e32 v3, 0 s_mov_b32 s8, 0 s_delay_alu instid0(VALU_DEP_3) v_add_co_u32 v6, vcc_lo, v2, v4 v_mov_b32_e32 v2, 33 s_mov_b32 s9, s8 s_mov_b32 s10, s8 s_mov_b32 s11, s8 v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo v_mov_b32_e32 v4, v3 v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8 v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10 v_mov_b32_e32 v11, s11 s_clause 0x3 global_store_b128 v[6:7], v[2:5], off global_store_b128 v[6:7], v[8:11], off offset:16 global_store_b128 v[6:7], v[8:11], off offset:32 global_store_b128 v[6:7], v[8:11], off offset:48 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_16 v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4 v_mov_b32_e32 v12, s5 s_clause 0x1 global_load_b64 v[13:14], v10, s[2:3] offset:32 glc global_load_b64 v[2:3], v10, s[2:3] offset:40 s_waitcnt vmcnt(0) v_readfirstlane_b32 s8, v2 v_readfirstlane_b32 s9, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[8:9], s[8:9], s[4:5] s_mul_i32 s9, s9, 24 s_mul_hi_u32 s10, s8, 24 s_mul_i32 s8, s8, 24 s_add_i32 s10, s10, s9 v_add_co_u32 v8, vcc_lo, v0, s8 v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo s_mov_b32 s8, exec_lo global_store_b64 v[8:9], v[13:14], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[4:5], v[13:14] s_cbranch_execz .LBB0_12 s_mov_b32 s9, 0 .LBB0_11: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5 s_sleep 1 global_store_b64 v[8:9], v[4:5], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5] v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2 s_or_b32 s9, vcc_lo, s9 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s9 s_cbranch_execnz .LBB0_11 .LBB0_12: s_or_b32 exec_lo, exec_lo, s8 v_mov_b32_e32 v2, 0 s_mov_b32 s9, exec_lo s_mov_b32 s8, exec_lo v_mbcnt_lo_u32_b32 v4, s9, 0 global_load_b64 v[2:3], v2, s[2:3] offset:16 v_cmpx_eq_u32_e32 0, v4 s_cbranch_execz .LBB0_14 s_bcnt1_i32_b32 s9, s9 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9 s_waitcnt vmcnt(0) global_atomic_add_u64 v[2:3], v[4:5], off offset:8 .LBB0_14: s_or_b32 exec_lo, exec_lo, s8 s_waitcnt vmcnt(0) global_load_b64 v[4:5], v[2:3], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5] s_cbranch_vccnz .LBB0_16 global_load_b32 v2, v[2:3], off offset:24 v_mov_b32_e32 v3, 0 s_waitcnt vmcnt(0) v_readfirstlane_b32 s8, v2 s_waitcnt_vscnt null, 0x0 global_store_b64 v[4:5], v[2:3], off s_and_b32 m0, s8, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB0_16: s_or_b32 exec_lo, exec_lo, s1 s_mul_i32 s1, s7, 24 s_mul_hi_u32 s7, s6, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s7, s7, s1 s_mul_i32 s1, s6, 24 v_add_co_u32 v0, vcc_lo, v0, s1 v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v0, 20 v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo s_branch .LBB0_20 .p2align 6 .LBB0_17: s_or_b32 exec_lo, exec_lo, s1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s1, v2 s_cmp_eq_u32 s1, 0 s_cbranch_scc1 .LBB0_19 s_sleep 1 s_cbranch_execnz .LBB0_20 s_branch .LBB0_22 .p2align 6 .LBB0_19: s_branch .LBB0_22 .LBB0_20: v_mov_b32_e32 v2, 1 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_17 global_load_b32 v2, v[0:1], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v2, 1, v2 s_branch .LBB0_17 .LBB0_22: global_load_b64 v[22:23], v[6:7], off s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_26 v_mov_b32_e32 v6, 0 s_clause 0x2 global_load_b64 v[2:3], v6, s[2:3] offset:40 global_load_b64 v[7:8], v6, s[2:3] offset:24 glc global_load_b64 v[4:5], v6, s[2:3] s_waitcnt vmcnt(2) v_add_co_u32 v9, vcc_lo, v2, 1 v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v9, s4 v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1] v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9 v_and_b32_e32 v3, v1, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v2, v0, v2 v_mul_lo_u32 v3, v3, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_hi_u32 v9, v2, 24 v_mul_lo_u32 v2, v2, 24 v_add_nc_u32_e32 v3, v9, v3 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_co_u32 v4, vcc_lo, v4, v2 v_mov_b32_e32 v2, v7 v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo v_mov_b32_e32 v3, v8 global_store_b64 v[4:5], v[7:8], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_26 s_mov_b32 s0, 0 .LBB0_25: s_sleep 1 global_store_b64 v[4:5], v[2:3], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3] v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB0_25 .LBB0_26: s_or_b32 exec_lo, exec_lo, s1 s_getpc_b64 s[4:5] s_add_u32 s4, s4, .str@rel32@lo+4 s_addc_u32 s5, s5, .str@rel32@hi+12 s_mov_b32 s0, -1 s_cmp_lg_u64 s[4:5], 0 s_cbranch_scc0 .LBB0_105 s_waitcnt vmcnt(0) v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22 v_mov_b32_e32 v25, 0 s_mov_b64 s[6:7], 15 s_branch .LBB0_29 .LBB0_28: s_or_b32 exec_lo, exec_lo, s1 s_sub_u32 s6, s6, s8 s_subb_u32 s7, s7, s9 s_add_u32 s4, s4, s8 s_addc_u32 s5, s5, s9 s_cmp_lg_u64 s[6:7], 0 s_cbranch_scc0 .LBB0_104 .LBB0_29: v_cmp_lt_u64_e64 s0, s[6:7], 56 s_delay_alu instid0(VALU_DEP_1) s_and_b32 s0, s0, exec_lo s_cselect_b32 s8, s6, 56 s_cselect_b32 s9, s7, 0 s_cmp_gt_u32 s8, 7 s_mov_b32 s0, -1 s_cbranch_scc1 .LBB0_34 v_mov_b32_e32 v2, 0 v_mov_b32_e32 v3, 0 s_cmp_eq_u32 s8, 0 s_cbranch_scc1 .LBB0_33 s_lshl_b64 s[0:1], s[8:9], 3 s_mov_b64 s[10:11], 0 s_mov_b64 s[12:13], s[4:5] .LBB0_32: global_load_u8 v4, v25, s[12:13] s_waitcnt vmcnt(0) v_and_b32_e32 v24, 0xffff, v4 s_delay_alu instid0(VALU_DEP_1) v_lshlrev_b64 v[4:5], s10, v[24:25] s_add_u32 s10, s10, 8 s_addc_u32 s11, s11, 0 s_add_u32 s12, s12, 1 s_addc_u32 s13, s13, 0 s_cmp_lg_u32 s0, s10 v_or_b32_e32 v2, v4, v2 v_or_b32_e32 v3, v5, v3 s_cbranch_scc1 .LBB0_32 .LBB0_33: s_mov_b32 s0, 0 s_mov_b32 s15, 0 .LBB0_34: s_and_not1_b32 vcc_lo, exec_lo, s0 s_mov_b64 s[0:1], s[4:5] s_cbranch_vccnz .LBB0_36 global_load_b64 v[2:3], v25, s[4:5] s_add_i32 s15, s8, -8 s_add_u32 s0, s4, 8 s_addc_u32 s1, s5, 0 .LBB0_36: s_cmp_gt_u32 s15, 7 s_cbranch_scc1 .LBB0_41 v_mov_b32_e32 v4, 0 v_mov_b32_e32 v5, 0 s_cmp_eq_u32 s15, 0 s_cbranch_scc1 .LBB0_40 s_mov_b64 s[10:11], 0 s_mov_b64 s[12:13], 0 .LBB0_39: s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s16, s0, s12 s_addc_u32 s17, s1, s13 s_add_u32 s12, s12, 1 global_load_u8 v6, v25, s[16:17] s_addc_u32 s13, s13, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v24, 0xffff, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[6:7], s10, v[24:25] s_add_u32 s10, s10, 8 s_addc_u32 s11, s11, 0 s_cmp_lg_u32 s15, s12 v_or_b32_e32 v4, v6, v4 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v5, v7, v5 s_cbranch_scc1 .LBB0_39 .LBB0_40: s_mov_b32 s14, 0 s_cbranch_execz .LBB0_42 s_branch .LBB0_43 .LBB0_41: .LBB0_42: global_load_b64 v[4:5], v25, s[0:1] s_add_i32 s14, s15, -8 s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 .LBB0_43: s_cmp_gt_u32 s14, 7 s_cbranch_scc1 .LBB0_48 v_mov_b32_e32 v6, 0 v_mov_b32_e32 v7, 0 s_cmp_eq_u32 s14, 0 s_cbranch_scc1 .LBB0_47 s_mov_b64 s[10:11], 0 s_mov_b64 s[12:13], 0 .LBB0_46: s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s16, s0, s12 s_addc_u32 s17, s1, s13 s_add_u32 s12, s12, 1 global_load_u8 v8, v25, s[16:17] s_addc_u32 s13, s13, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v24, 0xffff, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[8:9], s10, v[24:25] s_add_u32 s10, s10, 8 s_addc_u32 s11, s11, 0 s_cmp_lg_u32 s14, s12 v_or_b32_e32 v6, v8, v6 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v7, v9, v7 s_cbranch_scc1 .LBB0_46 .LBB0_47: s_mov_b32 s15, 0 s_cbranch_execz .LBB0_49 s_branch .LBB0_50 .LBB0_48: .LBB0_49: global_load_b64 v[6:7], v25, s[0:1] s_add_i32 s15, s14, -8 s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 .LBB0_50: s_cmp_gt_u32 s15, 7 s_cbranch_scc1 .LBB0_55 v_mov_b32_e32 v8, 0 v_mov_b32_e32 v9, 0 s_cmp_eq_u32 s15, 0 s_cbranch_scc1 .LBB0_54 s_mov_b64 s[10:11], 0 s_mov_b64 s[12:13], 0 .LBB0_53: s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s16, s0, s12 s_addc_u32 s17, s1, s13 s_add_u32 s12, s12, 1 global_load_u8 v10, v25, s[16:17] s_addc_u32 s13, s13, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v24, 0xffff, v10 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[10:11], s10, v[24:25] s_add_u32 s10, s10, 8 s_addc_u32 s11, s11, 0 s_cmp_lg_u32 s15, s12 v_or_b32_e32 v8, v10, v8 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v9, v11, v9 s_cbranch_scc1 .LBB0_53 .LBB0_54: s_mov_b32 s14, 0 s_cbranch_execz .LBB0_56 s_branch .LBB0_57 .LBB0_55: .LBB0_56: global_load_b64 v[8:9], v25, s[0:1] s_add_i32 s14, s15, -8 s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 .LBB0_57: s_cmp_gt_u32 s14, 7 s_cbranch_scc1 .LBB0_62 v_mov_b32_e32 v10, 0 v_mov_b32_e32 v11, 0 s_cmp_eq_u32 s14, 0 s_cbranch_scc1 .LBB0_61 s_mov_b64 s[10:11], 0 s_mov_b64 s[12:13], 0 .LBB0_60: s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s16, s0, s12 s_addc_u32 s17, s1, s13 s_add_u32 s12, s12, 1 global_load_u8 v12, v25, s[16:17] s_addc_u32 s13, s13, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v24, 0xffff, v12 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[12:13], s10, v[24:25] s_add_u32 s10, s10, 8 s_addc_u32 s11, s11, 0 s_cmp_lg_u32 s14, s12 v_or_b32_e32 v10, v12, v10 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v11, v13, v11 s_cbranch_scc1 .LBB0_60 .LBB0_61: s_mov_b32 s15, 0 s_cbranch_execz .LBB0_63 s_branch .LBB0_64 .LBB0_62: .LBB0_63: global_load_b64 v[10:11], v25, s[0:1] s_add_i32 s15, s14, -8 s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 .LBB0_64: s_cmp_gt_u32 s15, 7 s_cbranch_scc1 .LBB0_69 v_mov_b32_e32 v12, 0 v_mov_b32_e32 v13, 0 s_cmp_eq_u32 s15, 0 s_cbranch_scc1 .LBB0_68 s_mov_b64 s[10:11], 0 s_mov_b64 s[12:13], 0 .LBB0_67: s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s16, s0, s12 s_addc_u32 s17, s1, s13 s_add_u32 s12, s12, 1 global_load_u8 v14, v25, s[16:17] s_addc_u32 s13, s13, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v24, 0xffff, v14 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[14:15], s10, v[24:25] s_add_u32 s10, s10, 8 s_addc_u32 s11, s11, 0 s_cmp_lg_u32 s15, s12 v_or_b32_e32 v12, v14, v12 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v13, v15, v13 s_cbranch_scc1 .LBB0_67 .LBB0_68: s_mov_b32 s14, 0 s_cbranch_execz .LBB0_70 s_branch .LBB0_71 .LBB0_69: .LBB0_70: global_load_b64 v[12:13], v25, s[0:1] s_add_i32 s14, s15, -8 s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 .LBB0_71: s_cmp_gt_u32 s14, 7 s_cbranch_scc1 .LBB0_76 v_mov_b32_e32 v14, 0 v_mov_b32_e32 v15, 0 s_cmp_eq_u32 s14, 0 s_cbranch_scc1 .LBB0_75 s_mov_b64 s[10:11], 0 s_mov_b64 s[12:13], s[0:1] .LBB0_74: global_load_u8 v16, v25, s[12:13] s_add_i32 s14, s14, -1 s_waitcnt vmcnt(0) v_and_b32_e32 v24, 0xffff, v16 s_delay_alu instid0(VALU_DEP_1) v_lshlrev_b64 v[16:17], s10, v[24:25] s_add_u32 s10, s10, 8 s_addc_u32 s11, s11, 0 s_add_u32 s12, s12, 1 s_addc_u32 s13, s13, 0 s_cmp_lg_u32 s14, 0 v_or_b32_e32 v14, v16, v14 v_or_b32_e32 v15, v17, v15 s_cbranch_scc1 .LBB0_74 .LBB0_75: s_cbranch_execz .LBB0_77 s_branch .LBB0_78 .LBB0_76: .LBB0_77: global_load_b64 v[14:15], v25, s[0:1] .LBB0_78: v_mov_b32_e32 v24, v20 v_mov_b32_e32 v26, 0 v_mov_b32_e32 v27, 0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s0, v24 v_cmp_eq_u32_e64 s0, s0, v24 s_delay_alu instid0(VALU_DEP_1) s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_84 global_load_b64 v[18:19], v25, s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[16:17], v25, s[2:3] offset:40 global_load_b64 v[26:27], v25, s[2:3] s_mov_b32 s10, exec_lo s_waitcnt vmcnt(1) v_and_b32_e32 v17, v17, v19 v_and_b32_e32 v16, v16, v18 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_lo_u32 v17, v17, 24 v_mul_hi_u32 v21, v16, 24 v_mul_lo_u32 v16, v16, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v17, v21, v17 s_waitcnt vmcnt(0) v_add_co_u32 v16, vcc_lo, v26, v16 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo global_load_b64 v[16:17], v[16:17], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[26:27], v[18:19] s_cbranch_execz .LBB0_83 s_mov_b32 s11, 0 .p2align 6 .LBB0_81: s_sleep 1 s_clause 0x1 global_load_b64 v[16:17], v25, s[2:3] offset:40 global_load_b64 v[28:29], v25, s[2:3] v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_and_b32_e32 v16, v16, v18 s_waitcnt vmcnt(0) v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19 v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17] global_load_b64 v[16:17], v[26:27], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19] s_or_b32 s11, vcc_lo, s11 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s11 s_cbranch_execnz .LBB0_81 s_or_b32 exec_lo, exec_lo, s11 .LBB0_83: s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s10 .LBB0_84: s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s1 s_clause 0x1 global_load_b64 v[28:29], v25, s[2:3] offset:40 global_load_b128 v[16:19], v25, s[2:3] v_readfirstlane_b32 s10, v26 v_readfirstlane_b32 s11, v27 s_mov_b32 s14, exec_lo s_waitcnt vmcnt(1) v_readfirstlane_b32 s12, v28 v_readfirstlane_b32 s13, v29 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[12:13], s[10:11], s[12:13] s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_86 v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0 s_mul_i32 s14, s13, 24 s_mul_hi_u32 s15, s12, 24 v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1 s_add_i32 s15, s15, s14 s_mul_i32 s14, s12, 24 s_waitcnt vmcnt(0) v_add_co_u32 v30, vcc_lo, v16, s14 v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo global_store_b128 v[30:31], v[26:29], off offset:8 .LBB0_86: s_or_b32 exec_lo, exec_lo, s1 v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56 v_or_b32_e32 v21, 2, v0 s_lshl_b64 s[14:15], s[12:13], 12 v_lshlrev_b64 v[26:27], 6, v[24:25] s_lshl_b32 s1, s8, 2 s_delay_alu instid0(SALU_CYCLE_1) s_add_i32 s1, s1, 28 v_cndmask_b32_e32 v0, v21, v0, vcc_lo s_waitcnt vmcnt(0) v_add_co_u32 v18, vcc_lo, v18, s14 v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo s_and_b32 s1, s1, 0x1e0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_co_u32 v18, vcc_lo, v18, v26 v_and_or_b32 v0, v0, 0xffffff1f, s1 v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo s_clause 0x3 global_store_b128 v[18:19], v[0:3], off global_store_b128 v[18:19], v[4:7], off offset:16 global_store_b128 v[18:19], v[8:11], off offset:32 global_store_b128 v[18:19], v[12:15], off offset:48 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_94 s_clause 0x1 global_load_b64 v[8:9], v25, s[2:3] offset:32 glc global_load_b64 v[0:1], v25, s[2:3] offset:40 v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11 s_waitcnt vmcnt(0) v_readfirstlane_b32 s14, v0 v_readfirstlane_b32 s15, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[14:15], s[14:15], s[10:11] s_mul_i32 s15, s15, 24 s_mul_hi_u32 s16, s14, 24 s_mul_i32 s14, s14, 24 s_add_i32 s16, s16, s15 v_add_co_u32 v4, vcc_lo, v16, s14 v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo s_mov_b32 s14, exec_lo global_store_b64 v[4:5], v[8:9], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[2:3], v[8:9] s_cbranch_execz .LBB0_90 s_mov_b32 s15, 0 .LBB0_89: v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11 s_sleep 1 global_store_b64 v[4:5], v[2:3], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3] v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0 s_or_b32 s15, vcc_lo, s15 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s15 s_cbranch_execnz .LBB0_89 .LBB0_90: s_or_b32 exec_lo, exec_lo, s14 global_load_b64 v[0:1], v25, s[2:3] offset:16 s_mov_b32 s15, exec_lo s_mov_b32 s14, exec_lo v_mbcnt_lo_u32_b32 v2, s15, 0 s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v2 s_cbranch_execz .LBB0_92 s_bcnt1_i32_b32 s15, s15 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15 s_waitcnt vmcnt(0) global_atomic_add_u64 v[0:1], v[2:3], off offset:8 .LBB0_92: s_or_b32 exec_lo, exec_lo, s14 s_waitcnt vmcnt(0) global_load_b64 v[2:3], v[0:1], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3] s_cbranch_vccnz .LBB0_94 global_load_b32 v24, v[0:1], off offset:24 s_waitcnt vmcnt(0) v_readfirstlane_b32 s14, v24 s_waitcnt_vscnt null, 0x0 global_store_b64 v[2:3], v[24:25], off s_and_b32 m0, s14, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB0_94: s_or_b32 exec_lo, exec_lo, s1 s_mul_i32 s1, s13, 24 s_mul_hi_u32 s13, s12, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s13, s13, s1 s_mul_i32 s1, s12, 24 v_add_co_u32 v0, vcc_lo, v16, s1 v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v0, 20 v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo s_branch .LBB0_98 .p2align 6 .LBB0_95: s_or_b32 exec_lo, exec_lo, s1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s1, v2 s_cmp_eq_u32 s1, 0 s_cbranch_scc1 .LBB0_97 s_sleep 1 s_cbranch_execnz .LBB0_98 s_branch .LBB0_100 .p2align 6 .LBB0_97: s_branch .LBB0_100 .LBB0_98: v_mov_b32_e32 v2, 1 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_95 global_load_b32 v2, v[0:1], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v2, 1, v2 s_branch .LBB0_95 .LBB0_100: global_load_b64 v[0:1], v[18:19], off s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_28 s_clause 0x2 global_load_b64 v[4:5], v25, s[2:3] offset:40 global_load_b64 v[8:9], v25, s[2:3] offset:24 glc global_load_b64 v[6:7], v25, s[2:3] s_waitcnt vmcnt(2) v_add_co_u32 v10, vcc_lo, v4, 1 v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v2, vcc_lo, v10, s10 v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3] v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10 v_and_b32_e32 v5, v3, v5 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_and_b32_e32 v4, v2, v4 v_mul_hi_u32 v10, v4, 24 v_mul_lo_u32 v4, v4, 24 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_add_co_u32 v6, vcc_lo, v6, v4 v_mov_b32_e32 v4, v8 v_mul_lo_u32 v5, v5, 24 v_add_nc_u32_e32 v5, v10, v5 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo v_mov_b32_e32 v5, v9 global_store_b64 v[6:7], v[8:9], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_28 s_mov_b32 s0, 0 .LBB0_103: s_sleep 1 global_store_b64 v[6:7], v[4:5], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5] v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB0_103 s_branch .LBB0_28 .LBB0_104: s_mov_b32 s0, 0 .LBB0_105: s_delay_alu instid0(SALU_CYCLE_1) s_and_b32 vcc_lo, exec_lo, s0 s_cbranch_vccz .LBB0_132 v_readfirstlane_b32 s0, v20 v_mov_b32_e32 v4, 0 v_mov_b32_e32 v5, 0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_eq_u32_e64 s0, s0, v20 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_112 s_waitcnt vmcnt(0) v_mov_b32_e32 v0, 0 s_mov_b32 s4, exec_lo global_load_b64 v[6:7], v0, s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[1:2], v0, s[2:3] offset:40 global_load_b64 v[3:4], v0, s[2:3] s_waitcnt vmcnt(1) v_and_b32_e32 v1, v1, v6 v_and_b32_e32 v2, v2, v7 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_hi_u32 v5, v1, 24 v_mul_lo_u32 v2, v2, 24 v_mul_lo_u32 v1, v1, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v2, v5, v2 s_waitcnt vmcnt(0) v_add_co_u32 v1, vcc_lo, v3, v1 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo global_load_b64 v[4:5], v[1:2], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[4:5], v[6:7] s_cbranch_execz .LBB0_111 s_mov_b32 s5, 0 .p2align 6 .LBB0_109: s_sleep 1 s_clause 0x1 global_load_b64 v[1:2], v0, s[2:3] offset:40 global_load_b64 v[8:9], v0, s[2:3] v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_and_b32_e32 v1, v1, v6 s_waitcnt vmcnt(0) v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7 v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2] global_load_b64 v[4:5], v[3:4], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7] s_or_b32 s5, vcc_lo, s5 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s5 s_cbranch_execnz .LBB0_109 s_or_b32 exec_lo, exec_lo, s5 .LBB0_111: s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s4 .LBB0_112: s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s1 v_mov_b32_e32 v21, 0 v_readfirstlane_b32 s4, v4 v_readfirstlane_b32 s5, v5 s_mov_b32 s8, exec_lo s_clause 0x1 global_load_b64 v[6:7], v21, s[2:3] offset:40 global_load_b128 v[0:3], v21, s[2:3] s_waitcnt vmcnt(1) v_readfirstlane_b32 s6, v6 v_readfirstlane_b32 s7, v7 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[6:7], s[4:5], s[6:7] s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_114 v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0 s_mul_i32 s8, s7, 24 s_mul_hi_u32 s9, s6, 24 v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1 s_add_i32 s9, s9, s8 s_mul_i32 s8, s6, 24 s_waitcnt vmcnt(0) v_add_co_u32 v8, vcc_lo, v0, s8 v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo global_store_b128 v[8:9], v[4:7], off offset:8 .LBB0_114: s_or_b32 exec_lo, exec_lo, s1 s_lshl_b64 s[8:9], s[6:7], 12 v_and_or_b32 v22, v22, 0xffffff1d, 34 s_waitcnt vmcnt(0) v_add_co_u32 v4, vcc_lo, v2, s8 v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo v_lshlrev_b64 v[2:3], 6, v[20:21] s_mov_b32 s8, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) s_mov_b32 s9, s8 s_mov_b32 s10, s8 s_mov_b32 s11, s8 v_add_co_u32 v8, vcc_lo, v4, v2 v_mov_b32_e32 v6, 0 v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11 v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10 s_delay_alu instid0(VALU_DEP_4) v_mov_b32_e32 v7, v6 s_clause 0x4 global_store_b64 v[8:9], v[22:23], off global_store_b128 v[8:9], v[2:5], off offset:8 global_store_b128 v[8:9], v[2:5], off offset:24 global_store_b128 v[8:9], v[2:5], off offset:40 global_store_b64 v[8:9], v[6:7], off offset:56 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_122 v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4 v_mov_b32_e32 v10, s5 s_clause 0x1 global_load_b64 v[11:12], v8, s[2:3] offset:32 glc global_load_b64 v[2:3], v8, s[2:3] offset:40 s_waitcnt vmcnt(0) v_readfirstlane_b32 s8, v2 v_readfirstlane_b32 s9, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[8:9], s[8:9], s[4:5] s_mul_i32 s9, s9, 24 s_mul_hi_u32 s10, s8, 24 s_mul_i32 s8, s8, 24 s_add_i32 s10, s10, s9 v_add_co_u32 v6, vcc_lo, v0, s8 v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo s_mov_b32 s8, exec_lo global_store_b64 v[6:7], v[11:12], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[4:5], v[11:12] s_cbranch_execz .LBB0_118 s_mov_b32 s9, 0 .LBB0_117: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5 s_sleep 1 global_store_b64 v[6:7], v[4:5], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5] v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2 s_or_b32 s9, vcc_lo, s9 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s9 s_cbranch_execnz .LBB0_117 .LBB0_118: s_or_b32 exec_lo, exec_lo, s8 v_mov_b32_e32 v2, 0 s_mov_b32 s9, exec_lo s_mov_b32 s8, exec_lo v_mbcnt_lo_u32_b32 v4, s9, 0 global_load_b64 v[2:3], v2, s[2:3] offset:16 v_cmpx_eq_u32_e32 0, v4 s_cbranch_execz .LBB0_120 s_bcnt1_i32_b32 s9, s9 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9 s_waitcnt vmcnt(0) global_atomic_add_u64 v[2:3], v[4:5], off offset:8 .LBB0_120: s_or_b32 exec_lo, exec_lo, s8 s_waitcnt vmcnt(0) global_load_b64 v[4:5], v[2:3], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5] s_cbranch_vccnz .LBB0_122 global_load_b32 v2, v[2:3], off offset:24 v_mov_b32_e32 v3, 0 s_waitcnt vmcnt(0) v_readfirstlane_b32 s8, v2 s_waitcnt_vscnt null, 0x0 global_store_b64 v[4:5], v[2:3], off s_and_b32 m0, s8, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB0_122: s_or_b32 exec_lo, exec_lo, s1 s_mul_i32 s1, s7, 24 s_mul_hi_u32 s7, s6, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s7, s7, s1 s_mul_i32 s1, s6, 24 v_add_co_u32 v0, vcc_lo, v0, s1 v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v0, 20 v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo s_branch .LBB0_126 .p2align 6 .LBB0_123: s_or_b32 exec_lo, exec_lo, s1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s1, v2 s_cmp_eq_u32 s1, 0 s_cbranch_scc1 .LBB0_125 s_sleep 1 s_cbranch_execnz .LBB0_126 s_branch .LBB0_128 .p2align 6 .LBB0_125: s_branch .LBB0_128 .LBB0_126: v_mov_b32_e32 v2, 1 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_123 global_load_b32 v2, v[0:1], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v2, 1, v2 s_branch .LBB0_123 .LBB0_128: s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_132 v_mov_b32_e32 v6, 0 s_clause 0x2 global_load_b64 v[2:3], v6, s[2:3] offset:40 global_load_b64 v[7:8], v6, s[2:3] offset:24 glc global_load_b64 v[4:5], v6, s[2:3] s_waitcnt vmcnt(2) v_add_co_u32 v9, vcc_lo, v2, 1 v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v9, s4 v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1] v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9 v_and_b32_e32 v3, v1, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v2, v0, v2 v_mul_lo_u32 v3, v3, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_hi_u32 v9, v2, 24 v_mul_lo_u32 v2, v2, 24 v_add_nc_u32_e32 v3, v9, v3 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_co_u32 v4, vcc_lo, v4, v2 v_mov_b32_e32 v2, v7 v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo v_mov_b32_e32 v3, v8 global_store_b64 v[4:5], v[7:8], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_132 s_mov_b32 s0, 0 .LBB0_131: s_sleep 1 global_store_b64 v[4:5], v[2:3], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3] v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB0_131 .LBB0_132: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z10cuda_hellov .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 256 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 32 .amdhsa_next_free_sgpr 18 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z10cuda_hellov, .Lfunc_end0-_Z10cuda_hellov .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type .str,@object .section .rodata.str1.1,"aMS",@progbits,1 .str: .asciz "Hello, world!\n" .size .str, 15 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .offset: 0 .size: 4 .value_kind: hidden_block_count_x - .offset: 4 .size: 4 .value_kind: hidden_block_count_y - .offset: 8 .size: 4 .value_kind: hidden_block_count_z - .offset: 12 .size: 2 .value_kind: hidden_group_size_x - .offset: 14 .size: 2 .value_kind: hidden_group_size_y - .offset: 16 .size: 2 .value_kind: hidden_group_size_z - .offset: 18 .size: 2 .value_kind: hidden_remainder_x - .offset: 20 .size: 2 .value_kind: hidden_remainder_y - .offset: 22 .size: 2 .value_kind: hidden_remainder_z - .offset: 40 .size: 8 .value_kind: hidden_global_offset_x - .offset: 48 .size: 8 .value_kind: hidden_global_offset_y - .offset: 56 .size: 8 .value_kind: hidden_global_offset_z - .offset: 64 .size: 2 .value_kind: hidden_grid_dims - .offset: 80 .size: 8 .value_kind: hidden_hostcall_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 256 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z10cuda_hellov .private_segment_fixed_size: 0 .sgpr_count: 20 .sgpr_spill_count: 0 .symbol: _Z10cuda_hellov.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 32 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <stdio.h> #include <hip/hip_runtime.h> __global__ void cuda_hello(void) { // print a character buffer from the GPU! printf("Hello, world!\n"); } int main(void) { printf("Calling cuda_hello...\n"); // call the CUDA kernel from the GPU cuda_hello<<<1,1>>>(); // wait for the kernel to finish hipDeviceSynchronize(); printf("...device synchronized.\n"); return 0; }
.text .file "hello-part1.hip" .globl _Z25__device_stub__cuda_hellov # -- Begin function _Z25__device_stub__cuda_hellov .p2align 4, 0x90 .type _Z25__device_stub__cuda_hellov,@function _Z25__device_stub__cuda_hellov: # @_Z25__device_stub__cuda_hellov .cfi_startproc # %bb.0: subq $56, %rsp .cfi_def_cfa_offset 64 leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 48(%rsp), %r9 movl $_Z10cuda_hellov, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $72, %rsp .cfi_adjust_cfa_offset -72 retq .Lfunc_end0: .size _Z25__device_stub__cuda_hellov, .Lfunc_end0-_Z25__device_stub__cuda_hellov .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: subq $56, %rsp .cfi_def_cfa_offset 64 movl $.Lstr, %edi callq puts@PLT movabsq $4294967297, %rdi # imm = 0x100000001 movl $1, %esi movq %rdi, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_2 # %bb.1: leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 48(%rsp), %r9 movl $_Z10cuda_hellov, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_2: callq hipDeviceSynchronize movl $.Lstr.1, %edi callq puts@PLT xorl %eax, %eax addq $56, %rsp .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z10cuda_hellov, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z10cuda_hellov,@object # @_Z10cuda_hellov .section .rodata,"a",@progbits .globl _Z10cuda_hellov .p2align 3, 0x0 _Z10cuda_hellov: .quad _Z25__device_stub__cuda_hellov .size _Z10cuda_hellov, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z10cuda_hellov" .size .L__unnamed_1, 16 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .type .Lstr,@object # @str .section .rodata.str1.1,"aMS",@progbits,1 .Lstr: .asciz "Calling cuda_hello..." .size .Lstr, 22 .type .Lstr.1,@object # @str.1 .Lstr.1: .asciz "...device synchronized." .size .Lstr.1, 24 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z25__device_stub__cuda_hellov .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z10cuda_hellov .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z10cuda_hellov .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */ /* 0x000fe20000000f00 */ /*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */ /* 0x000fe200078e00ff */ /*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */ /* 0x000fe2000001ff00 */ /*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */ /* 0x000fe200078e00ff */ /*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */ /* 0x00006c0000000a00 */ /*0060*/ LEPC R8 ; /* 0x000000000008734e */ /* 0x000fe40000000000 */ /*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */ /* 0x000fe40000000f00 */ /*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */ /* 0x000fe40000000f00 */ /*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */ /* 0x000fe40000000f00 */ /*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */ /* 0x001fc40000000f00 */ /*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */ /* 0x000fc8000791e108 */ /*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */ /* 0x000fc800007e2509 */ /*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */ /* 0x002fea0003c00000 */ /*00e0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0100*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0110*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0120*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0130*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0140*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0150*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0160*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0170*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z10cuda_hellov .globl _Z10cuda_hellov .p2align 8 .type _Z10cuda_hellov,@function _Z10cuda_hellov: s_load_b64 s[2:3], s[0:1], 0x50 v_mbcnt_lo_u32_b32 v20, -1, 0 v_mov_b32_e32 v6, 0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20 v_readfirstlane_b32 s0, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_eq_u32_e64 s0, s0, v4 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_6 v_mov_b32_e32 v0, 0 s_mov_b32 s4, exec_lo s_waitcnt lgkmcnt(0) global_load_b64 v[8:9], v0, s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[1:2], v0, s[2:3] offset:40 global_load_b64 v[5:6], v0, s[2:3] s_waitcnt vmcnt(1) v_and_b32_e32 v1, v1, v8 v_and_b32_e32 v2, v2, v9 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_hi_u32 v3, v1, 24 v_mul_lo_u32 v2, v2, 24 v_mul_lo_u32 v1, v1, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v2, v3, v2 s_waitcnt vmcnt(0) v_add_co_u32 v1, vcc_lo, v5, v1 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo global_load_b64 v[6:7], v[1:2], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[6:7], v[8:9] s_cbranch_execz .LBB0_5 s_mov_b32 s5, 0 .p2align 6 .LBB0_3: s_sleep 1 s_clause 0x1 global_load_b64 v[1:2], v0, s[2:3] offset:40 global_load_b64 v[10:11], v0, s[2:3] v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v1, v1, v8 v_and_b32_e32 v7, v2, v9 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11] v_mov_b32_e32 v1, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2] v_mov_b32_e32 v6, v2 global_load_b64 v[6:7], v[5:6], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9] s_or_b32 s5, vcc_lo, s5 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s5 s_cbranch_execnz .LBB0_3 s_or_b32 exec_lo, exec_lo, s5 .LBB0_5: s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s4 .LBB0_6: s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s1 v_mov_b32_e32 v5, 0 v_readfirstlane_b32 s4, v6 v_readfirstlane_b32 s5, v7 s_mov_b32 s8, exec_lo s_waitcnt lgkmcnt(0) s_clause 0x1 global_load_b64 v[8:9], v5, s[2:3] offset:40 global_load_b128 v[0:3], v5, s[2:3] s_waitcnt vmcnt(1) v_readfirstlane_b32 s6, v8 v_readfirstlane_b32 s7, v9 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[6:7], s[4:5], s[6:7] s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_8 v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0 s_mul_i32 s8, s7, 24 s_mul_hi_u32 s9, s6, 24 v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1 s_add_i32 s9, s9, s8 s_mul_i32 s8, s6, 24 s_waitcnt vmcnt(0) v_add_co_u32 v10, vcc_lo, v0, s8 v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo global_store_b128 v[10:11], v[6:9], off offset:8 .LBB0_8: s_or_b32 exec_lo, exec_lo, s1 s_lshl_b64 s[8:9], s[6:7], 12 v_lshlrev_b64 v[4:5], 6, v[4:5] s_waitcnt vmcnt(0) v_add_co_u32 v2, vcc_lo, v2, s8 v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo v_mov_b32_e32 v3, 0 s_mov_b32 s8, 0 s_delay_alu instid0(VALU_DEP_3) v_add_co_u32 v6, vcc_lo, v2, v4 v_mov_b32_e32 v2, 33 s_mov_b32 s9, s8 s_mov_b32 s10, s8 s_mov_b32 s11, s8 v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo v_mov_b32_e32 v4, v3 v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8 v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10 v_mov_b32_e32 v11, s11 s_clause 0x3 global_store_b128 v[6:7], v[2:5], off global_store_b128 v[6:7], v[8:11], off offset:16 global_store_b128 v[6:7], v[8:11], off offset:32 global_store_b128 v[6:7], v[8:11], off offset:48 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_16 v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4 v_mov_b32_e32 v12, s5 s_clause 0x1 global_load_b64 v[13:14], v10, s[2:3] offset:32 glc global_load_b64 v[2:3], v10, s[2:3] offset:40 s_waitcnt vmcnt(0) v_readfirstlane_b32 s8, v2 v_readfirstlane_b32 s9, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[8:9], s[8:9], s[4:5] s_mul_i32 s9, s9, 24 s_mul_hi_u32 s10, s8, 24 s_mul_i32 s8, s8, 24 s_add_i32 s10, s10, s9 v_add_co_u32 v8, vcc_lo, v0, s8 v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo s_mov_b32 s8, exec_lo global_store_b64 v[8:9], v[13:14], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[4:5], v[13:14] s_cbranch_execz .LBB0_12 s_mov_b32 s9, 0 .LBB0_11: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5 s_sleep 1 global_store_b64 v[8:9], v[4:5], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5] v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2 s_or_b32 s9, vcc_lo, s9 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s9 s_cbranch_execnz .LBB0_11 .LBB0_12: s_or_b32 exec_lo, exec_lo, s8 v_mov_b32_e32 v2, 0 s_mov_b32 s9, exec_lo s_mov_b32 s8, exec_lo v_mbcnt_lo_u32_b32 v4, s9, 0 global_load_b64 v[2:3], v2, s[2:3] offset:16 v_cmpx_eq_u32_e32 0, v4 s_cbranch_execz .LBB0_14 s_bcnt1_i32_b32 s9, s9 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9 s_waitcnt vmcnt(0) global_atomic_add_u64 v[2:3], v[4:5], off offset:8 .LBB0_14: s_or_b32 exec_lo, exec_lo, s8 s_waitcnt vmcnt(0) global_load_b64 v[4:5], v[2:3], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5] s_cbranch_vccnz .LBB0_16 global_load_b32 v2, v[2:3], off offset:24 v_mov_b32_e32 v3, 0 s_waitcnt vmcnt(0) v_readfirstlane_b32 s8, v2 s_waitcnt_vscnt null, 0x0 global_store_b64 v[4:5], v[2:3], off s_and_b32 m0, s8, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB0_16: s_or_b32 exec_lo, exec_lo, s1 s_mul_i32 s1, s7, 24 s_mul_hi_u32 s7, s6, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s7, s7, s1 s_mul_i32 s1, s6, 24 v_add_co_u32 v0, vcc_lo, v0, s1 v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v0, 20 v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo s_branch .LBB0_20 .p2align 6 .LBB0_17: s_or_b32 exec_lo, exec_lo, s1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s1, v2 s_cmp_eq_u32 s1, 0 s_cbranch_scc1 .LBB0_19 s_sleep 1 s_cbranch_execnz .LBB0_20 s_branch .LBB0_22 .p2align 6 .LBB0_19: s_branch .LBB0_22 .LBB0_20: v_mov_b32_e32 v2, 1 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_17 global_load_b32 v2, v[0:1], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v2, 1, v2 s_branch .LBB0_17 .LBB0_22: global_load_b64 v[22:23], v[6:7], off s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_26 v_mov_b32_e32 v6, 0 s_clause 0x2 global_load_b64 v[2:3], v6, s[2:3] offset:40 global_load_b64 v[7:8], v6, s[2:3] offset:24 glc global_load_b64 v[4:5], v6, s[2:3] s_waitcnt vmcnt(2) v_add_co_u32 v9, vcc_lo, v2, 1 v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v9, s4 v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1] v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9 v_and_b32_e32 v3, v1, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v2, v0, v2 v_mul_lo_u32 v3, v3, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_hi_u32 v9, v2, 24 v_mul_lo_u32 v2, v2, 24 v_add_nc_u32_e32 v3, v9, v3 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_co_u32 v4, vcc_lo, v4, v2 v_mov_b32_e32 v2, v7 v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo v_mov_b32_e32 v3, v8 global_store_b64 v[4:5], v[7:8], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_26 s_mov_b32 s0, 0 .LBB0_25: s_sleep 1 global_store_b64 v[4:5], v[2:3], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3] v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB0_25 .LBB0_26: s_or_b32 exec_lo, exec_lo, s1 s_getpc_b64 s[4:5] s_add_u32 s4, s4, .str@rel32@lo+4 s_addc_u32 s5, s5, .str@rel32@hi+12 s_mov_b32 s0, -1 s_cmp_lg_u64 s[4:5], 0 s_cbranch_scc0 .LBB0_105 s_waitcnt vmcnt(0) v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22 v_mov_b32_e32 v25, 0 s_mov_b64 s[6:7], 15 s_branch .LBB0_29 .LBB0_28: s_or_b32 exec_lo, exec_lo, s1 s_sub_u32 s6, s6, s8 s_subb_u32 s7, s7, s9 s_add_u32 s4, s4, s8 s_addc_u32 s5, s5, s9 s_cmp_lg_u64 s[6:7], 0 s_cbranch_scc0 .LBB0_104 .LBB0_29: v_cmp_lt_u64_e64 s0, s[6:7], 56 s_delay_alu instid0(VALU_DEP_1) s_and_b32 s0, s0, exec_lo s_cselect_b32 s8, s6, 56 s_cselect_b32 s9, s7, 0 s_cmp_gt_u32 s8, 7 s_mov_b32 s0, -1 s_cbranch_scc1 .LBB0_34 v_mov_b32_e32 v2, 0 v_mov_b32_e32 v3, 0 s_cmp_eq_u32 s8, 0 s_cbranch_scc1 .LBB0_33 s_lshl_b64 s[0:1], s[8:9], 3 s_mov_b64 s[10:11], 0 s_mov_b64 s[12:13], s[4:5] .LBB0_32: global_load_u8 v4, v25, s[12:13] s_waitcnt vmcnt(0) v_and_b32_e32 v24, 0xffff, v4 s_delay_alu instid0(VALU_DEP_1) v_lshlrev_b64 v[4:5], s10, v[24:25] s_add_u32 s10, s10, 8 s_addc_u32 s11, s11, 0 s_add_u32 s12, s12, 1 s_addc_u32 s13, s13, 0 s_cmp_lg_u32 s0, s10 v_or_b32_e32 v2, v4, v2 v_or_b32_e32 v3, v5, v3 s_cbranch_scc1 .LBB0_32 .LBB0_33: s_mov_b32 s0, 0 s_mov_b32 s15, 0 .LBB0_34: s_and_not1_b32 vcc_lo, exec_lo, s0 s_mov_b64 s[0:1], s[4:5] s_cbranch_vccnz .LBB0_36 global_load_b64 v[2:3], v25, s[4:5] s_add_i32 s15, s8, -8 s_add_u32 s0, s4, 8 s_addc_u32 s1, s5, 0 .LBB0_36: s_cmp_gt_u32 s15, 7 s_cbranch_scc1 .LBB0_41 v_mov_b32_e32 v4, 0 v_mov_b32_e32 v5, 0 s_cmp_eq_u32 s15, 0 s_cbranch_scc1 .LBB0_40 s_mov_b64 s[10:11], 0 s_mov_b64 s[12:13], 0 .LBB0_39: s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s16, s0, s12 s_addc_u32 s17, s1, s13 s_add_u32 s12, s12, 1 global_load_u8 v6, v25, s[16:17] s_addc_u32 s13, s13, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v24, 0xffff, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[6:7], s10, v[24:25] s_add_u32 s10, s10, 8 s_addc_u32 s11, s11, 0 s_cmp_lg_u32 s15, s12 v_or_b32_e32 v4, v6, v4 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v5, v7, v5 s_cbranch_scc1 .LBB0_39 .LBB0_40: s_mov_b32 s14, 0 s_cbranch_execz .LBB0_42 s_branch .LBB0_43 .LBB0_41: .LBB0_42: global_load_b64 v[4:5], v25, s[0:1] s_add_i32 s14, s15, -8 s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 .LBB0_43: s_cmp_gt_u32 s14, 7 s_cbranch_scc1 .LBB0_48 v_mov_b32_e32 v6, 0 v_mov_b32_e32 v7, 0 s_cmp_eq_u32 s14, 0 s_cbranch_scc1 .LBB0_47 s_mov_b64 s[10:11], 0 s_mov_b64 s[12:13], 0 .LBB0_46: s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s16, s0, s12 s_addc_u32 s17, s1, s13 s_add_u32 s12, s12, 1 global_load_u8 v8, v25, s[16:17] s_addc_u32 s13, s13, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v24, 0xffff, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[8:9], s10, v[24:25] s_add_u32 s10, s10, 8 s_addc_u32 s11, s11, 0 s_cmp_lg_u32 s14, s12 v_or_b32_e32 v6, v8, v6 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v7, v9, v7 s_cbranch_scc1 .LBB0_46 .LBB0_47: s_mov_b32 s15, 0 s_cbranch_execz .LBB0_49 s_branch .LBB0_50 .LBB0_48: .LBB0_49: global_load_b64 v[6:7], v25, s[0:1] s_add_i32 s15, s14, -8 s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 .LBB0_50: s_cmp_gt_u32 s15, 7 s_cbranch_scc1 .LBB0_55 v_mov_b32_e32 v8, 0 v_mov_b32_e32 v9, 0 s_cmp_eq_u32 s15, 0 s_cbranch_scc1 .LBB0_54 s_mov_b64 s[10:11], 0 s_mov_b64 s[12:13], 0 .LBB0_53: s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s16, s0, s12 s_addc_u32 s17, s1, s13 s_add_u32 s12, s12, 1 global_load_u8 v10, v25, s[16:17] s_addc_u32 s13, s13, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v24, 0xffff, v10 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[10:11], s10, v[24:25] s_add_u32 s10, s10, 8 s_addc_u32 s11, s11, 0 s_cmp_lg_u32 s15, s12 v_or_b32_e32 v8, v10, v8 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v9, v11, v9 s_cbranch_scc1 .LBB0_53 .LBB0_54: s_mov_b32 s14, 0 s_cbranch_execz .LBB0_56 s_branch .LBB0_57 .LBB0_55: .LBB0_56: global_load_b64 v[8:9], v25, s[0:1] s_add_i32 s14, s15, -8 s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 .LBB0_57: s_cmp_gt_u32 s14, 7 s_cbranch_scc1 .LBB0_62 v_mov_b32_e32 v10, 0 v_mov_b32_e32 v11, 0 s_cmp_eq_u32 s14, 0 s_cbranch_scc1 .LBB0_61 s_mov_b64 s[10:11], 0 s_mov_b64 s[12:13], 0 .LBB0_60: s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s16, s0, s12 s_addc_u32 s17, s1, s13 s_add_u32 s12, s12, 1 global_load_u8 v12, v25, s[16:17] s_addc_u32 s13, s13, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v24, 0xffff, v12 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[12:13], s10, v[24:25] s_add_u32 s10, s10, 8 s_addc_u32 s11, s11, 0 s_cmp_lg_u32 s14, s12 v_or_b32_e32 v10, v12, v10 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v11, v13, v11 s_cbranch_scc1 .LBB0_60 .LBB0_61: s_mov_b32 s15, 0 s_cbranch_execz .LBB0_63 s_branch .LBB0_64 .LBB0_62: .LBB0_63: global_load_b64 v[10:11], v25, s[0:1] s_add_i32 s15, s14, -8 s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 .LBB0_64: s_cmp_gt_u32 s15, 7 s_cbranch_scc1 .LBB0_69 v_mov_b32_e32 v12, 0 v_mov_b32_e32 v13, 0 s_cmp_eq_u32 s15, 0 s_cbranch_scc1 .LBB0_68 s_mov_b64 s[10:11], 0 s_mov_b64 s[12:13], 0 .LBB0_67: s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s16, s0, s12 s_addc_u32 s17, s1, s13 s_add_u32 s12, s12, 1 global_load_u8 v14, v25, s[16:17] s_addc_u32 s13, s13, 0 s_waitcnt vmcnt(0) v_and_b32_e32 v24, 0xffff, v14 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) v_lshlrev_b64 v[14:15], s10, v[24:25] s_add_u32 s10, s10, 8 s_addc_u32 s11, s11, 0 s_cmp_lg_u32 s15, s12 v_or_b32_e32 v12, v14, v12 s_delay_alu instid0(VALU_DEP_2) v_or_b32_e32 v13, v15, v13 s_cbranch_scc1 .LBB0_67 .LBB0_68: s_mov_b32 s14, 0 s_cbranch_execz .LBB0_70 s_branch .LBB0_71 .LBB0_69: .LBB0_70: global_load_b64 v[12:13], v25, s[0:1] s_add_i32 s14, s15, -8 s_add_u32 s0, s0, 8 s_addc_u32 s1, s1, 0 .LBB0_71: s_cmp_gt_u32 s14, 7 s_cbranch_scc1 .LBB0_76 v_mov_b32_e32 v14, 0 v_mov_b32_e32 v15, 0 s_cmp_eq_u32 s14, 0 s_cbranch_scc1 .LBB0_75 s_mov_b64 s[10:11], 0 s_mov_b64 s[12:13], s[0:1] .LBB0_74: global_load_u8 v16, v25, s[12:13] s_add_i32 s14, s14, -1 s_waitcnt vmcnt(0) v_and_b32_e32 v24, 0xffff, v16 s_delay_alu instid0(VALU_DEP_1) v_lshlrev_b64 v[16:17], s10, v[24:25] s_add_u32 s10, s10, 8 s_addc_u32 s11, s11, 0 s_add_u32 s12, s12, 1 s_addc_u32 s13, s13, 0 s_cmp_lg_u32 s14, 0 v_or_b32_e32 v14, v16, v14 v_or_b32_e32 v15, v17, v15 s_cbranch_scc1 .LBB0_74 .LBB0_75: s_cbranch_execz .LBB0_77 s_branch .LBB0_78 .LBB0_76: .LBB0_77: global_load_b64 v[14:15], v25, s[0:1] .LBB0_78: v_mov_b32_e32 v24, v20 v_mov_b32_e32 v26, 0 v_mov_b32_e32 v27, 0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s0, v24 v_cmp_eq_u32_e64 s0, s0, v24 s_delay_alu instid0(VALU_DEP_1) s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_84 global_load_b64 v[18:19], v25, s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[16:17], v25, s[2:3] offset:40 global_load_b64 v[26:27], v25, s[2:3] s_mov_b32 s10, exec_lo s_waitcnt vmcnt(1) v_and_b32_e32 v17, v17, v19 v_and_b32_e32 v16, v16, v18 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_lo_u32 v17, v17, 24 v_mul_hi_u32 v21, v16, 24 v_mul_lo_u32 v16, v16, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v17, v21, v17 s_waitcnt vmcnt(0) v_add_co_u32 v16, vcc_lo, v26, v16 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo global_load_b64 v[16:17], v[16:17], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[26:27], v[18:19] s_cbranch_execz .LBB0_83 s_mov_b32 s11, 0 .p2align 6 .LBB0_81: s_sleep 1 s_clause 0x1 global_load_b64 v[16:17], v25, s[2:3] offset:40 global_load_b64 v[28:29], v25, s[2:3] v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_and_b32_e32 v16, v16, v18 s_waitcnt vmcnt(0) v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19 v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17] global_load_b64 v[16:17], v[26:27], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19] s_or_b32 s11, vcc_lo, s11 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s11 s_cbranch_execnz .LBB0_81 s_or_b32 exec_lo, exec_lo, s11 .LBB0_83: s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s10 .LBB0_84: s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s1 s_clause 0x1 global_load_b64 v[28:29], v25, s[2:3] offset:40 global_load_b128 v[16:19], v25, s[2:3] v_readfirstlane_b32 s10, v26 v_readfirstlane_b32 s11, v27 s_mov_b32 s14, exec_lo s_waitcnt vmcnt(1) v_readfirstlane_b32 s12, v28 v_readfirstlane_b32 s13, v29 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[12:13], s[10:11], s[12:13] s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_86 v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0 s_mul_i32 s14, s13, 24 s_mul_hi_u32 s15, s12, 24 v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1 s_add_i32 s15, s15, s14 s_mul_i32 s14, s12, 24 s_waitcnt vmcnt(0) v_add_co_u32 v30, vcc_lo, v16, s14 v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo global_store_b128 v[30:31], v[26:29], off offset:8 .LBB0_86: s_or_b32 exec_lo, exec_lo, s1 v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56 v_or_b32_e32 v21, 2, v0 s_lshl_b64 s[14:15], s[12:13], 12 v_lshlrev_b64 v[26:27], 6, v[24:25] s_lshl_b32 s1, s8, 2 s_delay_alu instid0(SALU_CYCLE_1) s_add_i32 s1, s1, 28 v_cndmask_b32_e32 v0, v21, v0, vcc_lo s_waitcnt vmcnt(0) v_add_co_u32 v18, vcc_lo, v18, s14 v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo s_and_b32 s1, s1, 0x1e0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_co_u32 v18, vcc_lo, v18, v26 v_and_or_b32 v0, v0, 0xffffff1f, s1 v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo s_clause 0x3 global_store_b128 v[18:19], v[0:3], off global_store_b128 v[18:19], v[4:7], off offset:16 global_store_b128 v[18:19], v[8:11], off offset:32 global_store_b128 v[18:19], v[12:15], off offset:48 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_94 s_clause 0x1 global_load_b64 v[8:9], v25, s[2:3] offset:32 glc global_load_b64 v[0:1], v25, s[2:3] offset:40 v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11 s_waitcnt vmcnt(0) v_readfirstlane_b32 s14, v0 v_readfirstlane_b32 s15, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[14:15], s[14:15], s[10:11] s_mul_i32 s15, s15, 24 s_mul_hi_u32 s16, s14, 24 s_mul_i32 s14, s14, 24 s_add_i32 s16, s16, s15 v_add_co_u32 v4, vcc_lo, v16, s14 v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo s_mov_b32 s14, exec_lo global_store_b64 v[4:5], v[8:9], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[2:3], v[8:9] s_cbranch_execz .LBB0_90 s_mov_b32 s15, 0 .LBB0_89: v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11 s_sleep 1 global_store_b64 v[4:5], v[2:3], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3] v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0 s_or_b32 s15, vcc_lo, s15 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s15 s_cbranch_execnz .LBB0_89 .LBB0_90: s_or_b32 exec_lo, exec_lo, s14 global_load_b64 v[0:1], v25, s[2:3] offset:16 s_mov_b32 s15, exec_lo s_mov_b32 s14, exec_lo v_mbcnt_lo_u32_b32 v2, s15, 0 s_delay_alu instid0(VALU_DEP_1) v_cmpx_eq_u32_e32 0, v2 s_cbranch_execz .LBB0_92 s_bcnt1_i32_b32 s15, s15 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15 s_waitcnt vmcnt(0) global_atomic_add_u64 v[0:1], v[2:3], off offset:8 .LBB0_92: s_or_b32 exec_lo, exec_lo, s14 s_waitcnt vmcnt(0) global_load_b64 v[2:3], v[0:1], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3] s_cbranch_vccnz .LBB0_94 global_load_b32 v24, v[0:1], off offset:24 s_waitcnt vmcnt(0) v_readfirstlane_b32 s14, v24 s_waitcnt_vscnt null, 0x0 global_store_b64 v[2:3], v[24:25], off s_and_b32 m0, s14, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB0_94: s_or_b32 exec_lo, exec_lo, s1 s_mul_i32 s1, s13, 24 s_mul_hi_u32 s13, s12, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s13, s13, s1 s_mul_i32 s1, s12, 24 v_add_co_u32 v0, vcc_lo, v16, s1 v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v0, 20 v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo s_branch .LBB0_98 .p2align 6 .LBB0_95: s_or_b32 exec_lo, exec_lo, s1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s1, v2 s_cmp_eq_u32 s1, 0 s_cbranch_scc1 .LBB0_97 s_sleep 1 s_cbranch_execnz .LBB0_98 s_branch .LBB0_100 .p2align 6 .LBB0_97: s_branch .LBB0_100 .LBB0_98: v_mov_b32_e32 v2, 1 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_95 global_load_b32 v2, v[0:1], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v2, 1, v2 s_branch .LBB0_95 .LBB0_100: global_load_b64 v[0:1], v[18:19], off s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_28 s_clause 0x2 global_load_b64 v[4:5], v25, s[2:3] offset:40 global_load_b64 v[8:9], v25, s[2:3] offset:24 glc global_load_b64 v[6:7], v25, s[2:3] s_waitcnt vmcnt(2) v_add_co_u32 v10, vcc_lo, v4, 1 v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v2, vcc_lo, v10, s10 v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3] v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10 v_and_b32_e32 v5, v3, v5 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_and_b32_e32 v4, v2, v4 v_mul_hi_u32 v10, v4, 24 v_mul_lo_u32 v4, v4, 24 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_add_co_u32 v6, vcc_lo, v6, v4 v_mov_b32_e32 v4, v8 v_mul_lo_u32 v5, v5, 24 v_add_nc_u32_e32 v5, v10, v5 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo v_mov_b32_e32 v5, v9 global_store_b64 v[6:7], v[8:9], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_28 s_mov_b32 s0, 0 .LBB0_103: s_sleep 1 global_store_b64 v[6:7], v[4:5], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5] v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB0_103 s_branch .LBB0_28 .LBB0_104: s_mov_b32 s0, 0 .LBB0_105: s_delay_alu instid0(SALU_CYCLE_1) s_and_b32 vcc_lo, exec_lo, s0 s_cbranch_vccz .LBB0_132 v_readfirstlane_b32 s0, v20 v_mov_b32_e32 v4, 0 v_mov_b32_e32 v5, 0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_eq_u32_e64 s0, s0, v20 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_112 s_waitcnt vmcnt(0) v_mov_b32_e32 v0, 0 s_mov_b32 s4, exec_lo global_load_b64 v[6:7], v0, s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv s_clause 0x1 global_load_b64 v[1:2], v0, s[2:3] offset:40 global_load_b64 v[3:4], v0, s[2:3] s_waitcnt vmcnt(1) v_and_b32_e32 v1, v1, v6 v_and_b32_e32 v2, v2, v7 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_hi_u32 v5, v1, 24 v_mul_lo_u32 v2, v2, 24 v_mul_lo_u32 v1, v1, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v2, v5, v2 s_waitcnt vmcnt(0) v_add_co_u32 v1, vcc_lo, v3, v1 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo global_load_b64 v[4:5], v[1:2], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmpx_ne_u64_e64 v[4:5], v[6:7] s_cbranch_execz .LBB0_111 s_mov_b32 s5, 0 .p2align 6 .LBB0_109: s_sleep 1 s_clause 0x1 global_load_b64 v[1:2], v0, s[2:3] offset:40 global_load_b64 v[8:9], v0, s[2:3] v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4 s_waitcnt vmcnt(1) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_and_b32_e32 v1, v1, v6 s_waitcnt vmcnt(0) v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7 v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2] global_load_b64 v[4:5], v[3:4], off glc s_waitcnt vmcnt(0) global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7] s_or_b32 s5, vcc_lo, s5 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s5 s_cbranch_execnz .LBB0_109 s_or_b32 exec_lo, exec_lo, s5 .LBB0_111: s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s4 .LBB0_112: s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s1 v_mov_b32_e32 v21, 0 v_readfirstlane_b32 s4, v4 v_readfirstlane_b32 s5, v5 s_mov_b32 s8, exec_lo s_clause 0x1 global_load_b64 v[6:7], v21, s[2:3] offset:40 global_load_b128 v[0:3], v21, s[2:3] s_waitcnt vmcnt(1) v_readfirstlane_b32 s6, v6 v_readfirstlane_b32 s7, v7 s_delay_alu instid0(VALU_DEP_1) s_and_b64 s[6:7], s[4:5], s[6:7] s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_114 v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0 s_mul_i32 s8, s7, 24 s_mul_hi_u32 s9, s6, 24 v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1 s_add_i32 s9, s9, s8 s_mul_i32 s8, s6, 24 s_waitcnt vmcnt(0) v_add_co_u32 v8, vcc_lo, v0, s8 v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo global_store_b128 v[8:9], v[4:7], off offset:8 .LBB0_114: s_or_b32 exec_lo, exec_lo, s1 s_lshl_b64 s[8:9], s[6:7], 12 v_and_or_b32 v22, v22, 0xffffff1d, 34 s_waitcnt vmcnt(0) v_add_co_u32 v4, vcc_lo, v2, s8 v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo v_lshlrev_b64 v[2:3], 6, v[20:21] s_mov_b32 s8, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) s_mov_b32 s9, s8 s_mov_b32 s10, s8 s_mov_b32 s11, s8 v_add_co_u32 v8, vcc_lo, v4, v2 v_mov_b32_e32 v6, 0 v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11 v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10 s_delay_alu instid0(VALU_DEP_4) v_mov_b32_e32 v7, v6 s_clause 0x4 global_store_b64 v[8:9], v[22:23], off global_store_b128 v[8:9], v[2:5], off offset:8 global_store_b128 v[8:9], v[2:5], off offset:24 global_store_b128 v[8:9], v[2:5], off offset:40 global_store_b64 v[8:9], v[6:7], off offset:56 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_122 v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4 v_mov_b32_e32 v10, s5 s_clause 0x1 global_load_b64 v[11:12], v8, s[2:3] offset:32 glc global_load_b64 v[2:3], v8, s[2:3] offset:40 s_waitcnt vmcnt(0) v_readfirstlane_b32 s8, v2 v_readfirstlane_b32 s9, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b64 s[8:9], s[8:9], s[4:5] s_mul_i32 s9, s9, 24 s_mul_hi_u32 s10, s8, 24 s_mul_i32 s8, s8, 24 s_add_i32 s10, s10, s9 v_add_co_u32 v6, vcc_lo, v0, s8 v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo s_mov_b32 s8, exec_lo global_store_b64 v[6:7], v[11:12], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc s_waitcnt vmcnt(0) v_cmpx_ne_u64_e64 v[4:5], v[11:12] s_cbranch_execz .LBB0_118 s_mov_b32 s9, 0 .LBB0_117: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5 s_sleep 1 global_store_b64 v[6:7], v[4:5], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5] v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2 s_or_b32 s9, vcc_lo, s9 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s9 s_cbranch_execnz .LBB0_117 .LBB0_118: s_or_b32 exec_lo, exec_lo, s8 v_mov_b32_e32 v2, 0 s_mov_b32 s9, exec_lo s_mov_b32 s8, exec_lo v_mbcnt_lo_u32_b32 v4, s9, 0 global_load_b64 v[2:3], v2, s[2:3] offset:16 v_cmpx_eq_u32_e32 0, v4 s_cbranch_execz .LBB0_120 s_bcnt1_i32_b32 s9, s9 s_delay_alu instid0(SALU_CYCLE_1) v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9 s_waitcnt vmcnt(0) global_atomic_add_u64 v[2:3], v[4:5], off offset:8 .LBB0_120: s_or_b32 exec_lo, exec_lo, s8 s_waitcnt vmcnt(0) global_load_b64 v[4:5], v[2:3], off offset:16 s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5] s_cbranch_vccnz .LBB0_122 global_load_b32 v2, v[2:3], off offset:24 v_mov_b32_e32 v3, 0 s_waitcnt vmcnt(0) v_readfirstlane_b32 s8, v2 s_waitcnt_vscnt null, 0x0 global_store_b64 v[4:5], v[2:3], off s_and_b32 m0, s8, 0xff s_sendmsg sendmsg(MSG_INTERRUPT) .LBB0_122: s_or_b32 exec_lo, exec_lo, s1 s_mul_i32 s1, s7, 24 s_mul_hi_u32 s7, s6, 24 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) s_add_i32 s7, s7, s1 s_mul_i32 s1, s6, 24 v_add_co_u32 v0, vcc_lo, v0, s1 v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v0, 20 v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo s_branch .LBB0_126 .p2align 6 .LBB0_123: s_or_b32 exec_lo, exec_lo, s1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s1, v2 s_cmp_eq_u32 s1, 0 s_cbranch_scc1 .LBB0_125 s_sleep 1 s_cbranch_execnz .LBB0_126 s_branch .LBB0_128 .p2align 6 .LBB0_125: s_branch .LBB0_128 .LBB0_126: v_mov_b32_e32 v2, 1 s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_123 global_load_b32 v2, v[0:1], off glc s_waitcnt vmcnt(0) buffer_gl1_inv buffer_gl0_inv v_and_b32_e32 v2, 1, v2 s_branch .LBB0_123 .LBB0_128: s_and_saveexec_b32 s1, s0 s_cbranch_execz .LBB0_132 v_mov_b32_e32 v6, 0 s_clause 0x2 global_load_b64 v[2:3], v6, s[2:3] offset:40 global_load_b64 v[7:8], v6, s[2:3] offset:24 glc global_load_b64 v[4:5], v6, s[2:3] s_waitcnt vmcnt(2) v_add_co_u32 v9, vcc_lo, v2, 1 v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v9, s4 v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1] v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9 v_and_b32_e32 v3, v1, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_and_b32_e32 v2, v0, v2 v_mul_lo_u32 v3, v3, 24 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_hi_u32 v9, v2, 24 v_mul_lo_u32 v2, v2, 24 v_add_nc_u32_e32 v3, v9, v3 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_co_u32 v4, vcc_lo, v4, v2 v_mov_b32_e32 v2, v7 v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo v_mov_b32_e32 v3, v8 global_store_b64 v[4:5], v[7:8], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc s_waitcnt vmcnt(0) v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_132 s_mov_b32 s0, 0 .LBB0_131: s_sleep 1 global_store_b64 v[4:5], v[2:3], off s_waitcnt_vscnt null, 0x0 global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc s_waitcnt vmcnt(0) v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3] v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8 s_or_b32 s0, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s0 s_cbranch_execnz .LBB0_131 .LBB0_132: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z10cuda_hellov .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 256 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 32 .amdhsa_next_free_sgpr 18 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z10cuda_hellov, .Lfunc_end0-_Z10cuda_hellov .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type .str,@object .section .rodata.str1.1,"aMS",@progbits,1 .str: .asciz "Hello, world!\n" .size .str, 15 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .offset: 0 .size: 4 .value_kind: hidden_block_count_x - .offset: 4 .size: 4 .value_kind: hidden_block_count_y - .offset: 8 .size: 4 .value_kind: hidden_block_count_z - .offset: 12 .size: 2 .value_kind: hidden_group_size_x - .offset: 14 .size: 2 .value_kind: hidden_group_size_y - .offset: 16 .size: 2 .value_kind: hidden_group_size_z - .offset: 18 .size: 2 .value_kind: hidden_remainder_x - .offset: 20 .size: 2 .value_kind: hidden_remainder_y - .offset: 22 .size: 2 .value_kind: hidden_remainder_z - .offset: 40 .size: 8 .value_kind: hidden_global_offset_x - .offset: 48 .size: 8 .value_kind: hidden_global_offset_y - .offset: 56 .size: 8 .value_kind: hidden_global_offset_z - .offset: 64 .size: 2 .value_kind: hidden_grid_dims - .offset: 80 .size: 8 .value_kind: hidden_hostcall_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 256 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z10cuda_hellov .private_segment_fixed_size: 0 .sgpr_count: 20 .sgpr_spill_count: 0 .symbol: _Z10cuda_hellov.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 32 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_0001ac5c_00000000-6_hello-part1.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z29__device_stub__Z10cuda_hellovv .type _Z29__device_stub__Z10cuda_hellovv, @function _Z29__device_stub__Z10cuda_hellovv: .LFB2082: .cfi_startproc endbr64 subq $88, %rsp .cfi_def_cfa_offset 96 movq %fs:40, %rax movq %rax, 72(%rsp) xorl %eax, %eax movl $1, 16(%rsp) movl $1, 20(%rsp) movl $1, 24(%rsp) movl $1, 28(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) leaq 8(%rsp), %rcx movq %rsp, %rdx leaq 28(%rsp), %rsi leaq 16(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 72(%rsp), %rax subq %fs:40, %rax jne .L8 addq $88, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 8(%rsp) .cfi_def_cfa_offset 104 pushq 8(%rsp) .cfi_def_cfa_offset 112 leaq 80(%rsp), %r9 movq 44(%rsp), %rcx movl 52(%rsp), %r8d movq 32(%rsp), %rsi movl 40(%rsp), %edx leaq _Z10cuda_hellov(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 96 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2082: .size _Z29__device_stub__Z10cuda_hellovv, .-_Z29__device_stub__Z10cuda_hellovv .globl _Z10cuda_hellov .type _Z10cuda_hellov, @function _Z10cuda_hellov: .LFB2083: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z29__device_stub__Z10cuda_hellovv addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2083: .size _Z10cuda_hellov, .-_Z10cuda_hellov .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "Calling cuda_hello...\n" .LC1: .string "...device synchronized.\n" .text .globl main .type main, @function main: .LFB2057: .cfi_startproc endbr64 subq $40, %rsp .cfi_def_cfa_offset 48 leaq .LC0(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $1, 20(%rsp) movl $1, 24(%rsp) movl $1, 8(%rsp) movl $1, 12(%rsp) movl $0, %r9d movl $0, %r8d movq 20(%rsp), %rdx movl $1, %ecx movq 8(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L14 .L12: call cudaDeviceSynchronize@PLT leaq .LC1(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $0, %eax addq $40, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L14: .cfi_restore_state call _Z29__device_stub__Z10cuda_hellovv jmp .L12 .cfi_endproc .LFE2057: .size main, .-main .section .rodata.str1.1 .LC2: .string "_Z10cuda_hellov" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC2(%rip), %rdx movq %rdx, %rcx leaq _Z10cuda_hellov(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "hello-part1.hip" .globl _Z25__device_stub__cuda_hellov # -- Begin function _Z25__device_stub__cuda_hellov .p2align 4, 0x90 .type _Z25__device_stub__cuda_hellov,@function _Z25__device_stub__cuda_hellov: # @_Z25__device_stub__cuda_hellov .cfi_startproc # %bb.0: subq $56, %rsp .cfi_def_cfa_offset 64 leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 48(%rsp), %r9 movl $_Z10cuda_hellov, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $72, %rsp .cfi_adjust_cfa_offset -72 retq .Lfunc_end0: .size _Z25__device_stub__cuda_hellov, .Lfunc_end0-_Z25__device_stub__cuda_hellov .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: subq $56, %rsp .cfi_def_cfa_offset 64 movl $.Lstr, %edi callq puts@PLT movabsq $4294967297, %rdi # imm = 0x100000001 movl $1, %esi movq %rdi, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_2 # %bb.1: leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 48(%rsp), %r9 movl $_Z10cuda_hellov, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_2: callq hipDeviceSynchronize movl $.Lstr.1, %edi callq puts@PLT xorl %eax, %eax addq $56, %rsp .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z10cuda_hellov, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z10cuda_hellov,@object # @_Z10cuda_hellov .section .rodata,"a",@progbits .globl _Z10cuda_hellov .p2align 3, 0x0 _Z10cuda_hellov: .quad _Z25__device_stub__cuda_hellov .size _Z10cuda_hellov, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z10cuda_hellov" .size .L__unnamed_1, 16 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .type .Lstr,@object # @str .section .rodata.str1.1,"aMS",@progbits,1 .Lstr: .asciz "Calling cuda_hello..." .size .Lstr, 22 .type .Lstr.1,@object # @str.1 .Lstr.1: .asciz "...device synchronized." .size .Lstr.1, 24 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z25__device_stub__cuda_hellov .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z10cuda_hellov .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include "includes.h" __global__ void kernel_sqrtweights(int N, double *wt){ unsigned int tid = blockIdx.x*blockDim.x + threadIdx.x; /* make sure to use only N threads */ if (tid<N) { wt[tid]=sqrt(wt[tid]); } }
code for sm_80 Function : _Z18kernel_sqrtweightsiPd .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */ /* 0x000e280000002500 */ /*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */ /* 0x000e240000002100 */ /*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */ /* 0x001fca00078e0203 */ /*0040*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */ /* 0x000fda0003f06070 */ /*0050*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */ /* 0x000fe200078e00ff */ /*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fc60000000a00 */ /*0080*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */ /* 0x000fca00078e0003 */ /*0090*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */ /* 0x000ea2000c1e1b00 */ /*00a0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x0 ; /* 0x00000000ff0a7424 */ /* 0x000fe200078e00ff */ /*00b0*/ BSSY B0, 0x1e0 ; /* 0x0000012000007945 */ /* 0x000fe20003800000 */ /*00c0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x3fd80000 ; /* 0x3fd80000ff0b7424 */ /* 0x000fe200078e00ff */ /*00d0*/ MUFU.RSQ64H R7, R5 ; /* 0x0000000500077308 */ /* 0x004e220000001c00 */ /*00e0*/ IADD3 R6, R5, -0x3500000, RZ ; /* 0xfcb0000005067810 */ /* 0x000fc80007ffe0ff */ /*00f0*/ ISETP.GE.U32.AND P0, PT, R6, 0x7ca00000, PT ; /* 0x7ca000000600780c */ /* 0x000fe40003f06070 */ /*0100*/ DMUL R8, R6, R6 ; /* 0x0000000606087228 */ /* 0x001e0c0000000000 */ /*0110*/ DFMA R8, R4, -R8, 1 ; /* 0x3ff000000408742b */ /* 0x001e0c0000000808 */ /*0120*/ DFMA R10, R8, R10, 0.5 ; /* 0x3fe00000080a742b */ /* 0x001fc8000000000a */ /*0130*/ DMUL R8, R6, R8 ; /* 0x0000000806087228 */ /* 0x000e0c0000000000 */ /*0140*/ DFMA R8, R10, R8, R6 ; /* 0x000000080a08722b */ /* 0x001e0c0000000006 */ /*0150*/ DMUL R10, R4, R8 ; /* 0x00000008040a7228 */ /* 0x001e080000000000 */ /*0160*/ IADD3 R17, R9, -0x100000, RZ ; /* 0xfff0000009117810 */ /* 0x000fe40007ffe0ff */ /*0170*/ DFMA R12, R10, -R10, R4 ; /* 0x8000000a0a0c722b */ /* 0x001e220000000004 */ /*0180*/ MOV R16, R8 ; /* 0x0000000800107202 */ /* 0x000fcc0000000f00 */ /*0190*/ DFMA R14, R12, R16, R10 ; /* 0x000000100c0e722b */ /* 0x001062000000000a */ /*01a0*/ @!P0 BRA 0x1d0 ; /* 0x0000002000008947 */ /* 0x000fea0003800000 */ /*01b0*/ MOV R0, 0x1d0 ; /* 0x000001d000007802 */ /* 0x000fca0000000f00 */ /*01c0*/ CALL.REL.NOINC 0x200 ; /* 0x0000003000007944 */ /* 0x003fea0003c00000 */ /*01d0*/ BSYNC B0 ; /* 0x0000000000007941 */ /* 0x000fea0003800000 */ /*01e0*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */ /* 0x002fe2000c101b04 */ /*01f0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0200*/ ISETP.GE.U32.AND P0, PT, R6, -0x3400000, PT ; /* 0xfcc000000600780c */ /* 0x000fe20003f06070 */ /*0210*/ BSSY B1, 0x460 ; /* 0x0000024000017945 */ /* 0x000fe20003800000 */ /*0220*/ IMAD.MOV.U32 R9, RZ, RZ, R17 ; /* 0x000000ffff097224 */ /* 0x000fd600078e0011 */ /*0230*/ @!P0 BRA 0x2c0 ; /* 0x0000008000008947 */ /* 0x000fea0003800000 */ /*0240*/ DFMA.RM R8, R12, R8, R10 ; /* 0x000000080c08722b */ /* 0x000e14000000400a */ /*0250*/ IADD3 R6, P0, R8, 0x1, RZ ; /* 0x0000000108067810 */ /* 0x001fca0007f1e0ff */ /*0260*/ IMAD.X R7, RZ, RZ, R9, P0 ; /* 0x000000ffff077224 */ /* 0x000fcc00000e0609 */ /*0270*/ DFMA.RP R4, -R8, R6, R4 ; /* 0x000000060804722b */ /* 0x000e0c0000008104 */ /*0280*/ DSETP.GT.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400722a */ /* 0x001e0c0003f04000 */ /*0290*/ FSEL R6, R6, R8, P0 ; /* 0x0000000806067208 */ /* 0x001fe40000000000 */ /*02a0*/ FSEL R7, R7, R9, P0 ; /* 0x0000000907077208 */ /* 0x000fe20000000000 */ /*02b0*/ BRA 0x450 ; /* 0x0000019000007947 */ /* 0x000fea0003800000 */ /*02c0*/ DSETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400722a */ /* 0x000e1c0003f05000 */ /*02d0*/ @!P0 BRA 0x440 ; /* 0x0000016000008947 */ /* 0x001fea0003800000 */ /*02e0*/ ISETP.GE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */ /* 0x000fda0003f06270 */ /*02f0*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; /* 0x00000000ff068424 */ /* 0x000fe200078e00ff */ /*0300*/ @!P0 MOV R7, 0xfff80000 ; /* 0xfff8000000078802 */ /* 0x000fe20000000f00 */ /*0310*/ @!P0 BRA 0x450 ; /* 0x0000013000008947 */ /* 0x000fea0003800000 */ /*0320*/ ISETP.GT.AND P0, PT, R5, 0x7fefffff, PT ; /* 0x7fefffff0500780c */ /* 0x000fda0003f04270 */ /*0330*/ @P0 BRA 0x440 ; /* 0x0000010000000947 */ /* 0x000fea0003800000 */ /*0340*/ DMUL R4, R4, 8.11296384146066816958e+31 ; /* 0x4690000004047828 */ /* 0x000e220000000000 */ /*0350*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */ /* 0x000fe200078e00ff */ /*0360*/ MOV R11, 0x3fd80000 ; /* 0x3fd80000000b7802 */ /* 0x000fe20000000f00 */ /*0370*/ IMAD.MOV.U32 R10, RZ, RZ, 0x0 ; /* 0x00000000ff0a7424 */ /* 0x000fc600078e00ff */ /*0380*/ MUFU.RSQ64H R7, R5 ; /* 0x0000000500077308 */ /* 0x001e240000001c00 */ /*0390*/ DMUL R8, R6, R6 ; /* 0x0000000606087228 */ /* 0x001e0c0000000000 */ /*03a0*/ DFMA R8, R4, -R8, 1 ; /* 0x3ff000000408742b */ /* 0x001e0c0000000808 */ /*03b0*/ DFMA R10, R8, R10, 0.5 ; /* 0x3fe00000080a742b */ /* 0x001fc8000000000a */ /*03c0*/ DMUL R8, R6, R8 ; /* 0x0000000806087228 */ /* 0x000e0c0000000000 */ /*03d0*/ DFMA R8, R10, R8, R6 ; /* 0x000000080a08722b */ /* 0x001e0c0000000006 */ /*03e0*/ DMUL R6, R4, R8 ; /* 0x0000000804067228 */ /* 0x0010480000000000 */ /*03f0*/ IADD3 R9, R9, -0x100000, RZ ; /* 0xfff0000009097810 */ /* 0x001fe40007ffe0ff */ /*0400*/ DFMA R10, R6, -R6, R4 ; /* 0x80000006060a722b */ /* 0x002e0c0000000004 */ /*0410*/ DFMA R6, R8, R10, R6 ; /* 0x0000000a0806722b */ /* 0x001e140000000006 */ /*0420*/ IADD3 R7, R7, -0x3500000, RZ ; /* 0xfcb0000007077810 */ /* 0x001fe20007ffe0ff */ /*0430*/ BRA 0x450 ; /* 0x0000001000007947 */ /* 0x000fea0003800000 */ /*0440*/ DADD R6, R4, R4 ; /* 0x0000000004067229 */ /* 0x00004c0000000004 */ /*0450*/ BSYNC B1 ; /* 0x0000000000017941 */ /* 0x000fea0003800000 */ /*0460*/ MOV R4, R0 ; /* 0x0000000000047202 */ /* 0x001fe20000000f00 */ /*0470*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */ /* 0x000fe400078e00ff */ /*0480*/ IMAD.MOV.U32 R14, RZ, RZ, R6 ; /* 0x000000ffff0e7224 */ /* 0x002fe400078e0006 */ /*0490*/ IMAD.MOV.U32 R15, RZ, RZ, R7 ; /* 0x000000ffff0f7224 */ /* 0x000fe200078e0007 */ /*04a0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffffb5004007950 */ /* 0x000fec0003c3ffff */ /*04b0*/ BRA 0x4b0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*04c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*04d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*04e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*04f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0500*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0510*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0520*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0530*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0540*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0550*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0560*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0570*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include "includes.h" __global__ void kernel_sqrtweights(int N, double *wt){ unsigned int tid = blockIdx.x*blockDim.x + threadIdx.x; /* make sure to use only N threads */ if (tid<N) { wt[tid]=sqrt(wt[tid]); } }
.file "tmpxft_0011c2b1_00000000-6_kernel_sqrtweights.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z39__device_stub__Z18kernel_sqrtweightsiPdiPd .type _Z39__device_stub__Z18kernel_sqrtweightsiPdiPd, @function _Z39__device_stub__Z18kernel_sqrtweightsiPdiPd: .LFB2051: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movl %edi, 12(%rsp) movq %rsi, (%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 12(%rsp), %rax movq %rax, 80(%rsp) movq %rsp, %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 104(%rsp), %rax subq %fs:40, %rax jne .L8 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z18kernel_sqrtweightsiPd(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z39__device_stub__Z18kernel_sqrtweightsiPdiPd, .-_Z39__device_stub__Z18kernel_sqrtweightsiPdiPd .globl _Z18kernel_sqrtweightsiPd .type _Z18kernel_sqrtweightsiPd, @function _Z18kernel_sqrtweightsiPd: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z39__device_stub__Z18kernel_sqrtweightsiPdiPd addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z18kernel_sqrtweightsiPd, .-_Z18kernel_sqrtweightsiPd .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z18kernel_sqrtweightsiPd" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z18kernel_sqrtweightsiPd(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include "includes.h" __global__ void kernel_sqrtweights(int N, double *wt){ unsigned int tid = blockIdx.x*blockDim.x + threadIdx.x; /* make sure to use only N threads */ if (tid<N) { wt[tid]=sqrt(wt[tid]); } }
#include <hip/hip_runtime.h> #include "includes.h" __global__ void kernel_sqrtweights(int N, double *wt){ unsigned int tid = blockIdx.x*blockDim.x + threadIdx.x; /* make sure to use only N threads */ if (tid<N) { wt[tid]=sqrt(wt[tid]); } }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <hip/hip_runtime.h> #include "includes.h" __global__ void kernel_sqrtweights(int N, double *wt){ unsigned int tid = blockIdx.x*blockDim.x + threadIdx.x; /* make sure to use only N threads */ if (tid<N) { wt[tid]=sqrt(wt[tid]); } }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z18kernel_sqrtweightsiPd .globl _Z18kernel_sqrtweightsiPd .p2align 8 .type _Z18kernel_sqrtweightsiPd,@function _Z18kernel_sqrtweightsiPd: s_clause 0x1 s_load_b32 s2, s[0:1], 0x1c s_load_b32 s3, s[0:1], 0x0 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_u32_e64 s3, v1 s_cbranch_execz .LBB0_2 s_load_b64 s[0:1], s[0:1], 0x8 v_mov_b32_e32 v2, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 3, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v0, vcc_lo, s0, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1) v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo global_load_b64 v[2:3], v[0:1], off s_waitcnt vmcnt(0) v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[2:3] v_cndmask_b32_e64 v4, 0, 1, vcc_lo v_lshlrev_b32_e32 v4, 8, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ldexp_f64 v[2:3], v[2:3], v4 v_rsq_f64_e32 v[4:5], v[2:3] s_waitcnt_depctr 0xfff v_mul_f64 v[6:7], v[2:3], v[4:5] v_mul_f64 v[4:5], v[4:5], 0.5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[8:9], -v[4:5], v[6:7], 0.5 v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7] v_fma_f64 v[4:5], v[4:5], v[8:9], v[4:5] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[8:9], -v[6:7], v[6:7], v[2:3] v_fma_f64 v[6:7], v[8:9], v[4:5], v[6:7] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[8:9], -v[6:7], v[6:7], v[2:3] v_fma_f64 v[4:5], v[8:9], v[4:5], v[6:7] v_cndmask_b32_e64 v6, 0, 0xffffff80, vcc_lo v_cmp_class_f64_e64 vcc_lo, v[2:3], 0x260 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_ldexp_f64 v[4:5], v[4:5], v6 v_dual_cndmask_b32 v3, v5, v3 :: v_dual_cndmask_b32 v2, v4, v2 global_store_b64 v[0:1], v[2:3], off .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z18kernel_sqrtweightsiPd .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 272 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 10 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z18kernel_sqrtweightsiPd, .Lfunc_end0-_Z18kernel_sqrtweightsiPd .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .offset: 0 .size: 4 .value_kind: by_value - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: hidden_block_count_x - .offset: 20 .size: 4 .value_kind: hidden_block_count_y - .offset: 24 .size: 4 .value_kind: hidden_block_count_z - .offset: 28 .size: 2 .value_kind: hidden_group_size_x - .offset: 30 .size: 2 .value_kind: hidden_group_size_y - .offset: 32 .size: 2 .value_kind: hidden_group_size_z - .offset: 34 .size: 2 .value_kind: hidden_remainder_x - .offset: 36 .size: 2 .value_kind: hidden_remainder_y - .offset: 38 .size: 2 .value_kind: hidden_remainder_z - .offset: 56 .size: 8 .value_kind: hidden_global_offset_x - .offset: 64 .size: 8 .value_kind: hidden_global_offset_y - .offset: 72 .size: 8 .value_kind: hidden_global_offset_z - .offset: 80 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 272 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z18kernel_sqrtweightsiPd .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z18kernel_sqrtweightsiPd.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 10 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <hip/hip_runtime.h> #include "includes.h" __global__ void kernel_sqrtweights(int N, double *wt){ unsigned int tid = blockIdx.x*blockDim.x + threadIdx.x; /* make sure to use only N threads */ if (tid<N) { wt[tid]=sqrt(wt[tid]); } }
.text .file "kernel_sqrtweights.hip" .globl _Z33__device_stub__kernel_sqrtweightsiPd # -- Begin function _Z33__device_stub__kernel_sqrtweightsiPd .p2align 4, 0x90 .type _Z33__device_stub__kernel_sqrtweightsiPd,@function _Z33__device_stub__kernel_sqrtweightsiPd: # @_Z33__device_stub__kernel_sqrtweightsiPd .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movl %edi, 4(%rsp) movq %rsi, 56(%rsp) leaq 4(%rsp), %rax movq %rax, 64(%rsp) leaq 56(%rsp), %rax movq %rax, 72(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z18kernel_sqrtweightsiPd, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end0: .size _Z33__device_stub__kernel_sqrtweightsiPd, .Lfunc_end0-_Z33__device_stub__kernel_sqrtweightsiPd .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z18kernel_sqrtweightsiPd, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z18kernel_sqrtweightsiPd,@object # @_Z18kernel_sqrtweightsiPd .section .rodata,"a",@progbits .globl _Z18kernel_sqrtweightsiPd .p2align 3, 0x0 _Z18kernel_sqrtweightsiPd: .quad _Z33__device_stub__kernel_sqrtweightsiPd .size _Z18kernel_sqrtweightsiPd, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z18kernel_sqrtweightsiPd" .size .L__unnamed_1, 26 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z33__device_stub__kernel_sqrtweightsiPd .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z18kernel_sqrtweightsiPd .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z18kernel_sqrtweightsiPd .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */ /* 0x000e280000002500 */ /*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */ /* 0x000e240000002100 */ /*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */ /* 0x001fca00078e0203 */ /*0040*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */ /* 0x000fda0003f06070 */ /*0050*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */ /* 0x000fe200078e00ff */ /*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fc60000000a00 */ /*0080*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */ /* 0x000fca00078e0003 */ /*0090*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */ /* 0x000ea2000c1e1b00 */ /*00a0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x0 ; /* 0x00000000ff0a7424 */ /* 0x000fe200078e00ff */ /*00b0*/ BSSY B0, 0x1e0 ; /* 0x0000012000007945 */ /* 0x000fe20003800000 */ /*00c0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x3fd80000 ; /* 0x3fd80000ff0b7424 */ /* 0x000fe200078e00ff */ /*00d0*/ MUFU.RSQ64H R7, R5 ; /* 0x0000000500077308 */ /* 0x004e220000001c00 */ /*00e0*/ IADD3 R6, R5, -0x3500000, RZ ; /* 0xfcb0000005067810 */ /* 0x000fc80007ffe0ff */ /*00f0*/ ISETP.GE.U32.AND P0, PT, R6, 0x7ca00000, PT ; /* 0x7ca000000600780c */ /* 0x000fe40003f06070 */ /*0100*/ DMUL R8, R6, R6 ; /* 0x0000000606087228 */ /* 0x001e0c0000000000 */ /*0110*/ DFMA R8, R4, -R8, 1 ; /* 0x3ff000000408742b */ /* 0x001e0c0000000808 */ /*0120*/ DFMA R10, R8, R10, 0.5 ; /* 0x3fe00000080a742b */ /* 0x001fc8000000000a */ /*0130*/ DMUL R8, R6, R8 ; /* 0x0000000806087228 */ /* 0x000e0c0000000000 */ /*0140*/ DFMA R8, R10, R8, R6 ; /* 0x000000080a08722b */ /* 0x001e0c0000000006 */ /*0150*/ DMUL R10, R4, R8 ; /* 0x00000008040a7228 */ /* 0x001e080000000000 */ /*0160*/ IADD3 R17, R9, -0x100000, RZ ; /* 0xfff0000009117810 */ /* 0x000fe40007ffe0ff */ /*0170*/ DFMA R12, R10, -R10, R4 ; /* 0x8000000a0a0c722b */ /* 0x001e220000000004 */ /*0180*/ MOV R16, R8 ; /* 0x0000000800107202 */ /* 0x000fcc0000000f00 */ /*0190*/ DFMA R14, R12, R16, R10 ; /* 0x000000100c0e722b */ /* 0x001062000000000a */ /*01a0*/ @!P0 BRA 0x1d0 ; /* 0x0000002000008947 */ /* 0x000fea0003800000 */ /*01b0*/ MOV R0, 0x1d0 ; /* 0x000001d000007802 */ /* 0x000fca0000000f00 */ /*01c0*/ CALL.REL.NOINC 0x200 ; /* 0x0000003000007944 */ /* 0x003fea0003c00000 */ /*01d0*/ BSYNC B0 ; /* 0x0000000000007941 */ /* 0x000fea0003800000 */ /*01e0*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */ /* 0x002fe2000c101b04 */ /*01f0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0200*/ ISETP.GE.U32.AND P0, PT, R6, -0x3400000, PT ; /* 0xfcc000000600780c */ /* 0x000fe20003f06070 */ /*0210*/ BSSY B1, 0x460 ; /* 0x0000024000017945 */ /* 0x000fe20003800000 */ /*0220*/ IMAD.MOV.U32 R9, RZ, RZ, R17 ; /* 0x000000ffff097224 */ /* 0x000fd600078e0011 */ /*0230*/ @!P0 BRA 0x2c0 ; /* 0x0000008000008947 */ /* 0x000fea0003800000 */ /*0240*/ DFMA.RM R8, R12, R8, R10 ; /* 0x000000080c08722b */ /* 0x000e14000000400a */ /*0250*/ IADD3 R6, P0, R8, 0x1, RZ ; /* 0x0000000108067810 */ /* 0x001fca0007f1e0ff */ /*0260*/ IMAD.X R7, RZ, RZ, R9, P0 ; /* 0x000000ffff077224 */ /* 0x000fcc00000e0609 */ /*0270*/ DFMA.RP R4, -R8, R6, R4 ; /* 0x000000060804722b */ /* 0x000e0c0000008104 */ /*0280*/ DSETP.GT.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400722a */ /* 0x001e0c0003f04000 */ /*0290*/ FSEL R6, R6, R8, P0 ; /* 0x0000000806067208 */ /* 0x001fe40000000000 */ /*02a0*/ FSEL R7, R7, R9, P0 ; /* 0x0000000907077208 */ /* 0x000fe20000000000 */ /*02b0*/ BRA 0x450 ; /* 0x0000019000007947 */ /* 0x000fea0003800000 */ /*02c0*/ DSETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400722a */ /* 0x000e1c0003f05000 */ /*02d0*/ @!P0 BRA 0x440 ; /* 0x0000016000008947 */ /* 0x001fea0003800000 */ /*02e0*/ ISETP.GE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */ /* 0x000fda0003f06270 */ /*02f0*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; /* 0x00000000ff068424 */ /* 0x000fe200078e00ff */ /*0300*/ @!P0 MOV R7, 0xfff80000 ; /* 0xfff8000000078802 */ /* 0x000fe20000000f00 */ /*0310*/ @!P0 BRA 0x450 ; /* 0x0000013000008947 */ /* 0x000fea0003800000 */ /*0320*/ ISETP.GT.AND P0, PT, R5, 0x7fefffff, PT ; /* 0x7fefffff0500780c */ /* 0x000fda0003f04270 */ /*0330*/ @P0 BRA 0x440 ; /* 0x0000010000000947 */ /* 0x000fea0003800000 */ /*0340*/ DMUL R4, R4, 8.11296384146066816958e+31 ; /* 0x4690000004047828 */ /* 0x000e220000000000 */ /*0350*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */ /* 0x000fe200078e00ff */ /*0360*/ MOV R11, 0x3fd80000 ; /* 0x3fd80000000b7802 */ /* 0x000fe20000000f00 */ /*0370*/ IMAD.MOV.U32 R10, RZ, RZ, 0x0 ; /* 0x00000000ff0a7424 */ /* 0x000fc600078e00ff */ /*0380*/ MUFU.RSQ64H R7, R5 ; /* 0x0000000500077308 */ /* 0x001e240000001c00 */ /*0390*/ DMUL R8, R6, R6 ; /* 0x0000000606087228 */ /* 0x001e0c0000000000 */ /*03a0*/ DFMA R8, R4, -R8, 1 ; /* 0x3ff000000408742b */ /* 0x001e0c0000000808 */ /*03b0*/ DFMA R10, R8, R10, 0.5 ; /* 0x3fe00000080a742b */ /* 0x001fc8000000000a */ /*03c0*/ DMUL R8, R6, R8 ; /* 0x0000000806087228 */ /* 0x000e0c0000000000 */ /*03d0*/ DFMA R8, R10, R8, R6 ; /* 0x000000080a08722b */ /* 0x001e0c0000000006 */ /*03e0*/ DMUL R6, R4, R8 ; /* 0x0000000804067228 */ /* 0x0010480000000000 */ /*03f0*/ IADD3 R9, R9, -0x100000, RZ ; /* 0xfff0000009097810 */ /* 0x001fe40007ffe0ff */ /*0400*/ DFMA R10, R6, -R6, R4 ; /* 0x80000006060a722b */ /* 0x002e0c0000000004 */ /*0410*/ DFMA R6, R8, R10, R6 ; /* 0x0000000a0806722b */ /* 0x001e140000000006 */ /*0420*/ IADD3 R7, R7, -0x3500000, RZ ; /* 0xfcb0000007077810 */ /* 0x001fe20007ffe0ff */ /*0430*/ BRA 0x450 ; /* 0x0000001000007947 */ /* 0x000fea0003800000 */ /*0440*/ DADD R6, R4, R4 ; /* 0x0000000004067229 */ /* 0x00004c0000000004 */ /*0450*/ BSYNC B1 ; /* 0x0000000000017941 */ /* 0x000fea0003800000 */ /*0460*/ MOV R4, R0 ; /* 0x0000000000047202 */ /* 0x001fe20000000f00 */ /*0470*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */ /* 0x000fe400078e00ff */ /*0480*/ IMAD.MOV.U32 R14, RZ, RZ, R6 ; /* 0x000000ffff0e7224 */ /* 0x002fe400078e0006 */ /*0490*/ IMAD.MOV.U32 R15, RZ, RZ, R7 ; /* 0x000000ffff0f7224 */ /* 0x000fe200078e0007 */ /*04a0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffffb5004007950 */ /* 0x000fec0003c3ffff */ /*04b0*/ BRA 0x4b0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*04c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*04d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*04e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*04f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0500*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0510*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0520*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0530*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0540*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0550*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0560*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0570*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z18kernel_sqrtweightsiPd .globl _Z18kernel_sqrtweightsiPd .p2align 8 .type _Z18kernel_sqrtweightsiPd,@function _Z18kernel_sqrtweightsiPd: s_clause 0x1 s_load_b32 s2, s[0:1], 0x1c s_load_b32 s3, s[0:1], 0x0 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_u32_e64 s3, v1 s_cbranch_execz .LBB0_2 s_load_b64 s[0:1], s[0:1], 0x8 v_mov_b32_e32 v2, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 3, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v0, vcc_lo, s0, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1) v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo global_load_b64 v[2:3], v[0:1], off s_waitcnt vmcnt(0) v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[2:3] v_cndmask_b32_e64 v4, 0, 1, vcc_lo v_lshlrev_b32_e32 v4, 8, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ldexp_f64 v[2:3], v[2:3], v4 v_rsq_f64_e32 v[4:5], v[2:3] s_waitcnt_depctr 0xfff v_mul_f64 v[6:7], v[2:3], v[4:5] v_mul_f64 v[4:5], v[4:5], 0.5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[8:9], -v[4:5], v[6:7], 0.5 v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7] v_fma_f64 v[4:5], v[4:5], v[8:9], v[4:5] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[8:9], -v[6:7], v[6:7], v[2:3] v_fma_f64 v[6:7], v[8:9], v[4:5], v[6:7] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[8:9], -v[6:7], v[6:7], v[2:3] v_fma_f64 v[4:5], v[8:9], v[4:5], v[6:7] v_cndmask_b32_e64 v6, 0, 0xffffff80, vcc_lo v_cmp_class_f64_e64 vcc_lo, v[2:3], 0x260 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_ldexp_f64 v[4:5], v[4:5], v6 v_dual_cndmask_b32 v3, v5, v3 :: v_dual_cndmask_b32 v2, v4, v2 global_store_b64 v[0:1], v[2:3], off .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z18kernel_sqrtweightsiPd .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 272 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 10 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z18kernel_sqrtweightsiPd, .Lfunc_end0-_Z18kernel_sqrtweightsiPd .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .offset: 0 .size: 4 .value_kind: by_value - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: hidden_block_count_x - .offset: 20 .size: 4 .value_kind: hidden_block_count_y - .offset: 24 .size: 4 .value_kind: hidden_block_count_z - .offset: 28 .size: 2 .value_kind: hidden_group_size_x - .offset: 30 .size: 2 .value_kind: hidden_group_size_y - .offset: 32 .size: 2 .value_kind: hidden_group_size_z - .offset: 34 .size: 2 .value_kind: hidden_remainder_x - .offset: 36 .size: 2 .value_kind: hidden_remainder_y - .offset: 38 .size: 2 .value_kind: hidden_remainder_z - .offset: 56 .size: 8 .value_kind: hidden_global_offset_x - .offset: 64 .size: 8 .value_kind: hidden_global_offset_y - .offset: 72 .size: 8 .value_kind: hidden_global_offset_z - .offset: 80 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 272 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z18kernel_sqrtweightsiPd .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z18kernel_sqrtweightsiPd.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 10 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_0011c2b1_00000000-6_kernel_sqrtweights.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z39__device_stub__Z18kernel_sqrtweightsiPdiPd .type _Z39__device_stub__Z18kernel_sqrtweightsiPdiPd, @function _Z39__device_stub__Z18kernel_sqrtweightsiPdiPd: .LFB2051: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movl %edi, 12(%rsp) movq %rsi, (%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 12(%rsp), %rax movq %rax, 80(%rsp) movq %rsp, %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 104(%rsp), %rax subq %fs:40, %rax jne .L8 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z18kernel_sqrtweightsiPd(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z39__device_stub__Z18kernel_sqrtweightsiPdiPd, .-_Z39__device_stub__Z18kernel_sqrtweightsiPdiPd .globl _Z18kernel_sqrtweightsiPd .type _Z18kernel_sqrtweightsiPd, @function _Z18kernel_sqrtweightsiPd: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z39__device_stub__Z18kernel_sqrtweightsiPdiPd addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z18kernel_sqrtweightsiPd, .-_Z18kernel_sqrtweightsiPd .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z18kernel_sqrtweightsiPd" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z18kernel_sqrtweightsiPd(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "kernel_sqrtweights.hip" .globl _Z33__device_stub__kernel_sqrtweightsiPd # -- Begin function _Z33__device_stub__kernel_sqrtweightsiPd .p2align 4, 0x90 .type _Z33__device_stub__kernel_sqrtweightsiPd,@function _Z33__device_stub__kernel_sqrtweightsiPd: # @_Z33__device_stub__kernel_sqrtweightsiPd .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movl %edi, 4(%rsp) movq %rsi, 56(%rsp) leaq 4(%rsp), %rax movq %rax, 64(%rsp) leaq 56(%rsp), %rax movq %rax, 72(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z18kernel_sqrtweightsiPd, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end0: .size _Z33__device_stub__kernel_sqrtweightsiPd, .Lfunc_end0-_Z33__device_stub__kernel_sqrtweightsiPd .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z18kernel_sqrtweightsiPd, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z18kernel_sqrtweightsiPd,@object # @_Z18kernel_sqrtweightsiPd .section .rodata,"a",@progbits .globl _Z18kernel_sqrtweightsiPd .p2align 3, 0x0 _Z18kernel_sqrtweightsiPd: .quad _Z33__device_stub__kernel_sqrtweightsiPd .size _Z18kernel_sqrtweightsiPd, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z18kernel_sqrtweightsiPd" .size .L__unnamed_1, 26 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z33__device_stub__kernel_sqrtweightsiPd .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z18kernel_sqrtweightsiPd .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#define t_max 1 #define t 1 /* (u[0][0][0][0][0]=((alpha*(ux[1][0][0][0][1]-ux[-1][0][0][0][1]))+((beta*(uy[0][1][0][0][2]-uy[0][-1][0][0][2]))+(gamma*(uz[0][0][1][0][3]-uz[0][0][-1][0][3]))))) */ __global__ void divergence(float * * u_0_0_out, float * u_0_0, float * ux_1_0, float * uy_2_0, float * uz_3_0, float alpha, float beta, float gamma, int x_max, int y_max, int z_max, int cbx) { /*float * const u__u_0[16] = { u_0_0 } ; float * const u__ux_1[16] = { ux_1_0 } ; float * const u__uy_2[16] = { uy_2_0 } ; float * const u__uz_3[16] = { uz_3_0 } ;*/ int _idx0; int _idx1; int _idx2; int _idx3; int _idx4; int _idx5; int idx_1_2; int pt_idx_x; int pt_idx_y; int pt_idx_z; int size_1_1; int size_1_2; //int t; int tmp; int v_idx_x; int v_idx_x_max; int v_idx_y; int v_idx_y_max; int v_idx_z; int v_idx_z_max; /* Initializations */ size_1_1=(y_max/blockDim.y); size_1_2=(z_max/blockDim.z); idx_1_2=(blockIdx.y/size_1_2); tmp=(blockIdx.y-(idx_1_2*size_1_2)); v_idx_x=(cbx*(threadIdx.x+(blockDim.x*blockIdx.x))); v_idx_x_max=(v_idx_x+cbx); v_idx_y=(threadIdx.y+(tmp*blockDim.y)); v_idx_y_max=(v_idx_y+1); v_idx_z=(threadIdx.z+(idx_1_2*blockDim.z)); v_idx_z_max=(v_idx_z+1); /* Implementation */ /* for t = 1..t_max by 1 parallel 1 <level 0> schedule { ... } */ //for (t=1; t<=t_max; t+=1) { /* Index bounds calculations for iterators in v[t=t, s=(cbx, 1, 1)][0] */ /* for POINT pt[t=t, s=(1, 1, 1)][0] of size [1, 1, 1] in v[t=t, s=(:, :, :)][0] parallel 1 <level 1> schedule default { ... } */ { /* Index bounds calculations for iterators in pt[t=t, s=(1, 1, 1)][0] */ pt_idx_z=v_idx_z; pt_idx_y=v_idx_y; for (pt_idx_x=v_idx_x; pt_idx_x<(v_idx_x_max-0); pt_idx_x+=1) { /* Index bounds calculations for iterators in pt[t=t, s=(1, 1, 1)][0] */ /* v[t=(t+1), s=pt[t=?, s=?][0]][0]=stencil(v[t=t, s=pt[t=?, s=?][0]][0]) */ /* _idx0 = (((((((pt_idx_z*x_max)+((2*pt_idx_z)*t))*y_max)+(pt_idx_y*x_max))+((2*pt_idx_y)*t))+pt_idx_x)+2) */ _idx0=(((((((pt_idx_z*x_max)+((2*pt_idx_z)*t))*y_max)+(pt_idx_y*x_max))+((2*pt_idx_y)*t))+pt_idx_x)+2); /* _idx1 = ((((((pt_idx_z*x_max)+((2*pt_idx_z)*t))*y_max)+(pt_idx_y*x_max))+((2*pt_idx_y)*t))+pt_idx_x) */ _idx1=(_idx0-2); /* _idx2 = ((((pt_idx_z*x_max)*y_max)+(((((2*pt_idx_z)*t)+pt_idx_y)+2)*x_max))+pt_idx_x) */ _idx2=(((_idx1-(((2*pt_idx_z)*t)*y_max))+((((2*pt_idx_z)*t)+2)*x_max))-((2*pt_idx_y)*t)); /* _idx3 = ((((pt_idx_z*x_max)*y_max)+((((2*pt_idx_z)*t)+pt_idx_y)*x_max))+pt_idx_x) */ _idx3=(_idx2-(2*x_max)); /* _idx4 = (((((pt_idx_z+2)*x_max)*y_max)+(pt_idx_y*x_max))+pt_idx_x) */ _idx4=((_idx3+((2*x_max)*y_max))-(((2*pt_idx_z)*t)*x_max)); /* _idx5 = ((((pt_idx_z*x_max)*y_max)+(pt_idx_y*x_max))+pt_idx_x) */ _idx5=(_idx4-((2*x_max)*y_max)); u_0_0[_idx5]=((alpha*(ux_1_0[_idx0]-ux_1_0[_idx1]))+((beta*(uy_2_0[_idx2]-uy_2_0[_idx3]))+(gamma*(uz_3_0[_idx4]-uz_3_0[_idx5])))); } } } } __global__ void initialize(float * u_0_0, float * ux_1_0, float * uy_2_0, float * uz_3_0, float alpha, float beta, float gamma, int x_max, int y_max, int z_max, int cbx) { float * const u__u_0[16] = { u_0_0 } ; float * const u__ux_1[16] = { ux_1_0 } ; float * const u__uy_2[16] = { uy_2_0 } ; float * const u__uz_3[16] = { uz_3_0 } ; int _idx0; int _idx1; int _idx2; int _idx3; int _idx4; int _idx5; int idx_1_2; int pt_idx_x; int pt_idx_y; int pt_idx_z; int size_1_1; int size_1_2; //int t; int tmp; int v_idx_x; int v_idx_x_max; int v_idx_y; int v_idx_y_max; int v_idx_z; int v_idx_z_max; /* Initializations */ size_1_1=(y_max/blockDim.y); size_1_2=(z_max/blockDim.z); idx_1_2=(blockIdx.y/size_1_2); tmp=(blockIdx.y-(idx_1_2*size_1_2)); v_idx_x=(cbx*(threadIdx.x+(blockDim.x*blockIdx.x))); v_idx_x_max=(v_idx_x+cbx); v_idx_y=(threadIdx.y+(tmp*blockDim.y)); v_idx_y_max=(v_idx_y+1); v_idx_z=(threadIdx.z+(idx_1_2*blockDim.z)); v_idx_z_max=(v_idx_z+1); /* Implementation */ /* for t = 1..t_max by 1 parallel 1 <level 0> schedule { ... } */ //for (t=1; t<=t_max; t+=1) { /* Index bounds calculations for iterators in v[t=t, s=(cbx, 1, 1)][0] */ /* for POINT pt[t=t, s=(1, 1, 1)][0] of size [1, 1, 1] in v[t=t, s=(:, :, :)][0] parallel 1 <level 1> schedule default { ... } */ { /* Index bounds calculations for iterators in pt[t=t, s=(1, 1, 1)][0] */ pt_idx_z=v_idx_z; pt_idx_y=v_idx_y; for (pt_idx_x=v_idx_x; pt_idx_x<(v_idx_x_max-0); pt_idx_x+=1) { /* Index bounds calculations for iterators in pt[t=t, s=(1, 1, 1)][0] */ /* v[t=(t+1), s=pt[t=?, s=?][0]][0]=stencil(v[t=t, s=pt[t=?, s=?][0]][0]) */ /* _idx0 = ((((((pt_idx_z*x_max)+((2*pt_idx_z)*t))*y_max)+(pt_idx_y*x_max))+((2*pt_idx_y)*t))+pt_idx_x) */ _idx0=((((((pt_idx_z*x_max)+((2*pt_idx_z)*t))*y_max)+(pt_idx_y*x_max))+((2*pt_idx_y)*t))+pt_idx_x); u__ux_1[(t-1)][_idx0]=0.2; /* _idx1 = ((((pt_idx_z*x_max)*y_max)+((((2*pt_idx_z)*t)+pt_idx_y)*x_max))+pt_idx_x) */ _idx1=(((_idx0-(((2*pt_idx_z)*t)*y_max))+(((2*pt_idx_z)*t)*x_max))-((2*pt_idx_y)*t)); u__uy_2[(t-1)][_idx1]=0.30000000000000004; /* _idx2 = ((((pt_idx_z*x_max)*y_max)+(pt_idx_y*x_max))+pt_idx_x) */ _idx2=(_idx1-(((2*pt_idx_z)*t)*x_max)); u__uz_3[(t-1)][_idx2]=0.4; /* _idx3 = (((((pt_idx_z+2)*x_max)*y_max)+(pt_idx_y*x_max))+pt_idx_x) */ _idx3=(_idx2+((2*x_max)*y_max)); u__uz_3[(t-1)][_idx3]=0.4; /* _idx4 = ((((pt_idx_z*x_max)*y_max)+(((((2*pt_idx_z)*t)+pt_idx_y)+2)*x_max))+pt_idx_x) */ _idx4=(_idx1+(2*x_max)); u__uy_2[(t-1)][_idx4]=0.30000000000000004; /* _idx5 = (((((((pt_idx_z*x_max)+((2*pt_idx_z)*t))*y_max)+(pt_idx_y*x_max))+((2*pt_idx_y)*t))+pt_idx_x)+2) */ _idx5=(_idx0+2); u__ux_1[(t-1)][_idx5]=0.2; u__u_0[(t-1)][_idx2]=0.1; } } } }
.file "tmpxft_0009176b_00000000-6_kernel.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z46__device_stub__Z10divergencePPfS_S_S_S_fffiiiiPPfS_S_S_S_fffiiii .type _Z46__device_stub__Z10divergencePPfS_S_S_S_fffiiiiPPfS_S_S_S_fffiiii, @function _Z46__device_stub__Z10divergencePPfS_S_S_S_fffiiiiPPfS_S_S_S_fffiiii: .LFB2051: .cfi_startproc endbr64 subq $248, %rsp .cfi_def_cfa_offset 256 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) movq %rdx, 40(%rsp) movq %rcx, 32(%rsp) movq %r8, 24(%rsp) movss %xmm0, 20(%rsp) movss %xmm1, 16(%rsp) movss %xmm2, 12(%rsp) movl %r9d, 8(%rsp) movq %fs:40, %rax movq %rax, 232(%rsp) xorl %eax, %eax leaq 56(%rsp), %rax movq %rax, 128(%rsp) leaq 48(%rsp), %rax movq %rax, 136(%rsp) leaq 40(%rsp), %rax movq %rax, 144(%rsp) leaq 32(%rsp), %rax movq %rax, 152(%rsp) leaq 24(%rsp), %rax movq %rax, 160(%rsp) leaq 20(%rsp), %rax movq %rax, 168(%rsp) leaq 16(%rsp), %rax movq %rax, 176(%rsp) leaq 12(%rsp), %rax movq %rax, 184(%rsp) leaq 8(%rsp), %rax movq %rax, 192(%rsp) leaq 256(%rsp), %rax movq %rax, 200(%rsp) leaq 264(%rsp), %rax movq %rax, 208(%rsp) leaq 272(%rsp), %rax movq %rax, 216(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) movl $1, 88(%rsp) movl $1, 92(%rsp) movl $1, 96(%rsp) movl $1, 100(%rsp) leaq 72(%rsp), %rcx leaq 64(%rsp), %rdx leaq 92(%rsp), %rsi leaq 80(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 232(%rsp), %rax subq %fs:40, %rax jne .L8 addq $248, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 72(%rsp) .cfi_def_cfa_offset 264 pushq 72(%rsp) .cfi_def_cfa_offset 272 leaq 144(%rsp), %r9 movq 108(%rsp), %rcx movl 116(%rsp), %r8d movq 96(%rsp), %rsi movl 104(%rsp), %edx leaq _Z10divergencePPfS_S_S_S_fffiiii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 256 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z46__device_stub__Z10divergencePPfS_S_S_S_fffiiiiPPfS_S_S_S_fffiiii, .-_Z46__device_stub__Z10divergencePPfS_S_S_S_fffiiiiPPfS_S_S_S_fffiiii .globl _Z10divergencePPfS_S_S_S_fffiiii .type _Z10divergencePPfS_S_S_S_fffiiii, @function _Z10divergencePPfS_S_S_S_fffiiii: .LFB2052: .cfi_startproc endbr64 subq $16, %rsp .cfi_def_cfa_offset 24 movl 40(%rsp), %eax pushq %rax .cfi_def_cfa_offset 32 movl 40(%rsp), %eax pushq %rax .cfi_def_cfa_offset 40 movl 40(%rsp), %eax pushq %rax .cfi_def_cfa_offset 48 call _Z46__device_stub__Z10divergencePPfS_S_S_S_fffiiiiPPfS_S_S_S_fffiiii addq $40, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z10divergencePPfS_S_S_S_fffiiii, .-_Z10divergencePPfS_S_S_S_fffiiii .globl _Z43__device_stub__Z10initializePfS_S_S_fffiiiiPfS_S_S_fffiiii .type _Z43__device_stub__Z10initializePfS_S_S_fffiiiiPfS_S_S_fffiiii, @function _Z43__device_stub__Z10initializePfS_S_S_fffiiiiPfS_S_S_fffiiii: .LFB2053: .cfi_startproc endbr64 subq $232, %rsp .cfi_def_cfa_offset 240 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) movq %rdx, 40(%rsp) movq %rcx, 32(%rsp) movss %xmm0, 28(%rsp) movss %xmm1, 24(%rsp) movss %xmm2, 20(%rsp) movl %r8d, 16(%rsp) movl %r9d, 12(%rsp) movq %fs:40, %rax movq %rax, 216(%rsp) xorl %eax, %eax leaq 56(%rsp), %rax movq %rax, 128(%rsp) leaq 48(%rsp), %rax movq %rax, 136(%rsp) leaq 40(%rsp), %rax movq %rax, 144(%rsp) leaq 32(%rsp), %rax movq %rax, 152(%rsp) leaq 28(%rsp), %rax movq %rax, 160(%rsp) leaq 24(%rsp), %rax movq %rax, 168(%rsp) leaq 20(%rsp), %rax movq %rax, 176(%rsp) leaq 16(%rsp), %rax movq %rax, 184(%rsp) leaq 12(%rsp), %rax movq %rax, 192(%rsp) leaq 240(%rsp), %rax movq %rax, 200(%rsp) leaq 248(%rsp), %rax movq %rax, 208(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) movl $1, 88(%rsp) movl $1, 92(%rsp) movl $1, 96(%rsp) movl $1, 100(%rsp) leaq 72(%rsp), %rcx leaq 64(%rsp), %rdx leaq 92(%rsp), %rsi leaq 80(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L15 .L11: movq 216(%rsp), %rax subq %fs:40, %rax jne .L16 addq $232, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L15: .cfi_restore_state pushq 72(%rsp) .cfi_def_cfa_offset 248 pushq 72(%rsp) .cfi_def_cfa_offset 256 leaq 144(%rsp), %r9 movq 108(%rsp), %rcx movl 116(%rsp), %r8d movq 96(%rsp), %rsi movl 104(%rsp), %edx leaq _Z10initializePfS_S_S_fffiiii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 240 jmp .L11 .L16: call __stack_chk_fail@PLT .cfi_endproc .LFE2053: .size _Z43__device_stub__Z10initializePfS_S_S_fffiiiiPfS_S_S_fffiiii, .-_Z43__device_stub__Z10initializePfS_S_S_fffiiiiPfS_S_S_fffiiii .globl _Z10initializePfS_S_S_fffiiii .type _Z10initializePfS_S_S_fffiiii, @function _Z10initializePfS_S_S_fffiiii: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movl 24(%rsp), %eax pushq %rax .cfi_def_cfa_offset 24 movl 24(%rsp), %eax pushq %rax .cfi_def_cfa_offset 32 call _Z43__device_stub__Z10initializePfS_S_S_fffiiiiPfS_S_S_fffiiii addq $24, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _Z10initializePfS_S_S_fffiiii, .-_Z10initializePfS_S_S_fffiiii .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z10initializePfS_S_S_fffiiii" .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC1: .string "_Z10divergencePPfS_S_S_S_fffiiii" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2056: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z10initializePfS_S_S_fffiiii(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC1(%rip), %rdx movq %rdx, %rcx leaq _Z10divergencePPfS_S_S_S_fffiiii(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2056: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#define t_max 1 #define t 1 /* (u[0][0][0][0][0]=((alpha*(ux[1][0][0][0][1]-ux[-1][0][0][0][1]))+((beta*(uy[0][1][0][0][2]-uy[0][-1][0][0][2]))+(gamma*(uz[0][0][1][0][3]-uz[0][0][-1][0][3]))))) */ __global__ void divergence(float * * u_0_0_out, float * u_0_0, float * ux_1_0, float * uy_2_0, float * uz_3_0, float alpha, float beta, float gamma, int x_max, int y_max, int z_max, int cbx) { /*float * const u__u_0[16] = { u_0_0 } ; float * const u__ux_1[16] = { ux_1_0 } ; float * const u__uy_2[16] = { uy_2_0 } ; float * const u__uz_3[16] = { uz_3_0 } ;*/ int _idx0; int _idx1; int _idx2; int _idx3; int _idx4; int _idx5; int idx_1_2; int pt_idx_x; int pt_idx_y; int pt_idx_z; int size_1_1; int size_1_2; //int t; int tmp; int v_idx_x; int v_idx_x_max; int v_idx_y; int v_idx_y_max; int v_idx_z; int v_idx_z_max; /* Initializations */ size_1_1=(y_max/blockDim.y); size_1_2=(z_max/blockDim.z); idx_1_2=(blockIdx.y/size_1_2); tmp=(blockIdx.y-(idx_1_2*size_1_2)); v_idx_x=(cbx*(threadIdx.x+(blockDim.x*blockIdx.x))); v_idx_x_max=(v_idx_x+cbx); v_idx_y=(threadIdx.y+(tmp*blockDim.y)); v_idx_y_max=(v_idx_y+1); v_idx_z=(threadIdx.z+(idx_1_2*blockDim.z)); v_idx_z_max=(v_idx_z+1); /* Implementation */ /* for t = 1..t_max by 1 parallel 1 <level 0> schedule { ... } */ //for (t=1; t<=t_max; t+=1) { /* Index bounds calculations for iterators in v[t=t, s=(cbx, 1, 1)][0] */ /* for POINT pt[t=t, s=(1, 1, 1)][0] of size [1, 1, 1] in v[t=t, s=(:, :, :)][0] parallel 1 <level 1> schedule default { ... } */ { /* Index bounds calculations for iterators in pt[t=t, s=(1, 1, 1)][0] */ pt_idx_z=v_idx_z; pt_idx_y=v_idx_y; for (pt_idx_x=v_idx_x; pt_idx_x<(v_idx_x_max-0); pt_idx_x+=1) { /* Index bounds calculations for iterators in pt[t=t, s=(1, 1, 1)][0] */ /* v[t=(t+1), s=pt[t=?, s=?][0]][0]=stencil(v[t=t, s=pt[t=?, s=?][0]][0]) */ /* _idx0 = (((((((pt_idx_z*x_max)+((2*pt_idx_z)*t))*y_max)+(pt_idx_y*x_max))+((2*pt_idx_y)*t))+pt_idx_x)+2) */ _idx0=(((((((pt_idx_z*x_max)+((2*pt_idx_z)*t))*y_max)+(pt_idx_y*x_max))+((2*pt_idx_y)*t))+pt_idx_x)+2); /* _idx1 = ((((((pt_idx_z*x_max)+((2*pt_idx_z)*t))*y_max)+(pt_idx_y*x_max))+((2*pt_idx_y)*t))+pt_idx_x) */ _idx1=(_idx0-2); /* _idx2 = ((((pt_idx_z*x_max)*y_max)+(((((2*pt_idx_z)*t)+pt_idx_y)+2)*x_max))+pt_idx_x) */ _idx2=(((_idx1-(((2*pt_idx_z)*t)*y_max))+((((2*pt_idx_z)*t)+2)*x_max))-((2*pt_idx_y)*t)); /* _idx3 = ((((pt_idx_z*x_max)*y_max)+((((2*pt_idx_z)*t)+pt_idx_y)*x_max))+pt_idx_x) */ _idx3=(_idx2-(2*x_max)); /* _idx4 = (((((pt_idx_z+2)*x_max)*y_max)+(pt_idx_y*x_max))+pt_idx_x) */ _idx4=((_idx3+((2*x_max)*y_max))-(((2*pt_idx_z)*t)*x_max)); /* _idx5 = ((((pt_idx_z*x_max)*y_max)+(pt_idx_y*x_max))+pt_idx_x) */ _idx5=(_idx4-((2*x_max)*y_max)); u_0_0[_idx5]=((alpha*(ux_1_0[_idx0]-ux_1_0[_idx1]))+((beta*(uy_2_0[_idx2]-uy_2_0[_idx3]))+(gamma*(uz_3_0[_idx4]-uz_3_0[_idx5])))); } } } } __global__ void initialize(float * u_0_0, float * ux_1_0, float * uy_2_0, float * uz_3_0, float alpha, float beta, float gamma, int x_max, int y_max, int z_max, int cbx) { float * const u__u_0[16] = { u_0_0 } ; float * const u__ux_1[16] = { ux_1_0 } ; float * const u__uy_2[16] = { uy_2_0 } ; float * const u__uz_3[16] = { uz_3_0 } ; int _idx0; int _idx1; int _idx2; int _idx3; int _idx4; int _idx5; int idx_1_2; int pt_idx_x; int pt_idx_y; int pt_idx_z; int size_1_1; int size_1_2; //int t; int tmp; int v_idx_x; int v_idx_x_max; int v_idx_y; int v_idx_y_max; int v_idx_z; int v_idx_z_max; /* Initializations */ size_1_1=(y_max/blockDim.y); size_1_2=(z_max/blockDim.z); idx_1_2=(blockIdx.y/size_1_2); tmp=(blockIdx.y-(idx_1_2*size_1_2)); v_idx_x=(cbx*(threadIdx.x+(blockDim.x*blockIdx.x))); v_idx_x_max=(v_idx_x+cbx); v_idx_y=(threadIdx.y+(tmp*blockDim.y)); v_idx_y_max=(v_idx_y+1); v_idx_z=(threadIdx.z+(idx_1_2*blockDim.z)); v_idx_z_max=(v_idx_z+1); /* Implementation */ /* for t = 1..t_max by 1 parallel 1 <level 0> schedule { ... } */ //for (t=1; t<=t_max; t+=1) { /* Index bounds calculations for iterators in v[t=t, s=(cbx, 1, 1)][0] */ /* for POINT pt[t=t, s=(1, 1, 1)][0] of size [1, 1, 1] in v[t=t, s=(:, :, :)][0] parallel 1 <level 1> schedule default { ... } */ { /* Index bounds calculations for iterators in pt[t=t, s=(1, 1, 1)][0] */ pt_idx_z=v_idx_z; pt_idx_y=v_idx_y; for (pt_idx_x=v_idx_x; pt_idx_x<(v_idx_x_max-0); pt_idx_x+=1) { /* Index bounds calculations for iterators in pt[t=t, s=(1, 1, 1)][0] */ /* v[t=(t+1), s=pt[t=?, s=?][0]][0]=stencil(v[t=t, s=pt[t=?, s=?][0]][0]) */ /* _idx0 = ((((((pt_idx_z*x_max)+((2*pt_idx_z)*t))*y_max)+(pt_idx_y*x_max))+((2*pt_idx_y)*t))+pt_idx_x) */ _idx0=((((((pt_idx_z*x_max)+((2*pt_idx_z)*t))*y_max)+(pt_idx_y*x_max))+((2*pt_idx_y)*t))+pt_idx_x); u__ux_1[(t-1)][_idx0]=0.2; /* _idx1 = ((((pt_idx_z*x_max)*y_max)+((((2*pt_idx_z)*t)+pt_idx_y)*x_max))+pt_idx_x) */ _idx1=(((_idx0-(((2*pt_idx_z)*t)*y_max))+(((2*pt_idx_z)*t)*x_max))-((2*pt_idx_y)*t)); u__uy_2[(t-1)][_idx1]=0.30000000000000004; /* _idx2 = ((((pt_idx_z*x_max)*y_max)+(pt_idx_y*x_max))+pt_idx_x) */ _idx2=(_idx1-(((2*pt_idx_z)*t)*x_max)); u__uz_3[(t-1)][_idx2]=0.4; /* _idx3 = (((((pt_idx_z+2)*x_max)*y_max)+(pt_idx_y*x_max))+pt_idx_x) */ _idx3=(_idx2+((2*x_max)*y_max)); u__uz_3[(t-1)][_idx3]=0.4; /* _idx4 = ((((pt_idx_z*x_max)*y_max)+(((((2*pt_idx_z)*t)+pt_idx_y)+2)*x_max))+pt_idx_x) */ _idx4=(_idx1+(2*x_max)); u__uy_2[(t-1)][_idx4]=0.30000000000000004; /* _idx5 = (((((((pt_idx_z*x_max)+((2*pt_idx_z)*t))*y_max)+(pt_idx_y*x_max))+((2*pt_idx_y)*t))+pt_idx_x)+2) */ _idx5=(_idx0+2); u__ux_1[(t-1)][_idx5]=0.2; u__u_0[(t-1)][_idx2]=0.1; } } } }
#include <hip/hip_runtime.h> #define t_max 1 #define t 1 /* (u[0][0][0][0][0]=((alpha*(ux[1][0][0][0][1]-ux[-1][0][0][0][1]))+((beta*(uy[0][1][0][0][2]-uy[0][-1][0][0][2]))+(gamma*(uz[0][0][1][0][3]-uz[0][0][-1][0][3]))))) */ __global__ void divergence(float * * u_0_0_out, float * u_0_0, float * ux_1_0, float * uy_2_0, float * uz_3_0, float alpha, float beta, float gamma, int x_max, int y_max, int z_max, int cbx) { /*float * const u__u_0[16] = { u_0_0 } ; float * const u__ux_1[16] = { ux_1_0 } ; float * const u__uy_2[16] = { uy_2_0 } ; float * const u__uz_3[16] = { uz_3_0 } ;*/ int _idx0; int _idx1; int _idx2; int _idx3; int _idx4; int _idx5; int idx_1_2; int pt_idx_x; int pt_idx_y; int pt_idx_z; int size_1_1; int size_1_2; //int t; int tmp; int v_idx_x; int v_idx_x_max; int v_idx_y; int v_idx_y_max; int v_idx_z; int v_idx_z_max; /* Initializations */ size_1_1=(y_max/blockDim.y); size_1_2=(z_max/blockDim.z); idx_1_2=(blockIdx.y/size_1_2); tmp=(blockIdx.y-(idx_1_2*size_1_2)); v_idx_x=(cbx*(threadIdx.x+(blockDim.x*blockIdx.x))); v_idx_x_max=(v_idx_x+cbx); v_idx_y=(threadIdx.y+(tmp*blockDim.y)); v_idx_y_max=(v_idx_y+1); v_idx_z=(threadIdx.z+(idx_1_2*blockDim.z)); v_idx_z_max=(v_idx_z+1); /* Implementation */ /* for t = 1..t_max by 1 parallel 1 <level 0> schedule { ... } */ //for (t=1; t<=t_max; t+=1) { /* Index bounds calculations for iterators in v[t=t, s=(cbx, 1, 1)][0] */ /* for POINT pt[t=t, s=(1, 1, 1)][0] of size [1, 1, 1] in v[t=t, s=(:, :, :)][0] parallel 1 <level 1> schedule default { ... } */ { /* Index bounds calculations for iterators in pt[t=t, s=(1, 1, 1)][0] */ pt_idx_z=v_idx_z; pt_idx_y=v_idx_y; for (pt_idx_x=v_idx_x; pt_idx_x<(v_idx_x_max-0); pt_idx_x+=1) { /* Index bounds calculations for iterators in pt[t=t, s=(1, 1, 1)][0] */ /* v[t=(t+1), s=pt[t=?, s=?][0]][0]=stencil(v[t=t, s=pt[t=?, s=?][0]][0]) */ /* _idx0 = (((((((pt_idx_z*x_max)+((2*pt_idx_z)*t))*y_max)+(pt_idx_y*x_max))+((2*pt_idx_y)*t))+pt_idx_x)+2) */ _idx0=(((((((pt_idx_z*x_max)+((2*pt_idx_z)*t))*y_max)+(pt_idx_y*x_max))+((2*pt_idx_y)*t))+pt_idx_x)+2); /* _idx1 = ((((((pt_idx_z*x_max)+((2*pt_idx_z)*t))*y_max)+(pt_idx_y*x_max))+((2*pt_idx_y)*t))+pt_idx_x) */ _idx1=(_idx0-2); /* _idx2 = ((((pt_idx_z*x_max)*y_max)+(((((2*pt_idx_z)*t)+pt_idx_y)+2)*x_max))+pt_idx_x) */ _idx2=(((_idx1-(((2*pt_idx_z)*t)*y_max))+((((2*pt_idx_z)*t)+2)*x_max))-((2*pt_idx_y)*t)); /* _idx3 = ((((pt_idx_z*x_max)*y_max)+((((2*pt_idx_z)*t)+pt_idx_y)*x_max))+pt_idx_x) */ _idx3=(_idx2-(2*x_max)); /* _idx4 = (((((pt_idx_z+2)*x_max)*y_max)+(pt_idx_y*x_max))+pt_idx_x) */ _idx4=((_idx3+((2*x_max)*y_max))-(((2*pt_idx_z)*t)*x_max)); /* _idx5 = ((((pt_idx_z*x_max)*y_max)+(pt_idx_y*x_max))+pt_idx_x) */ _idx5=(_idx4-((2*x_max)*y_max)); u_0_0[_idx5]=((alpha*(ux_1_0[_idx0]-ux_1_0[_idx1]))+((beta*(uy_2_0[_idx2]-uy_2_0[_idx3]))+(gamma*(uz_3_0[_idx4]-uz_3_0[_idx5])))); } } } } __global__ void initialize(float * u_0_0, float * ux_1_0, float * uy_2_0, float * uz_3_0, float alpha, float beta, float gamma, int x_max, int y_max, int z_max, int cbx) { float * const u__u_0[16] = { u_0_0 } ; float * const u__ux_1[16] = { ux_1_0 } ; float * const u__uy_2[16] = { uy_2_0 } ; float * const u__uz_3[16] = { uz_3_0 } ; int _idx0; int _idx1; int _idx2; int _idx3; int _idx4; int _idx5; int idx_1_2; int pt_idx_x; int pt_idx_y; int pt_idx_z; int size_1_1; int size_1_2; //int t; int tmp; int v_idx_x; int v_idx_x_max; int v_idx_y; int v_idx_y_max; int v_idx_z; int v_idx_z_max; /* Initializations */ size_1_1=(y_max/blockDim.y); size_1_2=(z_max/blockDim.z); idx_1_2=(blockIdx.y/size_1_2); tmp=(blockIdx.y-(idx_1_2*size_1_2)); v_idx_x=(cbx*(threadIdx.x+(blockDim.x*blockIdx.x))); v_idx_x_max=(v_idx_x+cbx); v_idx_y=(threadIdx.y+(tmp*blockDim.y)); v_idx_y_max=(v_idx_y+1); v_idx_z=(threadIdx.z+(idx_1_2*blockDim.z)); v_idx_z_max=(v_idx_z+1); /* Implementation */ /* for t = 1..t_max by 1 parallel 1 <level 0> schedule { ... } */ //for (t=1; t<=t_max; t+=1) { /* Index bounds calculations for iterators in v[t=t, s=(cbx, 1, 1)][0] */ /* for POINT pt[t=t, s=(1, 1, 1)][0] of size [1, 1, 1] in v[t=t, s=(:, :, :)][0] parallel 1 <level 1> schedule default { ... } */ { /* Index bounds calculations for iterators in pt[t=t, s=(1, 1, 1)][0] */ pt_idx_z=v_idx_z; pt_idx_y=v_idx_y; for (pt_idx_x=v_idx_x; pt_idx_x<(v_idx_x_max-0); pt_idx_x+=1) { /* Index bounds calculations for iterators in pt[t=t, s=(1, 1, 1)][0] */ /* v[t=(t+1), s=pt[t=?, s=?][0]][0]=stencil(v[t=t, s=pt[t=?, s=?][0]][0]) */ /* _idx0 = ((((((pt_idx_z*x_max)+((2*pt_idx_z)*t))*y_max)+(pt_idx_y*x_max))+((2*pt_idx_y)*t))+pt_idx_x) */ _idx0=((((((pt_idx_z*x_max)+((2*pt_idx_z)*t))*y_max)+(pt_idx_y*x_max))+((2*pt_idx_y)*t))+pt_idx_x); u__ux_1[(t-1)][_idx0]=0.2; /* _idx1 = ((((pt_idx_z*x_max)*y_max)+((((2*pt_idx_z)*t)+pt_idx_y)*x_max))+pt_idx_x) */ _idx1=(((_idx0-(((2*pt_idx_z)*t)*y_max))+(((2*pt_idx_z)*t)*x_max))-((2*pt_idx_y)*t)); u__uy_2[(t-1)][_idx1]=0.30000000000000004; /* _idx2 = ((((pt_idx_z*x_max)*y_max)+(pt_idx_y*x_max))+pt_idx_x) */ _idx2=(_idx1-(((2*pt_idx_z)*t)*x_max)); u__uz_3[(t-1)][_idx2]=0.4; /* _idx3 = (((((pt_idx_z+2)*x_max)*y_max)+(pt_idx_y*x_max))+pt_idx_x) */ _idx3=(_idx2+((2*x_max)*y_max)); u__uz_3[(t-1)][_idx3]=0.4; /* _idx4 = ((((pt_idx_z*x_max)*y_max)+(((((2*pt_idx_z)*t)+pt_idx_y)+2)*x_max))+pt_idx_x) */ _idx4=(_idx1+(2*x_max)); u__uy_2[(t-1)][_idx4]=0.30000000000000004; /* _idx5 = (((((((pt_idx_z*x_max)+((2*pt_idx_z)*t))*y_max)+(pt_idx_y*x_max))+((2*pt_idx_y)*t))+pt_idx_x)+2) */ _idx5=(_idx0+2); u__ux_1[(t-1)][_idx5]=0.2; u__u_0[(t-1)][_idx2]=0.1; } } } }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <hip/hip_runtime.h> #define t_max 1 #define t 1 /* (u[0][0][0][0][0]=((alpha*(ux[1][0][0][0][1]-ux[-1][0][0][0][1]))+((beta*(uy[0][1][0][0][2]-uy[0][-1][0][0][2]))+(gamma*(uz[0][0][1][0][3]-uz[0][0][-1][0][3]))))) */ __global__ void divergence(float * * u_0_0_out, float * u_0_0, float * ux_1_0, float * uy_2_0, float * uz_3_0, float alpha, float beta, float gamma, int x_max, int y_max, int z_max, int cbx) { /*float * const u__u_0[16] = { u_0_0 } ; float * const u__ux_1[16] = { ux_1_0 } ; float * const u__uy_2[16] = { uy_2_0 } ; float * const u__uz_3[16] = { uz_3_0 } ;*/ int _idx0; int _idx1; int _idx2; int _idx3; int _idx4; int _idx5; int idx_1_2; int pt_idx_x; int pt_idx_y; int pt_idx_z; int size_1_1; int size_1_2; //int t; int tmp; int v_idx_x; int v_idx_x_max; int v_idx_y; int v_idx_y_max; int v_idx_z; int v_idx_z_max; /* Initializations */ size_1_1=(y_max/blockDim.y); size_1_2=(z_max/blockDim.z); idx_1_2=(blockIdx.y/size_1_2); tmp=(blockIdx.y-(idx_1_2*size_1_2)); v_idx_x=(cbx*(threadIdx.x+(blockDim.x*blockIdx.x))); v_idx_x_max=(v_idx_x+cbx); v_idx_y=(threadIdx.y+(tmp*blockDim.y)); v_idx_y_max=(v_idx_y+1); v_idx_z=(threadIdx.z+(idx_1_2*blockDim.z)); v_idx_z_max=(v_idx_z+1); /* Implementation */ /* for t = 1..t_max by 1 parallel 1 <level 0> schedule { ... } */ //for (t=1; t<=t_max; t+=1) { /* Index bounds calculations for iterators in v[t=t, s=(cbx, 1, 1)][0] */ /* for POINT pt[t=t, s=(1, 1, 1)][0] of size [1, 1, 1] in v[t=t, s=(:, :, :)][0] parallel 1 <level 1> schedule default { ... } */ { /* Index bounds calculations for iterators in pt[t=t, s=(1, 1, 1)][0] */ pt_idx_z=v_idx_z; pt_idx_y=v_idx_y; for (pt_idx_x=v_idx_x; pt_idx_x<(v_idx_x_max-0); pt_idx_x+=1) { /* Index bounds calculations for iterators in pt[t=t, s=(1, 1, 1)][0] */ /* v[t=(t+1), s=pt[t=?, s=?][0]][0]=stencil(v[t=t, s=pt[t=?, s=?][0]][0]) */ /* _idx0 = (((((((pt_idx_z*x_max)+((2*pt_idx_z)*t))*y_max)+(pt_idx_y*x_max))+((2*pt_idx_y)*t))+pt_idx_x)+2) */ _idx0=(((((((pt_idx_z*x_max)+((2*pt_idx_z)*t))*y_max)+(pt_idx_y*x_max))+((2*pt_idx_y)*t))+pt_idx_x)+2); /* _idx1 = ((((((pt_idx_z*x_max)+((2*pt_idx_z)*t))*y_max)+(pt_idx_y*x_max))+((2*pt_idx_y)*t))+pt_idx_x) */ _idx1=(_idx0-2); /* _idx2 = ((((pt_idx_z*x_max)*y_max)+(((((2*pt_idx_z)*t)+pt_idx_y)+2)*x_max))+pt_idx_x) */ _idx2=(((_idx1-(((2*pt_idx_z)*t)*y_max))+((((2*pt_idx_z)*t)+2)*x_max))-((2*pt_idx_y)*t)); /* _idx3 = ((((pt_idx_z*x_max)*y_max)+((((2*pt_idx_z)*t)+pt_idx_y)*x_max))+pt_idx_x) */ _idx3=(_idx2-(2*x_max)); /* _idx4 = (((((pt_idx_z+2)*x_max)*y_max)+(pt_idx_y*x_max))+pt_idx_x) */ _idx4=((_idx3+((2*x_max)*y_max))-(((2*pt_idx_z)*t)*x_max)); /* _idx5 = ((((pt_idx_z*x_max)*y_max)+(pt_idx_y*x_max))+pt_idx_x) */ _idx5=(_idx4-((2*x_max)*y_max)); u_0_0[_idx5]=((alpha*(ux_1_0[_idx0]-ux_1_0[_idx1]))+((beta*(uy_2_0[_idx2]-uy_2_0[_idx3]))+(gamma*(uz_3_0[_idx4]-uz_3_0[_idx5])))); } } } } __global__ void initialize(float * u_0_0, float * ux_1_0, float * uy_2_0, float * uz_3_0, float alpha, float beta, float gamma, int x_max, int y_max, int z_max, int cbx) { float * const u__u_0[16] = { u_0_0 } ; float * const u__ux_1[16] = { ux_1_0 } ; float * const u__uy_2[16] = { uy_2_0 } ; float * const u__uz_3[16] = { uz_3_0 } ; int _idx0; int _idx1; int _idx2; int _idx3; int _idx4; int _idx5; int idx_1_2; int pt_idx_x; int pt_idx_y; int pt_idx_z; int size_1_1; int size_1_2; //int t; int tmp; int v_idx_x; int v_idx_x_max; int v_idx_y; int v_idx_y_max; int v_idx_z; int v_idx_z_max; /* Initializations */ size_1_1=(y_max/blockDim.y); size_1_2=(z_max/blockDim.z); idx_1_2=(blockIdx.y/size_1_2); tmp=(blockIdx.y-(idx_1_2*size_1_2)); v_idx_x=(cbx*(threadIdx.x+(blockDim.x*blockIdx.x))); v_idx_x_max=(v_idx_x+cbx); v_idx_y=(threadIdx.y+(tmp*blockDim.y)); v_idx_y_max=(v_idx_y+1); v_idx_z=(threadIdx.z+(idx_1_2*blockDim.z)); v_idx_z_max=(v_idx_z+1); /* Implementation */ /* for t = 1..t_max by 1 parallel 1 <level 0> schedule { ... } */ //for (t=1; t<=t_max; t+=1) { /* Index bounds calculations for iterators in v[t=t, s=(cbx, 1, 1)][0] */ /* for POINT pt[t=t, s=(1, 1, 1)][0] of size [1, 1, 1] in v[t=t, s=(:, :, :)][0] parallel 1 <level 1> schedule default { ... } */ { /* Index bounds calculations for iterators in pt[t=t, s=(1, 1, 1)][0] */ pt_idx_z=v_idx_z; pt_idx_y=v_idx_y; for (pt_idx_x=v_idx_x; pt_idx_x<(v_idx_x_max-0); pt_idx_x+=1) { /* Index bounds calculations for iterators in pt[t=t, s=(1, 1, 1)][0] */ /* v[t=(t+1), s=pt[t=?, s=?][0]][0]=stencil(v[t=t, s=pt[t=?, s=?][0]][0]) */ /* _idx0 = ((((((pt_idx_z*x_max)+((2*pt_idx_z)*t))*y_max)+(pt_idx_y*x_max))+((2*pt_idx_y)*t))+pt_idx_x) */ _idx0=((((((pt_idx_z*x_max)+((2*pt_idx_z)*t))*y_max)+(pt_idx_y*x_max))+((2*pt_idx_y)*t))+pt_idx_x); u__ux_1[(t-1)][_idx0]=0.2; /* _idx1 = ((((pt_idx_z*x_max)*y_max)+((((2*pt_idx_z)*t)+pt_idx_y)*x_max))+pt_idx_x) */ _idx1=(((_idx0-(((2*pt_idx_z)*t)*y_max))+(((2*pt_idx_z)*t)*x_max))-((2*pt_idx_y)*t)); u__uy_2[(t-1)][_idx1]=0.30000000000000004; /* _idx2 = ((((pt_idx_z*x_max)*y_max)+(pt_idx_y*x_max))+pt_idx_x) */ _idx2=(_idx1-(((2*pt_idx_z)*t)*x_max)); u__uz_3[(t-1)][_idx2]=0.4; /* _idx3 = (((((pt_idx_z+2)*x_max)*y_max)+(pt_idx_y*x_max))+pt_idx_x) */ _idx3=(_idx2+((2*x_max)*y_max)); u__uz_3[(t-1)][_idx3]=0.4; /* _idx4 = ((((pt_idx_z*x_max)*y_max)+(((((2*pt_idx_z)*t)+pt_idx_y)+2)*x_max))+pt_idx_x) */ _idx4=(_idx1+(2*x_max)); u__uy_2[(t-1)][_idx4]=0.30000000000000004; /* _idx5 = (((((((pt_idx_z*x_max)+((2*pt_idx_z)*t))*y_max)+(pt_idx_y*x_max))+((2*pt_idx_y)*t))+pt_idx_x)+2) */ _idx5=(_idx0+2); u__ux_1[(t-1)][_idx5]=0.2; u__u_0[(t-1)][_idx2]=0.1; } } } }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z10divergencePPfS_S_S_S_fffiiii .globl _Z10divergencePPfS_S_S_S_fffiiii .p2align 8 .type _Z10divergencePPfS_S_S_S_fffiiii,@function _Z10divergencePPfS_S_S_S_fffiiii: s_load_b32 s2, s[0:1], 0x40 s_waitcnt lgkmcnt(0) s_cmp_lt_i32 s2, 1 s_cbranch_scc1 .LBB0_3 s_clause 0x2 s_load_b64 s[12:13], s[0:1], 0x54 s_load_b64 s[20:21], s[0:1], 0x38 s_load_b128 s[16:19], s[0:1], 0x28 v_bfe_u32 v2, v0, 20, 10 s_waitcnt lgkmcnt(0) s_and_b32 s3, s13, 0xffff s_and_b32 s6, s12, 0xffff v_cvt_f32_u32_e32 v1, s3 s_sub_i32 s5, 0, s3 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_iflag_f32_e32 v1, v1 s_waitcnt_depctr 0xfff v_mul_f32_e32 v1, 0x4f7ffffe, v1 v_cvt_u32_f32_e32 v1, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s4, v1 s_mul_i32 s5, s5, s4 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_mul_hi_u32 s5, s4, s5 s_add_i32 s4, s4, s5 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_mul_hi_u32 s4, s21, s4 s_mul_i32 s5, s4, s3 s_add_i32 s7, s4, 1 s_sub_i32 s5, s21, s5 s_delay_alu instid0(SALU_CYCLE_1) s_sub_i32 s8, s5, s3 s_cmp_ge_u32 s5, s3 s_cselect_b32 s4, s7, s4 s_cselect_b32 s5, s8, s5 s_add_i32 s7, s4, 1 s_cmp_ge_u32 s5, s3 s_cselect_b32 s13, s7, s4 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cvt_f32_u32_e32 v1, s13 s_sub_i32 s5, 0, s13 v_rcp_iflag_f32_e32 v1, v1 s_waitcnt_depctr 0xfff v_mul_f32_e32 v1, 0x4f7ffffe, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cvt_u32_f32_e32 v1, v1 v_readfirstlane_b32 s4, v1 v_and_b32_e32 v1, 0x3ff, v0 v_bfe_u32 v0, v0, 10, 10 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) s_mul_i32 s5, s5, s4 v_mad_u64_u32 v[3:4], null, s14, s6, v[1:2] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_lshlrev_b32_e32 v8, 1, v0 s_mul_hi_u32 s5, s4, s5 s_add_i32 s4, s4, s5 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_mul_hi_u32 s4, s15, s4 s_mul_i32 s5, s4, s13 s_add_i32 s7, s4, 1 s_sub_i32 s5, s15, s5 s_delay_alu instid0(SALU_CYCLE_1) s_sub_i32 s8, s5, s13 s_cmp_ge_u32 s5, s13 s_cselect_b32 s14, s7, s4 s_cselect_b32 s4, s8, s5 s_add_i32 s21, s14, 1 s_cmp_ge_u32 s4, s13 s_load_b256 s[4:11], s[0:1], 0x8 s_cselect_b32 s0, s21, s14 s_lshr_b32 s1, s12, 16 v_mad_u64_u32 v[4:5], null, s0, s3, v[2:3] s_add_i32 s12, s20, 2 v_mul_lo_u32 v2, v3, s2 s_mul_i32 s0, s0, s13 s_add_i32 s3, s19, 2 s_sub_i32 s0, s15, s0 s_mul_i32 s3, s3, s20 s_delay_alu instid0(VALU_DEP_2) v_add_nc_u32_e32 v1, 2, v4 v_mul_lo_u32 v3, v4, s12 v_mul_lo_u32 v5, s20, v4 s_mul_i32 s0, s0, s1 v_mul_lo_u32 v4, s3, v4 v_mul_lo_u32 v1, s20, v1 v_add_nc_u32_e32 v6, s0, v0 s_lshl_b32 s1, s0, 1 v_add3_u32 v7, v0, v3, s0 v_add3_u32 v3, v0, v5, s0 s_delay_alu instid0(VALU_DEP_3) v_mul_lo_u32 v9, v6, s19 v_add3_u32 v10, v4, s1, v2 v_add3_u32 v0, v0, v1, s0 v_add_nc_u32_e32 v1, 2, v7 v_mul_lo_u32 v3, s19, v3 v_mul_lo_u32 v4, s19, v7 v_add_nc_u32_e32 v7, s2, v2 v_mul_lo_u32 v5, s19, v0 v_mul_lo_u32 v6, s19, v1 v_add3_u32 v0, v10, v9, v8 s_mov_b32 s1, 0 .LBB0_2: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v8, v6, v2 v_ashrrev_i32_e32 v1, 31, v0 v_add_nc_u32_e32 v12, v5, v2 v_add_nc_u32_e32 v14, v3, v2 v_add_nc_u32_e32 v10, v4, v2 v_ashrrev_i32_e32 v9, 31, v8 v_lshlrev_b64 v[16:17], 2, v[0:1] v_ashrrev_i32_e32 v13, 31, v12 v_ashrrev_i32_e32 v15, 31, v14 v_ashrrev_i32_e32 v11, 31, v10 v_lshlrev_b64 v[8:9], 2, v[8:9] v_add_nc_u32_e32 v2, 1, v2 v_lshlrev_b64 v[12:13], 2, v[12:13] s_waitcnt lgkmcnt(0) v_add_co_u32 v16, vcc_lo, s6, v16 v_add_co_ci_u32_e32 v17, vcc_lo, s7, v17, vcc_lo v_lshlrev_b64 v[14:15], 2, v[14:15] v_add_co_u32 v8, vcc_lo, s8, v8 v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo v_lshlrev_b64 v[10:11], 2, v[10:11] v_add_co_u32 v12, vcc_lo, s10, v12 v_add_co_ci_u32_e32 v13, vcc_lo, s11, v13, vcc_lo v_add_co_u32 v18, vcc_lo, s10, v14 v_add_co_ci_u32_e32 v19, vcc_lo, s11, v15, vcc_lo v_add_co_u32 v10, vcc_lo, s8, v10 v_add_co_ci_u32_e32 v11, vcc_lo, s9, v11, vcc_lo s_clause 0x1 global_load_b32 v1, v[12:13], off global_load_b32 v12, v[18:19], off s_clause 0x1 global_load_b32 v8, v[8:9], off global_load_b32 v9, v[10:11], off s_clause 0x1 global_load_b32 v10, v[16:17], off offset:8 global_load_b32 v11, v[16:17], off v_cmp_ge_i32_e32 vcc_lo, v2, v7 v_add_nc_u32_e32 v0, 1, v0 s_or_b32 s1, vcc_lo, s1 s_waitcnt vmcnt(0) v_dual_sub_f32 v1, v1, v12 :: v_dual_sub_f32 v10, v10, v11 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mul_f32_e32 v1, s18, v1 v_sub_f32_e32 v8, v8, v9 v_fmac_f32_e32 v1, s17, v8 v_add_co_u32 v8, s0, s4, v14 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_ci_u32_e64 v9, s0, s5, v15, s0 v_fmac_f32_e32 v1, s16, v10 global_store_b32 v[8:9], v1, off s_and_not1_b32 exec_lo, exec_lo, s1 s_cbranch_execnz .LBB0_2 .LBB0_3: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z10divergencePPfS_S_S_S_fffiiii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 328 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 2 .amdhsa_next_free_vgpr 20 .amdhsa_next_free_sgpr 22 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z10divergencePPfS_S_S_S_fffiiii, .Lfunc_end0-_Z10divergencePPfS_S_S_S_fffiiii .section .AMDGPU.csdata,"",@progbits .text .protected _Z10initializePfS_S_S_fffiiii .globl _Z10initializePfS_S_S_fffiiii .p2align 8 .type _Z10initializePfS_S_S_fffiiii,@function _Z10initializePfS_S_S_fffiiii: s_load_b32 s8, s[0:1], 0x38 s_waitcnt lgkmcnt(0) s_cmp_lt_i32 s8, 1 s_cbranch_scc1 .LBB1_3 s_clause 0x2 s_load_b64 s[10:11], s[0:1], 0x4c s_load_b32 s2, s[0:1], 0x34 s_load_b64 s[12:13], s[0:1], 0x2c v_bfe_u32 v3, v0, 20, 10 v_mov_b32_e32 v11, 0x3dcccccd v_mov_b32_e32 v10, 0x3ecccccd s_waitcnt lgkmcnt(0) s_and_b32 s9, s11, 0xffff s_and_b32 s11, s10, 0xffff v_cvt_f32_u32_e32 v1, s9 s_sub_i32 s4, 0, s9 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_iflag_f32_e32 v1, v1 s_waitcnt_depctr 0xfff v_mul_f32_e32 v1, 0x4f7ffffe, v1 v_cvt_u32_f32_e32 v1, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_readfirstlane_b32 s3, v1 s_mul_i32 s4, s4, s3 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_mul_hi_u32 s4, s3, s4 s_add_i32 s3, s3, s4 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_mul_hi_u32 s3, s2, s3 s_mul_i32 s4, s3, s9 s_delay_alu instid0(SALU_CYCLE_1) s_sub_i32 s2, s2, s4 s_add_i32 s4, s3, 1 s_sub_i32 s5, s2, s9 s_cmp_ge_u32 s2, s9 s_cselect_b32 s3, s4, s3 s_cselect_b32 s2, s5, s2 s_add_i32 s4, s3, 1 s_cmp_ge_u32 s2, s9 s_cselect_b32 s16, s4, s3 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cvt_f32_u32_e32 v1, s16 s_sub_i32 s2, 0, s16 v_rcp_iflag_f32_e32 v1, v1 s_waitcnt_depctr 0xfff v_mul_f32_e32 v1, 0x4f7ffffe, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cvt_u32_f32_e32 v1, v1 v_readfirstlane_b32 s17, v1 v_and_b32_e32 v1, 0x3ff, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) s_mul_i32 s2, s2, s17 v_mad_u64_u32 v[4:5], null, s14, s11, v[1:2] s_mul_hi_u32 s18, s17, s2 v_bfe_u32 v5, v0, 10, 10 s_add_i32 s17, s17, s18 s_load_b256 s[0:7], s[0:1], 0x0 s_mul_hi_u32 s17, s15, s17 s_delay_alu instid0(SALU_CYCLE_1) s_mul_i32 s18, s17, s16 s_add_i32 s14, s17, 1 s_sub_i32 s11, s15, s18 v_mul_lo_u32 v2, v4, s8 s_sub_i32 s18, s11, s16 s_cmp_ge_u32 s11, s16 v_lshlrev_b32_e32 v8, 1, v5 s_cselect_b32 s14, s14, s17 s_cselect_b32 s11, s18, s11 s_add_i32 s17, s14, 1 s_cmp_ge_u32 s11, s16 s_cselect_b32 s11, s17, s14 s_add_i32 s14, s13, 2 v_mad_u64_u32 v[0:1], null, s11, s9, v[3:4] s_mul_i32 s11, s11, s16 s_lshr_b32 s9, s10, 16 s_add_i32 s10, s12, 2 s_sub_i32 s11, s15, s11 s_mul_i32 s10, s10, s13 s_mul_i32 s11, s11, s9 s_delay_alu instid0(VALU_DEP_1) v_add_nc_u32_e32 v1, 2, v0 v_mul_lo_u32 v4, v0, s14 v_add_nc_u32_e32 v6, s11, v5 v_mul_lo_u32 v7, s13, v0 v_mul_lo_u32 v0, s10, v0 v_add_nc_u32_e32 v3, s8, v2 s_lshl_b32 s8, s11, 1 v_mul_lo_u32 v6, v6, s12 v_add3_u32 v4, v5, v4, s11 v_add3_u32 v7, v5, v7, s11 v_add3_u32 v0, v0, s8, v2 s_mov_b32 s8, 0 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_nc_u32_e32 v9, 2, v4 v_mul_lo_u32 v4, s12, v4 v_add3_u32 v0, v0, v6, v8 v_mov_b32_e32 v8, 0x3e4ccccd v_mul_lo_u32 v1, s13, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4) v_add3_u32 v1, v5, v1, s11 v_mul_lo_u32 v5, s12, v7 v_mul_lo_u32 v7, s12, v9 v_mov_b32_e32 v9, 0x3e99999a v_mul_lo_u32 v6, s12, v1 .LBB1_2: v_add_nc_u32_e32 v12, v4, v2 v_ashrrev_i32_e32 v1, 31, v0 v_add_nc_u32_e32 v14, v5, v2 s_delay_alu instid0(VALU_DEP_4) v_add_nc_u32_e32 v16, v6, v2 v_add_nc_u32_e32 v18, v7, v2 v_add_nc_u32_e32 v2, 1, v2 v_ashrrev_i32_e32 v13, 31, v12 v_lshlrev_b64 v[20:21], 2, v[0:1] v_ashrrev_i32_e32 v15, 31, v14 v_ashrrev_i32_e32 v17, 31, v16 v_cmp_ge_i32_e32 vcc_lo, v2, v3 v_lshlrev_b64 v[12:13], 2, v[12:13] v_ashrrev_i32_e32 v19, 31, v18 v_lshlrev_b64 v[14:15], 2, v[14:15] v_lshlrev_b64 v[16:17], 2, v[16:17] s_or_b32 s8, vcc_lo, s8 s_waitcnt lgkmcnt(0) v_add_co_u32 v20, vcc_lo, s2, v20 v_add_co_ci_u32_e32 v21, vcc_lo, s3, v21, vcc_lo v_add_co_u32 v12, vcc_lo, s4, v12 v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo v_lshlrev_b64 v[18:19], 2, v[18:19] v_add_co_u32 v22, vcc_lo, s6, v14 v_add_co_ci_u32_e32 v23, vcc_lo, s7, v15, vcc_lo v_add_co_u32 v16, vcc_lo, s6, v16 v_add_co_ci_u32_e32 v17, vcc_lo, s7, v17, vcc_lo v_add_nc_u32_e32 v0, 1, v0 v_add_co_u32 v18, vcc_lo, s4, v18 v_add_co_ci_u32_e32 v19, vcc_lo, s5, v19, vcc_lo v_add_co_u32 v14, vcc_lo, s0, v14 global_store_b32 v[20:21], v8, off v_add_co_ci_u32_e32 v15, vcc_lo, s1, v15, vcc_lo global_store_b32 v[12:13], v9, off s_clause 0x1 global_store_b32 v[22:23], v10, off global_store_b32 v[16:17], v10, off global_store_b32 v[18:19], v9, off global_store_b32 v[20:21], v8, off offset:8 global_store_b32 v[14:15], v11, off s_and_not1_b32 exec_lo, exec_lo, s8 s_cbranch_execnz .LBB1_2 .LBB1_3: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z10initializePfS_S_S_fffiiii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 320 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 2 .amdhsa_next_free_vgpr 24 .amdhsa_next_free_sgpr 19 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z10initializePfS_S_S_fffiiii, .Lfunc_end1-_Z10initializePfS_S_S_fffiiii .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .offset: 40 .size: 4 .value_kind: by_value - .offset: 44 .size: 4 .value_kind: by_value - .offset: 48 .size: 4 .value_kind: by_value - .offset: 52 .size: 4 .value_kind: by_value - .offset: 56 .size: 4 .value_kind: by_value - .offset: 60 .size: 4 .value_kind: by_value - .offset: 64 .size: 4 .value_kind: by_value - .offset: 72 .size: 4 .value_kind: hidden_block_count_x - .offset: 76 .size: 4 .value_kind: hidden_block_count_y - .offset: 80 .size: 4 .value_kind: hidden_block_count_z - .offset: 84 .size: 2 .value_kind: hidden_group_size_x - .offset: 86 .size: 2 .value_kind: hidden_group_size_y - .offset: 88 .size: 2 .value_kind: hidden_group_size_z - .offset: 90 .size: 2 .value_kind: hidden_remainder_x - .offset: 92 .size: 2 .value_kind: hidden_remainder_y - .offset: 94 .size: 2 .value_kind: hidden_remainder_z - .offset: 112 .size: 8 .value_kind: hidden_global_offset_x - .offset: 120 .size: 8 .value_kind: hidden_global_offset_y - .offset: 128 .size: 8 .value_kind: hidden_global_offset_z - .offset: 136 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 328 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z10divergencePPfS_S_S_S_fffiiii .private_segment_fixed_size: 0 .sgpr_count: 24 .sgpr_spill_count: 0 .symbol: _Z10divergencePPfS_S_S_S_fffiiii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 20 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .offset: 32 .size: 4 .value_kind: by_value - .offset: 36 .size: 4 .value_kind: by_value - .offset: 40 .size: 4 .value_kind: by_value - .offset: 44 .size: 4 .value_kind: by_value - .offset: 48 .size: 4 .value_kind: by_value - .offset: 52 .size: 4 .value_kind: by_value - .offset: 56 .size: 4 .value_kind: by_value - .offset: 64 .size: 4 .value_kind: hidden_block_count_x - .offset: 68 .size: 4 .value_kind: hidden_block_count_y - .offset: 72 .size: 4 .value_kind: hidden_block_count_z - .offset: 76 .size: 2 .value_kind: hidden_group_size_x - .offset: 78 .size: 2 .value_kind: hidden_group_size_y - .offset: 80 .size: 2 .value_kind: hidden_group_size_z - .offset: 82 .size: 2 .value_kind: hidden_remainder_x - .offset: 84 .size: 2 .value_kind: hidden_remainder_y - .offset: 86 .size: 2 .value_kind: hidden_remainder_z - .offset: 104 .size: 8 .value_kind: hidden_global_offset_x - .offset: 112 .size: 8 .value_kind: hidden_global_offset_y - .offset: 120 .size: 8 .value_kind: hidden_global_offset_z - .offset: 128 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 320 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z10initializePfS_S_S_fffiiii .private_segment_fixed_size: 0 .sgpr_count: 21 .sgpr_spill_count: 0 .symbol: _Z10initializePfS_S_S_fffiiii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 24 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <hip/hip_runtime.h> #define t_max 1 #define t 1 /* (u[0][0][0][0][0]=((alpha*(ux[1][0][0][0][1]-ux[-1][0][0][0][1]))+((beta*(uy[0][1][0][0][2]-uy[0][-1][0][0][2]))+(gamma*(uz[0][0][1][0][3]-uz[0][0][-1][0][3]))))) */ __global__ void divergence(float * * u_0_0_out, float * u_0_0, float * ux_1_0, float * uy_2_0, float * uz_3_0, float alpha, float beta, float gamma, int x_max, int y_max, int z_max, int cbx) { /*float * const u__u_0[16] = { u_0_0 } ; float * const u__ux_1[16] = { ux_1_0 } ; float * const u__uy_2[16] = { uy_2_0 } ; float * const u__uz_3[16] = { uz_3_0 } ;*/ int _idx0; int _idx1; int _idx2; int _idx3; int _idx4; int _idx5; int idx_1_2; int pt_idx_x; int pt_idx_y; int pt_idx_z; int size_1_1; int size_1_2; //int t; int tmp; int v_idx_x; int v_idx_x_max; int v_idx_y; int v_idx_y_max; int v_idx_z; int v_idx_z_max; /* Initializations */ size_1_1=(y_max/blockDim.y); size_1_2=(z_max/blockDim.z); idx_1_2=(blockIdx.y/size_1_2); tmp=(blockIdx.y-(idx_1_2*size_1_2)); v_idx_x=(cbx*(threadIdx.x+(blockDim.x*blockIdx.x))); v_idx_x_max=(v_idx_x+cbx); v_idx_y=(threadIdx.y+(tmp*blockDim.y)); v_idx_y_max=(v_idx_y+1); v_idx_z=(threadIdx.z+(idx_1_2*blockDim.z)); v_idx_z_max=(v_idx_z+1); /* Implementation */ /* for t = 1..t_max by 1 parallel 1 <level 0> schedule { ... } */ //for (t=1; t<=t_max; t+=1) { /* Index bounds calculations for iterators in v[t=t, s=(cbx, 1, 1)][0] */ /* for POINT pt[t=t, s=(1, 1, 1)][0] of size [1, 1, 1] in v[t=t, s=(:, :, :)][0] parallel 1 <level 1> schedule default { ... } */ { /* Index bounds calculations for iterators in pt[t=t, s=(1, 1, 1)][0] */ pt_idx_z=v_idx_z; pt_idx_y=v_idx_y; for (pt_idx_x=v_idx_x; pt_idx_x<(v_idx_x_max-0); pt_idx_x+=1) { /* Index bounds calculations for iterators in pt[t=t, s=(1, 1, 1)][0] */ /* v[t=(t+1), s=pt[t=?, s=?][0]][0]=stencil(v[t=t, s=pt[t=?, s=?][0]][0]) */ /* _idx0 = (((((((pt_idx_z*x_max)+((2*pt_idx_z)*t))*y_max)+(pt_idx_y*x_max))+((2*pt_idx_y)*t))+pt_idx_x)+2) */ _idx0=(((((((pt_idx_z*x_max)+((2*pt_idx_z)*t))*y_max)+(pt_idx_y*x_max))+((2*pt_idx_y)*t))+pt_idx_x)+2); /* _idx1 = ((((((pt_idx_z*x_max)+((2*pt_idx_z)*t))*y_max)+(pt_idx_y*x_max))+((2*pt_idx_y)*t))+pt_idx_x) */ _idx1=(_idx0-2); /* _idx2 = ((((pt_idx_z*x_max)*y_max)+(((((2*pt_idx_z)*t)+pt_idx_y)+2)*x_max))+pt_idx_x) */ _idx2=(((_idx1-(((2*pt_idx_z)*t)*y_max))+((((2*pt_idx_z)*t)+2)*x_max))-((2*pt_idx_y)*t)); /* _idx3 = ((((pt_idx_z*x_max)*y_max)+((((2*pt_idx_z)*t)+pt_idx_y)*x_max))+pt_idx_x) */ _idx3=(_idx2-(2*x_max)); /* _idx4 = (((((pt_idx_z+2)*x_max)*y_max)+(pt_idx_y*x_max))+pt_idx_x) */ _idx4=((_idx3+((2*x_max)*y_max))-(((2*pt_idx_z)*t)*x_max)); /* _idx5 = ((((pt_idx_z*x_max)*y_max)+(pt_idx_y*x_max))+pt_idx_x) */ _idx5=(_idx4-((2*x_max)*y_max)); u_0_0[_idx5]=((alpha*(ux_1_0[_idx0]-ux_1_0[_idx1]))+((beta*(uy_2_0[_idx2]-uy_2_0[_idx3]))+(gamma*(uz_3_0[_idx4]-uz_3_0[_idx5])))); } } } } __global__ void initialize(float * u_0_0, float * ux_1_0, float * uy_2_0, float * uz_3_0, float alpha, float beta, float gamma, int x_max, int y_max, int z_max, int cbx) { float * const u__u_0[16] = { u_0_0 } ; float * const u__ux_1[16] = { ux_1_0 } ; float * const u__uy_2[16] = { uy_2_0 } ; float * const u__uz_3[16] = { uz_3_0 } ; int _idx0; int _idx1; int _idx2; int _idx3; int _idx4; int _idx5; int idx_1_2; int pt_idx_x; int pt_idx_y; int pt_idx_z; int size_1_1; int size_1_2; //int t; int tmp; int v_idx_x; int v_idx_x_max; int v_idx_y; int v_idx_y_max; int v_idx_z; int v_idx_z_max; /* Initializations */ size_1_1=(y_max/blockDim.y); size_1_2=(z_max/blockDim.z); idx_1_2=(blockIdx.y/size_1_2); tmp=(blockIdx.y-(idx_1_2*size_1_2)); v_idx_x=(cbx*(threadIdx.x+(blockDim.x*blockIdx.x))); v_idx_x_max=(v_idx_x+cbx); v_idx_y=(threadIdx.y+(tmp*blockDim.y)); v_idx_y_max=(v_idx_y+1); v_idx_z=(threadIdx.z+(idx_1_2*blockDim.z)); v_idx_z_max=(v_idx_z+1); /* Implementation */ /* for t = 1..t_max by 1 parallel 1 <level 0> schedule { ... } */ //for (t=1; t<=t_max; t+=1) { /* Index bounds calculations for iterators in v[t=t, s=(cbx, 1, 1)][0] */ /* for POINT pt[t=t, s=(1, 1, 1)][0] of size [1, 1, 1] in v[t=t, s=(:, :, :)][0] parallel 1 <level 1> schedule default { ... } */ { /* Index bounds calculations for iterators in pt[t=t, s=(1, 1, 1)][0] */ pt_idx_z=v_idx_z; pt_idx_y=v_idx_y; for (pt_idx_x=v_idx_x; pt_idx_x<(v_idx_x_max-0); pt_idx_x+=1) { /* Index bounds calculations for iterators in pt[t=t, s=(1, 1, 1)][0] */ /* v[t=(t+1), s=pt[t=?, s=?][0]][0]=stencil(v[t=t, s=pt[t=?, s=?][0]][0]) */ /* _idx0 = ((((((pt_idx_z*x_max)+((2*pt_idx_z)*t))*y_max)+(pt_idx_y*x_max))+((2*pt_idx_y)*t))+pt_idx_x) */ _idx0=((((((pt_idx_z*x_max)+((2*pt_idx_z)*t))*y_max)+(pt_idx_y*x_max))+((2*pt_idx_y)*t))+pt_idx_x); u__ux_1[(t-1)][_idx0]=0.2; /* _idx1 = ((((pt_idx_z*x_max)*y_max)+((((2*pt_idx_z)*t)+pt_idx_y)*x_max))+pt_idx_x) */ _idx1=(((_idx0-(((2*pt_idx_z)*t)*y_max))+(((2*pt_idx_z)*t)*x_max))-((2*pt_idx_y)*t)); u__uy_2[(t-1)][_idx1]=0.30000000000000004; /* _idx2 = ((((pt_idx_z*x_max)*y_max)+(pt_idx_y*x_max))+pt_idx_x) */ _idx2=(_idx1-(((2*pt_idx_z)*t)*x_max)); u__uz_3[(t-1)][_idx2]=0.4; /* _idx3 = (((((pt_idx_z+2)*x_max)*y_max)+(pt_idx_y*x_max))+pt_idx_x) */ _idx3=(_idx2+((2*x_max)*y_max)); u__uz_3[(t-1)][_idx3]=0.4; /* _idx4 = ((((pt_idx_z*x_max)*y_max)+(((((2*pt_idx_z)*t)+pt_idx_y)+2)*x_max))+pt_idx_x) */ _idx4=(_idx1+(2*x_max)); u__uy_2[(t-1)][_idx4]=0.30000000000000004; /* _idx5 = (((((((pt_idx_z*x_max)+((2*pt_idx_z)*t))*y_max)+(pt_idx_y*x_max))+((2*pt_idx_y)*t))+pt_idx_x)+2) */ _idx5=(_idx0+2); u__ux_1[(t-1)][_idx5]=0.2; u__u_0[(t-1)][_idx2]=0.1; } } } }
.text .file "kernel.hip" .globl _Z25__device_stub__divergencePPfS_S_S_S_fffiiii # -- Begin function _Z25__device_stub__divergencePPfS_S_S_S_fffiiii .p2align 4, 0x90 .type _Z25__device_stub__divergencePPfS_S_S_S_fffiiii,@function _Z25__device_stub__divergencePPfS_S_S_S_fffiiii: # @_Z25__device_stub__divergencePPfS_S_S_S_fffiiii .cfi_startproc # %bb.0: subq $216, %rsp .cfi_def_cfa_offset 224 movq %rdi, 104(%rsp) movq %rsi, 96(%rsp) movq %rdx, 88(%rsp) movq %rcx, 80(%rsp) movq %r8, 72(%rsp) movss %xmm0, 20(%rsp) movss %xmm1, 16(%rsp) movss %xmm2, 12(%rsp) movl %r9d, 8(%rsp) leaq 104(%rsp), %rax movq %rax, 112(%rsp) leaq 96(%rsp), %rax movq %rax, 120(%rsp) leaq 88(%rsp), %rax movq %rax, 128(%rsp) leaq 80(%rsp), %rax movq %rax, 136(%rsp) leaq 72(%rsp), %rax movq %rax, 144(%rsp) leaq 20(%rsp), %rax movq %rax, 152(%rsp) leaq 16(%rsp), %rax movq %rax, 160(%rsp) leaq 12(%rsp), %rax movq %rax, 168(%rsp) leaq 8(%rsp), %rax movq %rax, 176(%rsp) leaq 224(%rsp), %rax movq %rax, 184(%rsp) leaq 232(%rsp), %rax movq %rax, 192(%rsp) leaq 240(%rsp), %rax movq %rax, 200(%rsp) leaq 56(%rsp), %rdi leaq 40(%rsp), %rsi leaq 32(%rsp), %rdx leaq 24(%rsp), %rcx callq __hipPopCallConfiguration movq 56(%rsp), %rsi movl 64(%rsp), %edx movq 40(%rsp), %rcx movl 48(%rsp), %r8d leaq 112(%rsp), %r9 movl $_Z10divergencePPfS_S_S_S_fffiiii, %edi pushq 24(%rsp) .cfi_adjust_cfa_offset 8 pushq 40(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $232, %rsp .cfi_adjust_cfa_offset -232 retq .Lfunc_end0: .size _Z25__device_stub__divergencePPfS_S_S_S_fffiiii, .Lfunc_end0-_Z25__device_stub__divergencePPfS_S_S_S_fffiiii .cfi_endproc # -- End function .globl _Z25__device_stub__initializePfS_S_S_fffiiii # -- Begin function _Z25__device_stub__initializePfS_S_S_fffiiii .p2align 4, 0x90 .type _Z25__device_stub__initializePfS_S_S_fffiiii,@function _Z25__device_stub__initializePfS_S_S_fffiiii: # @_Z25__device_stub__initializePfS_S_S_fffiiii .cfi_startproc # %bb.0: subq $200, %rsp .cfi_def_cfa_offset 208 movq %rdi, 104(%rsp) movq %rsi, 96(%rsp) movq %rdx, 88(%rsp) movq %rcx, 80(%rsp) movss %xmm0, 28(%rsp) movss %xmm1, 24(%rsp) movss %xmm2, 20(%rsp) movl %r8d, 16(%rsp) movl %r9d, 12(%rsp) leaq 104(%rsp), %rax movq %rax, 112(%rsp) leaq 96(%rsp), %rax movq %rax, 120(%rsp) leaq 88(%rsp), %rax movq %rax, 128(%rsp) leaq 80(%rsp), %rax movq %rax, 136(%rsp) leaq 28(%rsp), %rax movq %rax, 144(%rsp) leaq 24(%rsp), %rax movq %rax, 152(%rsp) leaq 20(%rsp), %rax movq %rax, 160(%rsp) leaq 16(%rsp), %rax movq %rax, 168(%rsp) leaq 12(%rsp), %rax movq %rax, 176(%rsp) leaq 208(%rsp), %rax movq %rax, 184(%rsp) leaq 216(%rsp), %rax movq %rax, 192(%rsp) leaq 64(%rsp), %rdi leaq 48(%rsp), %rsi leaq 40(%rsp), %rdx leaq 32(%rsp), %rcx callq __hipPopCallConfiguration movq 64(%rsp), %rsi movl 72(%rsp), %edx movq 48(%rsp), %rcx movl 56(%rsp), %r8d leaq 112(%rsp), %r9 movl $_Z10initializePfS_S_S_fffiiii, %edi pushq 32(%rsp) .cfi_adjust_cfa_offset 8 pushq 48(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $216, %rsp .cfi_adjust_cfa_offset -216 retq .Lfunc_end1: .size _Z25__device_stub__initializePfS_S_S_fffiiii, .Lfunc_end1-_Z25__device_stub__initializePfS_S_S_fffiiii .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rbx xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z10divergencePPfS_S_S_S_fffiiii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z10initializePfS_S_S_fffiiii, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z10divergencePPfS_S_S_S_fffiiii,@object # @_Z10divergencePPfS_S_S_S_fffiiii .section .rodata,"a",@progbits .globl _Z10divergencePPfS_S_S_S_fffiiii .p2align 3, 0x0 _Z10divergencePPfS_S_S_S_fffiiii: .quad _Z25__device_stub__divergencePPfS_S_S_S_fffiiii .size _Z10divergencePPfS_S_S_S_fffiiii, 8 .type _Z10initializePfS_S_S_fffiiii,@object # @_Z10initializePfS_S_S_fffiiii .globl _Z10initializePfS_S_S_fffiiii .p2align 3, 0x0 _Z10initializePfS_S_S_fffiiii: .quad _Z25__device_stub__initializePfS_S_S_fffiiii .size _Z10initializePfS_S_S_fffiiii, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z10divergencePPfS_S_S_S_fffiiii" .size .L__unnamed_1, 33 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z10initializePfS_S_S_fffiiii" .size .L__unnamed_2, 30 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z25__device_stub__divergencePPfS_S_S_S_fffiiii .addrsig_sym _Z25__device_stub__initializePfS_S_S_fffiiii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z10divergencePPfS_S_S_S_fffiiii .addrsig_sym _Z10initializePfS_S_S_fffiiii .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_0009176b_00000000-6_kernel.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z46__device_stub__Z10divergencePPfS_S_S_S_fffiiiiPPfS_S_S_S_fffiiii .type _Z46__device_stub__Z10divergencePPfS_S_S_S_fffiiiiPPfS_S_S_S_fffiiii, @function _Z46__device_stub__Z10divergencePPfS_S_S_S_fffiiiiPPfS_S_S_S_fffiiii: .LFB2051: .cfi_startproc endbr64 subq $248, %rsp .cfi_def_cfa_offset 256 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) movq %rdx, 40(%rsp) movq %rcx, 32(%rsp) movq %r8, 24(%rsp) movss %xmm0, 20(%rsp) movss %xmm1, 16(%rsp) movss %xmm2, 12(%rsp) movl %r9d, 8(%rsp) movq %fs:40, %rax movq %rax, 232(%rsp) xorl %eax, %eax leaq 56(%rsp), %rax movq %rax, 128(%rsp) leaq 48(%rsp), %rax movq %rax, 136(%rsp) leaq 40(%rsp), %rax movq %rax, 144(%rsp) leaq 32(%rsp), %rax movq %rax, 152(%rsp) leaq 24(%rsp), %rax movq %rax, 160(%rsp) leaq 20(%rsp), %rax movq %rax, 168(%rsp) leaq 16(%rsp), %rax movq %rax, 176(%rsp) leaq 12(%rsp), %rax movq %rax, 184(%rsp) leaq 8(%rsp), %rax movq %rax, 192(%rsp) leaq 256(%rsp), %rax movq %rax, 200(%rsp) leaq 264(%rsp), %rax movq %rax, 208(%rsp) leaq 272(%rsp), %rax movq %rax, 216(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) movl $1, 88(%rsp) movl $1, 92(%rsp) movl $1, 96(%rsp) movl $1, 100(%rsp) leaq 72(%rsp), %rcx leaq 64(%rsp), %rdx leaq 92(%rsp), %rsi leaq 80(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 232(%rsp), %rax subq %fs:40, %rax jne .L8 addq $248, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 72(%rsp) .cfi_def_cfa_offset 264 pushq 72(%rsp) .cfi_def_cfa_offset 272 leaq 144(%rsp), %r9 movq 108(%rsp), %rcx movl 116(%rsp), %r8d movq 96(%rsp), %rsi movl 104(%rsp), %edx leaq _Z10divergencePPfS_S_S_S_fffiiii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 256 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z46__device_stub__Z10divergencePPfS_S_S_S_fffiiiiPPfS_S_S_S_fffiiii, .-_Z46__device_stub__Z10divergencePPfS_S_S_S_fffiiiiPPfS_S_S_S_fffiiii .globl _Z10divergencePPfS_S_S_S_fffiiii .type _Z10divergencePPfS_S_S_S_fffiiii, @function _Z10divergencePPfS_S_S_S_fffiiii: .LFB2052: .cfi_startproc endbr64 subq $16, %rsp .cfi_def_cfa_offset 24 movl 40(%rsp), %eax pushq %rax .cfi_def_cfa_offset 32 movl 40(%rsp), %eax pushq %rax .cfi_def_cfa_offset 40 movl 40(%rsp), %eax pushq %rax .cfi_def_cfa_offset 48 call _Z46__device_stub__Z10divergencePPfS_S_S_S_fffiiiiPPfS_S_S_S_fffiiii addq $40, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z10divergencePPfS_S_S_S_fffiiii, .-_Z10divergencePPfS_S_S_S_fffiiii .globl _Z43__device_stub__Z10initializePfS_S_S_fffiiiiPfS_S_S_fffiiii .type _Z43__device_stub__Z10initializePfS_S_S_fffiiiiPfS_S_S_fffiiii, @function _Z43__device_stub__Z10initializePfS_S_S_fffiiiiPfS_S_S_fffiiii: .LFB2053: .cfi_startproc endbr64 subq $232, %rsp .cfi_def_cfa_offset 240 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) movq %rdx, 40(%rsp) movq %rcx, 32(%rsp) movss %xmm0, 28(%rsp) movss %xmm1, 24(%rsp) movss %xmm2, 20(%rsp) movl %r8d, 16(%rsp) movl %r9d, 12(%rsp) movq %fs:40, %rax movq %rax, 216(%rsp) xorl %eax, %eax leaq 56(%rsp), %rax movq %rax, 128(%rsp) leaq 48(%rsp), %rax movq %rax, 136(%rsp) leaq 40(%rsp), %rax movq %rax, 144(%rsp) leaq 32(%rsp), %rax movq %rax, 152(%rsp) leaq 28(%rsp), %rax movq %rax, 160(%rsp) leaq 24(%rsp), %rax movq %rax, 168(%rsp) leaq 20(%rsp), %rax movq %rax, 176(%rsp) leaq 16(%rsp), %rax movq %rax, 184(%rsp) leaq 12(%rsp), %rax movq %rax, 192(%rsp) leaq 240(%rsp), %rax movq %rax, 200(%rsp) leaq 248(%rsp), %rax movq %rax, 208(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) movl $1, 88(%rsp) movl $1, 92(%rsp) movl $1, 96(%rsp) movl $1, 100(%rsp) leaq 72(%rsp), %rcx leaq 64(%rsp), %rdx leaq 92(%rsp), %rsi leaq 80(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L15 .L11: movq 216(%rsp), %rax subq %fs:40, %rax jne .L16 addq $232, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L15: .cfi_restore_state pushq 72(%rsp) .cfi_def_cfa_offset 248 pushq 72(%rsp) .cfi_def_cfa_offset 256 leaq 144(%rsp), %r9 movq 108(%rsp), %rcx movl 116(%rsp), %r8d movq 96(%rsp), %rsi movl 104(%rsp), %edx leaq _Z10initializePfS_S_S_fffiiii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 240 jmp .L11 .L16: call __stack_chk_fail@PLT .cfi_endproc .LFE2053: .size _Z43__device_stub__Z10initializePfS_S_S_fffiiiiPfS_S_S_fffiiii, .-_Z43__device_stub__Z10initializePfS_S_S_fffiiiiPfS_S_S_fffiiii .globl _Z10initializePfS_S_S_fffiiii .type _Z10initializePfS_S_S_fffiiii, @function _Z10initializePfS_S_S_fffiiii: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movl 24(%rsp), %eax pushq %rax .cfi_def_cfa_offset 24 movl 24(%rsp), %eax pushq %rax .cfi_def_cfa_offset 32 call _Z43__device_stub__Z10initializePfS_S_S_fffiiiiPfS_S_S_fffiiii addq $24, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _Z10initializePfS_S_S_fffiiii, .-_Z10initializePfS_S_S_fffiiii .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z10initializePfS_S_S_fffiiii" .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC1: .string "_Z10divergencePPfS_S_S_S_fffiiii" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2056: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z10initializePfS_S_S_fffiiii(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC1(%rip), %rdx movq %rdx, %rcx leaq _Z10divergencePPfS_S_S_S_fffiiii(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2056: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "kernel.hip" .globl _Z25__device_stub__divergencePPfS_S_S_S_fffiiii # -- Begin function _Z25__device_stub__divergencePPfS_S_S_S_fffiiii .p2align 4, 0x90 .type _Z25__device_stub__divergencePPfS_S_S_S_fffiiii,@function _Z25__device_stub__divergencePPfS_S_S_S_fffiiii: # @_Z25__device_stub__divergencePPfS_S_S_S_fffiiii .cfi_startproc # %bb.0: subq $216, %rsp .cfi_def_cfa_offset 224 movq %rdi, 104(%rsp) movq %rsi, 96(%rsp) movq %rdx, 88(%rsp) movq %rcx, 80(%rsp) movq %r8, 72(%rsp) movss %xmm0, 20(%rsp) movss %xmm1, 16(%rsp) movss %xmm2, 12(%rsp) movl %r9d, 8(%rsp) leaq 104(%rsp), %rax movq %rax, 112(%rsp) leaq 96(%rsp), %rax movq %rax, 120(%rsp) leaq 88(%rsp), %rax movq %rax, 128(%rsp) leaq 80(%rsp), %rax movq %rax, 136(%rsp) leaq 72(%rsp), %rax movq %rax, 144(%rsp) leaq 20(%rsp), %rax movq %rax, 152(%rsp) leaq 16(%rsp), %rax movq %rax, 160(%rsp) leaq 12(%rsp), %rax movq %rax, 168(%rsp) leaq 8(%rsp), %rax movq %rax, 176(%rsp) leaq 224(%rsp), %rax movq %rax, 184(%rsp) leaq 232(%rsp), %rax movq %rax, 192(%rsp) leaq 240(%rsp), %rax movq %rax, 200(%rsp) leaq 56(%rsp), %rdi leaq 40(%rsp), %rsi leaq 32(%rsp), %rdx leaq 24(%rsp), %rcx callq __hipPopCallConfiguration movq 56(%rsp), %rsi movl 64(%rsp), %edx movq 40(%rsp), %rcx movl 48(%rsp), %r8d leaq 112(%rsp), %r9 movl $_Z10divergencePPfS_S_S_S_fffiiii, %edi pushq 24(%rsp) .cfi_adjust_cfa_offset 8 pushq 40(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $232, %rsp .cfi_adjust_cfa_offset -232 retq .Lfunc_end0: .size _Z25__device_stub__divergencePPfS_S_S_S_fffiiii, .Lfunc_end0-_Z25__device_stub__divergencePPfS_S_S_S_fffiiii .cfi_endproc # -- End function .globl _Z25__device_stub__initializePfS_S_S_fffiiii # -- Begin function _Z25__device_stub__initializePfS_S_S_fffiiii .p2align 4, 0x90 .type _Z25__device_stub__initializePfS_S_S_fffiiii,@function _Z25__device_stub__initializePfS_S_S_fffiiii: # @_Z25__device_stub__initializePfS_S_S_fffiiii .cfi_startproc # %bb.0: subq $200, %rsp .cfi_def_cfa_offset 208 movq %rdi, 104(%rsp) movq %rsi, 96(%rsp) movq %rdx, 88(%rsp) movq %rcx, 80(%rsp) movss %xmm0, 28(%rsp) movss %xmm1, 24(%rsp) movss %xmm2, 20(%rsp) movl %r8d, 16(%rsp) movl %r9d, 12(%rsp) leaq 104(%rsp), %rax movq %rax, 112(%rsp) leaq 96(%rsp), %rax movq %rax, 120(%rsp) leaq 88(%rsp), %rax movq %rax, 128(%rsp) leaq 80(%rsp), %rax movq %rax, 136(%rsp) leaq 28(%rsp), %rax movq %rax, 144(%rsp) leaq 24(%rsp), %rax movq %rax, 152(%rsp) leaq 20(%rsp), %rax movq %rax, 160(%rsp) leaq 16(%rsp), %rax movq %rax, 168(%rsp) leaq 12(%rsp), %rax movq %rax, 176(%rsp) leaq 208(%rsp), %rax movq %rax, 184(%rsp) leaq 216(%rsp), %rax movq %rax, 192(%rsp) leaq 64(%rsp), %rdi leaq 48(%rsp), %rsi leaq 40(%rsp), %rdx leaq 32(%rsp), %rcx callq __hipPopCallConfiguration movq 64(%rsp), %rsi movl 72(%rsp), %edx movq 48(%rsp), %rcx movl 56(%rsp), %r8d leaq 112(%rsp), %r9 movl $_Z10initializePfS_S_S_fffiiii, %edi pushq 32(%rsp) .cfi_adjust_cfa_offset 8 pushq 48(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $216, %rsp .cfi_adjust_cfa_offset -216 retq .Lfunc_end1: .size _Z25__device_stub__initializePfS_S_S_fffiiii, .Lfunc_end1-_Z25__device_stub__initializePfS_S_S_fffiiii .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rbx xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z10divergencePPfS_S_S_S_fffiiii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z10initializePfS_S_S_fffiiii, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z10divergencePPfS_S_S_S_fffiiii,@object # @_Z10divergencePPfS_S_S_S_fffiiii .section .rodata,"a",@progbits .globl _Z10divergencePPfS_S_S_S_fffiiii .p2align 3, 0x0 _Z10divergencePPfS_S_S_S_fffiiii: .quad _Z25__device_stub__divergencePPfS_S_S_S_fffiiii .size _Z10divergencePPfS_S_S_S_fffiiii, 8 .type _Z10initializePfS_S_S_fffiiii,@object # @_Z10initializePfS_S_S_fffiiii .globl _Z10initializePfS_S_S_fffiiii .p2align 3, 0x0 _Z10initializePfS_S_S_fffiiii: .quad _Z25__device_stub__initializePfS_S_S_fffiiii .size _Z10initializePfS_S_S_fffiiii, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z10divergencePPfS_S_S_S_fffiiii" .size .L__unnamed_1, 33 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z10initializePfS_S_S_fffiiii" .size .L__unnamed_2, 30 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z25__device_stub__divergencePPfS_S_S_S_fffiiii .addrsig_sym _Z25__device_stub__initializePfS_S_S_fffiiii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z10divergencePPfS_S_S_S_fffiiii .addrsig_sym _Z10initializePfS_S_S_fffiiii .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include <type_traits> #ifdef _WIN32 # define EXPORT __declspec(dllexport) #else # define EXPORT #endif using tt = std::true_type; using ft = std::false_type; EXPORT int __host__ shared_cuda11_func(int x) { return x * x + std::integral_constant<int, 17>::value; }
code for sm_80
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include <type_traits> #ifdef _WIN32 # define EXPORT __declspec(dllexport) #else # define EXPORT #endif using tt = std::true_type; using ft = std::false_type; EXPORT int __host__ shared_cuda11_func(int x) { return x * x + std::integral_constant<int, 17>::value; }
.file "tmpxft_0003bd54_00000000-6_shared.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2030: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2030: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z18shared_cuda11_funci .type _Z18shared_cuda11_funci, @function _Z18shared_cuda11_funci: .LFB2027: .cfi_startproc endbr64 imull %edi, %edi leal 17(%rdi), %eax ret .cfi_endproc .LFE2027: .size _Z18shared_cuda11_funci, .-_Z18shared_cuda11_funci .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2053: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2053: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include <type_traits> #ifdef _WIN32 # define EXPORT __declspec(dllexport) #else # define EXPORT #endif using tt = std::true_type; using ft = std::false_type; EXPORT int __host__ shared_cuda11_func(int x) { return x * x + std::integral_constant<int, 17>::value; }
#include <hip/hip_runtime.h> #include <type_traits> #ifdef _WIN32 # define EXPORT __declspec(dllexport) #else # define EXPORT #endif using tt = std::true_type; using ft = std::false_type; EXPORT int __host__ shared_cuda11_func(int x) { return x * x + std::integral_constant<int, 17>::value; }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <hip/hip_runtime.h> #include <type_traits> #ifdef _WIN32 # define EXPORT __declspec(dllexport) #else # define EXPORT #endif using tt = std::true_type; using ft = std::false_type; EXPORT int __host__ shared_cuda11_func(int x) { return x * x + std::integral_constant<int, 17>::value; }
.text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .amdgpu_metadata --- amdhsa.kernels: [] amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <hip/hip_runtime.h> #include <type_traits> #ifdef _WIN32 # define EXPORT __declspec(dllexport) #else # define EXPORT #endif using tt = std::true_type; using ft = std::false_type; EXPORT int __host__ shared_cuda11_func(int x) { return x * x + std::integral_constant<int, 17>::value; }
.text .file "shared.hip" .globl _Z18shared_cuda11_funci # -- Begin function _Z18shared_cuda11_funci .p2align 4, 0x90 .type _Z18shared_cuda11_funci,@function _Z18shared_cuda11_funci: # @_Z18shared_cuda11_funci .cfi_startproc # %bb.0: # kill: def $edi killed $edi def $rdi imull %edi, %edi leal 17(%rdi), %eax retq .Lfunc_end0: .size _Z18shared_cuda11_funci, .Lfunc_end0-_Z18shared_cuda11_funci .cfi_endproc # -- End function .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80
.text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .amdgpu_metadata --- amdhsa.kernels: [] amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_0003bd54_00000000-6_shared.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2030: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2030: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z18shared_cuda11_funci .type _Z18shared_cuda11_funci, @function _Z18shared_cuda11_funci: .LFB2027: .cfi_startproc endbr64 imull %edi, %edi leal 17(%rdi), %eax ret .cfi_endproc .LFE2027: .size _Z18shared_cuda11_funci, .-_Z18shared_cuda11_funci .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2053: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2053: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "shared.hip" .globl _Z18shared_cuda11_funci # -- Begin function _Z18shared_cuda11_funci .p2align 4, 0x90 .type _Z18shared_cuda11_funci,@function _Z18shared_cuda11_funci: # @_Z18shared_cuda11_funci .cfi_startproc # %bb.0: # kill: def $edi killed $edi def $rdi imull %edi, %edi leal 17(%rdi), %eax retq .Lfunc_end0: .size _Z18shared_cuda11_funci, .Lfunc_end0-_Z18shared_cuda11_funci .cfi_endproc # -- End function .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include "includes.h" extern "C" __global__ void add(int n, float *a, float *sum) { int i = threadIdx.x + blockDim.x * blockIdx.x; if (i<n) { for (int j = 0; j < n; j++) { sum[i] = sum[i] + a[i*n + j]; } } }
code for sm_80 Function : add .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */ /* 0x000e220000002500 */ /*0020*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */ /* 0x000fc60000000f00 */ /*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */ /* 0x000e220000002100 */ /*0040*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */ /* 0x000fe20003f06270 */ /*0050*/ IMAD R7, R7, c[0x0][0x0], R0 ; /* 0x0000000007077a24 */ /* 0x001fca00078e0200 */ /*0060*/ ISETP.GE.OR P0, PT, R7, c[0x0][0x160], !P0 ; /* 0x0000580007007a0c */ /* 0x000fda0004706670 */ /*0070*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*0080*/ IADD3 R0, R2, -0x1, RZ ; /* 0xffffffff02007810 */ /* 0x000fe20007ffe0ff */ /*0090*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */ /* 0x000fe200078e00ff */ /*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fe20000000a00 */ /*00b0*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */ /* 0x000fe200000001ff */ /*00c0*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */ /* 0x000fe40003f06070 */ /*00d0*/ LOP3.LUT R0, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302007812 */ /* 0x000fe200078ec0ff */ /*00e0*/ IMAD.WIDE R2, R7, R6, c[0x0][0x170] ; /* 0x00005c0007027625 */ /* 0x000fd400078e0206 */ /*00f0*/ @!P0 BRA 0x8a0 ; /* 0x000007a000008947 */ /* 0x000fea0003800000 */ /*0100*/ IADD3 R9, -R0, c[0x0][0x160], RZ ; /* 0x0000580000097a10 */ /* 0x000fe20007ffe1ff */ /*0110*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */ /* 0x000162000c1e1900 */ /*0120*/ IMAD R5, R7, c[0x0][0x160], RZ ; /* 0x0000580007057a24 */ /* 0x000fe200078e02ff */ /*0130*/ MOV R8, RZ ; /* 0x000000ff00087202 */ /* 0x000fe40000000f00 */ /*0140*/ ISETP.GT.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */ /* 0x000fe20003f04270 */ /*0150*/ IMAD.WIDE R4, R5, R6, c[0x0][0x168] ; /* 0x00005a0005047625 */ /* 0x000fd800078e0206 */ /*0160*/ @!P0 BRA 0x760 ; /* 0x000005f000008947 */ /* 0x001fea0003800000 */ /*0170*/ ISETP.GT.AND P1, PT, R9, 0xc, PT ; /* 0x0000000c0900780c */ /* 0x000fe40003f24270 */ /*0180*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */ /* 0x000fd60003f0f070 */ /*0190*/ @!P1 BRA 0x530 ; /* 0x0000039000009947 */ /* 0x000fea0003800000 */ /*01a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe40003f0e170 */ /*01b0*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */ /* 0x000ea4000c1e1900 */ /*01c0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */ /* 0x02cfca0000000000 */ /*01d0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */ /* 0x0001e8000c101904 */ /*01e0*/ LDG.E R10, [R4.64+0x4] ; /* 0x00000404040a7981 */ /* 0x000ea4000c1e1900 */ /*01f0*/ FADD R13, R11, R10 ; /* 0x0000000a0b0d7221 */ /* 0x004fca0000000000 */ /*0200*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */ /* 0x0003e8000c101904 */ /*0210*/ LDG.E R10, [R4.64+0x8] ; /* 0x00000804040a7981 */ /* 0x000ea4000c1e1900 */ /*0220*/ FADD R15, R13, R10 ; /* 0x0000000a0d0f7221 */ /* 0x004fca0000000000 */ /*0230*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */ /* 0x0005e8000c101904 */ /*0240*/ LDG.E R10, [R4.64+0xc] ; /* 0x00000c04040a7981 */ /* 0x000ee4000c1e1900 */ /*0250*/ FADD R17, R15, R10 ; /* 0x0000000a0f117221 */ /* 0x008fca0000000000 */ /*0260*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */ /* 0x0007e8000c101904 */ /*0270*/ LDG.E R10, [R4.64+0x10] ; /* 0x00001004040a7981 */ /* 0x000e24000c1e1900 */ /*0280*/ FADD R11, R17, R10 ; /* 0x0000000a110b7221 */ /* 0x001fca0000000000 */ /*0290*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */ /* 0x0001e8000c101904 */ /*02a0*/ LDG.E R10, [R4.64+0x14] ; /* 0x00001404040a7981 */ /* 0x000e64000c1e1900 */ /*02b0*/ FADD R13, R11, R10 ; /* 0x0000000a0b0d7221 */ /* 0x002fca0000000000 */ /*02c0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */ /* 0x0003e8000c101904 */ /*02d0*/ LDG.E R10, [R4.64+0x18] ; /* 0x00001804040a7981 */ /* 0x000ea4000c1e1900 */ /*02e0*/ FADD R15, R13, R10 ; /* 0x0000000a0d0f7221 */ /* 0x004fca0000000000 */ /*02f0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */ /* 0x0005e8000c101904 */ /*0300*/ LDG.E R10, [R4.64+0x1c] ; /* 0x00001c04040a7981 */ /* 0x000ee4000c1e1900 */ /*0310*/ FADD R17, R15, R10 ; /* 0x0000000a0f117221 */ /* 0x008fca0000000000 */ /*0320*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */ /* 0x0007e8000c101904 */ /*0330*/ LDG.E R10, [R4.64+0x20] ; /* 0x00002004040a7981 */ /* 0x000e24000c1e1900 */ /*0340*/ FADD R11, R17, R10 ; /* 0x0000000a110b7221 */ /* 0x001fca0000000000 */ /*0350*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */ /* 0x000fe8000c101904 */ /*0360*/ LDG.E R10, [R4.64+0x24] ; /* 0x00002404040a7981 */ /* 0x000e64000c1e1900 */ /*0370*/ FADD R13, R11, R10 ; /* 0x0000000a0b0d7221 */ /* 0x002fca0000000000 */ /*0380*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */ /* 0x0001e8000c101904 */ /*0390*/ LDG.E R10, [R4.64+0x28] ; /* 0x00002804040a7981 */ /* 0x000ea4000c1e1900 */ /*03a0*/ FADD R15, R13, R10 ; /* 0x0000000a0d0f7221 */ /* 0x004fca0000000000 */ /*03b0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */ /* 0x0003e8000c101904 */ /*03c0*/ LDG.E R10, [R4.64+0x2c] ; /* 0x00002c04040a7981 */ /* 0x000ee4000c1e1900 */ /*03d0*/ FADD R17, R15, R10 ; /* 0x0000000a0f117221 */ /* 0x008fca0000000000 */ /*03e0*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */ /* 0x0005e8000c101904 */ /*03f0*/ LDG.E R10, [R4.64+0x30] ; /* 0x00003004040a7981 */ /* 0x000ee4000c1e1900 */ /*0400*/ FADD R19, R17, R10 ; /* 0x0000000a11137221 */ /* 0x008fca0000000000 */ /*0410*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */ /* 0x0007e8000c101904 */ /*0420*/ LDG.E R10, [R4.64+0x34] ; /* 0x00003404040a7981 */ /* 0x000e24000c1e1900 */ /*0430*/ FADD R13, R19, R10 ; /* 0x0000000a130d7221 */ /* 0x001fca0000000000 */ /*0440*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */ /* 0x0007e8000c101904 */ /*0450*/ LDG.E R10, [R4.64+0x38] ; /* 0x00003804040a7981 */ /* 0x000e62000c1e1900 */ /*0460*/ IADD3 R9, R9, -0x10, RZ ; /* 0xfffffff009097810 */ /* 0x000fe20007ffe0ff */ /*0470*/ FADD R15, R13, R10 ; /* 0x0000000a0d0f7221 */ /* 0x002fca0000000000 */ /*0480*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */ /* 0x0007e8000c101904 */ /*0490*/ LDG.E R10, [R4.64+0x3c] ; /* 0x00003c04040a7981 */ /* 0x000f22000c1e1900 */ /*04a0*/ ISETP.GT.AND P1, PT, R9, 0xc, PT ; /* 0x0000000c0900780c */ /* 0x000fe40003f24270 */ /*04b0*/ IADD3 R8, R8, 0x10, RZ ; /* 0x0000001008087810 */ /* 0x000fe20007ffe0ff */ /*04c0*/ FADD R11, R15, R10 ; /* 0x0000000a0f0b7221 */ /* 0x010fe20000000000 */ /*04d0*/ IADD3 R10, P2, R4, 0x40, RZ ; /* 0x00000040040a7810 */ /* 0x000fc80007f5e0ff */ /*04e0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */ /* 0x0007e2000c101904 */ /*04f0*/ IMAD.X R17, RZ, RZ, R5, P2 ; /* 0x000000ffff117224 */ /* 0x004fe200010e0605 */ /*0500*/ MOV R4, R10 ; /* 0x0000000a00047202 */ /* 0x000fc80000000f00 */ /*0510*/ MOV R5, R17 ; /* 0x0000001100057202 */ /* 0x000fe20000000f00 */ /*0520*/ @P1 BRA 0x1b0 ; /* 0xfffffc8000001947 */ /* 0x000fea000383ffff */ /*0530*/ ISETP.GT.AND P1, PT, R9, 0x4, PT ; /* 0x000000040900780c */ /* 0x000fda0003f24270 */ /*0540*/ @!P1 BRA 0x740 ; /* 0x000001f000009947 */ /* 0x000fea0003800000 */ /*0550*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */ /* 0x000ea4000c1e1900 */ /*0560*/ FADD R11, R11, R10 ; /* 0x0000000a0b0b7221 */ /* 0x02cfca0000000000 */ /*0570*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */ /* 0x000fe8000c101904 */ /*0580*/ LDG.E R10, [R4.64+0x4] ; /* 0x00000404040a7981 */ /* 0x000ea4000c1e1900 */ /*0590*/ FADD R13, R11, R10 ; /* 0x0000000a0b0d7221 */ /* 0x004fca0000000000 */ /*05a0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */ /* 0x0001e8000c101904 */ /*05b0*/ LDG.E R10, [R4.64+0x8] ; /* 0x00000804040a7981 */ /* 0x000ea4000c1e1900 */ /*05c0*/ FADD R15, R13, R10 ; /* 0x0000000a0d0f7221 */ /* 0x004fca0000000000 */ /*05d0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */ /* 0x0003e8000c101904 */ /*05e0*/ LDG.E R10, [R4.64+0xc] ; /* 0x00000c04040a7981 */ /* 0x000ea4000c1e1900 */ /*05f0*/ FADD R17, R15, R10 ; /* 0x0000000a0f117221 */ /* 0x004fca0000000000 */ /*0600*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */ /* 0x0005e8000c101904 */ /*0610*/ LDG.E R10, [R4.64+0x10] ; /* 0x00001004040a7981 */ /* 0x000ee4000c1e1900 */ /*0620*/ FADD R19, R17, R10 ; /* 0x0000000a11137221 */ /* 0x008fca0000000000 */ /*0630*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */ /* 0x0007e8000c101904 */ /*0640*/ LDG.E R10, [R4.64+0x14] ; /* 0x00001404040a7981 */ /* 0x000e24000c1e1900 */ /*0650*/ FADD R13, R19, R10 ; /* 0x0000000a130d7221 */ /* 0x001fca0000000000 */ /*0660*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */ /* 0x0007e8000c101904 */ /*0670*/ LDG.E R10, [R4.64+0x18] ; /* 0x00001804040a7981 */ /* 0x000e64000c1e1900 */ /*0680*/ FADD R15, R13, R10 ; /* 0x0000000a0d0f7221 */ /* 0x002fca0000000000 */ /*0690*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */ /* 0x0007e8000c101904 */ /*06a0*/ LDG.E R10, [R4.64+0x1c] ; /* 0x00001c04040a7981 */ /* 0x000f22000c1e1900 */ /*06b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe40003f0e170 */ /*06c0*/ IADD3 R8, R8, 0x8, RZ ; /* 0x0000000808087810 */ /* 0x000fe40007ffe0ff */ /*06d0*/ IADD3 R9, R9, -0x8, RZ ; /* 0xfffffff809097810 */ /* 0x000fe20007ffe0ff */ /*06e0*/ FADD R11, R15, R10 ; /* 0x0000000a0f0b7221 */ /* 0x010fe20000000000 */ /*06f0*/ IADD3 R10, P1, R4, 0x20, RZ ; /* 0x00000020040a7810 */ /* 0x000fc80007f3e0ff */ /*0700*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */ /* 0x0007e2000c101904 */ /*0710*/ IMAD.X R17, RZ, RZ, R5, P1 ; /* 0x000000ffff117224 */ /* 0x004fe200008e0605 */ /*0720*/ MOV R4, R10 ; /* 0x0000000a00047202 */ /* 0x000fc80000000f00 */ /*0730*/ MOV R5, R17 ; /* 0x0000001100057202 */ /* 0x000fe40000000f00 */ /*0740*/ ISETP.NE.OR P0, PT, R9, RZ, P0 ; /* 0x000000ff0900720c */ /* 0x000fda0000705670 */ /*0750*/ @!P0 BRA 0x8a0 ; /* 0x0000014000008947 */ /* 0x000fea0003800000 */ /*0760*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */ /* 0x000ea4000c1e1900 */ /*0770*/ FADD R13, R10, R11 ; /* 0x0000000b0a0d7221 */ /* 0x02cfca0000000000 */ /*0780*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */ /* 0x0001e8000c101904 */ /*0790*/ LDG.E R10, [R4.64+0x4] ; /* 0x00000404040a7981 */ /* 0x000ea4000c1e1900 */ /*07a0*/ FADD R15, R13, R10 ; /* 0x0000000a0d0f7221 */ /* 0x004fca0000000000 */ /*07b0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */ /* 0x0003e8000c101904 */ /*07c0*/ LDG.E R10, [R4.64+0x8] ; /* 0x00000804040a7981 */ /* 0x000ea2000c1e1900 */ /*07d0*/ IADD3 R9, R9, -0x4, RZ ; /* 0xfffffffc09097810 */ /* 0x000fe20007ffe0ff */ /*07e0*/ FADD R17, R15, R10 ; /* 0x0000000a0f117221 */ /* 0x004fca0000000000 */ /*07f0*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */ /* 0x0003e8000c101904 */ /*0800*/ LDG.E R10, [R4.64+0xc] ; /* 0x00000c04040a7981 */ /* 0x000ea2000c1e1900 */ /*0810*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */ /* 0x000fe40003f05270 */ /*0820*/ IADD3 R8, R8, 0x4, RZ ; /* 0x0000000408087810 */ /* 0x000fe20007ffe0ff */ /*0830*/ FADD R11, R17, R10 ; /* 0x0000000a110b7221 */ /* 0x004fe20000000000 */ /*0840*/ IADD3 R10, P1, R4, 0x10, RZ ; /* 0x00000010040a7810 */ /* 0x000fc80007f3e0ff */ /*0850*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */ /* 0x0003e2000c101904 */ /*0860*/ IMAD.X R13, RZ, RZ, R5, P1 ; /* 0x000000ffff0d7224 */ /* 0x001fe200008e0605 */ /*0870*/ MOV R4, R10 ; /* 0x0000000a00047202 */ /* 0x000fc80000000f00 */ /*0880*/ MOV R5, R13 ; /* 0x0000000d00057202 */ /* 0x000fe20000000f00 */ /*0890*/ @P0 BRA 0x760 ; /* 0xfffffec000000947 */ /* 0x002fea000383ffff */ /*08a0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */ /* 0x000fda0003f05270 */ /*08b0*/ @!P0 EXIT ; /* 0x000000000000894d */ /* 0x000fea0003800000 */ /*08c0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */ /* 0x000162000c1e1900 */ /*08d0*/ IMAD R7, R7, c[0x0][0x160], R8 ; /* 0x0000580007077a24 */ /* 0x000fc800078e0208 */ /*08e0*/ IMAD.WIDE R6, R7, R6, c[0x0][0x168] ; /* 0x00005a0007067625 */ /* 0x000fc800078e0206 */ /*08f0*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */ /* 0x000fe200078e0006 */ /*0900*/ MOV R5, R7 ; /* 0x0000000700057202 */ /* 0x000fca0000000f00 */ /*0910*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */ /* 0x000ea2000c1e1900 */ /*0920*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */ /* 0x000fe40007ffe0ff */ /*0930*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */ /* 0x000fe40007f3e0ff */ /*0940*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */ /* 0x000fe40003f05270 */ /*0950*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */ /* 0x000fe20000ffe4ff */ /*0960*/ FADD R9, R4, R9 ; /* 0x0000000904097221 */ /* 0x026fca0000000000 */ /*0970*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */ /* 0x0003ea000c101904 */ /*0980*/ @P0 BRA 0x8f0 ; /* 0xffffff6000000947 */ /* 0x000fea000383ffff */ /*0990*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*09a0*/ BRA 0x9a0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*09b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*09c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*09d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*09e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*09f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0a00*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0a10*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0a20*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0a30*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0a40*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0a50*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0a60*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0a70*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include "includes.h" extern "C" __global__ void add(int n, float *a, float *sum) { int i = threadIdx.x + blockDim.x * blockIdx.x; if (i<n) { for (int j = 0; j < n; j++) { sum[i] = sum[i] + a[i*n + j]; } } }
.file "tmpxft_00001bf6_00000000-6_add.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z25__device_stub__Z3addiPfS_iPfS_ .type _Z25__device_stub__Z3addiPfS_iPfS_, @function _Z25__device_stub__Z3addiPfS_iPfS_: .LFB2051: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movl %edi, 28(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 28(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 120(%rsp), %rax subq %fs:40, %rax jne .L8 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq add(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z25__device_stub__Z3addiPfS_iPfS_, .-_Z25__device_stub__Z3addiPfS_iPfS_ .globl add .type add, @function add: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z25__device_stub__Z3addiPfS_iPfS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size add, .-add .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "add" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq add(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include "includes.h" extern "C" __global__ void add(int n, float *a, float *sum) { int i = threadIdx.x + blockDim.x * blockIdx.x; if (i<n) { for (int j = 0; j < n; j++) { sum[i] = sum[i] + a[i*n + j]; } } }
#include <hip/hip_runtime.h> #include "includes.h" extern "C" __global__ void add(int n, float *a, float *sum) { int i = threadIdx.x + blockDim.x * blockIdx.x; if (i<n) { for (int j = 0; j < n; j++) { sum[i] = sum[i] + a[i*n + j]; } } }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <hip/hip_runtime.h> #include "includes.h" extern "C" __global__ void add(int n, float *a, float *sum) { int i = threadIdx.x + blockDim.x * blockIdx.x; if (i<n) { for (int j = 0; j < n; j++) { sum[i] = sum[i] + a[i*n + j]; } } }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected add .globl add .p2align 8 .type add,@function add: s_clause 0x1 s_load_b32 s3, s[0:1], 0x24 s_load_b32 s2, s[0:1], 0x0 s_waitcnt lgkmcnt(0) s_and_b32 s3, s3, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[2:3], null, s15, s3, v[0:1] s_mov_b32 s3, exec_lo v_max_i32_e32 v0, 0, v2 s_delay_alu instid0(VALU_DEP_1) v_cmpx_gt_i32_e64 s2, v0 s_cbranch_execz .LBB0_3 s_load_b128 s[4:7], s[0:1], 0x8 v_ashrrev_i32_e32 v3, 31, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[2:3] v_mul_lo_u32 v2, v2, s2 v_ashrrev_i32_e32 v3, 31, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_lshlrev_b64 v[2:3], 2, v[2:3] s_waitcnt lgkmcnt(0) v_add_co_u32 v0, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo s_delay_alu instid0(VALU_DEP_3) v_add_co_u32 v2, vcc_lo, s4, v2 global_load_b32 v4, v[0:1], off v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo .LBB0_2: global_load_b32 v5, v[2:3], off v_add_co_u32 v2, vcc_lo, v2, 4 v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo s_add_i32 s2, s2, -1 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_lg_u32 s2, 0 s_waitcnt vmcnt(0) v_add_f32_e32 v4, v4, v5 global_store_b32 v[0:1], v4, off s_cbranch_scc1 .LBB0_2 .LBB0_3: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel add .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 6 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size add, .Lfunc_end0-add .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .offset: 0 .size: 4 .value_kind: by_value - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: add .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: add.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 6 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <hip/hip_runtime.h> #include "includes.h" extern "C" __global__ void add(int n, float *a, float *sum) { int i = threadIdx.x + blockDim.x * blockIdx.x; if (i<n) { for (int j = 0; j < n; j++) { sum[i] = sum[i] + a[i*n + j]; } } }
.text .file "add.hip" .globl __device_stub__add # -- Begin function __device_stub__add .p2align 4, 0x90 .type __device_stub__add,@function __device_stub__add: # @__device_stub__add .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movl %edi, 12(%rsp) movq %rsi, 72(%rsp) movq %rdx, 64(%rsp) leaq 12(%rsp), %rax movq %rax, 80(%rsp) leaq 72(%rsp), %rax movq %rax, 88(%rsp) leaq 64(%rsp), %rax movq %rax, 96(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $add, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end0: .size __device_stub__add, .Lfunc_end0-__device_stub__add .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $add, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type add,@object # @add .section .rodata,"a",@progbits .globl add .p2align 3, 0x0 add: .quad __device_stub__add .size add, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "add" .size .L__unnamed_1, 4 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __device_stub__add .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym add .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : add .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */ /* 0x000e220000002500 */ /*0020*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */ /* 0x000fc60000000f00 */ /*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */ /* 0x000e220000002100 */ /*0040*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */ /* 0x000fe20003f06270 */ /*0050*/ IMAD R7, R7, c[0x0][0x0], R0 ; /* 0x0000000007077a24 */ /* 0x001fca00078e0200 */ /*0060*/ ISETP.GE.OR P0, PT, R7, c[0x0][0x160], !P0 ; /* 0x0000580007007a0c */ /* 0x000fda0004706670 */ /*0070*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*0080*/ IADD3 R0, R2, -0x1, RZ ; /* 0xffffffff02007810 */ /* 0x000fe20007ffe0ff */ /*0090*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */ /* 0x000fe200078e00ff */ /*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fe20000000a00 */ /*00b0*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */ /* 0x000fe200000001ff */ /*00c0*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */ /* 0x000fe40003f06070 */ /*00d0*/ LOP3.LUT R0, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302007812 */ /* 0x000fe200078ec0ff */ /*00e0*/ IMAD.WIDE R2, R7, R6, c[0x0][0x170] ; /* 0x00005c0007027625 */ /* 0x000fd400078e0206 */ /*00f0*/ @!P0 BRA 0x8a0 ; /* 0x000007a000008947 */ /* 0x000fea0003800000 */ /*0100*/ IADD3 R9, -R0, c[0x0][0x160], RZ ; /* 0x0000580000097a10 */ /* 0x000fe20007ffe1ff */ /*0110*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */ /* 0x000162000c1e1900 */ /*0120*/ IMAD R5, R7, c[0x0][0x160], RZ ; /* 0x0000580007057a24 */ /* 0x000fe200078e02ff */ /*0130*/ MOV R8, RZ ; /* 0x000000ff00087202 */ /* 0x000fe40000000f00 */ /*0140*/ ISETP.GT.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */ /* 0x000fe20003f04270 */ /*0150*/ IMAD.WIDE R4, R5, R6, c[0x0][0x168] ; /* 0x00005a0005047625 */ /* 0x000fd800078e0206 */ /*0160*/ @!P0 BRA 0x760 ; /* 0x000005f000008947 */ /* 0x001fea0003800000 */ /*0170*/ ISETP.GT.AND P1, PT, R9, 0xc, PT ; /* 0x0000000c0900780c */ /* 0x000fe40003f24270 */ /*0180*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */ /* 0x000fd60003f0f070 */ /*0190*/ @!P1 BRA 0x530 ; /* 0x0000039000009947 */ /* 0x000fea0003800000 */ /*01a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe40003f0e170 */ /*01b0*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */ /* 0x000ea4000c1e1900 */ /*01c0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */ /* 0x02cfca0000000000 */ /*01d0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */ /* 0x0001e8000c101904 */ /*01e0*/ LDG.E R10, [R4.64+0x4] ; /* 0x00000404040a7981 */ /* 0x000ea4000c1e1900 */ /*01f0*/ FADD R13, R11, R10 ; /* 0x0000000a0b0d7221 */ /* 0x004fca0000000000 */ /*0200*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */ /* 0x0003e8000c101904 */ /*0210*/ LDG.E R10, [R4.64+0x8] ; /* 0x00000804040a7981 */ /* 0x000ea4000c1e1900 */ /*0220*/ FADD R15, R13, R10 ; /* 0x0000000a0d0f7221 */ /* 0x004fca0000000000 */ /*0230*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */ /* 0x0005e8000c101904 */ /*0240*/ LDG.E R10, [R4.64+0xc] ; /* 0x00000c04040a7981 */ /* 0x000ee4000c1e1900 */ /*0250*/ FADD R17, R15, R10 ; /* 0x0000000a0f117221 */ /* 0x008fca0000000000 */ /*0260*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */ /* 0x0007e8000c101904 */ /*0270*/ LDG.E R10, [R4.64+0x10] ; /* 0x00001004040a7981 */ /* 0x000e24000c1e1900 */ /*0280*/ FADD R11, R17, R10 ; /* 0x0000000a110b7221 */ /* 0x001fca0000000000 */ /*0290*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */ /* 0x0001e8000c101904 */ /*02a0*/ LDG.E R10, [R4.64+0x14] ; /* 0x00001404040a7981 */ /* 0x000e64000c1e1900 */ /*02b0*/ FADD R13, R11, R10 ; /* 0x0000000a0b0d7221 */ /* 0x002fca0000000000 */ /*02c0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */ /* 0x0003e8000c101904 */ /*02d0*/ LDG.E R10, [R4.64+0x18] ; /* 0x00001804040a7981 */ /* 0x000ea4000c1e1900 */ /*02e0*/ FADD R15, R13, R10 ; /* 0x0000000a0d0f7221 */ /* 0x004fca0000000000 */ /*02f0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */ /* 0x0005e8000c101904 */ /*0300*/ LDG.E R10, [R4.64+0x1c] ; /* 0x00001c04040a7981 */ /* 0x000ee4000c1e1900 */ /*0310*/ FADD R17, R15, R10 ; /* 0x0000000a0f117221 */ /* 0x008fca0000000000 */ /*0320*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */ /* 0x0007e8000c101904 */ /*0330*/ LDG.E R10, [R4.64+0x20] ; /* 0x00002004040a7981 */ /* 0x000e24000c1e1900 */ /*0340*/ FADD R11, R17, R10 ; /* 0x0000000a110b7221 */ /* 0x001fca0000000000 */ /*0350*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */ /* 0x000fe8000c101904 */ /*0360*/ LDG.E R10, [R4.64+0x24] ; /* 0x00002404040a7981 */ /* 0x000e64000c1e1900 */ /*0370*/ FADD R13, R11, R10 ; /* 0x0000000a0b0d7221 */ /* 0x002fca0000000000 */ /*0380*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */ /* 0x0001e8000c101904 */ /*0390*/ LDG.E R10, [R4.64+0x28] ; /* 0x00002804040a7981 */ /* 0x000ea4000c1e1900 */ /*03a0*/ FADD R15, R13, R10 ; /* 0x0000000a0d0f7221 */ /* 0x004fca0000000000 */ /*03b0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */ /* 0x0003e8000c101904 */ /*03c0*/ LDG.E R10, [R4.64+0x2c] ; /* 0x00002c04040a7981 */ /* 0x000ee4000c1e1900 */ /*03d0*/ FADD R17, R15, R10 ; /* 0x0000000a0f117221 */ /* 0x008fca0000000000 */ /*03e0*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */ /* 0x0005e8000c101904 */ /*03f0*/ LDG.E R10, [R4.64+0x30] ; /* 0x00003004040a7981 */ /* 0x000ee4000c1e1900 */ /*0400*/ FADD R19, R17, R10 ; /* 0x0000000a11137221 */ /* 0x008fca0000000000 */ /*0410*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */ /* 0x0007e8000c101904 */ /*0420*/ LDG.E R10, [R4.64+0x34] ; /* 0x00003404040a7981 */ /* 0x000e24000c1e1900 */ /*0430*/ FADD R13, R19, R10 ; /* 0x0000000a130d7221 */ /* 0x001fca0000000000 */ /*0440*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */ /* 0x0007e8000c101904 */ /*0450*/ LDG.E R10, [R4.64+0x38] ; /* 0x00003804040a7981 */ /* 0x000e62000c1e1900 */ /*0460*/ IADD3 R9, R9, -0x10, RZ ; /* 0xfffffff009097810 */ /* 0x000fe20007ffe0ff */ /*0470*/ FADD R15, R13, R10 ; /* 0x0000000a0d0f7221 */ /* 0x002fca0000000000 */ /*0480*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */ /* 0x0007e8000c101904 */ /*0490*/ LDG.E R10, [R4.64+0x3c] ; /* 0x00003c04040a7981 */ /* 0x000f22000c1e1900 */ /*04a0*/ ISETP.GT.AND P1, PT, R9, 0xc, PT ; /* 0x0000000c0900780c */ /* 0x000fe40003f24270 */ /*04b0*/ IADD3 R8, R8, 0x10, RZ ; /* 0x0000001008087810 */ /* 0x000fe20007ffe0ff */ /*04c0*/ FADD R11, R15, R10 ; /* 0x0000000a0f0b7221 */ /* 0x010fe20000000000 */ /*04d0*/ IADD3 R10, P2, R4, 0x40, RZ ; /* 0x00000040040a7810 */ /* 0x000fc80007f5e0ff */ /*04e0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */ /* 0x0007e2000c101904 */ /*04f0*/ IMAD.X R17, RZ, RZ, R5, P2 ; /* 0x000000ffff117224 */ /* 0x004fe200010e0605 */ /*0500*/ MOV R4, R10 ; /* 0x0000000a00047202 */ /* 0x000fc80000000f00 */ /*0510*/ MOV R5, R17 ; /* 0x0000001100057202 */ /* 0x000fe20000000f00 */ /*0520*/ @P1 BRA 0x1b0 ; /* 0xfffffc8000001947 */ /* 0x000fea000383ffff */ /*0530*/ ISETP.GT.AND P1, PT, R9, 0x4, PT ; /* 0x000000040900780c */ /* 0x000fda0003f24270 */ /*0540*/ @!P1 BRA 0x740 ; /* 0x000001f000009947 */ /* 0x000fea0003800000 */ /*0550*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */ /* 0x000ea4000c1e1900 */ /*0560*/ FADD R11, R11, R10 ; /* 0x0000000a0b0b7221 */ /* 0x02cfca0000000000 */ /*0570*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */ /* 0x000fe8000c101904 */ /*0580*/ LDG.E R10, [R4.64+0x4] ; /* 0x00000404040a7981 */ /* 0x000ea4000c1e1900 */ /*0590*/ FADD R13, R11, R10 ; /* 0x0000000a0b0d7221 */ /* 0x004fca0000000000 */ /*05a0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */ /* 0x0001e8000c101904 */ /*05b0*/ LDG.E R10, [R4.64+0x8] ; /* 0x00000804040a7981 */ /* 0x000ea4000c1e1900 */ /*05c0*/ FADD R15, R13, R10 ; /* 0x0000000a0d0f7221 */ /* 0x004fca0000000000 */ /*05d0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */ /* 0x0003e8000c101904 */ /*05e0*/ LDG.E R10, [R4.64+0xc] ; /* 0x00000c04040a7981 */ /* 0x000ea4000c1e1900 */ /*05f0*/ FADD R17, R15, R10 ; /* 0x0000000a0f117221 */ /* 0x004fca0000000000 */ /*0600*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */ /* 0x0005e8000c101904 */ /*0610*/ LDG.E R10, [R4.64+0x10] ; /* 0x00001004040a7981 */ /* 0x000ee4000c1e1900 */ /*0620*/ FADD R19, R17, R10 ; /* 0x0000000a11137221 */ /* 0x008fca0000000000 */ /*0630*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */ /* 0x0007e8000c101904 */ /*0640*/ LDG.E R10, [R4.64+0x14] ; /* 0x00001404040a7981 */ /* 0x000e24000c1e1900 */ /*0650*/ FADD R13, R19, R10 ; /* 0x0000000a130d7221 */ /* 0x001fca0000000000 */ /*0660*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */ /* 0x0007e8000c101904 */ /*0670*/ LDG.E R10, [R4.64+0x18] ; /* 0x00001804040a7981 */ /* 0x000e64000c1e1900 */ /*0680*/ FADD R15, R13, R10 ; /* 0x0000000a0d0f7221 */ /* 0x002fca0000000000 */ /*0690*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */ /* 0x0007e8000c101904 */ /*06a0*/ LDG.E R10, [R4.64+0x1c] ; /* 0x00001c04040a7981 */ /* 0x000f22000c1e1900 */ /*06b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe40003f0e170 */ /*06c0*/ IADD3 R8, R8, 0x8, RZ ; /* 0x0000000808087810 */ /* 0x000fe40007ffe0ff */ /*06d0*/ IADD3 R9, R9, -0x8, RZ ; /* 0xfffffff809097810 */ /* 0x000fe20007ffe0ff */ /*06e0*/ FADD R11, R15, R10 ; /* 0x0000000a0f0b7221 */ /* 0x010fe20000000000 */ /*06f0*/ IADD3 R10, P1, R4, 0x20, RZ ; /* 0x00000020040a7810 */ /* 0x000fc80007f3e0ff */ /*0700*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */ /* 0x0007e2000c101904 */ /*0710*/ IMAD.X R17, RZ, RZ, R5, P1 ; /* 0x000000ffff117224 */ /* 0x004fe200008e0605 */ /*0720*/ MOV R4, R10 ; /* 0x0000000a00047202 */ /* 0x000fc80000000f00 */ /*0730*/ MOV R5, R17 ; /* 0x0000001100057202 */ /* 0x000fe40000000f00 */ /*0740*/ ISETP.NE.OR P0, PT, R9, RZ, P0 ; /* 0x000000ff0900720c */ /* 0x000fda0000705670 */ /*0750*/ @!P0 BRA 0x8a0 ; /* 0x0000014000008947 */ /* 0x000fea0003800000 */ /*0760*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */ /* 0x000ea4000c1e1900 */ /*0770*/ FADD R13, R10, R11 ; /* 0x0000000b0a0d7221 */ /* 0x02cfca0000000000 */ /*0780*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */ /* 0x0001e8000c101904 */ /*0790*/ LDG.E R10, [R4.64+0x4] ; /* 0x00000404040a7981 */ /* 0x000ea4000c1e1900 */ /*07a0*/ FADD R15, R13, R10 ; /* 0x0000000a0d0f7221 */ /* 0x004fca0000000000 */ /*07b0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */ /* 0x0003e8000c101904 */ /*07c0*/ LDG.E R10, [R4.64+0x8] ; /* 0x00000804040a7981 */ /* 0x000ea2000c1e1900 */ /*07d0*/ IADD3 R9, R9, -0x4, RZ ; /* 0xfffffffc09097810 */ /* 0x000fe20007ffe0ff */ /*07e0*/ FADD R17, R15, R10 ; /* 0x0000000a0f117221 */ /* 0x004fca0000000000 */ /*07f0*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */ /* 0x0003e8000c101904 */ /*0800*/ LDG.E R10, [R4.64+0xc] ; /* 0x00000c04040a7981 */ /* 0x000ea2000c1e1900 */ /*0810*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */ /* 0x000fe40003f05270 */ /*0820*/ IADD3 R8, R8, 0x4, RZ ; /* 0x0000000408087810 */ /* 0x000fe20007ffe0ff */ /*0830*/ FADD R11, R17, R10 ; /* 0x0000000a110b7221 */ /* 0x004fe20000000000 */ /*0840*/ IADD3 R10, P1, R4, 0x10, RZ ; /* 0x00000010040a7810 */ /* 0x000fc80007f3e0ff */ /*0850*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */ /* 0x0003e2000c101904 */ /*0860*/ IMAD.X R13, RZ, RZ, R5, P1 ; /* 0x000000ffff0d7224 */ /* 0x001fe200008e0605 */ /*0870*/ MOV R4, R10 ; /* 0x0000000a00047202 */ /* 0x000fc80000000f00 */ /*0880*/ MOV R5, R13 ; /* 0x0000000d00057202 */ /* 0x000fe20000000f00 */ /*0890*/ @P0 BRA 0x760 ; /* 0xfffffec000000947 */ /* 0x002fea000383ffff */ /*08a0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */ /* 0x000fda0003f05270 */ /*08b0*/ @!P0 EXIT ; /* 0x000000000000894d */ /* 0x000fea0003800000 */ /*08c0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */ /* 0x000162000c1e1900 */ /*08d0*/ IMAD R7, R7, c[0x0][0x160], R8 ; /* 0x0000580007077a24 */ /* 0x000fc800078e0208 */ /*08e0*/ IMAD.WIDE R6, R7, R6, c[0x0][0x168] ; /* 0x00005a0007067625 */ /* 0x000fc800078e0206 */ /*08f0*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */ /* 0x000fe200078e0006 */ /*0900*/ MOV R5, R7 ; /* 0x0000000700057202 */ /* 0x000fca0000000f00 */ /*0910*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */ /* 0x000ea2000c1e1900 */ /*0920*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */ /* 0x000fe40007ffe0ff */ /*0930*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */ /* 0x000fe40007f3e0ff */ /*0940*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */ /* 0x000fe40003f05270 */ /*0950*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */ /* 0x000fe20000ffe4ff */ /*0960*/ FADD R9, R4, R9 ; /* 0x0000000904097221 */ /* 0x026fca0000000000 */ /*0970*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */ /* 0x0003ea000c101904 */ /*0980*/ @P0 BRA 0x8f0 ; /* 0xffffff6000000947 */ /* 0x000fea000383ffff */ /*0990*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*09a0*/ BRA 0x9a0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*09b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*09c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*09d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*09e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*09f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0a00*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0a10*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0a20*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0a30*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0a40*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0a50*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0a60*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0a70*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected add .globl add .p2align 8 .type add,@function add: s_clause 0x1 s_load_b32 s3, s[0:1], 0x24 s_load_b32 s2, s[0:1], 0x0 s_waitcnt lgkmcnt(0) s_and_b32 s3, s3, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[2:3], null, s15, s3, v[0:1] s_mov_b32 s3, exec_lo v_max_i32_e32 v0, 0, v2 s_delay_alu instid0(VALU_DEP_1) v_cmpx_gt_i32_e64 s2, v0 s_cbranch_execz .LBB0_3 s_load_b128 s[4:7], s[0:1], 0x8 v_ashrrev_i32_e32 v3, 31, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[2:3] v_mul_lo_u32 v2, v2, s2 v_ashrrev_i32_e32 v3, 31, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_lshlrev_b64 v[2:3], 2, v[2:3] s_waitcnt lgkmcnt(0) v_add_co_u32 v0, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo s_delay_alu instid0(VALU_DEP_3) v_add_co_u32 v2, vcc_lo, s4, v2 global_load_b32 v4, v[0:1], off v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo .LBB0_2: global_load_b32 v5, v[2:3], off v_add_co_u32 v2, vcc_lo, v2, 4 v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo s_add_i32 s2, s2, -1 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_lg_u32 s2, 0 s_waitcnt vmcnt(0) v_add_f32_e32 v4, v4, v5 global_store_b32 v[0:1], v4, off s_cbranch_scc1 .LBB0_2 .LBB0_3: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel add .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 6 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size add, .Lfunc_end0-add .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .offset: 0 .size: 4 .value_kind: by_value - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: add .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: add.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 6 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_00001bf6_00000000-6_add.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z25__device_stub__Z3addiPfS_iPfS_ .type _Z25__device_stub__Z3addiPfS_iPfS_, @function _Z25__device_stub__Z3addiPfS_iPfS_: .LFB2051: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movl %edi, 28(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 28(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 120(%rsp), %rax subq %fs:40, %rax jne .L8 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq add(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z25__device_stub__Z3addiPfS_iPfS_, .-_Z25__device_stub__Z3addiPfS_iPfS_ .globl add .type add, @function add: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z25__device_stub__Z3addiPfS_iPfS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size add, .-add .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "add" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq add(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "add.hip" .globl __device_stub__add # -- Begin function __device_stub__add .p2align 4, 0x90 .type __device_stub__add,@function __device_stub__add: # @__device_stub__add .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movl %edi, 12(%rsp) movq %rsi, 72(%rsp) movq %rdx, 64(%rsp) leaq 12(%rsp), %rax movq %rax, 80(%rsp) leaq 72(%rsp), %rax movq %rax, 88(%rsp) leaq 64(%rsp), %rax movq %rax, 96(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $add, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end0: .size __device_stub__add, .Lfunc_end0-__device_stub__add .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $add, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type add,@object # @add .section .rodata,"a",@progbits .globl add .p2align 3, 0x0 add: .quad __device_stub__add .size add, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "add" .size .L__unnamed_1, 4 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __device_stub__add .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym add .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include "includes.h" __global__ void convertBGR2RGBfloatKernel(uchar3 *src, float3 *dst, int width, int height) { int x = threadIdx.x + blockIdx.x * blockDim.x; int y = threadIdx.y + blockIdx.y * blockDim.y; if (x >= width || y >= height) { return; } uchar3 color = src[y * width + x]; dst[y * width + x] = make_float3(color.z, color.y, color.x); }
code for sm_80 Function : _Z25convertBGR2RGBfloatKernelP6uchar3P6float3ii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */ /* 0x000e280000002600 */ /*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */ /* 0x000e280000002200 */ /*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */ /* 0x000e680000002500 */ /*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */ /* 0x000e620000002100 */ /*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */ /* 0x001fca00078e0202 */ /*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */ /* 0x000fe20003f06270 */ /*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */ /* 0x002fca00078e0205 */ /*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */ /* 0x000fda0000706670 */ /*0090*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*00a0*/ HFMA2.MMA R5, -RZ, RZ, 0, 1.78813934326171875e-07 ; /* 0x00000003ff057435 */ /* 0x000fe200000001ff */ /*00b0*/ IMAD R0, R3, c[0x0][0x170], R0 ; /* 0x00005c0003007a24 */ /* 0x000fe200078e0200 */ /*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fd00000000a00 */ /*00d0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */ /* 0x000fca00078e0205 */ /*00e0*/ LDG.E.U8 R6, [R2.64+0x2] ; /* 0x0000020402067981 */ /* 0x000ea8000c1e1100 */ /*00f0*/ LDG.E.U8 R8, [R2.64+0x1] ; /* 0x0000010402087981 */ /* 0x000ee8000c1e1100 */ /*0100*/ LDG.E.U8 R10, [R2.64] ; /* 0x00000004020a7981 */ /* 0x000f22000c1e1100 */ /*0110*/ HFMA2.MMA R5, -RZ, RZ, 0, 7.152557373046875e-07 ; /* 0x0000000cff057435 */ /* 0x000fd400000001ff */ /*0120*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */ /* 0x000fe200078e0205 */ /*0130*/ I2F.U16 R7, R6 ; /* 0x0000000600077306 */ /* 0x004e300000101000 */ /*0140*/ I2F.U16 R9, R8 ; /* 0x0000000800097306 */ /* 0x008e700000101000 */ /*0150*/ I2F.U16 R11, R10 ; /* 0x0000000a000b7306 */ /* 0x010ea20000101000 */ /*0160*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */ /* 0x001fe8000c101904 */ /*0170*/ STG.E [R4.64+0x4], R9 ; /* 0x0000040904007986 */ /* 0x002fe8000c101904 */ /*0180*/ STG.E [R4.64+0x8], R11 ; /* 0x0000080b04007986 */ /* 0x004fe2000c101904 */ /*0190*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*01b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0200*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0210*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0220*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0230*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0240*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0250*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0260*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0270*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include "includes.h" __global__ void convertBGR2RGBfloatKernel(uchar3 *src, float3 *dst, int width, int height) { int x = threadIdx.x + blockIdx.x * blockDim.x; int y = threadIdx.y + blockIdx.y * blockDim.y; if (x >= width || y >= height) { return; } uchar3 color = src[y * width + x]; dst[y * width + x] = make_float3(color.z, color.y, color.x); }
.file "tmpxft_00110ffb_00000000-6_convertBGR2RGBfloatKernel.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z61__device_stub__Z25convertBGR2RGBfloatKernelP6uchar3P6float3iiP6uchar3P6float3ii .type _Z61__device_stub__Z25convertBGR2RGBfloatKernelP6uchar3P6float3iiP6uchar3P6float3ii, @function _Z61__device_stub__Z25convertBGR2RGBfloatKernelP6uchar3P6float3iiP6uchar3P6float3ii: .LFB2051: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z25convertBGR2RGBfloatKernelP6uchar3P6float3ii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z61__device_stub__Z25convertBGR2RGBfloatKernelP6uchar3P6float3iiP6uchar3P6float3ii, .-_Z61__device_stub__Z25convertBGR2RGBfloatKernelP6uchar3P6float3iiP6uchar3P6float3ii .globl _Z25convertBGR2RGBfloatKernelP6uchar3P6float3ii .type _Z25convertBGR2RGBfloatKernelP6uchar3P6float3ii, @function _Z25convertBGR2RGBfloatKernelP6uchar3P6float3ii: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z61__device_stub__Z25convertBGR2RGBfloatKernelP6uchar3P6float3iiP6uchar3P6float3ii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z25convertBGR2RGBfloatKernelP6uchar3P6float3ii, .-_Z25convertBGR2RGBfloatKernelP6uchar3P6float3ii .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC0: .string "_Z25convertBGR2RGBfloatKernelP6uchar3P6float3ii" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z25convertBGR2RGBfloatKernelP6uchar3P6float3ii(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include "includes.h" __global__ void convertBGR2RGBfloatKernel(uchar3 *src, float3 *dst, int width, int height) { int x = threadIdx.x + blockIdx.x * blockDim.x; int y = threadIdx.y + blockIdx.y * blockDim.y; if (x >= width || y >= height) { return; } uchar3 color = src[y * width + x]; dst[y * width + x] = make_float3(color.z, color.y, color.x); }
#include <hip/hip_runtime.h> #include "includes.h" __global__ void convertBGR2RGBfloatKernel(uchar3 *src, float3 *dst, int width, int height) { int x = threadIdx.x + blockIdx.x * blockDim.x; int y = threadIdx.y + blockIdx.y * blockDim.y; if (x >= width || y >= height) { return; } uchar3 color = src[y * width + x]; dst[y * width + x] = make_float3(color.z, color.y, color.x); }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <hip/hip_runtime.h> #include "includes.h" __global__ void convertBGR2RGBfloatKernel(uchar3 *src, float3 *dst, int width, int height) { int x = threadIdx.x + blockIdx.x * blockDim.x; int y = threadIdx.y + blockIdx.y * blockDim.y; if (x >= width || y >= height) { return; } uchar3 color = src[y * width + x]; dst[y * width + x] = make_float3(color.z, color.y, color.x); }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z25convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii .globl _Z25convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii .p2align 8 .type _Z25convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii,@function _Z25convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii: s_clause 0x1 s_load_b32 s2, s[0:1], 0x24 s_load_b64 s[4:5], s[0:1], 0x10 v_and_b32_e32 v2, 0x3ff, v0 v_bfe_u32 v3, v0, 10, 10 s_waitcnt lgkmcnt(0) s_and_b32 s3, s2, 0xffff s_lshr_b32 s2, s2, 16 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3] v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4] v_cmp_gt_i32_e32 vcc_lo, s4, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_gt_i32_e64 s2, s5, v1 s_and_b32 s2, vcc_lo, s2 s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB0_2 s_load_b128 s[0:3], s[0:1], 0x0 v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) v_mad_i64_i32 v[0:1], null, v2, 3, s[0:1] v_mad_i64_i32 v[3:4], null, v2, 12, s[2:3] s_clause 0x2 global_load_u8 v5, v[0:1], off offset:2 global_load_u8 v6, v[0:1], off offset:1 global_load_u8 v7, v[0:1], off s_waitcnt vmcnt(2) v_cvt_f32_ubyte0_e32 v0, v5 s_waitcnt vmcnt(1) v_cvt_f32_ubyte0_e32 v1, v6 s_waitcnt vmcnt(0) v_cvt_f32_ubyte0_e32 v2, v7 global_store_b96 v[3:4], v[0:2], off .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z25convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 8 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z25convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii, .Lfunc_end0-_Z25convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 20 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z25convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z25convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 8 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <hip/hip_runtime.h> #include "includes.h" __global__ void convertBGR2RGBfloatKernel(uchar3 *src, float3 *dst, int width, int height) { int x = threadIdx.x + blockIdx.x * blockDim.x; int y = threadIdx.y + blockIdx.y * blockDim.y; if (x >= width || y >= height) { return; } uchar3 color = src[y * width + x]; dst[y * width + x] = make_float3(color.z, color.y, color.x); }
.text .file "convertBGR2RGBfloatKernel.hip" .globl _Z40__device_stub__convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii # -- Begin function _Z40__device_stub__convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii .p2align 4, 0x90 .type _Z40__device_stub__convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii,@function _Z40__device_stub__convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii: # @_Z40__device_stub__convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 8(%rsp), %rax movq %rax, 104(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z25convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z40__device_stub__convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii, .Lfunc_end0-_Z40__device_stub__convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z25convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z25convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii,@object # @_Z25convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii .section .rodata,"a",@progbits .globl _Z25convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii .p2align 3, 0x0 _Z25convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii: .quad _Z40__device_stub__convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii .size _Z25convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z25convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii" .size .L__unnamed_1, 67 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z40__device_stub__convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z25convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z25convertBGR2RGBfloatKernelP6uchar3P6float3ii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */ /* 0x000e280000002600 */ /*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */ /* 0x000e280000002200 */ /*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */ /* 0x000e680000002500 */ /*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */ /* 0x000e620000002100 */ /*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */ /* 0x001fca00078e0202 */ /*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */ /* 0x000fe20003f06270 */ /*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */ /* 0x002fca00078e0205 */ /*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */ /* 0x000fda0000706670 */ /*0090*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*00a0*/ HFMA2.MMA R5, -RZ, RZ, 0, 1.78813934326171875e-07 ; /* 0x00000003ff057435 */ /* 0x000fe200000001ff */ /*00b0*/ IMAD R0, R3, c[0x0][0x170], R0 ; /* 0x00005c0003007a24 */ /* 0x000fe200078e0200 */ /*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fd00000000a00 */ /*00d0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */ /* 0x000fca00078e0205 */ /*00e0*/ LDG.E.U8 R6, [R2.64+0x2] ; /* 0x0000020402067981 */ /* 0x000ea8000c1e1100 */ /*00f0*/ LDG.E.U8 R8, [R2.64+0x1] ; /* 0x0000010402087981 */ /* 0x000ee8000c1e1100 */ /*0100*/ LDG.E.U8 R10, [R2.64] ; /* 0x00000004020a7981 */ /* 0x000f22000c1e1100 */ /*0110*/ HFMA2.MMA R5, -RZ, RZ, 0, 7.152557373046875e-07 ; /* 0x0000000cff057435 */ /* 0x000fd400000001ff */ /*0120*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */ /* 0x000fe200078e0205 */ /*0130*/ I2F.U16 R7, R6 ; /* 0x0000000600077306 */ /* 0x004e300000101000 */ /*0140*/ I2F.U16 R9, R8 ; /* 0x0000000800097306 */ /* 0x008e700000101000 */ /*0150*/ I2F.U16 R11, R10 ; /* 0x0000000a000b7306 */ /* 0x010ea20000101000 */ /*0160*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */ /* 0x001fe8000c101904 */ /*0170*/ STG.E [R4.64+0x4], R9 ; /* 0x0000040904007986 */ /* 0x002fe8000c101904 */ /*0180*/ STG.E [R4.64+0x8], R11 ; /* 0x0000080b04007986 */ /* 0x004fe2000c101904 */ /*0190*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*01b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0200*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0210*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0220*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0230*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0240*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0250*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0260*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0270*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z25convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii .globl _Z25convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii .p2align 8 .type _Z25convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii,@function _Z25convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii: s_clause 0x1 s_load_b32 s2, s[0:1], 0x24 s_load_b64 s[4:5], s[0:1], 0x10 v_and_b32_e32 v2, 0x3ff, v0 v_bfe_u32 v3, v0, 10, 10 s_waitcnt lgkmcnt(0) s_and_b32 s3, s2, 0xffff s_lshr_b32 s2, s2, 16 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3] v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4] v_cmp_gt_i32_e32 vcc_lo, s4, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_gt_i32_e64 s2, s5, v1 s_and_b32 s2, vcc_lo, s2 s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB0_2 s_load_b128 s[0:3], s[0:1], 0x0 v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) v_mad_i64_i32 v[0:1], null, v2, 3, s[0:1] v_mad_i64_i32 v[3:4], null, v2, 12, s[2:3] s_clause 0x2 global_load_u8 v5, v[0:1], off offset:2 global_load_u8 v6, v[0:1], off offset:1 global_load_u8 v7, v[0:1], off s_waitcnt vmcnt(2) v_cvt_f32_ubyte0_e32 v0, v5 s_waitcnt vmcnt(1) v_cvt_f32_ubyte0_e32 v1, v6 s_waitcnt vmcnt(0) v_cvt_f32_ubyte0_e32 v2, v7 global_store_b96 v[3:4], v[0:2], off .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z25convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 8 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z25convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii, .Lfunc_end0-_Z25convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 20 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z25convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z25convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 8 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_00110ffb_00000000-6_convertBGR2RGBfloatKernel.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z61__device_stub__Z25convertBGR2RGBfloatKernelP6uchar3P6float3iiP6uchar3P6float3ii .type _Z61__device_stub__Z25convertBGR2RGBfloatKernelP6uchar3P6float3iiP6uchar3P6float3ii, @function _Z61__device_stub__Z25convertBGR2RGBfloatKernelP6uchar3P6float3iiP6uchar3P6float3ii: .LFB2051: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z25convertBGR2RGBfloatKernelP6uchar3P6float3ii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z61__device_stub__Z25convertBGR2RGBfloatKernelP6uchar3P6float3iiP6uchar3P6float3ii, .-_Z61__device_stub__Z25convertBGR2RGBfloatKernelP6uchar3P6float3iiP6uchar3P6float3ii .globl _Z25convertBGR2RGBfloatKernelP6uchar3P6float3ii .type _Z25convertBGR2RGBfloatKernelP6uchar3P6float3ii, @function _Z25convertBGR2RGBfloatKernelP6uchar3P6float3ii: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z61__device_stub__Z25convertBGR2RGBfloatKernelP6uchar3P6float3iiP6uchar3P6float3ii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z25convertBGR2RGBfloatKernelP6uchar3P6float3ii, .-_Z25convertBGR2RGBfloatKernelP6uchar3P6float3ii .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC0: .string "_Z25convertBGR2RGBfloatKernelP6uchar3P6float3ii" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z25convertBGR2RGBfloatKernelP6uchar3P6float3ii(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "convertBGR2RGBfloatKernel.hip" .globl _Z40__device_stub__convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii # -- Begin function _Z40__device_stub__convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii .p2align 4, 0x90 .type _Z40__device_stub__convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii,@function _Z40__device_stub__convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii: # @_Z40__device_stub__convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 8(%rsp), %rax movq %rax, 104(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z25convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z40__device_stub__convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii, .Lfunc_end0-_Z40__device_stub__convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z25convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z25convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii,@object # @_Z25convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii .section .rodata,"a",@progbits .globl _Z25convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii .p2align 3, 0x0 _Z25convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii: .quad _Z40__device_stub__convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii .size _Z25convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z25convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii" .size .L__unnamed_1, 67 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z40__device_stub__convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z25convertBGR2RGBfloatKernelP15HIP_vector_typeIhLj3EEPS_IfLj3EEii .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include <iostream> #include <cuda.h> using std::cout; using std::endl; __global__ void my_kernel() { // I do absolutely nothing } int main(int argc, char *argv[]) { cout << "Hello world!! I will call a CUDA kernel now!!" << endl; my_kernel<<<1,1,0>>>(); cudaDeviceSynchronize(); return 0; }
code for sm_80 Function : _Z9my_kernelv .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0020*/ BRA 0x20; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0030*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0040*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0050*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0060*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0070*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0080*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0090*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include <iostream> #include <cuda.h> using std::cout; using std::endl; __global__ void my_kernel() { // I do absolutely nothing } int main(int argc, char *argv[]) { cout << "Hello world!! I will call a CUDA kernel now!!" << endl; my_kernel<<<1,1,0>>>(); cudaDeviceSynchronize(); return 0; }
.file "tmpxft_001485f6_00000000-6_hello.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3672: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3672: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z27__device_stub__Z9my_kernelvv .type _Z27__device_stub__Z9my_kernelvv, @function _Z27__device_stub__Z9my_kernelvv: .LFB3694: .cfi_startproc endbr64 subq $88, %rsp .cfi_def_cfa_offset 96 movq %fs:40, %rax movq %rax, 72(%rsp) xorl %eax, %eax movl $1, 16(%rsp) movl $1, 20(%rsp) movl $1, 24(%rsp) movl $1, 28(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) leaq 8(%rsp), %rcx movq %rsp, %rdx leaq 28(%rsp), %rsi leaq 16(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 72(%rsp), %rax subq %fs:40, %rax jne .L8 addq $88, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 8(%rsp) .cfi_def_cfa_offset 104 pushq 8(%rsp) .cfi_def_cfa_offset 112 leaq 80(%rsp), %r9 movq 44(%rsp), %rcx movl 52(%rsp), %r8d movq 32(%rsp), %rsi movl 40(%rsp), %edx leaq _Z9my_kernelv(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 96 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE3694: .size _Z27__device_stub__Z9my_kernelvv, .-_Z27__device_stub__Z9my_kernelvv .globl _Z9my_kernelv .type _Z9my_kernelv, @function _Z9my_kernelv: .LFB3695: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z27__device_stub__Z9my_kernelvv addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3695: .size _Z9my_kernelv, .-_Z9my_kernelv .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC0: .string "Hello world!! I will call a CUDA kernel now!!" .text .globl main .type main, @function main: .LFB3669: .cfi_startproc endbr64 subq $40, %rsp .cfi_def_cfa_offset 48 leaq .LC0(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movl $1, 20(%rsp) movl $1, 24(%rsp) movl $1, 8(%rsp) movl $1, 12(%rsp) movl $0, %r9d movl $0, %r8d movq 20(%rsp), %rdx movl $1, %ecx movq 8(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L14 .L12: call cudaDeviceSynchronize@PLT movl $0, %eax addq $40, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L14: .cfi_restore_state call _Z27__device_stub__Z9my_kernelvv jmp .L12 .cfi_endproc .LFE3669: .size main, .-main .section .rodata.str1.1,"aMS",@progbits,1 .LC1: .string "_Z9my_kernelv" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3697: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC1(%rip), %rdx movq %rdx, %rcx leaq _Z9my_kernelv(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3697: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include <iostream> #include <cuda.h> using std::cout; using std::endl; __global__ void my_kernel() { // I do absolutely nothing } int main(int argc, char *argv[]) { cout << "Hello world!! I will call a CUDA kernel now!!" << endl; my_kernel<<<1,1,0>>>(); cudaDeviceSynchronize(); return 0; }
#include <iostream> #include <hip/hip_runtime.h> using std::cout; using std::endl; __global__ void my_kernel() { // I do absolutely nothing } int main(int argc, char *argv[]) { cout << "Hello world!! I will call a CUDA kernel now!!" << endl; my_kernel<<<1,1,0>>>(); hipDeviceSynchronize(); return 0; }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <iostream> #include <hip/hip_runtime.h> using std::cout; using std::endl; __global__ void my_kernel() { // I do absolutely nothing } int main(int argc, char *argv[]) { cout << "Hello world!! I will call a CUDA kernel now!!" << endl; my_kernel<<<1,1,0>>>(); hipDeviceSynchronize(); return 0; }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z9my_kernelv .globl _Z9my_kernelv .p2align 8 .type _Z9my_kernelv,@function _Z9my_kernelv: s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z9my_kernelv .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 0 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 0 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 1 .amdhsa_next_free_sgpr 1 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z9my_kernelv, .Lfunc_end0-_Z9my_kernelv .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: [] .group_segment_fixed_size: 0 .kernarg_segment_align: 4 .kernarg_segment_size: 0 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z9my_kernelv .private_segment_fixed_size: 0 .sgpr_count: 0 .sgpr_spill_count: 0 .symbol: _Z9my_kernelv.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 0 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <iostream> #include <hip/hip_runtime.h> using std::cout; using std::endl; __global__ void my_kernel() { // I do absolutely nothing } int main(int argc, char *argv[]) { cout << "Hello world!! I will call a CUDA kernel now!!" << endl; my_kernel<<<1,1,0>>>(); hipDeviceSynchronize(); return 0; }
.text .file "hello.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z24__device_stub__my_kernelv # -- Begin function _Z24__device_stub__my_kernelv .p2align 4, 0x90 .type _Z24__device_stub__my_kernelv,@function _Z24__device_stub__my_kernelv: # @_Z24__device_stub__my_kernelv .cfi_startproc # %bb.0: subq $56, %rsp .cfi_def_cfa_offset 64 leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 48(%rsp), %r9 movl $_Z9my_kernelv, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $72, %rsp .cfi_adjust_cfa_offset -72 retq .Lfunc_end0: .size _Z24__device_stub__my_kernelv, .Lfunc_end0-_Z24__device_stub__my_kernelv .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $64, %rsp .cfi_def_cfa_offset 80 .cfi_offset %rbx, -16 movl $_ZSt4cout, %edi movl $.L.str, %esi movl $45, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %rbx testq %rbx, %rbx je .LBB1_7 # %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i cmpb $0, 56(%rbx) je .LBB1_3 # %bb.2: movzbl 67(%rbx), %eax jmp .LBB1_4 .LBB1_3: movq %rbx, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%rbx), %rax movq %rbx, %rdi movl $10, %esi callq *48(%rax) .LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movabsq $4294967297, %rdi # imm = 0x100000001 movl $1, %esi movq %rdi, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_6 # %bb.5: leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 48(%rsp), %r9 movl $_Z9my_kernelv, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_6: callq hipDeviceSynchronize xorl %eax, %eax addq $64, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 retq .LBB1_7: .cfi_def_cfa_offset 80 callq _ZSt16__throw_bad_castv .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z9my_kernelv, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z9my_kernelv,@object # @_Z9my_kernelv .section .rodata,"a",@progbits .globl _Z9my_kernelv .p2align 3, 0x0 _Z9my_kernelv: .quad _Z24__device_stub__my_kernelv .size _Z9my_kernelv, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Hello world!! I will call a CUDA kernel now!!" .size .L.str, 46 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z9my_kernelv" .size .L__unnamed_1, 14 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z24__device_stub__my_kernelv .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z9my_kernelv .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z9my_kernelv .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0020*/ BRA 0x20; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0030*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0040*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0050*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0060*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0070*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0080*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0090*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z9my_kernelv .globl _Z9my_kernelv .p2align 8 .type _Z9my_kernelv,@function _Z9my_kernelv: s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z9my_kernelv .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 0 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 0 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 1 .amdhsa_next_free_sgpr 1 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z9my_kernelv, .Lfunc_end0-_Z9my_kernelv .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: [] .group_segment_fixed_size: 0 .kernarg_segment_align: 4 .kernarg_segment_size: 0 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z9my_kernelv .private_segment_fixed_size: 0 .sgpr_count: 0 .sgpr_spill_count: 0 .symbol: _Z9my_kernelv.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 0 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_001485f6_00000000-6_hello.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3672: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3672: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z27__device_stub__Z9my_kernelvv .type _Z27__device_stub__Z9my_kernelvv, @function _Z27__device_stub__Z9my_kernelvv: .LFB3694: .cfi_startproc endbr64 subq $88, %rsp .cfi_def_cfa_offset 96 movq %fs:40, %rax movq %rax, 72(%rsp) xorl %eax, %eax movl $1, 16(%rsp) movl $1, 20(%rsp) movl $1, 24(%rsp) movl $1, 28(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) leaq 8(%rsp), %rcx movq %rsp, %rdx leaq 28(%rsp), %rsi leaq 16(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 72(%rsp), %rax subq %fs:40, %rax jne .L8 addq $88, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 8(%rsp) .cfi_def_cfa_offset 104 pushq 8(%rsp) .cfi_def_cfa_offset 112 leaq 80(%rsp), %r9 movq 44(%rsp), %rcx movl 52(%rsp), %r8d movq 32(%rsp), %rsi movl 40(%rsp), %edx leaq _Z9my_kernelv(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 96 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE3694: .size _Z27__device_stub__Z9my_kernelvv, .-_Z27__device_stub__Z9my_kernelvv .globl _Z9my_kernelv .type _Z9my_kernelv, @function _Z9my_kernelv: .LFB3695: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z27__device_stub__Z9my_kernelvv addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3695: .size _Z9my_kernelv, .-_Z9my_kernelv .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC0: .string "Hello world!! I will call a CUDA kernel now!!" .text .globl main .type main, @function main: .LFB3669: .cfi_startproc endbr64 subq $40, %rsp .cfi_def_cfa_offset 48 leaq .LC0(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movl $1, 20(%rsp) movl $1, 24(%rsp) movl $1, 8(%rsp) movl $1, 12(%rsp) movl $0, %r9d movl $0, %r8d movq 20(%rsp), %rdx movl $1, %ecx movq 8(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L14 .L12: call cudaDeviceSynchronize@PLT movl $0, %eax addq $40, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L14: .cfi_restore_state call _Z27__device_stub__Z9my_kernelvv jmp .L12 .cfi_endproc .LFE3669: .size main, .-main .section .rodata.str1.1,"aMS",@progbits,1 .LC1: .string "_Z9my_kernelv" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3697: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC1(%rip), %rdx movq %rdx, %rcx leaq _Z9my_kernelv(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3697: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "hello.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z24__device_stub__my_kernelv # -- Begin function _Z24__device_stub__my_kernelv .p2align 4, 0x90 .type _Z24__device_stub__my_kernelv,@function _Z24__device_stub__my_kernelv: # @_Z24__device_stub__my_kernelv .cfi_startproc # %bb.0: subq $56, %rsp .cfi_def_cfa_offset 64 leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 48(%rsp), %r9 movl $_Z9my_kernelv, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $72, %rsp .cfi_adjust_cfa_offset -72 retq .Lfunc_end0: .size _Z24__device_stub__my_kernelv, .Lfunc_end0-_Z24__device_stub__my_kernelv .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $64, %rsp .cfi_def_cfa_offset 80 .cfi_offset %rbx, -16 movl $_ZSt4cout, %edi movl $.L.str, %esi movl $45, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %rbx testq %rbx, %rbx je .LBB1_7 # %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i cmpb $0, 56(%rbx) je .LBB1_3 # %bb.2: movzbl 67(%rbx), %eax jmp .LBB1_4 .LBB1_3: movq %rbx, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%rbx), %rax movq %rbx, %rdi movl $10, %esi callq *48(%rax) .LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movabsq $4294967297, %rdi # imm = 0x100000001 movl $1, %esi movq %rdi, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_6 # %bb.5: leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 48(%rsp), %r9 movl $_Z9my_kernelv, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_6: callq hipDeviceSynchronize xorl %eax, %eax addq $64, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 retq .LBB1_7: .cfi_def_cfa_offset 80 callq _ZSt16__throw_bad_castv .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z9my_kernelv, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z9my_kernelv,@object # @_Z9my_kernelv .section .rodata,"a",@progbits .globl _Z9my_kernelv .p2align 3, 0x0 _Z9my_kernelv: .quad _Z24__device_stub__my_kernelv .size _Z9my_kernelv, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Hello world!! I will call a CUDA kernel now!!" .size .L.str, 46 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z9my_kernelv" .size .L__unnamed_1, 14 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z24__device_stub__my_kernelv .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z9my_kernelv .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
__global__ void Suma(int t_a, int t_b, int size_n, int size_m, float *a, float *b, float *c) { const uint idx = threadIdx.x + blockDim.x * blockIdx.x; const uint idy = threadIdx.y + blockDim.y * blockIdx.y; int ida = 0; int idb = 0; if(idx < size_m && idy < size_n){ if(t_a == 0){ ida = idx + (idy*size_m); } else{ ida = idy + (idx*size_n); } if(t_b == 0){ idb = idx + (idy*size_m); } else{ idb = idy + (idx*size_n); } c[idx + (idy*size_m)] = a[ida] + b[idb]; } } __global__ void Resta(int t_a, int t_b, int size_n, int size_m, float *a, float *b, float *c) { const uint idx = threadIdx.x + blockDim.x * blockIdx.x; const uint idy = threadIdx.y + blockDim.y * blockIdx.y; int ida = 0; int idb = 0; if(idx < size_m && idy < size_n){ if(t_a == 0){ ida = idx + (idy*size_m); } else{ ida = idy + (idx*size_n); } if(t_b == 0){ idb = idx + (idy*size_m); } else{ idb = idy + (idx*size_n); } c[idx + (idy*size_m)] = a[ida] - b[idb]; } } __global__ void Multi(int t_a, int t_b, int size_n, int size_m, float *a, float *b, float *c) { const uint idx = threadIdx.x + blockDim.x * blockIdx.x; const uint idy = threadIdx.y + blockDim.y * blockIdx.y; int ida = 0; int idb = 0; if(idx < size_m && idy < size_n){ if(t_a == 0){ ida = idx + (idy*size_m); } else{ ida = idy + (idx*size_n); } if(t_b == 0){ idb = idx + (idy*size_m); } else{ idb = idy + (idx*size_n); } c[idx + (idy*size_m)] = a[ida] * b[idb]; } } __global__ void RMulti(int t_a, int t_b, int size_n, int size_m, float b, float *a, float *c) { const uint idx = threadIdx.x + blockDim.x * blockIdx.x; const uint idy = threadIdx.y + blockDim.y * blockIdx.y; if(idx < size_m && idy < size_n){ c[idx + (idy*size_m)] = a[idx + (idy*size_m)] * b; } } __global__ void Divide(int t_a, int t_b, int size_n, int size_m, float *a, float *b, float *c) { const uint idx = threadIdx.x + blockDim.x * blockIdx.x; const uint idy = threadIdx.y + blockDim.y * blockIdx.y; int ida = 0; int idb = 0; if(idx < size_m && idy < size_n){ if(t_a == 0){ ida = idx + (idy*size_m); } else{ ida = idy + (idx*size_n); } if(t_b == 0){ idb = idx + (idy*size_m); } else{ idb = idy + (idx*size_n); } c[idx + (idy*size_m)] = a[ida] / b[idb]; } } __global__ void DOT(int t_a, int t_b, int sizean, int sizeam, int sizebm,float *a, float *b, float *c) { const uint tx = threadIdx.x + blockDim.x * blockIdx.x; const uint ty = threadIdx.y + blockDim.y * blockIdx.y; int ida = 0; int idb = 0; if(tx < sizebm && ty < sizean){ float Pvalue = 0; for (int k = 0; k < sizeam; ++k) { if(t_a == 0){ ida = ty * sizeam + k; } else{ ida = k * sizean + ty; } if(t_b == 0){ idb = k * sizebm + tx; } else{ idb = tx * sizeam + k; } float Aelement = a[ida]; float Belement = b[idb]; Pvalue += Aelement * Belement; } c[ty * sizebm + tx] = Pvalue; } } // dominante modificando la matriz original __global__ void Dom1(int size, float *a) { int ty = threadIdx.y + blockDim.y * blockIdx.y; float Pvalue = 0; if(ty < size){ for (int i = 0; i < size; ++i) { Pvalue += abs(a[ty * size + i]); } a[ty * size + ty] = Pvalue + 2000.0; } } // dominante guardando el resultado en otra matriz __global__ void Dom2(int size, float *a, float *b) { int ty = threadIdx.y + blockDim.y * blockIdx.y; float Pvalue = 0; if(ty < size){ for (int i = 0; i < size; ++i) { Pvalue += abs(a[ty * size + i]); b[ty * size + i] = a[ty * size + i]; } b[ty * size + ty] = Pvalue + 2000.0; } } __global__ void Transpose(int sizem, int sizen, const float *a, float *b) { const uint tx = threadIdx.x + blockDim.x * blockIdx.x; const uint ty = threadIdx.y + blockDim.y * blockIdx.y; if(tx < sizem && ty < sizen){ b[ty + (tx*sizen)] = a[tx + (ty*sizem)]; } } __global__ void neg(int size_n, int size_m, float * a, float *b) { const uint tx = threadIdx.x + blockDim.x * blockIdx.x; const uint ty = threadIdx.y + blockDim.y * blockIdx.y; if(tx < size_m && ty < size_n){ b[tx + (ty*size_m)] = a[tx + (ty*size_m)] * -1; } } __global__ void absolute(int size_n, int size_m, float *a, float *b) { const uint tx = threadIdx.x + blockDim.x * blockIdx.x; const uint ty = threadIdx.y + blockDim.y * blockIdx.y; if(tx < size_m && ty < size_n){ b[tx + (ty*size_m)] = abs(a[tx + (ty*size_m)]); } } // metodos para diagonales __global__ void Diag(int size, float *a, float *b) { const uint idy = threadIdx.y + blockDim.y * blockIdx.y; if(idy < size){ b[idy] = a[idy + (idy*size)]; } } __global__ void DiagFlat(int size, float *a, float *b) { const uint idy = threadIdx.y + blockDim.y * blockIdx.y; if(idy < size){ b[idy + (idy*size)] = a[idy]; } } // vec_dot sacado de https://www.nvidia.com/content/GTC-2010/pdfs/2131_GTC2010.pdf // matrixMul sacado de https://gist.github.com/wh5a/4313739 #define TILE_WIDTH 32 // Compute C = A * B __global__ void matrixMul(float * A, float * B, float * C, int numARows, int numAColumns, int numBRows, int numBColumns, int numCRows, int numCColumns, int t_a, int t_b) { //@@ Insert code to implement matrix multiplication here __shared__ float ds_M[TILE_WIDTH][TILE_WIDTH]; __shared__ float ds_N[TILE_WIDTH][TILE_WIDTH]; int bx = blockIdx.x, by = blockIdx.y, tx = threadIdx.x, ty = threadIdx.y, Row = by * TILE_WIDTH + ty, Col = bx * TILE_WIDTH + tx; float Pvalue = 0; int ida = 0; int idb = 0; for (int m = 0; m < (numAColumns-1)/TILE_WIDTH+1; ++m) { if (Row < numARows && m*TILE_WIDTH+tx < numAColumns){ if(t_a == 0){ ida = Row*numAColumns + (m*TILE_WIDTH+tx); } else{ ida = (m*TILE_WIDTH+tx)*numARows + Row; } ds_M[ty][tx] = A[ida]; } else{ ds_M[ty][tx] = 0; } if (Col < numBColumns && m*TILE_WIDTH+ty < numBRows){ if(t_b == 0){ idb = (m*TILE_WIDTH+ty)*numBColumns+Col; } else{ idb = Col*numBRows+(m*TILE_WIDTH+ty); } ds_N[ty][tx] = B[idb]; } else{ ds_N[ty][tx] = 0; } __syncthreads(); for (int k = 0; k < TILE_WIDTH; ++k) Pvalue += ds_M[ty][k] * ds_N[k][tx]; __syncthreads(); } if (Row < numCRows && Col < numCColumns) C[Row*numCColumns+Col] = Pvalue; } #define N 1024 // Compute C = A * B __global__ void vec_dot(float * a, float * b, float * c, int size, int t_a, int t_b) { c[0] = 0; __shared__ float temp[N]; int tx = threadIdx.x + blockDim.x * blockIdx.x; temp[threadIdx.x] = a[tx] * b[tx]; __syncthreads(); if(threadIdx.x == 0){ float sum = 0; for(int i = 0; i < N; i++){ if(tx + i < size){ sum += temp[i]; } } atomicAdd(c,sum); } } // matrix * vector __global__ void MatDotVec(float * A, float * B, float * C, int numARows, int numAColumns, int numBRows, int numBColumns, int numCRows, int numCColumns, int t_a, int t_b) { __shared__ float sub_mat[TILE_WIDTH][TILE_WIDTH]; __shared__ float sub_vec[TILE_WIDTH]; int by = blockIdx.y, ty = threadIdx.y, Row = by * TILE_WIDTH + ty; float Pvalue = 0; int ida = 0; for (int m = 0; m < (numAColumns-1)/TILE_WIDTH+1; ++m) { for (int tx = 0; tx <TILE_WIDTH; ++tx){ if (Row < numARows && m*TILE_WIDTH+tx < numAColumns){ if(t_a == 0){ ida = Row*numAColumns + (m*TILE_WIDTH+tx); } else{ ida = (m*TILE_WIDTH+tx)*numARows + Row; } sub_mat[ty][tx] = A[ida]; } else{ sub_mat[ty][tx] = 0; } } if(m*TILE_WIDTH+ty<numBRows){ sub_vec[ty] = B[m*TILE_WIDTH+ty]; } else{ sub_vec[ty]= 0; } __syncthreads(); for (int k = 0; k < TILE_WIDTH; ++k) Pvalue += sub_mat[ty][k] * sub_vec[k]; __syncthreads(); } if (Row < numCRows) C[Row] = Pvalue; } // Compute C = A * B #define N 1024 __global__ void cuadratic_sum(float * a, float * c, int size) { c[0] = 0; __shared__ float temp[N]; int tx = threadIdx.x + blockDim.x * blockIdx.x; temp[threadIdx.x] = a[tx] * a[tx]; __syncthreads(); if(threadIdx.x == 0){ float sum = 0; for(int i = 0; i < N; i++){ if(tx + i < size){ sum += temp[i]; } } atomicAdd(c,sum); } }
#include <hip/hip_runtime.h> __global__ void Suma(int t_a, int t_b, int size_n, int size_m, float *a, float *b, float *c) { const uint idx = threadIdx.x + blockDim.x * blockIdx.x; const uint idy = threadIdx.y + blockDim.y * blockIdx.y; int ida = 0; int idb = 0; if(idx < size_m && idy < size_n){ if(t_a == 0){ ida = idx + (idy*size_m); } else{ ida = idy + (idx*size_n); } if(t_b == 0){ idb = idx + (idy*size_m); } else{ idb = idy + (idx*size_n); } c[idx + (idy*size_m)] = a[ida] + b[idb]; } } __global__ void Resta(int t_a, int t_b, int size_n, int size_m, float *a, float *b, float *c) { const uint idx = threadIdx.x + blockDim.x * blockIdx.x; const uint idy = threadIdx.y + blockDim.y * blockIdx.y; int ida = 0; int idb = 0; if(idx < size_m && idy < size_n){ if(t_a == 0){ ida = idx + (idy*size_m); } else{ ida = idy + (idx*size_n); } if(t_b == 0){ idb = idx + (idy*size_m); } else{ idb = idy + (idx*size_n); } c[idx + (idy*size_m)] = a[ida] - b[idb]; } } __global__ void Multi(int t_a, int t_b, int size_n, int size_m, float *a, float *b, float *c) { const uint idx = threadIdx.x + blockDim.x * blockIdx.x; const uint idy = threadIdx.y + blockDim.y * blockIdx.y; int ida = 0; int idb = 0; if(idx < size_m && idy < size_n){ if(t_a == 0){ ida = idx + (idy*size_m); } else{ ida = idy + (idx*size_n); } if(t_b == 0){ idb = idx + (idy*size_m); } else{ idb = idy + (idx*size_n); } c[idx + (idy*size_m)] = a[ida] * b[idb]; } } __global__ void RMulti(int t_a, int t_b, int size_n, int size_m, float b, float *a, float *c) { const uint idx = threadIdx.x + blockDim.x * blockIdx.x; const uint idy = threadIdx.y + blockDim.y * blockIdx.y; if(idx < size_m && idy < size_n){ c[idx + (idy*size_m)] = a[idx + (idy*size_m)] * b; } } __global__ void Divide(int t_a, int t_b, int size_n, int size_m, float *a, float *b, float *c) { const uint idx = threadIdx.x + blockDim.x * blockIdx.x; const uint idy = threadIdx.y + blockDim.y * blockIdx.y; int ida = 0; int idb = 0; if(idx < size_m && idy < size_n){ if(t_a == 0){ ida = idx + (idy*size_m); } else{ ida = idy + (idx*size_n); } if(t_b == 0){ idb = idx + (idy*size_m); } else{ idb = idy + (idx*size_n); } c[idx + (idy*size_m)] = a[ida] / b[idb]; } } __global__ void DOT(int t_a, int t_b, int sizean, int sizeam, int sizebm,float *a, float *b, float *c) { const uint tx = threadIdx.x + blockDim.x * blockIdx.x; const uint ty = threadIdx.y + blockDim.y * blockIdx.y; int ida = 0; int idb = 0; if(tx < sizebm && ty < sizean){ float Pvalue = 0; for (int k = 0; k < sizeam; ++k) { if(t_a == 0){ ida = ty * sizeam + k; } else{ ida = k * sizean + ty; } if(t_b == 0){ idb = k * sizebm + tx; } else{ idb = tx * sizeam + k; } float Aelement = a[ida]; float Belement = b[idb]; Pvalue += Aelement * Belement; } c[ty * sizebm + tx] = Pvalue; } } // dominante modificando la matriz original __global__ void Dom1(int size, float *a) { int ty = threadIdx.y + blockDim.y * blockIdx.y; float Pvalue = 0; if(ty < size){ for (int i = 0; i < size; ++i) { Pvalue += abs(a[ty * size + i]); } a[ty * size + ty] = Pvalue + 2000.0; } } // dominante guardando el resultado en otra matriz __global__ void Dom2(int size, float *a, float *b) { int ty = threadIdx.y + blockDim.y * blockIdx.y; float Pvalue = 0; if(ty < size){ for (int i = 0; i < size; ++i) { Pvalue += abs(a[ty * size + i]); b[ty * size + i] = a[ty * size + i]; } b[ty * size + ty] = Pvalue + 2000.0; } } __global__ void Transpose(int sizem, int sizen, const float *a, float *b) { const uint tx = threadIdx.x + blockDim.x * blockIdx.x; const uint ty = threadIdx.y + blockDim.y * blockIdx.y; if(tx < sizem && ty < sizen){ b[ty + (tx*sizen)] = a[tx + (ty*sizem)]; } } __global__ void neg(int size_n, int size_m, float * a, float *b) { const uint tx = threadIdx.x + blockDim.x * blockIdx.x; const uint ty = threadIdx.y + blockDim.y * blockIdx.y; if(tx < size_m && ty < size_n){ b[tx + (ty*size_m)] = a[tx + (ty*size_m)] * -1; } } __global__ void absolute(int size_n, int size_m, float *a, float *b) { const uint tx = threadIdx.x + blockDim.x * blockIdx.x; const uint ty = threadIdx.y + blockDim.y * blockIdx.y; if(tx < size_m && ty < size_n){ b[tx + (ty*size_m)] = abs(a[tx + (ty*size_m)]); } } // metodos para diagonales __global__ void Diag(int size, float *a, float *b) { const uint idy = threadIdx.y + blockDim.y * blockIdx.y; if(idy < size){ b[idy] = a[idy + (idy*size)]; } } __global__ void DiagFlat(int size, float *a, float *b) { const uint idy = threadIdx.y + blockDim.y * blockIdx.y; if(idy < size){ b[idy + (idy*size)] = a[idy]; } } // vec_dot sacado de https://www.nvidia.com/content/GTC-2010/pdfs/2131_GTC2010.pdf // matrixMul sacado de https://gist.github.com/wh5a/4313739 #define TILE_WIDTH 32 // Compute C = A * B __global__ void matrixMul(float * A, float * B, float * C, int numARows, int numAColumns, int numBRows, int numBColumns, int numCRows, int numCColumns, int t_a, int t_b) { //@@ Insert code to implement matrix multiplication here __shared__ float ds_M[TILE_WIDTH][TILE_WIDTH]; __shared__ float ds_N[TILE_WIDTH][TILE_WIDTH]; int bx = blockIdx.x, by = blockIdx.y, tx = threadIdx.x, ty = threadIdx.y, Row = by * TILE_WIDTH + ty, Col = bx * TILE_WIDTH + tx; float Pvalue = 0; int ida = 0; int idb = 0; for (int m = 0; m < (numAColumns-1)/TILE_WIDTH+1; ++m) { if (Row < numARows && m*TILE_WIDTH+tx < numAColumns){ if(t_a == 0){ ida = Row*numAColumns + (m*TILE_WIDTH+tx); } else{ ida = (m*TILE_WIDTH+tx)*numARows + Row; } ds_M[ty][tx] = A[ida]; } else{ ds_M[ty][tx] = 0; } if (Col < numBColumns && m*TILE_WIDTH+ty < numBRows){ if(t_b == 0){ idb = (m*TILE_WIDTH+ty)*numBColumns+Col; } else{ idb = Col*numBRows+(m*TILE_WIDTH+ty); } ds_N[ty][tx] = B[idb]; } else{ ds_N[ty][tx] = 0; } __syncthreads(); for (int k = 0; k < TILE_WIDTH; ++k) Pvalue += ds_M[ty][k] * ds_N[k][tx]; __syncthreads(); } if (Row < numCRows && Col < numCColumns) C[Row*numCColumns+Col] = Pvalue; } #define N 1024 // Compute C = A * B __global__ void vec_dot(float * a, float * b, float * c, int size, int t_a, int t_b) { c[0] = 0; __shared__ float temp[N]; int tx = threadIdx.x + blockDim.x * blockIdx.x; temp[threadIdx.x] = a[tx] * b[tx]; __syncthreads(); if(threadIdx.x == 0){ float sum = 0; for(int i = 0; i < N; i++){ if(tx + i < size){ sum += temp[i]; } } atomicAdd(c,sum); } } // matrix * vector __global__ void MatDotVec(float * A, float * B, float * C, int numARows, int numAColumns, int numBRows, int numBColumns, int numCRows, int numCColumns, int t_a, int t_b) { __shared__ float sub_mat[TILE_WIDTH][TILE_WIDTH]; __shared__ float sub_vec[TILE_WIDTH]; int by = blockIdx.y, ty = threadIdx.y, Row = by * TILE_WIDTH + ty; float Pvalue = 0; int ida = 0; for (int m = 0; m < (numAColumns-1)/TILE_WIDTH+1; ++m) { for (int tx = 0; tx <TILE_WIDTH; ++tx){ if (Row < numARows && m*TILE_WIDTH+tx < numAColumns){ if(t_a == 0){ ida = Row*numAColumns + (m*TILE_WIDTH+tx); } else{ ida = (m*TILE_WIDTH+tx)*numARows + Row; } sub_mat[ty][tx] = A[ida]; } else{ sub_mat[ty][tx] = 0; } } if(m*TILE_WIDTH+ty<numBRows){ sub_vec[ty] = B[m*TILE_WIDTH+ty]; } else{ sub_vec[ty]= 0; } __syncthreads(); for (int k = 0; k < TILE_WIDTH; ++k) Pvalue += sub_mat[ty][k] * sub_vec[k]; __syncthreads(); } if (Row < numCRows) C[Row] = Pvalue; } // Compute C = A * B #define N 1024 __global__ void cuadratic_sum(float * a, float * c, int size) { c[0] = 0; __shared__ float temp[N]; int tx = threadIdx.x + blockDim.x * blockIdx.x; temp[threadIdx.x] = a[tx] * a[tx]; __syncthreads(); if(threadIdx.x == 0){ float sum = 0; for(int i = 0; i < N; i++){ if(tx + i < size){ sum += temp[i]; } } atomicAdd(c,sum); } }
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <hip/hip_runtime.h> __global__ void Suma(int t_a, int t_b, int size_n, int size_m, float *a, float *b, float *c) { const uint idx = threadIdx.x + blockDim.x * blockIdx.x; const uint idy = threadIdx.y + blockDim.y * blockIdx.y; int ida = 0; int idb = 0; if(idx < size_m && idy < size_n){ if(t_a == 0){ ida = idx + (idy*size_m); } else{ ida = idy + (idx*size_n); } if(t_b == 0){ idb = idx + (idy*size_m); } else{ idb = idy + (idx*size_n); } c[idx + (idy*size_m)] = a[ida] + b[idb]; } } __global__ void Resta(int t_a, int t_b, int size_n, int size_m, float *a, float *b, float *c) { const uint idx = threadIdx.x + blockDim.x * blockIdx.x; const uint idy = threadIdx.y + blockDim.y * blockIdx.y; int ida = 0; int idb = 0; if(idx < size_m && idy < size_n){ if(t_a == 0){ ida = idx + (idy*size_m); } else{ ida = idy + (idx*size_n); } if(t_b == 0){ idb = idx + (idy*size_m); } else{ idb = idy + (idx*size_n); } c[idx + (idy*size_m)] = a[ida] - b[idb]; } } __global__ void Multi(int t_a, int t_b, int size_n, int size_m, float *a, float *b, float *c) { const uint idx = threadIdx.x + blockDim.x * blockIdx.x; const uint idy = threadIdx.y + blockDim.y * blockIdx.y; int ida = 0; int idb = 0; if(idx < size_m && idy < size_n){ if(t_a == 0){ ida = idx + (idy*size_m); } else{ ida = idy + (idx*size_n); } if(t_b == 0){ idb = idx + (idy*size_m); } else{ idb = idy + (idx*size_n); } c[idx + (idy*size_m)] = a[ida] * b[idb]; } } __global__ void RMulti(int t_a, int t_b, int size_n, int size_m, float b, float *a, float *c) { const uint idx = threadIdx.x + blockDim.x * blockIdx.x; const uint idy = threadIdx.y + blockDim.y * blockIdx.y; if(idx < size_m && idy < size_n){ c[idx + (idy*size_m)] = a[idx + (idy*size_m)] * b; } } __global__ void Divide(int t_a, int t_b, int size_n, int size_m, float *a, float *b, float *c) { const uint idx = threadIdx.x + blockDim.x * blockIdx.x; const uint idy = threadIdx.y + blockDim.y * blockIdx.y; int ida = 0; int idb = 0; if(idx < size_m && idy < size_n){ if(t_a == 0){ ida = idx + (idy*size_m); } else{ ida = idy + (idx*size_n); } if(t_b == 0){ idb = idx + (idy*size_m); } else{ idb = idy + (idx*size_n); } c[idx + (idy*size_m)] = a[ida] / b[idb]; } } __global__ void DOT(int t_a, int t_b, int sizean, int sizeam, int sizebm,float *a, float *b, float *c) { const uint tx = threadIdx.x + blockDim.x * blockIdx.x; const uint ty = threadIdx.y + blockDim.y * blockIdx.y; int ida = 0; int idb = 0; if(tx < sizebm && ty < sizean){ float Pvalue = 0; for (int k = 0; k < sizeam; ++k) { if(t_a == 0){ ida = ty * sizeam + k; } else{ ida = k * sizean + ty; } if(t_b == 0){ idb = k * sizebm + tx; } else{ idb = tx * sizeam + k; } float Aelement = a[ida]; float Belement = b[idb]; Pvalue += Aelement * Belement; } c[ty * sizebm + tx] = Pvalue; } } // dominante modificando la matriz original __global__ void Dom1(int size, float *a) { int ty = threadIdx.y + blockDim.y * blockIdx.y; float Pvalue = 0; if(ty < size){ for (int i = 0; i < size; ++i) { Pvalue += abs(a[ty * size + i]); } a[ty * size + ty] = Pvalue + 2000.0; } } // dominante guardando el resultado en otra matriz __global__ void Dom2(int size, float *a, float *b) { int ty = threadIdx.y + blockDim.y * blockIdx.y; float Pvalue = 0; if(ty < size){ for (int i = 0; i < size; ++i) { Pvalue += abs(a[ty * size + i]); b[ty * size + i] = a[ty * size + i]; } b[ty * size + ty] = Pvalue + 2000.0; } } __global__ void Transpose(int sizem, int sizen, const float *a, float *b) { const uint tx = threadIdx.x + blockDim.x * blockIdx.x; const uint ty = threadIdx.y + blockDim.y * blockIdx.y; if(tx < sizem && ty < sizen){ b[ty + (tx*sizen)] = a[tx + (ty*sizem)]; } } __global__ void neg(int size_n, int size_m, float * a, float *b) { const uint tx = threadIdx.x + blockDim.x * blockIdx.x; const uint ty = threadIdx.y + blockDim.y * blockIdx.y; if(tx < size_m && ty < size_n){ b[tx + (ty*size_m)] = a[tx + (ty*size_m)] * -1; } } __global__ void absolute(int size_n, int size_m, float *a, float *b) { const uint tx = threadIdx.x + blockDim.x * blockIdx.x; const uint ty = threadIdx.y + blockDim.y * blockIdx.y; if(tx < size_m && ty < size_n){ b[tx + (ty*size_m)] = abs(a[tx + (ty*size_m)]); } } // metodos para diagonales __global__ void Diag(int size, float *a, float *b) { const uint idy = threadIdx.y + blockDim.y * blockIdx.y; if(idy < size){ b[idy] = a[idy + (idy*size)]; } } __global__ void DiagFlat(int size, float *a, float *b) { const uint idy = threadIdx.y + blockDim.y * blockIdx.y; if(idy < size){ b[idy + (idy*size)] = a[idy]; } } // vec_dot sacado de https://www.nvidia.com/content/GTC-2010/pdfs/2131_GTC2010.pdf // matrixMul sacado de https://gist.github.com/wh5a/4313739 #define TILE_WIDTH 32 // Compute C = A * B __global__ void matrixMul(float * A, float * B, float * C, int numARows, int numAColumns, int numBRows, int numBColumns, int numCRows, int numCColumns, int t_a, int t_b) { //@@ Insert code to implement matrix multiplication here __shared__ float ds_M[TILE_WIDTH][TILE_WIDTH]; __shared__ float ds_N[TILE_WIDTH][TILE_WIDTH]; int bx = blockIdx.x, by = blockIdx.y, tx = threadIdx.x, ty = threadIdx.y, Row = by * TILE_WIDTH + ty, Col = bx * TILE_WIDTH + tx; float Pvalue = 0; int ida = 0; int idb = 0; for (int m = 0; m < (numAColumns-1)/TILE_WIDTH+1; ++m) { if (Row < numARows && m*TILE_WIDTH+tx < numAColumns){ if(t_a == 0){ ida = Row*numAColumns + (m*TILE_WIDTH+tx); } else{ ida = (m*TILE_WIDTH+tx)*numARows + Row; } ds_M[ty][tx] = A[ida]; } else{ ds_M[ty][tx] = 0; } if (Col < numBColumns && m*TILE_WIDTH+ty < numBRows){ if(t_b == 0){ idb = (m*TILE_WIDTH+ty)*numBColumns+Col; } else{ idb = Col*numBRows+(m*TILE_WIDTH+ty); } ds_N[ty][tx] = B[idb]; } else{ ds_N[ty][tx] = 0; } __syncthreads(); for (int k = 0; k < TILE_WIDTH; ++k) Pvalue += ds_M[ty][k] * ds_N[k][tx]; __syncthreads(); } if (Row < numCRows && Col < numCColumns) C[Row*numCColumns+Col] = Pvalue; } #define N 1024 // Compute C = A * B __global__ void vec_dot(float * a, float * b, float * c, int size, int t_a, int t_b) { c[0] = 0; __shared__ float temp[N]; int tx = threadIdx.x + blockDim.x * blockIdx.x; temp[threadIdx.x] = a[tx] * b[tx]; __syncthreads(); if(threadIdx.x == 0){ float sum = 0; for(int i = 0; i < N; i++){ if(tx + i < size){ sum += temp[i]; } } atomicAdd(c,sum); } } // matrix * vector __global__ void MatDotVec(float * A, float * B, float * C, int numARows, int numAColumns, int numBRows, int numBColumns, int numCRows, int numCColumns, int t_a, int t_b) { __shared__ float sub_mat[TILE_WIDTH][TILE_WIDTH]; __shared__ float sub_vec[TILE_WIDTH]; int by = blockIdx.y, ty = threadIdx.y, Row = by * TILE_WIDTH + ty; float Pvalue = 0; int ida = 0; for (int m = 0; m < (numAColumns-1)/TILE_WIDTH+1; ++m) { for (int tx = 0; tx <TILE_WIDTH; ++tx){ if (Row < numARows && m*TILE_WIDTH+tx < numAColumns){ if(t_a == 0){ ida = Row*numAColumns + (m*TILE_WIDTH+tx); } else{ ida = (m*TILE_WIDTH+tx)*numARows + Row; } sub_mat[ty][tx] = A[ida]; } else{ sub_mat[ty][tx] = 0; } } if(m*TILE_WIDTH+ty<numBRows){ sub_vec[ty] = B[m*TILE_WIDTH+ty]; } else{ sub_vec[ty]= 0; } __syncthreads(); for (int k = 0; k < TILE_WIDTH; ++k) Pvalue += sub_mat[ty][k] * sub_vec[k]; __syncthreads(); } if (Row < numCRows) C[Row] = Pvalue; } // Compute C = A * B #define N 1024 __global__ void cuadratic_sum(float * a, float * c, int size) { c[0] = 0; __shared__ float temp[N]; int tx = threadIdx.x + blockDim.x * blockIdx.x; temp[threadIdx.x] = a[tx] * a[tx]; __syncthreads(); if(threadIdx.x == 0){ float sum = 0; for(int i = 0; i < N; i++){ if(tx + i < size){ sum += temp[i]; } } atomicAdd(c,sum); } }
.text .file "kernel.hip" .globl _Z19__device_stub__SumaiiiiPfS_S_ # -- Begin function _Z19__device_stub__SumaiiiiPfS_S_ .p2align 4, 0x90 .type _Z19__device_stub__SumaiiiiPfS_S_,@function _Z19__device_stub__SumaiiiiPfS_S_: # @_Z19__device_stub__SumaiiiiPfS_S_ .cfi_startproc # %bb.0: subq $136, %rsp .cfi_def_cfa_offset 144 movl %edi, 12(%rsp) movl %esi, 8(%rsp) movl %edx, 4(%rsp) movl %ecx, (%rsp) movq %r8, 72(%rsp) movq %r9, 64(%rsp) leaq 12(%rsp), %rax movq %rax, 80(%rsp) leaq 8(%rsp), %rax movq %rax, 88(%rsp) leaq 4(%rsp), %rax movq %rax, 96(%rsp) movq %rsp, %rax movq %rax, 104(%rsp) leaq 72(%rsp), %rax movq %rax, 112(%rsp) leaq 64(%rsp), %rax movq %rax, 120(%rsp) leaq 144(%rsp), %rax movq %rax, 128(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z4SumaiiiiPfS_S_, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $152, %rsp .cfi_adjust_cfa_offset -152 retq .Lfunc_end0: .size _Z19__device_stub__SumaiiiiPfS_S_, .Lfunc_end0-_Z19__device_stub__SumaiiiiPfS_S_ .cfi_endproc # -- End function .globl _Z20__device_stub__RestaiiiiPfS_S_ # -- Begin function _Z20__device_stub__RestaiiiiPfS_S_ .p2align 4, 0x90 .type _Z20__device_stub__RestaiiiiPfS_S_,@function _Z20__device_stub__RestaiiiiPfS_S_: # @_Z20__device_stub__RestaiiiiPfS_S_ .cfi_startproc # %bb.0: subq $136, %rsp .cfi_def_cfa_offset 144 movl %edi, 12(%rsp) movl %esi, 8(%rsp) movl %edx, 4(%rsp) movl %ecx, (%rsp) movq %r8, 72(%rsp) movq %r9, 64(%rsp) leaq 12(%rsp), %rax movq %rax, 80(%rsp) leaq 8(%rsp), %rax movq %rax, 88(%rsp) leaq 4(%rsp), %rax movq %rax, 96(%rsp) movq %rsp, %rax movq %rax, 104(%rsp) leaq 72(%rsp), %rax movq %rax, 112(%rsp) leaq 64(%rsp), %rax movq %rax, 120(%rsp) leaq 144(%rsp), %rax movq %rax, 128(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z5RestaiiiiPfS_S_, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $152, %rsp .cfi_adjust_cfa_offset -152 retq .Lfunc_end1: .size _Z20__device_stub__RestaiiiiPfS_S_, .Lfunc_end1-_Z20__device_stub__RestaiiiiPfS_S_ .cfi_endproc # -- End function .globl _Z20__device_stub__MultiiiiiPfS_S_ # -- Begin function _Z20__device_stub__MultiiiiiPfS_S_ .p2align 4, 0x90 .type _Z20__device_stub__MultiiiiiPfS_S_,@function _Z20__device_stub__MultiiiiiPfS_S_: # @_Z20__device_stub__MultiiiiiPfS_S_ .cfi_startproc # %bb.0: subq $136, %rsp .cfi_def_cfa_offset 144 movl %edi, 12(%rsp) movl %esi, 8(%rsp) movl %edx, 4(%rsp) movl %ecx, (%rsp) movq %r8, 72(%rsp) movq %r9, 64(%rsp) leaq 12(%rsp), %rax movq %rax, 80(%rsp) leaq 8(%rsp), %rax movq %rax, 88(%rsp) leaq 4(%rsp), %rax movq %rax, 96(%rsp) movq %rsp, %rax movq %rax, 104(%rsp) leaq 72(%rsp), %rax movq %rax, 112(%rsp) leaq 64(%rsp), %rax movq %rax, 120(%rsp) leaq 144(%rsp), %rax movq %rax, 128(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z5MultiiiiiPfS_S_, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $152, %rsp .cfi_adjust_cfa_offset -152 retq .Lfunc_end2: .size _Z20__device_stub__MultiiiiiPfS_S_, .Lfunc_end2-_Z20__device_stub__MultiiiiiPfS_S_ .cfi_endproc # -- End function .globl _Z21__device_stub__RMultiiiiifPfS_ # -- Begin function _Z21__device_stub__RMultiiiiifPfS_ .p2align 4, 0x90 .type _Z21__device_stub__RMultiiiiifPfS_,@function _Z21__device_stub__RMultiiiiifPfS_: # @_Z21__device_stub__RMultiiiiifPfS_ .cfi_startproc # %bb.0: subq $152, %rsp .cfi_def_cfa_offset 160 movl %edi, 28(%rsp) movl %esi, 24(%rsp) movl %edx, 20(%rsp) movl %ecx, 16(%rsp) movss %xmm0, 12(%rsp) movq %r8, 88(%rsp) movq %r9, 80(%rsp) leaq 28(%rsp), %rax movq %rax, 96(%rsp) leaq 24(%rsp), %rax movq %rax, 104(%rsp) leaq 20(%rsp), %rax movq %rax, 112(%rsp) leaq 16(%rsp), %rax movq %rax, 120(%rsp) leaq 12(%rsp), %rax movq %rax, 128(%rsp) leaq 88(%rsp), %rax movq %rax, 136(%rsp) leaq 80(%rsp), %rax movq %rax, 144(%rsp) leaq 64(%rsp), %rdi leaq 48(%rsp), %rsi leaq 40(%rsp), %rdx leaq 32(%rsp), %rcx callq __hipPopCallConfiguration movq 64(%rsp), %rsi movl 72(%rsp), %edx movq 48(%rsp), %rcx movl 56(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z6RMultiiiiifPfS_, %edi pushq 32(%rsp) .cfi_adjust_cfa_offset 8 pushq 48(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $168, %rsp .cfi_adjust_cfa_offset -168 retq .Lfunc_end3: .size _Z21__device_stub__RMultiiiiifPfS_, .Lfunc_end3-_Z21__device_stub__RMultiiiiifPfS_ .cfi_endproc # -- End function .globl _Z21__device_stub__DivideiiiiPfS_S_ # -- Begin function _Z21__device_stub__DivideiiiiPfS_S_ .p2align 4, 0x90 .type _Z21__device_stub__DivideiiiiPfS_S_,@function _Z21__device_stub__DivideiiiiPfS_S_: # @_Z21__device_stub__DivideiiiiPfS_S_ .cfi_startproc # %bb.0: subq $136, %rsp .cfi_def_cfa_offset 144 movl %edi, 12(%rsp) movl %esi, 8(%rsp) movl %edx, 4(%rsp) movl %ecx, (%rsp) movq %r8, 72(%rsp) movq %r9, 64(%rsp) leaq 12(%rsp), %rax movq %rax, 80(%rsp) leaq 8(%rsp), %rax movq %rax, 88(%rsp) leaq 4(%rsp), %rax movq %rax, 96(%rsp) movq %rsp, %rax movq %rax, 104(%rsp) leaq 72(%rsp), %rax movq %rax, 112(%rsp) leaq 64(%rsp), %rax movq %rax, 120(%rsp) leaq 144(%rsp), %rax movq %rax, 128(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z6DivideiiiiPfS_S_, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $152, %rsp .cfi_adjust_cfa_offset -152 retq .Lfunc_end4: .size _Z21__device_stub__DivideiiiiPfS_S_, .Lfunc_end4-_Z21__device_stub__DivideiiiiPfS_S_ .cfi_endproc # -- End function .globl _Z18__device_stub__DOTiiiiiPfS_S_ # -- Begin function _Z18__device_stub__DOTiiiiiPfS_S_ .p2align 4, 0x90 .type _Z18__device_stub__DOTiiiiiPfS_S_,@function _Z18__device_stub__DOTiiiiiPfS_S_: # @_Z18__device_stub__DOTiiiiiPfS_S_ .cfi_startproc # %bb.0: subq $152, %rsp .cfi_def_cfa_offset 160 movl %edi, 20(%rsp) movl %esi, 16(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) movl %r8d, 4(%rsp) movq %r9, 72(%rsp) leaq 20(%rsp), %rax movq %rax, 80(%rsp) leaq 16(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 8(%rsp), %rax movq %rax, 104(%rsp) leaq 4(%rsp), %rax movq %rax, 112(%rsp) leaq 72(%rsp), %rax movq %rax, 120(%rsp) leaq 160(%rsp), %rax movq %rax, 128(%rsp) leaq 168(%rsp), %rax movq %rax, 136(%rsp) leaq 56(%rsp), %rdi leaq 40(%rsp), %rsi leaq 32(%rsp), %rdx leaq 24(%rsp), %rcx callq __hipPopCallConfiguration movq 56(%rsp), %rsi movl 64(%rsp), %edx movq 40(%rsp), %rcx movl 48(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z3DOTiiiiiPfS_S_, %edi pushq 24(%rsp) .cfi_adjust_cfa_offset 8 pushq 40(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $168, %rsp .cfi_adjust_cfa_offset -168 retq .Lfunc_end5: .size _Z18__device_stub__DOTiiiiiPfS_S_, .Lfunc_end5-_Z18__device_stub__DOTiiiiiPfS_S_ .cfi_endproc # -- End function .globl _Z19__device_stub__Dom1iPf # -- Begin function _Z19__device_stub__Dom1iPf .p2align 4, 0x90 .type _Z19__device_stub__Dom1iPf,@function _Z19__device_stub__Dom1iPf: # @_Z19__device_stub__Dom1iPf .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movl %edi, 4(%rsp) movq %rsi, 56(%rsp) leaq 4(%rsp), %rax movq %rax, 64(%rsp) leaq 56(%rsp), %rax movq %rax, 72(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z4Dom1iPf, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end6: .size _Z19__device_stub__Dom1iPf, .Lfunc_end6-_Z19__device_stub__Dom1iPf .cfi_endproc # -- End function .globl _Z19__device_stub__Dom2iPfS_ # -- Begin function _Z19__device_stub__Dom2iPfS_ .p2align 4, 0x90 .type _Z19__device_stub__Dom2iPfS_,@function _Z19__device_stub__Dom2iPfS_: # @_Z19__device_stub__Dom2iPfS_ .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movl %edi, 12(%rsp) movq %rsi, 72(%rsp) movq %rdx, 64(%rsp) leaq 12(%rsp), %rax movq %rax, 80(%rsp) leaq 72(%rsp), %rax movq %rax, 88(%rsp) leaq 64(%rsp), %rax movq %rax, 96(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z4Dom2iPfS_, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end7: .size _Z19__device_stub__Dom2iPfS_, .Lfunc_end7-_Z19__device_stub__Dom2iPfS_ .cfi_endproc # -- End function .globl _Z24__device_stub__TransposeiiPKfPf # -- Begin function _Z24__device_stub__TransposeiiPKfPf .p2align 4, 0x90 .type _Z24__device_stub__TransposeiiPKfPf,@function _Z24__device_stub__TransposeiiPKfPf: # @_Z24__device_stub__TransposeiiPKfPf .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movl %edi, 12(%rsp) movl %esi, 8(%rsp) movq %rdx, 72(%rsp) movq %rcx, 64(%rsp) leaq 12(%rsp), %rax movq %rax, 80(%rsp) leaq 8(%rsp), %rax movq %rax, 88(%rsp) leaq 72(%rsp), %rax movq %rax, 96(%rsp) leaq 64(%rsp), %rax movq %rax, 104(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z9TransposeiiPKfPf, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end8: .size _Z24__device_stub__TransposeiiPKfPf, .Lfunc_end8-_Z24__device_stub__TransposeiiPKfPf .cfi_endproc # -- End function .globl _Z18__device_stub__negiiPfS_ # -- Begin function _Z18__device_stub__negiiPfS_ .p2align 4, 0x90 .type _Z18__device_stub__negiiPfS_,@function _Z18__device_stub__negiiPfS_: # @_Z18__device_stub__negiiPfS_ .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movl %edi, 12(%rsp) movl %esi, 8(%rsp) movq %rdx, 72(%rsp) movq %rcx, 64(%rsp) leaq 12(%rsp), %rax movq %rax, 80(%rsp) leaq 8(%rsp), %rax movq %rax, 88(%rsp) leaq 72(%rsp), %rax movq %rax, 96(%rsp) leaq 64(%rsp), %rax movq %rax, 104(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z3negiiPfS_, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end9: .size _Z18__device_stub__negiiPfS_, .Lfunc_end9-_Z18__device_stub__negiiPfS_ .cfi_endproc # -- End function .globl _Z23__device_stub__absoluteiiPfS_ # -- Begin function _Z23__device_stub__absoluteiiPfS_ .p2align 4, 0x90 .type _Z23__device_stub__absoluteiiPfS_,@function _Z23__device_stub__absoluteiiPfS_: # @_Z23__device_stub__absoluteiiPfS_ .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movl %edi, 12(%rsp) movl %esi, 8(%rsp) movq %rdx, 72(%rsp) movq %rcx, 64(%rsp) leaq 12(%rsp), %rax movq %rax, 80(%rsp) leaq 8(%rsp), %rax movq %rax, 88(%rsp) leaq 72(%rsp), %rax movq %rax, 96(%rsp) leaq 64(%rsp), %rax movq %rax, 104(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z8absoluteiiPfS_, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end10: .size _Z23__device_stub__absoluteiiPfS_, .Lfunc_end10-_Z23__device_stub__absoluteiiPfS_ .cfi_endproc # -- End function .globl _Z19__device_stub__DiagiPfS_ # -- Begin function _Z19__device_stub__DiagiPfS_ .p2align 4, 0x90 .type _Z19__device_stub__DiagiPfS_,@function _Z19__device_stub__DiagiPfS_: # @_Z19__device_stub__DiagiPfS_ .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movl %edi, 12(%rsp) movq %rsi, 72(%rsp) movq %rdx, 64(%rsp) leaq 12(%rsp), %rax movq %rax, 80(%rsp) leaq 72(%rsp), %rax movq %rax, 88(%rsp) leaq 64(%rsp), %rax movq %rax, 96(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z4DiagiPfS_, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end11: .size _Z19__device_stub__DiagiPfS_, .Lfunc_end11-_Z19__device_stub__DiagiPfS_ .cfi_endproc # -- End function .globl _Z23__device_stub__DiagFlatiPfS_ # -- Begin function _Z23__device_stub__DiagFlatiPfS_ .p2align 4, 0x90 .type _Z23__device_stub__DiagFlatiPfS_,@function _Z23__device_stub__DiagFlatiPfS_: # @_Z23__device_stub__DiagFlatiPfS_ .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movl %edi, 12(%rsp) movq %rsi, 72(%rsp) movq %rdx, 64(%rsp) leaq 12(%rsp), %rax movq %rax, 80(%rsp) leaq 72(%rsp), %rax movq %rax, 88(%rsp) leaq 64(%rsp), %rax movq %rax, 96(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z8DiagFlatiPfS_, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end12: .size _Z23__device_stub__DiagFlatiPfS_, .Lfunc_end12-_Z23__device_stub__DiagFlatiPfS_ .cfi_endproc # -- End function .globl _Z24__device_stub__matrixMulPfS_S_iiiiiiii # -- Begin function _Z24__device_stub__matrixMulPfS_S_iiiiiiii .p2align 4, 0x90 .type _Z24__device_stub__matrixMulPfS_S_iiiiiiii,@function _Z24__device_stub__matrixMulPfS_S_iiiiiiii: # @_Z24__device_stub__matrixMulPfS_S_iiiiiiii .cfi_startproc # %bb.0: subq $184, %rsp .cfi_def_cfa_offset 192 movq %rdi, 88(%rsp) movq %rsi, 80(%rsp) movq %rdx, 72(%rsp) movl %ecx, 20(%rsp) movl %r8d, 16(%rsp) movl %r9d, 12(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 72(%rsp), %rax movq %rax, 112(%rsp) leaq 20(%rsp), %rax movq %rax, 120(%rsp) leaq 16(%rsp), %rax movq %rax, 128(%rsp) leaq 12(%rsp), %rax movq %rax, 136(%rsp) leaq 192(%rsp), %rax movq %rax, 144(%rsp) leaq 200(%rsp), %rax movq %rax, 152(%rsp) leaq 208(%rsp), %rax movq %rax, 160(%rsp) leaq 216(%rsp), %rax movq %rax, 168(%rsp) leaq 224(%rsp), %rax movq %rax, 176(%rsp) leaq 56(%rsp), %rdi leaq 40(%rsp), %rsi leaq 32(%rsp), %rdx leaq 24(%rsp), %rcx callq __hipPopCallConfiguration movq 56(%rsp), %rsi movl 64(%rsp), %edx movq 40(%rsp), %rcx movl 48(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z9matrixMulPfS_S_iiiiiiii, %edi pushq 24(%rsp) .cfi_adjust_cfa_offset 8 pushq 40(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $200, %rsp .cfi_adjust_cfa_offset -200 retq .Lfunc_end13: .size _Z24__device_stub__matrixMulPfS_S_iiiiiiii, .Lfunc_end13-_Z24__device_stub__matrixMulPfS_S_iiiiiiii .cfi_endproc # -- End function .globl _Z22__device_stub__vec_dotPfS_S_iii # -- Begin function _Z22__device_stub__vec_dotPfS_S_iii .p2align 4, 0x90 .type _Z22__device_stub__vec_dotPfS_S_iii,@function _Z22__device_stub__vec_dotPfS_S_iii: # @_Z22__device_stub__vec_dotPfS_S_iii .cfi_startproc # %bb.0: subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 88(%rsp) movq %rsi, 80(%rsp) movq %rdx, 72(%rsp) movl %ecx, 20(%rsp) movl %r8d, 16(%rsp) movl %r9d, 12(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 72(%rsp), %rax movq %rax, 112(%rsp) leaq 20(%rsp), %rax movq %rax, 120(%rsp) leaq 16(%rsp), %rax movq %rax, 128(%rsp) leaq 12(%rsp), %rax movq %rax, 136(%rsp) leaq 56(%rsp), %rdi leaq 40(%rsp), %rsi leaq 32(%rsp), %rdx leaq 24(%rsp), %rcx callq __hipPopCallConfiguration movq 56(%rsp), %rsi movl 64(%rsp), %edx movq 40(%rsp), %rcx movl 48(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z7vec_dotPfS_S_iii, %edi pushq 24(%rsp) .cfi_adjust_cfa_offset 8 pushq 40(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $168, %rsp .cfi_adjust_cfa_offset -168 retq .Lfunc_end14: .size _Z22__device_stub__vec_dotPfS_S_iii, .Lfunc_end14-_Z22__device_stub__vec_dotPfS_S_iii .cfi_endproc # -- End function .globl _Z24__device_stub__MatDotVecPfS_S_iiiiiiii # -- Begin function _Z24__device_stub__MatDotVecPfS_S_iiiiiiii .p2align 4, 0x90 .type _Z24__device_stub__MatDotVecPfS_S_iiiiiiii,@function _Z24__device_stub__MatDotVecPfS_S_iiiiiiii: # @_Z24__device_stub__MatDotVecPfS_S_iiiiiiii .cfi_startproc # %bb.0: subq $184, %rsp .cfi_def_cfa_offset 192 movq %rdi, 88(%rsp) movq %rsi, 80(%rsp) movq %rdx, 72(%rsp) movl %ecx, 20(%rsp) movl %r8d, 16(%rsp) movl %r9d, 12(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 72(%rsp), %rax movq %rax, 112(%rsp) leaq 20(%rsp), %rax movq %rax, 120(%rsp) leaq 16(%rsp), %rax movq %rax, 128(%rsp) leaq 12(%rsp), %rax movq %rax, 136(%rsp) leaq 192(%rsp), %rax movq %rax, 144(%rsp) leaq 200(%rsp), %rax movq %rax, 152(%rsp) leaq 208(%rsp), %rax movq %rax, 160(%rsp) leaq 216(%rsp), %rax movq %rax, 168(%rsp) leaq 224(%rsp), %rax movq %rax, 176(%rsp) leaq 56(%rsp), %rdi leaq 40(%rsp), %rsi leaq 32(%rsp), %rdx leaq 24(%rsp), %rcx callq __hipPopCallConfiguration movq 56(%rsp), %rsi movl 64(%rsp), %edx movq 40(%rsp), %rcx movl 48(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z9MatDotVecPfS_S_iiiiiiii, %edi pushq 24(%rsp) .cfi_adjust_cfa_offset 8 pushq 40(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $200, %rsp .cfi_adjust_cfa_offset -200 retq .Lfunc_end15: .size _Z24__device_stub__MatDotVecPfS_S_iiiiiiii, .Lfunc_end15-_Z24__device_stub__MatDotVecPfS_S_iiiiiiii .cfi_endproc # -- End function .globl _Z28__device_stub__cuadratic_sumPfS_i # -- Begin function _Z28__device_stub__cuadratic_sumPfS_i .p2align 4, 0x90 .type _Z28__device_stub__cuadratic_sumPfS_i,@function _Z28__device_stub__cuadratic_sumPfS_i: # @_Z28__device_stub__cuadratic_sumPfS_i .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 12(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z13cuadratic_sumPfS_i, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end16: .size _Z28__device_stub__cuadratic_sumPfS_i, .Lfunc_end16-_Z28__device_stub__cuadratic_sumPfS_i .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB17_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB17_2: movq __hip_gpubin_handle(%rip), %rbx xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z4SumaiiiiPfS_S_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z5RestaiiiiPfS_S_, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z5MultiiiiiPfS_S_, %esi movl $.L__unnamed_3, %edx movl $.L__unnamed_3, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z6RMultiiiiifPfS_, %esi movl $.L__unnamed_4, %edx movl $.L__unnamed_4, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z6DivideiiiiPfS_S_, %esi movl $.L__unnamed_5, %edx movl $.L__unnamed_5, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z3DOTiiiiiPfS_S_, %esi movl $.L__unnamed_6, %edx movl $.L__unnamed_6, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z4Dom1iPf, %esi movl $.L__unnamed_7, %edx movl $.L__unnamed_7, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z4Dom2iPfS_, %esi movl $.L__unnamed_8, %edx movl $.L__unnamed_8, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z9TransposeiiPKfPf, %esi movl $.L__unnamed_9, %edx movl $.L__unnamed_9, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z3negiiPfS_, %esi movl $.L__unnamed_10, %edx movl $.L__unnamed_10, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z8absoluteiiPfS_, %esi movl $.L__unnamed_11, %edx movl $.L__unnamed_11, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z4DiagiPfS_, %esi movl $.L__unnamed_12, %edx movl $.L__unnamed_12, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z8DiagFlatiPfS_, %esi movl $.L__unnamed_13, %edx movl $.L__unnamed_13, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z9matrixMulPfS_S_iiiiiiii, %esi movl $.L__unnamed_14, %edx movl $.L__unnamed_14, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z7vec_dotPfS_S_iii, %esi movl $.L__unnamed_15, %edx movl $.L__unnamed_15, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z9MatDotVecPfS_S_iiiiiiii, %esi movl $.L__unnamed_16, %edx movl $.L__unnamed_16, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z13cuadratic_sumPfS_i, %esi movl $.L__unnamed_17, %edx movl $.L__unnamed_17, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end17: .size __hip_module_ctor, .Lfunc_end17-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB18_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB18_2: retq .Lfunc_end18: .size __hip_module_dtor, .Lfunc_end18-__hip_module_dtor .cfi_endproc # -- End function .type _Z4SumaiiiiPfS_S_,@object # @_Z4SumaiiiiPfS_S_ .section .rodata,"a",@progbits .globl _Z4SumaiiiiPfS_S_ .p2align 3, 0x0 _Z4SumaiiiiPfS_S_: .quad _Z19__device_stub__SumaiiiiPfS_S_ .size _Z4SumaiiiiPfS_S_, 8 .type _Z5RestaiiiiPfS_S_,@object # @_Z5RestaiiiiPfS_S_ .globl _Z5RestaiiiiPfS_S_ .p2align 3, 0x0 _Z5RestaiiiiPfS_S_: .quad _Z20__device_stub__RestaiiiiPfS_S_ .size _Z5RestaiiiiPfS_S_, 8 .type _Z5MultiiiiiPfS_S_,@object # @_Z5MultiiiiiPfS_S_ .globl _Z5MultiiiiiPfS_S_ .p2align 3, 0x0 _Z5MultiiiiiPfS_S_: .quad _Z20__device_stub__MultiiiiiPfS_S_ .size _Z5MultiiiiiPfS_S_, 8 .type _Z6RMultiiiiifPfS_,@object # @_Z6RMultiiiiifPfS_ .globl _Z6RMultiiiiifPfS_ .p2align 3, 0x0 _Z6RMultiiiiifPfS_: .quad _Z21__device_stub__RMultiiiiifPfS_ .size _Z6RMultiiiiifPfS_, 8 .type _Z6DivideiiiiPfS_S_,@object # @_Z6DivideiiiiPfS_S_ .globl _Z6DivideiiiiPfS_S_ .p2align 3, 0x0 _Z6DivideiiiiPfS_S_: .quad _Z21__device_stub__DivideiiiiPfS_S_ .size _Z6DivideiiiiPfS_S_, 8 .type _Z3DOTiiiiiPfS_S_,@object # @_Z3DOTiiiiiPfS_S_ .globl _Z3DOTiiiiiPfS_S_ .p2align 3, 0x0 _Z3DOTiiiiiPfS_S_: .quad _Z18__device_stub__DOTiiiiiPfS_S_ .size _Z3DOTiiiiiPfS_S_, 8 .type _Z4Dom1iPf,@object # @_Z4Dom1iPf .globl _Z4Dom1iPf .p2align 3, 0x0 _Z4Dom1iPf: .quad _Z19__device_stub__Dom1iPf .size _Z4Dom1iPf, 8 .type _Z4Dom2iPfS_,@object # @_Z4Dom2iPfS_ .globl _Z4Dom2iPfS_ .p2align 3, 0x0 _Z4Dom2iPfS_: .quad _Z19__device_stub__Dom2iPfS_ .size _Z4Dom2iPfS_, 8 .type _Z9TransposeiiPKfPf,@object # @_Z9TransposeiiPKfPf .globl _Z9TransposeiiPKfPf .p2align 3, 0x0 _Z9TransposeiiPKfPf: .quad _Z24__device_stub__TransposeiiPKfPf .size _Z9TransposeiiPKfPf, 8 .type _Z3negiiPfS_,@object # @_Z3negiiPfS_ .globl _Z3negiiPfS_ .p2align 3, 0x0 _Z3negiiPfS_: .quad _Z18__device_stub__negiiPfS_ .size _Z3negiiPfS_, 8 .type _Z8absoluteiiPfS_,@object # @_Z8absoluteiiPfS_ .globl _Z8absoluteiiPfS_ .p2align 3, 0x0 _Z8absoluteiiPfS_: .quad _Z23__device_stub__absoluteiiPfS_ .size _Z8absoluteiiPfS_, 8 .type _Z4DiagiPfS_,@object # @_Z4DiagiPfS_ .globl _Z4DiagiPfS_ .p2align 3, 0x0 _Z4DiagiPfS_: .quad _Z19__device_stub__DiagiPfS_ .size _Z4DiagiPfS_, 8 .type _Z8DiagFlatiPfS_,@object # @_Z8DiagFlatiPfS_ .globl _Z8DiagFlatiPfS_ .p2align 3, 0x0 _Z8DiagFlatiPfS_: .quad _Z23__device_stub__DiagFlatiPfS_ .size _Z8DiagFlatiPfS_, 8 .type _Z9matrixMulPfS_S_iiiiiiii,@object # @_Z9matrixMulPfS_S_iiiiiiii .globl _Z9matrixMulPfS_S_iiiiiiii .p2align 3, 0x0 _Z9matrixMulPfS_S_iiiiiiii: .quad _Z24__device_stub__matrixMulPfS_S_iiiiiiii .size _Z9matrixMulPfS_S_iiiiiiii, 8 .type _Z7vec_dotPfS_S_iii,@object # @_Z7vec_dotPfS_S_iii .globl _Z7vec_dotPfS_S_iii .p2align 3, 0x0 _Z7vec_dotPfS_S_iii: .quad _Z22__device_stub__vec_dotPfS_S_iii .size _Z7vec_dotPfS_S_iii, 8 .type _Z9MatDotVecPfS_S_iiiiiiii,@object # @_Z9MatDotVecPfS_S_iiiiiiii .globl _Z9MatDotVecPfS_S_iiiiiiii .p2align 3, 0x0 _Z9MatDotVecPfS_S_iiiiiiii: .quad _Z24__device_stub__MatDotVecPfS_S_iiiiiiii .size _Z9MatDotVecPfS_S_iiiiiiii, 8 .type _Z13cuadratic_sumPfS_i,@object # @_Z13cuadratic_sumPfS_i .globl _Z13cuadratic_sumPfS_i .p2align 3, 0x0 _Z13cuadratic_sumPfS_i: .quad _Z28__device_stub__cuadratic_sumPfS_i .size _Z13cuadratic_sumPfS_i, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z4SumaiiiiPfS_S_" .size .L__unnamed_1, 18 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z5RestaiiiiPfS_S_" .size .L__unnamed_2, 19 .type .L__unnamed_3,@object # @2 .L__unnamed_3: .asciz "_Z5MultiiiiiPfS_S_" .size .L__unnamed_3, 19 .type .L__unnamed_4,@object # @3 .L__unnamed_4: .asciz "_Z6RMultiiiiifPfS_" .size .L__unnamed_4, 19 .type .L__unnamed_5,@object # @4 .L__unnamed_5: .asciz "_Z6DivideiiiiPfS_S_" .size .L__unnamed_5, 20 .type .L__unnamed_6,@object # @5 .L__unnamed_6: .asciz "_Z3DOTiiiiiPfS_S_" .size .L__unnamed_6, 18 .type .L__unnamed_7,@object # @6 .L__unnamed_7: .asciz "_Z4Dom1iPf" .size .L__unnamed_7, 11 .type .L__unnamed_8,@object # @7 .L__unnamed_8: .asciz "_Z4Dom2iPfS_" .size .L__unnamed_8, 13 .type .L__unnamed_9,@object # @8 .L__unnamed_9: .asciz "_Z9TransposeiiPKfPf" .size .L__unnamed_9, 20 .type .L__unnamed_10,@object # @9 .L__unnamed_10: .asciz "_Z3negiiPfS_" .size .L__unnamed_10, 13 .type .L__unnamed_11,@object # @10 .L__unnamed_11: .asciz "_Z8absoluteiiPfS_" .size .L__unnamed_11, 18 .type .L__unnamed_12,@object # @11 .L__unnamed_12: .asciz "_Z4DiagiPfS_" .size .L__unnamed_12, 13 .type .L__unnamed_13,@object # @12 .L__unnamed_13: .asciz "_Z8DiagFlatiPfS_" .size .L__unnamed_13, 17 .type .L__unnamed_14,@object # @13 .L__unnamed_14: .asciz "_Z9matrixMulPfS_S_iiiiiiii" .size .L__unnamed_14, 27 .type .L__unnamed_15,@object # @14 .L__unnamed_15: .asciz "_Z7vec_dotPfS_S_iii" .size .L__unnamed_15, 20 .type .L__unnamed_16,@object # @15 .L__unnamed_16: .asciz "_Z9MatDotVecPfS_S_iiiiiiii" .size .L__unnamed_16, 27 .type .L__unnamed_17,@object # @16 .L__unnamed_17: .asciz "_Z13cuadratic_sumPfS_i" .size .L__unnamed_17, 23 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z19__device_stub__SumaiiiiPfS_S_ .addrsig_sym _Z20__device_stub__RestaiiiiPfS_S_ .addrsig_sym _Z20__device_stub__MultiiiiiPfS_S_ .addrsig_sym _Z21__device_stub__RMultiiiiifPfS_ .addrsig_sym _Z21__device_stub__DivideiiiiPfS_S_ .addrsig_sym _Z18__device_stub__DOTiiiiiPfS_S_ .addrsig_sym _Z19__device_stub__Dom1iPf .addrsig_sym _Z19__device_stub__Dom2iPfS_ .addrsig_sym _Z24__device_stub__TransposeiiPKfPf .addrsig_sym _Z18__device_stub__negiiPfS_ .addrsig_sym _Z23__device_stub__absoluteiiPfS_ .addrsig_sym _Z19__device_stub__DiagiPfS_ .addrsig_sym _Z23__device_stub__DiagFlatiPfS_ .addrsig_sym _Z24__device_stub__matrixMulPfS_S_iiiiiiii .addrsig_sym _Z22__device_stub__vec_dotPfS_S_iii .addrsig_sym _Z24__device_stub__MatDotVecPfS_S_iiiiiiii .addrsig_sym _Z28__device_stub__cuadratic_sumPfS_i .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z4SumaiiiiPfS_S_ .addrsig_sym _Z5RestaiiiiPfS_S_ .addrsig_sym _Z5MultiiiiiPfS_S_ .addrsig_sym _Z6RMultiiiiifPfS_ .addrsig_sym _Z6DivideiiiiPfS_S_ .addrsig_sym _Z3DOTiiiiiPfS_S_ .addrsig_sym _Z4Dom1iPf .addrsig_sym _Z4Dom2iPfS_ .addrsig_sym _Z9TransposeiiPKfPf .addrsig_sym _Z3negiiPfS_ .addrsig_sym _Z8absoluteiiPfS_ .addrsig_sym _Z4DiagiPfS_ .addrsig_sym _Z8DiagFlatiPfS_ .addrsig_sym _Z9matrixMulPfS_S_iiiiiiii .addrsig_sym _Z7vec_dotPfS_S_iii .addrsig_sym _Z9MatDotVecPfS_S_iiiiiiii .addrsig_sym _Z13cuadratic_sumPfS_i .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include <iostream> #include <cuda_runtime_api.h> #include <stdlib.h> using namespace std; #define LEN 100000000 __global__ void add_vec(int *v1, int *v2, int *res, size_t l) { // cudaError_t status; int i = blockIdx.x * blockDim.x + threadIdx.x; int step = gridDim.x * blockDim.x; for (; i < l; i+= step) { res[i] = v1[i] + v2[i]; } } int main() { int *v1_cpu, *v2_cpu, *res_cpu; v1_cpu = (int*)calloc(LEN, sizeof(int)); v2_cpu = (int*)calloc(LEN, sizeof(int)); for (int i = 0; i < LEN; i++) { v1_cpu[i] = i; v2_cpu[i] = i * 40 + 2; } cudaError_t status; int *v1_gpu, *v2_gpu, *res_gpu; status = cudaMalloc((void**)&v1_gpu, sizeof(int) * LEN); if (status != cudaSuccess) { cout << cudaGetErrorString(status) << endl; } status = cudaMalloc((void**)&v2_gpu, sizeof(int) * LEN); if (status != cudaSuccess) { cout << cudaGetErrorString(status) << endl; } status = cudaMalloc((void**)&res_gpu, sizeof(int) * LEN); if (status != cudaSuccess) { cout << cudaGetErrorString(status) << endl; } status = cudaMemcpy(v1_gpu, v1_cpu, sizeof(int) * LEN, cudaMemcpyHostToDevice); if (status != cudaSuccess) { cout << cudaGetErrorString(status) << endl; } status = cudaMemcpy(v2_gpu, v2_cpu, sizeof(int) * LEN, cudaMemcpyHostToDevice); if (status != cudaSuccess) { cout << cudaGetErrorString(status) << endl; } free(v1_cpu); free(v2_cpu); add_vec<<<2, 32, 0>>>(v1_gpu, v2_gpu, res_gpu, LEN); res_cpu = (int*)calloc(sizeof(int), LEN); status = cudaMemcpy(res_cpu, res_gpu, sizeof(int) * LEN, cudaMemcpyDeviceToHost); if (status != cudaSuccess) { cout << cudaGetErrorString(status) << endl; } status = cudaFree(v1_gpu); if (status != cudaSuccess) { cout << cudaGetErrorString(status) << endl; } status = cudaFree(v2_gpu); if (status != cudaSuccess) { cout << cudaGetErrorString(status) << endl; } status = cudaFree(res_gpu); if (status != cudaSuccess) { cout << cudaGetErrorString(status) << endl; } free(res_cpu); return 0; }
code for sm_80 Function : _Z7add_vecPiS_S_m .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */ /* 0x000e280000002500 */ /*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */ /* 0x000e240000002100 */ /*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */ /* 0x001fca00078e0203 */ /*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */ /* 0x000fe40003f06070 */ /*0050*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */ /* 0x000fc80000011400 */ /*0060*/ ISETP.GE.U32.AND.EX P0, PT, R2, c[0x0][0x17c], PT, P0 ; /* 0x00005f0002007a0c */ /* 0x000fda0003f06100 */ /*0070*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*0080*/ IMAD.MOV.U32 R11, RZ, RZ, R2 ; /* 0x000000ffff0b7224 */ /* 0x000fe200078e0002 */ /*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fe20000000a00 */ /*00a0*/ IMAD.MOV.U32 R8, RZ, RZ, R0 ; /* 0x000000ffff087224 */ /* 0x000fc800078e0000 */ /*00b0*/ IMAD.SHL.U32 R6, R8.reuse, 0x4, RZ ; /* 0x0000000408067824 */ /* 0x041fe200078e00ff */ /*00c0*/ SHF.L.U64.HI R7, R8, 0x2, R11 ; /* 0x0000000208077819 */ /* 0x000fc8000001020b */ /*00d0*/ IADD3 R4, P1, R6.reuse, c[0x0][0x160], RZ ; /* 0x0000580006047a10 */ /* 0x040fe40007f3e0ff */ /*00e0*/ IADD3 R2, P0, R6, c[0x0][0x168], RZ ; /* 0x00005a0006027a10 */ /* 0x000fe40007f1e0ff */ /*00f0*/ IADD3.X R5, R7.reuse, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590007057a10 */ /* 0x040fe40000ffe4ff */ /*0100*/ IADD3.X R3, R7, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0007037a10 */ /* 0x000fc800007fe4ff */ /*0110*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */ /* 0x000ea8000c1e1900 */ /*0120*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */ /* 0x000ea2000c1e1900 */ /*0130*/ IADD3 R6, P0, R6, c[0x0][0x170], RZ ; /* 0x00005c0006067a10 */ /* 0x000fe20007f1e0ff */ /*0140*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff0b7624 */ /* 0x000fc600078e00ff */ /*0150*/ IADD3.X R7, R7, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0007077a10 */ /* 0x000fe200007fe4ff */ /*0160*/ IMAD R8, R11, c[0x0][0x0], R0 ; /* 0x000000000b087a24 */ /* 0x000fca00078e0200 */ /*0170*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0c */ /* 0x000fe40003f06070 */ /*0180*/ SHF.R.S32.HI R11, RZ, 0x1f, R8 ; /* 0x0000001fff0b7819 */ /* 0x000fc80000011408 */ /*0190*/ ISETP.GE.U32.AND.EX P0, PT, R11, c[0x0][0x17c], PT, P0 ; /* 0x00005f000b007a0c */ /* 0x000fe20003f06100 */ /*01a0*/ IMAD.MOV.U32 R0, RZ, RZ, R8 ; /* 0x000000ffff007224 */ /* 0x000fe400078e0008 */ /*01b0*/ IMAD.IADD R9, R2, 0x1, R5 ; /* 0x0000000102097824 */ /* 0x004fca00078e0205 */ /*01c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */ /* 0x0001ea000c101904 */ /*01d0*/ @!P0 BRA 0xb0 ; /* 0xfffffed000008947 */ /* 0x000fea000383ffff */ /*01e0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0200*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0210*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0220*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0230*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0240*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0250*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0260*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0270*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include <iostream> #include <cuda_runtime_api.h> #include <stdlib.h> using namespace std; #define LEN 100000000 __global__ void add_vec(int *v1, int *v2, int *res, size_t l) { // cudaError_t status; int i = blockIdx.x * blockDim.x + threadIdx.x; int step = gridDim.x * blockDim.x; for (; i < l; i+= step) { res[i] = v1[i] + v2[i]; } } int main() { int *v1_cpu, *v2_cpu, *res_cpu; v1_cpu = (int*)calloc(LEN, sizeof(int)); v2_cpu = (int*)calloc(LEN, sizeof(int)); for (int i = 0; i < LEN; i++) { v1_cpu[i] = i; v2_cpu[i] = i * 40 + 2; } cudaError_t status; int *v1_gpu, *v2_gpu, *res_gpu; status = cudaMalloc((void**)&v1_gpu, sizeof(int) * LEN); if (status != cudaSuccess) { cout << cudaGetErrorString(status) << endl; } status = cudaMalloc((void**)&v2_gpu, sizeof(int) * LEN); if (status != cudaSuccess) { cout << cudaGetErrorString(status) << endl; } status = cudaMalloc((void**)&res_gpu, sizeof(int) * LEN); if (status != cudaSuccess) { cout << cudaGetErrorString(status) << endl; } status = cudaMemcpy(v1_gpu, v1_cpu, sizeof(int) * LEN, cudaMemcpyHostToDevice); if (status != cudaSuccess) { cout << cudaGetErrorString(status) << endl; } status = cudaMemcpy(v2_gpu, v2_cpu, sizeof(int) * LEN, cudaMemcpyHostToDevice); if (status != cudaSuccess) { cout << cudaGetErrorString(status) << endl; } free(v1_cpu); free(v2_cpu); add_vec<<<2, 32, 0>>>(v1_gpu, v2_gpu, res_gpu, LEN); res_cpu = (int*)calloc(sizeof(int), LEN); status = cudaMemcpy(res_cpu, res_gpu, sizeof(int) * LEN, cudaMemcpyDeviceToHost); if (status != cudaSuccess) { cout << cudaGetErrorString(status) << endl; } status = cudaFree(v1_gpu); if (status != cudaSuccess) { cout << cudaGetErrorString(status) << endl; } status = cudaFree(v2_gpu); if (status != cudaSuccess) { cout << cudaGetErrorString(status) << endl; } status = cudaFree(res_gpu); if (status != cudaSuccess) { cout << cudaGetErrorString(status) << endl; } free(res_cpu); return 0; }
.file "tmpxft_000c9b3d_00000000-6_task1_1.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3672: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3672: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z31__device_stub__Z7add_vecPiS_S_mPiS_S_m .type _Z31__device_stub__Z7add_vecPiS_S_mPiS_S_m, @function _Z31__device_stub__Z7add_vecPiS_S_mPiS_S_m: .LFB3694: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movq %rcx, (%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) movq %rsp, %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z7add_vecPiS_S_m(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE3694: .size _Z31__device_stub__Z7add_vecPiS_S_mPiS_S_m, .-_Z31__device_stub__Z7add_vecPiS_S_mPiS_S_m .globl _Z7add_vecPiS_S_m .type _Z7add_vecPiS_S_m, @function _Z7add_vecPiS_S_m: .LFB3695: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z31__device_stub__Z7add_vecPiS_S_mPiS_S_m addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3695: .size _Z7add_vecPiS_S_m, .-_Z7add_vecPiS_S_m .globl main .type main, @function main: .LFB3669: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $72, %rsp .cfi_def_cfa_offset 96 movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax movl $4, %esi movl $100000000, %edi call calloc@PLT movq %rax, %rbp movl $4, %esi movl $100000000, %edi call calloc@PLT movq %rax, %rbx movl $2, %edx movl $0, %eax .L12: movl %eax, 0(%rbp,%rax,4) movl %edx, (%rbx,%rax,4) addq $1, %rax addl $40, %edx cmpq $100000000, %rax jne .L12 leaq 8(%rsp), %rdi movl $400000000, %esi call cudaMalloc@PLT testl %eax, %eax jne .L26 .L13: leaq 16(%rsp), %rdi movl $400000000, %esi call cudaMalloc@PLT testl %eax, %eax jne .L27 .L14: leaq 24(%rsp), %rdi movl $400000000, %esi call cudaMalloc@PLT testl %eax, %eax jne .L28 .L15: movl $1, %ecx movl $400000000, %edx movq %rbp, %rsi movq 8(%rsp), %rdi call cudaMemcpy@PLT testl %eax, %eax jne .L29 .L16: movl $1, %ecx movl $400000000, %edx movq %rbx, %rsi movq 16(%rsp), %rdi call cudaMemcpy@PLT testl %eax, %eax jne .L30 .L17: movq %rbp, %rdi call free@PLT movq %rbx, %rdi call free@PLT movl $32, 44(%rsp) movl $1, 48(%rsp) movl $2, 32(%rsp) movl $1, 36(%rsp) movl $0, %r9d movl $0, %r8d movq 44(%rsp), %rdx movl $1, %ecx movq 32(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L31 .L18: movl $100000000, %esi movl $4, %edi call calloc@PLT movq %rax, %rbx movl $2, %ecx movl $400000000, %edx movq 24(%rsp), %rsi movq %rax, %rdi call cudaMemcpy@PLT testl %eax, %eax jne .L32 .L19: movq 8(%rsp), %rdi call cudaFree@PLT testl %eax, %eax jne .L33 .L20: movq 16(%rsp), %rdi call cudaFree@PLT testl %eax, %eax jne .L34 .L21: movq 24(%rsp), %rdi call cudaFree@PLT testl %eax, %eax jne .L35 .L22: movq %rbx, %rdi call free@PLT movq 56(%rsp), %rax subq %fs:40, %rax jne .L36 movl $0, %eax addq $72, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L26: .cfi_restore_state movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT jmp .L13 .L27: movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT jmp .L14 .L28: movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT jmp .L15 .L29: movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT jmp .L16 .L30: movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT jmp .L17 .L31: movl $100000000, %ecx movq 24(%rsp), %rdx movq 16(%rsp), %rsi movq 8(%rsp), %rdi call _Z31__device_stub__Z7add_vecPiS_S_mPiS_S_m jmp .L18 .L32: movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT jmp .L19 .L33: movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT jmp .L20 .L34: movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT jmp .L21 .L35: movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT jmp .L22 .L36: call __stack_chk_fail@PLT .cfi_endproc .LFE3669: .size main, .-main .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z7add_vecPiS_S_m" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3697: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z7add_vecPiS_S_m(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3697: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include <iostream> #include <cuda_runtime_api.h> #include <stdlib.h> using namespace std; #define LEN 100000000 __global__ void add_vec(int *v1, int *v2, int *res, size_t l) { // cudaError_t status; int i = blockIdx.x * blockDim.x + threadIdx.x; int step = gridDim.x * blockDim.x; for (; i < l; i+= step) { res[i] = v1[i] + v2[i]; } } int main() { int *v1_cpu, *v2_cpu, *res_cpu; v1_cpu = (int*)calloc(LEN, sizeof(int)); v2_cpu = (int*)calloc(LEN, sizeof(int)); for (int i = 0; i < LEN; i++) { v1_cpu[i] = i; v2_cpu[i] = i * 40 + 2; } cudaError_t status; int *v1_gpu, *v2_gpu, *res_gpu; status = cudaMalloc((void**)&v1_gpu, sizeof(int) * LEN); if (status != cudaSuccess) { cout << cudaGetErrorString(status) << endl; } status = cudaMalloc((void**)&v2_gpu, sizeof(int) * LEN); if (status != cudaSuccess) { cout << cudaGetErrorString(status) << endl; } status = cudaMalloc((void**)&res_gpu, sizeof(int) * LEN); if (status != cudaSuccess) { cout << cudaGetErrorString(status) << endl; } status = cudaMemcpy(v1_gpu, v1_cpu, sizeof(int) * LEN, cudaMemcpyHostToDevice); if (status != cudaSuccess) { cout << cudaGetErrorString(status) << endl; } status = cudaMemcpy(v2_gpu, v2_cpu, sizeof(int) * LEN, cudaMemcpyHostToDevice); if (status != cudaSuccess) { cout << cudaGetErrorString(status) << endl; } free(v1_cpu); free(v2_cpu); add_vec<<<2, 32, 0>>>(v1_gpu, v2_gpu, res_gpu, LEN); res_cpu = (int*)calloc(sizeof(int), LEN); status = cudaMemcpy(res_cpu, res_gpu, sizeof(int) * LEN, cudaMemcpyDeviceToHost); if (status != cudaSuccess) { cout << cudaGetErrorString(status) << endl; } status = cudaFree(v1_gpu); if (status != cudaSuccess) { cout << cudaGetErrorString(status) << endl; } status = cudaFree(v2_gpu); if (status != cudaSuccess) { cout << cudaGetErrorString(status) << endl; } status = cudaFree(res_gpu); if (status != cudaSuccess) { cout << cudaGetErrorString(status) << endl; } free(res_cpu); return 0; }
#include <hip/hip_runtime.h> #include <iostream> #include <hip/hip_runtime_api.h> #include <stdlib.h> using namespace std; #define LEN 100000000 __global__ void add_vec(int *v1, int *v2, int *res, size_t l) { // cudaError_t status; int i = blockIdx.x * blockDim.x + threadIdx.x; int step = gridDim.x * blockDim.x; for (; i < l; i+= step) { res[i] = v1[i] + v2[i]; } } int main() { int *v1_cpu, *v2_cpu, *res_cpu; v1_cpu = (int*)calloc(LEN, sizeof(int)); v2_cpu = (int*)calloc(LEN, sizeof(int)); for (int i = 0; i < LEN; i++) { v1_cpu[i] = i; v2_cpu[i] = i * 40 + 2; } hipError_t status; int *v1_gpu, *v2_gpu, *res_gpu; status = hipMalloc((void**)&v1_gpu, sizeof(int) * LEN); if (status != hipSuccess) { cout << hipGetErrorString(status) << endl; } status = hipMalloc((void**)&v2_gpu, sizeof(int) * LEN); if (status != hipSuccess) { cout << hipGetErrorString(status) << endl; } status = hipMalloc((void**)&res_gpu, sizeof(int) * LEN); if (status != hipSuccess) { cout << hipGetErrorString(status) << endl; } status = hipMemcpy(v1_gpu, v1_cpu, sizeof(int) * LEN, hipMemcpyHostToDevice); if (status != hipSuccess) { cout << hipGetErrorString(status) << endl; } status = hipMemcpy(v2_gpu, v2_cpu, sizeof(int) * LEN, hipMemcpyHostToDevice); if (status != hipSuccess) { cout << hipGetErrorString(status) << endl; } free(v1_cpu); free(v2_cpu); add_vec<<<2, 32, 0>>>(v1_gpu, v2_gpu, res_gpu, LEN); res_cpu = (int*)calloc(sizeof(int), LEN); status = hipMemcpy(res_cpu, res_gpu, sizeof(int) * LEN, hipMemcpyDeviceToHost); if (status != hipSuccess) { cout << hipGetErrorString(status) << endl; } status = hipFree(v1_gpu); if (status != hipSuccess) { cout << hipGetErrorString(status) << endl; } status = hipFree(v2_gpu); if (status != hipSuccess) { cout << hipGetErrorString(status) << endl; } status = hipFree(res_gpu); if (status != hipSuccess) { cout << hipGetErrorString(status) << endl; } free(res_cpu); return 0; }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <hip/hip_runtime.h> #include <iostream> #include <hip/hip_runtime_api.h> #include <stdlib.h> using namespace std; #define LEN 100000000 __global__ void add_vec(int *v1, int *v2, int *res, size_t l) { // cudaError_t status; int i = blockIdx.x * blockDim.x + threadIdx.x; int step = gridDim.x * blockDim.x; for (; i < l; i+= step) { res[i] = v1[i] + v2[i]; } } int main() { int *v1_cpu, *v2_cpu, *res_cpu; v1_cpu = (int*)calloc(LEN, sizeof(int)); v2_cpu = (int*)calloc(LEN, sizeof(int)); for (int i = 0; i < LEN; i++) { v1_cpu[i] = i; v2_cpu[i] = i * 40 + 2; } hipError_t status; int *v1_gpu, *v2_gpu, *res_gpu; status = hipMalloc((void**)&v1_gpu, sizeof(int) * LEN); if (status != hipSuccess) { cout << hipGetErrorString(status) << endl; } status = hipMalloc((void**)&v2_gpu, sizeof(int) * LEN); if (status != hipSuccess) { cout << hipGetErrorString(status) << endl; } status = hipMalloc((void**)&res_gpu, sizeof(int) * LEN); if (status != hipSuccess) { cout << hipGetErrorString(status) << endl; } status = hipMemcpy(v1_gpu, v1_cpu, sizeof(int) * LEN, hipMemcpyHostToDevice); if (status != hipSuccess) { cout << hipGetErrorString(status) << endl; } status = hipMemcpy(v2_gpu, v2_cpu, sizeof(int) * LEN, hipMemcpyHostToDevice); if (status != hipSuccess) { cout << hipGetErrorString(status) << endl; } free(v1_cpu); free(v2_cpu); add_vec<<<2, 32, 0>>>(v1_gpu, v2_gpu, res_gpu, LEN); res_cpu = (int*)calloc(sizeof(int), LEN); status = hipMemcpy(res_cpu, res_gpu, sizeof(int) * LEN, hipMemcpyDeviceToHost); if (status != hipSuccess) { cout << hipGetErrorString(status) << endl; } status = hipFree(v1_gpu); if (status != hipSuccess) { cout << hipGetErrorString(status) << endl; } status = hipFree(v2_gpu); if (status != hipSuccess) { cout << hipGetErrorString(status) << endl; } status = hipFree(res_gpu); if (status != hipSuccess) { cout << hipGetErrorString(status) << endl; } free(res_cpu); return 0; }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z7add_vecPiS_S_m .globl _Z7add_vecPiS_S_m .p2align 8 .type _Z7add_vecPiS_S_m,@function _Z7add_vecPiS_S_m: s_clause 0x1 s_load_b32 s6, s[0:1], 0x2c s_load_b64 s[2:3], s[0:1], 0x18 s_add_u32 s4, s0, 32 s_addc_u32 s5, s1, 0 s_waitcnt lgkmcnt(0) s_and_b32 s10, s6, 0xffff s_mov_b32 s6, exec_lo v_mad_u64_u32 v[1:2], null, s15, s10, v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v2, 31, v1 v_cmpx_gt_u64_e64 s[2:3], v[1:2] s_cbranch_execz .LBB0_3 s_load_b32 s11, s[4:5], 0x0 s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b64 s[8:9], s[0:1], 0x10 s_waitcnt lgkmcnt(0) s_add_i32 s15, s15, s11 s_mul_i32 s1, s11, s10 v_mad_u64_u32 v[3:4], null, s15, s10, v[0:1] s_ashr_i32 s10, s1, 31 s_mov_b32 s11, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_ashrrev_i32_e32 v0, 31, v3 v_sub_co_u32 v3, vcc_lo, v3, s1 v_subrev_co_ci_u32_e32 v4, vcc_lo, s10, v0, vcc_lo .p2align 6 .LBB0_2: v_lshlrev_b64 v[0:1], 2, v[1:2] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v5, vcc_lo, s4, v0 v_add_co_ci_u32_e32 v6, vcc_lo, s5, v1, vcc_lo v_add_co_u32 v7, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v8, vcc_lo, s7, v1, vcc_lo v_add_co_u32 v3, vcc_lo, v3, s1 global_load_b32 v9, v[5:6], off global_load_b32 v7, v[7:8], off v_add_co_ci_u32_e32 v4, vcc_lo, s10, v4, vcc_lo v_add_co_u32 v5, s0, s8, v0 v_ashrrev_i32_e32 v2, 31, v3 s_delay_alu instid0(VALU_DEP_3) v_cmp_le_u64_e32 vcc_lo, s[2:3], v[3:4] v_add_co_ci_u32_e64 v6, s0, s9, v1, s0 v_mov_b32_e32 v1, v3 s_or_b32 s11, vcc_lo, s11 s_waitcnt vmcnt(0) v_add_nc_u32_e32 v0, v7, v9 global_store_b32 v[5:6], v0, off s_and_not1_b32 exec_lo, exec_lo, s11 s_cbranch_execnz .LBB0_2 .LBB0_3: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z7add_vecPiS_S_m .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 10 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z7add_vecPiS_S_m, .Lfunc_end0-_Z7add_vecPiS_S_m .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 8 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z7add_vecPiS_S_m .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z7add_vecPiS_S_m.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 10 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <hip/hip_runtime.h> #include <iostream> #include <hip/hip_runtime_api.h> #include <stdlib.h> using namespace std; #define LEN 100000000 __global__ void add_vec(int *v1, int *v2, int *res, size_t l) { // cudaError_t status; int i = blockIdx.x * blockDim.x + threadIdx.x; int step = gridDim.x * blockDim.x; for (; i < l; i+= step) { res[i] = v1[i] + v2[i]; } } int main() { int *v1_cpu, *v2_cpu, *res_cpu; v1_cpu = (int*)calloc(LEN, sizeof(int)); v2_cpu = (int*)calloc(LEN, sizeof(int)); for (int i = 0; i < LEN; i++) { v1_cpu[i] = i; v2_cpu[i] = i * 40 + 2; } hipError_t status; int *v1_gpu, *v2_gpu, *res_gpu; status = hipMalloc((void**)&v1_gpu, sizeof(int) * LEN); if (status != hipSuccess) { cout << hipGetErrorString(status) << endl; } status = hipMalloc((void**)&v2_gpu, sizeof(int) * LEN); if (status != hipSuccess) { cout << hipGetErrorString(status) << endl; } status = hipMalloc((void**)&res_gpu, sizeof(int) * LEN); if (status != hipSuccess) { cout << hipGetErrorString(status) << endl; } status = hipMemcpy(v1_gpu, v1_cpu, sizeof(int) * LEN, hipMemcpyHostToDevice); if (status != hipSuccess) { cout << hipGetErrorString(status) << endl; } status = hipMemcpy(v2_gpu, v2_cpu, sizeof(int) * LEN, hipMemcpyHostToDevice); if (status != hipSuccess) { cout << hipGetErrorString(status) << endl; } free(v1_cpu); free(v2_cpu); add_vec<<<2, 32, 0>>>(v1_gpu, v2_gpu, res_gpu, LEN); res_cpu = (int*)calloc(sizeof(int), LEN); status = hipMemcpy(res_cpu, res_gpu, sizeof(int) * LEN, hipMemcpyDeviceToHost); if (status != hipSuccess) { cout << hipGetErrorString(status) << endl; } status = hipFree(v1_gpu); if (status != hipSuccess) { cout << hipGetErrorString(status) << endl; } status = hipFree(v2_gpu); if (status != hipSuccess) { cout << hipGetErrorString(status) << endl; } status = hipFree(res_gpu); if (status != hipSuccess) { cout << hipGetErrorString(status) << endl; } free(res_cpu); return 0; }
.text .file "task1_1.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z22__device_stub__add_vecPiS_S_m # -- Begin function _Z22__device_stub__add_vecPiS_S_m .p2align 4, 0x90 .type _Z22__device_stub__add_vecPiS_S_m,@function _Z22__device_stub__add_vecPiS_S_m: # @_Z22__device_stub__add_vecPiS_S_m .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movq %rcx, 48(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 48(%rsp), %rax movq %rax, 104(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z7add_vecPiS_S_m, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z22__device_stub__add_vecPiS_S_m, .Lfunc_end0-_Z22__device_stub__add_vecPiS_S_m .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 subq $144, %rsp .cfi_def_cfa_offset 176 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movl $100000000, %edi # imm = 0x5F5E100 movl $4, %esi callq calloc movq %rax, %rbx movl $100000000, %edi # imm = 0x5F5E100 movl $4, %esi callq calloc movq %rax, %r14 movl $2, %eax xorl %ecx, %ecx .p2align 4, 0x90 .LBB1_1: # =>This Inner Loop Header: Depth=1 movl %ecx, (%rbx,%rcx,4) movl %eax, (%r14,%rcx,4) incq %rcx addl $40, %eax cmpq $100000000, %rcx # imm = 0x5F5E100 jne .LBB1_1 # %bb.2: leaq 24(%rsp), %rdi movl $400000000, %esi # imm = 0x17D78400 callq hipMalloc testl %eax, %eax je .LBB1_11 # %bb.3: movl %eax, %edi callq hipGetErrorString testq %rax, %rax je .LBB1_4 # %bb.5: movq %rax, %rdi movq %rax, %r15 callq strlen movl $_ZSt4cout, %edi movq %r15, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_6 .LBB1_4: movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cout(%rax), %rdi movl _ZSt4cout+32(%rax), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB1_6: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %r15 testq %r15, %r15 je .LBB1_86 # %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i cmpb $0, 56(%r15) je .LBB1_9 # %bb.8: movzbl 67(%r15), %eax jmp .LBB1_10 .LBB1_9: movq %r15, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r15), %rax movq %r15, %rdi movl $10, %esi callq *48(%rax) .LBB1_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv .LBB1_11: leaq 16(%rsp), %rdi movl $400000000, %esi # imm = 0x17D78400 callq hipMalloc testl %eax, %eax je .LBB1_20 # %bb.12: movl %eax, %edi callq hipGetErrorString testq %rax, %rax je .LBB1_13 # %bb.14: movq %rax, %rdi movq %rax, %r15 callq strlen movl $_ZSt4cout, %edi movq %r15, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_15 .LBB1_13: movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cout(%rax), %rdi movl _ZSt4cout+32(%rax), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB1_15: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit52 movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %r15 testq %r15, %r15 je .LBB1_86 # %bb.16: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i68 cmpb $0, 56(%r15) je .LBB1_18 # %bb.17: movzbl 67(%r15), %eax jmp .LBB1_19 .LBB1_18: movq %r15, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r15), %rax movq %r15, %rdi movl $10, %esi callq *48(%rax) .LBB1_19: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit71 movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv .LBB1_20: leaq 8(%rsp), %rdi movl $400000000, %esi # imm = 0x17D78400 callq hipMalloc testl %eax, %eax je .LBB1_29 # %bb.21: movl %eax, %edi callq hipGetErrorString testq %rax, %rax je .LBB1_22 # %bb.23: movq %rax, %rdi movq %rax, %r15 callq strlen movl $_ZSt4cout, %edi movq %r15, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_24 .LBB1_22: movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cout(%rax), %rdi movl _ZSt4cout+32(%rax), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB1_24: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit54 movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %r15 testq %r15, %r15 je .LBB1_86 # %bb.25: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i73 cmpb $0, 56(%r15) je .LBB1_27 # %bb.26: movzbl 67(%r15), %eax jmp .LBB1_28 .LBB1_27: movq %r15, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r15), %rax movq %r15, %rdi movl $10, %esi callq *48(%rax) .LBB1_28: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit76 movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv .LBB1_29: movq 24(%rsp), %rdi movl $400000000, %edx # imm = 0x17D78400 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy testl %eax, %eax je .LBB1_38 # %bb.30: movl %eax, %edi callq hipGetErrorString testq %rax, %rax je .LBB1_31 # %bb.32: movq %rax, %rdi movq %rax, %r15 callq strlen movl $_ZSt4cout, %edi movq %r15, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_33 .LBB1_31: movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cout(%rax), %rdi movl _ZSt4cout+32(%rax), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB1_33: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit56 movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %r15 testq %r15, %r15 je .LBB1_86 # %bb.34: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i78 cmpb $0, 56(%r15) je .LBB1_36 # %bb.35: movzbl 67(%r15), %eax jmp .LBB1_37 .LBB1_36: movq %r15, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r15), %rax movq %r15, %rdi movl $10, %esi callq *48(%rax) .LBB1_37: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit81 movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv .LBB1_38: movq 16(%rsp), %rdi movl $400000000, %edx # imm = 0x17D78400 movq %r14, %rsi movl $1, %ecx callq hipMemcpy testl %eax, %eax je .LBB1_47 # %bb.39: movl %eax, %edi callq hipGetErrorString testq %rax, %rax je .LBB1_40 # %bb.41: movq %rax, %rdi movq %rax, %r15 callq strlen movl $_ZSt4cout, %edi movq %r15, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_42 .LBB1_40: movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cout(%rax), %rdi movl _ZSt4cout+32(%rax), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB1_42: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit58 movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %r15 testq %r15, %r15 je .LBB1_86 # %bb.43: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i83 cmpb $0, 56(%r15) je .LBB1_45 # %bb.44: movzbl 67(%r15), %eax jmp .LBB1_46 .LBB1_45: movq %r15, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r15), %rax movq %r15, %rdi movl $10, %esi callq *48(%rax) .LBB1_46: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit86 movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv .LBB1_47: movq %rbx, %rdi callq free movq %r14, %rdi callq free movabsq $4294967298, %rdi # imm = 0x100000002 leaq 30(%rdi), %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_49 # %bb.48: movq 24(%rsp), %rax movq 16(%rsp), %rcx movq 8(%rsp), %rdx movq %rax, 104(%rsp) movq %rcx, 96(%rsp) movq %rdx, 88(%rsp) movq $100000000, 80(%rsp) # imm = 0x5F5E100 leaq 104(%rsp), %rax movq %rax, 112(%rsp) leaq 96(%rsp), %rax movq %rax, 120(%rsp) leaq 88(%rsp), %rax movq %rax, 128(%rsp) leaq 80(%rsp), %rax movq %rax, 136(%rsp) leaq 64(%rsp), %rdi leaq 48(%rsp), %rsi leaq 40(%rsp), %rdx leaq 32(%rsp), %rcx callq __hipPopCallConfiguration movq 64(%rsp), %rsi movl 72(%rsp), %edx movq 48(%rsp), %rcx movl 56(%rsp), %r8d leaq 112(%rsp), %r9 movl $_Z7add_vecPiS_S_m, %edi pushq 32(%rsp) .cfi_adjust_cfa_offset 8 pushq 48(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_49: movl $4, %edi movl $100000000, %esi # imm = 0x5F5E100 callq calloc movq %rax, %rbx movq 8(%rsp), %rsi movl $400000000, %edx # imm = 0x17D78400 movq %rax, %rdi movl $2, %ecx callq hipMemcpy testl %eax, %eax je .LBB1_58 # %bb.50: movl %eax, %edi callq hipGetErrorString testq %rax, %rax je .LBB1_51 # %bb.52: movq %rax, %rdi movq %rax, %r14 callq strlen movl $_ZSt4cout, %edi movq %r14, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_53 .LBB1_51: movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cout(%rax), %rdi movl _ZSt4cout+32(%rax), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB1_53: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit60 movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %r14 testq %r14, %r14 je .LBB1_86 # %bb.54: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i88 cmpb $0, 56(%r14) je .LBB1_56 # %bb.55: movzbl 67(%r14), %eax jmp .LBB1_57 .LBB1_56: movq %r14, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r14), %rax movq %r14, %rdi movl $10, %esi callq *48(%rax) .LBB1_57: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit91 movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv .LBB1_58: movq 24(%rsp), %rdi callq hipFree testl %eax, %eax je .LBB1_67 # %bb.59: movl %eax, %edi callq hipGetErrorString testq %rax, %rax je .LBB1_60 # %bb.61: movq %rax, %rdi movq %rax, %r14 callq strlen movl $_ZSt4cout, %edi movq %r14, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_62 .LBB1_60: movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cout(%rax), %rdi movl _ZSt4cout+32(%rax), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB1_62: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit62 movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %r14 testq %r14, %r14 je .LBB1_86 # %bb.63: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i93 cmpb $0, 56(%r14) je .LBB1_65 # %bb.64: movzbl 67(%r14), %eax jmp .LBB1_66 .LBB1_65: movq %r14, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r14), %rax movq %r14, %rdi movl $10, %esi callq *48(%rax) .LBB1_66: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit96 movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv .LBB1_67: movq 16(%rsp), %rdi callq hipFree testl %eax, %eax je .LBB1_76 # %bb.68: movl %eax, %edi callq hipGetErrorString testq %rax, %rax je .LBB1_69 # %bb.70: movq %rax, %rdi movq %rax, %r14 callq strlen movl $_ZSt4cout, %edi movq %r14, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_71 .LBB1_69: movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cout(%rax), %rdi movl _ZSt4cout+32(%rax), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB1_71: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit64 movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %r14 testq %r14, %r14 je .LBB1_86 # %bb.72: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i98 cmpb $0, 56(%r14) je .LBB1_74 # %bb.73: movzbl 67(%r14), %eax jmp .LBB1_75 .LBB1_74: movq %r14, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r14), %rax movq %r14, %rdi movl $10, %esi callq *48(%rax) .LBB1_75: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit101 movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv .LBB1_76: movq 8(%rsp), %rdi callq hipFree testl %eax, %eax je .LBB1_85 # %bb.77: movl %eax, %edi callq hipGetErrorString testq %rax, %rax je .LBB1_78 # %bb.79: movq %rax, %rdi movq %rax, %r14 callq strlen movl $_ZSt4cout, %edi movq %r14, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_80 .LBB1_78: movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cout(%rax), %rdi movl _ZSt4cout+32(%rax), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB1_80: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit66 movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %r14 testq %r14, %r14 je .LBB1_86 # %bb.81: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i103 cmpb $0, 56(%r14) je .LBB1_83 # %bb.82: movzbl 67(%r14), %eax jmp .LBB1_84 .LBB1_83: movq %r14, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r14), %rax movq %r14, %rdi movl $10, %esi callq *48(%rax) .LBB1_84: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit106 movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv .LBB1_85: movq %rbx, %rdi callq free xorl %eax, %eax addq $144, %rsp .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .LBB1_86: .cfi_def_cfa_offset 176 callq _ZSt16__throw_bad_castv .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z7add_vecPiS_S_m, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z7add_vecPiS_S_m,@object # @_Z7add_vecPiS_S_m .section .rodata,"a",@progbits .globl _Z7add_vecPiS_S_m .p2align 3, 0x0 _Z7add_vecPiS_S_m: .quad _Z22__device_stub__add_vecPiS_S_m .size _Z7add_vecPiS_S_m, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z7add_vecPiS_S_m" .size .L__unnamed_1, 18 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z22__device_stub__add_vecPiS_S_m .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z7add_vecPiS_S_m .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z7add_vecPiS_S_m .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */ /* 0x000e280000002500 */ /*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */ /* 0x000e240000002100 */ /*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */ /* 0x001fca00078e0203 */ /*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */ /* 0x000fe40003f06070 */ /*0050*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */ /* 0x000fc80000011400 */ /*0060*/ ISETP.GE.U32.AND.EX P0, PT, R2, c[0x0][0x17c], PT, P0 ; /* 0x00005f0002007a0c */ /* 0x000fda0003f06100 */ /*0070*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*0080*/ IMAD.MOV.U32 R11, RZ, RZ, R2 ; /* 0x000000ffff0b7224 */ /* 0x000fe200078e0002 */ /*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fe20000000a00 */ /*00a0*/ IMAD.MOV.U32 R8, RZ, RZ, R0 ; /* 0x000000ffff087224 */ /* 0x000fc800078e0000 */ /*00b0*/ IMAD.SHL.U32 R6, R8.reuse, 0x4, RZ ; /* 0x0000000408067824 */ /* 0x041fe200078e00ff */ /*00c0*/ SHF.L.U64.HI R7, R8, 0x2, R11 ; /* 0x0000000208077819 */ /* 0x000fc8000001020b */ /*00d0*/ IADD3 R4, P1, R6.reuse, c[0x0][0x160], RZ ; /* 0x0000580006047a10 */ /* 0x040fe40007f3e0ff */ /*00e0*/ IADD3 R2, P0, R6, c[0x0][0x168], RZ ; /* 0x00005a0006027a10 */ /* 0x000fe40007f1e0ff */ /*00f0*/ IADD3.X R5, R7.reuse, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590007057a10 */ /* 0x040fe40000ffe4ff */ /*0100*/ IADD3.X R3, R7, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0007037a10 */ /* 0x000fc800007fe4ff */ /*0110*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */ /* 0x000ea8000c1e1900 */ /*0120*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */ /* 0x000ea2000c1e1900 */ /*0130*/ IADD3 R6, P0, R6, c[0x0][0x170], RZ ; /* 0x00005c0006067a10 */ /* 0x000fe20007f1e0ff */ /*0140*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff0b7624 */ /* 0x000fc600078e00ff */ /*0150*/ IADD3.X R7, R7, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0007077a10 */ /* 0x000fe200007fe4ff */ /*0160*/ IMAD R8, R11, c[0x0][0x0], R0 ; /* 0x000000000b087a24 */ /* 0x000fca00078e0200 */ /*0170*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0c */ /* 0x000fe40003f06070 */ /*0180*/ SHF.R.S32.HI R11, RZ, 0x1f, R8 ; /* 0x0000001fff0b7819 */ /* 0x000fc80000011408 */ /*0190*/ ISETP.GE.U32.AND.EX P0, PT, R11, c[0x0][0x17c], PT, P0 ; /* 0x00005f000b007a0c */ /* 0x000fe20003f06100 */ /*01a0*/ IMAD.MOV.U32 R0, RZ, RZ, R8 ; /* 0x000000ffff007224 */ /* 0x000fe400078e0008 */ /*01b0*/ IMAD.IADD R9, R2, 0x1, R5 ; /* 0x0000000102097824 */ /* 0x004fca00078e0205 */ /*01c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */ /* 0x0001ea000c101904 */ /*01d0*/ @!P0 BRA 0xb0 ; /* 0xfffffed000008947 */ /* 0x000fea000383ffff */ /*01e0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0200*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0210*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0220*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0230*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0240*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0250*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0260*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0270*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z7add_vecPiS_S_m .globl _Z7add_vecPiS_S_m .p2align 8 .type _Z7add_vecPiS_S_m,@function _Z7add_vecPiS_S_m: s_clause 0x1 s_load_b32 s6, s[0:1], 0x2c s_load_b64 s[2:3], s[0:1], 0x18 s_add_u32 s4, s0, 32 s_addc_u32 s5, s1, 0 s_waitcnt lgkmcnt(0) s_and_b32 s10, s6, 0xffff s_mov_b32 s6, exec_lo v_mad_u64_u32 v[1:2], null, s15, s10, v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v2, 31, v1 v_cmpx_gt_u64_e64 s[2:3], v[1:2] s_cbranch_execz .LBB0_3 s_load_b32 s11, s[4:5], 0x0 s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b64 s[8:9], s[0:1], 0x10 s_waitcnt lgkmcnt(0) s_add_i32 s15, s15, s11 s_mul_i32 s1, s11, s10 v_mad_u64_u32 v[3:4], null, s15, s10, v[0:1] s_ashr_i32 s10, s1, 31 s_mov_b32 s11, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_ashrrev_i32_e32 v0, 31, v3 v_sub_co_u32 v3, vcc_lo, v3, s1 v_subrev_co_ci_u32_e32 v4, vcc_lo, s10, v0, vcc_lo .p2align 6 .LBB0_2: v_lshlrev_b64 v[0:1], 2, v[1:2] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v5, vcc_lo, s4, v0 v_add_co_ci_u32_e32 v6, vcc_lo, s5, v1, vcc_lo v_add_co_u32 v7, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v8, vcc_lo, s7, v1, vcc_lo v_add_co_u32 v3, vcc_lo, v3, s1 global_load_b32 v9, v[5:6], off global_load_b32 v7, v[7:8], off v_add_co_ci_u32_e32 v4, vcc_lo, s10, v4, vcc_lo v_add_co_u32 v5, s0, s8, v0 v_ashrrev_i32_e32 v2, 31, v3 s_delay_alu instid0(VALU_DEP_3) v_cmp_le_u64_e32 vcc_lo, s[2:3], v[3:4] v_add_co_ci_u32_e64 v6, s0, s9, v1, s0 v_mov_b32_e32 v1, v3 s_or_b32 s11, vcc_lo, s11 s_waitcnt vmcnt(0) v_add_nc_u32_e32 v0, v7, v9 global_store_b32 v[5:6], v0, off s_and_not1_b32 exec_lo, exec_lo, s11 s_cbranch_execnz .LBB0_2 .LBB0_3: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z7add_vecPiS_S_m .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 10 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z7add_vecPiS_S_m, .Lfunc_end0-_Z7add_vecPiS_S_m .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 8 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z7add_vecPiS_S_m .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z7add_vecPiS_S_m.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 10 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_000c9b3d_00000000-6_task1_1.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3672: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3672: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z31__device_stub__Z7add_vecPiS_S_mPiS_S_m .type _Z31__device_stub__Z7add_vecPiS_S_mPiS_S_m, @function _Z31__device_stub__Z7add_vecPiS_S_mPiS_S_m: .LFB3694: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movq %rcx, (%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) movq %rsp, %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z7add_vecPiS_S_m(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE3694: .size _Z31__device_stub__Z7add_vecPiS_S_mPiS_S_m, .-_Z31__device_stub__Z7add_vecPiS_S_mPiS_S_m .globl _Z7add_vecPiS_S_m .type _Z7add_vecPiS_S_m, @function _Z7add_vecPiS_S_m: .LFB3695: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z31__device_stub__Z7add_vecPiS_S_mPiS_S_m addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3695: .size _Z7add_vecPiS_S_m, .-_Z7add_vecPiS_S_m .globl main .type main, @function main: .LFB3669: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $72, %rsp .cfi_def_cfa_offset 96 movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax movl $4, %esi movl $100000000, %edi call calloc@PLT movq %rax, %rbp movl $4, %esi movl $100000000, %edi call calloc@PLT movq %rax, %rbx movl $2, %edx movl $0, %eax .L12: movl %eax, 0(%rbp,%rax,4) movl %edx, (%rbx,%rax,4) addq $1, %rax addl $40, %edx cmpq $100000000, %rax jne .L12 leaq 8(%rsp), %rdi movl $400000000, %esi call cudaMalloc@PLT testl %eax, %eax jne .L26 .L13: leaq 16(%rsp), %rdi movl $400000000, %esi call cudaMalloc@PLT testl %eax, %eax jne .L27 .L14: leaq 24(%rsp), %rdi movl $400000000, %esi call cudaMalloc@PLT testl %eax, %eax jne .L28 .L15: movl $1, %ecx movl $400000000, %edx movq %rbp, %rsi movq 8(%rsp), %rdi call cudaMemcpy@PLT testl %eax, %eax jne .L29 .L16: movl $1, %ecx movl $400000000, %edx movq %rbx, %rsi movq 16(%rsp), %rdi call cudaMemcpy@PLT testl %eax, %eax jne .L30 .L17: movq %rbp, %rdi call free@PLT movq %rbx, %rdi call free@PLT movl $32, 44(%rsp) movl $1, 48(%rsp) movl $2, 32(%rsp) movl $1, 36(%rsp) movl $0, %r9d movl $0, %r8d movq 44(%rsp), %rdx movl $1, %ecx movq 32(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L31 .L18: movl $100000000, %esi movl $4, %edi call calloc@PLT movq %rax, %rbx movl $2, %ecx movl $400000000, %edx movq 24(%rsp), %rsi movq %rax, %rdi call cudaMemcpy@PLT testl %eax, %eax jne .L32 .L19: movq 8(%rsp), %rdi call cudaFree@PLT testl %eax, %eax jne .L33 .L20: movq 16(%rsp), %rdi call cudaFree@PLT testl %eax, %eax jne .L34 .L21: movq 24(%rsp), %rdi call cudaFree@PLT testl %eax, %eax jne .L35 .L22: movq %rbx, %rdi call free@PLT movq 56(%rsp), %rax subq %fs:40, %rax jne .L36 movl $0, %eax addq $72, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L26: .cfi_restore_state movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT jmp .L13 .L27: movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT jmp .L14 .L28: movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT jmp .L15 .L29: movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT jmp .L16 .L30: movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT jmp .L17 .L31: movl $100000000, %ecx movq 24(%rsp), %rdx movq 16(%rsp), %rsi movq 8(%rsp), %rdi call _Z31__device_stub__Z7add_vecPiS_S_mPiS_S_m jmp .L18 .L32: movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT jmp .L19 .L33: movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT jmp .L20 .L34: movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT jmp .L21 .L35: movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT jmp .L22 .L36: call __stack_chk_fail@PLT .cfi_endproc .LFE3669: .size main, .-main .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z7add_vecPiS_S_m" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3697: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z7add_vecPiS_S_m(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3697: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "task1_1.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z22__device_stub__add_vecPiS_S_m # -- Begin function _Z22__device_stub__add_vecPiS_S_m .p2align 4, 0x90 .type _Z22__device_stub__add_vecPiS_S_m,@function _Z22__device_stub__add_vecPiS_S_m: # @_Z22__device_stub__add_vecPiS_S_m .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movq %rcx, 48(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 48(%rsp), %rax movq %rax, 104(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z7add_vecPiS_S_m, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z22__device_stub__add_vecPiS_S_m, .Lfunc_end0-_Z22__device_stub__add_vecPiS_S_m .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 subq $144, %rsp .cfi_def_cfa_offset 176 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movl $100000000, %edi # imm = 0x5F5E100 movl $4, %esi callq calloc movq %rax, %rbx movl $100000000, %edi # imm = 0x5F5E100 movl $4, %esi callq calloc movq %rax, %r14 movl $2, %eax xorl %ecx, %ecx .p2align 4, 0x90 .LBB1_1: # =>This Inner Loop Header: Depth=1 movl %ecx, (%rbx,%rcx,4) movl %eax, (%r14,%rcx,4) incq %rcx addl $40, %eax cmpq $100000000, %rcx # imm = 0x5F5E100 jne .LBB1_1 # %bb.2: leaq 24(%rsp), %rdi movl $400000000, %esi # imm = 0x17D78400 callq hipMalloc testl %eax, %eax je .LBB1_11 # %bb.3: movl %eax, %edi callq hipGetErrorString testq %rax, %rax je .LBB1_4 # %bb.5: movq %rax, %rdi movq %rax, %r15 callq strlen movl $_ZSt4cout, %edi movq %r15, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_6 .LBB1_4: movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cout(%rax), %rdi movl _ZSt4cout+32(%rax), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB1_6: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %r15 testq %r15, %r15 je .LBB1_86 # %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i cmpb $0, 56(%r15) je .LBB1_9 # %bb.8: movzbl 67(%r15), %eax jmp .LBB1_10 .LBB1_9: movq %r15, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r15), %rax movq %r15, %rdi movl $10, %esi callq *48(%rax) .LBB1_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv .LBB1_11: leaq 16(%rsp), %rdi movl $400000000, %esi # imm = 0x17D78400 callq hipMalloc testl %eax, %eax je .LBB1_20 # %bb.12: movl %eax, %edi callq hipGetErrorString testq %rax, %rax je .LBB1_13 # %bb.14: movq %rax, %rdi movq %rax, %r15 callq strlen movl $_ZSt4cout, %edi movq %r15, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_15 .LBB1_13: movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cout(%rax), %rdi movl _ZSt4cout+32(%rax), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB1_15: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit52 movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %r15 testq %r15, %r15 je .LBB1_86 # %bb.16: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i68 cmpb $0, 56(%r15) je .LBB1_18 # %bb.17: movzbl 67(%r15), %eax jmp .LBB1_19 .LBB1_18: movq %r15, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r15), %rax movq %r15, %rdi movl $10, %esi callq *48(%rax) .LBB1_19: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit71 movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv .LBB1_20: leaq 8(%rsp), %rdi movl $400000000, %esi # imm = 0x17D78400 callq hipMalloc testl %eax, %eax je .LBB1_29 # %bb.21: movl %eax, %edi callq hipGetErrorString testq %rax, %rax je .LBB1_22 # %bb.23: movq %rax, %rdi movq %rax, %r15 callq strlen movl $_ZSt4cout, %edi movq %r15, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_24 .LBB1_22: movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cout(%rax), %rdi movl _ZSt4cout+32(%rax), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB1_24: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit54 movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %r15 testq %r15, %r15 je .LBB1_86 # %bb.25: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i73 cmpb $0, 56(%r15) je .LBB1_27 # %bb.26: movzbl 67(%r15), %eax jmp .LBB1_28 .LBB1_27: movq %r15, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r15), %rax movq %r15, %rdi movl $10, %esi callq *48(%rax) .LBB1_28: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit76 movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv .LBB1_29: movq 24(%rsp), %rdi movl $400000000, %edx # imm = 0x17D78400 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy testl %eax, %eax je .LBB1_38 # %bb.30: movl %eax, %edi callq hipGetErrorString testq %rax, %rax je .LBB1_31 # %bb.32: movq %rax, %rdi movq %rax, %r15 callq strlen movl $_ZSt4cout, %edi movq %r15, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_33 .LBB1_31: movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cout(%rax), %rdi movl _ZSt4cout+32(%rax), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB1_33: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit56 movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %r15 testq %r15, %r15 je .LBB1_86 # %bb.34: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i78 cmpb $0, 56(%r15) je .LBB1_36 # %bb.35: movzbl 67(%r15), %eax jmp .LBB1_37 .LBB1_36: movq %r15, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r15), %rax movq %r15, %rdi movl $10, %esi callq *48(%rax) .LBB1_37: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit81 movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv .LBB1_38: movq 16(%rsp), %rdi movl $400000000, %edx # imm = 0x17D78400 movq %r14, %rsi movl $1, %ecx callq hipMemcpy testl %eax, %eax je .LBB1_47 # %bb.39: movl %eax, %edi callq hipGetErrorString testq %rax, %rax je .LBB1_40 # %bb.41: movq %rax, %rdi movq %rax, %r15 callq strlen movl $_ZSt4cout, %edi movq %r15, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_42 .LBB1_40: movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cout(%rax), %rdi movl _ZSt4cout+32(%rax), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB1_42: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit58 movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %r15 testq %r15, %r15 je .LBB1_86 # %bb.43: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i83 cmpb $0, 56(%r15) je .LBB1_45 # %bb.44: movzbl 67(%r15), %eax jmp .LBB1_46 .LBB1_45: movq %r15, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r15), %rax movq %r15, %rdi movl $10, %esi callq *48(%rax) .LBB1_46: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit86 movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv .LBB1_47: movq %rbx, %rdi callq free movq %r14, %rdi callq free movabsq $4294967298, %rdi # imm = 0x100000002 leaq 30(%rdi), %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_49 # %bb.48: movq 24(%rsp), %rax movq 16(%rsp), %rcx movq 8(%rsp), %rdx movq %rax, 104(%rsp) movq %rcx, 96(%rsp) movq %rdx, 88(%rsp) movq $100000000, 80(%rsp) # imm = 0x5F5E100 leaq 104(%rsp), %rax movq %rax, 112(%rsp) leaq 96(%rsp), %rax movq %rax, 120(%rsp) leaq 88(%rsp), %rax movq %rax, 128(%rsp) leaq 80(%rsp), %rax movq %rax, 136(%rsp) leaq 64(%rsp), %rdi leaq 48(%rsp), %rsi leaq 40(%rsp), %rdx leaq 32(%rsp), %rcx callq __hipPopCallConfiguration movq 64(%rsp), %rsi movl 72(%rsp), %edx movq 48(%rsp), %rcx movl 56(%rsp), %r8d leaq 112(%rsp), %r9 movl $_Z7add_vecPiS_S_m, %edi pushq 32(%rsp) .cfi_adjust_cfa_offset 8 pushq 48(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_49: movl $4, %edi movl $100000000, %esi # imm = 0x5F5E100 callq calloc movq %rax, %rbx movq 8(%rsp), %rsi movl $400000000, %edx # imm = 0x17D78400 movq %rax, %rdi movl $2, %ecx callq hipMemcpy testl %eax, %eax je .LBB1_58 # %bb.50: movl %eax, %edi callq hipGetErrorString testq %rax, %rax je .LBB1_51 # %bb.52: movq %rax, %rdi movq %rax, %r14 callq strlen movl $_ZSt4cout, %edi movq %r14, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_53 .LBB1_51: movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cout(%rax), %rdi movl _ZSt4cout+32(%rax), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB1_53: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit60 movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %r14 testq %r14, %r14 je .LBB1_86 # %bb.54: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i88 cmpb $0, 56(%r14) je .LBB1_56 # %bb.55: movzbl 67(%r14), %eax jmp .LBB1_57 .LBB1_56: movq %r14, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r14), %rax movq %r14, %rdi movl $10, %esi callq *48(%rax) .LBB1_57: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit91 movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv .LBB1_58: movq 24(%rsp), %rdi callq hipFree testl %eax, %eax je .LBB1_67 # %bb.59: movl %eax, %edi callq hipGetErrorString testq %rax, %rax je .LBB1_60 # %bb.61: movq %rax, %rdi movq %rax, %r14 callq strlen movl $_ZSt4cout, %edi movq %r14, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_62 .LBB1_60: movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cout(%rax), %rdi movl _ZSt4cout+32(%rax), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB1_62: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit62 movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %r14 testq %r14, %r14 je .LBB1_86 # %bb.63: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i93 cmpb $0, 56(%r14) je .LBB1_65 # %bb.64: movzbl 67(%r14), %eax jmp .LBB1_66 .LBB1_65: movq %r14, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r14), %rax movq %r14, %rdi movl $10, %esi callq *48(%rax) .LBB1_66: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit96 movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv .LBB1_67: movq 16(%rsp), %rdi callq hipFree testl %eax, %eax je .LBB1_76 # %bb.68: movl %eax, %edi callq hipGetErrorString testq %rax, %rax je .LBB1_69 # %bb.70: movq %rax, %rdi movq %rax, %r14 callq strlen movl $_ZSt4cout, %edi movq %r14, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_71 .LBB1_69: movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cout(%rax), %rdi movl _ZSt4cout+32(%rax), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB1_71: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit64 movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %r14 testq %r14, %r14 je .LBB1_86 # %bb.72: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i98 cmpb $0, 56(%r14) je .LBB1_74 # %bb.73: movzbl 67(%r14), %eax jmp .LBB1_75 .LBB1_74: movq %r14, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r14), %rax movq %r14, %rdi movl $10, %esi callq *48(%rax) .LBB1_75: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit101 movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv .LBB1_76: movq 8(%rsp), %rdi callq hipFree testl %eax, %eax je .LBB1_85 # %bb.77: movl %eax, %edi callq hipGetErrorString testq %rax, %rax je .LBB1_78 # %bb.79: movq %rax, %rdi movq %rax, %r14 callq strlen movl $_ZSt4cout, %edi movq %r14, %rsi movq %rax, %rdx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l jmp .LBB1_80 .LBB1_78: movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax leaq _ZSt4cout(%rax), %rdi movl _ZSt4cout+32(%rax), %esi orl $1, %esi callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate .LBB1_80: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit66 movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %r14 testq %r14, %r14 je .LBB1_86 # %bb.81: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i103 cmpb $0, 56(%r14) je .LBB1_83 # %bb.82: movzbl 67(%r14), %eax jmp .LBB1_84 .LBB1_83: movq %r14, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r14), %rax movq %r14, %rdi movl $10, %esi callq *48(%rax) .LBB1_84: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit106 movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv .LBB1_85: movq %rbx, %rdi callq free xorl %eax, %eax addq $144, %rsp .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .LBB1_86: .cfi_def_cfa_offset 176 callq _ZSt16__throw_bad_castv .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z7add_vecPiS_S_m, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z7add_vecPiS_S_m,@object # @_Z7add_vecPiS_S_m .section .rodata,"a",@progbits .globl _Z7add_vecPiS_S_m .p2align 3, 0x0 _Z7add_vecPiS_S_m: .quad _Z22__device_stub__add_vecPiS_S_m .size _Z7add_vecPiS_S_m, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z7add_vecPiS_S_m" .size .L__unnamed_1, 18 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z22__device_stub__add_vecPiS_S_m .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z7add_vecPiS_S_m .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include "includes.h" __global__ void sortKernelSimple(int *arr, int arr_len, int odd) { int i = 2 * (blockIdx.x * blockDim.x + threadIdx.x) + odd; if (i < arr_len - 1) { //Even int a = arr[i]; int b = arr[i + 1]; if (a > b) { arr[i] = b; arr[i + 1] = a; } } }
code for sm_80 Function : _Z16sortKernelSimplePiii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */ /* 0x000e220000002500 */ /*0020*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */ /* 0x000fe40000000800 */ /*0030*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */ /* 0x000fe2000fffe03f */ /*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */ /* 0x000e240000002100 */ /*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */ /* 0x001fca00078e0203 */ /*0060*/ LEA R0, R0, c[0x0][0x16c], 0x1 ; /* 0x00005b0000007a11 */ /* 0x000fc800078e08ff */ /*0070*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */ /* 0x000fda000bf06270 */ /*0080*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*0090*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */ /* 0x000fe200000001ff */ /*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fd20000000a00 */ /*00b0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */ /* 0x000fca00078e0203 */ /*00c0*/ LDG.E R5, [R2.64+0x4] ; /* 0x0000040402057981 */ /* 0x000ea8000c1e1900 */ /*00d0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */ /* 0x000ea4000c1e1900 */ /*00e0*/ ISETP.GT.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */ /* 0x004fda0003f04270 */ /*00f0*/ @!P0 EXIT ; /* 0x000000000000894d */ /* 0x000fea0003800000 */ /*0100*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */ /* 0x000fe8000c101904 */ /*0110*/ STG.E [R2.64+0x4], R0 ; /* 0x0000040002007986 */ /* 0x000fe2000c101904 */ /*0120*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0130*/ BRA 0x130; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0140*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0150*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0160*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0170*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0180*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0190*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include "includes.h" __global__ void sortKernelSimple(int *arr, int arr_len, int odd) { int i = 2 * (blockIdx.x * blockDim.x + threadIdx.x) + odd; if (i < arr_len - 1) { //Even int a = arr[i]; int b = arr[i + 1]; if (a > b) { arr[i] = b; arr[i + 1] = a; } } }
.file "tmpxft_00193084_00000000-6_sortKernelSimple.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z38__device_stub__Z16sortKernelSimplePiiiPiii .type _Z38__device_stub__Z16sortKernelSimplePiiiPiii, @function _Z38__device_stub__Z16sortKernelSimplePiiiPiii: .LFB2051: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movl %esi, 4(%rsp) movl %edx, (%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) leaq 4(%rsp), %rax movq %rax, 88(%rsp) movq %rsp, %rax movq %rax, 96(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 104(%rsp), %rax subq %fs:40, %rax jne .L8 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z16sortKernelSimplePiii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z38__device_stub__Z16sortKernelSimplePiiiPiii, .-_Z38__device_stub__Z16sortKernelSimplePiiiPiii .globl _Z16sortKernelSimplePiii .type _Z16sortKernelSimplePiii, @function _Z16sortKernelSimplePiii: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z38__device_stub__Z16sortKernelSimplePiiiPiii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z16sortKernelSimplePiii, .-_Z16sortKernelSimplePiii .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z16sortKernelSimplePiii" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z16sortKernelSimplePiii(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include "includes.h" __global__ void sortKernelSimple(int *arr, int arr_len, int odd) { int i = 2 * (blockIdx.x * blockDim.x + threadIdx.x) + odd; if (i < arr_len - 1) { //Even int a = arr[i]; int b = arr[i + 1]; if (a > b) { arr[i] = b; arr[i + 1] = a; } } }
#include <hip/hip_runtime.h> #include "includes.h" __global__ void sortKernelSimple(int *arr, int arr_len, int odd) { int i = 2 * (blockIdx.x * blockDim.x + threadIdx.x) + odd; if (i < arr_len - 1) { //Even int a = arr[i]; int b = arr[i + 1]; if (a > b) { arr[i] = b; arr[i + 1] = a; } } }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <hip/hip_runtime.h> #include "includes.h" __global__ void sortKernelSimple(int *arr, int arr_len, int odd) { int i = 2 * (blockIdx.x * blockDim.x + threadIdx.x) + odd; if (i < arr_len - 1) { //Even int a = arr[i]; int b = arr[i + 1]; if (a > b) { arr[i] = b; arr[i + 1] = a; } } }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z16sortKernelSimplePiii .globl _Z16sortKernelSimplePiii .p2align 8 .type _Z16sortKernelSimplePiii,@function _Z16sortKernelSimplePiii: s_clause 0x1 s_load_b32 s4, s[0:1], 0x1c s_load_b64 s[2:3], s[0:1], 0x8 s_waitcnt lgkmcnt(0) s_and_b32 s4, s4, 0xffff s_add_i32 s2, s2, -1 v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshl_add_u32 v0, v1, 1, s3 v_cmp_gt_i32_e32 vcc_lo, s2, v0 s_and_saveexec_b32 s2, vcc_lo s_cbranch_execz .LBB0_3 s_load_b64 s[0:1], s[0:1], 0x0 v_ashrrev_i32_e32 v1, 31, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[0:1] s_waitcnt lgkmcnt(0) v_add_co_u32 v0, vcc_lo, s0, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo global_load_b64 v[2:3], v[0:1], off s_waitcnt vmcnt(0) v_cmp_gt_i32_e32 vcc_lo, v2, v3 s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_3 v_mov_b32_e32 v4, v2 global_store_b64 v[0:1], v[3:4], off .LBB0_3: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z16sortKernelSimplePiii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 272 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 5 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z16sortKernelSimplePiii, .Lfunc_end0-_Z16sortKernelSimplePiii .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 4 .value_kind: by_value - .offset: 12 .size: 4 .value_kind: by_value - .offset: 16 .size: 4 .value_kind: hidden_block_count_x - .offset: 20 .size: 4 .value_kind: hidden_block_count_y - .offset: 24 .size: 4 .value_kind: hidden_block_count_z - .offset: 28 .size: 2 .value_kind: hidden_group_size_x - .offset: 30 .size: 2 .value_kind: hidden_group_size_y - .offset: 32 .size: 2 .value_kind: hidden_group_size_z - .offset: 34 .size: 2 .value_kind: hidden_remainder_x - .offset: 36 .size: 2 .value_kind: hidden_remainder_y - .offset: 38 .size: 2 .value_kind: hidden_remainder_z - .offset: 56 .size: 8 .value_kind: hidden_global_offset_x - .offset: 64 .size: 8 .value_kind: hidden_global_offset_y - .offset: 72 .size: 8 .value_kind: hidden_global_offset_z - .offset: 80 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 272 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z16sortKernelSimplePiii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z16sortKernelSimplePiii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 5 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <hip/hip_runtime.h> #include "includes.h" __global__ void sortKernelSimple(int *arr, int arr_len, int odd) { int i = 2 * (blockIdx.x * blockDim.x + threadIdx.x) + odd; if (i < arr_len - 1) { //Even int a = arr[i]; int b = arr[i + 1]; if (a > b) { arr[i] = b; arr[i + 1] = a; } } }
.text .file "sortKernelSimple.hip" .globl _Z31__device_stub__sortKernelSimplePiii # -- Begin function _Z31__device_stub__sortKernelSimplePiii .p2align 4, 0x90 .type _Z31__device_stub__sortKernelSimplePiii,@function _Z31__device_stub__sortKernelSimplePiii: # @_Z31__device_stub__sortKernelSimplePiii .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movl %esi, 4(%rsp) movl %edx, (%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 4(%rsp), %rax movq %rax, 72(%rsp) movq %rsp, %rax movq %rax, 80(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z16sortKernelSimplePiii, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end0: .size _Z31__device_stub__sortKernelSimplePiii, .Lfunc_end0-_Z31__device_stub__sortKernelSimplePiii .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z16sortKernelSimplePiii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z16sortKernelSimplePiii,@object # @_Z16sortKernelSimplePiii .section .rodata,"a",@progbits .globl _Z16sortKernelSimplePiii .p2align 3, 0x0 _Z16sortKernelSimplePiii: .quad _Z31__device_stub__sortKernelSimplePiii .size _Z16sortKernelSimplePiii, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z16sortKernelSimplePiii" .size .L__unnamed_1, 25 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z31__device_stub__sortKernelSimplePiii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z16sortKernelSimplePiii .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z16sortKernelSimplePiii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */ /* 0x000e220000002500 */ /*0020*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */ /* 0x000fe40000000800 */ /*0030*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */ /* 0x000fe2000fffe03f */ /*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */ /* 0x000e240000002100 */ /*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */ /* 0x001fca00078e0203 */ /*0060*/ LEA R0, R0, c[0x0][0x16c], 0x1 ; /* 0x00005b0000007a11 */ /* 0x000fc800078e08ff */ /*0070*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */ /* 0x000fda000bf06270 */ /*0080*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*0090*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */ /* 0x000fe200000001ff */ /*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fd20000000a00 */ /*00b0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */ /* 0x000fca00078e0203 */ /*00c0*/ LDG.E R5, [R2.64+0x4] ; /* 0x0000040402057981 */ /* 0x000ea8000c1e1900 */ /*00d0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */ /* 0x000ea4000c1e1900 */ /*00e0*/ ISETP.GT.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */ /* 0x004fda0003f04270 */ /*00f0*/ @!P0 EXIT ; /* 0x000000000000894d */ /* 0x000fea0003800000 */ /*0100*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */ /* 0x000fe8000c101904 */ /*0110*/ STG.E [R2.64+0x4], R0 ; /* 0x0000040002007986 */ /* 0x000fe2000c101904 */ /*0120*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0130*/ BRA 0x130; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0140*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0150*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0160*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0170*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0180*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0190*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z16sortKernelSimplePiii .globl _Z16sortKernelSimplePiii .p2align 8 .type _Z16sortKernelSimplePiii,@function _Z16sortKernelSimplePiii: s_clause 0x1 s_load_b32 s4, s[0:1], 0x1c s_load_b64 s[2:3], s[0:1], 0x8 s_waitcnt lgkmcnt(0) s_and_b32 s4, s4, 0xffff s_add_i32 s2, s2, -1 v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshl_add_u32 v0, v1, 1, s3 v_cmp_gt_i32_e32 vcc_lo, s2, v0 s_and_saveexec_b32 s2, vcc_lo s_cbranch_execz .LBB0_3 s_load_b64 s[0:1], s[0:1], 0x0 v_ashrrev_i32_e32 v1, 31, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[0:1] s_waitcnt lgkmcnt(0) v_add_co_u32 v0, vcc_lo, s0, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo global_load_b64 v[2:3], v[0:1], off s_waitcnt vmcnt(0) v_cmp_gt_i32_e32 vcc_lo, v2, v3 s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_3 v_mov_b32_e32 v4, v2 global_store_b64 v[0:1], v[3:4], off .LBB0_3: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z16sortKernelSimplePiii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 272 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 5 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z16sortKernelSimplePiii, .Lfunc_end0-_Z16sortKernelSimplePiii .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 4 .value_kind: by_value - .offset: 12 .size: 4 .value_kind: by_value - .offset: 16 .size: 4 .value_kind: hidden_block_count_x - .offset: 20 .size: 4 .value_kind: hidden_block_count_y - .offset: 24 .size: 4 .value_kind: hidden_block_count_z - .offset: 28 .size: 2 .value_kind: hidden_group_size_x - .offset: 30 .size: 2 .value_kind: hidden_group_size_y - .offset: 32 .size: 2 .value_kind: hidden_group_size_z - .offset: 34 .size: 2 .value_kind: hidden_remainder_x - .offset: 36 .size: 2 .value_kind: hidden_remainder_y - .offset: 38 .size: 2 .value_kind: hidden_remainder_z - .offset: 56 .size: 8 .value_kind: hidden_global_offset_x - .offset: 64 .size: 8 .value_kind: hidden_global_offset_y - .offset: 72 .size: 8 .value_kind: hidden_global_offset_z - .offset: 80 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 272 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z16sortKernelSimplePiii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z16sortKernelSimplePiii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 5 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_00193084_00000000-6_sortKernelSimple.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z38__device_stub__Z16sortKernelSimplePiiiPiii .type _Z38__device_stub__Z16sortKernelSimplePiiiPiii, @function _Z38__device_stub__Z16sortKernelSimplePiiiPiii: .LFB2051: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movl %esi, 4(%rsp) movl %edx, (%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) leaq 4(%rsp), %rax movq %rax, 88(%rsp) movq %rsp, %rax movq %rax, 96(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 104(%rsp), %rax subq %fs:40, %rax jne .L8 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z16sortKernelSimplePiii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z38__device_stub__Z16sortKernelSimplePiiiPiii, .-_Z38__device_stub__Z16sortKernelSimplePiiiPiii .globl _Z16sortKernelSimplePiii .type _Z16sortKernelSimplePiii, @function _Z16sortKernelSimplePiii: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z38__device_stub__Z16sortKernelSimplePiiiPiii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z16sortKernelSimplePiii, .-_Z16sortKernelSimplePiii .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z16sortKernelSimplePiii" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z16sortKernelSimplePiii(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "sortKernelSimple.hip" .globl _Z31__device_stub__sortKernelSimplePiii # -- Begin function _Z31__device_stub__sortKernelSimplePiii .p2align 4, 0x90 .type _Z31__device_stub__sortKernelSimplePiii,@function _Z31__device_stub__sortKernelSimplePiii: # @_Z31__device_stub__sortKernelSimplePiii .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movl %esi, 4(%rsp) movl %edx, (%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 4(%rsp), %rax movq %rax, 72(%rsp) movq %rsp, %rax movq %rax, 80(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z16sortKernelSimplePiii, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end0: .size _Z31__device_stub__sortKernelSimplePiii, .Lfunc_end0-_Z31__device_stub__sortKernelSimplePiii .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z16sortKernelSimplePiii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z16sortKernelSimplePiii,@object # @_Z16sortKernelSimplePiii .section .rodata,"a",@progbits .globl _Z16sortKernelSimplePiii .p2align 3, 0x0 _Z16sortKernelSimplePiii: .quad _Z31__device_stub__sortKernelSimplePiii .size _Z16sortKernelSimplePiii, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z16sortKernelSimplePiii" .size .L__unnamed_1, 25 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z31__device_stub__sortKernelSimplePiii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z16sortKernelSimplePiii .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include <stdio.h> #include <stdlib.h> #include <sys/time.h> #include <time.h> #include <cuda_runtime.h> double my_timer() { struct timeval time; double _ret_val_0; gettimeofday(( & time), 0); _ret_val_0=(time.tv_sec+(time.tv_usec/1000000.0)); return _ret_val_0; } #define BLOCK_SIZE 16 void matrixMulCPU(int8_t *A, int8_t *B, int *C, int size){ int i, j, k; int sum; for(i = 0; i < size; i++){ for(j = 0; j < size; j++){ sum = 0; for(k = 0; k < size; k++){ sum += A[i * size + k] * B[j * size + k]; } C[i * size + j] = sum; } } } __global__ void matrixMulGPU(int8_t *A, int8_t *B, int *C, int width){ // Block index int bx = blockIdx.x; int by = blockIdx.y; // Thread index int tx = threadIdx.x; int ty = threadIdx.y; // Index of the first sub-matrix of A processed by the block int aBegin = width * BLOCK_SIZE * by; // Index of the last sub-matrix of A processed by the block int aEnd = aBegin + width - 1; // Step size used to iterate through the sub-matrices of A int aStep = BLOCK_SIZE; // Index of the first sub-matrix of B processed by the block int bBegin = width * BLOCK_SIZE * bx; // Step size used to iterate through the sub-matrices of B int bStep = BLOCK_SIZE; // Csub is used to store the element of the block sub-matrix // that is computed by the thread int Csub = 0; // Loop over all the sub-matrices of A and B // required to compute the block sub-matrix for (int a = aBegin, b = bBegin; a <= aEnd; a += aStep, b += bStep) { // Declaration of the shared memory array As used to // store the sub-matrix of A __shared__ int8_t As[BLOCK_SIZE][BLOCK_SIZE]; // Declaration of the shared memory array Bs used to // store the sub-matrix of B __shared__ int8_t Bs[BLOCK_SIZE][BLOCK_SIZE]; // Load the matrices from device memory // to shared memory; each thread loads // one element of each matrix As[ty][tx] = A[a + width * ty + tx]; Bs[ty][tx] = B[b + width * ty + tx]; // Synchronize to make sure the matrices are loaded __syncthreads(); // Multiply the two matrices together; // each thread computes one element // of the block sub-matrix #pragma unroll for (int k = 0; k < BLOCK_SIZE; ++k) { Csub += (int)As[ty][k] * (int)Bs[tx][k]; } // Synchronize to make sure that the preceding // computation is done before loading two new // sub-matrices of A and B in the next iteration __syncthreads(); } // Write the block sub-matrix to device memory; // each thread writes one element int c = width * BLOCK_SIZE * by + BLOCK_SIZE * bx; C[c + width * ty + tx] = Csub; } int main(int argc, char *argv[]){ int i; int8_t *A, *B; int *C, *D; int8_t *A_dev, *B_dev; int *C_dev; double start_timer, end_timer; int width, MSIZE; if(argc < 2){ printf("Error input options\n"); exit(1); } width = atoi(argv[1]); MSIZE = width * width; A = (int8_t*)malloc(sizeof(int8_t)*MSIZE); cudaMalloc(&A_dev, MSIZE*sizeof(int8_t)); B = (int8_t*)malloc(sizeof(int8_t)*MSIZE); cudaMalloc(&B_dev, MSIZE*sizeof(int8_t)); C = (int*)malloc(sizeof(int)*MSIZE); cudaMalloc(&C_dev, MSIZE*sizeof(int)); D = (int*)malloc(sizeof(int)*MSIZE); srand(time(NULL)); // Init matrix for(i = 0; i < MSIZE; i++){ A[i] = 1;//(rand() % 16) - 8; B[i] = 1;//(rand() % 16) - 8; C[i] = 0; D[i] = 0; } cudaMemcpy(A_dev, A, MSIZE*sizeof(int8_t), cudaMemcpyHostToDevice); cudaMemcpy(B_dev, B, MSIZE*sizeof(int8_t), cudaMemcpyHostToDevice); cudaMemcpy(C_dev, C, MSIZE*sizeof(int), cudaMemcpyHostToDevice); cudaDeviceSynchronize(); /*thread blcok conf.*/ dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE); dim3 grid(width/dimBlock.x, width/dimBlock.y); start_timer = my_timer(); matrixMulGPU<<<grid, dimBlock>>>(A_dev, B_dev, C_dev, width); cudaDeviceSynchronize(); end_timer = my_timer(); printf("The GPU Elapsed Time:%lf Sec.\n", end_timer - start_timer); cudaMemcpy(C, C_dev, MSIZE*sizeof(int), cudaMemcpyDeviceToHost); cudaDeviceSynchronize(); start_timer = my_timer(); matrixMulCPU(A, B, D, width); end_timer = my_timer(); printf("The CPU Elapsed Time:%lf Sec.\n", end_timer - start_timer); //Verification printf("Verifying\n"); int flag = 0; for(i = 0; i < MSIZE; i++){ if(abs(C[i] - D[i]) > 1e-3){ printf("Error:%d, %d, %d\n", C[i], D[i], i); break; } flag ++; } if(flag == MSIZE) printf("Verify Success!!\n"); // memory free free(A); cudaFree(A_dev); free(B); cudaFree(B_dev); free(C); cudaFree(C_dev); free(D); return 0; }
code for sm_80 Function : _Z12matrixMulGPUPaS_Pii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */ /* 0x000e220000002500 */ /*0020*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */ /* 0x000fe20003f01270 */ /*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fe40000000a00 */ /*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */ /* 0x000e280000002100 */ /*0050*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */ /* 0x000e680000002600 */ /*0060*/ S2R R4, SR_TID.Y ; /* 0x0000000000047919 */ /* 0x000ea40000002200 */ /*0070*/ @!P0 IMAD.MOV.U32 R15, RZ, RZ, RZ ; /* 0x000000ffff0f8224 */ /* 0x000fc400078e00ff */ /*0080*/ IMAD R3, R5, 0x10, R0 ; /* 0x0000001005037824 */ /* 0x001fe400078e0200 */ /*0090*/ IMAD R2, R7, c[0x0][0x178], RZ ; /* 0x00005e0007027a24 */ /* 0x002fe400078e02ff */ /*00a0*/ IMAD R3, R4, c[0x0][0x178], R3 ; /* 0x00005e0004037a24 */ /* 0x004fe400078e0203 */ /*00b0*/ IMAD.SHL.U32 R12, R2, 0x10, RZ ; /* 0x00000010020c7824 */ /* 0x000fe400078e00ff */ /*00c0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */ /* 0x000fe400078e00ff */ /*00d0*/ IMAD.IADD R3, R12, 0x1, R3 ; /* 0x000000010c037824 */ /* 0x000fc800078e0203 */ /*00e0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */ /* 0x000fe200078e0202 */ /*00f0*/ @!P0 BRA 0x690 ; /* 0x0000059000008947 */ /* 0x000fea0003800000 */ /*0100*/ IMAD R5, R5, 0x10, R4.reuse ; /* 0x0000001005057824 */ /* 0x100fe400078e0204 */ /*0110*/ IMAD R7, R7, 0x10, R4 ; /* 0x0000001007077824 */ /* 0x000fe400078e0204 */ /*0120*/ IMAD R5, R5, c[0x0][0x178], R0.reuse ; /* 0x00005e0005057a24 */ /* 0x100fe400078e0200 */ /*0130*/ IMAD R6, R7, c[0x0][0x178], R0.reuse ; /* 0x00005e0007067a24 */ /* 0x100fe200078e0200 */ /*0140*/ IADD3 R7, R12, c[0x0][0x178], RZ ; /* 0x00005e000c077a10 */ /* 0x000fe20007ffe0ff */ /*0150*/ IMAD.SHL.U32 R9, R4, 0x10, RZ ; /* 0x0000001004097824 */ /* 0x000fe200078e00ff */ /*0160*/ IADD3 R8, P0, R5, c[0x0][0x168], RZ ; /* 0x00005a0005087a10 */ /* 0x000fe20007f1e0ff */ /*0170*/ IMAD.MOV.U32 R15, RZ, RZ, RZ ; /* 0x000000ffff0f7224 */ /* 0x000fe200078e00ff */ /*0180*/ IADD3 R10, P1, R6, c[0x0][0x160], RZ ; /* 0x00005800060a7a10 */ /* 0x000fe20007f3e0ff */ /*0190*/ IMAD.IADD R9, R9, 0x1, R0 ; /* 0x0000000109097824 */ /* 0x000fe200078e0200 */ /*01a0*/ LEA.HI.X.SX32 R11, R5, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b00050b7a11 */ /* 0x000fc400000f0eff */ /*01b0*/ LEA.HI.X.SX32 R5, R6, c[0x0][0x164], 0x1, P1 ; /* 0x0000590006057a11 */ /* 0x000fc600008f0eff */ /*01c0*/ IMAD.MOV.U32 R16, RZ, RZ, R10 ; /* 0x000000ffff107224 */ /* 0x000fe400078e000a */ /*01d0*/ IMAD.MOV.U32 R17, RZ, RZ, R5 ; /* 0x000000ffff117224 */ /* 0x000fe400078e0005 */ /*01e0*/ IMAD.MOV.U32 R18, RZ, RZ, R8 ; /* 0x000000ffff127224 */ /* 0x000fe400078e0008 */ /*01f0*/ IMAD.MOV.U32 R19, RZ, RZ, R11 ; /* 0x000000ffff137224 */ /* 0x000fe200078e000b */ /*0200*/ LDG.E.U8 R6, [R16.64] ; /* 0x0000000410067981 */ /* 0x000ea8000c1e1100 */ /*0210*/ LDG.E.U8 R14, [R18.64] ; /* 0x00000004120e7981 */ /* 0x000ee2000c1e1100 */ /*0220*/ IADD3 R12, R12, 0x10, RZ ; /* 0x000000100c0c7810 */ /* 0x000fc40007ffe0ff */ /*0230*/ IADD3 R10, P2, R10, 0x10, RZ ; /* 0x000000100a0a7810 */ /* 0x000fe40007f5e0ff */ /*0240*/ ISETP.GE.AND P0, PT, R12, R7, PT ; /* 0x000000070c00720c */ /* 0x000fe40003f06270 */ /*0250*/ IADD3 R8, P1, R8, 0x10, RZ ; /* 0x0000001008087810 */ /* 0x000fe20007f3e0ff */ /*0260*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */ /* 0x000fc800010e0605 */ /*0270*/ IMAD.X R11, RZ, RZ, R11, P1 ; /* 0x000000ffff0b7224 */ /* 0x000fe200008e060b */ /*0280*/ STS.U8 [R9], R6 ; /* 0x0000000609007388 */ /* 0x004fe80000000000 */ /*0290*/ STS.U8 [R9+0x100], R14 ; /* 0x0001000e09007388 */ /* 0x008fe80000000000 */ /*02a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*02b0*/ LDS.U8 R13, [R0.X16+0x100] ; /* 0x00010000000d7984 */ /* 0x000fe8000000c000 */ /*02c0*/ LDS.U8 R20, [R0.X16+0x101] ; /* 0x0001010000147984 */ /* 0x000e28000000c000 */ /*02d0*/ LDS.U8 R21, [R0.X16+0x102] ; /* 0x0001020000157984 */ /* 0x000fe8000000c000 */ /*02e0*/ LDS.U8 R26, [R0.X16+0x103] ; /* 0x00010300001a7984 */ /* 0x000e68000000c000 */ /*02f0*/ LDS.U8 R22, [R4.X16] ; /* 0x0000000004167984 */ /* 0x000fe8000000c000 */ /*0300*/ LDS.U8 R23, [R4.X16+0x1] ; /* 0x0000010004177984 */ /* 0x000ea8000000c000 */ /*0310*/ LDS.U8 R24, [R4.X16+0x2] ; /* 0x0000020004187984 */ /* 0x000fe8000000c000 */ /*0320*/ LDS.U8 R25, [R4.X16+0x3] ; /* 0x0000030004197984 */ /* 0x000ee8000000c000 */ /*0330*/ LDS.U8 R6, [R0.X16+0x104] ; /* 0x0001040000067984 */ /* 0x000fe8000000c000 */ /*0340*/ LDS.U8 R17, [R0.X16+0x106] ; /* 0x0001060000117984 */ /* 0x000fe8000000c000 */ /*0350*/ LDS.U8 R18, [R4.X16+0x4] ; /* 0x0000040004127984 */ /* 0x000fe2000000c000 */ /*0360*/ PRMT R16, R20, 0x7604, R13 ; /* 0x0000760414107816 */ /* 0x001fc6000000000d */ /*0370*/ LDS.U8 R14, [R4.X16+0x6] ; /* 0x00000600040e7984 */ /* 0x000fe8000000c000 */ /*0380*/ LDS.U8 R13, [R0.X16+0x105] ; /* 0x00010500000d7984 */ /* 0x000e22000000c000 */ /*0390*/ PRMT R27, R26, 0x7604, R21 ; /* 0x000076041a1b7816 */ /* 0x002fc60000000015 */ /*03a0*/ LDS.U8 R20, [R0.X16+0x107] ; /* 0x0001070000147984 */ /* 0x000e62000000c000 */ /*03b0*/ PRMT R16, R27, 0x1054, R16 ; /* 0x000010541b107816 */ /* 0x000fc60000000010 */ /*03c0*/ LDS.U8 R21, [R4.X16+0x5] ; /* 0x0000050004157984 */ /* 0x000f22000000c000 */ /*03d0*/ PRMT R26, R23, 0x7604, R22 ; /* 0x00007604171a7816 */ /* 0x004fc60000000016 */ /*03e0*/ LDS.U8 R19, [R4.X16+0x7] ; /* 0x0000070004137984 */ /* 0x000ea8000000c000 */ /*03f0*/ LDS.U8 R22, [R0.X16+0x108] ; /* 0x0001080000167984 */ /* 0x000fe2000000c000 */ /*0400*/ PRMT R25, R25, 0x7604, R24 ; /* 0x0000760419197816 */ /* 0x008fc60000000018 */ /*0410*/ LDS.U8 R23, [R0.X16+0x109] ; /* 0x0001090000177984 */ /* 0x000ee2000000c000 */ /*0420*/ PRMT R26, R25, 0x1054, R26 ; /* 0x00001054191a7816 */ /* 0x000fc6000000001a */ /*0430*/ LDS.U8 R24, [R0.X16+0x10b] ; /* 0x00010b0000187984 */ /* 0x000fe8000000c000 */ /*0440*/ LDS.U8 R25, [R0.X16+0x10a] ; /* 0x00010a0000197984 */ /* 0x000f68000000c000 */ /*0450*/ LDS.U8 R28, [R4.X16+0xb] ; /* 0x00000b00041c7984 */ /* 0x000fe2000000c000 */ /*0460*/ PRMT R6, R13, 0x7604, R6 ; /* 0x000076040d067816 */ /* 0x001fc60000000006 */ /*0470*/ LDS.U8 R13, [R0.X16+0x10e] ; /* 0x00010e00000d7984 */ /* 0x000fe2000000c000 */ /*0480*/ PRMT R17, R20, 0x7604, R17 ; /* 0x0000760414117816 */ /* 0x002fc60000000011 */ /*0490*/ LDS.U8 R20, [R0.X16+0x10c] ; /* 0x00010c0000147984 */ /* 0x000fe2000000c000 */ /*04a0*/ PRMT R18, R21, 0x7604, R18 ; /* 0x0000760415127816 */ /* 0x010fe40000000012 */ /*04b0*/ PRMT R17, R17, 0x1054, R6 ; /* 0x0000105411117816 */ /* 0x000fe20000000006 */ /*04c0*/ IDP.4A.S8.S8 R6, R16, R26, R15 ; /* 0x0000001a10067226 */ /* 0x000fe2000000060f */ /*04d0*/ PRMT R19, R19, 0x7604, R14 ; /* 0x0000760413137816 */ /* 0x004fe2000000000e */ /*04e0*/ LDS.U8 R21, [R4.X16+0x8] ; /* 0x0000080004157984 */ /* 0x000fe6000000c000 */ /*04f0*/ PRMT R18, R19, 0x1054, R18 ; /* 0x0000105413127816 */ /* 0x000fe20000000012 */ /*0500*/ LDS.U8 R26, [R4.X16+0x9] ; /* 0x00000900041a7984 */ /* 0x000e22000000c000 */ /*0510*/ PRMT R22, R23, 0x7604, R22 ; /* 0x0000760417167816 */ /* 0x008fc60000000016 */ /*0520*/ IDP.4A.S8.S8 R6, R17, R18, R6 ; /* 0x0000001211067226 */ /* 0x000fe20000000606 */ /*0530*/ LDS.U8 R23, [R4.X16+0xa] ; /* 0x00000a0004177984 */ /* 0x000e68000000c000 */ /*0540*/ LDS.U8 R19, [R0.X16+0x10d] ; /* 0x00010d0000137984 */ /* 0x000ea2000000c000 */ /*0550*/ PRMT R25, R24, 0x7604, R25 ; /* 0x0000760418197816 */ /* 0x020fc60000000019 */ /*0560*/ LDS.U8 R18, [R0.X16+0x10f] ; /* 0x00010f0000127984 */ /* 0x000ee2000000c000 */ /*0570*/ PRMT R25, R25, 0x1054, R22 ; /* 0x0000105419197816 */ /* 0x000fc60000000016 */ /*0580*/ LDS.U8 R15, [R4.X16+0xc] ; /* 0x00000c00040f7984 */ /* 0x000fe8000000c000 */ /*0590*/ LDS.U8 R16, [R4.X16+0xd] ; /* 0x00000d0004107984 */ /* 0x000f28000000c000 */ /*05a0*/ LDS.U8 R14, [R4.X16+0xe] ; /* 0x00000e00040e7984 */ /* 0x000fe8000000c000 */ /*05b0*/ LDS.U8 R17, [R4.X16+0xf] ; /* 0x00000f0004117984 */ /* 0x000f62000000c000 */ /*05c0*/ PRMT R21, R26, 0x7604, R21 ; /* 0x000076041a157816 */ /* 0x001fc40000000015 */ /*05d0*/ PRMT R28, R28, 0x7604, R23 ; /* 0x000076041c1c7816 */ /* 0x002fc80000000017 */ /*05e0*/ PRMT R21, R28, 0x1054, R21 ; /* 0x000010541c157816 */ /* 0x000fe40000000015 */ /*05f0*/ PRMT R19, R19, 0x7604, R20 ; /* 0x0000760413137816 */ /* 0x004fe40000000014 */ /*0600*/ PRMT R18, R18, 0x7604, R13 ; /* 0x0000760412127816 */ /* 0x008fe2000000000d */ /*0610*/ IDP.4A.S8.S8 R6, R25, R21, R6 ; /* 0x0000001519067226 */ /* 0x000fc60000000606 */ /*0620*/ PRMT R19, R18, 0x1054, R19 ; /* 0x0000105412137816 */ /* 0x000fe40000000013 */ /*0630*/ PRMT R15, R16, 0x7604, R15 ; /* 0x00007604100f7816 */ /* 0x010fe4000000000f */ /*0640*/ PRMT R14, R17, 0x7604, R14 ; /* 0x00007604110e7816 */ /* 0x020fc8000000000e */ /*0650*/ PRMT R15, R14, 0x1054, R15 ; /* 0x000010540e0f7816 */ /* 0x000fca000000000f */ /*0660*/ IDP.4A.S8.S8 R15, R19, R15, R6 ; /* 0x0000000f130f7226 */ /* 0x000fe20000000606 */ /*0670*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*0680*/ @!P0 BRA 0x1c0 ; /* 0xfffffb3000008947 */ /* 0x000fea000383ffff */ /*0690*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */ /* 0x000fe2000c101904 */ /*06a0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*06b0*/ BRA 0x6b0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*06c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*06d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*06e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*06f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0700*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0710*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0720*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0730*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0740*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0750*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0760*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0770*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include <stdio.h> #include <stdlib.h> #include <sys/time.h> #include <time.h> #include <cuda_runtime.h> double my_timer() { struct timeval time; double _ret_val_0; gettimeofday(( & time), 0); _ret_val_0=(time.tv_sec+(time.tv_usec/1000000.0)); return _ret_val_0; } #define BLOCK_SIZE 16 void matrixMulCPU(int8_t *A, int8_t *B, int *C, int size){ int i, j, k; int sum; for(i = 0; i < size; i++){ for(j = 0; j < size; j++){ sum = 0; for(k = 0; k < size; k++){ sum += A[i * size + k] * B[j * size + k]; } C[i * size + j] = sum; } } } __global__ void matrixMulGPU(int8_t *A, int8_t *B, int *C, int width){ // Block index int bx = blockIdx.x; int by = blockIdx.y; // Thread index int tx = threadIdx.x; int ty = threadIdx.y; // Index of the first sub-matrix of A processed by the block int aBegin = width * BLOCK_SIZE * by; // Index of the last sub-matrix of A processed by the block int aEnd = aBegin + width - 1; // Step size used to iterate through the sub-matrices of A int aStep = BLOCK_SIZE; // Index of the first sub-matrix of B processed by the block int bBegin = width * BLOCK_SIZE * bx; // Step size used to iterate through the sub-matrices of B int bStep = BLOCK_SIZE; // Csub is used to store the element of the block sub-matrix // that is computed by the thread int Csub = 0; // Loop over all the sub-matrices of A and B // required to compute the block sub-matrix for (int a = aBegin, b = bBegin; a <= aEnd; a += aStep, b += bStep) { // Declaration of the shared memory array As used to // store the sub-matrix of A __shared__ int8_t As[BLOCK_SIZE][BLOCK_SIZE]; // Declaration of the shared memory array Bs used to // store the sub-matrix of B __shared__ int8_t Bs[BLOCK_SIZE][BLOCK_SIZE]; // Load the matrices from device memory // to shared memory; each thread loads // one element of each matrix As[ty][tx] = A[a + width * ty + tx]; Bs[ty][tx] = B[b + width * ty + tx]; // Synchronize to make sure the matrices are loaded __syncthreads(); // Multiply the two matrices together; // each thread computes one element // of the block sub-matrix #pragma unroll for (int k = 0; k < BLOCK_SIZE; ++k) { Csub += (int)As[ty][k] * (int)Bs[tx][k]; } // Synchronize to make sure that the preceding // computation is done before loading two new // sub-matrices of A and B in the next iteration __syncthreads(); } // Write the block sub-matrix to device memory; // each thread writes one element int c = width * BLOCK_SIZE * by + BLOCK_SIZE * bx; C[c + width * ty + tx] = Csub; } int main(int argc, char *argv[]){ int i; int8_t *A, *B; int *C, *D; int8_t *A_dev, *B_dev; int *C_dev; double start_timer, end_timer; int width, MSIZE; if(argc < 2){ printf("Error input options\n"); exit(1); } width = atoi(argv[1]); MSIZE = width * width; A = (int8_t*)malloc(sizeof(int8_t)*MSIZE); cudaMalloc(&A_dev, MSIZE*sizeof(int8_t)); B = (int8_t*)malloc(sizeof(int8_t)*MSIZE); cudaMalloc(&B_dev, MSIZE*sizeof(int8_t)); C = (int*)malloc(sizeof(int)*MSIZE); cudaMalloc(&C_dev, MSIZE*sizeof(int)); D = (int*)malloc(sizeof(int)*MSIZE); srand(time(NULL)); // Init matrix for(i = 0; i < MSIZE; i++){ A[i] = 1;//(rand() % 16) - 8; B[i] = 1;//(rand() % 16) - 8; C[i] = 0; D[i] = 0; } cudaMemcpy(A_dev, A, MSIZE*sizeof(int8_t), cudaMemcpyHostToDevice); cudaMemcpy(B_dev, B, MSIZE*sizeof(int8_t), cudaMemcpyHostToDevice); cudaMemcpy(C_dev, C, MSIZE*sizeof(int), cudaMemcpyHostToDevice); cudaDeviceSynchronize(); /*thread blcok conf.*/ dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE); dim3 grid(width/dimBlock.x, width/dimBlock.y); start_timer = my_timer(); matrixMulGPU<<<grid, dimBlock>>>(A_dev, B_dev, C_dev, width); cudaDeviceSynchronize(); end_timer = my_timer(); printf("The GPU Elapsed Time:%lf Sec.\n", end_timer - start_timer); cudaMemcpy(C, C_dev, MSIZE*sizeof(int), cudaMemcpyDeviceToHost); cudaDeviceSynchronize(); start_timer = my_timer(); matrixMulCPU(A, B, D, width); end_timer = my_timer(); printf("The CPU Elapsed Time:%lf Sec.\n", end_timer - start_timer); //Verification printf("Verifying\n"); int flag = 0; for(i = 0; i < MSIZE; i++){ if(abs(C[i] - D[i]) > 1e-3){ printf("Error:%d, %d, %d\n", C[i], D[i], i); break; } flag ++; } if(flag == MSIZE) printf("Verify Success!!\n"); // memory free free(A); cudaFree(A_dev); free(B); cudaFree(B_dev); free(C); cudaFree(C_dev); free(D); return 0; }
.file "tmpxft_000587e4_00000000-6_matrixMul8.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2062: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2062: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z8my_timerv .type _Z8my_timerv, @function _Z8my_timerv: .LFB2057: .cfi_startproc endbr64 subq $40, %rsp .cfi_def_cfa_offset 48 movq %fs:40, %rax movq %rax, 24(%rsp) xorl %eax, %eax movq %rsp, %rdi movl $0, %esi call gettimeofday@PLT pxor %xmm0, %xmm0 cvtsi2sdq 8(%rsp), %xmm0 divsd .LC0(%rip), %xmm0 pxor %xmm1, %xmm1 cvtsi2sdq (%rsp), %xmm1 addsd %xmm1, %xmm0 movq 24(%rsp), %rax subq %fs:40, %rax jne .L6 addq $40, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L6: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size _Z8my_timerv, .-_Z8my_timerv .globl _Z12matrixMulCPUPaS_Pii .type _Z12matrixMulCPUPaS_Pii, @function _Z12matrixMulCPUPaS_Pii: .LFB2058: .cfi_startproc endbr64 testl %ecx, %ecx jle .L15 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 movq %rdi, %r9 movq %rsi, %r12 movq %rdx, %r11 movl %ecx, %ebp movslq %ecx, %r8 leaq 0(,%r8,4), %r14 addq %r14, %r11 movq %r8, %r13 negq %r13 salq $2, %r13 movl $0, %ebx .L9: leaq (%r11,%r13), %r10 movq %r12, %rdi .L12: movl $0, %eax movl $0, %ecx .L10: movsbl (%r9,%rax), %edx movsbl (%rdi,%rax), %esi imull %esi, %edx addl %edx, %ecx addq $1, %rax cmpq %r8, %rax jne .L10 movl %ecx, (%r10) addq $4, %r10 addq %r8, %rdi cmpq %r11, %r10 jne .L12 addl $1, %ebx addq %r14, %r11 addq %r8, %r9 cmpl %ebx, %ebp jne .L9 popq %rbx .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .L15: .cfi_restore 3 .cfi_restore 6 .cfi_restore 12 .cfi_restore 13 .cfi_restore 14 ret .cfi_endproc .LFE2058: .size _Z12matrixMulCPUPaS_Pii, .-_Z12matrixMulCPUPaS_Pii .globl _Z37__device_stub__Z12matrixMulGPUPaS_PiiPaS_Pii .type _Z37__device_stub__Z12matrixMulGPUPaS_PiiPaS_Pii, @function _Z37__device_stub__Z12matrixMulGPUPaS_PiiPaS_Pii: .LFB2084: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movl %ecx, 4(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L22 .L18: movq 136(%rsp), %rax subq %fs:40, %rax jne .L23 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L22: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z12matrixMulGPUPaS_Pii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L18 .L23: call __stack_chk_fail@PLT .cfi_endproc .LFE2084: .size _Z37__device_stub__Z12matrixMulGPUPaS_PiiPaS_Pii, .-_Z37__device_stub__Z12matrixMulGPUPaS_PiiPaS_Pii .globl _Z12matrixMulGPUPaS_Pii .type _Z12matrixMulGPUPaS_Pii, @function _Z12matrixMulGPUPaS_Pii: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z37__device_stub__Z12matrixMulGPUPaS_PiiPaS_Pii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _Z12matrixMulGPUPaS_Pii, .-_Z12matrixMulGPUPaS_Pii .section .rodata.str1.1,"aMS",@progbits,1 .LC1: .string "Error input options\n" .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC2: .string "The GPU Elapsed Time:%lf Sec.\n" .align 8 .LC3: .string "The CPU Elapsed Time:%lf Sec.\n" .section .rodata.str1.1 .LC4: .string "Verifying\n" .LC5: .string "Error:%d, %d, %d\n" .LC6: .string "Verify Success!!\n" .text .globl main .type main, @function main: .LFB2059: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $104, %rsp .cfi_def_cfa_offset 160 movq %fs:40, %rax movq %rax, 88(%rsp) xorl %eax, %eax cmpl $1, %edi jle .L40 movq 8(%rsi), %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT movq %rax, 24(%rsp) movl %eax, 20(%rsp) movl %eax, %r15d imull %eax, %r15d movslq %r15d, %rbx movq %rbx, %rdi call malloc@PLT movq %rax, %r14 leaq 40(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT movq %rbx, %rdi call malloc@PLT movq %rax, %r13 leaq 48(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq 0(,%rbx,4), %r12 movq %r12, 8(%rsp) movq %r12, %rdi call malloc@PLT movq %rax, %rbp leaq 56(%rsp), %rdi movq %r12, %rsi call cudaMalloc@PLT movq %r12, %rdi call malloc@PLT movq %rax, %r12 movl $0, %edi call time@PLT movl %eax, %edi call srand@PLT testl %r15d, %r15d jle .L28 movl $0, %eax .L29: movb $1, (%r14,%rax) movb $1, 0(%r13,%rax) movl $0, 0(%rbp,%rax,4) movl $0, (%r12,%rax,4) addq $1, %rax cmpq %rax, %rbx jne .L29 .L28: movl $1, %ecx movq %rbx, %rdx movq %r14, %rsi movq 40(%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movq %rbx, %rdx movq %r13, %rsi movq 48(%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movq 8(%rsp), %rdx movq %rbp, %rsi movq 56(%rsp), %rdi call cudaMemcpy@PLT call cudaDeviceSynchronize@PLT movl $1, 72(%rsp) movl 24(%rsp), %eax shrl $4, %eax movl %eax, 76(%rsp) movl %eax, 80(%rsp) movl $1, 84(%rsp) call _Z8my_timerv movsd %xmm0, 24(%rsp) movl $16, 64(%rsp) movl $16, 68(%rsp) movl 72(%rsp), %ecx movl $0, %r9d movl $0, %r8d movq 64(%rsp), %rdx movq 76(%rsp), %rdi movl 84(%rsp), %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L41 .L30: call cudaDeviceSynchronize@PLT call _Z8my_timerv subsd 24(%rsp), %xmm0 leaq .LC2(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT movl $2, %ecx movq 8(%rsp), %rdx movq 56(%rsp), %rsi movq %rbp, %rdi call cudaMemcpy@PLT call cudaDeviceSynchronize@PLT call _Z8my_timerv movsd %xmm0, 8(%rsp) movl 20(%rsp), %ecx movq %r12, %rdx movq %r13, %rsi movq %r14, %rdi call _Z12matrixMulCPUPaS_Pii call _Z8my_timerv subsd 8(%rsp), %xmm0 leaq .LC3(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT leaq .LC4(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT testl %r15d, %r15d jle .L31 movl $0, %r8d jmp .L34 .L40: leaq .LC1(%rip), %rsi movl $2, %edi call __printf_chk@PLT movl $1, %edi call exit@PLT .L41: movl 20(%rsp), %ecx movq 56(%rsp), %rdx movq 48(%rsp), %rsi movq 40(%rsp), %rdi call _Z37__device_stub__Z12matrixMulGPUPaS_PiiPaS_Pii jmp .L30 .L37: movq %rax, %r8 .L34: movl 0(%rbp,%r8,4), %esi movl (%r12,%r8,4), %ecx movl %esi, %edx subl %ecx, %edx movl %edx, %eax negl %eax cmovs %edx, %eax testl %eax, %eax jg .L42 leaq 1(%r8), %rax cmpq %rax, %rbx jne .L37 leal 1(%r8), %ebx jmp .L33 .L42: movl %r8d, %ebx movl %esi, %edx leaq .LC5(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT .L33: cmpl %ebx, %r15d je .L31 .L35: movq %r14, %rdi call free@PLT movq 40(%rsp), %rdi call cudaFree@PLT movq %r13, %rdi call free@PLT movq 48(%rsp), %rdi call cudaFree@PLT movq %rbp, %rdi call free@PLT movq 56(%rsp), %rdi call cudaFree@PLT movq %r12, %rdi call free@PLT movq 88(%rsp), %rax subq %fs:40, %rax jne .L43 movl $0, %eax addq $104, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L31: .cfi_restore_state leaq .LC6(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT jmp .L35 .L43: call __stack_chk_fail@PLT .cfi_endproc .LFE2059: .size main, .-main .section .rodata.str1.1 .LC7: .string "_Z12matrixMulGPUPaS_Pii" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2087: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC7(%rip), %rdx movq %rdx, %rcx leaq _Z12matrixMulGPUPaS_Pii(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2087: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst8,"aM",@progbits,8 .align 8 .LC0: .long 0 .long 1093567616 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include <stdio.h> #include <stdlib.h> #include <sys/time.h> #include <time.h> #include <cuda_runtime.h> double my_timer() { struct timeval time; double _ret_val_0; gettimeofday(( & time), 0); _ret_val_0=(time.tv_sec+(time.tv_usec/1000000.0)); return _ret_val_0; } #define BLOCK_SIZE 16 void matrixMulCPU(int8_t *A, int8_t *B, int *C, int size){ int i, j, k; int sum; for(i = 0; i < size; i++){ for(j = 0; j < size; j++){ sum = 0; for(k = 0; k < size; k++){ sum += A[i * size + k] * B[j * size + k]; } C[i * size + j] = sum; } } } __global__ void matrixMulGPU(int8_t *A, int8_t *B, int *C, int width){ // Block index int bx = blockIdx.x; int by = blockIdx.y; // Thread index int tx = threadIdx.x; int ty = threadIdx.y; // Index of the first sub-matrix of A processed by the block int aBegin = width * BLOCK_SIZE * by; // Index of the last sub-matrix of A processed by the block int aEnd = aBegin + width - 1; // Step size used to iterate through the sub-matrices of A int aStep = BLOCK_SIZE; // Index of the first sub-matrix of B processed by the block int bBegin = width * BLOCK_SIZE * bx; // Step size used to iterate through the sub-matrices of B int bStep = BLOCK_SIZE; // Csub is used to store the element of the block sub-matrix // that is computed by the thread int Csub = 0; // Loop over all the sub-matrices of A and B // required to compute the block sub-matrix for (int a = aBegin, b = bBegin; a <= aEnd; a += aStep, b += bStep) { // Declaration of the shared memory array As used to // store the sub-matrix of A __shared__ int8_t As[BLOCK_SIZE][BLOCK_SIZE]; // Declaration of the shared memory array Bs used to // store the sub-matrix of B __shared__ int8_t Bs[BLOCK_SIZE][BLOCK_SIZE]; // Load the matrices from device memory // to shared memory; each thread loads // one element of each matrix As[ty][tx] = A[a + width * ty + tx]; Bs[ty][tx] = B[b + width * ty + tx]; // Synchronize to make sure the matrices are loaded __syncthreads(); // Multiply the two matrices together; // each thread computes one element // of the block sub-matrix #pragma unroll for (int k = 0; k < BLOCK_SIZE; ++k) { Csub += (int)As[ty][k] * (int)Bs[tx][k]; } // Synchronize to make sure that the preceding // computation is done before loading two new // sub-matrices of A and B in the next iteration __syncthreads(); } // Write the block sub-matrix to device memory; // each thread writes one element int c = width * BLOCK_SIZE * by + BLOCK_SIZE * bx; C[c + width * ty + tx] = Csub; } int main(int argc, char *argv[]){ int i; int8_t *A, *B; int *C, *D; int8_t *A_dev, *B_dev; int *C_dev; double start_timer, end_timer; int width, MSIZE; if(argc < 2){ printf("Error input options\n"); exit(1); } width = atoi(argv[1]); MSIZE = width * width; A = (int8_t*)malloc(sizeof(int8_t)*MSIZE); cudaMalloc(&A_dev, MSIZE*sizeof(int8_t)); B = (int8_t*)malloc(sizeof(int8_t)*MSIZE); cudaMalloc(&B_dev, MSIZE*sizeof(int8_t)); C = (int*)malloc(sizeof(int)*MSIZE); cudaMalloc(&C_dev, MSIZE*sizeof(int)); D = (int*)malloc(sizeof(int)*MSIZE); srand(time(NULL)); // Init matrix for(i = 0; i < MSIZE; i++){ A[i] = 1;//(rand() % 16) - 8; B[i] = 1;//(rand() % 16) - 8; C[i] = 0; D[i] = 0; } cudaMemcpy(A_dev, A, MSIZE*sizeof(int8_t), cudaMemcpyHostToDevice); cudaMemcpy(B_dev, B, MSIZE*sizeof(int8_t), cudaMemcpyHostToDevice); cudaMemcpy(C_dev, C, MSIZE*sizeof(int), cudaMemcpyHostToDevice); cudaDeviceSynchronize(); /*thread blcok conf.*/ dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE); dim3 grid(width/dimBlock.x, width/dimBlock.y); start_timer = my_timer(); matrixMulGPU<<<grid, dimBlock>>>(A_dev, B_dev, C_dev, width); cudaDeviceSynchronize(); end_timer = my_timer(); printf("The GPU Elapsed Time:%lf Sec.\n", end_timer - start_timer); cudaMemcpy(C, C_dev, MSIZE*sizeof(int), cudaMemcpyDeviceToHost); cudaDeviceSynchronize(); start_timer = my_timer(); matrixMulCPU(A, B, D, width); end_timer = my_timer(); printf("The CPU Elapsed Time:%lf Sec.\n", end_timer - start_timer); //Verification printf("Verifying\n"); int flag = 0; for(i = 0; i < MSIZE; i++){ if(abs(C[i] - D[i]) > 1e-3){ printf("Error:%d, %d, %d\n", C[i], D[i], i); break; } flag ++; } if(flag == MSIZE) printf("Verify Success!!\n"); // memory free free(A); cudaFree(A_dev); free(B); cudaFree(B_dev); free(C); cudaFree(C_dev); free(D); return 0; }
#include <stdio.h> #include <stdlib.h> #include <sys/time.h> #include <time.h> #include <hip/hip_runtime.h> double my_timer() { struct timeval time; double _ret_val_0; gettimeofday(( & time), 0); _ret_val_0=(time.tv_sec+(time.tv_usec/1000000.0)); return _ret_val_0; } #define BLOCK_SIZE 16 void matrixMulCPU(int8_t *A, int8_t *B, int *C, int size){ int i, j, k; int sum; for(i = 0; i < size; i++){ for(j = 0; j < size; j++){ sum = 0; for(k = 0; k < size; k++){ sum += A[i * size + k] * B[j * size + k]; } C[i * size + j] = sum; } } } __global__ void matrixMulGPU(int8_t *A, int8_t *B, int *C, int width){ // Block index int bx = blockIdx.x; int by = blockIdx.y; // Thread index int tx = threadIdx.x; int ty = threadIdx.y; // Index of the first sub-matrix of A processed by the block int aBegin = width * BLOCK_SIZE * by; // Index of the last sub-matrix of A processed by the block int aEnd = aBegin + width - 1; // Step size used to iterate through the sub-matrices of A int aStep = BLOCK_SIZE; // Index of the first sub-matrix of B processed by the block int bBegin = width * BLOCK_SIZE * bx; // Step size used to iterate through the sub-matrices of B int bStep = BLOCK_SIZE; // Csub is used to store the element of the block sub-matrix // that is computed by the thread int Csub = 0; // Loop over all the sub-matrices of A and B // required to compute the block sub-matrix for (int a = aBegin, b = bBegin; a <= aEnd; a += aStep, b += bStep) { // Declaration of the shared memory array As used to // store the sub-matrix of A __shared__ int8_t As[BLOCK_SIZE][BLOCK_SIZE]; // Declaration of the shared memory array Bs used to // store the sub-matrix of B __shared__ int8_t Bs[BLOCK_SIZE][BLOCK_SIZE]; // Load the matrices from device memory // to shared memory; each thread loads // one element of each matrix As[ty][tx] = A[a + width * ty + tx]; Bs[ty][tx] = B[b + width * ty + tx]; // Synchronize to make sure the matrices are loaded __syncthreads(); // Multiply the two matrices together; // each thread computes one element // of the block sub-matrix #pragma unroll for (int k = 0; k < BLOCK_SIZE; ++k) { Csub += (int)As[ty][k] * (int)Bs[tx][k]; } // Synchronize to make sure that the preceding // computation is done before loading two new // sub-matrices of A and B in the next iteration __syncthreads(); } // Write the block sub-matrix to device memory; // each thread writes one element int c = width * BLOCK_SIZE * by + BLOCK_SIZE * bx; C[c + width * ty + tx] = Csub; } int main(int argc, char *argv[]){ int i; int8_t *A, *B; int *C, *D; int8_t *A_dev, *B_dev; int *C_dev; double start_timer, end_timer; int width, MSIZE; if(argc < 2){ printf("Error input options\n"); exit(1); } width = atoi(argv[1]); MSIZE = width * width; A = (int8_t*)malloc(sizeof(int8_t)*MSIZE); hipMalloc(&A_dev, MSIZE*sizeof(int8_t)); B = (int8_t*)malloc(sizeof(int8_t)*MSIZE); hipMalloc(&B_dev, MSIZE*sizeof(int8_t)); C = (int*)malloc(sizeof(int)*MSIZE); hipMalloc(&C_dev, MSIZE*sizeof(int)); D = (int*)malloc(sizeof(int)*MSIZE); srand(time(NULL)); // Init matrix for(i = 0; i < MSIZE; i++){ A[i] = 1;//(rand() % 16) - 8; B[i] = 1;//(rand() % 16) - 8; C[i] = 0; D[i] = 0; } hipMemcpy(A_dev, A, MSIZE*sizeof(int8_t), hipMemcpyHostToDevice); hipMemcpy(B_dev, B, MSIZE*sizeof(int8_t), hipMemcpyHostToDevice); hipMemcpy(C_dev, C, MSIZE*sizeof(int), hipMemcpyHostToDevice); hipDeviceSynchronize(); /*thread blcok conf.*/ dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE); dim3 grid(width/dimBlock.x, width/dimBlock.y); start_timer = my_timer(); matrixMulGPU<<<grid, dimBlock>>>(A_dev, B_dev, C_dev, width); hipDeviceSynchronize(); end_timer = my_timer(); printf("The GPU Elapsed Time:%lf Sec.\n", end_timer - start_timer); hipMemcpy(C, C_dev, MSIZE*sizeof(int), hipMemcpyDeviceToHost); hipDeviceSynchronize(); start_timer = my_timer(); matrixMulCPU(A, B, D, width); end_timer = my_timer(); printf("The CPU Elapsed Time:%lf Sec.\n", end_timer - start_timer); //Verification printf("Verifying\n"); int flag = 0; for(i = 0; i < MSIZE; i++){ if(abs(C[i] - D[i]) > 1e-3){ printf("Error:%d, %d, %d\n", C[i], D[i], i); break; } flag ++; } if(flag == MSIZE) printf("Verify Success!!\n"); // memory free free(A); hipFree(A_dev); free(B); hipFree(B_dev); free(C); hipFree(C_dev); free(D); return 0; }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <stdio.h> #include <stdlib.h> #include <sys/time.h> #include <time.h> #include <hip/hip_runtime.h> double my_timer() { struct timeval time; double _ret_val_0; gettimeofday(( & time), 0); _ret_val_0=(time.tv_sec+(time.tv_usec/1000000.0)); return _ret_val_0; } #define BLOCK_SIZE 16 void matrixMulCPU(int8_t *A, int8_t *B, int *C, int size){ int i, j, k; int sum; for(i = 0; i < size; i++){ for(j = 0; j < size; j++){ sum = 0; for(k = 0; k < size; k++){ sum += A[i * size + k] * B[j * size + k]; } C[i * size + j] = sum; } } } __global__ void matrixMulGPU(int8_t *A, int8_t *B, int *C, int width){ // Block index int bx = blockIdx.x; int by = blockIdx.y; // Thread index int tx = threadIdx.x; int ty = threadIdx.y; // Index of the first sub-matrix of A processed by the block int aBegin = width * BLOCK_SIZE * by; // Index of the last sub-matrix of A processed by the block int aEnd = aBegin + width - 1; // Step size used to iterate through the sub-matrices of A int aStep = BLOCK_SIZE; // Index of the first sub-matrix of B processed by the block int bBegin = width * BLOCK_SIZE * bx; // Step size used to iterate through the sub-matrices of B int bStep = BLOCK_SIZE; // Csub is used to store the element of the block sub-matrix // that is computed by the thread int Csub = 0; // Loop over all the sub-matrices of A and B // required to compute the block sub-matrix for (int a = aBegin, b = bBegin; a <= aEnd; a += aStep, b += bStep) { // Declaration of the shared memory array As used to // store the sub-matrix of A __shared__ int8_t As[BLOCK_SIZE][BLOCK_SIZE]; // Declaration of the shared memory array Bs used to // store the sub-matrix of B __shared__ int8_t Bs[BLOCK_SIZE][BLOCK_SIZE]; // Load the matrices from device memory // to shared memory; each thread loads // one element of each matrix As[ty][tx] = A[a + width * ty + tx]; Bs[ty][tx] = B[b + width * ty + tx]; // Synchronize to make sure the matrices are loaded __syncthreads(); // Multiply the two matrices together; // each thread computes one element // of the block sub-matrix #pragma unroll for (int k = 0; k < BLOCK_SIZE; ++k) { Csub += (int)As[ty][k] * (int)Bs[tx][k]; } // Synchronize to make sure that the preceding // computation is done before loading two new // sub-matrices of A and B in the next iteration __syncthreads(); } // Write the block sub-matrix to device memory; // each thread writes one element int c = width * BLOCK_SIZE * by + BLOCK_SIZE * bx; C[c + width * ty + tx] = Csub; } int main(int argc, char *argv[]){ int i; int8_t *A, *B; int *C, *D; int8_t *A_dev, *B_dev; int *C_dev; double start_timer, end_timer; int width, MSIZE; if(argc < 2){ printf("Error input options\n"); exit(1); } width = atoi(argv[1]); MSIZE = width * width; A = (int8_t*)malloc(sizeof(int8_t)*MSIZE); hipMalloc(&A_dev, MSIZE*sizeof(int8_t)); B = (int8_t*)malloc(sizeof(int8_t)*MSIZE); hipMalloc(&B_dev, MSIZE*sizeof(int8_t)); C = (int*)malloc(sizeof(int)*MSIZE); hipMalloc(&C_dev, MSIZE*sizeof(int)); D = (int*)malloc(sizeof(int)*MSIZE); srand(time(NULL)); // Init matrix for(i = 0; i < MSIZE; i++){ A[i] = 1;//(rand() % 16) - 8; B[i] = 1;//(rand() % 16) - 8; C[i] = 0; D[i] = 0; } hipMemcpy(A_dev, A, MSIZE*sizeof(int8_t), hipMemcpyHostToDevice); hipMemcpy(B_dev, B, MSIZE*sizeof(int8_t), hipMemcpyHostToDevice); hipMemcpy(C_dev, C, MSIZE*sizeof(int), hipMemcpyHostToDevice); hipDeviceSynchronize(); /*thread blcok conf.*/ dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE); dim3 grid(width/dimBlock.x, width/dimBlock.y); start_timer = my_timer(); matrixMulGPU<<<grid, dimBlock>>>(A_dev, B_dev, C_dev, width); hipDeviceSynchronize(); end_timer = my_timer(); printf("The GPU Elapsed Time:%lf Sec.\n", end_timer - start_timer); hipMemcpy(C, C_dev, MSIZE*sizeof(int), hipMemcpyDeviceToHost); hipDeviceSynchronize(); start_timer = my_timer(); matrixMulCPU(A, B, D, width); end_timer = my_timer(); printf("The CPU Elapsed Time:%lf Sec.\n", end_timer - start_timer); //Verification printf("Verifying\n"); int flag = 0; for(i = 0; i < MSIZE; i++){ if(abs(C[i] - D[i]) > 1e-3){ printf("Error:%d, %d, %d\n", C[i], D[i], i); break; } flag ++; } if(flag == MSIZE) printf("Verify Success!!\n"); // memory free free(A); hipFree(A_dev); free(B); hipFree(B_dev); free(C); hipFree(C_dev); free(D); return 0; }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z12matrixMulGPUPaS_Pii .globl _Z12matrixMulGPUPaS_Pii .p2align 8 .type _Z12matrixMulGPUPaS_Pii,@function _Z12matrixMulGPUPaS_Pii: s_load_b32 s3, s[0:1], 0x18 v_and_b32_e32 v1, 0x3ff, v0 v_bfe_u32 v0, v0, 10, 10 s_waitcnt lgkmcnt(0) s_mul_i32 s2, s3, s15 s_delay_alu instid0(SALU_CYCLE_1) s_lshl_b32 s8, s2, 4 s_cmp_lt_i32 s3, 1 s_cbranch_scc1 .LBB0_3 v_lshl_add_u32 v4, s14, 4, v0 s_load_b128 s[4:7], s[0:1], 0x0 v_lshl_add_u32 v37, s15, 4, v0 v_lshlrev_b32_e32 v5, 4, v0 v_lshlrev_b32_e32 v38, 4, v1 v_mad_u64_u32 v[2:3], null, s3, v4, v[1:2] s_add_i32 s9, s8, s3 s_mov_b32 s10, s8 s_delay_alu instid0(VALU_DEP_2) v_add_nc_u32_e32 v7, 0x100, v38 v_add_nc_u32_e32 v9, 0x101, v38 v_add_nc_u32_e32 v11, 0x102, v38 v_add_nc_u32_e32 v14, 0x103, v38 v_mad_u64_u32 v[3:4], null, s3, v37, v[1:2] v_mov_b32_e32 v4, 0 v_add_nc_u32_e32 v6, v5, v1 v_or_b32_e32 v8, 1, v5 v_or_b32_e32 v10, 2, v5 v_or_b32_e32 v12, 3, v5 v_or_b32_e32 v15, 4, v5 v_add_nc_u32_e32 v13, 0x100, v6 v_add_nc_u32_e32 v16, 0x104, v38 v_or_b32_e32 v17, 5, v5 v_add_nc_u32_e32 v18, 0x105, v38 v_or_b32_e32 v19, 6, v5 v_add_nc_u32_e32 v20, 0x106, v38 v_or_b32_e32 v21, 7, v5 v_add_nc_u32_e32 v22, 0x107, v38 v_or_b32_e32 v23, 8, v5 v_add_nc_u32_e32 v24, 0x108, v38 v_or_b32_e32 v25, 9, v5 v_add_nc_u32_e32 v26, 0x109, v38 v_or_b32_e32 v27, 10, v5 v_add_nc_u32_e32 v28, 0x10a, v38 v_or_b32_e32 v29, 11, v5 v_add_nc_u32_e32 v30, 0x10b, v38 v_or_b32_e32 v31, 12, v5 v_add_nc_u32_e32 v32, 0x10c, v38 v_or_b32_e32 v33, 13, v5 v_add_nc_u32_e32 v34, 0x10d, v38 v_or_b32_e32 v35, 14, v5 v_add_nc_u32_e32 v36, 0x10e, v38 v_or_b32_e32 v37, 15, v5 v_add_nc_u32_e32 v38, 0x10f, v38 .LBB0_2: v_ashrrev_i32_e32 v40, 31, v3 v_ashrrev_i32_e32 v43, 31, v2 s_waitcnt lgkmcnt(0) v_add_co_u32 v41, s2, s4, v3 v_add_co_u32 v39, vcc_lo, s6, v2 v_add_co_ci_u32_e64 v42, s2, s5, v40, s2 v_add_co_ci_u32_e32 v40, vcc_lo, s7, v43, vcc_lo global_load_u8 v41, v[41:42], off global_load_u8 v39, v[39:40], off v_add_nc_u32_e32 v2, 16, v2 v_add_nc_u32_e32 v3, 16, v3 s_add_i32 s10, s10, 16 s_waitcnt vmcnt(1) ds_store_b8 v6, v41 s_waitcnt vmcnt(0) ds_store_b8 v13, v39 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv ds_load_i8 v39, v5 ds_load_i8 v40, v7 ds_load_i8 v41, v8 ds_load_i8 v42, v9 ds_load_i8 v43, v10 ds_load_i8 v44, v11 ds_load_i8 v45, v12 ds_load_i8 v46, v14 ds_load_i8 v47, v15 ds_load_i8 v48, v16 ds_load_i8 v49, v17 ds_load_i8 v50, v18 ds_load_i8 v51, v19 ds_load_i8 v52, v20 ds_load_i8 v53, v21 ds_load_i8 v54, v22 ds_load_i8 v55, v29 ds_load_i8 v56, v23 ds_load_i8 v57, v24 ds_load_i8 v58, v25 ds_load_i8 v59, v26 ds_load_i8 v60, v27 ds_load_i8 v61, v28 ds_load_i8 v62, v30 ds_load_i8 v63, v31 ds_load_i8 v64, v33 ds_load_i8 v65, v35 ds_load_i8 v66, v37 ds_load_i8 v67, v32 ds_load_i8 v68, v34 ds_load_i8 v69, v36 ds_load_i8 v70, v38 s_waitcnt lgkmcnt(29) v_perm_b32 v39, v41, v39, 0xc0c0400 s_waitcnt lgkmcnt(25) v_perm_b32 v41, v45, v43, 0x4000c0c v_perm_b32 v40, v42, v40, 0xc0c0400 s_waitcnt lgkmcnt(24) v_perm_b32 v42, v46, v44, 0x4000c0c s_waitcnt lgkmcnt(21) v_perm_b32 v43, v49, v47, 0xc0c0400 s_waitcnt lgkmcnt(17) v_perm_b32 v44, v53, v51, 0x4000c0c v_perm_b32 v45, v50, v48, 0xc0c0400 s_waitcnt lgkmcnt(16) v_perm_b32 v46, v54, v52, 0x4000c0c v_or_b32_e32 v39, v41, v39 v_or_b32_e32 v40, v42, v40 s_waitcnt lgkmcnt(12) v_perm_b32 v47, v58, v56, 0xc0c0400 s_waitcnt lgkmcnt(10) v_perm_b32 v48, v55, v60, 0x4000c0c v_perm_b32 v49, v59, v57, 0xc0c0400 s_waitcnt lgkmcnt(8) v_perm_b32 v50, v62, v61, 0x4000c0c v_or_b32_e32 v43, v44, v43 v_or_b32_e32 v44, v46, v45 v_dot4_i32_iu8 v4, v40, v39, v4 neg_lo:[1,1,0] s_waitcnt lgkmcnt(6) v_perm_b32 v41, v64, v63, 0xc0c0400 s_waitcnt lgkmcnt(4) v_perm_b32 v42, v66, v65, 0x4000c0c s_waitcnt lgkmcnt(2) v_perm_b32 v39, v68, v67, 0xc0c0400 s_waitcnt lgkmcnt(0) v_perm_b32 v40, v70, v69, 0x4000c0c v_or_b32_e32 v45, v48, v47 v_or_b32_e32 v46, v50, v49 v_dot4_i32_iu8 v4, v44, v43, v4 neg_lo:[1,1,0] v_or_b32_e32 v41, v42, v41 v_or_b32_e32 v39, v40, v39 s_cmp_ge_i32 s10, s9 s_delay_alu instid0(VALU_DEP_3) v_dot4_i32_iu8 v4, v46, v45, v4 neg_lo:[1,1,0] s_barrier buffer_gl0_inv v_dot4_i32_iu8 v4, v39, v41, v4 neg_lo:[1,1,0] s_cbranch_scc0 .LBB0_2 s_branch .LBB0_4 .LBB0_3: v_mov_b32_e32 v4, 0 .LBB0_4: v_mul_lo_u32 v0, v0, s3 v_lshl_add_u32 v1, s14, 4, v1 s_load_b64 s[0:1], s[0:1], 0x10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add3_u32 v0, v1, v0, s8 v_ashrrev_i32_e32 v1, 31, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[0:1] s_waitcnt lgkmcnt(0) v_add_co_u32 v0, vcc_lo, s0, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo global_store_b32 v[0:1], v4, off s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z12matrixMulGPUPaS_Pii .amdhsa_group_segment_fixed_size 512 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 28 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 71 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z12matrixMulGPUPaS_Pii, .Lfunc_end0-_Z12matrixMulGPUPaS_Pii .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value .group_segment_fixed_size: 512 .kernarg_segment_align: 8 .kernarg_segment_size: 28 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z12matrixMulGPUPaS_Pii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z12matrixMulGPUPaS_Pii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 71 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <stdio.h> #include <stdlib.h> #include <sys/time.h> #include <time.h> #include <hip/hip_runtime.h> double my_timer() { struct timeval time; double _ret_val_0; gettimeofday(( & time), 0); _ret_val_0=(time.tv_sec+(time.tv_usec/1000000.0)); return _ret_val_0; } #define BLOCK_SIZE 16 void matrixMulCPU(int8_t *A, int8_t *B, int *C, int size){ int i, j, k; int sum; for(i = 0; i < size; i++){ for(j = 0; j < size; j++){ sum = 0; for(k = 0; k < size; k++){ sum += A[i * size + k] * B[j * size + k]; } C[i * size + j] = sum; } } } __global__ void matrixMulGPU(int8_t *A, int8_t *B, int *C, int width){ // Block index int bx = blockIdx.x; int by = blockIdx.y; // Thread index int tx = threadIdx.x; int ty = threadIdx.y; // Index of the first sub-matrix of A processed by the block int aBegin = width * BLOCK_SIZE * by; // Index of the last sub-matrix of A processed by the block int aEnd = aBegin + width - 1; // Step size used to iterate through the sub-matrices of A int aStep = BLOCK_SIZE; // Index of the first sub-matrix of B processed by the block int bBegin = width * BLOCK_SIZE * bx; // Step size used to iterate through the sub-matrices of B int bStep = BLOCK_SIZE; // Csub is used to store the element of the block sub-matrix // that is computed by the thread int Csub = 0; // Loop over all the sub-matrices of A and B // required to compute the block sub-matrix for (int a = aBegin, b = bBegin; a <= aEnd; a += aStep, b += bStep) { // Declaration of the shared memory array As used to // store the sub-matrix of A __shared__ int8_t As[BLOCK_SIZE][BLOCK_SIZE]; // Declaration of the shared memory array Bs used to // store the sub-matrix of B __shared__ int8_t Bs[BLOCK_SIZE][BLOCK_SIZE]; // Load the matrices from device memory // to shared memory; each thread loads // one element of each matrix As[ty][tx] = A[a + width * ty + tx]; Bs[ty][tx] = B[b + width * ty + tx]; // Synchronize to make sure the matrices are loaded __syncthreads(); // Multiply the two matrices together; // each thread computes one element // of the block sub-matrix #pragma unroll for (int k = 0; k < BLOCK_SIZE; ++k) { Csub += (int)As[ty][k] * (int)Bs[tx][k]; } // Synchronize to make sure that the preceding // computation is done before loading two new // sub-matrices of A and B in the next iteration __syncthreads(); } // Write the block sub-matrix to device memory; // each thread writes one element int c = width * BLOCK_SIZE * by + BLOCK_SIZE * bx; C[c + width * ty + tx] = Csub; } int main(int argc, char *argv[]){ int i; int8_t *A, *B; int *C, *D; int8_t *A_dev, *B_dev; int *C_dev; double start_timer, end_timer; int width, MSIZE; if(argc < 2){ printf("Error input options\n"); exit(1); } width = atoi(argv[1]); MSIZE = width * width; A = (int8_t*)malloc(sizeof(int8_t)*MSIZE); hipMalloc(&A_dev, MSIZE*sizeof(int8_t)); B = (int8_t*)malloc(sizeof(int8_t)*MSIZE); hipMalloc(&B_dev, MSIZE*sizeof(int8_t)); C = (int*)malloc(sizeof(int)*MSIZE); hipMalloc(&C_dev, MSIZE*sizeof(int)); D = (int*)malloc(sizeof(int)*MSIZE); srand(time(NULL)); // Init matrix for(i = 0; i < MSIZE; i++){ A[i] = 1;//(rand() % 16) - 8; B[i] = 1;//(rand() % 16) - 8; C[i] = 0; D[i] = 0; } hipMemcpy(A_dev, A, MSIZE*sizeof(int8_t), hipMemcpyHostToDevice); hipMemcpy(B_dev, B, MSIZE*sizeof(int8_t), hipMemcpyHostToDevice); hipMemcpy(C_dev, C, MSIZE*sizeof(int), hipMemcpyHostToDevice); hipDeviceSynchronize(); /*thread blcok conf.*/ dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE); dim3 grid(width/dimBlock.x, width/dimBlock.y); start_timer = my_timer(); matrixMulGPU<<<grid, dimBlock>>>(A_dev, B_dev, C_dev, width); hipDeviceSynchronize(); end_timer = my_timer(); printf("The GPU Elapsed Time:%lf Sec.\n", end_timer - start_timer); hipMemcpy(C, C_dev, MSIZE*sizeof(int), hipMemcpyDeviceToHost); hipDeviceSynchronize(); start_timer = my_timer(); matrixMulCPU(A, B, D, width); end_timer = my_timer(); printf("The CPU Elapsed Time:%lf Sec.\n", end_timer - start_timer); //Verification printf("Verifying\n"); int flag = 0; for(i = 0; i < MSIZE; i++){ if(abs(C[i] - D[i]) > 1e-3){ printf("Error:%d, %d, %d\n", C[i], D[i], i); break; } flag ++; } if(flag == MSIZE) printf("Verify Success!!\n"); // memory free free(A); hipFree(A_dev); free(B); hipFree(B_dev); free(C); hipFree(C_dev); free(D); return 0; }
.text .file "matrixMul8.hip" .section .rodata.cst8,"aM",@progbits,8 .p2align 3, 0x0 # -- Begin function _Z8my_timerv .LCPI0_0: .quad 0x412e848000000000 # double 1.0E+6 .text .globl _Z8my_timerv .p2align 4, 0x90 .type _Z8my_timerv,@function _Z8my_timerv: # @_Z8my_timerv .cfi_startproc # %bb.0: subq $24, %rsp .cfi_def_cfa_offset 32 leaq 8(%rsp), %rdi xorl %esi, %esi callq gettimeofday cvtsi2sdq 8(%rsp), %xmm1 cvtsi2sdq 16(%rsp), %xmm0 divsd .LCPI0_0(%rip), %xmm0 addsd %xmm1, %xmm0 addq $24, %rsp .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z8my_timerv, .Lfunc_end0-_Z8my_timerv .cfi_endproc # -- End function .globl _Z12matrixMulCPUPaS_Pii # -- Begin function _Z12matrixMulCPUPaS_Pii .p2align 4, 0x90 .type _Z12matrixMulCPUPaS_Pii,@function _Z12matrixMulCPUPaS_Pii: # @_Z12matrixMulCPUPaS_Pii .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %rdx, -8(%rsp) # 8-byte Spill testl %ecx, %ecx jle .LBB1_7 # %bb.1: # %.preheader26.lr.ph movl %ecx, %eax xorl %edx, %edx xorl %r9d, %r9d .p2align 4, 0x90 .LBB1_2: # %.preheader26 # =>This Loop Header: Depth=1 # Child Loop BB1_3 Depth 2 # Child Loop BB1_4 Depth 3 movl %edx, %r10d addq %rdi, %r10 movl %r9d, %r11d imull %ecx, %r11d movq -8(%rsp), %r8 # 8-byte Reload leaq (%r8,%r11,4), %r11 xorl %ebx, %ebx xorl %r14d, %r14d .p2align 4, 0x90 .LBB1_3: # %.preheader # Parent Loop BB1_2 Depth=1 # => This Loop Header: Depth=2 # Child Loop BB1_4 Depth 3 movl %ebx, %r15d addq %rsi, %r15 xorl %r12d, %r12d xorl %ebp, %ebp .p2align 4, 0x90 .LBB1_4: # Parent Loop BB1_2 Depth=1 # Parent Loop BB1_3 Depth=2 # => This Inner Loop Header: Depth=3 movsbl (%r10,%r12), %r13d movsbl (%r15,%r12), %r8d imull %r13d, %r8d addl %r8d, %ebp incq %r12 cmpq %r12, %rax jne .LBB1_4 # %bb.5: # %._crit_edge # in Loop: Header=BB1_3 Depth=2 movl %ebp, (%r11,%r14,4) incq %r14 addl %ecx, %ebx cmpq %rax, %r14 jne .LBB1_3 # %bb.6: # %._crit_edge30 # in Loop: Header=BB1_2 Depth=1 incq %r9 addl %ecx, %edx cmpq %rax, %r9 jne .LBB1_2 .LBB1_7: # %._crit_edge32 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size _Z12matrixMulCPUPaS_Pii, .Lfunc_end1-_Z12matrixMulCPUPaS_Pii .cfi_endproc # -- End function .globl _Z27__device_stub__matrixMulGPUPaS_Pii # -- Begin function _Z27__device_stub__matrixMulGPUPaS_Pii .p2align 4, 0x90 .type _Z27__device_stub__matrixMulGPUPaS_Pii,@function _Z27__device_stub__matrixMulGPUPaS_Pii: # @_Z27__device_stub__matrixMulGPUPaS_Pii .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movl %ecx, 4(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z12matrixMulGPUPaS_Pii, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end2: .size _Z27__device_stub__matrixMulGPUPaS_Pii, .Lfunc_end2-_Z27__device_stub__matrixMulGPUPaS_Pii .cfi_endproc # -- End function .section .rodata.cst8,"aM",@progbits,8 .p2align 3, 0x0 # -- Begin function main .LCPI3_0: .quad 0x412e848000000000 # double 1.0E+6 .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $184, %rsp .cfi_def_cfa_offset 240 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 cmpl $1, %edi jle .LBB3_20 # %bb.1: movq 8(%rsi), %rdi xorl %esi, %esi movl $10, %edx callq __isoc23_strtol movq %rax, %rbp movl %ebp, %r12d imull %r12d, %r12d movq %r12, %rdi callq malloc movq %rax, %rbx leaq 72(%rsp), %rdi movq %r12, %rsi callq hipMalloc movq %r12, %rdi callq malloc movq %rax, %r14 leaq 64(%rsp), %rdi movq %r12, %rsi callq hipMalloc leaq (,%r12,4), %r15 movq %r15, %rdi callq malloc movq %rax, 56(%rsp) # 8-byte Spill leaq 8(%rsp), %rdi movq %r15, %rsi callq hipMalloc movq %r15, 48(%rsp) # 8-byte Spill movq %r15, %rdi callq malloc movq %rax, %r13 xorl %edi, %edi callq time movl %eax, %edi callq srand testl %ebp, %ebp je .LBB3_3 # %bb.2: # %.lr.ph.preheader cmpl $2, %r12d movl $1, %r15d cmovael %r12d, %r15d movq %rbx, %rdi movl $1, %esi movq %r15, %rdx callq memset@PLT movq %r14, %rdi movl $1, %esi movq %r15, %rdx callq memset@PLT shlq $2, %r15 movq 56(%rsp), %rdi # 8-byte Reload xorl %esi, %esi movq %r15, %rdx callq memset@PLT movq %r13, %rdi xorl %esi, %esi movq %r15, %rdx callq memset@PLT .LBB3_3: # %._crit_edge movq %r13, 88(%rsp) # 8-byte Spill movq 72(%rsp), %rdi movq %rbx, %rsi movq %r12, %rdx movl $1, %ecx callq hipMemcpy movq 64(%rsp), %rdi movq %r14, %rsi movq %r12, 104(%rsp) # 8-byte Spill movq %r12, %rdx movl $1, %ecx callq hipMemcpy movq 8(%rsp), %rdi movq 56(%rsp), %r13 # 8-byte Reload movq %r13, %rsi movq 48(%rsp), %r12 # 8-byte Reload movq %r12, %rdx movl $1, %ecx callq hipMemcpy callq hipDeviceSynchronize movl %ebp, %eax shrl $4, %eax movq %rax, %r15 shlq $32, %r15 orq %rax, %r15 leaq 16(%rsp), %rdi xorl %esi, %esi callq gettimeofday cvtsi2sdq 16(%rsp), %xmm0 cvtsi2sdq 24(%rsp), %xmm1 divsd .LCPI3_0(%rip), %xmm1 addsd %xmm0, %xmm1 movsd %xmm1, 96(%rsp) # 8-byte Spill movabsq $68719476752, %rdx # imm = 0x1000000010 movq %r15, %rdi movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB3_5 # %bb.4: movq 72(%rsp), %rax movq 64(%rsp), %rcx movq 8(%rsp), %rdx movq %rax, 176(%rsp) movq %rcx, 168(%rsp) movq %rdx, 160(%rsp) movl %ebp, 84(%rsp) leaq 176(%rsp), %rax movq %rax, 16(%rsp) leaq 168(%rsp), %rax movq %rax, 24(%rsp) leaq 160(%rsp), %rax movq %rax, 32(%rsp) leaq 84(%rsp), %rax movq %rax, 40(%rsp) leaq 144(%rsp), %rdi leaq 128(%rsp), %rsi leaq 120(%rsp), %rdx leaq 112(%rsp), %rcx callq __hipPopCallConfiguration movq 144(%rsp), %rsi movl 152(%rsp), %edx movq 128(%rsp), %rcx movl 136(%rsp), %r8d leaq 16(%rsp), %r9 movl $_Z12matrixMulGPUPaS_Pii, %edi pushq 112(%rsp) .cfi_adjust_cfa_offset 8 pushq 128(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB3_5: callq hipDeviceSynchronize leaq 16(%rsp), %rdi xorl %esi, %esi callq gettimeofday xorps %xmm1, %xmm1 cvtsi2sdq 16(%rsp), %xmm1 xorps %xmm0, %xmm0 cvtsi2sdq 24(%rsp), %xmm0 divsd .LCPI3_0(%rip), %xmm0 addsd %xmm1, %xmm0 subsd 96(%rsp), %xmm0 # 8-byte Folded Reload movl $.L.str.1, %edi movb $1, %al callq printf movq 8(%rsp), %rsi movq %r13, %rdi movq %r12, %rdx movl $2, %ecx callq hipMemcpy callq hipDeviceSynchronize leaq 16(%rsp), %rdi xorl %esi, %esi callq gettimeofday xorps %xmm0, %xmm0 cvtsi2sdq 16(%rsp), %xmm0 xorps %xmm1, %xmm1 cvtsi2sdq 24(%rsp), %xmm1 divsd .LCPI3_0(%rip), %xmm1 addsd %xmm0, %xmm1 movsd %xmm1, 48(%rsp) # 8-byte Spill testl %ebp, %ebp jle .LBB3_12 # %bb.6: # %.preheader26.lr.ph.i movl %ebp, %eax xorl %ecx, %ecx xorl %edx, %edx .p2align 4, 0x90 .LBB3_7: # %.preheader26.i # =>This Loop Header: Depth=1 # Child Loop BB3_8 Depth 2 # Child Loop BB3_9 Depth 3 movl %ecx, %esi movq %rbx, %r13 addq %rbx, %rsi movl %edx, %edi imull %ebp, %edi movq 88(%rsp), %r8 # 8-byte Reload leaq (%r8,%rdi,4), %rdi xorl %r8d, %r8d xorl %r9d, %r9d .p2align 4, 0x90 .LBB3_8: # %.preheader.i # Parent Loop BB3_7 Depth=1 # => This Loop Header: Depth=2 # Child Loop BB3_9 Depth 3 movl %r8d, %r10d addq %r14, %r10 xorl %r11d, %r11d xorl %r12d, %r12d .p2align 4, 0x90 .LBB3_9: # Parent Loop BB3_7 Depth=1 # Parent Loop BB3_8 Depth=2 # => This Inner Loop Header: Depth=3 movsbl (%rsi,%r11), %ebx movsbl (%r10,%r11), %r15d imull %ebx, %r15d addl %r15d, %r12d incq %r11 cmpq %r11, %rax jne .LBB3_9 # %bb.10: # %._crit_edge.i # in Loop: Header=BB3_8 Depth=2 movl %r12d, (%rdi,%r9,4) incq %r9 addl %ebp, %r8d cmpq %rax, %r9 jne .LBB3_8 # %bb.11: # %._crit_edge30.i # in Loop: Header=BB3_7 Depth=1 incq %rdx addl %ebp, %ecx cmpq %rax, %rdx movq %r13, %rbx jne .LBB3_7 .LBB3_12: # %_Z12matrixMulCPUPaS_Pii.exit leaq 16(%rsp), %rdi xorl %esi, %esi callq gettimeofday xorps %xmm1, %xmm1 cvtsi2sdq 16(%rsp), %xmm1 xorps %xmm0, %xmm0 cvtsi2sdq 24(%rsp), %xmm0 divsd .LCPI3_0(%rip), %xmm0 addsd %xmm1, %xmm0 subsd 48(%rsp), %xmm0 # 8-byte Folded Reload movl $.L.str.2, %edi movb $1, %al callq printf movl $.Lstr, %edi callq puts@PLT testl %ebp, %ebp movq 104(%rsp), %r15 # 8-byte Reload movq 56(%rsp), %r12 # 8-byte Reload movq 88(%rsp), %r13 # 8-byte Reload movl $0, %eax je .LBB3_17 # %bb.13: # %.lr.ph84.preheader cmpl $2, %r15d movl $1, %eax cmovael %r15d, %eax xorl %ebp, %ebp .p2align 4, 0x90 .LBB3_14: # %.lr.ph84 # =>This Inner Loop Header: Depth=1 movl (%r12,%rbp,4), %esi movl (%r13,%rbp,4), %edx cmpl %edx, %esi jne .LBB3_15 # %bb.16: # in Loop: Header=BB3_14 Depth=1 incq %rbp cmpq %rbp, %rax jne .LBB3_14 .LBB3_17: # %.loopexit cmpl %r15d, %eax jne .LBB3_19 .LBB3_18: movl $.Lstr.1, %edi callq puts@PLT .LBB3_19: movq %rbx, %rdi callq free movq 72(%rsp), %rdi callq hipFree movq %r14, %rdi callq free movq 64(%rsp), %rdi callq hipFree movq %r12, %rdi callq free movq 8(%rsp), %rdi callq hipFree movq %r13, %rdi callq free xorl %eax, %eax addq $184, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB3_15: .cfi_def_cfa_offset 240 movl $.L.str.4, %edi movl %ebp, %ecx xorl %eax, %eax callq printf movl %ebp, %eax cmpl %r15d, %eax je .LBB3_18 jmp .LBB3_19 .LBB3_20: movl $.Lstr.2, %edi callq puts@PLT movl $1, %edi callq exit .Lfunc_end3: .size main, .Lfunc_end3-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB4_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB4_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z12matrixMulGPUPaS_Pii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end4: .size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB5_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB5_2: retq .Lfunc_end5: .size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor .cfi_endproc # -- End function .type _Z12matrixMulGPUPaS_Pii,@object # @_Z12matrixMulGPUPaS_Pii .section .rodata,"a",@progbits .globl _Z12matrixMulGPUPaS_Pii .p2align 3, 0x0 _Z12matrixMulGPUPaS_Pii: .quad _Z27__device_stub__matrixMulGPUPaS_Pii .size _Z12matrixMulGPUPaS_Pii, 8 .type .L.str.1,@object # @.str.1 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.1: .asciz "The GPU Elapsed Time:%lf Sec.\n" .size .L.str.1, 31 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "The CPU Elapsed Time:%lf Sec.\n" .size .L.str.2, 31 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "Error:%d, %d, %d\n" .size .L.str.4, 18 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z12matrixMulGPUPaS_Pii" .size .L__unnamed_1, 24 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .type .Lstr,@object # @str .section .rodata.str1.1,"aMS",@progbits,1 .Lstr: .asciz "Verifying" .size .Lstr, 10 .type .Lstr.1,@object # @str.1 .Lstr.1: .asciz "Verify Success!!" .size .Lstr.1, 17 .type .Lstr.2,@object # @str.2 .Lstr.2: .asciz "Error input options" .size .Lstr.2, 20 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z27__device_stub__matrixMulGPUPaS_Pii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z12matrixMulGPUPaS_Pii .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z12matrixMulGPUPaS_Pii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */ /* 0x000e220000002500 */ /*0020*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */ /* 0x000fe20003f01270 */ /*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fe40000000a00 */ /*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */ /* 0x000e280000002100 */ /*0050*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */ /* 0x000e680000002600 */ /*0060*/ S2R R4, SR_TID.Y ; /* 0x0000000000047919 */ /* 0x000ea40000002200 */ /*0070*/ @!P0 IMAD.MOV.U32 R15, RZ, RZ, RZ ; /* 0x000000ffff0f8224 */ /* 0x000fc400078e00ff */ /*0080*/ IMAD R3, R5, 0x10, R0 ; /* 0x0000001005037824 */ /* 0x001fe400078e0200 */ /*0090*/ IMAD R2, R7, c[0x0][0x178], RZ ; /* 0x00005e0007027a24 */ /* 0x002fe400078e02ff */ /*00a0*/ IMAD R3, R4, c[0x0][0x178], R3 ; /* 0x00005e0004037a24 */ /* 0x004fe400078e0203 */ /*00b0*/ IMAD.SHL.U32 R12, R2, 0x10, RZ ; /* 0x00000010020c7824 */ /* 0x000fe400078e00ff */ /*00c0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */ /* 0x000fe400078e00ff */ /*00d0*/ IMAD.IADD R3, R12, 0x1, R3 ; /* 0x000000010c037824 */ /* 0x000fc800078e0203 */ /*00e0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */ /* 0x000fe200078e0202 */ /*00f0*/ @!P0 BRA 0x690 ; /* 0x0000059000008947 */ /* 0x000fea0003800000 */ /*0100*/ IMAD R5, R5, 0x10, R4.reuse ; /* 0x0000001005057824 */ /* 0x100fe400078e0204 */ /*0110*/ IMAD R7, R7, 0x10, R4 ; /* 0x0000001007077824 */ /* 0x000fe400078e0204 */ /*0120*/ IMAD R5, R5, c[0x0][0x178], R0.reuse ; /* 0x00005e0005057a24 */ /* 0x100fe400078e0200 */ /*0130*/ IMAD R6, R7, c[0x0][0x178], R0.reuse ; /* 0x00005e0007067a24 */ /* 0x100fe200078e0200 */ /*0140*/ IADD3 R7, R12, c[0x0][0x178], RZ ; /* 0x00005e000c077a10 */ /* 0x000fe20007ffe0ff */ /*0150*/ IMAD.SHL.U32 R9, R4, 0x10, RZ ; /* 0x0000001004097824 */ /* 0x000fe200078e00ff */ /*0160*/ IADD3 R8, P0, R5, c[0x0][0x168], RZ ; /* 0x00005a0005087a10 */ /* 0x000fe20007f1e0ff */ /*0170*/ IMAD.MOV.U32 R15, RZ, RZ, RZ ; /* 0x000000ffff0f7224 */ /* 0x000fe200078e00ff */ /*0180*/ IADD3 R10, P1, R6, c[0x0][0x160], RZ ; /* 0x00005800060a7a10 */ /* 0x000fe20007f3e0ff */ /*0190*/ IMAD.IADD R9, R9, 0x1, R0 ; /* 0x0000000109097824 */ /* 0x000fe200078e0200 */ /*01a0*/ LEA.HI.X.SX32 R11, R5, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b00050b7a11 */ /* 0x000fc400000f0eff */ /*01b0*/ LEA.HI.X.SX32 R5, R6, c[0x0][0x164], 0x1, P1 ; /* 0x0000590006057a11 */ /* 0x000fc600008f0eff */ /*01c0*/ IMAD.MOV.U32 R16, RZ, RZ, R10 ; /* 0x000000ffff107224 */ /* 0x000fe400078e000a */ /*01d0*/ IMAD.MOV.U32 R17, RZ, RZ, R5 ; /* 0x000000ffff117224 */ /* 0x000fe400078e0005 */ /*01e0*/ IMAD.MOV.U32 R18, RZ, RZ, R8 ; /* 0x000000ffff127224 */ /* 0x000fe400078e0008 */ /*01f0*/ IMAD.MOV.U32 R19, RZ, RZ, R11 ; /* 0x000000ffff137224 */ /* 0x000fe200078e000b */ /*0200*/ LDG.E.U8 R6, [R16.64] ; /* 0x0000000410067981 */ /* 0x000ea8000c1e1100 */ /*0210*/ LDG.E.U8 R14, [R18.64] ; /* 0x00000004120e7981 */ /* 0x000ee2000c1e1100 */ /*0220*/ IADD3 R12, R12, 0x10, RZ ; /* 0x000000100c0c7810 */ /* 0x000fc40007ffe0ff */ /*0230*/ IADD3 R10, P2, R10, 0x10, RZ ; /* 0x000000100a0a7810 */ /* 0x000fe40007f5e0ff */ /*0240*/ ISETP.GE.AND P0, PT, R12, R7, PT ; /* 0x000000070c00720c */ /* 0x000fe40003f06270 */ /*0250*/ IADD3 R8, P1, R8, 0x10, RZ ; /* 0x0000001008087810 */ /* 0x000fe20007f3e0ff */ /*0260*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */ /* 0x000fc800010e0605 */ /*0270*/ IMAD.X R11, RZ, RZ, R11, P1 ; /* 0x000000ffff0b7224 */ /* 0x000fe200008e060b */ /*0280*/ STS.U8 [R9], R6 ; /* 0x0000000609007388 */ /* 0x004fe80000000000 */ /*0290*/ STS.U8 [R9+0x100], R14 ; /* 0x0001000e09007388 */ /* 0x008fe80000000000 */ /*02a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*02b0*/ LDS.U8 R13, [R0.X16+0x100] ; /* 0x00010000000d7984 */ /* 0x000fe8000000c000 */ /*02c0*/ LDS.U8 R20, [R0.X16+0x101] ; /* 0x0001010000147984 */ /* 0x000e28000000c000 */ /*02d0*/ LDS.U8 R21, [R0.X16+0x102] ; /* 0x0001020000157984 */ /* 0x000fe8000000c000 */ /*02e0*/ LDS.U8 R26, [R0.X16+0x103] ; /* 0x00010300001a7984 */ /* 0x000e68000000c000 */ /*02f0*/ LDS.U8 R22, [R4.X16] ; /* 0x0000000004167984 */ /* 0x000fe8000000c000 */ /*0300*/ LDS.U8 R23, [R4.X16+0x1] ; /* 0x0000010004177984 */ /* 0x000ea8000000c000 */ /*0310*/ LDS.U8 R24, [R4.X16+0x2] ; /* 0x0000020004187984 */ /* 0x000fe8000000c000 */ /*0320*/ LDS.U8 R25, [R4.X16+0x3] ; /* 0x0000030004197984 */ /* 0x000ee8000000c000 */ /*0330*/ LDS.U8 R6, [R0.X16+0x104] ; /* 0x0001040000067984 */ /* 0x000fe8000000c000 */ /*0340*/ LDS.U8 R17, [R0.X16+0x106] ; /* 0x0001060000117984 */ /* 0x000fe8000000c000 */ /*0350*/ LDS.U8 R18, [R4.X16+0x4] ; /* 0x0000040004127984 */ /* 0x000fe2000000c000 */ /*0360*/ PRMT R16, R20, 0x7604, R13 ; /* 0x0000760414107816 */ /* 0x001fc6000000000d */ /*0370*/ LDS.U8 R14, [R4.X16+0x6] ; /* 0x00000600040e7984 */ /* 0x000fe8000000c000 */ /*0380*/ LDS.U8 R13, [R0.X16+0x105] ; /* 0x00010500000d7984 */ /* 0x000e22000000c000 */ /*0390*/ PRMT R27, R26, 0x7604, R21 ; /* 0x000076041a1b7816 */ /* 0x002fc60000000015 */ /*03a0*/ LDS.U8 R20, [R0.X16+0x107] ; /* 0x0001070000147984 */ /* 0x000e62000000c000 */ /*03b0*/ PRMT R16, R27, 0x1054, R16 ; /* 0x000010541b107816 */ /* 0x000fc60000000010 */ /*03c0*/ LDS.U8 R21, [R4.X16+0x5] ; /* 0x0000050004157984 */ /* 0x000f22000000c000 */ /*03d0*/ PRMT R26, R23, 0x7604, R22 ; /* 0x00007604171a7816 */ /* 0x004fc60000000016 */ /*03e0*/ LDS.U8 R19, [R4.X16+0x7] ; /* 0x0000070004137984 */ /* 0x000ea8000000c000 */ /*03f0*/ LDS.U8 R22, [R0.X16+0x108] ; /* 0x0001080000167984 */ /* 0x000fe2000000c000 */ /*0400*/ PRMT R25, R25, 0x7604, R24 ; /* 0x0000760419197816 */ /* 0x008fc60000000018 */ /*0410*/ LDS.U8 R23, [R0.X16+0x109] ; /* 0x0001090000177984 */ /* 0x000ee2000000c000 */ /*0420*/ PRMT R26, R25, 0x1054, R26 ; /* 0x00001054191a7816 */ /* 0x000fc6000000001a */ /*0430*/ LDS.U8 R24, [R0.X16+0x10b] ; /* 0x00010b0000187984 */ /* 0x000fe8000000c000 */ /*0440*/ LDS.U8 R25, [R0.X16+0x10a] ; /* 0x00010a0000197984 */ /* 0x000f68000000c000 */ /*0450*/ LDS.U8 R28, [R4.X16+0xb] ; /* 0x00000b00041c7984 */ /* 0x000fe2000000c000 */ /*0460*/ PRMT R6, R13, 0x7604, R6 ; /* 0x000076040d067816 */ /* 0x001fc60000000006 */ /*0470*/ LDS.U8 R13, [R0.X16+0x10e] ; /* 0x00010e00000d7984 */ /* 0x000fe2000000c000 */ /*0480*/ PRMT R17, R20, 0x7604, R17 ; /* 0x0000760414117816 */ /* 0x002fc60000000011 */ /*0490*/ LDS.U8 R20, [R0.X16+0x10c] ; /* 0x00010c0000147984 */ /* 0x000fe2000000c000 */ /*04a0*/ PRMT R18, R21, 0x7604, R18 ; /* 0x0000760415127816 */ /* 0x010fe40000000012 */ /*04b0*/ PRMT R17, R17, 0x1054, R6 ; /* 0x0000105411117816 */ /* 0x000fe20000000006 */ /*04c0*/ IDP.4A.S8.S8 R6, R16, R26, R15 ; /* 0x0000001a10067226 */ /* 0x000fe2000000060f */ /*04d0*/ PRMT R19, R19, 0x7604, R14 ; /* 0x0000760413137816 */ /* 0x004fe2000000000e */ /*04e0*/ LDS.U8 R21, [R4.X16+0x8] ; /* 0x0000080004157984 */ /* 0x000fe6000000c000 */ /*04f0*/ PRMT R18, R19, 0x1054, R18 ; /* 0x0000105413127816 */ /* 0x000fe20000000012 */ /*0500*/ LDS.U8 R26, [R4.X16+0x9] ; /* 0x00000900041a7984 */ /* 0x000e22000000c000 */ /*0510*/ PRMT R22, R23, 0x7604, R22 ; /* 0x0000760417167816 */ /* 0x008fc60000000016 */ /*0520*/ IDP.4A.S8.S8 R6, R17, R18, R6 ; /* 0x0000001211067226 */ /* 0x000fe20000000606 */ /*0530*/ LDS.U8 R23, [R4.X16+0xa] ; /* 0x00000a0004177984 */ /* 0x000e68000000c000 */ /*0540*/ LDS.U8 R19, [R0.X16+0x10d] ; /* 0x00010d0000137984 */ /* 0x000ea2000000c000 */ /*0550*/ PRMT R25, R24, 0x7604, R25 ; /* 0x0000760418197816 */ /* 0x020fc60000000019 */ /*0560*/ LDS.U8 R18, [R0.X16+0x10f] ; /* 0x00010f0000127984 */ /* 0x000ee2000000c000 */ /*0570*/ PRMT R25, R25, 0x1054, R22 ; /* 0x0000105419197816 */ /* 0x000fc60000000016 */ /*0580*/ LDS.U8 R15, [R4.X16+0xc] ; /* 0x00000c00040f7984 */ /* 0x000fe8000000c000 */ /*0590*/ LDS.U8 R16, [R4.X16+0xd] ; /* 0x00000d0004107984 */ /* 0x000f28000000c000 */ /*05a0*/ LDS.U8 R14, [R4.X16+0xe] ; /* 0x00000e00040e7984 */ /* 0x000fe8000000c000 */ /*05b0*/ LDS.U8 R17, [R4.X16+0xf] ; /* 0x00000f0004117984 */ /* 0x000f62000000c000 */ /*05c0*/ PRMT R21, R26, 0x7604, R21 ; /* 0x000076041a157816 */ /* 0x001fc40000000015 */ /*05d0*/ PRMT R28, R28, 0x7604, R23 ; /* 0x000076041c1c7816 */ /* 0x002fc80000000017 */ /*05e0*/ PRMT R21, R28, 0x1054, R21 ; /* 0x000010541c157816 */ /* 0x000fe40000000015 */ /*05f0*/ PRMT R19, R19, 0x7604, R20 ; /* 0x0000760413137816 */ /* 0x004fe40000000014 */ /*0600*/ PRMT R18, R18, 0x7604, R13 ; /* 0x0000760412127816 */ /* 0x008fe2000000000d */ /*0610*/ IDP.4A.S8.S8 R6, R25, R21, R6 ; /* 0x0000001519067226 */ /* 0x000fc60000000606 */ /*0620*/ PRMT R19, R18, 0x1054, R19 ; /* 0x0000105412137816 */ /* 0x000fe40000000013 */ /*0630*/ PRMT R15, R16, 0x7604, R15 ; /* 0x00007604100f7816 */ /* 0x010fe4000000000f */ /*0640*/ PRMT R14, R17, 0x7604, R14 ; /* 0x00007604110e7816 */ /* 0x020fc8000000000e */ /*0650*/ PRMT R15, R14, 0x1054, R15 ; /* 0x000010540e0f7816 */ /* 0x000fca000000000f */ /*0660*/ IDP.4A.S8.S8 R15, R19, R15, R6 ; /* 0x0000000f130f7226 */ /* 0x000fe20000000606 */ /*0670*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*0680*/ @!P0 BRA 0x1c0 ; /* 0xfffffb3000008947 */ /* 0x000fea000383ffff */ /*0690*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */ /* 0x000fe2000c101904 */ /*06a0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*06b0*/ BRA 0x6b0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*06c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*06d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*06e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*06f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0700*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0710*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0720*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0730*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0740*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0750*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0760*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0770*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z12matrixMulGPUPaS_Pii .globl _Z12matrixMulGPUPaS_Pii .p2align 8 .type _Z12matrixMulGPUPaS_Pii,@function _Z12matrixMulGPUPaS_Pii: s_load_b32 s3, s[0:1], 0x18 v_and_b32_e32 v1, 0x3ff, v0 v_bfe_u32 v0, v0, 10, 10 s_waitcnt lgkmcnt(0) s_mul_i32 s2, s3, s15 s_delay_alu instid0(SALU_CYCLE_1) s_lshl_b32 s8, s2, 4 s_cmp_lt_i32 s3, 1 s_cbranch_scc1 .LBB0_3 v_lshl_add_u32 v4, s14, 4, v0 s_load_b128 s[4:7], s[0:1], 0x0 v_lshl_add_u32 v37, s15, 4, v0 v_lshlrev_b32_e32 v5, 4, v0 v_lshlrev_b32_e32 v38, 4, v1 v_mad_u64_u32 v[2:3], null, s3, v4, v[1:2] s_add_i32 s9, s8, s3 s_mov_b32 s10, s8 s_delay_alu instid0(VALU_DEP_2) v_add_nc_u32_e32 v7, 0x100, v38 v_add_nc_u32_e32 v9, 0x101, v38 v_add_nc_u32_e32 v11, 0x102, v38 v_add_nc_u32_e32 v14, 0x103, v38 v_mad_u64_u32 v[3:4], null, s3, v37, v[1:2] v_mov_b32_e32 v4, 0 v_add_nc_u32_e32 v6, v5, v1 v_or_b32_e32 v8, 1, v5 v_or_b32_e32 v10, 2, v5 v_or_b32_e32 v12, 3, v5 v_or_b32_e32 v15, 4, v5 v_add_nc_u32_e32 v13, 0x100, v6 v_add_nc_u32_e32 v16, 0x104, v38 v_or_b32_e32 v17, 5, v5 v_add_nc_u32_e32 v18, 0x105, v38 v_or_b32_e32 v19, 6, v5 v_add_nc_u32_e32 v20, 0x106, v38 v_or_b32_e32 v21, 7, v5 v_add_nc_u32_e32 v22, 0x107, v38 v_or_b32_e32 v23, 8, v5 v_add_nc_u32_e32 v24, 0x108, v38 v_or_b32_e32 v25, 9, v5 v_add_nc_u32_e32 v26, 0x109, v38 v_or_b32_e32 v27, 10, v5 v_add_nc_u32_e32 v28, 0x10a, v38 v_or_b32_e32 v29, 11, v5 v_add_nc_u32_e32 v30, 0x10b, v38 v_or_b32_e32 v31, 12, v5 v_add_nc_u32_e32 v32, 0x10c, v38 v_or_b32_e32 v33, 13, v5 v_add_nc_u32_e32 v34, 0x10d, v38 v_or_b32_e32 v35, 14, v5 v_add_nc_u32_e32 v36, 0x10e, v38 v_or_b32_e32 v37, 15, v5 v_add_nc_u32_e32 v38, 0x10f, v38 .LBB0_2: v_ashrrev_i32_e32 v40, 31, v3 v_ashrrev_i32_e32 v43, 31, v2 s_waitcnt lgkmcnt(0) v_add_co_u32 v41, s2, s4, v3 v_add_co_u32 v39, vcc_lo, s6, v2 v_add_co_ci_u32_e64 v42, s2, s5, v40, s2 v_add_co_ci_u32_e32 v40, vcc_lo, s7, v43, vcc_lo global_load_u8 v41, v[41:42], off global_load_u8 v39, v[39:40], off v_add_nc_u32_e32 v2, 16, v2 v_add_nc_u32_e32 v3, 16, v3 s_add_i32 s10, s10, 16 s_waitcnt vmcnt(1) ds_store_b8 v6, v41 s_waitcnt vmcnt(0) ds_store_b8 v13, v39 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv ds_load_i8 v39, v5 ds_load_i8 v40, v7 ds_load_i8 v41, v8 ds_load_i8 v42, v9 ds_load_i8 v43, v10 ds_load_i8 v44, v11 ds_load_i8 v45, v12 ds_load_i8 v46, v14 ds_load_i8 v47, v15 ds_load_i8 v48, v16 ds_load_i8 v49, v17 ds_load_i8 v50, v18 ds_load_i8 v51, v19 ds_load_i8 v52, v20 ds_load_i8 v53, v21 ds_load_i8 v54, v22 ds_load_i8 v55, v29 ds_load_i8 v56, v23 ds_load_i8 v57, v24 ds_load_i8 v58, v25 ds_load_i8 v59, v26 ds_load_i8 v60, v27 ds_load_i8 v61, v28 ds_load_i8 v62, v30 ds_load_i8 v63, v31 ds_load_i8 v64, v33 ds_load_i8 v65, v35 ds_load_i8 v66, v37 ds_load_i8 v67, v32 ds_load_i8 v68, v34 ds_load_i8 v69, v36 ds_load_i8 v70, v38 s_waitcnt lgkmcnt(29) v_perm_b32 v39, v41, v39, 0xc0c0400 s_waitcnt lgkmcnt(25) v_perm_b32 v41, v45, v43, 0x4000c0c v_perm_b32 v40, v42, v40, 0xc0c0400 s_waitcnt lgkmcnt(24) v_perm_b32 v42, v46, v44, 0x4000c0c s_waitcnt lgkmcnt(21) v_perm_b32 v43, v49, v47, 0xc0c0400 s_waitcnt lgkmcnt(17) v_perm_b32 v44, v53, v51, 0x4000c0c v_perm_b32 v45, v50, v48, 0xc0c0400 s_waitcnt lgkmcnt(16) v_perm_b32 v46, v54, v52, 0x4000c0c v_or_b32_e32 v39, v41, v39 v_or_b32_e32 v40, v42, v40 s_waitcnt lgkmcnt(12) v_perm_b32 v47, v58, v56, 0xc0c0400 s_waitcnt lgkmcnt(10) v_perm_b32 v48, v55, v60, 0x4000c0c v_perm_b32 v49, v59, v57, 0xc0c0400 s_waitcnt lgkmcnt(8) v_perm_b32 v50, v62, v61, 0x4000c0c v_or_b32_e32 v43, v44, v43 v_or_b32_e32 v44, v46, v45 v_dot4_i32_iu8 v4, v40, v39, v4 neg_lo:[1,1,0] s_waitcnt lgkmcnt(6) v_perm_b32 v41, v64, v63, 0xc0c0400 s_waitcnt lgkmcnt(4) v_perm_b32 v42, v66, v65, 0x4000c0c s_waitcnt lgkmcnt(2) v_perm_b32 v39, v68, v67, 0xc0c0400 s_waitcnt lgkmcnt(0) v_perm_b32 v40, v70, v69, 0x4000c0c v_or_b32_e32 v45, v48, v47 v_or_b32_e32 v46, v50, v49 v_dot4_i32_iu8 v4, v44, v43, v4 neg_lo:[1,1,0] v_or_b32_e32 v41, v42, v41 v_or_b32_e32 v39, v40, v39 s_cmp_ge_i32 s10, s9 s_delay_alu instid0(VALU_DEP_3) v_dot4_i32_iu8 v4, v46, v45, v4 neg_lo:[1,1,0] s_barrier buffer_gl0_inv v_dot4_i32_iu8 v4, v39, v41, v4 neg_lo:[1,1,0] s_cbranch_scc0 .LBB0_2 s_branch .LBB0_4 .LBB0_3: v_mov_b32_e32 v4, 0 .LBB0_4: v_mul_lo_u32 v0, v0, s3 v_lshl_add_u32 v1, s14, 4, v1 s_load_b64 s[0:1], s[0:1], 0x10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add3_u32 v0, v1, v0, s8 v_ashrrev_i32_e32 v1, 31, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[0:1] s_waitcnt lgkmcnt(0) v_add_co_u32 v0, vcc_lo, s0, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo global_store_b32 v[0:1], v4, off s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z12matrixMulGPUPaS_Pii .amdhsa_group_segment_fixed_size 512 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 28 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 71 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z12matrixMulGPUPaS_Pii, .Lfunc_end0-_Z12matrixMulGPUPaS_Pii .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value .group_segment_fixed_size: 512 .kernarg_segment_align: 8 .kernarg_segment_size: 28 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z12matrixMulGPUPaS_Pii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z12matrixMulGPUPaS_Pii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 71 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_000587e4_00000000-6_matrixMul8.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2062: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2062: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z8my_timerv .type _Z8my_timerv, @function _Z8my_timerv: .LFB2057: .cfi_startproc endbr64 subq $40, %rsp .cfi_def_cfa_offset 48 movq %fs:40, %rax movq %rax, 24(%rsp) xorl %eax, %eax movq %rsp, %rdi movl $0, %esi call gettimeofday@PLT pxor %xmm0, %xmm0 cvtsi2sdq 8(%rsp), %xmm0 divsd .LC0(%rip), %xmm0 pxor %xmm1, %xmm1 cvtsi2sdq (%rsp), %xmm1 addsd %xmm1, %xmm0 movq 24(%rsp), %rax subq %fs:40, %rax jne .L6 addq $40, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L6: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size _Z8my_timerv, .-_Z8my_timerv .globl _Z12matrixMulCPUPaS_Pii .type _Z12matrixMulCPUPaS_Pii, @function _Z12matrixMulCPUPaS_Pii: .LFB2058: .cfi_startproc endbr64 testl %ecx, %ecx jle .L15 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 movq %rdi, %r9 movq %rsi, %r12 movq %rdx, %r11 movl %ecx, %ebp movslq %ecx, %r8 leaq 0(,%r8,4), %r14 addq %r14, %r11 movq %r8, %r13 negq %r13 salq $2, %r13 movl $0, %ebx .L9: leaq (%r11,%r13), %r10 movq %r12, %rdi .L12: movl $0, %eax movl $0, %ecx .L10: movsbl (%r9,%rax), %edx movsbl (%rdi,%rax), %esi imull %esi, %edx addl %edx, %ecx addq $1, %rax cmpq %r8, %rax jne .L10 movl %ecx, (%r10) addq $4, %r10 addq %r8, %rdi cmpq %r11, %r10 jne .L12 addl $1, %ebx addq %r14, %r11 addq %r8, %r9 cmpl %ebx, %ebp jne .L9 popq %rbx .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .L15: .cfi_restore 3 .cfi_restore 6 .cfi_restore 12 .cfi_restore 13 .cfi_restore 14 ret .cfi_endproc .LFE2058: .size _Z12matrixMulCPUPaS_Pii, .-_Z12matrixMulCPUPaS_Pii .globl _Z37__device_stub__Z12matrixMulGPUPaS_PiiPaS_Pii .type _Z37__device_stub__Z12matrixMulGPUPaS_PiiPaS_Pii, @function _Z37__device_stub__Z12matrixMulGPUPaS_PiiPaS_Pii: .LFB2084: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movl %ecx, 4(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L22 .L18: movq 136(%rsp), %rax subq %fs:40, %rax jne .L23 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L22: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z12matrixMulGPUPaS_Pii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L18 .L23: call __stack_chk_fail@PLT .cfi_endproc .LFE2084: .size _Z37__device_stub__Z12matrixMulGPUPaS_PiiPaS_Pii, .-_Z37__device_stub__Z12matrixMulGPUPaS_PiiPaS_Pii .globl _Z12matrixMulGPUPaS_Pii .type _Z12matrixMulGPUPaS_Pii, @function _Z12matrixMulGPUPaS_Pii: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z37__device_stub__Z12matrixMulGPUPaS_PiiPaS_Pii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _Z12matrixMulGPUPaS_Pii, .-_Z12matrixMulGPUPaS_Pii .section .rodata.str1.1,"aMS",@progbits,1 .LC1: .string "Error input options\n" .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC2: .string "The GPU Elapsed Time:%lf Sec.\n" .align 8 .LC3: .string "The CPU Elapsed Time:%lf Sec.\n" .section .rodata.str1.1 .LC4: .string "Verifying\n" .LC5: .string "Error:%d, %d, %d\n" .LC6: .string "Verify Success!!\n" .text .globl main .type main, @function main: .LFB2059: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $104, %rsp .cfi_def_cfa_offset 160 movq %fs:40, %rax movq %rax, 88(%rsp) xorl %eax, %eax cmpl $1, %edi jle .L40 movq 8(%rsi), %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT movq %rax, 24(%rsp) movl %eax, 20(%rsp) movl %eax, %r15d imull %eax, %r15d movslq %r15d, %rbx movq %rbx, %rdi call malloc@PLT movq %rax, %r14 leaq 40(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT movq %rbx, %rdi call malloc@PLT movq %rax, %r13 leaq 48(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq 0(,%rbx,4), %r12 movq %r12, 8(%rsp) movq %r12, %rdi call malloc@PLT movq %rax, %rbp leaq 56(%rsp), %rdi movq %r12, %rsi call cudaMalloc@PLT movq %r12, %rdi call malloc@PLT movq %rax, %r12 movl $0, %edi call time@PLT movl %eax, %edi call srand@PLT testl %r15d, %r15d jle .L28 movl $0, %eax .L29: movb $1, (%r14,%rax) movb $1, 0(%r13,%rax) movl $0, 0(%rbp,%rax,4) movl $0, (%r12,%rax,4) addq $1, %rax cmpq %rax, %rbx jne .L29 .L28: movl $1, %ecx movq %rbx, %rdx movq %r14, %rsi movq 40(%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movq %rbx, %rdx movq %r13, %rsi movq 48(%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movq 8(%rsp), %rdx movq %rbp, %rsi movq 56(%rsp), %rdi call cudaMemcpy@PLT call cudaDeviceSynchronize@PLT movl $1, 72(%rsp) movl 24(%rsp), %eax shrl $4, %eax movl %eax, 76(%rsp) movl %eax, 80(%rsp) movl $1, 84(%rsp) call _Z8my_timerv movsd %xmm0, 24(%rsp) movl $16, 64(%rsp) movl $16, 68(%rsp) movl 72(%rsp), %ecx movl $0, %r9d movl $0, %r8d movq 64(%rsp), %rdx movq 76(%rsp), %rdi movl 84(%rsp), %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L41 .L30: call cudaDeviceSynchronize@PLT call _Z8my_timerv subsd 24(%rsp), %xmm0 leaq .LC2(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT movl $2, %ecx movq 8(%rsp), %rdx movq 56(%rsp), %rsi movq %rbp, %rdi call cudaMemcpy@PLT call cudaDeviceSynchronize@PLT call _Z8my_timerv movsd %xmm0, 8(%rsp) movl 20(%rsp), %ecx movq %r12, %rdx movq %r13, %rsi movq %r14, %rdi call _Z12matrixMulCPUPaS_Pii call _Z8my_timerv subsd 8(%rsp), %xmm0 leaq .LC3(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT leaq .LC4(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT testl %r15d, %r15d jle .L31 movl $0, %r8d jmp .L34 .L40: leaq .LC1(%rip), %rsi movl $2, %edi call __printf_chk@PLT movl $1, %edi call exit@PLT .L41: movl 20(%rsp), %ecx movq 56(%rsp), %rdx movq 48(%rsp), %rsi movq 40(%rsp), %rdi call _Z37__device_stub__Z12matrixMulGPUPaS_PiiPaS_Pii jmp .L30 .L37: movq %rax, %r8 .L34: movl 0(%rbp,%r8,4), %esi movl (%r12,%r8,4), %ecx movl %esi, %edx subl %ecx, %edx movl %edx, %eax negl %eax cmovs %edx, %eax testl %eax, %eax jg .L42 leaq 1(%r8), %rax cmpq %rax, %rbx jne .L37 leal 1(%r8), %ebx jmp .L33 .L42: movl %r8d, %ebx movl %esi, %edx leaq .LC5(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT .L33: cmpl %ebx, %r15d je .L31 .L35: movq %r14, %rdi call free@PLT movq 40(%rsp), %rdi call cudaFree@PLT movq %r13, %rdi call free@PLT movq 48(%rsp), %rdi call cudaFree@PLT movq %rbp, %rdi call free@PLT movq 56(%rsp), %rdi call cudaFree@PLT movq %r12, %rdi call free@PLT movq 88(%rsp), %rax subq %fs:40, %rax jne .L43 movl $0, %eax addq $104, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L31: .cfi_restore_state leaq .LC6(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT jmp .L35 .L43: call __stack_chk_fail@PLT .cfi_endproc .LFE2059: .size main, .-main .section .rodata.str1.1 .LC7: .string "_Z12matrixMulGPUPaS_Pii" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2087: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC7(%rip), %rdx movq %rdx, %rcx leaq _Z12matrixMulGPUPaS_Pii(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2087: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst8,"aM",@progbits,8 .align 8 .LC0: .long 0 .long 1093567616 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "matrixMul8.hip" .section .rodata.cst8,"aM",@progbits,8 .p2align 3, 0x0 # -- Begin function _Z8my_timerv .LCPI0_0: .quad 0x412e848000000000 # double 1.0E+6 .text .globl _Z8my_timerv .p2align 4, 0x90 .type _Z8my_timerv,@function _Z8my_timerv: # @_Z8my_timerv .cfi_startproc # %bb.0: subq $24, %rsp .cfi_def_cfa_offset 32 leaq 8(%rsp), %rdi xorl %esi, %esi callq gettimeofday cvtsi2sdq 8(%rsp), %xmm1 cvtsi2sdq 16(%rsp), %xmm0 divsd .LCPI0_0(%rip), %xmm0 addsd %xmm1, %xmm0 addq $24, %rsp .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z8my_timerv, .Lfunc_end0-_Z8my_timerv .cfi_endproc # -- End function .globl _Z12matrixMulCPUPaS_Pii # -- Begin function _Z12matrixMulCPUPaS_Pii .p2align 4, 0x90 .type _Z12matrixMulCPUPaS_Pii,@function _Z12matrixMulCPUPaS_Pii: # @_Z12matrixMulCPUPaS_Pii .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %rdx, -8(%rsp) # 8-byte Spill testl %ecx, %ecx jle .LBB1_7 # %bb.1: # %.preheader26.lr.ph movl %ecx, %eax xorl %edx, %edx xorl %r9d, %r9d .p2align 4, 0x90 .LBB1_2: # %.preheader26 # =>This Loop Header: Depth=1 # Child Loop BB1_3 Depth 2 # Child Loop BB1_4 Depth 3 movl %edx, %r10d addq %rdi, %r10 movl %r9d, %r11d imull %ecx, %r11d movq -8(%rsp), %r8 # 8-byte Reload leaq (%r8,%r11,4), %r11 xorl %ebx, %ebx xorl %r14d, %r14d .p2align 4, 0x90 .LBB1_3: # %.preheader # Parent Loop BB1_2 Depth=1 # => This Loop Header: Depth=2 # Child Loop BB1_4 Depth 3 movl %ebx, %r15d addq %rsi, %r15 xorl %r12d, %r12d xorl %ebp, %ebp .p2align 4, 0x90 .LBB1_4: # Parent Loop BB1_2 Depth=1 # Parent Loop BB1_3 Depth=2 # => This Inner Loop Header: Depth=3 movsbl (%r10,%r12), %r13d movsbl (%r15,%r12), %r8d imull %r13d, %r8d addl %r8d, %ebp incq %r12 cmpq %r12, %rax jne .LBB1_4 # %bb.5: # %._crit_edge # in Loop: Header=BB1_3 Depth=2 movl %ebp, (%r11,%r14,4) incq %r14 addl %ecx, %ebx cmpq %rax, %r14 jne .LBB1_3 # %bb.6: # %._crit_edge30 # in Loop: Header=BB1_2 Depth=1 incq %r9 addl %ecx, %edx cmpq %rax, %r9 jne .LBB1_2 .LBB1_7: # %._crit_edge32 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size _Z12matrixMulCPUPaS_Pii, .Lfunc_end1-_Z12matrixMulCPUPaS_Pii .cfi_endproc # -- End function .globl _Z27__device_stub__matrixMulGPUPaS_Pii # -- Begin function _Z27__device_stub__matrixMulGPUPaS_Pii .p2align 4, 0x90 .type _Z27__device_stub__matrixMulGPUPaS_Pii,@function _Z27__device_stub__matrixMulGPUPaS_Pii: # @_Z27__device_stub__matrixMulGPUPaS_Pii .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movl %ecx, 4(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z12matrixMulGPUPaS_Pii, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end2: .size _Z27__device_stub__matrixMulGPUPaS_Pii, .Lfunc_end2-_Z27__device_stub__matrixMulGPUPaS_Pii .cfi_endproc # -- End function .section .rodata.cst8,"aM",@progbits,8 .p2align 3, 0x0 # -- Begin function main .LCPI3_0: .quad 0x412e848000000000 # double 1.0E+6 .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $184, %rsp .cfi_def_cfa_offset 240 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 cmpl $1, %edi jle .LBB3_20 # %bb.1: movq 8(%rsi), %rdi xorl %esi, %esi movl $10, %edx callq __isoc23_strtol movq %rax, %rbp movl %ebp, %r12d imull %r12d, %r12d movq %r12, %rdi callq malloc movq %rax, %rbx leaq 72(%rsp), %rdi movq %r12, %rsi callq hipMalloc movq %r12, %rdi callq malloc movq %rax, %r14 leaq 64(%rsp), %rdi movq %r12, %rsi callq hipMalloc leaq (,%r12,4), %r15 movq %r15, %rdi callq malloc movq %rax, 56(%rsp) # 8-byte Spill leaq 8(%rsp), %rdi movq %r15, %rsi callq hipMalloc movq %r15, 48(%rsp) # 8-byte Spill movq %r15, %rdi callq malloc movq %rax, %r13 xorl %edi, %edi callq time movl %eax, %edi callq srand testl %ebp, %ebp je .LBB3_3 # %bb.2: # %.lr.ph.preheader cmpl $2, %r12d movl $1, %r15d cmovael %r12d, %r15d movq %rbx, %rdi movl $1, %esi movq %r15, %rdx callq memset@PLT movq %r14, %rdi movl $1, %esi movq %r15, %rdx callq memset@PLT shlq $2, %r15 movq 56(%rsp), %rdi # 8-byte Reload xorl %esi, %esi movq %r15, %rdx callq memset@PLT movq %r13, %rdi xorl %esi, %esi movq %r15, %rdx callq memset@PLT .LBB3_3: # %._crit_edge movq %r13, 88(%rsp) # 8-byte Spill movq 72(%rsp), %rdi movq %rbx, %rsi movq %r12, %rdx movl $1, %ecx callq hipMemcpy movq 64(%rsp), %rdi movq %r14, %rsi movq %r12, 104(%rsp) # 8-byte Spill movq %r12, %rdx movl $1, %ecx callq hipMemcpy movq 8(%rsp), %rdi movq 56(%rsp), %r13 # 8-byte Reload movq %r13, %rsi movq 48(%rsp), %r12 # 8-byte Reload movq %r12, %rdx movl $1, %ecx callq hipMemcpy callq hipDeviceSynchronize movl %ebp, %eax shrl $4, %eax movq %rax, %r15 shlq $32, %r15 orq %rax, %r15 leaq 16(%rsp), %rdi xorl %esi, %esi callq gettimeofday cvtsi2sdq 16(%rsp), %xmm0 cvtsi2sdq 24(%rsp), %xmm1 divsd .LCPI3_0(%rip), %xmm1 addsd %xmm0, %xmm1 movsd %xmm1, 96(%rsp) # 8-byte Spill movabsq $68719476752, %rdx # imm = 0x1000000010 movq %r15, %rdi movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB3_5 # %bb.4: movq 72(%rsp), %rax movq 64(%rsp), %rcx movq 8(%rsp), %rdx movq %rax, 176(%rsp) movq %rcx, 168(%rsp) movq %rdx, 160(%rsp) movl %ebp, 84(%rsp) leaq 176(%rsp), %rax movq %rax, 16(%rsp) leaq 168(%rsp), %rax movq %rax, 24(%rsp) leaq 160(%rsp), %rax movq %rax, 32(%rsp) leaq 84(%rsp), %rax movq %rax, 40(%rsp) leaq 144(%rsp), %rdi leaq 128(%rsp), %rsi leaq 120(%rsp), %rdx leaq 112(%rsp), %rcx callq __hipPopCallConfiguration movq 144(%rsp), %rsi movl 152(%rsp), %edx movq 128(%rsp), %rcx movl 136(%rsp), %r8d leaq 16(%rsp), %r9 movl $_Z12matrixMulGPUPaS_Pii, %edi pushq 112(%rsp) .cfi_adjust_cfa_offset 8 pushq 128(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB3_5: callq hipDeviceSynchronize leaq 16(%rsp), %rdi xorl %esi, %esi callq gettimeofday xorps %xmm1, %xmm1 cvtsi2sdq 16(%rsp), %xmm1 xorps %xmm0, %xmm0 cvtsi2sdq 24(%rsp), %xmm0 divsd .LCPI3_0(%rip), %xmm0 addsd %xmm1, %xmm0 subsd 96(%rsp), %xmm0 # 8-byte Folded Reload movl $.L.str.1, %edi movb $1, %al callq printf movq 8(%rsp), %rsi movq %r13, %rdi movq %r12, %rdx movl $2, %ecx callq hipMemcpy callq hipDeviceSynchronize leaq 16(%rsp), %rdi xorl %esi, %esi callq gettimeofday xorps %xmm0, %xmm0 cvtsi2sdq 16(%rsp), %xmm0 xorps %xmm1, %xmm1 cvtsi2sdq 24(%rsp), %xmm1 divsd .LCPI3_0(%rip), %xmm1 addsd %xmm0, %xmm1 movsd %xmm1, 48(%rsp) # 8-byte Spill testl %ebp, %ebp jle .LBB3_12 # %bb.6: # %.preheader26.lr.ph.i movl %ebp, %eax xorl %ecx, %ecx xorl %edx, %edx .p2align 4, 0x90 .LBB3_7: # %.preheader26.i # =>This Loop Header: Depth=1 # Child Loop BB3_8 Depth 2 # Child Loop BB3_9 Depth 3 movl %ecx, %esi movq %rbx, %r13 addq %rbx, %rsi movl %edx, %edi imull %ebp, %edi movq 88(%rsp), %r8 # 8-byte Reload leaq (%r8,%rdi,4), %rdi xorl %r8d, %r8d xorl %r9d, %r9d .p2align 4, 0x90 .LBB3_8: # %.preheader.i # Parent Loop BB3_7 Depth=1 # => This Loop Header: Depth=2 # Child Loop BB3_9 Depth 3 movl %r8d, %r10d addq %r14, %r10 xorl %r11d, %r11d xorl %r12d, %r12d .p2align 4, 0x90 .LBB3_9: # Parent Loop BB3_7 Depth=1 # Parent Loop BB3_8 Depth=2 # => This Inner Loop Header: Depth=3 movsbl (%rsi,%r11), %ebx movsbl (%r10,%r11), %r15d imull %ebx, %r15d addl %r15d, %r12d incq %r11 cmpq %r11, %rax jne .LBB3_9 # %bb.10: # %._crit_edge.i # in Loop: Header=BB3_8 Depth=2 movl %r12d, (%rdi,%r9,4) incq %r9 addl %ebp, %r8d cmpq %rax, %r9 jne .LBB3_8 # %bb.11: # %._crit_edge30.i # in Loop: Header=BB3_7 Depth=1 incq %rdx addl %ebp, %ecx cmpq %rax, %rdx movq %r13, %rbx jne .LBB3_7 .LBB3_12: # %_Z12matrixMulCPUPaS_Pii.exit leaq 16(%rsp), %rdi xorl %esi, %esi callq gettimeofday xorps %xmm1, %xmm1 cvtsi2sdq 16(%rsp), %xmm1 xorps %xmm0, %xmm0 cvtsi2sdq 24(%rsp), %xmm0 divsd .LCPI3_0(%rip), %xmm0 addsd %xmm1, %xmm0 subsd 48(%rsp), %xmm0 # 8-byte Folded Reload movl $.L.str.2, %edi movb $1, %al callq printf movl $.Lstr, %edi callq puts@PLT testl %ebp, %ebp movq 104(%rsp), %r15 # 8-byte Reload movq 56(%rsp), %r12 # 8-byte Reload movq 88(%rsp), %r13 # 8-byte Reload movl $0, %eax je .LBB3_17 # %bb.13: # %.lr.ph84.preheader cmpl $2, %r15d movl $1, %eax cmovael %r15d, %eax xorl %ebp, %ebp .p2align 4, 0x90 .LBB3_14: # %.lr.ph84 # =>This Inner Loop Header: Depth=1 movl (%r12,%rbp,4), %esi movl (%r13,%rbp,4), %edx cmpl %edx, %esi jne .LBB3_15 # %bb.16: # in Loop: Header=BB3_14 Depth=1 incq %rbp cmpq %rbp, %rax jne .LBB3_14 .LBB3_17: # %.loopexit cmpl %r15d, %eax jne .LBB3_19 .LBB3_18: movl $.Lstr.1, %edi callq puts@PLT .LBB3_19: movq %rbx, %rdi callq free movq 72(%rsp), %rdi callq hipFree movq %r14, %rdi callq free movq 64(%rsp), %rdi callq hipFree movq %r12, %rdi callq free movq 8(%rsp), %rdi callq hipFree movq %r13, %rdi callq free xorl %eax, %eax addq $184, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB3_15: .cfi_def_cfa_offset 240 movl $.L.str.4, %edi movl %ebp, %ecx xorl %eax, %eax callq printf movl %ebp, %eax cmpl %r15d, %eax je .LBB3_18 jmp .LBB3_19 .LBB3_20: movl $.Lstr.2, %edi callq puts@PLT movl $1, %edi callq exit .Lfunc_end3: .size main, .Lfunc_end3-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB4_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB4_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z12matrixMulGPUPaS_Pii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end4: .size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB5_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB5_2: retq .Lfunc_end5: .size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor .cfi_endproc # -- End function .type _Z12matrixMulGPUPaS_Pii,@object # @_Z12matrixMulGPUPaS_Pii .section .rodata,"a",@progbits .globl _Z12matrixMulGPUPaS_Pii .p2align 3, 0x0 _Z12matrixMulGPUPaS_Pii: .quad _Z27__device_stub__matrixMulGPUPaS_Pii .size _Z12matrixMulGPUPaS_Pii, 8 .type .L.str.1,@object # @.str.1 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.1: .asciz "The GPU Elapsed Time:%lf Sec.\n" .size .L.str.1, 31 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "The CPU Elapsed Time:%lf Sec.\n" .size .L.str.2, 31 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "Error:%d, %d, %d\n" .size .L.str.4, 18 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z12matrixMulGPUPaS_Pii" .size .L__unnamed_1, 24 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .type .Lstr,@object # @str .section .rodata.str1.1,"aMS",@progbits,1 .Lstr: .asciz "Verifying" .size .Lstr, 10 .type .Lstr.1,@object # @str.1 .Lstr.1: .asciz "Verify Success!!" .size .Lstr.1, 17 .type .Lstr.2,@object # @str.2 .Lstr.2: .asciz "Error input options" .size .Lstr.2, 20 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z27__device_stub__matrixMulGPUPaS_Pii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z12matrixMulGPUPaS_Pii .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include "includes.h" __global__ void AssembleArrayOfNoticedChannels ( const int nmbrOfChnnls, const float lwrNtcdEnrg, const float hghrNtcdEnrg, const float *lwrChnnlBndrs, const float *hghrChnnlBndrs, const float *gdQltChnnls, float *ntcdChnnls ) { int c = threadIdx.x + blockDim.x * blockIdx.x; if ( c < nmbrOfChnnls ) { ntcdChnnls[c] = ( lwrChnnlBndrs[c] > lwrNtcdEnrg ) * ( hghrChnnlBndrs[c] < hghrNtcdEnrg ) * ( 1 - gdQltChnnls[c] ); } }
code for sm_80 Function : _Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */ /* 0x000e280000002100 */ /*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */ /* 0x000e240000002500 */ /*0030*/ IMAD R8, R3, c[0x0][0x0], R8 ; /* 0x0000000003087a24 */ /* 0x001fca00078e0208 */ /*0040*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x160], PT ; /* 0x0000580008007a0c */ /* 0x000fda0003f06270 */ /*0050*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */ /* 0x000fe200000001ff */ /*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fd20000000a00 */ /*0080*/ IMAD.WIDE R4, R8, R9, c[0x0][0x178] ; /* 0x00005e0008047625 */ /* 0x000fc800078e0209 */ /*0090*/ IMAD.WIDE R2, R8.reuse, R9.reuse, c[0x0][0x170] ; /* 0x00005c0008027625 */ /* 0x0c0fe400078e0209 */ /*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */ /* 0x000ea8000c1e1900 */ /*00b0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */ /* 0x000ee2000c1e1900 */ /*00c0*/ IMAD.WIDE R6, R8, R9, c[0x0][0x180] ; /* 0x0000600008067625 */ /* 0x000fcc00078e0209 */ /*00d0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */ /* 0x000f22000c1e1900 */ /*00e0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x188] ; /* 0x0000620008087625 */ /* 0x000fe200078e0209 */ /*00f0*/ FSETP.GEU.AND P0, PT, R4, c[0x0][0x168], PT ; /* 0x00005a0004007a0b */ /* 0x004fc80003f0e000 */ /*0100*/ FSETP.GT.AND P0, PT, R2, c[0x0][0x164], !P0 ; /* 0x0000590002007a0b */ /* 0x008fc80004704000 */ /*0110*/ SEL R0, RZ, 0x1, !P0 ; /* 0x00000001ff007807 */ /* 0x000fe20004000000 */ /*0120*/ FADD R11, -R6, 1 ; /* 0x3f800000060b7421 */ /* 0x010fca0000000100 */ /*0130*/ I2F.U32 R0, R0 ; /* 0x0000000000007306 */ /* 0x000e240000201000 */ /*0140*/ FMUL R11, R0, R11 ; /* 0x0000000b000b7220 */ /* 0x001fca0000400000 */ /*0150*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */ /* 0x000fe2000c101904 */ /*0160*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0170*/ BRA 0x170; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0180*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0190*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include "includes.h" __global__ void AssembleArrayOfNoticedChannels ( const int nmbrOfChnnls, const float lwrNtcdEnrg, const float hghrNtcdEnrg, const float *lwrChnnlBndrs, const float *hghrChnnlBndrs, const float *gdQltChnnls, float *ntcdChnnls ) { int c = threadIdx.x + blockDim.x * blockIdx.x; if ( c < nmbrOfChnnls ) { ntcdChnnls[c] = ( lwrChnnlBndrs[c] > lwrNtcdEnrg ) * ( hghrChnnlBndrs[c] < hghrNtcdEnrg ) * ( 1 - gdQltChnnls[c] ); } }
.file "tmpxft_0002c937_00000000-6_AssembleArrayOfNoticedChannels.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z62__device_stub__Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_PfiffPKfS0_S0_Pf .type _Z62__device_stub__Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_PfiffPKfS0_S0_Pf, @function _Z62__device_stub__Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_PfiffPKfS0_S0_Pf: .LFB2051: .cfi_startproc endbr64 subq $184, %rsp .cfi_def_cfa_offset 192 movl %edi, 44(%rsp) movss %xmm0, 40(%rsp) movss %xmm1, 36(%rsp) movq %rsi, 24(%rsp) movq %rdx, 16(%rsp) movq %rcx, 8(%rsp) movq %r8, (%rsp) movq %fs:40, %rax movq %rax, 168(%rsp) xorl %eax, %eax leaq 44(%rsp), %rax movq %rax, 112(%rsp) leaq 40(%rsp), %rax movq %rax, 120(%rsp) leaq 36(%rsp), %rax movq %rax, 128(%rsp) leaq 24(%rsp), %rax movq %rax, 136(%rsp) leaq 16(%rsp), %rax movq %rax, 144(%rsp) leaq 8(%rsp), %rax movq %rax, 152(%rsp) movq %rsp, %rax movq %rax, 160(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) movl $1, 72(%rsp) movl $1, 76(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) leaq 56(%rsp), %rcx leaq 48(%rsp), %rdx leaq 76(%rsp), %rsi leaq 64(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 168(%rsp), %rax subq %fs:40, %rax jne .L8 addq $184, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 56(%rsp) .cfi_def_cfa_offset 200 pushq 56(%rsp) .cfi_def_cfa_offset 208 leaq 128(%rsp), %r9 movq 92(%rsp), %rcx movl 100(%rsp), %r8d movq 80(%rsp), %rsi movl 88(%rsp), %edx leaq _Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 192 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z62__device_stub__Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_PfiffPKfS0_S0_Pf, .-_Z62__device_stub__Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_PfiffPKfS0_S0_Pf .globl _Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf .type _Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf, @function _Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z62__device_stub__Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_PfiffPKfS0_S0_Pf addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf, .-_Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC0: .string "_Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include "includes.h" __global__ void AssembleArrayOfNoticedChannels ( const int nmbrOfChnnls, const float lwrNtcdEnrg, const float hghrNtcdEnrg, const float *lwrChnnlBndrs, const float *hghrChnnlBndrs, const float *gdQltChnnls, float *ntcdChnnls ) { int c = threadIdx.x + blockDim.x * blockIdx.x; if ( c < nmbrOfChnnls ) { ntcdChnnls[c] = ( lwrChnnlBndrs[c] > lwrNtcdEnrg ) * ( hghrChnnlBndrs[c] < hghrNtcdEnrg ) * ( 1 - gdQltChnnls[c] ); } }
#include <hip/hip_runtime.h> #include "includes.h" __global__ void AssembleArrayOfNoticedChannels ( const int nmbrOfChnnls, const float lwrNtcdEnrg, const float hghrNtcdEnrg, const float *lwrChnnlBndrs, const float *hghrChnnlBndrs, const float *gdQltChnnls, float *ntcdChnnls ) { int c = threadIdx.x + blockDim.x * blockIdx.x; if ( c < nmbrOfChnnls ) { ntcdChnnls[c] = ( lwrChnnlBndrs[c] > lwrNtcdEnrg ) * ( hghrChnnlBndrs[c] < hghrNtcdEnrg ) * ( 1 - gdQltChnnls[c] ); } }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <hip/hip_runtime.h> #include "includes.h" __global__ void AssembleArrayOfNoticedChannels ( const int nmbrOfChnnls, const float lwrNtcdEnrg, const float hghrNtcdEnrg, const float *lwrChnnlBndrs, const float *hghrChnnlBndrs, const float *gdQltChnnls, float *ntcdChnnls ) { int c = threadIdx.x + blockDim.x * blockIdx.x; if ( c < nmbrOfChnnls ) { ntcdChnnls[c] = ( lwrChnnlBndrs[c] > lwrNtcdEnrg ) * ( hghrChnnlBndrs[c] < hghrNtcdEnrg ) * ( 1 - gdQltChnnls[c] ); } }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf .globl _Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf .p2align 8 .type _Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf,@function _Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf: s_clause 0x1 s_load_b32 s2, s[0:1], 0x3c s_load_b32 s3, s[0:1], 0x0 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s3, v1 s_cbranch_execz .LBB0_2 s_load_b256 s[4:11], s[0:1], 0x10 v_ashrrev_i32_e32 v2, 31, v1 s_load_b64 s[0:1], s[0:1], 0x4 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s4, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo v_add_co_u32 v4, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo v_add_co_u32 v6, vcc_lo, s8, v0 v_add_co_ci_u32_e32 v7, vcc_lo, s9, v1, vcc_lo global_load_b32 v2, v[2:3], off global_load_b32 v3, v[4:5], off global_load_b32 v4, v[6:7], off s_waitcnt vmcnt(2) v_cmp_lt_f32_e32 vcc_lo, s0, v2 s_waitcnt vmcnt(1) v_cmp_gt_f32_e64 s0, s1, v3 s_waitcnt vmcnt(0) v_sub_f32_e32 v2, 1.0, v4 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2) s_and_b32 s0, vcc_lo, s0 v_add_co_u32 v0, vcc_lo, s10, v0 v_cndmask_b32_e64 v3, 0, 1.0, s0 v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo v_mul_f32_e32 v2, v2, v3 global_store_b32 v[0:1], v2, off .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 304 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 8 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf, .Lfunc_end0-_Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .offset: 0 .size: 4 .value_kind: by_value - .offset: 4 .size: 4 .value_kind: by_value - .offset: 8 .size: 4 .value_kind: by_value - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 40 .size: 8 .value_kind: global_buffer - .offset: 48 .size: 4 .value_kind: hidden_block_count_x - .offset: 52 .size: 4 .value_kind: hidden_block_count_y - .offset: 56 .size: 4 .value_kind: hidden_block_count_z - .offset: 60 .size: 2 .value_kind: hidden_group_size_x - .offset: 62 .size: 2 .value_kind: hidden_group_size_y - .offset: 64 .size: 2 .value_kind: hidden_group_size_z - .offset: 66 .size: 2 .value_kind: hidden_remainder_x - .offset: 68 .size: 2 .value_kind: hidden_remainder_y - .offset: 70 .size: 2 .value_kind: hidden_remainder_z - .offset: 88 .size: 8 .value_kind: hidden_global_offset_x - .offset: 96 .size: 8 .value_kind: hidden_global_offset_y - .offset: 104 .size: 8 .value_kind: hidden_global_offset_z - .offset: 112 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 304 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 8 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <hip/hip_runtime.h> #include "includes.h" __global__ void AssembleArrayOfNoticedChannels ( const int nmbrOfChnnls, const float lwrNtcdEnrg, const float hghrNtcdEnrg, const float *lwrChnnlBndrs, const float *hghrChnnlBndrs, const float *gdQltChnnls, float *ntcdChnnls ) { int c = threadIdx.x + blockDim.x * blockIdx.x; if ( c < nmbrOfChnnls ) { ntcdChnnls[c] = ( lwrChnnlBndrs[c] > lwrNtcdEnrg ) * ( hghrChnnlBndrs[c] < hghrNtcdEnrg ) * ( 1 - gdQltChnnls[c] ); } }
.text .file "AssembleArrayOfNoticedChannels.hip" .globl _Z45__device_stub__AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf # -- Begin function _Z45__device_stub__AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf .p2align 4, 0x90 .type _Z45__device_stub__AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf,@function _Z45__device_stub__AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf: # @_Z45__device_stub__AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf .cfi_startproc # %bb.0: subq $152, %rsp .cfi_def_cfa_offset 160 movl %edi, 12(%rsp) movss %xmm0, 8(%rsp) movss %xmm1, 4(%rsp) movq %rsi, 88(%rsp) movq %rdx, 80(%rsp) movq %rcx, 72(%rsp) movq %r8, 64(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 8(%rsp), %rax movq %rax, 104(%rsp) leaq 4(%rsp), %rax movq %rax, 112(%rsp) leaq 88(%rsp), %rax movq %rax, 120(%rsp) leaq 80(%rsp), %rax movq %rax, 128(%rsp) leaq 72(%rsp), %rax movq %rax, 136(%rsp) leaq 64(%rsp), %rax movq %rax, 144(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $168, %rsp .cfi_adjust_cfa_offset -168 retq .Lfunc_end0: .size _Z45__device_stub__AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf, .Lfunc_end0-_Z45__device_stub__AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf,@object # @_Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf .section .rodata,"a",@progbits .globl _Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf .p2align 3, 0x0 _Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf: .quad _Z45__device_stub__AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf .size _Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf" .size .L__unnamed_1, 49 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z45__device_stub__AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */ /* 0x000e280000002100 */ /*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */ /* 0x000e240000002500 */ /*0030*/ IMAD R8, R3, c[0x0][0x0], R8 ; /* 0x0000000003087a24 */ /* 0x001fca00078e0208 */ /*0040*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x160], PT ; /* 0x0000580008007a0c */ /* 0x000fda0003f06270 */ /*0050*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */ /* 0x000fe200000001ff */ /*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fd20000000a00 */ /*0080*/ IMAD.WIDE R4, R8, R9, c[0x0][0x178] ; /* 0x00005e0008047625 */ /* 0x000fc800078e0209 */ /*0090*/ IMAD.WIDE R2, R8.reuse, R9.reuse, c[0x0][0x170] ; /* 0x00005c0008027625 */ /* 0x0c0fe400078e0209 */ /*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */ /* 0x000ea8000c1e1900 */ /*00b0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */ /* 0x000ee2000c1e1900 */ /*00c0*/ IMAD.WIDE R6, R8, R9, c[0x0][0x180] ; /* 0x0000600008067625 */ /* 0x000fcc00078e0209 */ /*00d0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */ /* 0x000f22000c1e1900 */ /*00e0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x188] ; /* 0x0000620008087625 */ /* 0x000fe200078e0209 */ /*00f0*/ FSETP.GEU.AND P0, PT, R4, c[0x0][0x168], PT ; /* 0x00005a0004007a0b */ /* 0x004fc80003f0e000 */ /*0100*/ FSETP.GT.AND P0, PT, R2, c[0x0][0x164], !P0 ; /* 0x0000590002007a0b */ /* 0x008fc80004704000 */ /*0110*/ SEL R0, RZ, 0x1, !P0 ; /* 0x00000001ff007807 */ /* 0x000fe20004000000 */ /*0120*/ FADD R11, -R6, 1 ; /* 0x3f800000060b7421 */ /* 0x010fca0000000100 */ /*0130*/ I2F.U32 R0, R0 ; /* 0x0000000000007306 */ /* 0x000e240000201000 */ /*0140*/ FMUL R11, R0, R11 ; /* 0x0000000b000b7220 */ /* 0x001fca0000400000 */ /*0150*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */ /* 0x000fe2000c101904 */ /*0160*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0170*/ BRA 0x170; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0180*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0190*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf .globl _Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf .p2align 8 .type _Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf,@function _Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf: s_clause 0x1 s_load_b32 s2, s[0:1], 0x3c s_load_b32 s3, s[0:1], 0x0 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s3, v1 s_cbranch_execz .LBB0_2 s_load_b256 s[4:11], s[0:1], 0x10 v_ashrrev_i32_e32 v2, 31, v1 s_load_b64 s[0:1], s[0:1], 0x4 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s4, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo v_add_co_u32 v4, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo v_add_co_u32 v6, vcc_lo, s8, v0 v_add_co_ci_u32_e32 v7, vcc_lo, s9, v1, vcc_lo global_load_b32 v2, v[2:3], off global_load_b32 v3, v[4:5], off global_load_b32 v4, v[6:7], off s_waitcnt vmcnt(2) v_cmp_lt_f32_e32 vcc_lo, s0, v2 s_waitcnt vmcnt(1) v_cmp_gt_f32_e64 s0, s1, v3 s_waitcnt vmcnt(0) v_sub_f32_e32 v2, 1.0, v4 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2) s_and_b32 s0, vcc_lo, s0 v_add_co_u32 v0, vcc_lo, s10, v0 v_cndmask_b32_e64 v3, 0, 1.0, s0 v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo v_mul_f32_e32 v2, v2, v3 global_store_b32 v[0:1], v2, off .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 304 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 8 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf, .Lfunc_end0-_Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .offset: 0 .size: 4 .value_kind: by_value - .offset: 4 .size: 4 .value_kind: by_value - .offset: 8 .size: 4 .value_kind: by_value - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 40 .size: 8 .value_kind: global_buffer - .offset: 48 .size: 4 .value_kind: hidden_block_count_x - .offset: 52 .size: 4 .value_kind: hidden_block_count_y - .offset: 56 .size: 4 .value_kind: hidden_block_count_z - .offset: 60 .size: 2 .value_kind: hidden_group_size_x - .offset: 62 .size: 2 .value_kind: hidden_group_size_y - .offset: 64 .size: 2 .value_kind: hidden_group_size_z - .offset: 66 .size: 2 .value_kind: hidden_remainder_x - .offset: 68 .size: 2 .value_kind: hidden_remainder_y - .offset: 70 .size: 2 .value_kind: hidden_remainder_z - .offset: 88 .size: 8 .value_kind: hidden_global_offset_x - .offset: 96 .size: 8 .value_kind: hidden_global_offset_y - .offset: 104 .size: 8 .value_kind: hidden_global_offset_z - .offset: 112 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 304 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 8 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_0002c937_00000000-6_AssembleArrayOfNoticedChannels.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z62__device_stub__Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_PfiffPKfS0_S0_Pf .type _Z62__device_stub__Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_PfiffPKfS0_S0_Pf, @function _Z62__device_stub__Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_PfiffPKfS0_S0_Pf: .LFB2051: .cfi_startproc endbr64 subq $184, %rsp .cfi_def_cfa_offset 192 movl %edi, 44(%rsp) movss %xmm0, 40(%rsp) movss %xmm1, 36(%rsp) movq %rsi, 24(%rsp) movq %rdx, 16(%rsp) movq %rcx, 8(%rsp) movq %r8, (%rsp) movq %fs:40, %rax movq %rax, 168(%rsp) xorl %eax, %eax leaq 44(%rsp), %rax movq %rax, 112(%rsp) leaq 40(%rsp), %rax movq %rax, 120(%rsp) leaq 36(%rsp), %rax movq %rax, 128(%rsp) leaq 24(%rsp), %rax movq %rax, 136(%rsp) leaq 16(%rsp), %rax movq %rax, 144(%rsp) leaq 8(%rsp), %rax movq %rax, 152(%rsp) movq %rsp, %rax movq %rax, 160(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) movl $1, 72(%rsp) movl $1, 76(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) leaq 56(%rsp), %rcx leaq 48(%rsp), %rdx leaq 76(%rsp), %rsi leaq 64(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 168(%rsp), %rax subq %fs:40, %rax jne .L8 addq $184, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 56(%rsp) .cfi_def_cfa_offset 200 pushq 56(%rsp) .cfi_def_cfa_offset 208 leaq 128(%rsp), %r9 movq 92(%rsp), %rcx movl 100(%rsp), %r8d movq 80(%rsp), %rsi movl 88(%rsp), %edx leaq _Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 192 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z62__device_stub__Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_PfiffPKfS0_S0_Pf, .-_Z62__device_stub__Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_PfiffPKfS0_S0_Pf .globl _Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf .type _Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf, @function _Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z62__device_stub__Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_PfiffPKfS0_S0_Pf addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf, .-_Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC0: .string "_Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "AssembleArrayOfNoticedChannels.hip" .globl _Z45__device_stub__AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf # -- Begin function _Z45__device_stub__AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf .p2align 4, 0x90 .type _Z45__device_stub__AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf,@function _Z45__device_stub__AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf: # @_Z45__device_stub__AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf .cfi_startproc # %bb.0: subq $152, %rsp .cfi_def_cfa_offset 160 movl %edi, 12(%rsp) movss %xmm0, 8(%rsp) movss %xmm1, 4(%rsp) movq %rsi, 88(%rsp) movq %rdx, 80(%rsp) movq %rcx, 72(%rsp) movq %r8, 64(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 8(%rsp), %rax movq %rax, 104(%rsp) leaq 4(%rsp), %rax movq %rax, 112(%rsp) leaq 88(%rsp), %rax movq %rax, 120(%rsp) leaq 80(%rsp), %rax movq %rax, 128(%rsp) leaq 72(%rsp), %rax movq %rax, 136(%rsp) leaq 64(%rsp), %rax movq %rax, 144(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $168, %rsp .cfi_adjust_cfa_offset -168 retq .Lfunc_end0: .size _Z45__device_stub__AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf, .Lfunc_end0-_Z45__device_stub__AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf,@object # @_Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf .section .rodata,"a",@progbits .globl _Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf .p2align 3, 0x0 _Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf: .quad _Z45__device_stub__AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf .size _Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf" .size .L__unnamed_1, 49 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z45__device_stub__AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z30AssembleArrayOfNoticedChannelsiffPKfS0_S0_Pf .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include <stdio.h> #include <stdlib.h> #include <iostream> #include <math.h> #include <sys/time.h> using namespace std; //************************************************************************** double cpuSecond() { struct timeval tp; gettimeofday(&tp, NULL); return((double)tp.tv_sec + (double)tp.tv_usec*1e-6); } //************************************************************************** __global__ void transformacion_kernel_global(float * A, float * B, float * C, float * D, float * mx) { int tid = threadIdx.x; int Bsize = blockDim.x; int i= tid + Bsize * blockIdx.x; float c = 0.0; // valor a calcular extern __shared__ float sdata[]; // memoria compartida float *sdata_A = sdata; // Puntero al primer valor de A float *sdata_B = sdata+Bsize; // Puntero al primer valor de B float *sdata_C = sdata+Bsize*2; // Puntero al primer valor de C float *sdata_C2 = sdata+Bsize*3; // Puntero al primer valor de una copia de C // Paso a memoria compartida de A y B *(sdata_A+tid) = A[i]; *(sdata_B+tid) = B[i]; __syncthreads(); /***** Fase del calculo de C (memoria global) *****/ int jinicio = blockIdx.x * Bsize; int jfin = jinicio + Bsize; for (int j = jinicio; j < jfin; j++){ float a = A[j] * i; int signo = int(ceil(a))%2 == 0 ? 1 : -1; c += a + B[j] * signo; } C[i] = c; *(sdata_C+tid) = c; *(sdata_C2+tid) = c; __syncthreads(); /***** Fase del calculo de D (reduccion suma) y mx (reduccion >) *****/ float n, m; for (int s=blockDim.x/2; s>0; s>>=1){ if (tid < s){ *(sdata_C+tid) += *(sdata_C+tid+s); n = *(sdata_C2+tid); m = *(sdata_C2+tid+s); *(sdata_C2+tid) = (n > m) ? n : m; } __syncthreads(); } if (tid == 0){ D[blockIdx.x] = *(sdata_C); mx[blockIdx.x] = *(sdata_C2); } } //************************************************************************** __global__ void transformacion_kernel_shared(float * A, float * B, float * C, float * D, float * mx) { int tid = threadIdx.x; int Bsize = blockDim.x; int i= tid + Bsize * blockIdx.x; float c = 0.0; // valor a calcular extern __shared__ float sdata[]; // memoria compartida float *sdata_A = sdata; // Puntero al primer valor de A float *sdata_B = sdata+Bsize; // Puntero al primer valor de B float *sdata_C = sdata+Bsize*2; // Puntero al primer valor de C float *sdata_C2 = sdata+Bsize*3; // Puntero al primer valor de una copia de C // Paso a memoria compartida de A y B *(sdata_A+tid) = A[i]; *(sdata_B+tid) = B[i]; __syncthreads(); /***** Fase del calculo de C (memoria compartida) *****/ for (int j = 0; j < Bsize; j++){ float a = *(sdata_A+j) * i; int signo = int(ceil(a))%2 == 0 ? 1 : -1; c += a + *(sdata_B+j) * signo; } C[i] = c; *(sdata_C+tid) = c; *(sdata_C2+tid) = c; __syncthreads(); /***** Fase del calculo de D (reduccion suma) y mx (reduccion >) *****/ float n, m; for (int s=blockDim.x/2; s>0; s>>=1){ if (tid < s){ *(sdata_C+tid) += *(sdata_C+tid+s); n = *(sdata_C2+tid); m = *(sdata_C2+tid+s); *(sdata_C2+tid) = (n > m) ? n : m; } __syncthreads(); } if (tid == 0){ D[blockIdx.x] = *(sdata_C); mx[blockIdx.x] = *(sdata_C2); } } //************************************************************************** int main(int argc, char *argv[]) //************************************************************************** { //Get GPU information int devID; cudaDeviceProp props; cudaError_t err; err = cudaGetDevice(&devID); if(err != cudaSuccess) cout << "CUDA GET DEVICE ERROR" << endl; cudaGetDeviceProperties(&props, devID); printf("Device %d: \"%s\" with Compute %d.%d capability\n\n", devID, props.name, props.major, props.minor); int Bsize, NBlocks; if (argc != 3){ cout << "Uso: transformacion Num_bloques Tam_bloque "<<endl; return(0); }else{ NBlocks = atoi(argv[1]); Bsize= atoi(argv[2]); } const int N=Bsize*NBlocks; // Pointers to memory float *h_A, *h_B, *h_C, *h_D, *h_D_global, *h_mx_global, h_mx, *h_D_shared, *h_mx_shared; //host float *d_A, *d_B, *d_C, *d_D_global, *d_mx_global, *d_D_shared, *d_mx_shared; // device // Allocate arrays a, b, c and d on host h_A = new float[N]; h_B = new float[N]; h_C = new float[N]; h_D = new float[NBlocks]; // resultados del kernel de memoria global h_D_global = new float[NBlocks]; h_mx_global= new float[NBlocks]; // resultados del kernel de memoria compartida h_D_shared = new float[NBlocks]; h_mx_shared = new float[NBlocks]; // Allocate device memory int sizeABC = N*sizeof(float); int sizeD = NBlocks*sizeof(float); d_A = NULL; err = cudaMalloc((void **) &d_A, sizeABC); if (err != cudaSuccess) cout << "ERROR RESERVA A" << endl; d_B = NULL; err = cudaMalloc((void **) &d_B, sizeABC); if (err != cudaSuccess) cout << "ERROR RESERVA B" << endl; d_C = NULL; err = cudaMalloc((void **) &d_C, sizeABC); if (err != cudaSuccess) cout << "ERROR RESERVA C" << endl; d_D_global = NULL; err = cudaMalloc((void **) &d_D_global, sizeD); if (err != cudaSuccess) cout << "ERROR RESERVA D (GLOBAL)" << endl; d_mx_global = NULL; // array with the maximum of each block of C (device) err = cudaMalloc((void **) &d_mx_global, sizeD); if (err != cudaSuccess) cout << "ERROR RESERVA MX (GLOBAL)" << endl; d_D_shared = NULL; err = cudaMalloc((void **) &d_D_shared, sizeD); if (err != cudaSuccess) cout << "ERROR RESERVA D (SHARED)" << endl; d_mx_shared = NULL; err = cudaMalloc((void **) &d_mx_shared, sizeD); if (err != cudaSuccess) cout << "ERROR RESERVA MX (SHARED)" << endl; //* Initialize arrays */ for (int i=0; i<N; i++){ h_A[i]= (float) (1 -(i%100)*0.001); h_B[i]= (float) (0.5+(i%10) *0.1 ); } cudaDeviceSetCacheConfig(cudaFuncCachePreferShared); /*********************** GPU Phase (global memory) ************************/ double t1 = cpuSecond(); // copy A and B to device err = cudaMemcpy(d_A, h_A, sizeABC, cudaMemcpyHostToDevice); if (err != cudaSuccess) cout << "ERROR COPIA A" << endl; err = cudaMemcpy(d_B, h_B, sizeABC, cudaMemcpyHostToDevice); if (err != cudaSuccess) cout << "ERROR COPIA B" << endl; dim3 threadsPerBlock(Bsize, 1); dim3 numBlocks(NBlocks, 1); int smemSize = Bsize*4*sizeof(float); transformacion_kernel_global<<<numBlocks, threadsPerBlock, smemSize>>>( d_A, d_B, d_C, d_D_global, d_mx_global); cudaMemcpy(h_D_global, d_D_global, NBlocks*sizeof(float), cudaMemcpyDeviceToHost); cudaMemcpy(h_mx_global, d_mx_global, NBlocks*sizeof(float), cudaMemcpyDeviceToHost); float mx_global_final = h_mx_global[0]; cudaDeviceSynchronize(); // final reduction on CPU for (int k = 1; k<NBlocks; k++) mx_global_final = (mx_global_final > h_mx_global[k]) ? mx_global_final : h_mx_global[k]; double tgpu_global=cpuSecond()-t1; /********************** GPU Phase (shared memory) **********************/ t1 = cpuSecond(); // copy A and B to device //err = cudaMemcpy(d_A, h_A, sizeABC, cudaMemcpyHostToDevice); //if (err != cudaSuccess) cout << "ERROR COPIA A" << endl; //err = cudaMemcpy(d_B, h_B, sizeABC, cudaMemcpyHostToDevice); //if (err != cudaSuccess) cout << "ERROR COPIA B" << endl; smemSize = Bsize*4*sizeof(float); transformacion_kernel_shared<<<numBlocks, threadsPerBlock, smemSize>>>( d_A, d_B, d_C, d_D_shared, d_mx_shared); cudaMemcpy(h_D_shared, d_D_shared, NBlocks*sizeof(float), cudaMemcpyDeviceToHost); cudaMemcpy(h_mx_shared, d_mx_shared, NBlocks*sizeof(float), cudaMemcpyDeviceToHost); float mx_shared_final = h_mx_shared[0]; cudaDeviceSynchronize(); // final reduction on CPU for (int k = 1; k<NBlocks; k++) mx_shared_final = (mx_shared_final > h_mx_shared[k]) ? mx_shared_final : h_mx_shared[k]; double tgpu_shared=cpuSecond()-t1; /******************************* CPU Phase *****************************/ // Time measurement t1=cpuSecond(); // Compute C[i], d[K] and mx for (int k=0; k<NBlocks;k++) { int istart=k*Bsize; int iend =istart+Bsize; h_D[k]=0.0; for (int i=istart; i<iend;i++){ h_C[i]=0.0; for (int j=istart; j<iend;j++){ float a=h_A[j]*i; if ((int)ceil(a) % 2 ==0) h_C[i]+= a + h_B[j]; else h_C[i]+= a - h_B[j]; } h_D[k]+=h_C[i]; h_mx= (i==1) ? h_C[0] : max(h_C[i],h_mx); } } double tsec=cpuSecond()-t1; /********************** RESULTADOS ***************************/ //for (int i=0; i<N;i++) cout<<"C["<<i<<"]="<<h_C[i]<<endl; /*cout<<"................................."<<endl; for (int k=0; k<NBlocks;k++){ cout<<"D["<<k<<"]="<<h_D[k]<<endl; cout<<"D_global["<<k<<"]="<<h_D_global[k]<<endl; cout<<"D_shared["<<k<<"]="<<h_D_shared[k]<<endl; }*/ cout<<"................................."<<endl<<"El valor máximo en C (sec) es: "<<h_mx<<endl; cout<<"................................."<<endl<<"El valor máximo en C (gpu global) es: "<<mx_global_final<<endl; cout<<"................................."<<endl<<"El valor máximo en C (gpu shared) es: "<<mx_shared_final << endl; cout << endl << "N=" << N << "= " << Bsize << "*" << NBlocks << endl; cout << "Tiempo gastado CPU= " << tsec << endl; cout << "Tiempo gastado GPU (mem global)= " << tgpu_global << endl; cout << "Tiempo gastado GPU (mem compartida)= " << tgpu_shared << endl; cout << endl << "Ganancia mem global = " << tsec/tgpu_global << endl; cout << "Ganancia mem compartida = " << tsec/tgpu_shared << endl; // Free host memory delete [] h_A; delete [] h_B; delete [] h_C; delete [] h_D; delete [] h_D_global; delete [] h_mx_global; delete [] h_D_shared; delete [] h_mx_shared; // Free device memory cudaFree(d_A); cudaFree(d_B); cudaFree(d_C); cudaFree(d_mx_global); cudaFree(d_mx_shared); cudaFree(d_D_global); cudaFree(d_D_shared); }
.file "tmpxft_000a837c_00000000-6_transformacion.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3673: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3673: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z9cpuSecondv .type _Z9cpuSecondv, @function _Z9cpuSecondv: .LFB3669: .cfi_startproc endbr64 subq $40, %rsp .cfi_def_cfa_offset 48 movq %fs:40, %rax movq %rax, 24(%rsp) xorl %eax, %eax movq %rsp, %rdi movl $0, %esi call gettimeofday@PLT pxor %xmm0, %xmm0 cvtsi2sdq 8(%rsp), %xmm0 mulsd .LC0(%rip), %xmm0 pxor %xmm1, %xmm1 cvtsi2sdq (%rsp), %xmm1 addsd %xmm1, %xmm0 movq 24(%rsp), %rax subq %fs:40, %rax jne .L6 addq $40, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L6: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE3669: .size _Z9cpuSecondv, .-_Z9cpuSecondv .globl _Z56__device_stub__Z28transformacion_kernel_globalPfS_S_S_S_PfS_S_S_S_ .type _Z56__device_stub__Z28transformacion_kernel_globalPfS_S_S_S_PfS_S_S_S_, @function _Z56__device_stub__Z28transformacion_kernel_globalPfS_S_S_S_PfS_S_S_S_: .LFB3695: .cfi_startproc endbr64 subq $168, %rsp .cfi_def_cfa_offset 176 movq %rdi, 40(%rsp) movq %rsi, 32(%rsp) movq %rdx, 24(%rsp) movq %rcx, 16(%rsp) movq %r8, 8(%rsp) movq %fs:40, %rax movq %rax, 152(%rsp) xorl %eax, %eax leaq 40(%rsp), %rax movq %rax, 112(%rsp) leaq 32(%rsp), %rax movq %rax, 120(%rsp) leaq 24(%rsp), %rax movq %rax, 128(%rsp) leaq 16(%rsp), %rax movq %rax, 136(%rsp) leaq 8(%rsp), %rax movq %rax, 144(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) movl $1, 72(%rsp) movl $1, 76(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) leaq 56(%rsp), %rcx leaq 48(%rsp), %rdx leaq 76(%rsp), %rsi leaq 64(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L11 .L7: movq 152(%rsp), %rax subq %fs:40, %rax jne .L12 addq $168, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L11: .cfi_restore_state pushq 56(%rsp) .cfi_def_cfa_offset 184 pushq 56(%rsp) .cfi_def_cfa_offset 192 leaq 128(%rsp), %r9 movq 92(%rsp), %rcx movl 100(%rsp), %r8d movq 80(%rsp), %rsi movl 88(%rsp), %edx leaq _Z28transformacion_kernel_globalPfS_S_S_S_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 176 jmp .L7 .L12: call __stack_chk_fail@PLT .cfi_endproc .LFE3695: .size _Z56__device_stub__Z28transformacion_kernel_globalPfS_S_S_S_PfS_S_S_S_, .-_Z56__device_stub__Z28transformacion_kernel_globalPfS_S_S_S_PfS_S_S_S_ .globl _Z28transformacion_kernel_globalPfS_S_S_S_ .type _Z28transformacion_kernel_globalPfS_S_S_S_, @function _Z28transformacion_kernel_globalPfS_S_S_S_: .LFB3696: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z56__device_stub__Z28transformacion_kernel_globalPfS_S_S_S_PfS_S_S_S_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3696: .size _Z28transformacion_kernel_globalPfS_S_S_S_, .-_Z28transformacion_kernel_globalPfS_S_S_S_ .globl _Z56__device_stub__Z28transformacion_kernel_sharedPfS_S_S_S_PfS_S_S_S_ .type _Z56__device_stub__Z28transformacion_kernel_sharedPfS_S_S_S_PfS_S_S_S_, @function _Z56__device_stub__Z28transformacion_kernel_sharedPfS_S_S_S_PfS_S_S_S_: .LFB3697: .cfi_startproc endbr64 subq $168, %rsp .cfi_def_cfa_offset 176 movq %rdi, 40(%rsp) movq %rsi, 32(%rsp) movq %rdx, 24(%rsp) movq %rcx, 16(%rsp) movq %r8, 8(%rsp) movq %fs:40, %rax movq %rax, 152(%rsp) xorl %eax, %eax leaq 40(%rsp), %rax movq %rax, 112(%rsp) leaq 32(%rsp), %rax movq %rax, 120(%rsp) leaq 24(%rsp), %rax movq %rax, 128(%rsp) leaq 16(%rsp), %rax movq %rax, 136(%rsp) leaq 8(%rsp), %rax movq %rax, 144(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) movl $1, 72(%rsp) movl $1, 76(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) leaq 56(%rsp), %rcx leaq 48(%rsp), %rdx leaq 76(%rsp), %rsi leaq 64(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L19 .L15: movq 152(%rsp), %rax subq %fs:40, %rax jne .L20 addq $168, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L19: .cfi_restore_state pushq 56(%rsp) .cfi_def_cfa_offset 184 pushq 56(%rsp) .cfi_def_cfa_offset 192 leaq 128(%rsp), %r9 movq 92(%rsp), %rcx movl 100(%rsp), %r8d movq 80(%rsp), %rsi movl 88(%rsp), %edx leaq _Z28transformacion_kernel_sharedPfS_S_S_S_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 176 jmp .L15 .L20: call __stack_chk_fail@PLT .cfi_endproc .LFE3697: .size _Z56__device_stub__Z28transformacion_kernel_sharedPfS_S_S_S_PfS_S_S_S_, .-_Z56__device_stub__Z28transformacion_kernel_sharedPfS_S_S_S_PfS_S_S_S_ .globl _Z28transformacion_kernel_sharedPfS_S_S_S_ .type _Z28transformacion_kernel_sharedPfS_S_S_S_, @function _Z28transformacion_kernel_sharedPfS_S_S_S_: .LFB3698: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z56__device_stub__Z28transformacion_kernel_sharedPfS_S_S_S_PfS_S_S_S_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3698: .size _Z28transformacion_kernel_sharedPfS_S_S_S_, .-_Z28transformacion_kernel_sharedPfS_S_S_S_ .section .rodata.str1.1,"aMS",@progbits,1 .LC2: .string "CUDA GET DEVICE ERROR" .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC3: .string "Device %d: \"%s\" with Compute %d.%d capability\n\n" .align 8 .LC4: .string "Uso: transformacion Num_bloques Tam_bloque " .section .rodata.str1.1 .LC5: .string "ERROR RESERVA A" .LC6: .string "ERROR RESERVA B" .LC7: .string "ERROR RESERVA C" .LC8: .string "ERROR RESERVA D (GLOBAL)" .LC9: .string "ERROR RESERVA MX (GLOBAL)" .LC10: .string "ERROR RESERVA D (SHARED)" .LC11: .string "ERROR RESERVA MX (SHARED)" .LC16: .string "ERROR COPIA A" .LC17: .string "ERROR COPIA B" .section .rodata.str1.8 .align 8 .LC21: .string "................................." .align 8 .LC22: .string "El valor m\303\241ximo en C (sec) es: " .align 8 .LC23: .string "El valor m\303\241ximo en C (gpu global) es: " .align 8 .LC24: .string "El valor m\303\241ximo en C (gpu shared) es: " .section .rodata.str1.1 .LC25: .string "N=" .LC26: .string "= " .LC27: .string "*" .LC28: .string "Tiempo gastado CPU= " .section .rodata.str1.8 .align 8 .LC29: .string "Tiempo gastado GPU (mem global)= " .align 8 .LC30: .string "Tiempo gastado GPU (mem compartida)= " .section .rodata.str1.1 .LC31: .string "Ganancia mem global = " .LC32: .string "Ganancia mem compartida = " .text .globl main .type main, @function main: .LFB3670: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $1320, %rsp .cfi_def_cfa_offset 1376 movl %edi, %ebx movq %rsi, %rbp movq %fs:40, %rax movq %rax, 1304(%rsp) xorl %eax, %eax leaq 188(%rsp), %rdi call cudaGetDevice@PLT testl %eax, %eax jne .L82 .L24: leaq 272(%rsp), %r12 movl 188(%rsp), %esi movq %r12, %rdi call cudaGetDeviceProperties_v2@PLT movl 636(%rsp), %r9d movl 632(%rsp), %r8d movq %r12, %rcx movl 188(%rsp), %edx leaq .LC3(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT cmpl $3, %ebx je .L25 leaq .LC4(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT .L26: movq 1304(%rsp), %rax subq %fs:40, %rax jne .L83 movl $0, %eax addq $1320, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L82: .cfi_restore_state leaq .LC2(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT jmp .L24 .L25: movq 8(%rbp), %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT movq %rax, %r13 movl %eax, 160(%rsp) movq 16(%rbp), %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT movq %rax, 24(%rsp) movl %eax, 156(%rsp) imull %r13d, %eax movl %eax, 152(%rsp) movslq %eax, %rbx movabsq $2305843009213693950, %rax cmpq %rbx, %rax jb .L27 leaq 0(,%rbx,4), %rbp movq %rbp, %rdi call _Znam@PLT movq %rax, 56(%rsp) movq %rbp, %rdi call _Znam@PLT movq %rax, 64(%rsp) movq %rbp, %rdi call _Znam@PLT movq %rax, %r15 movslq %r13d, %rbp movabsq $2305843009213693950, %rax cmpq %rbp, %rax jb .L84 leaq 0(,%rbp,4), %r12 movq %r12, %rdi call _Znam@PLT movq %rax, 128(%rsp) movq %r12, %rdi call _Znam@PLT movq %rax, 136(%rsp) movq %r12, %rdi call _Znam@PLT movq %rax, 144(%rsp) movq %r12, %rdi call _Znam@PLT movq %rax, 96(%rsp) movq %r12, %rdi call _Znam@PLT movq %rax, %r14 leal 0(,%rbp,4), %eax movl %eax, 8(%rsp) movq $0, 192(%rsp) movl 152(%rsp), %eax sall $2, %eax movslq %eax, %rbp leaq 192(%rsp), %rdi movq %rbp, %rsi call cudaMalloc@PLT testl %eax, %eax jne .L85 .L32: movq $0, 200(%rsp) leaq 200(%rsp), %rdi movq %rbp, %rsi call cudaMalloc@PLT testl %eax, %eax jne .L86 .L34: movq $0, 208(%rsp) leaq 208(%rsp), %rdi movq %rbp, %rsi call cudaMalloc@PLT testl %eax, %eax jne .L87 .L35: movq $0, 216(%rsp) movslq 8(%rsp), %rax movq %rax, 8(%rsp) leaq 216(%rsp), %rdi movq %rax, %rsi call cudaMalloc@PLT testl %eax, %eax jne .L88 .L36: movq $0, 224(%rsp) leaq 224(%rsp), %rdi movq 8(%rsp), %rsi call cudaMalloc@PLT testl %eax, %eax jne .L89 .L37: movq $0, 232(%rsp) leaq 232(%rsp), %rdi movq 8(%rsp), %rsi call cudaMalloc@PLT testl %eax, %eax jne .L90 .L38: movq $0, 240(%rsp) leaq 240(%rsp), %rdi movq 8(%rsp), %rsi call cudaMalloc@PLT testl %eax, %eax jne .L91 .L39: cmpl $0, 152(%rsp) jle .L40 movl $0, %edx movsd .LC12(%rip), %xmm5 movsd .LC13(%rip), %xmm4 movsd .LC14(%rip), %xmm3 movsd .LC15(%rip), %xmm2 movq 56(%rsp), %rdi movq 64(%rsp), %r8 .L41: movslq %edx, %rax imulq $1374389535, %rax, %rcx sarq $37, %rcx movl %edx, %esi sarl $31, %esi subl %esi, %ecx imull $100, %ecx, %ecx movl %edx, %r9d subl %ecx, %r9d pxor %xmm1, %xmm1 cvtsi2sdl %r9d, %xmm1 mulsd %xmm5, %xmm1 movapd %xmm4, %xmm0 subsd %xmm1, %xmm0 cvtsd2ss %xmm0, %xmm0 movss %xmm0, (%rdi,%rdx,4) imulq $1717986919, %rax, %rax sarq $34, %rax subl %esi, %eax leal (%rax,%rax,4), %eax addl %eax, %eax movl %edx, %ecx subl %eax, %ecx pxor %xmm0, %xmm0 cvtsi2sdl %ecx, %xmm0 mulsd %xmm3, %xmm0 addsd %xmm2, %xmm0 cvtsd2ss %xmm0, %xmm0 movss %xmm0, (%r8,%rdx,4) addq $1, %rdx cmpq %rdx, %rbx jne .L41 .L40: movl $1, %edi call cudaDeviceSetCacheConfig@PLT call _Z9cpuSecondv movsd %xmm0, 8(%rsp) movl $1, %ecx movq %rbp, %rdx movq 56(%rsp), %rsi movq 192(%rsp), %rdi call cudaMemcpy@PLT testl %eax, %eax jne .L92 .L42: movl $1, %ecx movq %rbp, %rdx movq 64(%rsp), %rsi movq 200(%rsp), %rdi call cudaMemcpy@PLT testl %eax, %eax jne .L93 .L43: movq 24(%rsp), %rax movl %eax, 248(%rsp) movl $1, 252(%rsp) movl $1, 256(%rsp) movl %r13d, 260(%rsp) movl $1, 264(%rsp) movl $1, 268(%rsp) sall $2, %eax movslq %eax, %rsi movq %rsi, 72(%rsp) sall $2, %eax movslq %eax, %rbx movl $0, %r9d movq %rbx, %r8 movq 248(%rsp), %rdx movl $1, %ecx movq 260(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L94 .L44: movl $2, %ecx movq %r12, %rdx movq 216(%rsp), %rsi movq 136(%rsp), %rdi call cudaMemcpy@PLT movl $2, %ecx movq %r12, %rdx movq 224(%rsp), %rsi movq 144(%rsp), %rbp movq %rbp, %rdi call cudaMemcpy@PLT movss 0(%rbp), %xmm5 movss %xmm5, 32(%rsp) call cudaDeviceSynchronize@PLT cmpl $1, %r13d jle .L45 leaq 4(%rbp), %rax leal -2(%r13), %edx leaq 8(%rbp,%rdx,4), %rdx .L48: movss 32(%rsp), %xmm5 maxss (%rax), %xmm5 movss %xmm5, 32(%rsp) addq $4, %rax cmpq %rdx, %rax jne .L48 call _Z9cpuSecondv subsd 8(%rsp), %xmm0 movsd %xmm0, 112(%rsp) call _Z9cpuSecondv movsd %xmm0, 8(%rsp) movl 256(%rsp), %ecx movl $0, %r9d movq %rbx, %r8 movq 248(%rsp), %rdx movq 260(%rsp), %rdi movl 268(%rsp), %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L66 movl $2, %ecx movq %r12, %rdx movq 232(%rsp), %rsi movq 96(%rsp), %rdi call cudaMemcpy@PLT movl $2, %ecx movq %r12, %rdx movq 240(%rsp), %rsi movq %r14, %rdi call cudaMemcpy@PLT movl (%r14), %ebx call cudaDeviceSynchronize@PLT .L68: leaq 4(%r14), %rax leal -2(%r13), %edx leaq 8(%r14,%rdx,4), %rdx movd %ebx, %xmm0 .L53: maxss (%rax), %xmm0 addq $4, %rax cmpq %rdx, %rax jne .L53 movd %xmm0, %ebx call _Z9cpuSecondv subsd 8(%rsp), %xmm0 movsd %xmm0, 104(%rsp) call _Z9cpuSecondv movsd %xmm0, 120(%rsp) .L67: movq 128(%rsp), %rdi movq %rdi, %rdx movq 24(%rsp), %rsi movl %esi, %r8d movslq %esi, %rax movq %rax, 80(%rsp) movl %esi, %eax movq 56(%rsp), %rcx leaq (%rcx,%rax,4), %rbp movl %r13d, %eax leaq (%rdi,%rax,4), %rax movq %rax, 88(%rsp) movl %esi, %ecx movl $0, %esi movl $0, %edi movl %ebx, 164(%rsp) movss 16(%rsp), %xmm5 movq %r14, 168(%rsp) jmp .L64 .L27: movq 1304(%rsp), %rax subq %fs:40, %rax je .L30 call __stack_chk_fail@PLT .L30: call __cxa_throw_bad_array_new_length@PLT .L84: movq 1304(%rsp), %rax subq %fs:40, %rax je .L33 call __stack_chk_fail@PLT .L33: call __cxa_throw_bad_array_new_length@PLT .L85: leaq .LC5(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT jmp .L32 .L86: leaq .LC6(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT jmp .L34 .L87: leaq .LC7(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT jmp .L35 .L88: leaq .LC8(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT jmp .L36 .L89: leaq .LC9(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT jmp .L37 .L90: leaq .LC10(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT jmp .L38 .L91: leaq .LC11(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT jmp .L39 .L92: leaq .LC16(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT jmp .L42 .L93: leaq .LC17(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT jmp .L43 .L94: movq 224(%rsp), %r8 movq 216(%rsp), %rcx movq 208(%rsp), %rdx movq 200(%rsp), %rsi movq 192(%rsp), %rdi call _Z56__device_stub__Z28transformacion_kernel_globalPfS_S_S_S_PfS_S_S_S_ jmp .L44 .L66: movq 240(%rsp), %r8 movq 232(%rsp), %rcx movq 208(%rsp), %rdx movq 200(%rsp), %rsi movq 192(%rsp), %rdi call _Z56__device_stub__Z28transformacion_kernel_sharedPfS_S_S_S_PfS_S_S_S_ movl $2, %ecx movq %r12, %rdx movq 232(%rsp), %rsi movq 96(%rsp), %rdi call cudaMemcpy@PLT movl $2, %ecx movq %r12, %rdx movq 240(%rsp), %rsi movq %r14, %rdi call cudaMemcpy@PLT movl (%r14), %ebx call cudaDeviceSynchronize@PLT cmpl $1, %r13d jg .L68 jmp .L50 .L58: subss (%rdx), %xmm0 addss %xmm0, %xmm3 .L59: addq $4, %rax addq $4, %rdx cmpq %rbp, %rax je .L95 .L60: movaps %xmm4, %xmm0 mulss (%rax), %xmm0 movaps %xmm0, %xmm2 movss .LC33(%rip), %xmm1 andps %xmm0, %xmm1 movss .LC18(%rip), %xmm6 ucomiss %xmm1, %xmm6 jbe .L57 cvttss2sil %xmm0, %ecx pxor %xmm1, %xmm1 cvtsi2ssl %ecx, %xmm1 cmpnless %xmm1, %xmm2 movss .LC20(%rip), %xmm7 andps %xmm7, %xmm2 addss %xmm2, %xmm1 movss .LC33(%rip), %xmm2 andnps %xmm0, %xmm2 orps %xmm1, %xmm2 .L57: cvttss2sil %xmm2, %ecx testb $1, %cl jne .L58 addss (%rdx), %xmm0 addss %xmm0, %xmm3 jmp .L59 .L95: movss %xmm3, (%r15,%rbx,4) movss 8(%rsp), %xmm7 addss %xmm3, %xmm7 movss %xmm7, 8(%rsp) cmpl $1, %ebx je .L96 movaps %xmm5, %xmm1 movaps %xmm3, %xmm0 call fmaxf@PLT movaps %xmm0, %xmm5 .L62: addq $1, %rbx cmpl %ebx, %r13d jle .L97 .L63: movq %r12, %rdx movq %r14, %rax pxor %xmm3, %xmm3 pxor %xmm4, %xmm4 cvtsi2ssl %ebx, %xmm4 jmp .L60 .L96: movss (%r15), %xmm5 jmp .L62 .L97: movq 24(%rsp), %rdx movl 36(%rsp), %edi movl 40(%rsp), %r8d movl 44(%rsp), %ecx movq 48(%rsp), %rsi movq 16(%rsp), %rax movss 8(%rsp), %xmm7 movss %xmm7, (%rax) .L56: addq $4, %rdx addl %r8d, %edi addl %r8d, %ecx movq 72(%rsp), %rax addq %rax, %rbp movq 80(%rsp), %rax addq %rax, %rsi movq 88(%rsp), %rax cmpq %rax, %rdx je .L98 .L64: movq %rdx, 16(%rsp) movl $0x00000000, (%rdx) movl %ecx, %r13d cmpl %ecx, %edi jge .L56 leaq 0(,%rsi,4), %rax movq 56(%rsp), %rbx leaq (%rbx,%rax), %r14 movq 64(%rsp), %rbx leaq (%rbx,%rax), %r12 movq %rsi, %rbx movl $0x00000000, 8(%rsp) movq %rdx, 24(%rsp) movl %edi, 36(%rsp) movl %r8d, 40(%rsp) movl %ecx, 44(%rsp) movq %rsi, 48(%rsp) jmp .L63 .L98: movl 164(%rsp), %ebx movss %xmm5, 16(%rsp) movq 168(%rsp), %r14 .L55: call _Z9cpuSecondv subsd 120(%rsp), %xmm0 movq %xmm0, %r13 leaq .LC21(%rip), %r12 movq %r12, %rsi leaq _ZSt4cout(%rip), %rbp movq %rbp, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movq %rax, %rdi leaq .LC22(%rip), %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi pxor %xmm0, %xmm0 cvtss2sd 16(%rsp), %xmm0 call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movq %r12, %rsi movq %rbp, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movq %rax, %rdi leaq .LC23(%rip), %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi pxor %xmm0, %xmm0 cvtss2sd 32(%rsp), %xmm0 call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movq %r12, %rsi movq %rbp, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movq %rax, %rdi leaq .LC24(%rip), %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi movd %ebx, %xmm5 pxor %xmm0, %xmm0 cvtss2sd %xmm5, %xmm0 call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movq %rbp, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movq %rax, %rdi leaq .LC25(%rip), %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi movl 152(%rsp), %esi call _ZNSolsEi@PLT movq %rax, %rdi leaq .LC26(%rip), %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi movl 156(%rsp), %esi call _ZNSolsEi@PLT movq %rax, %rdi leaq .LC27(%rip), %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi movl 160(%rsp), %esi call _ZNSolsEi@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT leaq .LC28(%rip), %rsi movq %rbp, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi movq %r13, %xmm0 call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT leaq .LC29(%rip), %rsi movq %rbp, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi movsd 112(%rsp), %xmm0 call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT leaq .LC30(%rip), %rsi movq %rbp, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi movsd 104(%rsp), %xmm0 call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movq %rbp, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movq %rax, %rdi leaq .LC31(%rip), %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi movq %r13, %xmm5 divsd 112(%rsp), %xmm5 movapd %xmm5, %xmm0 call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT leaq .LC32(%rip), %rsi movq %rbp, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi movq %r13, %xmm5 divsd 104(%rsp), %xmm5 movapd %xmm5, %xmm0 call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movq 56(%rsp), %rdi call _ZdaPv@PLT movq 64(%rsp), %rdi call _ZdaPv@PLT movq %r15, %rdi call _ZdaPv@PLT movq 128(%rsp), %rdi call _ZdaPv@PLT movq 136(%rsp), %rdi call _ZdaPv@PLT movq 144(%rsp), %rdi call _ZdaPv@PLT movq 96(%rsp), %rdi call _ZdaPv@PLT movq %r14, %rdi call _ZdaPv@PLT movq 192(%rsp), %rdi call cudaFree@PLT movq 200(%rsp), %rdi call cudaFree@PLT movq 208(%rsp), %rdi call cudaFree@PLT movq 224(%rsp), %rdi call cudaFree@PLT movq 240(%rsp), %rdi call cudaFree@PLT movq 216(%rsp), %rdi call cudaFree@PLT movq 232(%rsp), %rdi call cudaFree@PLT jmp .L26 .L45: call _Z9cpuSecondv subsd 8(%rsp), %xmm0 movsd %xmm0, 112(%rsp) call _Z9cpuSecondv movsd %xmm0, 8(%rsp) movl 256(%rsp), %ecx movl $0, %r9d movq %rbx, %r8 movq 248(%rsp), %rdx movq 260(%rsp), %rdi movl 268(%rsp), %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L66 movl $2, %ecx movq %r12, %rdx movq 232(%rsp), %rsi movq 96(%rsp), %rdi call cudaMemcpy@PLT movl $2, %ecx movq %r12, %rdx movq 240(%rsp), %rsi movq %r14, %rdi call cudaMemcpy@PLT movl (%r14), %ebx call cudaDeviceSynchronize@PLT .L50: call _Z9cpuSecondv subsd 8(%rsp), %xmm0 movsd %xmm0, 104(%rsp) call _Z9cpuSecondv movsd %xmm0, 120(%rsp) testl %r13d, %r13d jle .L55 jmp .L67 .L83: call __stack_chk_fail@PLT .cfi_endproc .LFE3670: .size main, .-main .section .rodata.str1.8 .align 8 .LC34: .string "_Z28transformacion_kernel_sharedPfS_S_S_S_" .align 8 .LC35: .string "_Z28transformacion_kernel_globalPfS_S_S_S_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3700: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC34(%rip), %rdx movq %rdx, %rcx leaq _Z28transformacion_kernel_sharedPfS_S_S_S_(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC35(%rip), %rdx movq %rdx, %rcx leaq _Z28transformacion_kernel_globalPfS_S_S_S_(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3700: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst8,"aM",@progbits,8 .align 8 .LC0: .long -1598689907 .long 1051772663 .align 8 .LC12: .long -755914244 .long 1062232653 .align 8 .LC13: .long 0 .long 1072693248 .align 8 .LC14: .long -1717986918 .long 1069128089 .align 8 .LC15: .long 0 .long 1071644672 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC18: .long 1258291200 .align 4 .LC20: .long 1065353216 .align 4 .LC33: .long 2147483647 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include <stdio.h> #include <stdlib.h> #include <iostream> #include <math.h> #include <sys/time.h> using namespace std; //************************************************************************** double cpuSecond() { struct timeval tp; gettimeofday(&tp, NULL); return((double)tp.tv_sec + (double)tp.tv_usec*1e-6); } //************************************************************************** __global__ void transformacion_kernel_global(float * A, float * B, float * C, float * D, float * mx) { int tid = threadIdx.x; int Bsize = blockDim.x; int i= tid + Bsize * blockIdx.x; float c = 0.0; // valor a calcular extern __shared__ float sdata[]; // memoria compartida float *sdata_A = sdata; // Puntero al primer valor de A float *sdata_B = sdata+Bsize; // Puntero al primer valor de B float *sdata_C = sdata+Bsize*2; // Puntero al primer valor de C float *sdata_C2 = sdata+Bsize*3; // Puntero al primer valor de una copia de C // Paso a memoria compartida de A y B *(sdata_A+tid) = A[i]; *(sdata_B+tid) = B[i]; __syncthreads(); /***** Fase del calculo de C (memoria global) *****/ int jinicio = blockIdx.x * Bsize; int jfin = jinicio + Bsize; for (int j = jinicio; j < jfin; j++){ float a = A[j] * i; int signo = int(ceil(a))%2 == 0 ? 1 : -1; c += a + B[j] * signo; } C[i] = c; *(sdata_C+tid) = c; *(sdata_C2+tid) = c; __syncthreads(); /***** Fase del calculo de D (reduccion suma) y mx (reduccion >) *****/ float n, m; for (int s=blockDim.x/2; s>0; s>>=1){ if (tid < s){ *(sdata_C+tid) += *(sdata_C+tid+s); n = *(sdata_C2+tid); m = *(sdata_C2+tid+s); *(sdata_C2+tid) = (n > m) ? n : m; } __syncthreads(); } if (tid == 0){ D[blockIdx.x] = *(sdata_C); mx[blockIdx.x] = *(sdata_C2); } } //************************************************************************** __global__ void transformacion_kernel_shared(float * A, float * B, float * C, float * D, float * mx) { int tid = threadIdx.x; int Bsize = blockDim.x; int i= tid + Bsize * blockIdx.x; float c = 0.0; // valor a calcular extern __shared__ float sdata[]; // memoria compartida float *sdata_A = sdata; // Puntero al primer valor de A float *sdata_B = sdata+Bsize; // Puntero al primer valor de B float *sdata_C = sdata+Bsize*2; // Puntero al primer valor de C float *sdata_C2 = sdata+Bsize*3; // Puntero al primer valor de una copia de C // Paso a memoria compartida de A y B *(sdata_A+tid) = A[i]; *(sdata_B+tid) = B[i]; __syncthreads(); /***** Fase del calculo de C (memoria compartida) *****/ for (int j = 0; j < Bsize; j++){ float a = *(sdata_A+j) * i; int signo = int(ceil(a))%2 == 0 ? 1 : -1; c += a + *(sdata_B+j) * signo; } C[i] = c; *(sdata_C+tid) = c; *(sdata_C2+tid) = c; __syncthreads(); /***** Fase del calculo de D (reduccion suma) y mx (reduccion >) *****/ float n, m; for (int s=blockDim.x/2; s>0; s>>=1){ if (tid < s){ *(sdata_C+tid) += *(sdata_C+tid+s); n = *(sdata_C2+tid); m = *(sdata_C2+tid+s); *(sdata_C2+tid) = (n > m) ? n : m; } __syncthreads(); } if (tid == 0){ D[blockIdx.x] = *(sdata_C); mx[blockIdx.x] = *(sdata_C2); } } //************************************************************************** int main(int argc, char *argv[]) //************************************************************************** { //Get GPU information int devID; cudaDeviceProp props; cudaError_t err; err = cudaGetDevice(&devID); if(err != cudaSuccess) cout << "CUDA GET DEVICE ERROR" << endl; cudaGetDeviceProperties(&props, devID); printf("Device %d: \"%s\" with Compute %d.%d capability\n\n", devID, props.name, props.major, props.minor); int Bsize, NBlocks; if (argc != 3){ cout << "Uso: transformacion Num_bloques Tam_bloque "<<endl; return(0); }else{ NBlocks = atoi(argv[1]); Bsize= atoi(argv[2]); } const int N=Bsize*NBlocks; // Pointers to memory float *h_A, *h_B, *h_C, *h_D, *h_D_global, *h_mx_global, h_mx, *h_D_shared, *h_mx_shared; //host float *d_A, *d_B, *d_C, *d_D_global, *d_mx_global, *d_D_shared, *d_mx_shared; // device // Allocate arrays a, b, c and d on host h_A = new float[N]; h_B = new float[N]; h_C = new float[N]; h_D = new float[NBlocks]; // resultados del kernel de memoria global h_D_global = new float[NBlocks]; h_mx_global= new float[NBlocks]; // resultados del kernel de memoria compartida h_D_shared = new float[NBlocks]; h_mx_shared = new float[NBlocks]; // Allocate device memory int sizeABC = N*sizeof(float); int sizeD = NBlocks*sizeof(float); d_A = NULL; err = cudaMalloc((void **) &d_A, sizeABC); if (err != cudaSuccess) cout << "ERROR RESERVA A" << endl; d_B = NULL; err = cudaMalloc((void **) &d_B, sizeABC); if (err != cudaSuccess) cout << "ERROR RESERVA B" << endl; d_C = NULL; err = cudaMalloc((void **) &d_C, sizeABC); if (err != cudaSuccess) cout << "ERROR RESERVA C" << endl; d_D_global = NULL; err = cudaMalloc((void **) &d_D_global, sizeD); if (err != cudaSuccess) cout << "ERROR RESERVA D (GLOBAL)" << endl; d_mx_global = NULL; // array with the maximum of each block of C (device) err = cudaMalloc((void **) &d_mx_global, sizeD); if (err != cudaSuccess) cout << "ERROR RESERVA MX (GLOBAL)" << endl; d_D_shared = NULL; err = cudaMalloc((void **) &d_D_shared, sizeD); if (err != cudaSuccess) cout << "ERROR RESERVA D (SHARED)" << endl; d_mx_shared = NULL; err = cudaMalloc((void **) &d_mx_shared, sizeD); if (err != cudaSuccess) cout << "ERROR RESERVA MX (SHARED)" << endl; //* Initialize arrays */ for (int i=0; i<N; i++){ h_A[i]= (float) (1 -(i%100)*0.001); h_B[i]= (float) (0.5+(i%10) *0.1 ); } cudaDeviceSetCacheConfig(cudaFuncCachePreferShared); /*********************** GPU Phase (global memory) ************************/ double t1 = cpuSecond(); // copy A and B to device err = cudaMemcpy(d_A, h_A, sizeABC, cudaMemcpyHostToDevice); if (err != cudaSuccess) cout << "ERROR COPIA A" << endl; err = cudaMemcpy(d_B, h_B, sizeABC, cudaMemcpyHostToDevice); if (err != cudaSuccess) cout << "ERROR COPIA B" << endl; dim3 threadsPerBlock(Bsize, 1); dim3 numBlocks(NBlocks, 1); int smemSize = Bsize*4*sizeof(float); transformacion_kernel_global<<<numBlocks, threadsPerBlock, smemSize>>>( d_A, d_B, d_C, d_D_global, d_mx_global); cudaMemcpy(h_D_global, d_D_global, NBlocks*sizeof(float), cudaMemcpyDeviceToHost); cudaMemcpy(h_mx_global, d_mx_global, NBlocks*sizeof(float), cudaMemcpyDeviceToHost); float mx_global_final = h_mx_global[0]; cudaDeviceSynchronize(); // final reduction on CPU for (int k = 1; k<NBlocks; k++) mx_global_final = (mx_global_final > h_mx_global[k]) ? mx_global_final : h_mx_global[k]; double tgpu_global=cpuSecond()-t1; /********************** GPU Phase (shared memory) **********************/ t1 = cpuSecond(); // copy A and B to device //err = cudaMemcpy(d_A, h_A, sizeABC, cudaMemcpyHostToDevice); //if (err != cudaSuccess) cout << "ERROR COPIA A" << endl; //err = cudaMemcpy(d_B, h_B, sizeABC, cudaMemcpyHostToDevice); //if (err != cudaSuccess) cout << "ERROR COPIA B" << endl; smemSize = Bsize*4*sizeof(float); transformacion_kernel_shared<<<numBlocks, threadsPerBlock, smemSize>>>( d_A, d_B, d_C, d_D_shared, d_mx_shared); cudaMemcpy(h_D_shared, d_D_shared, NBlocks*sizeof(float), cudaMemcpyDeviceToHost); cudaMemcpy(h_mx_shared, d_mx_shared, NBlocks*sizeof(float), cudaMemcpyDeviceToHost); float mx_shared_final = h_mx_shared[0]; cudaDeviceSynchronize(); // final reduction on CPU for (int k = 1; k<NBlocks; k++) mx_shared_final = (mx_shared_final > h_mx_shared[k]) ? mx_shared_final : h_mx_shared[k]; double tgpu_shared=cpuSecond()-t1; /******************************* CPU Phase *****************************/ // Time measurement t1=cpuSecond(); // Compute C[i], d[K] and mx for (int k=0; k<NBlocks;k++) { int istart=k*Bsize; int iend =istart+Bsize; h_D[k]=0.0; for (int i=istart; i<iend;i++){ h_C[i]=0.0; for (int j=istart; j<iend;j++){ float a=h_A[j]*i; if ((int)ceil(a) % 2 ==0) h_C[i]+= a + h_B[j]; else h_C[i]+= a - h_B[j]; } h_D[k]+=h_C[i]; h_mx= (i==1) ? h_C[0] : max(h_C[i],h_mx); } } double tsec=cpuSecond()-t1; /********************** RESULTADOS ***************************/ //for (int i=0; i<N;i++) cout<<"C["<<i<<"]="<<h_C[i]<<endl; /*cout<<"................................."<<endl; for (int k=0; k<NBlocks;k++){ cout<<"D["<<k<<"]="<<h_D[k]<<endl; cout<<"D_global["<<k<<"]="<<h_D_global[k]<<endl; cout<<"D_shared["<<k<<"]="<<h_D_shared[k]<<endl; }*/ cout<<"................................."<<endl<<"El valor máximo en C (sec) es: "<<h_mx<<endl; cout<<"................................."<<endl<<"El valor máximo en C (gpu global) es: "<<mx_global_final<<endl; cout<<"................................."<<endl<<"El valor máximo en C (gpu shared) es: "<<mx_shared_final << endl; cout << endl << "N=" << N << "= " << Bsize << "*" << NBlocks << endl; cout << "Tiempo gastado CPU= " << tsec << endl; cout << "Tiempo gastado GPU (mem global)= " << tgpu_global << endl; cout << "Tiempo gastado GPU (mem compartida)= " << tgpu_shared << endl; cout << endl << "Ganancia mem global = " << tsec/tgpu_global << endl; cout << "Ganancia mem compartida = " << tsec/tgpu_shared << endl; // Free host memory delete [] h_A; delete [] h_B; delete [] h_C; delete [] h_D; delete [] h_D_global; delete [] h_mx_global; delete [] h_D_shared; delete [] h_mx_shared; // Free device memory cudaFree(d_A); cudaFree(d_B); cudaFree(d_C); cudaFree(d_mx_global); cudaFree(d_mx_shared); cudaFree(d_D_global); cudaFree(d_D_shared); }
#include <hip/hip_runtime.h> #include <stdio.h> #include <stdlib.h> #include <iostream> #include <math.h> #include <sys/time.h> using namespace std; //************************************************************************** double cpuSecond() { struct timeval tp; gettimeofday(&tp, NULL); return((double)tp.tv_sec + (double)tp.tv_usec*1e-6); } //************************************************************************** __global__ void transformacion_kernel_global(float * A, float * B, float * C, float * D, float * mx) { int tid = threadIdx.x; int Bsize = blockDim.x; int i= tid + Bsize * blockIdx.x; float c = 0.0; // valor a calcular extern __shared__ float sdata[]; // memoria compartida float *sdata_A = sdata; // Puntero al primer valor de A float *sdata_B = sdata+Bsize; // Puntero al primer valor de B float *sdata_C = sdata+Bsize*2; // Puntero al primer valor de C float *sdata_C2 = sdata+Bsize*3; // Puntero al primer valor de una copia de C // Paso a memoria compartida de A y B *(sdata_A+tid) = A[i]; *(sdata_B+tid) = B[i]; __syncthreads(); /***** Fase del calculo de C (memoria global) *****/ int jinicio = blockIdx.x * Bsize; int jfin = jinicio + Bsize; for (int j = jinicio; j < jfin; j++){ float a = A[j] * i; int signo = int(ceil(a))%2 == 0 ? 1 : -1; c += a + B[j] * signo; } C[i] = c; *(sdata_C+tid) = c; *(sdata_C2+tid) = c; __syncthreads(); /***** Fase del calculo de D (reduccion suma) y mx (reduccion >) *****/ float n, m; for (int s=blockDim.x/2; s>0; s>>=1){ if (tid < s){ *(sdata_C+tid) += *(sdata_C+tid+s); n = *(sdata_C2+tid); m = *(sdata_C2+tid+s); *(sdata_C2+tid) = (n > m) ? n : m; } __syncthreads(); } if (tid == 0){ D[blockIdx.x] = *(sdata_C); mx[blockIdx.x] = *(sdata_C2); } } //************************************************************************** __global__ void transformacion_kernel_shared(float * A, float * B, float * C, float * D, float * mx) { int tid = threadIdx.x; int Bsize = blockDim.x; int i= tid + Bsize * blockIdx.x; float c = 0.0; // valor a calcular extern __shared__ float sdata[]; // memoria compartida float *sdata_A = sdata; // Puntero al primer valor de A float *sdata_B = sdata+Bsize; // Puntero al primer valor de B float *sdata_C = sdata+Bsize*2; // Puntero al primer valor de C float *sdata_C2 = sdata+Bsize*3; // Puntero al primer valor de una copia de C // Paso a memoria compartida de A y B *(sdata_A+tid) = A[i]; *(sdata_B+tid) = B[i]; __syncthreads(); /***** Fase del calculo de C (memoria compartida) *****/ for (int j = 0; j < Bsize; j++){ float a = *(sdata_A+j) * i; int signo = int(ceil(a))%2 == 0 ? 1 : -1; c += a + *(sdata_B+j) * signo; } C[i] = c; *(sdata_C+tid) = c; *(sdata_C2+tid) = c; __syncthreads(); /***** Fase del calculo de D (reduccion suma) y mx (reduccion >) *****/ float n, m; for (int s=blockDim.x/2; s>0; s>>=1){ if (tid < s){ *(sdata_C+tid) += *(sdata_C+tid+s); n = *(sdata_C2+tid); m = *(sdata_C2+tid+s); *(sdata_C2+tid) = (n > m) ? n : m; } __syncthreads(); } if (tid == 0){ D[blockIdx.x] = *(sdata_C); mx[blockIdx.x] = *(sdata_C2); } } //************************************************************************** int main(int argc, char *argv[]) //************************************************************************** { //Get GPU information int devID; hipDeviceProp_t props; hipError_t err; err = hipGetDevice(&devID); if(err != hipSuccess) cout << "CUDA GET DEVICE ERROR" << endl; hipGetDeviceProperties(&props, devID); printf("Device %d: \"%s\" with Compute %d.%d capability\n\n", devID, props.name, props.major, props.minor); int Bsize, NBlocks; if (argc != 3){ cout << "Uso: transformacion Num_bloques Tam_bloque "<<endl; return(0); }else{ NBlocks = atoi(argv[1]); Bsize= atoi(argv[2]); } const int N=Bsize*NBlocks; // Pointers to memory float *h_A, *h_B, *h_C, *h_D, *h_D_global, *h_mx_global, h_mx, *h_D_shared, *h_mx_shared; //host float *d_A, *d_B, *d_C, *d_D_global, *d_mx_global, *d_D_shared, *d_mx_shared; // device // Allocate arrays a, b, c and d on host h_A = new float[N]; h_B = new float[N]; h_C = new float[N]; h_D = new float[NBlocks]; // resultados del kernel de memoria global h_D_global = new float[NBlocks]; h_mx_global= new float[NBlocks]; // resultados del kernel de memoria compartida h_D_shared = new float[NBlocks]; h_mx_shared = new float[NBlocks]; // Allocate device memory int sizeABC = N*sizeof(float); int sizeD = NBlocks*sizeof(float); d_A = NULL; err = hipMalloc((void **) &d_A, sizeABC); if (err != hipSuccess) cout << "ERROR RESERVA A" << endl; d_B = NULL; err = hipMalloc((void **) &d_B, sizeABC); if (err != hipSuccess) cout << "ERROR RESERVA B" << endl; d_C = NULL; err = hipMalloc((void **) &d_C, sizeABC); if (err != hipSuccess) cout << "ERROR RESERVA C" << endl; d_D_global = NULL; err = hipMalloc((void **) &d_D_global, sizeD); if (err != hipSuccess) cout << "ERROR RESERVA D (GLOBAL)" << endl; d_mx_global = NULL; // array with the maximum of each block of C (device) err = hipMalloc((void **) &d_mx_global, sizeD); if (err != hipSuccess) cout << "ERROR RESERVA MX (GLOBAL)" << endl; d_D_shared = NULL; err = hipMalloc((void **) &d_D_shared, sizeD); if (err != hipSuccess) cout << "ERROR RESERVA D (SHARED)" << endl; d_mx_shared = NULL; err = hipMalloc((void **) &d_mx_shared, sizeD); if (err != hipSuccess) cout << "ERROR RESERVA MX (SHARED)" << endl; //* Initialize arrays */ for (int i=0; i<N; i++){ h_A[i]= (float) (1 -(i%100)*0.001); h_B[i]= (float) (0.5+(i%10) *0.1 ); } hipDeviceSetCacheConfig(hipFuncCachePreferShared); /*********************** GPU Phase (global memory) ************************/ double t1 = cpuSecond(); // copy A and B to device err = hipMemcpy(d_A, h_A, sizeABC, hipMemcpyHostToDevice); if (err != hipSuccess) cout << "ERROR COPIA A" << endl; err = hipMemcpy(d_B, h_B, sizeABC, hipMemcpyHostToDevice); if (err != hipSuccess) cout << "ERROR COPIA B" << endl; dim3 threadsPerBlock(Bsize, 1); dim3 numBlocks(NBlocks, 1); int smemSize = Bsize*4*sizeof(float); transformacion_kernel_global<<<numBlocks, threadsPerBlock, smemSize>>>( d_A, d_B, d_C, d_D_global, d_mx_global); hipMemcpy(h_D_global, d_D_global, NBlocks*sizeof(float), hipMemcpyDeviceToHost); hipMemcpy(h_mx_global, d_mx_global, NBlocks*sizeof(float), hipMemcpyDeviceToHost); float mx_global_final = h_mx_global[0]; hipDeviceSynchronize(); // final reduction on CPU for (int k = 1; k<NBlocks; k++) mx_global_final = (mx_global_final > h_mx_global[k]) ? mx_global_final : h_mx_global[k]; double tgpu_global=cpuSecond()-t1; /********************** GPU Phase (shared memory) **********************/ t1 = cpuSecond(); // copy A and B to device //err = cudaMemcpy(d_A, h_A, sizeABC, cudaMemcpyHostToDevice); //if (err != cudaSuccess) cout << "ERROR COPIA A" << endl; //err = cudaMemcpy(d_B, h_B, sizeABC, cudaMemcpyHostToDevice); //if (err != cudaSuccess) cout << "ERROR COPIA B" << endl; smemSize = Bsize*4*sizeof(float); transformacion_kernel_shared<<<numBlocks, threadsPerBlock, smemSize>>>( d_A, d_B, d_C, d_D_shared, d_mx_shared); hipMemcpy(h_D_shared, d_D_shared, NBlocks*sizeof(float), hipMemcpyDeviceToHost); hipMemcpy(h_mx_shared, d_mx_shared, NBlocks*sizeof(float), hipMemcpyDeviceToHost); float mx_shared_final = h_mx_shared[0]; hipDeviceSynchronize(); // final reduction on CPU for (int k = 1; k<NBlocks; k++) mx_shared_final = (mx_shared_final > h_mx_shared[k]) ? mx_shared_final : h_mx_shared[k]; double tgpu_shared=cpuSecond()-t1; /******************************* CPU Phase *****************************/ // Time measurement t1=cpuSecond(); // Compute C[i], d[K] and mx for (int k=0; k<NBlocks;k++) { int istart=k*Bsize; int iend =istart+Bsize; h_D[k]=0.0; for (int i=istart; i<iend;i++){ h_C[i]=0.0; for (int j=istart; j<iend;j++){ float a=h_A[j]*i; if ((int)ceil(a) % 2 ==0) h_C[i]+= a + h_B[j]; else h_C[i]+= a - h_B[j]; } h_D[k]+=h_C[i]; h_mx= (i==1) ? h_C[0] : max(h_C[i],h_mx); } } double tsec=cpuSecond()-t1; /********************** RESULTADOS ***************************/ //for (int i=0; i<N;i++) cout<<"C["<<i<<"]="<<h_C[i]<<endl; /*cout<<"................................."<<endl; for (int k=0; k<NBlocks;k++){ cout<<"D["<<k<<"]="<<h_D[k]<<endl; cout<<"D_global["<<k<<"]="<<h_D_global[k]<<endl; cout<<"D_shared["<<k<<"]="<<h_D_shared[k]<<endl; }*/ cout<<"................................."<<endl<<"El valor máximo en C (sec) es: "<<h_mx<<endl; cout<<"................................."<<endl<<"El valor máximo en C (gpu global) es: "<<mx_global_final<<endl; cout<<"................................."<<endl<<"El valor máximo en C (gpu shared) es: "<<mx_shared_final << endl; cout << endl << "N=" << N << "= " << Bsize << "*" << NBlocks << endl; cout << "Tiempo gastado CPU= " << tsec << endl; cout << "Tiempo gastado GPU (mem global)= " << tgpu_global << endl; cout << "Tiempo gastado GPU (mem compartida)= " << tgpu_shared << endl; cout << endl << "Ganancia mem global = " << tsec/tgpu_global << endl; cout << "Ganancia mem compartida = " << tsec/tgpu_shared << endl; // Free host memory delete [] h_A; delete [] h_B; delete [] h_C; delete [] h_D; delete [] h_D_global; delete [] h_mx_global; delete [] h_D_shared; delete [] h_mx_shared; // Free device memory hipFree(d_A); hipFree(d_B); hipFree(d_C); hipFree(d_mx_global); hipFree(d_mx_shared); hipFree(d_D_global); hipFree(d_D_shared); }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <hip/hip_runtime.h> #include <stdio.h> #include <stdlib.h> #include <iostream> #include <math.h> #include <sys/time.h> using namespace std; //************************************************************************** double cpuSecond() { struct timeval tp; gettimeofday(&tp, NULL); return((double)tp.tv_sec + (double)tp.tv_usec*1e-6); } //************************************************************************** __global__ void transformacion_kernel_global(float * A, float * B, float * C, float * D, float * mx) { int tid = threadIdx.x; int Bsize = blockDim.x; int i= tid + Bsize * blockIdx.x; float c = 0.0; // valor a calcular extern __shared__ float sdata[]; // memoria compartida float *sdata_A = sdata; // Puntero al primer valor de A float *sdata_B = sdata+Bsize; // Puntero al primer valor de B float *sdata_C = sdata+Bsize*2; // Puntero al primer valor de C float *sdata_C2 = sdata+Bsize*3; // Puntero al primer valor de una copia de C // Paso a memoria compartida de A y B *(sdata_A+tid) = A[i]; *(sdata_B+tid) = B[i]; __syncthreads(); /***** Fase del calculo de C (memoria global) *****/ int jinicio = blockIdx.x * Bsize; int jfin = jinicio + Bsize; for (int j = jinicio; j < jfin; j++){ float a = A[j] * i; int signo = int(ceil(a))%2 == 0 ? 1 : -1; c += a + B[j] * signo; } C[i] = c; *(sdata_C+tid) = c; *(sdata_C2+tid) = c; __syncthreads(); /***** Fase del calculo de D (reduccion suma) y mx (reduccion >) *****/ float n, m; for (int s=blockDim.x/2; s>0; s>>=1){ if (tid < s){ *(sdata_C+tid) += *(sdata_C+tid+s); n = *(sdata_C2+tid); m = *(sdata_C2+tid+s); *(sdata_C2+tid) = (n > m) ? n : m; } __syncthreads(); } if (tid == 0){ D[blockIdx.x] = *(sdata_C); mx[blockIdx.x] = *(sdata_C2); } } //************************************************************************** __global__ void transformacion_kernel_shared(float * A, float * B, float * C, float * D, float * mx) { int tid = threadIdx.x; int Bsize = blockDim.x; int i= tid + Bsize * blockIdx.x; float c = 0.0; // valor a calcular extern __shared__ float sdata[]; // memoria compartida float *sdata_A = sdata; // Puntero al primer valor de A float *sdata_B = sdata+Bsize; // Puntero al primer valor de B float *sdata_C = sdata+Bsize*2; // Puntero al primer valor de C float *sdata_C2 = sdata+Bsize*3; // Puntero al primer valor de una copia de C // Paso a memoria compartida de A y B *(sdata_A+tid) = A[i]; *(sdata_B+tid) = B[i]; __syncthreads(); /***** Fase del calculo de C (memoria compartida) *****/ for (int j = 0; j < Bsize; j++){ float a = *(sdata_A+j) * i; int signo = int(ceil(a))%2 == 0 ? 1 : -1; c += a + *(sdata_B+j) * signo; } C[i] = c; *(sdata_C+tid) = c; *(sdata_C2+tid) = c; __syncthreads(); /***** Fase del calculo de D (reduccion suma) y mx (reduccion >) *****/ float n, m; for (int s=blockDim.x/2; s>0; s>>=1){ if (tid < s){ *(sdata_C+tid) += *(sdata_C+tid+s); n = *(sdata_C2+tid); m = *(sdata_C2+tid+s); *(sdata_C2+tid) = (n > m) ? n : m; } __syncthreads(); } if (tid == 0){ D[blockIdx.x] = *(sdata_C); mx[blockIdx.x] = *(sdata_C2); } } //************************************************************************** int main(int argc, char *argv[]) //************************************************************************** { //Get GPU information int devID; hipDeviceProp_t props; hipError_t err; err = hipGetDevice(&devID); if(err != hipSuccess) cout << "CUDA GET DEVICE ERROR" << endl; hipGetDeviceProperties(&props, devID); printf("Device %d: \"%s\" with Compute %d.%d capability\n\n", devID, props.name, props.major, props.minor); int Bsize, NBlocks; if (argc != 3){ cout << "Uso: transformacion Num_bloques Tam_bloque "<<endl; return(0); }else{ NBlocks = atoi(argv[1]); Bsize= atoi(argv[2]); } const int N=Bsize*NBlocks; // Pointers to memory float *h_A, *h_B, *h_C, *h_D, *h_D_global, *h_mx_global, h_mx, *h_D_shared, *h_mx_shared; //host float *d_A, *d_B, *d_C, *d_D_global, *d_mx_global, *d_D_shared, *d_mx_shared; // device // Allocate arrays a, b, c and d on host h_A = new float[N]; h_B = new float[N]; h_C = new float[N]; h_D = new float[NBlocks]; // resultados del kernel de memoria global h_D_global = new float[NBlocks]; h_mx_global= new float[NBlocks]; // resultados del kernel de memoria compartida h_D_shared = new float[NBlocks]; h_mx_shared = new float[NBlocks]; // Allocate device memory int sizeABC = N*sizeof(float); int sizeD = NBlocks*sizeof(float); d_A = NULL; err = hipMalloc((void **) &d_A, sizeABC); if (err != hipSuccess) cout << "ERROR RESERVA A" << endl; d_B = NULL; err = hipMalloc((void **) &d_B, sizeABC); if (err != hipSuccess) cout << "ERROR RESERVA B" << endl; d_C = NULL; err = hipMalloc((void **) &d_C, sizeABC); if (err != hipSuccess) cout << "ERROR RESERVA C" << endl; d_D_global = NULL; err = hipMalloc((void **) &d_D_global, sizeD); if (err != hipSuccess) cout << "ERROR RESERVA D (GLOBAL)" << endl; d_mx_global = NULL; // array with the maximum of each block of C (device) err = hipMalloc((void **) &d_mx_global, sizeD); if (err != hipSuccess) cout << "ERROR RESERVA MX (GLOBAL)" << endl; d_D_shared = NULL; err = hipMalloc((void **) &d_D_shared, sizeD); if (err != hipSuccess) cout << "ERROR RESERVA D (SHARED)" << endl; d_mx_shared = NULL; err = hipMalloc((void **) &d_mx_shared, sizeD); if (err != hipSuccess) cout << "ERROR RESERVA MX (SHARED)" << endl; //* Initialize arrays */ for (int i=0; i<N; i++){ h_A[i]= (float) (1 -(i%100)*0.001); h_B[i]= (float) (0.5+(i%10) *0.1 ); } hipDeviceSetCacheConfig(hipFuncCachePreferShared); /*********************** GPU Phase (global memory) ************************/ double t1 = cpuSecond(); // copy A and B to device err = hipMemcpy(d_A, h_A, sizeABC, hipMemcpyHostToDevice); if (err != hipSuccess) cout << "ERROR COPIA A" << endl; err = hipMemcpy(d_B, h_B, sizeABC, hipMemcpyHostToDevice); if (err != hipSuccess) cout << "ERROR COPIA B" << endl; dim3 threadsPerBlock(Bsize, 1); dim3 numBlocks(NBlocks, 1); int smemSize = Bsize*4*sizeof(float); transformacion_kernel_global<<<numBlocks, threadsPerBlock, smemSize>>>( d_A, d_B, d_C, d_D_global, d_mx_global); hipMemcpy(h_D_global, d_D_global, NBlocks*sizeof(float), hipMemcpyDeviceToHost); hipMemcpy(h_mx_global, d_mx_global, NBlocks*sizeof(float), hipMemcpyDeviceToHost); float mx_global_final = h_mx_global[0]; hipDeviceSynchronize(); // final reduction on CPU for (int k = 1; k<NBlocks; k++) mx_global_final = (mx_global_final > h_mx_global[k]) ? mx_global_final : h_mx_global[k]; double tgpu_global=cpuSecond()-t1; /********************** GPU Phase (shared memory) **********************/ t1 = cpuSecond(); // copy A and B to device //err = cudaMemcpy(d_A, h_A, sizeABC, cudaMemcpyHostToDevice); //if (err != cudaSuccess) cout << "ERROR COPIA A" << endl; //err = cudaMemcpy(d_B, h_B, sizeABC, cudaMemcpyHostToDevice); //if (err != cudaSuccess) cout << "ERROR COPIA B" << endl; smemSize = Bsize*4*sizeof(float); transformacion_kernel_shared<<<numBlocks, threadsPerBlock, smemSize>>>( d_A, d_B, d_C, d_D_shared, d_mx_shared); hipMemcpy(h_D_shared, d_D_shared, NBlocks*sizeof(float), hipMemcpyDeviceToHost); hipMemcpy(h_mx_shared, d_mx_shared, NBlocks*sizeof(float), hipMemcpyDeviceToHost); float mx_shared_final = h_mx_shared[0]; hipDeviceSynchronize(); // final reduction on CPU for (int k = 1; k<NBlocks; k++) mx_shared_final = (mx_shared_final > h_mx_shared[k]) ? mx_shared_final : h_mx_shared[k]; double tgpu_shared=cpuSecond()-t1; /******************************* CPU Phase *****************************/ // Time measurement t1=cpuSecond(); // Compute C[i], d[K] and mx for (int k=0; k<NBlocks;k++) { int istart=k*Bsize; int iend =istart+Bsize; h_D[k]=0.0; for (int i=istart; i<iend;i++){ h_C[i]=0.0; for (int j=istart; j<iend;j++){ float a=h_A[j]*i; if ((int)ceil(a) % 2 ==0) h_C[i]+= a + h_B[j]; else h_C[i]+= a - h_B[j]; } h_D[k]+=h_C[i]; h_mx= (i==1) ? h_C[0] : max(h_C[i],h_mx); } } double tsec=cpuSecond()-t1; /********************** RESULTADOS ***************************/ //for (int i=0; i<N;i++) cout<<"C["<<i<<"]="<<h_C[i]<<endl; /*cout<<"................................."<<endl; for (int k=0; k<NBlocks;k++){ cout<<"D["<<k<<"]="<<h_D[k]<<endl; cout<<"D_global["<<k<<"]="<<h_D_global[k]<<endl; cout<<"D_shared["<<k<<"]="<<h_D_shared[k]<<endl; }*/ cout<<"................................."<<endl<<"El valor máximo en C (sec) es: "<<h_mx<<endl; cout<<"................................."<<endl<<"El valor máximo en C (gpu global) es: "<<mx_global_final<<endl; cout<<"................................."<<endl<<"El valor máximo en C (gpu shared) es: "<<mx_shared_final << endl; cout << endl << "N=" << N << "= " << Bsize << "*" << NBlocks << endl; cout << "Tiempo gastado CPU= " << tsec << endl; cout << "Tiempo gastado GPU (mem global)= " << tgpu_global << endl; cout << "Tiempo gastado GPU (mem compartida)= " << tgpu_shared << endl; cout << endl << "Ganancia mem global = " << tsec/tgpu_global << endl; cout << "Ganancia mem compartida = " << tsec/tgpu_shared << endl; // Free host memory delete [] h_A; delete [] h_B; delete [] h_C; delete [] h_D; delete [] h_D_global; delete [] h_mx_global; delete [] h_D_shared; delete [] h_mx_shared; // Free device memory hipFree(d_A); hipFree(d_B); hipFree(d_C); hipFree(d_mx_global); hipFree(d_mx_shared); hipFree(d_D_global); hipFree(d_D_shared); }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z28transformacion_kernel_globalPfS_S_S_S_ .globl _Z28transformacion_kernel_globalPfS_S_S_S_ .p2align 8 .type _Z28transformacion_kernel_globalPfS_S_S_S_,@function _Z28transformacion_kernel_globalPfS_S_S_S_: s_clause 0x1 s_load_b32 s3, s[0:1], 0x34 s_load_b128 s[4:7], s[0:1], 0x0 s_mov_b32 s2, s15 s_waitcnt lgkmcnt(0) s_and_b32 s3, s3, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) s_mul_i32 s8, s15, s3 s_lshl_b32 s9, s3, 2 v_add_nc_u32_e32 v1, s8, v0 s_cmp_eq_u32 s3, 0 v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[3:4], 2, v[1:2] v_add_co_u32 v5, vcc_lo, s4, v3 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo v_add_co_u32 v3, vcc_lo, s6, v3 v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo global_load_b32 v5, v[5:6], off global_load_b32 v3, v[3:4], off v_lshlrev_b32_e32 v4, 2, v0 s_delay_alu instid0(VALU_DEP_1) v_add_nc_u32_e32 v6, 0, v4 v_add3_u32 v4, 0, s9, v4 s_waitcnt vmcnt(1) ds_store_b32 v6, v5 s_waitcnt vmcnt(0) ds_store_b32 v4, v3 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv s_cbranch_scc1 .LBB0_3 s_ashr_i32 s9, s8, 31 s_add_i32 s10, s8, s3 s_lshl_b64 s[12:13], s[8:9], 2 v_cvt_f32_i32_e32 v4, v1 s_add_u32 s4, s4, s12 v_mov_b32_e32 v3, 0 s_addc_u32 s5, s5, s13 s_add_u32 s6, s6, s12 s_addc_u32 s7, s7, s13 .p2align 6 .LBB0_2: s_load_b32 s9, s[4:5], 0x0 s_add_i32 s8, s8, 1 s_add_u32 s4, s4, 4 s_addc_u32 s5, s5, 0 s_waitcnt lgkmcnt(0) v_mul_f32_e32 v5, s9, v4 s_load_b32 s9, s[6:7], 0x0 s_add_u32 s6, s6, 4 s_addc_u32 s7, s7, 0 s_cmp_ge_i32 s8, s10 v_ceil_f32_e32 v6, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cvt_i32_f32_e32 v6, v6 v_and_b32_e32 v6, 1, v6 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_eq_u32_e32 vcc_lo, 0, v6 v_cndmask_b32_e64 v6, -1, 1, vcc_lo v_cvt_f32_i32_e32 v6, v6 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmac_f32_e32 v5, s9, v6 v_add_f32_e32 v3, v3, v5 s_cbranch_scc0 .LBB0_2 s_branch .LBB0_4 .LBB0_3: v_mov_b32_e32 v3, 0 .LBB0_4: s_load_b64 s[6:7], s[0:1], 0x10 v_lshlrev_b64 v[4:5], 2, v[1:2] v_lshlrev_b32_e32 v6, 2, v0 s_lshl_b32 s4, s3, 3 s_mul_i32 s8, s3, 12 s_add_i32 s5, s4, 0 s_add_i32 s4, s8, 0 v_add_nc_u32_e32 v1, s5, v6 v_add_nc_u32_e32 v2, s4, v6 s_cmp_lt_u32 s3, 2 ds_store_b32 v1, v3 ds_store_b32 v2, v3 s_waitcnt lgkmcnt(0) v_add_co_u32 v4, vcc_lo, s6, v4 v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo global_store_b32 v[4:5], v3, off s_waitcnt_vscnt null, 0x0 s_barrier s_set_inst_prefetch_distance 0x1 s_branch .LBB0_6 .p2align 6 .LBB0_5: s_or_b32 exec_lo, exec_lo, s7 s_waitcnt lgkmcnt(0) s_barrier s_cmp_lt_u32 s3, 4 s_mov_b32 s3, s6 .LBB0_6: buffer_gl0_inv s_cbranch_scc1 .LBB0_9 s_lshr_b32 s6, s3, 1 s_mov_b32 s7, exec_lo v_cmpx_gt_u32_e64 s6, v0 s_cbranch_execz .LBB0_5 s_lshl_b32 s8, s6, 2 s_delay_alu instid0(SALU_CYCLE_1) v_add_nc_u32_e32 v3, s8, v1 ds_load_b32 v3, v3 ds_load_b32 v4, v1 s_waitcnt lgkmcnt(0) v_dual_add_f32 v3, v3, v4 :: v_dual_add_nc_u32 v4, s8, v2 ds_store_b32 v1, v3 ds_load_b32 v3, v2 ds_load_b32 v4, v4 s_waitcnt lgkmcnt(0) v_cmp_gt_f32_e32 vcc_lo, v3, v4 v_cndmask_b32_e32 v3, v4, v3, vcc_lo ds_store_b32 v2, v3 s_branch .LBB0_5 .LBB0_9: s_set_inst_prefetch_distance 0x2 s_mov_b32 s3, exec_lo v_cmpx_eq_u32_e32 0, v0 s_cbranch_execz .LBB0_11 v_dual_mov_b32 v0, s5 :: v_dual_mov_b32 v1, s4 s_load_b128 s[8:11], s[0:1], 0x18 s_mov_b32 s3, 0 v_mov_b32_e32 v2, 0 ds_load_b32 v0, v0 ds_load_b32 v1, v1 s_lshl_b64 s[0:1], s[2:3], 2 s_waitcnt lgkmcnt(0) s_add_u32 s2, s8, s0 s_addc_u32 s3, s9, s1 s_add_u32 s0, s10, s0 s_addc_u32 s1, s11, s1 s_clause 0x1 global_store_b32 v2, v0, s[2:3] global_store_b32 v2, v1, s[0:1] .LBB0_11: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z28transformacion_kernel_globalPfS_S_S_S_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 296 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 7 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z28transformacion_kernel_globalPfS_S_S_S_, .Lfunc_end0-_Z28transformacion_kernel_globalPfS_S_S_S_ .section .AMDGPU.csdata,"",@progbits .text .protected _Z28transformacion_kernel_sharedPfS_S_S_S_ .globl _Z28transformacion_kernel_sharedPfS_S_S_S_ .p2align 8 .type _Z28transformacion_kernel_sharedPfS_S_S_S_,@function _Z28transformacion_kernel_sharedPfS_S_S_S_: s_clause 0x1 s_load_b32 s3, s[0:1], 0x34 s_load_b128 s[4:7], s[0:1], 0x0 s_mov_b32 s2, s15 s_waitcnt lgkmcnt(0) s_and_b32 s3, s3, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1] v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[3:4], 2, v[1:2] v_add_co_u32 v5, vcc_lo, s4, v3 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo v_add_co_u32 v3, vcc_lo, s6, v3 v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo s_lshl_b32 s4, s3, 2 global_load_b32 v5, v[5:6], off global_load_b32 v3, v[3:4], off v_lshlrev_b32_e32 v4, 2, v0 s_mov_b32 s5, 0 s_cmp_eq_u32 s3, 0 s_delay_alu instid0(VALU_DEP_1) v_add_nc_u32_e32 v6, 0, v4 v_add3_u32 v4, 0, s4, v4 s_waitcnt vmcnt(1) ds_store_b32 v6, v5 s_waitcnt vmcnt(0) ds_store_b32 v4, v3 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv s_cbranch_scc1 .LBB1_3 v_cvt_f32_i32_e32 v4, v1 v_mov_b32_e32 v3, 0 s_add_i32 s6, s4, 0 .p2align 6 .LBB1_2: s_add_i32 s7, s5, 0 s_delay_alu instid0(SALU_CYCLE_1) v_mov_b32_e32 v5, s7 s_add_i32 s7, s6, s5 s_add_i32 s5, s5, 4 v_mov_b32_e32 v6, s7 s_cmp_eq_u32 s4, s5 ds_load_b32 v5, v5 ds_load_b32 v6, v6 s_waitcnt lgkmcnt(1) v_mul_f32_e32 v5, v5, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ceil_f32_e32 v7, v5 v_cvt_i32_f32_e32 v7, v7 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_and_b32_e32 v7, 1, v7 v_cmp_eq_u32_e32 vcc_lo, 0, v7 v_cndmask_b32_e64 v7, -1, 1, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cvt_f32_i32_e32 v7, v7 s_waitcnt lgkmcnt(0) v_fmac_f32_e32 v5, v6, v7 s_delay_alu instid0(VALU_DEP_1) v_add_f32_e32 v3, v3, v5 s_cbranch_scc0 .LBB1_2 s_branch .LBB1_4 .LBB1_3: v_mov_b32_e32 v3, 0 .LBB1_4: s_load_b64 s[6:7], s[0:1], 0x10 v_lshlrev_b64 v[4:5], 2, v[1:2] v_lshlrev_b32_e32 v6, 2, v0 s_lshl_b32 s4, s3, 3 s_mul_i32 s8, s3, 12 s_add_i32 s5, s4, 0 s_add_i32 s4, s8, 0 v_add_nc_u32_e32 v1, s5, v6 v_add_nc_u32_e32 v2, s4, v6 s_cmp_lt_u32 s3, 2 ds_store_b32 v1, v3 ds_store_b32 v2, v3 s_waitcnt lgkmcnt(0) v_add_co_u32 v4, vcc_lo, s6, v4 v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo global_store_b32 v[4:5], v3, off s_waitcnt_vscnt null, 0x0 s_barrier s_set_inst_prefetch_distance 0x1 s_branch .LBB1_6 .p2align 6 .LBB1_5: s_or_b32 exec_lo, exec_lo, s7 s_waitcnt lgkmcnt(0) s_barrier s_cmp_lt_u32 s3, 4 s_mov_b32 s3, s6 .LBB1_6: buffer_gl0_inv s_cbranch_scc1 .LBB1_9 s_lshr_b32 s6, s3, 1 s_mov_b32 s7, exec_lo v_cmpx_gt_u32_e64 s6, v0 s_cbranch_execz .LBB1_5 s_lshl_b32 s8, s6, 2 s_delay_alu instid0(SALU_CYCLE_1) v_add_nc_u32_e32 v3, s8, v1 ds_load_b32 v3, v3 ds_load_b32 v4, v1 s_waitcnt lgkmcnt(0) v_dual_add_f32 v3, v3, v4 :: v_dual_add_nc_u32 v4, s8, v2 ds_store_b32 v1, v3 ds_load_b32 v3, v2 ds_load_b32 v4, v4 s_waitcnt lgkmcnt(0) v_cmp_gt_f32_e32 vcc_lo, v3, v4 v_cndmask_b32_e32 v3, v4, v3, vcc_lo ds_store_b32 v2, v3 s_branch .LBB1_5 .LBB1_9: s_set_inst_prefetch_distance 0x2 s_mov_b32 s3, exec_lo v_cmpx_eq_u32_e32 0, v0 s_cbranch_execz .LBB1_11 v_dual_mov_b32 v0, s5 :: v_dual_mov_b32 v1, s4 s_load_b128 s[8:11], s[0:1], 0x18 s_mov_b32 s3, 0 v_mov_b32_e32 v2, 0 ds_load_b32 v0, v0 ds_load_b32 v1, v1 s_lshl_b64 s[0:1], s[2:3], 2 s_waitcnt lgkmcnt(0) s_add_u32 s2, s8, s0 s_addc_u32 s3, s9, s1 s_add_u32 s0, s10, s0 s_addc_u32 s1, s11, s1 s_clause 0x1 global_store_b32 v2, v0, s[2:3] global_store_b32 v2, v1, s[0:1] .LBB1_11: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z28transformacion_kernel_sharedPfS_S_S_S_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 296 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 8 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z28transformacion_kernel_sharedPfS_S_S_S_, .Lfunc_end1-_Z28transformacion_kernel_sharedPfS_S_S_S_ .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .offset: 40 .size: 4 .value_kind: hidden_block_count_x - .offset: 44 .size: 4 .value_kind: hidden_block_count_y - .offset: 48 .size: 4 .value_kind: hidden_block_count_z - .offset: 52 .size: 2 .value_kind: hidden_group_size_x - .offset: 54 .size: 2 .value_kind: hidden_group_size_y - .offset: 56 .size: 2 .value_kind: hidden_group_size_z - .offset: 58 .size: 2 .value_kind: hidden_remainder_x - .offset: 60 .size: 2 .value_kind: hidden_remainder_y - .offset: 62 .size: 2 .value_kind: hidden_remainder_z - .offset: 80 .size: 8 .value_kind: hidden_global_offset_x - .offset: 88 .size: 8 .value_kind: hidden_global_offset_y - .offset: 96 .size: 8 .value_kind: hidden_global_offset_z - .offset: 104 .size: 2 .value_kind: hidden_grid_dims - .offset: 160 .size: 4 .value_kind: hidden_dynamic_lds_size .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 296 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z28transformacion_kernel_globalPfS_S_S_S_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z28transformacion_kernel_globalPfS_S_S_S_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 7 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .offset: 40 .size: 4 .value_kind: hidden_block_count_x - .offset: 44 .size: 4 .value_kind: hidden_block_count_y - .offset: 48 .size: 4 .value_kind: hidden_block_count_z - .offset: 52 .size: 2 .value_kind: hidden_group_size_x - .offset: 54 .size: 2 .value_kind: hidden_group_size_y - .offset: 56 .size: 2 .value_kind: hidden_group_size_z - .offset: 58 .size: 2 .value_kind: hidden_remainder_x - .offset: 60 .size: 2 .value_kind: hidden_remainder_y - .offset: 62 .size: 2 .value_kind: hidden_remainder_z - .offset: 80 .size: 8 .value_kind: hidden_global_offset_x - .offset: 88 .size: 8 .value_kind: hidden_global_offset_y - .offset: 96 .size: 8 .value_kind: hidden_global_offset_z - .offset: 104 .size: 2 .value_kind: hidden_grid_dims - .offset: 160 .size: 4 .value_kind: hidden_dynamic_lds_size .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 296 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z28transformacion_kernel_sharedPfS_S_S_S_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z28transformacion_kernel_sharedPfS_S_S_S_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 8 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include "includes.h" __global__ void kernelA(int n, float *x, float *y) { int index = blockIdx.x * blockDim.x + threadIdx.x; int stride = blockDim.x * gridDim.x; for (int i = index; i < n; i += stride) { if (x[i] > y[i]) { for (int j = 0; j < n / CONST; j++) y[i] = x[j] + y[j]; } else { for (int j = 0; j < n / CONST; j++) y[i] = x[j] / y[j]; } } }
.file "tmpxft_000e7f72_00000000-6_kernelA.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z29__device_stub__Z7kernelAiPfS_iPfS_ .type _Z29__device_stub__Z7kernelAiPfS_iPfS_, @function _Z29__device_stub__Z7kernelAiPfS_iPfS_: .LFB2051: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movl %edi, 28(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 28(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 120(%rsp), %rax subq %fs:40, %rax jne .L8 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z7kernelAiPfS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z29__device_stub__Z7kernelAiPfS_iPfS_, .-_Z29__device_stub__Z7kernelAiPfS_iPfS_ .globl _Z7kernelAiPfS_ .type _Z7kernelAiPfS_, @function _Z7kernelAiPfS_: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z29__device_stub__Z7kernelAiPfS_iPfS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z7kernelAiPfS_, .-_Z7kernelAiPfS_ .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z7kernelAiPfS_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z7kernelAiPfS_(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include "includes.h" __global__ void kernelA(int n, float *x, float *y) { int index = blockIdx.x * blockDim.x + threadIdx.x; int stride = blockDim.x * gridDim.x; for (int i = index; i < n; i += stride) { if (x[i] > y[i]) { for (int j = 0; j < n / CONST; j++) y[i] = x[j] + y[j]; } else { for (int j = 0; j < n / CONST; j++) y[i] = x[j] / y[j]; } } }
#include <hip/hip_runtime.h> #include "includes.h" __global__ void kernelA(int n, float *x, float *y) { int index = blockIdx.x * blockDim.x + threadIdx.x; int stride = blockDim.x * gridDim.x; for (int i = index; i < n; i += stride) { if (x[i] > y[i]) { for (int j = 0; j < n / CONST; j++) y[i] = x[j] + y[j]; } else { for (int j = 0; j < n / CONST; j++) y[i] = x[j] / y[j]; } } }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <hip/hip_runtime.h> #include "includes.h" __global__ void kernelA(int n, float *x, float *y) { int index = blockIdx.x * blockDim.x + threadIdx.x; int stride = blockDim.x * gridDim.x; for (int i = index; i < n; i += stride) { if (x[i] > y[i]) { for (int j = 0; j < n / CONST; j++) y[i] = x[j] + y[j]; } else { for (int j = 0; j < n / CONST; j++) y[i] = x[j] / y[j]; } } }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z7kernelAiPfS_ .globl _Z7kernelAiPfS_ .p2align 8 .type _Z7kernelAiPfS_,@function _Z7kernelAiPfS_: s_clause 0x1 s_load_b32 s4, s[0:1], 0x24 s_load_b32 s8, s[0:1], 0x0 s_add_u32 s2, s0, 24 s_addc_u32 s3, s1, 0 s_mov_b32 s5, exec_lo s_waitcnt lgkmcnt(0) s_and_b32 s4, s4, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1] v_cmpx_gt_i32_e64 s8, v1 s_cbranch_execz .LBB0_9 s_load_b32 s11, s[2:3], 0x0 s_load_b128 s[0:3], s[0:1], 0x8 s_ashr_i32 s5, s8, 31 v_mov_b32_e32 v0, 0 s_lshr_b32 s5, s5, 25 s_mov_b32 s12, 0 s_add_i32 s5, s8, s5 s_delay_alu instid0(SALU_CYCLE_1) s_ashr_i32 s9, s5, 7 s_cmpk_gt_i32 s8, 0x7f s_cselect_b32 s10, -1, 0 s_waitcnt lgkmcnt(0) s_mul_i32 s11, s11, s4 s_branch .LBB0_3 .LBB0_2: s_or_b32 exec_lo, exec_lo, s13 v_add_nc_u32_e32 v1, s11, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_cmp_le_i32_e32 vcc_lo, s8, v1 s_or_b32 s12, vcc_lo, s12 s_and_not1_b32 exec_lo, exec_lo, s12 s_cbranch_execz .LBB0_9 .LBB0_3: v_ashrrev_i32_e32 v2, 31, v1 s_mov_b32 s4, exec_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[2:3], 2, v[1:2] v_add_co_u32 v4, vcc_lo, s0, v2 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo v_add_co_u32 v2, vcc_lo, s2, v2 v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo global_load_b32 v4, v[4:5], off global_load_b32 v5, v[2:3], off s_waitcnt vmcnt(0) v_cmpx_ngt_f32_e32 v4, v5 s_xor_b32 s13, exec_lo, s4 s_cbranch_execz .LBB0_6 s_mov_b64 s[4:5], s[2:3] s_and_not1_b32 vcc_lo, exec_lo, s10 s_mov_b64 s[6:7], s[0:1] s_mov_b32 s14, s9 s_cbranch_vccnz .LBB0_6 .p2align 6 .LBB0_5: s_clause 0x1 global_load_b32 v4, v0, s[6:7] global_load_b32 v5, v0, s[4:5] s_add_i32 s14, s14, -1 s_add_u32 s6, s6, 4 s_addc_u32 s7, s7, 0 s_add_u32 s4, s4, 4 s_addc_u32 s5, s5, 0 s_cmp_lg_u32 s14, 0 s_waitcnt vmcnt(0) v_div_scale_f32 v6, null, v5, v5, v4 v_div_scale_f32 v9, vcc_lo, v4, v5, v4 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_rcp_f32_e32 v7, v6 s_waitcnt_depctr 0xfff v_fma_f32 v8, -v6, v7, 1.0 v_fmac_f32_e32 v7, v8, v7 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f32_e32 v8, v9, v7 v_fma_f32 v10, -v6, v8, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fmac_f32_e32 v8, v10, v7 v_fma_f32 v6, -v6, v8, v9 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_div_fmas_f32 v6, v6, v7, v8 v_div_fixup_f32 v4, v6, v5, v4 global_store_b32 v[2:3], v4, off s_cbranch_scc1 .LBB0_5 .LBB0_6: s_and_not1_saveexec_b32 s13, s13 s_cbranch_execz .LBB0_2 s_mov_b64 s[4:5], s[2:3] s_and_not1_b32 vcc_lo, exec_lo, s10 s_mov_b64 s[6:7], s[0:1] s_mov_b32 s14, s9 s_cbranch_vccnz .LBB0_2 .LBB0_8: s_clause 0x1 global_load_b32 v4, v0, s[6:7] global_load_b32 v5, v0, s[4:5] s_add_i32 s14, s14, -1 s_add_u32 s6, s6, 4 s_addc_u32 s7, s7, 0 s_add_u32 s4, s4, 4 s_addc_u32 s5, s5, 0 s_cmp_eq_u32 s14, 0 s_waitcnt vmcnt(0) v_add_f32_e32 v4, v4, v5 global_store_b32 v[2:3], v4, off s_cbranch_scc0 .LBB0_8 s_branch .LBB0_2 .LBB0_9: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z7kernelAiPfS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 11 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z7kernelAiPfS_, .Lfunc_end0-_Z7kernelAiPfS_ .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .offset: 0 .size: 4 .value_kind: by_value - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z7kernelAiPfS_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z7kernelAiPfS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 11 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <hip/hip_runtime.h> #include "includes.h" __global__ void kernelA(int n, float *x, float *y) { int index = blockIdx.x * blockDim.x + threadIdx.x; int stride = blockDim.x * gridDim.x; for (int i = index; i < n; i += stride) { if (x[i] > y[i]) { for (int j = 0; j < n / CONST; j++) y[i] = x[j] + y[j]; } else { for (int j = 0; j < n / CONST; j++) y[i] = x[j] / y[j]; } } }
.text .file "kernelA.hip" .globl _Z22__device_stub__kernelAiPfS_ # -- Begin function _Z22__device_stub__kernelAiPfS_ .p2align 4, 0x90 .type _Z22__device_stub__kernelAiPfS_,@function _Z22__device_stub__kernelAiPfS_: # @_Z22__device_stub__kernelAiPfS_ .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movl %edi, 12(%rsp) movq %rsi, 72(%rsp) movq %rdx, 64(%rsp) leaq 12(%rsp), %rax movq %rax, 80(%rsp) leaq 72(%rsp), %rax movq %rax, 88(%rsp) leaq 64(%rsp), %rax movq %rax, 96(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z7kernelAiPfS_, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end0: .size _Z22__device_stub__kernelAiPfS_, .Lfunc_end0-_Z22__device_stub__kernelAiPfS_ .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z7kernelAiPfS_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z7kernelAiPfS_,@object # @_Z7kernelAiPfS_ .section .rodata,"a",@progbits .globl _Z7kernelAiPfS_ .p2align 3, 0x0 _Z7kernelAiPfS_: .quad _Z22__device_stub__kernelAiPfS_ .size _Z7kernelAiPfS_, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z7kernelAiPfS_" .size .L__unnamed_1, 16 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z22__device_stub__kernelAiPfS_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z7kernelAiPfS_ .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_000e7f72_00000000-6_kernelA.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z29__device_stub__Z7kernelAiPfS_iPfS_ .type _Z29__device_stub__Z7kernelAiPfS_iPfS_, @function _Z29__device_stub__Z7kernelAiPfS_iPfS_: .LFB2051: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movl %edi, 28(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 28(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 120(%rsp), %rax subq %fs:40, %rax jne .L8 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z7kernelAiPfS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z29__device_stub__Z7kernelAiPfS_iPfS_, .-_Z29__device_stub__Z7kernelAiPfS_iPfS_ .globl _Z7kernelAiPfS_ .type _Z7kernelAiPfS_, @function _Z7kernelAiPfS_: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z29__device_stub__Z7kernelAiPfS_iPfS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z7kernelAiPfS_, .-_Z7kernelAiPfS_ .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z7kernelAiPfS_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z7kernelAiPfS_(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "kernelA.hip" .globl _Z22__device_stub__kernelAiPfS_ # -- Begin function _Z22__device_stub__kernelAiPfS_ .p2align 4, 0x90 .type _Z22__device_stub__kernelAiPfS_,@function _Z22__device_stub__kernelAiPfS_: # @_Z22__device_stub__kernelAiPfS_ .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movl %edi, 12(%rsp) movq %rsi, 72(%rsp) movq %rdx, 64(%rsp) leaq 12(%rsp), %rax movq %rax, 80(%rsp) leaq 72(%rsp), %rax movq %rax, 88(%rsp) leaq 64(%rsp), %rax movq %rax, 96(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z7kernelAiPfS_, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end0: .size _Z22__device_stub__kernelAiPfS_, .Lfunc_end0-_Z22__device_stub__kernelAiPfS_ .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z7kernelAiPfS_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z7kernelAiPfS_,@object # @_Z7kernelAiPfS_ .section .rodata,"a",@progbits .globl _Z7kernelAiPfS_ .p2align 3, 0x0 _Z7kernelAiPfS_: .quad _Z22__device_stub__kernelAiPfS_ .size _Z7kernelAiPfS_, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z7kernelAiPfS_" .size .L__unnamed_1, 16 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z22__device_stub__kernelAiPfS_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z7kernelAiPfS_ .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include <thrust/host_vector.h> #include <thrust/device_vector.h> #include <thrust/execution_policy.h> #include <thrust/transform.h> struct TenX { __host__ __device__ int operator() (int x) const { return x*10; } } myFunctor; void hostVectors() { thrust::host_vector<int> vec1(4), vec2(4); printf("Host\n"); for (size_t i=0; i < vec1.size(); i++) vec1[i] = i; thrust::transform(vec1.begin(), vec1.end(), vec2.begin(), myFunctor); for (size_t i=0; i < vec1.size(); i++) { printf("%d\t%d\n", vec1[i], vec2[i]); } } void deviceVectors() { thrust::host_vector<int> vec1(4), vec2(4); thrust::device_vector<int> vec1_dev(4), vec2_dev(4); printf("Device\n"); for (size_t i=0; i < vec1.size(); i++) vec1[i] = i; vec1_dev = vec1; thrust::transform(vec1_dev.begin(), vec1_dev.end(), vec2_dev.begin(), myFunctor); vec2 = vec2_dev; for (size_t i=0; i < vec1.size(); i++) { printf("%d\t%d\n", vec1[i], vec2[i]); } } void deviceVectorDevPointers() { thrust::host_vector<int> vec1(4), vec2(4); thrust::device_vector<int> vec1_dev(4), vec2_dev(4); thrust::device_ptr<int> vec1_dev_start(thrust::raw_pointer_cast(&vec1_dev[0])); thrust::device_ptr<int> vec2_dev_start(thrust::raw_pointer_cast(&vec2_dev[0])); printf("Device device pointers\n"); for (size_t i=0; i < vec1.size(); i++) vec1[i] = i; vec1_dev = vec1; thrust::transform(thrust::device, vec1_dev_start, vec1_dev_start + 4, vec2_dev_start, myFunctor); vec2 = vec2_dev; for (size_t i=0; i < vec1.size(); i++) { printf("%d\t%d\n", vec1[i], vec2[i]); } } void deviceVectorPointers() { thrust::host_vector<int> vec1(4), vec2(4); thrust::device_vector<int> vec1_dev(4), vec2_dev(4); int *vec1_dev_start = thrust::raw_pointer_cast(&vec1_dev[0]); int *vec2_dev_start = thrust::raw_pointer_cast(&vec2_dev[0]); printf("Device pointers\n"); for (size_t i=0; i < vec1.size(); i++) vec1[i] = i; vec1_dev = vec1; thrust::transform(thrust::device, vec1_dev_start, vec1_dev_start + 4, vec2_dev_start, myFunctor); vec2 = vec2_dev; for (size_t i=0; i < vec1.size(); i++) { printf("%d\t%d\n", vec1[i], vec2[i]); } } void deviceVecToPointerToDevPointer() { thrust::host_vector<int> vec1(4), vec2(4); thrust::device_vector<int> vec1_dev(4), vec2_dev(4); int *vec1_dev_start = thrust::raw_pointer_cast(&vec1_dev[0]); int *vec2_dev_start = thrust::raw_pointer_cast(&vec2_dev[0]); thrust::device_ptr<int> vec1_dev_ptr(vec1_dev_start); thrust::device_ptr<int> vec2_dev_ptr(vec2_dev_start); printf("Device vec->ptr->devptr\n"); for (size_t i=0; i < vec1.size(); i++) vec1[i] = i; vec1_dev = vec1; thrust::transform(thrust::device, vec1_dev_ptr, vec1_dev_ptr + 4, vec2_dev_ptr, myFunctor); vec2 = vec2_dev; for (size_t i=0; i < vec1.size(); i++) { printf("%d\t%d\n", vec1[i], vec2[i]); } } int main() { hostVectors(); deviceVectors(); deviceVectorDevPointers(); deviceVectorPointers(); deviceVecToPointerToDevPointer(); return 0; }
code for sm_80 Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tElN6thrust20THRUST_200700_800_NS8cuda_cub11__transform17unary_transform_fIPiSB_NS9_14no_stencil_tagE4TenXNS9_21always_true_predicateEEEEEvT0_T1_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */ /* 0x000e220000002500 */ /*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fc60000000a00 */ /*0030*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */ /* 0x000e620000002100 */ /*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */ /* 0x001fca00078e00ff */ /*0050*/ IADD3 R0, P1, R2.reuse, R7, RZ ; /* 0x0000000702007210 */ /* 0x042fe40007f3e0ff */ /*0060*/ IADD3 R6, P0, -R2, c[0x0][0x160], RZ ; /* 0x0000580002067a10 */ /* 0x000fc60007f1e1ff */ /*0070*/ IMAD.X R5, RZ, RZ, R3, P1 ; /* 0x000000ffff057224 */ /* 0x000fe200008e0603 */ /*0080*/ IADD3.X R3, ~R3, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590003037a10 */ /* 0x000fe200007fe5ff */ /*0090*/ IMAD.SHL.U32 R2, R0, 0x4, RZ ; /* 0x0000000400027824 */ /* 0x000fe200078e00ff */ /*00a0*/ ISETP.GT.U32.AND P0, PT, R6, 0x1ff, PT ; /* 0x000001ff0600780c */ /* 0x000fe40003f04070 */ /*00b0*/ SHF.L.U64.HI R0, R0, 0x2, R5 ; /* 0x0000000200007819 */ /* 0x000fe40000010205 */ /*00c0*/ ISETP.GT.AND.EX P0, PT, R3, RZ, PT, P0 ; /* 0x000000ff0300720c */ /* 0x000fe40003f04300 */ /*00d0*/ IADD3 R4, P1, R2.reuse, c[0x0][0x168], RZ ; /* 0x00005a0002047a10 */ /* 0x040fe40007f3e0ff */ /*00e0*/ IADD3 R2, P2, R2, c[0x0][0x170], RZ ; /* 0x00005c0002027a10 */ /* 0x000fc40007f5e0ff */ /*00f0*/ IADD3.X R5, R0.reuse, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0000057a10 */ /* 0x040fe40000ffe4ff */ /*0100*/ IADD3.X R3, R0, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0000037a10 */ /* 0x000fca00017fe4ff */ /*0110*/ @P0 BRA 0x230 ; /* 0x0000011000000947 */ /* 0x000fea0003800000 */ /*0120*/ IADD3 R0, R7, 0x100, RZ ; /* 0x0000010007007810 */ /* 0x000fe20007ffe0ff */ /*0130*/ BSSY B0, 0x1e0 ; /* 0x000000a000007945 */ /* 0x000fe20003800000 */ /*0140*/ ISETP.GT.U32.AND P0, PT, R6.reuse, R7, PT ; /* 0x000000070600720c */ /* 0x040fe40003f04070 */ /*0150*/ SHF.R.S32.HI R7, RZ, 0x1f, R6 ; /* 0x0000001fff077819 */ /* 0x000fe40000011406 */ /*0160*/ ISETP.GT.U32.AND P1, PT, R6, R0, PT ; /* 0x000000000600720c */ /* 0x000fe40003f24070 */ /*0170*/ ISETP.GT.AND.EX P0, PT, R7.reuse, RZ, PT, P0 ; /* 0x000000ff0700720c */ /* 0x040fe40003f04300 */ /*0180*/ ISETP.GT.AND.EX P1, PT, R7, RZ, PT, P1 ; /* 0x000000ff0700720c */ /* 0x000fd60003f24310 */ /*0190*/ @!P0 BRA 0x1d0 ; /* 0x0000003000008947 */ /* 0x000fea0003800000 */ /*01a0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */ /* 0x000ea4000c1e1900 */ /*01b0*/ IMAD R7, R0, 0xa, RZ ; /* 0x0000000a00077824 */ /* 0x004fca00078e02ff */ /*01c0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */ /* 0x0001e4000c101904 */ /*01d0*/ BSYNC B0 ; /* 0x0000000000007941 */ /* 0x000fea0003800000 */ /*01e0*/ @!P1 EXIT ; /* 0x000000000000994d */ /* 0x000fea0003800000 */ /*01f0*/ LDG.E R4, [R4.64+0x400] ; /* 0x0004000404047981 */ /* 0x000ea4000c1e1900 */ /*0200*/ IMAD R7, R4, 0xa, RZ ; /* 0x0000000a04077824 */ /* 0x005fca00078e02ff */ /*0210*/ STG.E [R2.64+0x400], R7 ; /* 0x0004000702007986 */ /* 0x000fe2000c101904 */ /*0220*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0230*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */ /* 0x000ea4000c1e1900 */ /*0240*/ IMAD R7, R0, 0xa, RZ ; /* 0x0000000a00077824 */ /* 0x004fca00078e02ff */ /*0250*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */ /* 0x000fe8000c101904 */ /*0260*/ LDG.E R0, [R4.64+0x400] ; /* 0x0004000404007981 */ /* 0x000ea4000c1e1900 */ /*0270*/ IMAD R9, R0, 0xa, RZ ; /* 0x0000000a00097824 */ /* 0x004fca00078e02ff */ /*0280*/ STG.E [R2.64+0x400], R9 ; /* 0x0004000902007986 */ /* 0x000fe2000c101904 */ /*0290*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*02a0*/ BRA 0x2a0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*02b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0300*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0310*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0320*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0330*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0340*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0350*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0360*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0370*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ .......... Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tElN6thrust20THRUST_200700_800_NS8cuda_cub11__transform17unary_transform_fINS7_10device_ptrIiEESC_NS9_14no_stencil_tagE4TenXNS9_21always_true_predicateEEEEEvT0_T1_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */ /* 0x000e220000002500 */ /*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fc60000000a00 */ /*0030*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */ /* 0x000e620000002100 */ /*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */ /* 0x001fca00078e00ff */ /*0050*/ IADD3 R0, P1, R2.reuse, R7, RZ ; /* 0x0000000702007210 */ /* 0x042fe40007f3e0ff */ /*0060*/ IADD3 R6, P0, -R2, c[0x0][0x160], RZ ; /* 0x0000580002067a10 */ /* 0x000fc60007f1e1ff */ /*0070*/ IMAD.X R5, RZ, RZ, R3, P1 ; /* 0x000000ffff057224 */ /* 0x000fe200008e0603 */ /*0080*/ IADD3.X R3, ~R3, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590003037a10 */ /* 0x000fe200007fe5ff */ /*0090*/ IMAD.SHL.U32 R2, R0, 0x4, RZ ; /* 0x0000000400027824 */ /* 0x000fe200078e00ff */ /*00a0*/ ISETP.GT.U32.AND P0, PT, R6, 0x1ff, PT ; /* 0x000001ff0600780c */ /* 0x000fe40003f04070 */ /*00b0*/ SHF.L.U64.HI R0, R0, 0x2, R5 ; /* 0x0000000200007819 */ /* 0x000fe40000010205 */ /*00c0*/ ISETP.GT.AND.EX P0, PT, R3, RZ, PT, P0 ; /* 0x000000ff0300720c */ /* 0x000fe40003f04300 */ /*00d0*/ IADD3 R4, P1, R2.reuse, c[0x0][0x168], RZ ; /* 0x00005a0002047a10 */ /* 0x040fe40007f3e0ff */ /*00e0*/ IADD3 R2, P2, R2, c[0x0][0x170], RZ ; /* 0x00005c0002027a10 */ /* 0x000fc40007f5e0ff */ /*00f0*/ IADD3.X R5, R0.reuse, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0000057a10 */ /* 0x040fe40000ffe4ff */ /*0100*/ IADD3.X R3, R0, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0000037a10 */ /* 0x000fca00017fe4ff */ /*0110*/ @P0 BRA 0x230 ; /* 0x0000011000000947 */ /* 0x000fea0003800000 */ /*0120*/ IADD3 R0, R7, 0x100, RZ ; /* 0x0000010007007810 */ /* 0x000fe20007ffe0ff */ /*0130*/ BSSY B0, 0x1e0 ; /* 0x000000a000007945 */ /* 0x000fe20003800000 */ /*0140*/ ISETP.GT.U32.AND P0, PT, R6.reuse, R7, PT ; /* 0x000000070600720c */ /* 0x040fe40003f04070 */ /*0150*/ SHF.R.S32.HI R7, RZ, 0x1f, R6 ; /* 0x0000001fff077819 */ /* 0x000fe40000011406 */ /*0160*/ ISETP.GT.U32.AND P1, PT, R6, R0, PT ; /* 0x000000000600720c */ /* 0x000fe40003f24070 */ /*0170*/ ISETP.GT.AND.EX P0, PT, R7.reuse, RZ, PT, P0 ; /* 0x000000ff0700720c */ /* 0x040fe40003f04300 */ /*0180*/ ISETP.GT.AND.EX P1, PT, R7, RZ, PT, P1 ; /* 0x000000ff0700720c */ /* 0x000fd60003f24310 */ /*0190*/ @!P0 BRA 0x1d0 ; /* 0x0000003000008947 */ /* 0x000fea0003800000 */ /*01a0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */ /* 0x000ea4000c1e1900 */ /*01b0*/ IMAD R7, R0, 0xa, RZ ; /* 0x0000000a00077824 */ /* 0x004fca00078e02ff */ /*01c0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */ /* 0x0001e4000c101904 */ /*01d0*/ BSYNC B0 ; /* 0x0000000000007941 */ /* 0x000fea0003800000 */ /*01e0*/ @!P1 EXIT ; /* 0x000000000000994d */ /* 0x000fea0003800000 */ /*01f0*/ LDG.E R4, [R4.64+0x400] ; /* 0x0004000404047981 */ /* 0x000ea4000c1e1900 */ /*0200*/ IMAD R7, R4, 0xa, RZ ; /* 0x0000000a04077824 */ /* 0x005fca00078e02ff */ /*0210*/ STG.E [R2.64+0x400], R7 ; /* 0x0004000702007986 */ /* 0x000fe2000c101904 */ /*0220*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0230*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */ /* 0x000ea4000c1e1900 */ /*0240*/ IMAD R7, R0, 0xa, RZ ; /* 0x0000000a00077824 */ /* 0x004fca00078e02ff */ /*0250*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */ /* 0x000fe8000c101904 */ /*0260*/ LDG.E R0, [R4.64+0x400] ; /* 0x0004000404007981 */ /* 0x000ea4000c1e1900 */ /*0270*/ IMAD R9, R0, 0xa, RZ ; /* 0x0000000a00097824 */ /* 0x004fca00078e02ff */ /*0280*/ STG.E [R2.64+0x400], R9 ; /* 0x0004000902007986 */ /* 0x000fe2000c101904 */ /*0290*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*02a0*/ BRA 0x2a0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*02b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0300*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0310*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0320*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0330*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0340*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0350*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0360*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0370*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ .......... Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tElN6thrust20THRUST_200700_800_NS8cuda_cub11__transform17unary_transform_fINS7_6detail15normal_iteratorINS7_10device_ptrIiEEEESF_NS9_14no_stencil_tagE4TenXNS9_21always_true_predicateEEEEEvT0_T1_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */ /* 0x000e220000002500 */ /*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fc60000000a00 */ /*0030*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */ /* 0x000e620000002100 */ /*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */ /* 0x001fca00078e00ff */ /*0050*/ IADD3 R0, P1, R2.reuse, R7, RZ ; /* 0x0000000702007210 */ /* 0x042fe40007f3e0ff */ /*0060*/ IADD3 R6, P0, -R2, c[0x0][0x160], RZ ; /* 0x0000580002067a10 */ /* 0x000fc60007f1e1ff */ /*0070*/ IMAD.X R5, RZ, RZ, R3, P1 ; /* 0x000000ffff057224 */ /* 0x000fe200008e0603 */ /*0080*/ IADD3.X R3, ~R3, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590003037a10 */ /* 0x000fe200007fe5ff */ /*0090*/ IMAD.SHL.U32 R2, R0, 0x4, RZ ; /* 0x0000000400027824 */ /* 0x000fe200078e00ff */ /*00a0*/ ISETP.GT.U32.AND P0, PT, R6, 0x1ff, PT ; /* 0x000001ff0600780c */ /* 0x000fe40003f04070 */ /*00b0*/ SHF.L.U64.HI R0, R0, 0x2, R5 ; /* 0x0000000200007819 */ /* 0x000fe40000010205 */ /*00c0*/ ISETP.GT.AND.EX P0, PT, R3, RZ, PT, P0 ; /* 0x000000ff0300720c */ /* 0x000fe40003f04300 */ /*00d0*/ IADD3 R4, P1, R2.reuse, c[0x0][0x168], RZ ; /* 0x00005a0002047a10 */ /* 0x040fe40007f3e0ff */ /*00e0*/ IADD3 R2, P2, R2, c[0x0][0x170], RZ ; /* 0x00005c0002027a10 */ /* 0x000fc40007f5e0ff */ /*00f0*/ IADD3.X R5, R0.reuse, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0000057a10 */ /* 0x040fe40000ffe4ff */ /*0100*/ IADD3.X R3, R0, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0000037a10 */ /* 0x000fca00017fe4ff */ /*0110*/ @P0 BRA 0x230 ; /* 0x0000011000000947 */ /* 0x000fea0003800000 */ /*0120*/ IADD3 R0, R7, 0x100, RZ ; /* 0x0000010007007810 */ /* 0x000fe20007ffe0ff */ /*0130*/ BSSY B0, 0x1e0 ; /* 0x000000a000007945 */ /* 0x000fe20003800000 */ /*0140*/ ISETP.GT.U32.AND P0, PT, R6.reuse, R7, PT ; /* 0x000000070600720c */ /* 0x040fe40003f04070 */ /*0150*/ SHF.R.S32.HI R7, RZ, 0x1f, R6 ; /* 0x0000001fff077819 */ /* 0x000fe40000011406 */ /*0160*/ ISETP.GT.U32.AND P1, PT, R6, R0, PT ; /* 0x000000000600720c */ /* 0x000fe40003f24070 */ /*0170*/ ISETP.GT.AND.EX P0, PT, R7.reuse, RZ, PT, P0 ; /* 0x000000ff0700720c */ /* 0x040fe40003f04300 */ /*0180*/ ISETP.GT.AND.EX P1, PT, R7, RZ, PT, P1 ; /* 0x000000ff0700720c */ /* 0x000fd60003f24310 */ /*0190*/ @!P0 BRA 0x1d0 ; /* 0x0000003000008947 */ /* 0x000fea0003800000 */ /*01a0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */ /* 0x000ea4000c1e1900 */ /*01b0*/ IMAD R7, R0, 0xa, RZ ; /* 0x0000000a00077824 */ /* 0x004fca00078e02ff */ /*01c0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */ /* 0x0001e4000c101904 */ /*01d0*/ BSYNC B0 ; /* 0x0000000000007941 */ /* 0x000fea0003800000 */ /*01e0*/ @!P1 EXIT ; /* 0x000000000000994d */ /* 0x000fea0003800000 */ /*01f0*/ LDG.E R4, [R4.64+0x400] ; /* 0x0004000404047981 */ /* 0x000ea4000c1e1900 */ /*0200*/ IMAD R7, R4, 0xa, RZ ; /* 0x0000000a04077824 */ /* 0x005fca00078e02ff */ /*0210*/ STG.E [R2.64+0x400], R7 ; /* 0x0004000702007986 */ /* 0x000fe2000c101904 */ /*0220*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0230*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */ /* 0x000ea4000c1e1900 */ /*0240*/ IMAD R7, R0, 0xa, RZ ; /* 0x0000000a00077824 */ /* 0x004fca00078e02ff */ /*0250*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */ /* 0x000fe8000c101904 */ /*0260*/ LDG.E R0, [R4.64+0x400] ; /* 0x0004000404007981 */ /* 0x000ea4000c1e1900 */ /*0270*/ IMAD R9, R0, 0xa, RZ ; /* 0x0000000a00097824 */ /* 0x004fca00078e02ff */ /*0280*/ STG.E [R2.64+0x400], R9 ; /* 0x0004000902007986 */ /* 0x000fe2000c101904 */ /*0290*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*02a0*/ BRA 0x2a0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*02b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0300*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0310*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0320*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0330*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0340*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0350*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0360*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0370*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ .......... Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIiEEiEEEEvT0_T1_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */ /* 0x000e220000002500 */ /*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fc60000000a00 */ /*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */ /* 0x000e620000002100 */ /*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */ /* 0x001fca00078e00ff */ /*0050*/ IADD3 R4, P1, -R2.reuse, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */ /* 0x040fe40007f3e1ff */ /*0060*/ IADD3 R0, P2, R2, R5, RZ ; /* 0x0000000502007210 */ /* 0x002fe40007f5e0ff */ /*0070*/ ISETP.GT.U32.AND P0, PT, R4, 0x1ff, PT ; /* 0x000001ff0400780c */ /* 0x000fe40003f04070 */ /*0080*/ IADD3.X R6, ~R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003067a10 */ /* 0x000fe20000ffe5ff */ /*0090*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */ /* 0x000fe200010e0603 */ /*00a0*/ LEA R2, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */ /* 0x000fe400078210ff */ /*00b0*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */ /* 0x000fc40003f04100 */ /*00c0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0000037a11 */ /* 0x000fd600008f1403 */ /*00d0*/ @P0 BRA 0x1a0 ; /* 0x000000c000000947 */ /* 0x000fea0003800000 */ /*00e0*/ ISETP.GT.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */ /* 0x000fe40003f04070 */ /*00f0*/ SHF.R.S32.HI R6, RZ, 0x1f, R4 ; /* 0x0000001fff067819 */ /* 0x000fe40000011404 */ /*0100*/ IADD3 R0, R5, 0x100, RZ ; /* 0x0000010005007810 */ /* 0x000fe40007ffe0ff */ /*0110*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */ /* 0x000fda0003f04100 */ /*0120*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff070624 */ /* 0x000fca00078e00ff */ /*0130*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */ /* 0x0001e2000c101904 */ /*0140*/ ISETP.GT.U32.AND P0, PT, R4, R0, PT ; /* 0x000000000400720c */ /* 0x000fc80003f04070 */ /*0150*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */ /* 0x000fda0003f04100 */ /*0160*/ @!P0 EXIT ; /* 0x000000000000894d */ /* 0x000fea0003800000 */ /*0170*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */ /* 0x001fca00078e00ff */ /*0180*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */ /* 0x000fe2000c101904 */ /*0190*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */ /* 0x000fca00078e00ff */ /*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */ /* 0x000fe8000c101904 */ /*01c0*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */ /* 0x000fe2000c101904 */ /*01d0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0200*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0210*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0220*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0230*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0240*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0250*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0260*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0270*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ .......... Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0020*/ BRA 0x20; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0030*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0040*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0050*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0060*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0070*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0080*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0090*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include <thrust/host_vector.h> #include <thrust/device_vector.h> #include <thrust/execution_policy.h> #include <thrust/transform.h> struct TenX { __host__ __device__ int operator() (int x) const { return x*10; } } myFunctor; void hostVectors() { thrust::host_vector<int> vec1(4), vec2(4); printf("Host\n"); for (size_t i=0; i < vec1.size(); i++) vec1[i] = i; thrust::transform(vec1.begin(), vec1.end(), vec2.begin(), myFunctor); for (size_t i=0; i < vec1.size(); i++) { printf("%d\t%d\n", vec1[i], vec2[i]); } } void deviceVectors() { thrust::host_vector<int> vec1(4), vec2(4); thrust::device_vector<int> vec1_dev(4), vec2_dev(4); printf("Device\n"); for (size_t i=0; i < vec1.size(); i++) vec1[i] = i; vec1_dev = vec1; thrust::transform(vec1_dev.begin(), vec1_dev.end(), vec2_dev.begin(), myFunctor); vec2 = vec2_dev; for (size_t i=0; i < vec1.size(); i++) { printf("%d\t%d\n", vec1[i], vec2[i]); } } void deviceVectorDevPointers() { thrust::host_vector<int> vec1(4), vec2(4); thrust::device_vector<int> vec1_dev(4), vec2_dev(4); thrust::device_ptr<int> vec1_dev_start(thrust::raw_pointer_cast(&vec1_dev[0])); thrust::device_ptr<int> vec2_dev_start(thrust::raw_pointer_cast(&vec2_dev[0])); printf("Device device pointers\n"); for (size_t i=0; i < vec1.size(); i++) vec1[i] = i; vec1_dev = vec1; thrust::transform(thrust::device, vec1_dev_start, vec1_dev_start + 4, vec2_dev_start, myFunctor); vec2 = vec2_dev; for (size_t i=0; i < vec1.size(); i++) { printf("%d\t%d\n", vec1[i], vec2[i]); } } void deviceVectorPointers() { thrust::host_vector<int> vec1(4), vec2(4); thrust::device_vector<int> vec1_dev(4), vec2_dev(4); int *vec1_dev_start = thrust::raw_pointer_cast(&vec1_dev[0]); int *vec2_dev_start = thrust::raw_pointer_cast(&vec2_dev[0]); printf("Device pointers\n"); for (size_t i=0; i < vec1.size(); i++) vec1[i] = i; vec1_dev = vec1; thrust::transform(thrust::device, vec1_dev_start, vec1_dev_start + 4, vec2_dev_start, myFunctor); vec2 = vec2_dev; for (size_t i=0; i < vec1.size(); i++) { printf("%d\t%d\n", vec1[i], vec2[i]); } } void deviceVecToPointerToDevPointer() { thrust::host_vector<int> vec1(4), vec2(4); thrust::device_vector<int> vec1_dev(4), vec2_dev(4); int *vec1_dev_start = thrust::raw_pointer_cast(&vec1_dev[0]); int *vec2_dev_start = thrust::raw_pointer_cast(&vec2_dev[0]); thrust::device_ptr<int> vec1_dev_ptr(vec1_dev_start); thrust::device_ptr<int> vec2_dev_ptr(vec2_dev_start); printf("Device vec->ptr->devptr\n"); for (size_t i=0; i < vec1.size(); i++) vec1[i] = i; vec1_dev = vec1; thrust::transform(thrust::device, vec1_dev_ptr, vec1_dev_ptr + 4, vec2_dev_ptr, myFunctor); vec2 = vec2_dev; for (size_t i=0; i < vec1.size(); i++) { printf("%d\t%d\n", vec1[i], vec2[i]); } } int main() { hostVectors(); deviceVectors(); deviceVectorDevPointers(); deviceVectorPointers(); deviceVecToPointerToDevPointer(); return 0; }
#include <hip/hip_runtime.h> #include <thrust/host_vector.h> #include <thrust/device_vector.h> #include <thrust/execution_policy.h> #include <thrust/transform.h> struct TenX { __host__ __device__ int operator() (int x) const { return x*10; } } myFunctor; void hostVectors() { thrust::host_vector<int> vec1(4), vec2(4); printf("Host\n"); for (size_t i=0; i < vec1.size(); i++) vec1[i] = i; thrust::transform(vec1.begin(), vec1.end(), vec2.begin(), myFunctor); for (size_t i=0; i < vec1.size(); i++) { printf("%d\t%d\n", vec1[i], vec2[i]); } } void deviceVectors() { thrust::host_vector<int> vec1(4), vec2(4); thrust::device_vector<int> vec1_dev(4), vec2_dev(4); printf("Device\n"); for (size_t i=0; i < vec1.size(); i++) vec1[i] = i; vec1_dev = vec1; thrust::transform(vec1_dev.begin(), vec1_dev.end(), vec2_dev.begin(), myFunctor); vec2 = vec2_dev; for (size_t i=0; i < vec1.size(); i++) { printf("%d\t%d\n", vec1[i], vec2[i]); } } void deviceVectorDevPointers() { thrust::host_vector<int> vec1(4), vec2(4); thrust::device_vector<int> vec1_dev(4), vec2_dev(4); thrust::device_ptr<int> vec1_dev_start(thrust::raw_pointer_cast(&vec1_dev[0])); thrust::device_ptr<int> vec2_dev_start(thrust::raw_pointer_cast(&vec2_dev[0])); printf("Device device pointers\n"); for (size_t i=0; i < vec1.size(); i++) vec1[i] = i; vec1_dev = vec1; thrust::transform(thrust::device, vec1_dev_start, vec1_dev_start + 4, vec2_dev_start, myFunctor); vec2 = vec2_dev; for (size_t i=0; i < vec1.size(); i++) { printf("%d\t%d\n", vec1[i], vec2[i]); } } void deviceVectorPointers() { thrust::host_vector<int> vec1(4), vec2(4); thrust::device_vector<int> vec1_dev(4), vec2_dev(4); int *vec1_dev_start = thrust::raw_pointer_cast(&vec1_dev[0]); int *vec2_dev_start = thrust::raw_pointer_cast(&vec2_dev[0]); printf("Device pointers\n"); for (size_t i=0; i < vec1.size(); i++) vec1[i] = i; vec1_dev = vec1; thrust::transform(thrust::device, vec1_dev_start, vec1_dev_start + 4, vec2_dev_start, myFunctor); vec2 = vec2_dev; for (size_t i=0; i < vec1.size(); i++) { printf("%d\t%d\n", vec1[i], vec2[i]); } } void deviceVecToPointerToDevPointer() { thrust::host_vector<int> vec1(4), vec2(4); thrust::device_vector<int> vec1_dev(4), vec2_dev(4); int *vec1_dev_start = thrust::raw_pointer_cast(&vec1_dev[0]); int *vec2_dev_start = thrust::raw_pointer_cast(&vec2_dev[0]); thrust::device_ptr<int> vec1_dev_ptr(vec1_dev_start); thrust::device_ptr<int> vec2_dev_ptr(vec2_dev_start); printf("Device vec->ptr->devptr\n"); for (size_t i=0; i < vec1.size(); i++) vec1[i] = i; vec1_dev = vec1; thrust::transform(thrust::device, vec1_dev_ptr, vec1_dev_ptr + 4, vec2_dev_ptr, myFunctor); vec2 = vec2_dev; for (size_t i=0; i < vec1.size(); i++) { printf("%d\t%d\n", vec1[i], vec2[i]); } } int main() { hostVectors(); deviceVectors(); deviceVectorDevPointers(); deviceVectorPointers(); deviceVecToPointerToDevPointer(); return 0; }