system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include "curand_kernel.h"
#include <memory>
#include <ctime>
#include <stdio.h>
#include <stdlib.h>
#include <chrono>
#include <algorithm>
#include <numeric>
using defer = std::shared_ptr<void>;
#define HEIGHT 32
#define WIDTH 32
#define hBLOCKS 6
#define wBLOCKS 6
//return resurl of this expression (x*x + y*y <= 1)
__device__ bool inCircle(curandState_t* state)
{
float x = curand_uniform(state);
float y = curand_uniform(state);
return x * x + y * y <= 1.0f;
}
__global__ void CalculatePointsIntheCircle(int* result, int randseed)
{
curandState_t state;
unsigned long long seed = (threadIdx.x + blockDim.x * blockIdx.x) + (threadIdx.y + blockDim.y * blockIdx.y) * (randseed % 1000);
//init curand
curand_init(seed, 0, 0, &state);
if (inCircle(&state))
{
atomicAdd(&result[threadIdx.x * HEIGHT + threadIdx.y], 1);
}
return;
}
int main()
{
const size_t size = WIDTH * HEIGHT;
int count [size];
memset(&count, 0, size * sizeof(int));
int* dev_count;
cudaMalloc((void**)&dev_count, size * sizeof(int));
// starting the timer here so that we include the cost of
// all of the operations on the GPU.
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
//use un_ptr, that don`t forget free memory
defer _(nullptr, [&](...)
{ cudaFree(dev_count); cudaEventDestroy(start); cudaEventDestroy(stop); printf("free"); });
dim3 blocks(hBLOCKS, wBLOCKS, 1);
dim3 threads(HEIGHT, WIDTH, 1);
int randseed = std::chrono::duration_cast<std::chrono::milliseconds>
(std::chrono::system_clock::now().time_since_epoch()).count();
CalculatePointsIntheCircle <<<blocks, threads >>> (dev_count, randseed);
cudaMemcpy(&count, dev_count, size * sizeof(int), cudaMemcpyDeviceToHost);
// result pi
int ans = 0;
ans = std::accumulate(&count[0], &count[size - 1], ans);
float fullsize = static_cast<float>(HEIGHT * WIDTH * hBLOCKS * wBLOCKS);
float pi = (4.0f * static_cast<float>(ans));
pi /= fullsize;
printf("Result pi %f \n", pi);
//print elapsed time
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
printf( "Elapsed time %3.1f ms\n", elapsedTime );
return 0;
} | #include <hip/hip_runtime.h>
#include "hiprand/hiprand_kernel.h"
#include <memory>
#include <ctime>
#include <stdio.h>
#include <stdlib.h>
#include <chrono>
#include <algorithm>
#include <numeric>
using defer = std::shared_ptr<void>;
#define HEIGHT 32
#define WIDTH 32
#define hBLOCKS 6
#define wBLOCKS 6
//return resurl of this expression (x*x + y*y <= 1)
__device__ bool inCircle(hiprandState_t* state)
{
float x = hiprand_uniform(state);
float y = hiprand_uniform(state);
return x * x + y * y <= 1.0f;
}
__global__ void CalculatePointsIntheCircle(int* result, int randseed)
{
hiprandState_t state;
unsigned long long seed = (threadIdx.x + blockDim.x * blockIdx.x) + (threadIdx.y + blockDim.y * blockIdx.y) * (randseed % 1000);
//init curand
hiprand_init(seed, 0, 0, &state);
if (inCircle(&state))
{
atomicAdd(&result[threadIdx.x * HEIGHT + threadIdx.y], 1);
}
return;
}
int main()
{
const size_t size = WIDTH * HEIGHT;
int count [size];
memset(&count, 0, size * sizeof(int));
int* dev_count;
hipMalloc((void**)&dev_count, size * sizeof(int));
// starting the timer here so that we include the cost of
// all of the operations on the GPU.
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
//use un_ptr, that don`t forget free memory
defer _(nullptr, [&](...)
{ hipFree(dev_count); hipEventDestroy(start); hipEventDestroy(stop); printf("free"); });
dim3 blocks(hBLOCKS, wBLOCKS, 1);
dim3 threads(HEIGHT, WIDTH, 1);
int randseed = std::chrono::duration_cast<std::chrono::milliseconds>
(std::chrono::system_clock::now().time_since_epoch()).count();
CalculatePointsIntheCircle <<<blocks, threads >>> (dev_count, randseed);
hipMemcpy(&count, dev_count, size * sizeof(int), hipMemcpyDeviceToHost);
// result pi
int ans = 0;
ans = std::accumulate(&count[0], &count[size - 1], ans);
float fullsize = static_cast<float>(HEIGHT * WIDTH * hBLOCKS * wBLOCKS);
float pi = (4.0f * static_cast<float>(ans));
pi /= fullsize;
printf("Result pi %f \n", pi);
//print elapsed time
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
printf( "Elapsed time %3.1f ms\n", elapsedTime );
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "hiprand/hiprand_kernel.h"
#include <memory>
#include <ctime>
#include <stdio.h>
#include <stdlib.h>
#include <chrono>
#include <algorithm>
#include <numeric>
using defer = std::shared_ptr<void>;
#define HEIGHT 32
#define WIDTH 32
#define hBLOCKS 6
#define wBLOCKS 6
//return resurl of this expression (x*x + y*y <= 1)
__device__ bool inCircle(hiprandState_t* state)
{
float x = hiprand_uniform(state);
float y = hiprand_uniform(state);
return x * x + y * y <= 1.0f;
}
__global__ void CalculatePointsIntheCircle(int* result, int randseed)
{
hiprandState_t state;
unsigned long long seed = (threadIdx.x + blockDim.x * blockIdx.x) + (threadIdx.y + blockDim.y * blockIdx.y) * (randseed % 1000);
//init curand
hiprand_init(seed, 0, 0, &state);
if (inCircle(&state))
{
atomicAdd(&result[threadIdx.x * HEIGHT + threadIdx.y], 1);
}
return;
}
int main()
{
const size_t size = WIDTH * HEIGHT;
int count [size];
memset(&count, 0, size * sizeof(int));
int* dev_count;
hipMalloc((void**)&dev_count, size * sizeof(int));
// starting the timer here so that we include the cost of
// all of the operations on the GPU.
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
//use un_ptr, that don`t forget free memory
defer _(nullptr, [&](...)
{ hipFree(dev_count); hipEventDestroy(start); hipEventDestroy(stop); printf("free"); });
dim3 blocks(hBLOCKS, wBLOCKS, 1);
dim3 threads(HEIGHT, WIDTH, 1);
int randseed = std::chrono::duration_cast<std::chrono::milliseconds>
(std::chrono::system_clock::now().time_since_epoch()).count();
CalculatePointsIntheCircle <<<blocks, threads >>> (dev_count, randseed);
hipMemcpy(&count, dev_count, size * sizeof(int), hipMemcpyDeviceToHost);
// result pi
int ans = 0;
ans = std::accumulate(&count[0], &count[size - 1], ans);
float fullsize = static_cast<float>(HEIGHT * WIDTH * hBLOCKS * wBLOCKS);
float pi = (4.0f * static_cast<float>(ans));
pi /= fullsize;
printf("Result pi %f \n", pi);
//print elapsed time
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
printf( "Elapsed time %3.1f ms\n", elapsedTime );
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26CalculatePointsIntheCirclePii
.globl _Z26CalculatePointsIntheCirclePii
.p2align 8
.type _Z26CalculatePointsIntheCirclePii,@function
_Z26CalculatePointsIntheCirclePii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_mul_hi_i32 s5, s3, 0x10624dd3
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_lshr_b32 s4, s5, 31
s_ashr_i32 s5, s5, 6
s_and_b32 s2, s2, 0xffff
s_add_i32 s4, s5, s4
s_mul_i32 s14, s14, s2
s_mulk_i32 s4, 0x3e8
s_mov_b32 s2, exec_lo
s_sub_i32 s3, s3, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v2, s3
v_add3_u32 v2, s14, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v2, 0x2c7f967f, v2
v_mul_lo_u32 v2, v2, 0x493c4aa1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v3, 0x75bcd15, v2
v_add_nc_u32_e32 v5, 0x583f19, v2
v_xor_b32_e32 v7, 0x159a55e5, v2
v_lshrrev_b32_e32 v4, 2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_xor_b32_e32 v3, v4, v3
v_lshlrev_b32_e32 v4, 4, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v6, 1, v3
v_xor_b32_e32 v4, v4, v6
v_lshrrev_b32_e32 v6, 2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor3_b32 v3, v4, v5, v3
v_xor_b32_e32 v4, v6, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v5, 4, v3
v_lshlrev_b32_e32 v6, 1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v5, v6, v5
v_xor3_b32 v4, v5, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add3_u32 v4, v2, v4, 0x8acd61a2
v_add3_u32 v2, v2, v3, 0x8ac7d9dd
v_cvt_f32_u32_e32 v3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v2, v2
v_dual_fmaak_f32 v3, 0x2f800000, v3, 0x2f800000 :: v_dual_fmaak_f32 v2, 0x2f800000, v2, 0x2f800000
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v3, v3, v3
v_fmac_f32_e32 v3, v2, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ge_f32_e32 1.0, v3
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 5, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_lshl_u32 v0, v0, v1, 2
v_mov_b32_e32 v1, 1
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26CalculatePointsIntheCirclePii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26CalculatePointsIntheCirclePii, .Lfunc_end0-_Z26CalculatePointsIntheCirclePii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26CalculatePointsIntheCirclePii
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z26CalculatePointsIntheCirclePii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "hiprand/hiprand_kernel.h"
#include <memory>
#include <ctime>
#include <stdio.h>
#include <stdlib.h>
#include <chrono>
#include <algorithm>
#include <numeric>
using defer = std::shared_ptr<void>;
#define HEIGHT 32
#define WIDTH 32
#define hBLOCKS 6
#define wBLOCKS 6
//return resurl of this expression (x*x + y*y <= 1)
__device__ bool inCircle(hiprandState_t* state)
{
float x = hiprand_uniform(state);
float y = hiprand_uniform(state);
return x * x + y * y <= 1.0f;
}
__global__ void CalculatePointsIntheCircle(int* result, int randseed)
{
hiprandState_t state;
unsigned long long seed = (threadIdx.x + blockDim.x * blockIdx.x) + (threadIdx.y + blockDim.y * blockIdx.y) * (randseed % 1000);
//init curand
hiprand_init(seed, 0, 0, &state);
if (inCircle(&state))
{
atomicAdd(&result[threadIdx.x * HEIGHT + threadIdx.y], 1);
}
return;
}
int main()
{
const size_t size = WIDTH * HEIGHT;
int count [size];
memset(&count, 0, size * sizeof(int));
int* dev_count;
hipMalloc((void**)&dev_count, size * sizeof(int));
// starting the timer here so that we include the cost of
// all of the operations on the GPU.
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
//use un_ptr, that don`t forget free memory
defer _(nullptr, [&](...)
{ hipFree(dev_count); hipEventDestroy(start); hipEventDestroy(stop); printf("free"); });
dim3 blocks(hBLOCKS, wBLOCKS, 1);
dim3 threads(HEIGHT, WIDTH, 1);
int randseed = std::chrono::duration_cast<std::chrono::milliseconds>
(std::chrono::system_clock::now().time_since_epoch()).count();
CalculatePointsIntheCircle <<<blocks, threads >>> (dev_count, randseed);
hipMemcpy(&count, dev_count, size * sizeof(int), hipMemcpyDeviceToHost);
// result pi
int ans = 0;
ans = std::accumulate(&count[0], &count[size - 1], ans);
float fullsize = static_cast<float>(HEIGHT * WIDTH * hBLOCKS * wBLOCKS);
float pi = (4.0f * static_cast<float>(ans));
pi /= fullsize;
printf("Result pi %f \n", pi);
//print elapsed time
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
printf( "Elapsed time %3.1f ms\n", elapsedTime );
return 0;
} | .text
.file "kernel.hip"
.globl _Z41__device_stub__CalculatePointsIntheCirclePii # -- Begin function _Z41__device_stub__CalculatePointsIntheCirclePii
.p2align 4, 0x90
.type _Z41__device_stub__CalculatePointsIntheCirclePii,@function
_Z41__device_stub__CalculatePointsIntheCirclePii: # @_Z41__device_stub__CalculatePointsIntheCirclePii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z26CalculatePointsIntheCirclePii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z41__device_stub__CalculatePointsIntheCirclePii, .Lfunc_end0-_Z41__device_stub__CalculatePointsIntheCirclePii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x40800000 # float 4
.LCPI1_1:
.long 0x47100000 # float 36864
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $4224, %rsp # imm = 0x1080
.cfi_def_cfa_offset 4256
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
.cfi_escape 0x2e, 0x00
leaq 128(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
xorl %esi, %esi
callq memset@PLT
.cfi_escape 0x2e, 0x00
leaq 48(%rsp), %rbx
movl $4096, %esi # imm = 0x1000
movq %rbx, %rdi
callq hipMalloc
.cfi_escape 0x2e, 0x00
leaq 40(%rsp), %r14
movq %r14, %rdi
callq hipEventCreate
.cfi_escape 0x2e, 0x00
movq %rsp, %r15
movq %r15, %rdi
callq hipEventCreate
movq 40(%rsp), %rdi
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
xorps %xmm0, %xmm0
movups %xmm0, 56(%rsp)
movq %rbx, 16(%rsp)
movq %r14, 24(%rsp)
movq %r15, 32(%rsp)
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $48, %edi
callq _Znwm
.Ltmp1:
# %bb.1: # %_ZNSt10shared_ptrIvEC2IZ4mainEUlzE_EEDnT_.exit
movq %rbx, 16(%rax)
movq %r14, 24(%rax)
movq %r15, 32(%rax)
movabsq $4294967297, %r14 # imm = 0x100000001
movq %r14, 8(%rax)
movq $_ZTVSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE+16, (%rax)
movq $0, 40(%rax)
movq %rax, 64(%rsp)
.cfi_escape 0x2e, 0x00
callq _ZNSt6chrono3_V212system_clock3nowEv
movabsq $4835703278458516699, %rcx # imm = 0x431BDE82D7B634DB
imulq %rcx
movq %rdx, %rbx
.Ltmp11:
.cfi_escape 0x2e, 0x00
movabsq $25769803782, %rdi # imm = 0x600000006
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp12:
# %bb.2:
testl %eax, %eax
jne .LBB1_5
# %bb.3:
movq %rbx, %rax
shrq $63, %rax
shrq $18, %rbx
addl %eax, %ebx
movq 48(%rsp), %rax
movq %rax, 120(%rsp)
movl %ebx, 12(%rsp)
leaq 120(%rsp), %rax
movq %rax, 16(%rsp)
leaq 12(%rsp), %rax
movq %rax, 24(%rsp)
.Ltmp13:
.cfi_escape 0x2e, 0x00
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp14:
# %bb.4: # %.noexc
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
.Ltmp15:
.cfi_escape 0x2e, 0x10
leaq 16(%rsp), %r9
movl $_Z26CalculatePointsIntheCirclePii, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp16:
.LBB1_5:
movq 48(%rsp), %rsi
.Ltmp17:
.cfi_escape 0x2e, 0x00
leaq 128(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movl $2, %ecx
callq hipMemcpy
.Ltmp18:
# %bb.6: # %.lr.ph.i.preheader
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_7: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
addl 128(%rsp,%rcx), %eax
addq $4, %rcx
cmpq $4092, %rcx # imm = 0xFFC
jne .LBB1_7
# %bb.8: # %_ZSt10accumulateIPiiET0_T_S2_S1_.exit
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
divss .LCPI1_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movl $.L.str, %edi
movb $1, %al
callq printf
movq (%rsp), %rdi
.Ltmp20:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp21:
# %bb.9:
movq (%rsp), %rdi
.Ltmp22:
.cfi_escape 0x2e, 0x00
callq hipEventSynchronize
.Ltmp23:
# %bb.10:
movq 40(%rsp), %rsi
movq (%rsp), %rdx
.Ltmp25:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
callq hipEventElapsedTime
.Ltmp26:
# %bb.11:
movss 16(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 64(%rsp), %rbx
testq %rbx, %rbx
je .LBB1_26
# %bb.12:
movq 8(%rbx), %rax
cmpq %r14, %rax
jne .LBB1_21
# %bb.13:
movq $0, 8(%rbx)
movq (%rbx), %rax
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq *16(%rax)
movq (%rbx), %rax
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq *24(%rax)
jmp .LBB1_26
.LBB1_21:
cmpb $0, __libc_single_threaded(%rip)
je .LBB1_23
# %bb.22:
movl 8(%rbx), %eax
leal -1(%rax), %ecx
movl %ecx, 8(%rbx)
cmpl $1, %eax
je .LBB1_25
.LBB1_26: # %_ZNSt12__shared_ptrIvLN9__gnu_cxx12_Lock_policyE2EED2Ev.exit
xorl %eax, %eax
addq $4224, %rsp # imm = 0x1080
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_23:
.cfi_def_cfa_offset 4256
movl $-1, %eax
lock xaddl %eax, 8(%rbx)
cmpl $1, %eax
jne .LBB1_26
.LBB1_25:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv
jmp .LBB1_26
.LBB1_28:
.Ltmp27:
jmp .LBB1_29
.LBB1_14:
.Ltmp2:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq __cxa_begin_catch
.Ltmp3:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
callq _ZZ4mainENKUlzE_clEz
.Ltmp4:
# %bb.15:
.Ltmp5:
.cfi_escape 0x2e, 0x00
callq __cxa_rethrow
.Ltmp6:
# %bb.19:
.LBB1_16:
.Ltmp7:
movq %rax, %rbx
.Ltmp8:
.cfi_escape 0x2e, 0x00
callq __cxa_end_catch
.Ltmp9:
# %bb.17: # %common.resume
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.LBB1_18:
.Ltmp10:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq __clang_call_terminate
.LBB1_27:
.Ltmp24:
jmp .LBB1_29
.LBB1_20:
.Ltmp19:
.LBB1_29:
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
leaq 56(%rsp), %rdi
callq _ZNSt12__shared_ptrIvLN9__gnu_cxx12_Lock_policyE2EED2Ev
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase0-.Lttbaseref0
.Lttbaseref0:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 1 # On action: 1
.uleb128 .Ltmp11-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp18-.Ltmp11 # Call between .Ltmp11 and .Ltmp18
.uleb128 .Ltmp19-.Lfunc_begin0 # jumps to .Ltmp19
.byte 0 # On action: cleanup
.uleb128 .Ltmp20-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp23-.Ltmp20 # Call between .Ltmp20 and .Ltmp23
.uleb128 .Ltmp24-.Lfunc_begin0 # jumps to .Ltmp24
.byte 0 # On action: cleanup
.uleb128 .Ltmp25-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp26-.Ltmp25 # Call between .Ltmp25 and .Ltmp26
.uleb128 .Ltmp27-.Lfunc_begin0 # jumps to .Ltmp27
.byte 0 # On action: cleanup
.uleb128 .Ltmp26-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp3-.Ltmp26 # Call between .Ltmp26 and .Ltmp3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp6-.Ltmp3 # Call between .Ltmp3 and .Ltmp6
.uleb128 .Ltmp7-.Lfunc_begin0 # jumps to .Ltmp7
.byte 0 # On action: cleanup
.uleb128 .Ltmp8-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp9-.Ltmp8 # Call between .Ltmp8 and .Ltmp9
.uleb128 .Ltmp10-.Lfunc_begin0 # jumps to .Ltmp10
.byte 1 # On action: 1
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Lfunc_end1-.Ltmp9 # Call between .Ltmp9 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.byte 1 # >> Action Record 1 <<
# Catch TypeInfo 1
.byte 0 # No further actions
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long 0 # TypeInfo 1
.Lttbase0:
.p2align 2, 0x0
# -- End function
.section .text._ZNSt12__shared_ptrIvLN9__gnu_cxx12_Lock_policyE2EED2Ev,"axG",@progbits,_ZNSt12__shared_ptrIvLN9__gnu_cxx12_Lock_policyE2EED2Ev,comdat
.weak _ZNSt12__shared_ptrIvLN9__gnu_cxx12_Lock_policyE2EED2Ev # -- Begin function _ZNSt12__shared_ptrIvLN9__gnu_cxx12_Lock_policyE2EED2Ev
.p2align 4, 0x90
.type _ZNSt12__shared_ptrIvLN9__gnu_cxx12_Lock_policyE2EED2Ev,@function
_ZNSt12__shared_ptrIvLN9__gnu_cxx12_Lock_policyE2EED2Ev: # @_ZNSt12__shared_ptrIvLN9__gnu_cxx12_Lock_policyE2EED2Ev
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq 8(%rdi), %rbx
testq %rbx, %rbx
je .LBB2_6
# %bb.1:
movq 8(%rbx), %rax
movabsq $4294967297, %rcx # imm = 0x100000001
cmpq %rcx, %rax
jne .LBB2_2
# %bb.7:
movq $0, 8(%rbx)
movq (%rbx), %rax
movq %rbx, %rdi
callq *16(%rax)
movq (%rbx), %rax
movq %rbx, %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmpq *24(%rax) # TAILCALL
.LBB2_2:
.cfi_def_cfa_offset 16
cmpb $0, __libc_single_threaded(%rip)
je .LBB2_4
# %bb.3:
movl 8(%rbx), %eax
leal -1(%rax), %ecx
movl %ecx, 8(%rbx)
cmpl $1, %eax
je .LBB2_8
.LBB2_6: # %_ZNSt14__shared_countILN9__gnu_cxx12_Lock_policyE2EED2Ev.exit
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB2_4:
.cfi_def_cfa_offset 16
movl $-1, %eax
lock xaddl %eax, 8(%rbx)
cmpl $1, %eax
jne .LBB2_6
.LBB2_8:
movq %rbx, %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv # TAILCALL
.Lfunc_end2:
.size _ZNSt12__shared_ptrIvLN9__gnu_cxx12_Lock_policyE2EED2Ev, .Lfunc_end2-_ZNSt12__shared_ptrIvLN9__gnu_cxx12_Lock_policyE2EED2Ev
.cfi_endproc
# -- End function
.section .text.__clang_call_terminate,"axG",@progbits,__clang_call_terminate,comdat
.hidden __clang_call_terminate # -- Begin function __clang_call_terminate
.weak __clang_call_terminate
.p2align 4, 0x90
.type __clang_call_terminate,@function
__clang_call_terminate: # @__clang_call_terminate
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq __cxa_begin_catch
callq _ZSt9terminatev
.Lfunc_end3:
.size __clang_call_terminate, .Lfunc_end3-__clang_call_terminate
.cfi_endproc
# -- End function
.section .text._ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv,"axG",@progbits,_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv,comdat
.weak _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv # -- Begin function _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv
.p2align 4, 0x90
.type _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv,@function
_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv: # @_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq (%rdi), %rax
callq *16(%rax)
cmpb $0, __libc_single_threaded(%rip)
je .LBB4_2
# %bb.1:
movl 12(%rbx), %eax
leal -1(%rax), %ecx
movl %ecx, 12(%rbx)
cmpl $1, %eax
jne .LBB4_4
.LBB4_5:
movq (%rbx), %rax
movq %rbx, %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmpq *24(%rax) # TAILCALL
.LBB4_2:
.cfi_def_cfa_offset 16
movl $-1, %eax
lock xaddl %eax, 12(%rbx)
cmpl $1, %eax
je .LBB4_5
.LBB4_4: # %_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE19_M_release_last_useEv.exit
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv, .Lfunc_end4-_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function _ZZ4mainENKUlzE_clEz
.type _ZZ4mainENKUlzE_clEz,@function
_ZZ4mainENKUlzE_clEz: # @_ZZ4mainENKUlzE_clEz
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq (%rdi), %rax
movq (%rax), %rdi
callq hipFree
movq 8(%rbx), %rax
movq (%rax), %rdi
callq hipEventDestroy
movq 16(%rbx), %rax
movq (%rax), %rdi
callq hipEventDestroy
movl $.L.str.2, %edi
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.Lfunc_end5:
.size _ZZ4mainENKUlzE_clEz, .Lfunc_end5-_ZZ4mainENKUlzE_clEz
.cfi_endproc
# -- End function
.section .text._ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED2Ev,"axG",@progbits,_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED2Ev,comdat
.weak _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED2Ev # -- Begin function _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED2Ev
.p2align 4, 0x90
.type _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED2Ev,@function
_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED2Ev: # @_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED2Ev
.cfi_startproc
# %bb.0:
retq
.Lfunc_end6:
.size _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED2Ev, .Lfunc_end6-_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED2Ev
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function _ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev
.type _ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev,@function
_ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev: # @_ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev
.cfi_startproc
# %bb.0:
jmp _ZdlPv # TAILCALL
.Lfunc_end7:
.size _ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev, .Lfunc_end7-_ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv
.type _ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv,@function
_ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv: # @_ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq 16(%rdi), %rax
movq (%rax), %rdi
.Ltmp28:
callq hipFree
.Ltmp29:
# %bb.1: # %.noexc
movq 24(%rbx), %rax
movq (%rax), %rdi
.Ltmp30:
callq hipEventDestroy
.Ltmp31:
# %bb.2: # %.noexc1
movq 32(%rbx), %rax
movq (%rax), %rdi
.Ltmp32:
callq hipEventDestroy
.Ltmp33:
# %bb.3: # %_ZZ4mainENKUlzE_clEz.exit
movl $.L.str.2, %edi
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.LBB8_4:
.cfi_def_cfa_offset 16
.Ltmp34:
movq %rax, %rdi
callq __clang_call_terminate
.Lfunc_end8:
.size _ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv, .Lfunc_end8-_ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table8:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase1-.Lttbaseref1
.Lttbaseref1:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Ltmp28-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp33-.Ltmp28 # Call between .Ltmp28 and .Ltmp33
.uleb128 .Ltmp34-.Lfunc_begin1 # jumps to .Ltmp34
.byte 1 # On action: 1
.Lcst_end1:
.byte 1 # >> Action Record 1 <<
# Catch TypeInfo 1
.byte 0 # No further actions
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long 0 # TypeInfo 1
.Lttbase1:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function _ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv
.type _ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv,@function
_ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv: # @_ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv
.cfi_startproc
# %bb.0: # %_ZNSt15__allocated_ptrISaISt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EEEED2Ev.exit
jmp _ZdlPv # TAILCALL
.Lfunc_end9:
.size _ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv, .Lfunc_end9-_ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info
.type _ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info,@function
_ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info: # @_ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info
.cfi_startproc
# %bb.0:
movq 8(%rsi), %rax
cmpq $_ZTSZ4mainEUlzE_, %rax
je .LBB10_1
# %bb.2:
cmpb $42, (%rax)
jne .LBB10_4
# %bb.3:
xorl %ecx, %ecx
jmp .LBB10_5
.LBB10_1:
movb $1, %cl
jmp .LBB10_5
.LBB10_4:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl $_ZTSZ4mainEUlzE_, %esi
movq %rdi, %rbx
movq %rax, %rdi
callq strcmp
movq %rbx, %rdi
testl %eax, %eax
sete %cl
popq %rbx
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.LBB10_5: # %_ZNKSt9type_infoeqERKS_.exit
addq $16, %rdi
xorl %eax, %eax
testb %cl, %cl
cmovneq %rdi, %rax
retq
.Lfunc_end10:
.size _ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info, .Lfunc_end10-_ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info
.cfi_endproc
# -- End function
.section .text._ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED0Ev,"axG",@progbits,_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED0Ev,comdat
.weak _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED0Ev # -- Begin function _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED0Ev
.p2align 4, 0x90
.type _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED0Ev,@function
_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED0Ev: # @_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED0Ev
.cfi_startproc
# %bb.0:
ud2
.Lfunc_end11:
.size _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED0Ev, .Lfunc_end11-_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED0Ev
.cfi_endproc
# -- End function
.section .text._ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv,"axG",@progbits,_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv,comdat
.weak _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv # -- Begin function _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv
.p2align 4, 0x90
.type _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv,@function
_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv: # @_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv
.cfi_startproc
# %bb.0:
movq (%rdi), %rax
jmpq *8(%rax) # TAILCALL
.Lfunc_end12:
.size _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv, .Lfunc_end12-_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB13_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB13_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26CalculatePointsIntheCirclePii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end13:
.size __hip_module_ctor, .Lfunc_end13-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB14_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB14_2:
retq
.Lfunc_end14:
.size __hip_module_dtor, .Lfunc_end14-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26CalculatePointsIntheCirclePii,@object # @_Z26CalculatePointsIntheCirclePii
.section .rodata,"a",@progbits
.globl _Z26CalculatePointsIntheCirclePii
.p2align 3, 0x0
_Z26CalculatePointsIntheCirclePii:
.quad _Z41__device_stub__CalculatePointsIntheCirclePii
.size _Z26CalculatePointsIntheCirclePii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Result pi %f \n"
.size .L.str, 15
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Elapsed time %3.1f ms\n"
.size .L.str.1, 23
.type _ZTVSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE,@object # @_ZTVSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE
.section .rodata,"a",@progbits
.p2align 3, 0x0
_ZTVSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE:
.quad 0
.quad _ZTISt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE
.quad _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED2Ev
.quad _ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev
.quad _ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv
.quad _ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv
.quad _ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info
.size _ZTVSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE, 56
.type _ZTSSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE,@object # @_ZTSSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE
_ZTSSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE:
.asciz "St19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE"
.size _ZTSSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE, 74
.type _ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE,@object # @_ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE
.section .rodata._ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE,"aG",@progbits,_ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE,comdat
.weak _ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE
_ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE:
.asciz "St16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE"
.size _ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE, 52
.type _ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE,@object # @_ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE
.section .rodata._ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE,"aG",@progbits,_ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE,comdat
.weak _ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE
_ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE:
.asciz "St11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE"
.size _ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE, 47
.type _ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE,@object # @_ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE
.section .rodata._ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE,"aG",@progbits,_ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE,comdat
.weak _ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE
.p2align 3, 0x0
_ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE:
.quad _ZTVN10__cxxabiv117__class_type_infoE+16
.quad _ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE
.size _ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE, 16
.type _ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE,@object # @_ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE
.section .rodata._ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE,"aG",@progbits,_ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE,comdat
.weak _ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE
.p2align 3, 0x0
_ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE
.quad _ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE
.size _ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE, 24
.type _ZTISt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE,@object # @_ZTISt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE
.section .rodata,"a",@progbits
.p2align 3, 0x0
_ZTISt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTSSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE
.quad _ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE
.size _ZTISt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE, 24
.type _ZTVSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE,@object # @_ZTVSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE
.section .rodata._ZTVSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE,"aG",@progbits,_ZTVSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE,comdat
.weak _ZTVSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE
.p2align 3, 0x0
_ZTVSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE:
.quad 0
.quad _ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE
.quad _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED2Ev
.quad _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EED0Ev
.quad __cxa_pure_virtual
.quad _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv
.quad __cxa_pure_virtual
.size _ZTVSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE, 56
.type _ZTSZ4mainEUlzE_,@object # @_ZTSZ4mainEUlzE_
.section .rodata,"a",@progbits
_ZTSZ4mainEUlzE_:
.asciz "Z4mainEUlzE_"
.size _ZTSZ4mainEUlzE_, 13
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "free"
.size .L.str.2, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z26CalculatePointsIntheCirclePii"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__CalculatePointsIntheCirclePii
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z26CalculatePointsIntheCirclePii
.addrsig_sym _ZTVN10__cxxabiv120__si_class_type_infoE
.addrsig_sym _ZTSSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE
.addrsig_sym _ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE
.addrsig_sym _ZTVN10__cxxabiv117__class_type_infoE
.addrsig_sym _ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE
.addrsig_sym _ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE
.addrsig_sym _ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE
.addrsig_sym _ZTISt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE
.addrsig_sym _ZTSZ4mainEUlzE_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z26CalculatePointsIntheCirclePii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIMAD.WIDE UR4, UR6, 0x10624dd3, URZ ; /* 0x10624dd3060478a5 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e260000002500 */
/*0050*/ USHF.R.U32.HI UR4, URZ, 0x1f, UR5 ; /* 0x0000001f3f047899 */
/* 0x000fe20008011605 */
/*0060*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e660000002600 */
/*0070*/ ULEA.HI.SX32 UR4, UR5, UR4, 0x1a ; /* 0x0000000405047291 */
/* 0x000fe2000f8fd23f */
/*0080*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e660000002200 */
/*0090*/ UIMAD UR4, UR4, -0x3e8, UR6 ; /* 0xfffffc18040478a4 */
/* 0x000fe2000f8e0206 */
/*00a0*/ IMAD R2, R5, c[0x0][0x0], R0 ; /* 0x0000000005027a24 */
/* 0x001fc400078e0200 */
/*00b0*/ IMAD R5, R4, c[0x0][0x4], R3 ; /* 0x0000010004057a24 */
/* 0x002fc800078e0203 */
/*00c0*/ IMAD R2, R5, UR4, R2 ; /* 0x0000000405027c24 */
/* 0x000fca000f8e0202 */
/*00d0*/ LOP3.LUT R2, R2, 0xaad26b49, RZ, 0x3c, !PT ; /* 0xaad26b4902027812 */
/* 0x000fca00078e3cff */
/*00e0*/ IMAD R2, R2, 0x4182bed5, RZ ; /* 0x4182bed502027824 */
/* 0x000fca00078e02ff */
/*00f0*/ IADD3 R4, R2.reuse, 0x75bcd15, RZ ; /* 0x075bcd1502047810 */
/* 0x040fe40007ffe0ff */
/*0100*/ LOP3.LUT R5, R2.reuse, 0x159a55e5, RZ, 0x3c, !PT ; /* 0x159a55e502057812 */
/* 0x040fe400078e3cff */
/*0110*/ IADD3 R6, R2, 0x583f19, RZ ; /* 0x00583f1902067810 */
/* 0x000fe40007ffe0ff */
/*0120*/ SHF.R.U32.HI R7, RZ, 0x2, R4 ; /* 0x00000002ff077819 */
/* 0x000fe40000011604 */
/*0130*/ SHF.R.U32.HI R9, RZ, 0x2, R5 ; /* 0x00000002ff097819 */
/* 0x000fe20000011605 */
/*0140*/ IMAD.SHL.U32 R5, R6, 0x10, RZ ; /* 0x0000001006057824 */
/* 0x000fe200078e00ff */
/*0150*/ LOP3.LUT R7, R7, R4, RZ, 0x3c, !PT ; /* 0x0000000407077212 */
/* 0x000fc400078e3cff */
/*0160*/ LOP3.LUT R4, R9, 0x159a55e5, R2, 0x96, !PT ; /* 0x159a55e509047812 */
/* 0x000fe400078e9602 */
/*0170*/ LOP3.LUT R6, R7.reuse, R5, R6, 0x96, !PT ; /* 0x0000000507067212 */
/* 0x040fe200078e9606 */
/*0180*/ IMAD.SHL.U32 R7, R7, 0x2, RZ ; /* 0x0000000207077824 */
/* 0x000fe200078e00ff */
/*0190*/ SHF.L.U32 R5, R4, 0x1, RZ ; /* 0x0000000104057819 */
/* 0x000fc800000006ff */
/*01a0*/ LOP3.LUT R7, R6, R7, RZ, 0x3c, !PT ; /* 0x0000000706077212 */
/* 0x000fc800078e3cff */
/*01b0*/ LOP3.LUT R5, R7.reuse, R5, R4, 0x96, !PT ; /* 0x0000000507057212 */
/* 0x040fe200078e9604 */
/*01c0*/ IMAD.SHL.U32 R4, R7, 0x10, RZ ; /* 0x0000001007047824 */
/* 0x000fca00078e00ff */
/*01d0*/ LOP3.LUT R5, R5, R4, RZ, 0x3c, !PT ; /* 0x0000000405057212 */
/* 0x000fe200078e3cff */
/*01e0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x2f800000 ; /* 0x2f800000ff047424 */
/* 0x000fc600078e00ff */
/*01f0*/ IADD3 R5, R2.reuse, -0x25fe145e, R5 ; /* 0xda01eba202057810 */
/* 0x040fe40007ffe005 */
/*0200*/ IADD3 R2, R2, -0x26039c23, R7 ; /* 0xd9fc63dd02027810 */
/* 0x000fc80007ffe007 */
/*0210*/ I2F.U32 R5, R5 ; /* 0x0000000500057306 */
/* 0x000e300000201000 */
/*0220*/ I2F.U32 R2, R2 ; /* 0x0000000200027306 */
/* 0x000e620000201000 */
/*0230*/ FFMA R6, R5, R4, 1.1641532182693481445e-10 ; /* 0x2f00000005067423 */
/* 0x001fc80000000004 */
/*0240*/ FMUL R7, R6, R6 ; /* 0x0000000606077220 */
/* 0x000fe40000400000 */
/*0250*/ FFMA R4, R2, R4, 1.1641532182693481445e-10 ; /* 0x2f00000002047423 */
/* 0x002fc80000000004 */
/*0260*/ FFMA R7, R4, R4, R7 ; /* 0x0000000404077223 */
/* 0x000fca0000000007 */
/*0270*/ FSETP.GTU.AND P0, PT, R7, 1, PT ; /* 0x3f8000000700780b */
/* 0x000fda0003f0c000 */
/*0280*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0290*/ LEA R3, R0, R3, 0x5 ; /* 0x0000000300037211 */
/* 0x000fe200078e28ff */
/*02a0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*02b0*/ HFMA2.MMA R5, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff057435 */
/* 0x000fe200000001ff */
/*02c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*02d0*/ IMAD.WIDE.U32 R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0002 */
/*02e0*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x000fe2000c10e184 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ BRA 0x300; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26CalculatePointsIntheCirclePii
.globl _Z26CalculatePointsIntheCirclePii
.p2align 8
.type _Z26CalculatePointsIntheCirclePii,@function
_Z26CalculatePointsIntheCirclePii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_mul_hi_i32 s5, s3, 0x10624dd3
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_lshr_b32 s4, s5, 31
s_ashr_i32 s5, s5, 6
s_and_b32 s2, s2, 0xffff
s_add_i32 s4, s5, s4
s_mul_i32 s14, s14, s2
s_mulk_i32 s4, 0x3e8
s_mov_b32 s2, exec_lo
s_sub_i32 s3, s3, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v2, s3
v_add3_u32 v2, s14, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v2, 0x2c7f967f, v2
v_mul_lo_u32 v2, v2, 0x493c4aa1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v3, 0x75bcd15, v2
v_add_nc_u32_e32 v5, 0x583f19, v2
v_xor_b32_e32 v7, 0x159a55e5, v2
v_lshrrev_b32_e32 v4, 2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_xor_b32_e32 v3, v4, v3
v_lshlrev_b32_e32 v4, 4, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v6, 1, v3
v_xor_b32_e32 v4, v4, v6
v_lshrrev_b32_e32 v6, 2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor3_b32 v3, v4, v5, v3
v_xor_b32_e32 v4, v6, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v5, 4, v3
v_lshlrev_b32_e32 v6, 1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v5, v6, v5
v_xor3_b32 v4, v5, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add3_u32 v4, v2, v4, 0x8acd61a2
v_add3_u32 v2, v2, v3, 0x8ac7d9dd
v_cvt_f32_u32_e32 v3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v2, v2
v_dual_fmaak_f32 v3, 0x2f800000, v3, 0x2f800000 :: v_dual_fmaak_f32 v2, 0x2f800000, v2, 0x2f800000
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v3, v3, v3
v_fmac_f32_e32 v3, v2, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ge_f32_e32 1.0, v3
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 5, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_lshl_u32 v0, v0, v1, 2
v_mov_b32_e32 v1, 1
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26CalculatePointsIntheCirclePii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26CalculatePointsIntheCirclePii, .Lfunc_end0-_Z26CalculatePointsIntheCirclePii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26CalculatePointsIntheCirclePii
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z26CalculatePointsIntheCirclePii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void fill_bspline_4(const float4 *xyzq, const int ncoord, const float *recip, const int nfftx, const int nffty, const int nfftz, int *gix, int *giy, int *giz, float *charge, float *thetax, float *thetay, float *thetaz, float *dthetax, float *dthetay, float *dthetaz) {
// Position to xyzq and atomgrid
unsigned int pos = blockIdx.x*blockDim.x + threadIdx.x;
while (pos < ncoord) {
float4 xyzqi = xyzq[pos];
float x = xyzqi.x;
float y = xyzqi.y;
float z = xyzqi.z;
float q = xyzqi.w;
float w;
// NOTE: I don't think we need the +2.0f here..
w = x*recip[0] + y*recip[1] + z*recip[2] + 2.0f;
float frx = (float)(nfftx*(w - (floorf(w + 0.5f) - 0.5f)));
w = x*recip[3] + y*recip[4] + z*recip[5] + 2.0f;
float fry = (float)(nffty*(w - (floorf(w + 0.5f) - 0.5f)));
w = x*recip[6] + y*recip[7] + z*recip[8] + 2.0f;
float frz = (float)(nfftz*(w - (floorf(w + 0.5f) - 0.5f)));
int frxi = (int)(frx);
int fryi = (int)(fry);
int frzi = (int)(frz);
float wx = frx - (float)frxi;
float wy = fry - (float)fryi;
float wz = frz - (float)frzi;
gix[pos] = frxi;
giy[pos] = fryi;
giz[pos] = frzi;
charge[pos] = q;
float3 theta_tmp[4];
float3 dtheta_tmp[4];
theta_tmp[3].x = 0.0f;
theta_tmp[3].y = 0.0f;
theta_tmp[3].z = 0.0f;
theta_tmp[1].x = wx;
theta_tmp[1].y = wy;
theta_tmp[1].z = wz;
theta_tmp[0].x = 1.0f - wx;
theta_tmp[0].y = 1.0f - wy;
theta_tmp[0].z = 1.0f - wz;
// compute standard b-spline recursion
theta_tmp[2].x = 0.5f*wx*theta_tmp[1].x;
theta_tmp[2].y = 0.5f*wy*theta_tmp[1].y;
theta_tmp[2].z = 0.5f*wz*theta_tmp[1].z;
theta_tmp[1].x = 0.5f*((wx+1.0f)*theta_tmp[0].x + (2.0f-wx)*theta_tmp[1].x);
theta_tmp[1].y = 0.5f*((wy+1.0f)*theta_tmp[0].y + (2.0f-wy)*theta_tmp[1].y);
theta_tmp[1].z = 0.5f*((wz+1.0f)*theta_tmp[0].z + (2.0f-wz)*theta_tmp[1].z);
theta_tmp[0].x = 0.5f*(1.0f-wx)*theta_tmp[0].x;
theta_tmp[0].y = 0.5f*(1.0f-wy)*theta_tmp[0].y;
theta_tmp[0].z = 0.5f*(1.0f-wz)*theta_tmp[0].z;
// perform standard b-spline differentiationa
dtheta_tmp[0].x = -theta_tmp[0].x;
dtheta_tmp[0].y = -theta_tmp[0].y;
dtheta_tmp[0].z = -theta_tmp[0].z;
dtheta_tmp[1].x = theta_tmp[0].x - theta_tmp[1].x;
dtheta_tmp[1].y = theta_tmp[0].y - theta_tmp[1].y;
dtheta_tmp[1].z = theta_tmp[0].z - theta_tmp[1].z;
dtheta_tmp[2].x = theta_tmp[1].x - theta_tmp[2].x;
dtheta_tmp[2].y = theta_tmp[1].y - theta_tmp[2].y;
dtheta_tmp[2].z = theta_tmp[1].z - theta_tmp[2].z;
dtheta_tmp[3].x = theta_tmp[2].x - theta_tmp[3].x;
dtheta_tmp[3].y = theta_tmp[2].y - theta_tmp[3].y;
dtheta_tmp[3].z = theta_tmp[2].z - theta_tmp[3].z;
// one more recursion
theta_tmp[3].x = (1.0f/3.0f)*wx*theta_tmp[2].x;
theta_tmp[3].y = (1.0f/3.0f)*wy*theta_tmp[2].y;
theta_tmp[3].z = (1.0f/3.0f)*wz*theta_tmp[2].z;
theta_tmp[2].x = (1.0f/3.0f)*((wx+1.0f)*theta_tmp[1].x + (3.0f-wx)*theta_tmp[2].x);
theta_tmp[2].y = (1.0f/3.0f)*((wy+1.0f)*theta_tmp[1].y + (3.0f-wy)*theta_tmp[2].y);
theta_tmp[2].z = (1.0f/3.0f)*((wz+1.0f)*theta_tmp[1].z + (3.0f-wz)*theta_tmp[2].z);
theta_tmp[1].x = (1.0f/3.0f)*((wx+2.0f)*theta_tmp[0].x + (2.0f-wx)*theta_tmp[1].x);
theta_tmp[1].y = (1.0f/3.0f)*((wy+2.0f)*theta_tmp[0].y + (2.0f-wy)*theta_tmp[1].y);
theta_tmp[1].z = (1.0f/3.0f)*((wz+2.0f)*theta_tmp[0].z + (2.0f-wz)*theta_tmp[1].z);
theta_tmp[0].x = (1.0f/3.0f)*(1.0f-wx)*theta_tmp[0].x;
theta_tmp[0].y = (1.0f/3.0f)*(1.0f-wy)*theta_tmp[0].y;
theta_tmp[0].z = (1.0f/3.0f)*(1.0f-wz)*theta_tmp[0].z;
// Store theta_tmp and dtheta_tmp into global memory
int pos4 = pos*4;
thetax[pos4] = theta_tmp[0].x;
thetax[pos4+1] = theta_tmp[1].x;
thetax[pos4+2] = theta_tmp[2].x;
thetax[pos4+3] = theta_tmp[3].x;
thetay[pos4] = theta_tmp[0].y;
thetay[pos4+1] = theta_tmp[1].y;
thetay[pos4+2] = theta_tmp[2].y;
thetay[pos4+3] = theta_tmp[3].y;
thetaz[pos4] = theta_tmp[0].z;
thetaz[pos4+1] = theta_tmp[1].z;
thetaz[pos4+2] = theta_tmp[2].z;
thetaz[pos4+3] = theta_tmp[3].z;
dthetax[pos4] = dtheta_tmp[0].x;
dthetax[pos4+1] = dtheta_tmp[1].x;
dthetax[pos4+2] = dtheta_tmp[2].x;
dthetax[pos4+3] = dtheta_tmp[3].x;
dthetay[pos4] = dtheta_tmp[0].y;
dthetay[pos4+1] = dtheta_tmp[1].y;
dthetay[pos4+2] = dtheta_tmp[2].y;
dthetay[pos4+3] = dtheta_tmp[3].y;
dthetaz[pos4] = dtheta_tmp[0].z;
dthetaz[pos4+1] = dtheta_tmp[1].z;
dthetaz[pos4+2] = dtheta_tmp[2].z;
dthetaz[pos4+3] = dtheta_tmp[3].z;
pos += blockDim.x*gridDim.x;
}
} | code for sm_80
Function : _Z14fill_bspline_4PK6float4iPKfiiiPiS4_S4_PfS5_S5_S5_S5_S5_S5_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x168], PT ; /* 0x00005a0008007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ I2F R0, c[0x0][0x178] ; /* 0x00005e0000007b06 */
/* 0x000e220000201400 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fce0000000a00 */
/*0080*/ I2F R2, c[0x0][0x17c] ; /* 0x00005f0000027b06 */
/* 0x000e700000201400 */
/*0090*/ I2F R3, c[0x0][0x180] ; /* 0x0000600000037b06 */
/* 0x001ea40000201400 */
/*00a0*/ HFMA2.MMA R5, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff057435 */
/* 0x000fe200000001ff */
/*00b0*/ MOV R10, c[0x0][0x170] ; /* 0x00005c00000a7a02 */
/* 0x000fe40000000f00 */
/*00c0*/ MOV R11, c[0x0][0x174] ; /* 0x00005d00000b7a02 */
/* 0x000fca0000000f00 */
/*00d0*/ LDG.E R14, [R10.64+0x4] ; /* 0x000004040a0e7981 */
/* 0x000ee4000c1e1900 */
/*00e0*/ IMAD.WIDE.U32 R4, R8.reuse, R5, c[0x0][0x160] ; /* 0x0000580008047625 */
/* 0x040fe400078e0005 */
/*00f0*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x000f28000c1e1900 */
/*0100*/ LDG.E.128 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee8000c1e1d00 */
/*0110*/ LDG.E R16, [R10.64+0x8] ; /* 0x000008040a107981 */
/* 0x000f68000c1e1900 */
/*0120*/ LDG.E R18, [R10.64+0x10] ; /* 0x000010040a127981 */
/* 0x004ea8000c1e1900 */
/*0130*/ LDG.E R17, [R10.64+0xc] ; /* 0x00000c040a117981 */
/* 0x000ea8000c1e1900 */
/*0140*/ LDG.E R19, [R10.64+0x14] ; /* 0x000014040a137981 */
/* 0x000ea8000c1e1900 */
/*0150*/ LDG.E R12, [R10.64+0x1c] ; /* 0x00001c040a0c7981 */
/* 0x0000a8000c1e1900 */
/*0160*/ LDG.E R9, [R10.64+0x18] ; /* 0x000018040a097981 */
/* 0x0000a8000c1e1900 */
/*0170*/ LDG.E R13, [R10.64+0x20] ; /* 0x000020040a0d7981 */
/* 0x0000a2000c1e1900 */
/*0180*/ SHF.L.U32 R20, R8, 0x2, RZ ; /* 0x0000000208147819 */
/* 0x000fe200000006ff */
/*0190*/ FMUL R14, R5, R14 ; /* 0x0000000e050e7220 */
/* 0x008fc80000400000 */
/*01a0*/ FFMA R15, R4, R15, R14 ; /* 0x0000000f040f7223 */
/* 0x010fc8000000000e */
/*01b0*/ FFMA R15, R6, R16, R15 ; /* 0x00000010060f7223 */
/* 0x020fe4000000000f */
/*01c0*/ FMUL R18, R5, R18 ; /* 0x0000001205127220 */
/* 0x004fe40000400000 */
/*01d0*/ FADD R15, R15, 2 ; /* 0x400000000f0f7421 */
/* 0x000fe40000000000 */
/*01e0*/ FFMA R17, R4, R17, R18 ; /* 0x0000001104117223 */
/* 0x000fe40000000012 */
/*01f0*/ FADD R14, R15, 0.5 ; /* 0x3f0000000f0e7421 */
/* 0x000fe40000000000 */
/*0200*/ FFMA R17, R6, R19, R17 ; /* 0x0000001306117223 */
/* 0x000fc80000000011 */
/*0210*/ FRND.FLOOR R14, R14 ; /* 0x0000000e000e7307 */
/* 0x000ea20000205000 */
/*0220*/ FADD R17, R17, 2 ; /* 0x4000000011117421 */
/* 0x000fc80000000000 */
/*0230*/ FADD R11, R17, 0.5 ; /* 0x3f000000110b7421 */
/* 0x001fe40000000000 */
/*0240*/ FMUL R12, R5, R12 ; /* 0x0000000c050c7220 */
/* 0x000fc80000400000 */
/*0250*/ FRND.FLOOR R11, R11 ; /* 0x0000000b000b7307 */
/* 0x000e220000205000 */
/*0260*/ FFMA R9, R4, R9, R12 ; /* 0x0000000904097223 */
/* 0x000fe4000000000c */
/*0270*/ FADD R10, R14, -0.5 ; /* 0xbf0000000e0a7421 */
/* 0x004fc80000000000 */
/*0280*/ FADD R15, R15, -R10 ; /* 0x8000000a0f0f7221 */
/* 0x000fe40000000000 */
/*0290*/ FFMA R9, R6, R13, R9 ; /* 0x0000000d06097223 */
/* 0x000fe40000000009 */
/*02a0*/ FMUL R15, R0, R15 ; /* 0x0000000f000f7220 */
/* 0x000fe40000400000 */
/*02b0*/ FADD R9, R9, 2 ; /* 0x4000000009097421 */
/* 0x000fe40000000000 */
/*02c0*/ F2I.TRUNC.NTZ R27, R15 ; /* 0x0000000f001b7305 */
/* 0x000ea2000020f100 */
/*02d0*/ FADD R4, R11, -0.5 ; /* 0xbf0000000b047421 */
/* 0x001fe40000000000 */
/*02e0*/ FADD R10, R9, 0.5 ; /* 0x3f000000090a7421 */
/* 0x000fc40000000000 */
/*02f0*/ FADD R17, R17, -R4 ; /* 0x8000000411117221 */
/* 0x000fc80000000000 */
/*0300*/ FRND.FLOOR R10, R10 ; /* 0x0000000a000a7307 */
/* 0x000e220000205000 */
/*0310*/ FMUL R17, R2, R17 ; /* 0x0000001102117220 */
/* 0x002fce0000400000 */
/*0320*/ F2I.TRUNC.NTZ R29, R17 ; /* 0x00000011001d7305 */
/* 0x000e70000020f100 */
/*0330*/ I2F R6, R27 ; /* 0x0000001b00067306 */
/* 0x004ea20000201400 */
/*0340*/ FADD R4, R10, -0.5 ; /* 0xbf0000000a047421 */
/* 0x001fc80000000000 */
/*0350*/ FADD R4, R9, -R4 ; /* 0x8000000409047221 */
/* 0x000fc60000000000 */
/*0360*/ I2F R14, R29 ; /* 0x0000001d000e7306 */
/* 0x002e220000201400 */
/*0370*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0380*/ FADD R15, R15, -R6 ; /* 0x800000060f0f7221 */
/* 0x004fe40000000000 */
/*0390*/ FMUL R6, R3, R4 ; /* 0x0000000403067220 */
/* 0x000fc80000400000 */
/*03a0*/ F2I.TRUNC.NTZ R25, R6 ; /* 0x0000000600197305 */
/* 0x000e62000020f100 */
/*03b0*/ FADD R26, -R15, 2 ; /* 0x400000000f1a7421 */
/* 0x000fe40000000100 */
/*03c0*/ FADD R14, R17, -R14 ; /* 0x8000000e110e7221 */
/* 0x001fe40000000000 */
/*03d0*/ IMAD.WIDE.U32 R10, R8, R5, c[0x0][0x188] ; /* 0x00006200080a7625 */
/* 0x000fc800078e0005 */
/*03e0*/ FADD R23, -R15.reuse, 1 ; /* 0x3f8000000f177421 */
/* 0x040fe40000000100 */
/*03f0*/ FADD R12, R15.reuse, 1 ; /* 0x3f8000000f0c7421 */
/* 0x040fe40000000000 */
/*0400*/ FMUL R4, R15, R26 ; /* 0x0000001a0f047220 */
/* 0x000fe40000400000 */
/*0410*/ IMAD.WIDE.U32 R16, R8.reuse, R5.reuse, c[0x0][0x190] ; /* 0x0000640008107625 */
/* 0x0c0fe200078e0005 */
/*0420*/ STG.E [R10.64], R27 ; /* 0x0000001b0a007986 */
/* 0x000fe6000c101904 */
/*0430*/ IMAD.WIDE.U32 R18, R8, R5, c[0x0][0x198] ; /* 0x0000660008127625 */
/* 0x000fe200078e0005 */
/*0440*/ STG.E [R16.64], R29 ; /* 0x0000001d10007986 */
/* 0x000fe6000c101904 */
/*0450*/ FFMA R9, R23, R12, R4 ; /* 0x0000000c17097223 */
/* 0x000fe20000000004 */
/*0460*/ STG.E [R18.64], R25 ; /* 0x0000001912007986 */
/* 0x0021e2000c101904 */
/*0470*/ FMUL R4, R15, 0.5 ; /* 0x3f0000000f047820 */
/* 0x000fc40000400000 */
/*0480*/ FMUL R9, R9, 0.5 ; /* 0x3f00000009097820 */
/* 0x000fe40000400000 */
/*0490*/ FADD R24, -R14, 2 ; /* 0x400000000e187421 */
/* 0x000fe40000000100 */
/*04a0*/ FADD R28, -R15.reuse, 3 ; /* 0x404000000f1c7421 */
/* 0x040fe20000000100 */
/*04b0*/ I2F R25, R25 ; /* 0x0000001900197306 */
/* 0x001e220000201400 */
/*04c0*/ FMUL R4, R15, R4 ; /* 0x000000040f047220 */
/* 0x000fe40000400000 */
/*04d0*/ FMUL R13, R12, R9.reuse ; /* 0x000000090c0d7220 */
/* 0x080fe40000400000 */
/*04e0*/ FMUL R11, R26, R9 ; /* 0x000000091a0b7220 */
/* 0x000fc40000400000 */
/*04f0*/ FADD R21, -R14.reuse, 1 ; /* 0x3f8000000e157421 */
/* 0x040fe40000000100 */
/*0500*/ FADD R26, R14.reuse, 1 ; /* 0x3f8000000e1a7421 */
/* 0x040fe40000000000 */
/*0510*/ FMUL R10, R14, R24 ; /* 0x000000180e0a7220 */
/* 0x000fe40000400000 */
/*0520*/ FFMA R28, R4, R28, R13 ; /* 0x0000001c041c7223 */
/* 0x000fe4000000000d */
/*0530*/ IMAD.WIDE.U32 R12, R8, R5, c[0x0][0x1a0] ; /* 0x00006800080c7625 */
/* 0x000fc800078e0005 */
/*0540*/ FMUL R22, R23, 0.5 ; /* 0x3f00000017167820 */
/* 0x000fe40000400000 */
/*0550*/ FFMA R16, R21, R26, R10 ; /* 0x0000001a15107223 */
/* 0x000fe2000000000a */
/*0560*/ STG.E [R12.64], R7 ; /* 0x000000070c007986 */
/* 0x0001e2000c101904 */
/*0570*/ FADD R17, R15, 2 ; /* 0x400000000f117421 */
/* 0x000fe40000000000 */
/*0580*/ FMUL R22, R23, R22 ; /* 0x0000001617167220 */
/* 0x000fe40000400000 */
/*0590*/ FMUL R29, R15, 0.3333333432674407959 ; /* 0x3eaaaaab0f1d7820 */
/* 0x000fe40000400000 */
/*05a0*/ FMUL R27, R14, 0.5 ; /* 0x3f0000000e1b7820 */
/* 0x000fc40000400000 */
/*05b0*/ FMUL R15, R16, 0.5 ; /* 0x3f000000100f7820 */
/* 0x000fe40000400000 */
/*05c0*/ FMUL R23, R23, 0.3333333432674407959 ; /* 0x3eaaaaab17177820 */
/* 0x000fe40000400000 */
/*05d0*/ FADD R12, R6, -R25 ; /* 0x80000019060c7221 */
/* 0x001fe40000000000 */
/*05e0*/ FMUL R16, R14.reuse, R27 ; /* 0x0000001b0e107220 */
/* 0x040fe40000400000 */
/*05f0*/ FADD R19, -R14, 3 ; /* 0x404000000e137421 */
/* 0x000fe40000000100 */
/*0600*/ FMUL R26, R26, R15 ; /* 0x0000000f1a1a7220 */
/* 0x000fc40000400000 */
/*0610*/ FMUL R27, R22, R23 ; /* 0x00000017161b7220 */
/* 0x000fe40000400000 */
/*0620*/ FADD R23, -R12, 2 ; /* 0x400000000c177421 */
/* 0x000fe40000000100 */
/*0630*/ FFMA R13, R16, R19, R26 ; /* 0x00000013100d7223 */
/* 0x000fe4000000001a */
/*0640*/ FMUL R18, R21, 0.5 ; /* 0x3f00000015127820 */
/* 0x000fe40000400000 */
/*0650*/ FADD R19, -R12.reuse, 1 ; /* 0x3f8000000c137421 */
/* 0x040fe40000000100 */
/*0660*/ FADD R26, R12, 1 ; /* 0x3f8000000c1a7421 */
/* 0x000fc40000000000 */
/*0670*/ FMUL R6, R12, R23 ; /* 0x000000170c067220 */
/* 0x000fe40000400000 */
/*0680*/ FFMA R17, R22, R17, R11 ; /* 0x0000001116117223 */
/* 0x000fe4000000000b */
/*0690*/ FMUL R18, R21, R18 ; /* 0x0000001215127220 */
/* 0x000fe40000400000 */
/*06a0*/ FMUL R24, R24, R15 ; /* 0x0000000f18187220 */
/* 0x000fe40000400000 */
/*06b0*/ FADD R25, R14, 2 ; /* 0x400000000e197421 */
/* 0x000fe40000000000 */
/*06c0*/ FFMA R6, R19, R26, R6 ; /* 0x0000001a13067223 */
/* 0x000fc40000000006 */
/*06d0*/ IMAD.WIDE R10, R20, R5, c[0x0][0x1a8] ; /* 0x00006a00140a7625 */
/* 0x000fc800078e0205 */
/*06e0*/ FMUL R7, R28, 0.3333333432674407959 ; /* 0x3eaaaaab1c077820 */
/* 0x000fe40000400000 */
/*06f0*/ FMUL R28, R17, 0.3333333432674407959 ; /* 0x3eaaaaab111c7820 */
/* 0x000fe40000400000 */
/*0700*/ FFMA R25, R18, R25, R24 ; /* 0x0000001912197223 */
/* 0x000fe40000000018 */
/*0710*/ FMUL R29, R4, R29 ; /* 0x0000001d041d7220 */
/* 0x000fe40000400000 */
/*0720*/ FMUL R24, R19.reuse, 0.5 ; /* 0x3f00000013187820 */
/* 0x040fe40000400000 */
/*0730*/ FMUL R17, R6, 0.5 ; /* 0x3f00000006117820 */
/* 0x000fe20000400000 */
/*0740*/ STG.E [R10.64], R27 ; /* 0x0000001b0a007986 */
/* 0x0001e2000c101904 */
/*0750*/ FMUL R24, R19, R24 ; /* 0x0000001813187220 */
/* 0x000fc40000400000 */
/*0760*/ FMUL R23, R23, R17 ; /* 0x0000001117177220 */
/* 0x000fe20000400000 */
/*0770*/ STG.E [R10.64+0xc], R29 ; /* 0x00000c1d0a007986 */
/* 0x0003e2000c101904 */
/*0780*/ FMUL R21, R21, 0.3333333432674407959 ; /* 0x3eaaaaab15157820 */
/* 0x000fc60000400000 */
/*0790*/ STG.E [R10.64+0x8], R7 ; /* 0x000008070a007986 */
/* 0x0005e2000c101904 */
/*07a0*/ FMUL R27, R13, 0.3333333432674407959 ; /* 0x3eaaaaab0d1b7820 */
/* 0x001fc60000400000 */
/*07b0*/ STG.E [R10.64+0x4], R28 ; /* 0x0000041c0a007986 */
/* 0x0001e2000c101904 */
/*07c0*/ FADD R13, R12, 2 ; /* 0x400000000c0d7421 */
/* 0x000fe40000000000 */
/*07d0*/ FMUL R29, R18, R21 ; /* 0x00000015121d7220 */
/* 0x002fe40000400000 */
/*07e0*/ FFMA R13, R24, R13, R23 ; /* 0x0000000d180d7223 */
/* 0x000fe40000000017 */
/*07f0*/ IMAD.WIDE R6, R20, R5, c[0x0][0x1b0] ; /* 0x00006c0014067625 */
/* 0x004fc800078e0205 */
/*0800*/ FMUL R11, R12, 0.5 ; /* 0x3f0000000c0b7820 */
/* 0x001fe40000400000 */
/*0810*/ FMUL R23, R14, 0.3333333432674407959 ; /* 0x3eaaaaab0e177820 */
/* 0x000fe40000400000 */
/*0820*/ FADD R21, -R12.reuse, 3 ; /* 0x404000000c157421 */
/* 0x040fe40000000100 */
/*0830*/ FMUL R14, R12, R11 ; /* 0x0000000b0c0e7220 */
/* 0x000fe40000400000 */
/*0840*/ FMUL R26, R26, R17 ; /* 0x000000111a1a7220 */
/* 0x000fe20000400000 */
/*0850*/ STG.E [R6.64+0x8], R27 ; /* 0x0000081b06007986 */
/* 0x0001e2000c101904 */
/*0860*/ FMUL R25, R25, 0.3333333432674407959 ; /* 0x3eaaaaab19197820 */
/* 0x000fc40000400000 */
/*0870*/ FMUL R23, R16, R23 ; /* 0x0000001710177220 */
/* 0x000fe40000400000 */
/*0880*/ FFMA R21, R14, R21, R26 ; /* 0x000000150e157223 */
/* 0x000fe4000000001a */
/*0890*/ FMUL R19, R19, 0.3333333432674407959 ; /* 0x3eaaaaab13137820 */
/* 0x000fe20000400000 */
/*08a0*/ STG.E [R6.64+0x4], R25 ; /* 0x0000041906007986 */
/* 0x0003e2000c101904 */
/*08b0*/ FMUL R27, R13, 0.3333333432674407959 ; /* 0x3eaaaaab0d1b7820 */
/* 0x001fe40000400000 */
/*08c0*/ FMUL R13, R12, 0.3333333432674407959 ; /* 0x3eaaaaab0c0d7820 */
/* 0x000fe20000400000 */
/*08d0*/ STG.E [R6.64], R29 ; /* 0x0000001d06007986 */
/* 0x0001e2000c101904 */
/*08e0*/ FMUL R28, R24, R19 ; /* 0x00000013181c7220 */
/* 0x000fc40000400000 */
/*08f0*/ IMAD.WIDE R10, R20, R5, c[0x0][0x1b8] ; /* 0x00006e00140a7625 */
/* 0x000fe200078e0205 */
/*0900*/ STG.E [R6.64+0xc], R23 ; /* 0x00000c1706007986 */
/* 0x0005e6000c101904 */
/*0910*/ FMUL R25, R21, 0.3333333432674407959 ; /* 0x3eaaaaab15197820 */
/* 0x002fe40000400000 */
/*0920*/ FMUL R21, R14, R13 ; /* 0x0000000d0e157220 */
/* 0x000fe40000400000 */
/*0930*/ IMAD.WIDE R12, R20, R5, c[0x0][0x1c0] ; /* 0x00007000140c7625 */
/* 0x000fc800078e0205 */
/*0940*/ FADD R29, -R22, -RZ ; /* 0x800000ff161d7221 */
/* 0x001fe40000000100 */
/*0950*/ FADD R19, -R9, R22 ; /* 0x0000001609137221 */
/* 0x000fe40000000100 */
/*0960*/ FADD R23, -R4, R9 ; /* 0x0000000904177221 */
/* 0x004fe40000000100 */
/*0970*/ IMAD.WIDE R6, R20, R5, c[0x0][0x1c8] ; /* 0x0000720014067625 */
/* 0x000fe200078e0205 */
/*0980*/ STG.E [R10.64], R28 ; /* 0x0000001c0a007986 */
/* 0x000fe6000c101904 */
/*0990*/ FADD R9, -R15, R18 ; /* 0x000000120f097221 */
/* 0x000fe20000000100 */
/*09a0*/ STG.E [R10.64+0x4], R27 ; /* 0x0000041b0a007986 */
/* 0x0001e2000c101904 */
/*09b0*/ FADD R15, -R16, R15 ; /* 0x0000000f100f7221 */
/* 0x000fc60000000100 */
/*09c0*/ STG.E [R10.64+0x8], R25 ; /* 0x000008190a007986 */
/* 0x000fe8000c101904 */
/*09d0*/ STG.E [R10.64+0xc], R21 ; /* 0x00000c150a007986 */
/* 0x0003e8000c101904 */
/*09e0*/ STG.E [R12.64], R29 ; /* 0x0000001d0c007986 */
/* 0x000fe2000c101904 */
/*09f0*/ FADD R27, -R18, -RZ ; /* 0x800000ff121b7221 */
/* 0x001fc60000000100 */
/*0a00*/ STG.E [R12.64+0x4], R19 ; /* 0x000004130c007986 */
/* 0x000fe8000c101904 */
/*0a10*/ STG.E [R12.64+0x8], R23 ; /* 0x000008170c007986 */
/* 0x000fe2000c101904 */
/*0a20*/ IMAD.WIDE R20, R20, R5, c[0x0][0x1d0] ; /* 0x0000740014147625 */
/* 0x002fc600078e0205 */
/*0a30*/ STG.E [R12.64+0xc], R4 ; /* 0x00000c040c007986 */
/* 0x000fe2000c101904 */
/*0a40*/ FADD R5, -R17, R24 ; /* 0x0000001811057221 */
/* 0x000fe40000000100 */
/*0a50*/ FADD R11, -R24, -RZ ; /* 0x800000ff180b7221 */
/* 0x000fe20000000100 */
/*0a60*/ STG.E [R6.64+0x4], R9 ; /* 0x0000040906007986 */
/* 0x0001e2000c101904 */
/*0a70*/ FADD R17, -R14, R17 ; /* 0x000000110e117221 */
/* 0x000fc60000000100 */
/*0a80*/ STG.E [R6.64], R27 ; /* 0x0000001b06007986 */
/* 0x0003e8000c101904 */
/*0a90*/ STG.E [R6.64+0x8], R15 ; /* 0x0000080f06007986 */
/* 0x0003e2000c101904 */
/*0aa0*/ MOV R9, c[0x0][0x0] ; /* 0x0000000000097a02 */
/* 0x001fc60000000f00 */
/*0ab0*/ STG.E [R6.64+0xc], R16 ; /* 0x00000c1006007986 */
/* 0x0003e8000c101904 */
/*0ac0*/ STG.E [R20.64], R11 ; /* 0x0000000b14007986 */
/* 0x0003e2000c101904 */
/*0ad0*/ IMAD R8, R9, c[0x0][0xc], R8 ; /* 0x0000030009087a24 */
/* 0x000fc600078e0208 */
/*0ae0*/ STG.E [R20.64+0x4], R5 ; /* 0x0000040514007986 */
/* 0x0003e8000c101904 */
/*0af0*/ STG.E [R20.64+0x8], R17 ; /* 0x0000081114007986 */
/* 0x0003e8000c101904 */
/*0b00*/ STG.E [R20.64+0xc], R14 ; /* 0x00000c0e14007986 */
/* 0x0003e2000c101904 */
/*0b10*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x168], PT ; /* 0x00005a0008007a0c */
/* 0x000fda0003f06070 */
/*0b20*/ @!P0 BRA 0xa0 ; /* 0xfffff57000008947 */
/* 0x002fea000383ffff */
/*0b30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b40*/ BRA 0xb40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void fill_bspline_4(const float4 *xyzq, const int ncoord, const float *recip, const int nfftx, const int nffty, const int nfftz, int *gix, int *giy, int *giz, float *charge, float *thetax, float *thetay, float *thetaz, float *dthetax, float *dthetay, float *dthetaz) {
// Position to xyzq and atomgrid
unsigned int pos = blockIdx.x*blockDim.x + threadIdx.x;
while (pos < ncoord) {
float4 xyzqi = xyzq[pos];
float x = xyzqi.x;
float y = xyzqi.y;
float z = xyzqi.z;
float q = xyzqi.w;
float w;
// NOTE: I don't think we need the +2.0f here..
w = x*recip[0] + y*recip[1] + z*recip[2] + 2.0f;
float frx = (float)(nfftx*(w - (floorf(w + 0.5f) - 0.5f)));
w = x*recip[3] + y*recip[4] + z*recip[5] + 2.0f;
float fry = (float)(nffty*(w - (floorf(w + 0.5f) - 0.5f)));
w = x*recip[6] + y*recip[7] + z*recip[8] + 2.0f;
float frz = (float)(nfftz*(w - (floorf(w + 0.5f) - 0.5f)));
int frxi = (int)(frx);
int fryi = (int)(fry);
int frzi = (int)(frz);
float wx = frx - (float)frxi;
float wy = fry - (float)fryi;
float wz = frz - (float)frzi;
gix[pos] = frxi;
giy[pos] = fryi;
giz[pos] = frzi;
charge[pos] = q;
float3 theta_tmp[4];
float3 dtheta_tmp[4];
theta_tmp[3].x = 0.0f;
theta_tmp[3].y = 0.0f;
theta_tmp[3].z = 0.0f;
theta_tmp[1].x = wx;
theta_tmp[1].y = wy;
theta_tmp[1].z = wz;
theta_tmp[0].x = 1.0f - wx;
theta_tmp[0].y = 1.0f - wy;
theta_tmp[0].z = 1.0f - wz;
// compute standard b-spline recursion
theta_tmp[2].x = 0.5f*wx*theta_tmp[1].x;
theta_tmp[2].y = 0.5f*wy*theta_tmp[1].y;
theta_tmp[2].z = 0.5f*wz*theta_tmp[1].z;
theta_tmp[1].x = 0.5f*((wx+1.0f)*theta_tmp[0].x + (2.0f-wx)*theta_tmp[1].x);
theta_tmp[1].y = 0.5f*((wy+1.0f)*theta_tmp[0].y + (2.0f-wy)*theta_tmp[1].y);
theta_tmp[1].z = 0.5f*((wz+1.0f)*theta_tmp[0].z + (2.0f-wz)*theta_tmp[1].z);
theta_tmp[0].x = 0.5f*(1.0f-wx)*theta_tmp[0].x;
theta_tmp[0].y = 0.5f*(1.0f-wy)*theta_tmp[0].y;
theta_tmp[0].z = 0.5f*(1.0f-wz)*theta_tmp[0].z;
// perform standard b-spline differentiationa
dtheta_tmp[0].x = -theta_tmp[0].x;
dtheta_tmp[0].y = -theta_tmp[0].y;
dtheta_tmp[0].z = -theta_tmp[0].z;
dtheta_tmp[1].x = theta_tmp[0].x - theta_tmp[1].x;
dtheta_tmp[1].y = theta_tmp[0].y - theta_tmp[1].y;
dtheta_tmp[1].z = theta_tmp[0].z - theta_tmp[1].z;
dtheta_tmp[2].x = theta_tmp[1].x - theta_tmp[2].x;
dtheta_tmp[2].y = theta_tmp[1].y - theta_tmp[2].y;
dtheta_tmp[2].z = theta_tmp[1].z - theta_tmp[2].z;
dtheta_tmp[3].x = theta_tmp[2].x - theta_tmp[3].x;
dtheta_tmp[3].y = theta_tmp[2].y - theta_tmp[3].y;
dtheta_tmp[3].z = theta_tmp[2].z - theta_tmp[3].z;
// one more recursion
theta_tmp[3].x = (1.0f/3.0f)*wx*theta_tmp[2].x;
theta_tmp[3].y = (1.0f/3.0f)*wy*theta_tmp[2].y;
theta_tmp[3].z = (1.0f/3.0f)*wz*theta_tmp[2].z;
theta_tmp[2].x = (1.0f/3.0f)*((wx+1.0f)*theta_tmp[1].x + (3.0f-wx)*theta_tmp[2].x);
theta_tmp[2].y = (1.0f/3.0f)*((wy+1.0f)*theta_tmp[1].y + (3.0f-wy)*theta_tmp[2].y);
theta_tmp[2].z = (1.0f/3.0f)*((wz+1.0f)*theta_tmp[1].z + (3.0f-wz)*theta_tmp[2].z);
theta_tmp[1].x = (1.0f/3.0f)*((wx+2.0f)*theta_tmp[0].x + (2.0f-wx)*theta_tmp[1].x);
theta_tmp[1].y = (1.0f/3.0f)*((wy+2.0f)*theta_tmp[0].y + (2.0f-wy)*theta_tmp[1].y);
theta_tmp[1].z = (1.0f/3.0f)*((wz+2.0f)*theta_tmp[0].z + (2.0f-wz)*theta_tmp[1].z);
theta_tmp[0].x = (1.0f/3.0f)*(1.0f-wx)*theta_tmp[0].x;
theta_tmp[0].y = (1.0f/3.0f)*(1.0f-wy)*theta_tmp[0].y;
theta_tmp[0].z = (1.0f/3.0f)*(1.0f-wz)*theta_tmp[0].z;
// Store theta_tmp and dtheta_tmp into global memory
int pos4 = pos*4;
thetax[pos4] = theta_tmp[0].x;
thetax[pos4+1] = theta_tmp[1].x;
thetax[pos4+2] = theta_tmp[2].x;
thetax[pos4+3] = theta_tmp[3].x;
thetay[pos4] = theta_tmp[0].y;
thetay[pos4+1] = theta_tmp[1].y;
thetay[pos4+2] = theta_tmp[2].y;
thetay[pos4+3] = theta_tmp[3].y;
thetaz[pos4] = theta_tmp[0].z;
thetaz[pos4+1] = theta_tmp[1].z;
thetaz[pos4+2] = theta_tmp[2].z;
thetaz[pos4+3] = theta_tmp[3].z;
dthetax[pos4] = dtheta_tmp[0].x;
dthetax[pos4+1] = dtheta_tmp[1].x;
dthetax[pos4+2] = dtheta_tmp[2].x;
dthetax[pos4+3] = dtheta_tmp[3].x;
dthetay[pos4] = dtheta_tmp[0].y;
dthetay[pos4+1] = dtheta_tmp[1].y;
dthetay[pos4+2] = dtheta_tmp[2].y;
dthetay[pos4+3] = dtheta_tmp[3].y;
dthetaz[pos4] = dtheta_tmp[0].z;
dthetaz[pos4+1] = dtheta_tmp[1].z;
dthetaz[pos4+2] = dtheta_tmp[2].z;
dthetaz[pos4+3] = dtheta_tmp[3].z;
pos += blockDim.x*gridDim.x;
}
} | .file "tmpxft_0000f79c_00000000-6_fill_bspline_4.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z76__device_stub__Z14fill_bspline_4PK6float4iPKfiiiPiS4_S4_PfS5_S5_S5_S5_S5_S5_PK6float4iPKfiiiPiS4_S4_PfS5_S5_S5_S5_S5_S5_
.type _Z76__device_stub__Z14fill_bspline_4PK6float4iPKfiiiPiS4_S4_PfS5_S5_S5_S5_S5_S5_PK6float4iPKfiiiPiS4_S4_PfS5_S5_S5_S5_S5_S5_, @function
_Z76__device_stub__Z14fill_bspline_4PK6float4iPKfiiiPiS4_S4_PfS5_S5_S5_S5_S5_S5_PK6float4iPKfiiiPiS4_S4_PfS5_S5_S5_S5_S5_S5_:
.LFB2051:
.cfi_startproc
endbr64
subq $328, %rsp
.cfi_def_cfa_offset 336
movq %rdi, 104(%rsp)
movl %esi, 100(%rsp)
movq %rdx, 88(%rsp)
movl %ecx, 96(%rsp)
movl %r8d, 84(%rsp)
movl %r9d, 80(%rsp)
movq 336(%rsp), %rax
movq %rax, 72(%rsp)
movq 344(%rsp), %rax
movq %rax, 64(%rsp)
movq 352(%rsp), %rax
movq %rax, 56(%rsp)
movq 360(%rsp), %rax
movq %rax, 48(%rsp)
movq 368(%rsp), %rax
movq %rax, 40(%rsp)
movq 376(%rsp), %rax
movq %rax, 32(%rsp)
movq 384(%rsp), %rax
movq %rax, 24(%rsp)
movq 392(%rsp), %rax
movq %rax, 16(%rsp)
movq 400(%rsp), %rax
movq %rax, 8(%rsp)
movq 408(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 312(%rsp)
xorl %eax, %eax
leaq 104(%rsp), %rax
movq %rax, 176(%rsp)
leaq 100(%rsp), %rax
movq %rax, 184(%rsp)
leaq 88(%rsp), %rax
movq %rax, 192(%rsp)
leaq 96(%rsp), %rax
movq %rax, 200(%rsp)
leaq 84(%rsp), %rax
movq %rax, 208(%rsp)
leaq 80(%rsp), %rax
movq %rax, 216(%rsp)
leaq 72(%rsp), %rax
movq %rax, 224(%rsp)
leaq 64(%rsp), %rax
movq %rax, 232(%rsp)
leaq 56(%rsp), %rax
movq %rax, 240(%rsp)
leaq 48(%rsp), %rax
movq %rax, 248(%rsp)
leaq 40(%rsp), %rax
movq %rax, 256(%rsp)
leaq 32(%rsp), %rax
movq %rax, 264(%rsp)
leaq 24(%rsp), %rax
movq %rax, 272(%rsp)
leaq 16(%rsp), %rax
movq %rax, 280(%rsp)
leaq 8(%rsp), %rax
movq %rax, 288(%rsp)
movq %rsp, %rax
movq %rax, 296(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movl $1, 136(%rsp)
movl $1, 140(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
leaq 120(%rsp), %rcx
leaq 112(%rsp), %rdx
leaq 140(%rsp), %rsi
leaq 128(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 312(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $328, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 120(%rsp)
.cfi_def_cfa_offset 344
pushq 120(%rsp)
.cfi_def_cfa_offset 352
leaq 192(%rsp), %r9
movq 156(%rsp), %rcx
movl 164(%rsp), %r8d
movq 144(%rsp), %rsi
movl 152(%rsp), %edx
leaq _Z14fill_bspline_4PK6float4iPKfiiiPiS4_S4_PfS5_S5_S5_S5_S5_S5_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 336
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z76__device_stub__Z14fill_bspline_4PK6float4iPKfiiiPiS4_S4_PfS5_S5_S5_S5_S5_S5_PK6float4iPKfiiiPiS4_S4_PfS5_S5_S5_S5_S5_S5_, .-_Z76__device_stub__Z14fill_bspline_4PK6float4iPKfiiiPiS4_S4_PfS5_S5_S5_S5_S5_S5_PK6float4iPKfiiiPiS4_S4_PfS5_S5_S5_S5_S5_S5_
.globl _Z14fill_bspline_4PK6float4iPKfiiiPiS4_S4_PfS5_S5_S5_S5_S5_S5_
.type _Z14fill_bspline_4PK6float4iPKfiiiPiS4_S4_PfS5_S5_S5_S5_S5_S5_, @function
_Z14fill_bspline_4PK6float4iPKfiiiPiS4_S4_PfS5_S5_S5_S5_S5_S5_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 88(%rsp)
.cfi_def_cfa_offset 24
pushq 88(%rsp)
.cfi_def_cfa_offset 32
pushq 88(%rsp)
.cfi_def_cfa_offset 40
pushq 88(%rsp)
.cfi_def_cfa_offset 48
pushq 88(%rsp)
.cfi_def_cfa_offset 56
pushq 88(%rsp)
.cfi_def_cfa_offset 64
pushq 88(%rsp)
.cfi_def_cfa_offset 72
pushq 88(%rsp)
.cfi_def_cfa_offset 80
pushq 88(%rsp)
.cfi_def_cfa_offset 88
pushq 88(%rsp)
.cfi_def_cfa_offset 96
call _Z76__device_stub__Z14fill_bspline_4PK6float4iPKfiiiPiS4_S4_PfS5_S5_S5_S5_S5_S5_PK6float4iPKfiiiPiS4_S4_PfS5_S5_S5_S5_S5_S5_
addq $88, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14fill_bspline_4PK6float4iPKfiiiPiS4_S4_PfS5_S5_S5_S5_S5_S5_, .-_Z14fill_bspline_4PK6float4iPKfiiiPiS4_S4_PfS5_S5_S5_S5_S5_S5_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z14fill_bspline_4PK6float4iPKfiiiPiS4_S4_PfS5_S5_S5_S5_S5_S5_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14fill_bspline_4PK6float4iPKfiiiPiS4_S4_PfS5_S5_S5_S5_S5_S5_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void fill_bspline_4(const float4 *xyzq, const int ncoord, const float *recip, const int nfftx, const int nffty, const int nfftz, int *gix, int *giy, int *giz, float *charge, float *thetax, float *thetay, float *thetaz, float *dthetax, float *dthetay, float *dthetaz) {
// Position to xyzq and atomgrid
unsigned int pos = blockIdx.x*blockDim.x + threadIdx.x;
while (pos < ncoord) {
float4 xyzqi = xyzq[pos];
float x = xyzqi.x;
float y = xyzqi.y;
float z = xyzqi.z;
float q = xyzqi.w;
float w;
// NOTE: I don't think we need the +2.0f here..
w = x*recip[0] + y*recip[1] + z*recip[2] + 2.0f;
float frx = (float)(nfftx*(w - (floorf(w + 0.5f) - 0.5f)));
w = x*recip[3] + y*recip[4] + z*recip[5] + 2.0f;
float fry = (float)(nffty*(w - (floorf(w + 0.5f) - 0.5f)));
w = x*recip[6] + y*recip[7] + z*recip[8] + 2.0f;
float frz = (float)(nfftz*(w - (floorf(w + 0.5f) - 0.5f)));
int frxi = (int)(frx);
int fryi = (int)(fry);
int frzi = (int)(frz);
float wx = frx - (float)frxi;
float wy = fry - (float)fryi;
float wz = frz - (float)frzi;
gix[pos] = frxi;
giy[pos] = fryi;
giz[pos] = frzi;
charge[pos] = q;
float3 theta_tmp[4];
float3 dtheta_tmp[4];
theta_tmp[3].x = 0.0f;
theta_tmp[3].y = 0.0f;
theta_tmp[3].z = 0.0f;
theta_tmp[1].x = wx;
theta_tmp[1].y = wy;
theta_tmp[1].z = wz;
theta_tmp[0].x = 1.0f - wx;
theta_tmp[0].y = 1.0f - wy;
theta_tmp[0].z = 1.0f - wz;
// compute standard b-spline recursion
theta_tmp[2].x = 0.5f*wx*theta_tmp[1].x;
theta_tmp[2].y = 0.5f*wy*theta_tmp[1].y;
theta_tmp[2].z = 0.5f*wz*theta_tmp[1].z;
theta_tmp[1].x = 0.5f*((wx+1.0f)*theta_tmp[0].x + (2.0f-wx)*theta_tmp[1].x);
theta_tmp[1].y = 0.5f*((wy+1.0f)*theta_tmp[0].y + (2.0f-wy)*theta_tmp[1].y);
theta_tmp[1].z = 0.5f*((wz+1.0f)*theta_tmp[0].z + (2.0f-wz)*theta_tmp[1].z);
theta_tmp[0].x = 0.5f*(1.0f-wx)*theta_tmp[0].x;
theta_tmp[0].y = 0.5f*(1.0f-wy)*theta_tmp[0].y;
theta_tmp[0].z = 0.5f*(1.0f-wz)*theta_tmp[0].z;
// perform standard b-spline differentiationa
dtheta_tmp[0].x = -theta_tmp[0].x;
dtheta_tmp[0].y = -theta_tmp[0].y;
dtheta_tmp[0].z = -theta_tmp[0].z;
dtheta_tmp[1].x = theta_tmp[0].x - theta_tmp[1].x;
dtheta_tmp[1].y = theta_tmp[0].y - theta_tmp[1].y;
dtheta_tmp[1].z = theta_tmp[0].z - theta_tmp[1].z;
dtheta_tmp[2].x = theta_tmp[1].x - theta_tmp[2].x;
dtheta_tmp[2].y = theta_tmp[1].y - theta_tmp[2].y;
dtheta_tmp[2].z = theta_tmp[1].z - theta_tmp[2].z;
dtheta_tmp[3].x = theta_tmp[2].x - theta_tmp[3].x;
dtheta_tmp[3].y = theta_tmp[2].y - theta_tmp[3].y;
dtheta_tmp[3].z = theta_tmp[2].z - theta_tmp[3].z;
// one more recursion
theta_tmp[3].x = (1.0f/3.0f)*wx*theta_tmp[2].x;
theta_tmp[3].y = (1.0f/3.0f)*wy*theta_tmp[2].y;
theta_tmp[3].z = (1.0f/3.0f)*wz*theta_tmp[2].z;
theta_tmp[2].x = (1.0f/3.0f)*((wx+1.0f)*theta_tmp[1].x + (3.0f-wx)*theta_tmp[2].x);
theta_tmp[2].y = (1.0f/3.0f)*((wy+1.0f)*theta_tmp[1].y + (3.0f-wy)*theta_tmp[2].y);
theta_tmp[2].z = (1.0f/3.0f)*((wz+1.0f)*theta_tmp[1].z + (3.0f-wz)*theta_tmp[2].z);
theta_tmp[1].x = (1.0f/3.0f)*((wx+2.0f)*theta_tmp[0].x + (2.0f-wx)*theta_tmp[1].x);
theta_tmp[1].y = (1.0f/3.0f)*((wy+2.0f)*theta_tmp[0].y + (2.0f-wy)*theta_tmp[1].y);
theta_tmp[1].z = (1.0f/3.0f)*((wz+2.0f)*theta_tmp[0].z + (2.0f-wz)*theta_tmp[1].z);
theta_tmp[0].x = (1.0f/3.0f)*(1.0f-wx)*theta_tmp[0].x;
theta_tmp[0].y = (1.0f/3.0f)*(1.0f-wy)*theta_tmp[0].y;
theta_tmp[0].z = (1.0f/3.0f)*(1.0f-wz)*theta_tmp[0].z;
// Store theta_tmp and dtheta_tmp into global memory
int pos4 = pos*4;
thetax[pos4] = theta_tmp[0].x;
thetax[pos4+1] = theta_tmp[1].x;
thetax[pos4+2] = theta_tmp[2].x;
thetax[pos4+3] = theta_tmp[3].x;
thetay[pos4] = theta_tmp[0].y;
thetay[pos4+1] = theta_tmp[1].y;
thetay[pos4+2] = theta_tmp[2].y;
thetay[pos4+3] = theta_tmp[3].y;
thetaz[pos4] = theta_tmp[0].z;
thetaz[pos4+1] = theta_tmp[1].z;
thetaz[pos4+2] = theta_tmp[2].z;
thetaz[pos4+3] = theta_tmp[3].z;
dthetax[pos4] = dtheta_tmp[0].x;
dthetax[pos4+1] = dtheta_tmp[1].x;
dthetax[pos4+2] = dtheta_tmp[2].x;
dthetax[pos4+3] = dtheta_tmp[3].x;
dthetay[pos4] = dtheta_tmp[0].y;
dthetay[pos4+1] = dtheta_tmp[1].y;
dthetay[pos4+2] = dtheta_tmp[2].y;
dthetay[pos4+3] = dtheta_tmp[3].y;
dthetaz[pos4] = dtheta_tmp[0].z;
dthetaz[pos4+1] = dtheta_tmp[1].z;
dthetaz[pos4+2] = dtheta_tmp[2].z;
dthetaz[pos4+3] = dtheta_tmp[3].z;
pos += blockDim.x*gridDim.x;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void fill_bspline_4(const float4 *xyzq, const int ncoord, const float *recip, const int nfftx, const int nffty, const int nfftz, int *gix, int *giy, int *giz, float *charge, float *thetax, float *thetay, float *thetaz, float *dthetax, float *dthetay, float *dthetaz) {
// Position to xyzq and atomgrid
unsigned int pos = blockIdx.x*blockDim.x + threadIdx.x;
while (pos < ncoord) {
float4 xyzqi = xyzq[pos];
float x = xyzqi.x;
float y = xyzqi.y;
float z = xyzqi.z;
float q = xyzqi.w;
float w;
// NOTE: I don't think we need the +2.0f here..
w = x*recip[0] + y*recip[1] + z*recip[2] + 2.0f;
float frx = (float)(nfftx*(w - (floorf(w + 0.5f) - 0.5f)));
w = x*recip[3] + y*recip[4] + z*recip[5] + 2.0f;
float fry = (float)(nffty*(w - (floorf(w + 0.5f) - 0.5f)));
w = x*recip[6] + y*recip[7] + z*recip[8] + 2.0f;
float frz = (float)(nfftz*(w - (floorf(w + 0.5f) - 0.5f)));
int frxi = (int)(frx);
int fryi = (int)(fry);
int frzi = (int)(frz);
float wx = frx - (float)frxi;
float wy = fry - (float)fryi;
float wz = frz - (float)frzi;
gix[pos] = frxi;
giy[pos] = fryi;
giz[pos] = frzi;
charge[pos] = q;
float3 theta_tmp[4];
float3 dtheta_tmp[4];
theta_tmp[3].x = 0.0f;
theta_tmp[3].y = 0.0f;
theta_tmp[3].z = 0.0f;
theta_tmp[1].x = wx;
theta_tmp[1].y = wy;
theta_tmp[1].z = wz;
theta_tmp[0].x = 1.0f - wx;
theta_tmp[0].y = 1.0f - wy;
theta_tmp[0].z = 1.0f - wz;
// compute standard b-spline recursion
theta_tmp[2].x = 0.5f*wx*theta_tmp[1].x;
theta_tmp[2].y = 0.5f*wy*theta_tmp[1].y;
theta_tmp[2].z = 0.5f*wz*theta_tmp[1].z;
theta_tmp[1].x = 0.5f*((wx+1.0f)*theta_tmp[0].x + (2.0f-wx)*theta_tmp[1].x);
theta_tmp[1].y = 0.5f*((wy+1.0f)*theta_tmp[0].y + (2.0f-wy)*theta_tmp[1].y);
theta_tmp[1].z = 0.5f*((wz+1.0f)*theta_tmp[0].z + (2.0f-wz)*theta_tmp[1].z);
theta_tmp[0].x = 0.5f*(1.0f-wx)*theta_tmp[0].x;
theta_tmp[0].y = 0.5f*(1.0f-wy)*theta_tmp[0].y;
theta_tmp[0].z = 0.5f*(1.0f-wz)*theta_tmp[0].z;
// perform standard b-spline differentiationa
dtheta_tmp[0].x = -theta_tmp[0].x;
dtheta_tmp[0].y = -theta_tmp[0].y;
dtheta_tmp[0].z = -theta_tmp[0].z;
dtheta_tmp[1].x = theta_tmp[0].x - theta_tmp[1].x;
dtheta_tmp[1].y = theta_tmp[0].y - theta_tmp[1].y;
dtheta_tmp[1].z = theta_tmp[0].z - theta_tmp[1].z;
dtheta_tmp[2].x = theta_tmp[1].x - theta_tmp[2].x;
dtheta_tmp[2].y = theta_tmp[1].y - theta_tmp[2].y;
dtheta_tmp[2].z = theta_tmp[1].z - theta_tmp[2].z;
dtheta_tmp[3].x = theta_tmp[2].x - theta_tmp[3].x;
dtheta_tmp[3].y = theta_tmp[2].y - theta_tmp[3].y;
dtheta_tmp[3].z = theta_tmp[2].z - theta_tmp[3].z;
// one more recursion
theta_tmp[3].x = (1.0f/3.0f)*wx*theta_tmp[2].x;
theta_tmp[3].y = (1.0f/3.0f)*wy*theta_tmp[2].y;
theta_tmp[3].z = (1.0f/3.0f)*wz*theta_tmp[2].z;
theta_tmp[2].x = (1.0f/3.0f)*((wx+1.0f)*theta_tmp[1].x + (3.0f-wx)*theta_tmp[2].x);
theta_tmp[2].y = (1.0f/3.0f)*((wy+1.0f)*theta_tmp[1].y + (3.0f-wy)*theta_tmp[2].y);
theta_tmp[2].z = (1.0f/3.0f)*((wz+1.0f)*theta_tmp[1].z + (3.0f-wz)*theta_tmp[2].z);
theta_tmp[1].x = (1.0f/3.0f)*((wx+2.0f)*theta_tmp[0].x + (2.0f-wx)*theta_tmp[1].x);
theta_tmp[1].y = (1.0f/3.0f)*((wy+2.0f)*theta_tmp[0].y + (2.0f-wy)*theta_tmp[1].y);
theta_tmp[1].z = (1.0f/3.0f)*((wz+2.0f)*theta_tmp[0].z + (2.0f-wz)*theta_tmp[1].z);
theta_tmp[0].x = (1.0f/3.0f)*(1.0f-wx)*theta_tmp[0].x;
theta_tmp[0].y = (1.0f/3.0f)*(1.0f-wy)*theta_tmp[0].y;
theta_tmp[0].z = (1.0f/3.0f)*(1.0f-wz)*theta_tmp[0].z;
// Store theta_tmp and dtheta_tmp into global memory
int pos4 = pos*4;
thetax[pos4] = theta_tmp[0].x;
thetax[pos4+1] = theta_tmp[1].x;
thetax[pos4+2] = theta_tmp[2].x;
thetax[pos4+3] = theta_tmp[3].x;
thetay[pos4] = theta_tmp[0].y;
thetay[pos4+1] = theta_tmp[1].y;
thetay[pos4+2] = theta_tmp[2].y;
thetay[pos4+3] = theta_tmp[3].y;
thetaz[pos4] = theta_tmp[0].z;
thetaz[pos4+1] = theta_tmp[1].z;
thetaz[pos4+2] = theta_tmp[2].z;
thetaz[pos4+3] = theta_tmp[3].z;
dthetax[pos4] = dtheta_tmp[0].x;
dthetax[pos4+1] = dtheta_tmp[1].x;
dthetax[pos4+2] = dtheta_tmp[2].x;
dthetax[pos4+3] = dtheta_tmp[3].x;
dthetay[pos4] = dtheta_tmp[0].y;
dthetay[pos4+1] = dtheta_tmp[1].y;
dthetay[pos4+2] = dtheta_tmp[2].y;
dthetay[pos4+3] = dtheta_tmp[3].y;
dthetaz[pos4] = dtheta_tmp[0].z;
dthetaz[pos4+1] = dtheta_tmp[1].z;
dthetaz[pos4+2] = dtheta_tmp[2].z;
dthetaz[pos4+3] = dtheta_tmp[3].z;
pos += blockDim.x*gridDim.x;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void fill_bspline_4(const float4 *xyzq, const int ncoord, const float *recip, const int nfftx, const int nffty, const int nfftz, int *gix, int *giy, int *giz, float *charge, float *thetax, float *thetay, float *thetaz, float *dthetax, float *dthetay, float *dthetaz) {
// Position to xyzq and atomgrid
unsigned int pos = blockIdx.x*blockDim.x + threadIdx.x;
while (pos < ncoord) {
float4 xyzqi = xyzq[pos];
float x = xyzqi.x;
float y = xyzqi.y;
float z = xyzqi.z;
float q = xyzqi.w;
float w;
// NOTE: I don't think we need the +2.0f here..
w = x*recip[0] + y*recip[1] + z*recip[2] + 2.0f;
float frx = (float)(nfftx*(w - (floorf(w + 0.5f) - 0.5f)));
w = x*recip[3] + y*recip[4] + z*recip[5] + 2.0f;
float fry = (float)(nffty*(w - (floorf(w + 0.5f) - 0.5f)));
w = x*recip[6] + y*recip[7] + z*recip[8] + 2.0f;
float frz = (float)(nfftz*(w - (floorf(w + 0.5f) - 0.5f)));
int frxi = (int)(frx);
int fryi = (int)(fry);
int frzi = (int)(frz);
float wx = frx - (float)frxi;
float wy = fry - (float)fryi;
float wz = frz - (float)frzi;
gix[pos] = frxi;
giy[pos] = fryi;
giz[pos] = frzi;
charge[pos] = q;
float3 theta_tmp[4];
float3 dtheta_tmp[4];
theta_tmp[3].x = 0.0f;
theta_tmp[3].y = 0.0f;
theta_tmp[3].z = 0.0f;
theta_tmp[1].x = wx;
theta_tmp[1].y = wy;
theta_tmp[1].z = wz;
theta_tmp[0].x = 1.0f - wx;
theta_tmp[0].y = 1.0f - wy;
theta_tmp[0].z = 1.0f - wz;
// compute standard b-spline recursion
theta_tmp[2].x = 0.5f*wx*theta_tmp[1].x;
theta_tmp[2].y = 0.5f*wy*theta_tmp[1].y;
theta_tmp[2].z = 0.5f*wz*theta_tmp[1].z;
theta_tmp[1].x = 0.5f*((wx+1.0f)*theta_tmp[0].x + (2.0f-wx)*theta_tmp[1].x);
theta_tmp[1].y = 0.5f*((wy+1.0f)*theta_tmp[0].y + (2.0f-wy)*theta_tmp[1].y);
theta_tmp[1].z = 0.5f*((wz+1.0f)*theta_tmp[0].z + (2.0f-wz)*theta_tmp[1].z);
theta_tmp[0].x = 0.5f*(1.0f-wx)*theta_tmp[0].x;
theta_tmp[0].y = 0.5f*(1.0f-wy)*theta_tmp[0].y;
theta_tmp[0].z = 0.5f*(1.0f-wz)*theta_tmp[0].z;
// perform standard b-spline differentiationa
dtheta_tmp[0].x = -theta_tmp[0].x;
dtheta_tmp[0].y = -theta_tmp[0].y;
dtheta_tmp[0].z = -theta_tmp[0].z;
dtheta_tmp[1].x = theta_tmp[0].x - theta_tmp[1].x;
dtheta_tmp[1].y = theta_tmp[0].y - theta_tmp[1].y;
dtheta_tmp[1].z = theta_tmp[0].z - theta_tmp[1].z;
dtheta_tmp[2].x = theta_tmp[1].x - theta_tmp[2].x;
dtheta_tmp[2].y = theta_tmp[1].y - theta_tmp[2].y;
dtheta_tmp[2].z = theta_tmp[1].z - theta_tmp[2].z;
dtheta_tmp[3].x = theta_tmp[2].x - theta_tmp[3].x;
dtheta_tmp[3].y = theta_tmp[2].y - theta_tmp[3].y;
dtheta_tmp[3].z = theta_tmp[2].z - theta_tmp[3].z;
// one more recursion
theta_tmp[3].x = (1.0f/3.0f)*wx*theta_tmp[2].x;
theta_tmp[3].y = (1.0f/3.0f)*wy*theta_tmp[2].y;
theta_tmp[3].z = (1.0f/3.0f)*wz*theta_tmp[2].z;
theta_tmp[2].x = (1.0f/3.0f)*((wx+1.0f)*theta_tmp[1].x + (3.0f-wx)*theta_tmp[2].x);
theta_tmp[2].y = (1.0f/3.0f)*((wy+1.0f)*theta_tmp[1].y + (3.0f-wy)*theta_tmp[2].y);
theta_tmp[2].z = (1.0f/3.0f)*((wz+1.0f)*theta_tmp[1].z + (3.0f-wz)*theta_tmp[2].z);
theta_tmp[1].x = (1.0f/3.0f)*((wx+2.0f)*theta_tmp[0].x + (2.0f-wx)*theta_tmp[1].x);
theta_tmp[1].y = (1.0f/3.0f)*((wy+2.0f)*theta_tmp[0].y + (2.0f-wy)*theta_tmp[1].y);
theta_tmp[1].z = (1.0f/3.0f)*((wz+2.0f)*theta_tmp[0].z + (2.0f-wz)*theta_tmp[1].z);
theta_tmp[0].x = (1.0f/3.0f)*(1.0f-wx)*theta_tmp[0].x;
theta_tmp[0].y = (1.0f/3.0f)*(1.0f-wy)*theta_tmp[0].y;
theta_tmp[0].z = (1.0f/3.0f)*(1.0f-wz)*theta_tmp[0].z;
// Store theta_tmp and dtheta_tmp into global memory
int pos4 = pos*4;
thetax[pos4] = theta_tmp[0].x;
thetax[pos4+1] = theta_tmp[1].x;
thetax[pos4+2] = theta_tmp[2].x;
thetax[pos4+3] = theta_tmp[3].x;
thetay[pos4] = theta_tmp[0].y;
thetay[pos4+1] = theta_tmp[1].y;
thetay[pos4+2] = theta_tmp[2].y;
thetay[pos4+3] = theta_tmp[3].y;
thetaz[pos4] = theta_tmp[0].z;
thetaz[pos4+1] = theta_tmp[1].z;
thetaz[pos4+2] = theta_tmp[2].z;
thetaz[pos4+3] = theta_tmp[3].z;
dthetax[pos4] = dtheta_tmp[0].x;
dthetax[pos4+1] = dtheta_tmp[1].x;
dthetax[pos4+2] = dtheta_tmp[2].x;
dthetax[pos4+3] = dtheta_tmp[3].x;
dthetay[pos4] = dtheta_tmp[0].y;
dthetay[pos4+1] = dtheta_tmp[1].y;
dthetay[pos4+2] = dtheta_tmp[2].y;
dthetay[pos4+3] = dtheta_tmp[3].y;
dthetaz[pos4] = dtheta_tmp[0].z;
dthetaz[pos4+1] = dtheta_tmp[1].z;
dthetaz[pos4+2] = dtheta_tmp[2].z;
dthetaz[pos4+3] = dtheta_tmp[3].z;
pos += blockDim.x*gridDim.x;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_
.globl _Z14fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_
.p2align 8
.type _Z14fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_,@function
_Z14fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x84
s_load_b32 s28, s[0:1], 0x8
s_add_u32 s2, s0, 0x78
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s29, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s29, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s28, v1
s_cbranch_execz .LBB0_3
s_clause 0x1
s_load_b128 s[20:23], s[0:1], 0x10
s_load_b32 s30, s[0:1], 0x20
s_load_b32 s31, s[2:3], 0x0
s_clause 0x3
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b256 s[4:11], s[0:1], 0x28
s_load_b256 s[12:19], s[0:1], 0x48
s_load_b128 s[24:27], s[0:1], 0x68
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v1
s_waitcnt lgkmcnt(0)
v_cvt_f32_i32_e32 v0, s22
v_cvt_f32_i32_e32 v5, s23
v_cvt_f32_i32_e32 v6, s30
s_mul_i32 s1, s31, s29
s_mov_b32 s23, 0
s_lshl_b32 s22, s1, 2
.LBB0_2:
v_lshlrev_b64 v[15:16], 4, v[1:2]
s_clause 0x1
global_load_b128 v[7:10], v2, s[20:21]
global_load_b128 v[11:14], v2, s[20:21] offset:16
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[19:20], 2, v[1:2]
v_add_co_u32 v15, vcc_lo, s2, v15
v_add_co_ci_u32_e32 v16, vcc_lo, s3, v16, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[27:28], 2, v[3:4]
v_add_co_u32 v29, s0, s4, v19
global_load_b128 v[15:18], v[15:16], off
global_load_b32 v75, v2, s[20:21] offset:32
v_add_nc_u32_e32 v21, 1, v3
v_add_nc_u32_e32 v1, s1, v1
v_add_co_ci_u32_e64 v30, s0, s5, v20, s0
v_add_co_u32 v31, s0, s6, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v32, s0, s7, v20, s0
v_add_co_u32 v33, s0, s8, v19
v_add_co_ci_u32_e64 v34, s0, s9, v20, s0
v_add_co_u32 v19, s0, s10, v19
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v20, s0, s11, v20, s0
s_waitcnt vmcnt(1)
v_mul_f32_e32 v4, v16, v8
v_mul_f32_e32 v8, v16, v11
v_add_nc_u32_e32 v23, 2, v3
v_mul_f32_e32 v11, v16, v14
v_cmp_le_u32_e32 vcc_lo, s28, v1
v_fmac_f32_e32 v4, v15, v7
v_dual_fmac_f32 v8, v15, v10 :: v_dual_add_nc_u32 v25, 3, v3
v_add_nc_u32_e32 v3, s22, v3
s_or_b32 s23, vcc_lo, s23
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v4, v17, v9
v_dual_fmac_f32 v8, v17, v12 :: v_dual_fmac_f32 v11, v15, v13
v_add_co_u32 v35, vcc_lo, s12, v27
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v4, 2.0, v4
v_add_f32_e32 v7, 2.0, v8
v_add_co_ci_u32_e32 v36, vcc_lo, s13, v28, vcc_lo
v_add_co_u32 v37, vcc_lo, s14, v27
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_add_f32 v9, 0.5, v4 :: v_dual_add_f32 v10, 0.5, v7
v_add_co_ci_u32_e32 v38, vcc_lo, s15, v28, vcc_lo
v_add_co_u32 v39, vcc_lo, s16, v27
v_floor_f32_e32 v9, v9
s_delay_alu instid0(VALU_DEP_4)
v_floor_f32_e32 v10, v10
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v11, v17, v75
v_ashrrev_i32_e32 v22, 31, v21
v_add_co_ci_u32_e32 v40, vcc_lo, s17, v28, vcc_lo
v_add_f32_e32 v10, -0.5, v10
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_add_f32 v8, 2.0, v11 :: v_dual_add_f32 v9, -0.5, v9
v_add_co_u32 v41, vcc_lo, s18, v27
v_ashrrev_i32_e32 v24, 31, v23
v_dual_add_f32 v11, 0.5, v8 :: v_dual_sub_f32 v4, v4, v9
v_add_co_ci_u32_e32 v42, vcc_lo, s19, v28, vcc_lo
v_lshlrev_b64 v[21:22], 2, v[21:22]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_floor_f32_e32 v11, v11
v_mul_f32_e32 v9, v4, v0
v_add_co_u32 v43, vcc_lo, s24, v27
v_ashrrev_i32_e32 v26, 31, v25
v_add_co_ci_u32_e32 v44, vcc_lo, s25, v28, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_cvt_i32_f32_e32 v9, v9
v_lshlrev_b64 v[23:24], 2, v[23:24]
v_add_co_u32 v27, vcc_lo, s26, v27
v_add_co_ci_u32_e32 v28, vcc_lo, s27, v28, vcc_lo
v_cvt_f32_i32_e32 v12, v9
v_lshlrev_b64 v[25:26], 2, v[25:26]
v_add_co_u32 v45, vcc_lo, s12, v21
v_add_co_ci_u32_e32 v46, vcc_lo, s13, v22, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_fma_f32 v4, v4, v0, -v12
v_sub_f32_e32 v7, v7, v10
v_add_co_u32 v47, vcc_lo, s12, v23
v_add_co_ci_u32_e32 v48, vcc_lo, s13, v24, vcc_lo
v_dual_mul_f32 v12, 0.5, v4 :: v_dual_add_f32 v11, -0.5, v11
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_mul_f32_e32 v10, v7, v5
v_add_co_u32 v49, vcc_lo, s12, v25
v_add_co_ci_u32_e32 v50, vcc_lo, s13, v26, vcc_lo
v_sub_f32_e32 v8, v8, v11
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cvt_i32_f32_e32 v10, v10
v_add_co_u32 v51, vcc_lo, s14, v21
v_add_co_ci_u32_e32 v52, vcc_lo, s15, v22, vcc_lo
v_mul_f32_e32 v11, v8, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cvt_f32_i32_e32 v13, v10
v_add_co_u32 v53, vcc_lo, s14, v23
v_add_co_ci_u32_e32 v54, vcc_lo, s15, v24, vcc_lo
v_cvt_i32_f32_e32 v11, v11
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_fma_f32 v7, v7, v5, -v13
v_add_co_u32 v55, vcc_lo, s14, v25
v_add_co_ci_u32_e32 v56, vcc_lo, s15, v26, vcc_lo
v_cvt_f32_i32_e32 v14, v11
v_add_co_u32 v57, vcc_lo, s16, v21
global_store_b32 v[19:20], v18, off
global_store_b32 v[29:30], v9, off
global_store_b32 v[31:32], v10, off
global_store_b32 v[33:34], v11, off
v_fma_f32 v8, v8, v6, -v14
v_dual_sub_f32 v9, 1.0, v4 :: v_dual_sub_f32 v18, 2.0, v7
v_dual_mul_f32 v13, 0.5, v7 :: v_dual_sub_f32 v16, 2.0, v4
v_add_co_ci_u32_e32 v58, vcc_lo, s17, v22, vcc_lo
v_add_co_u32 v59, vcc_lo, s16, v23
v_add_co_ci_u32_e32 v60, vcc_lo, s17, v24, vcc_lo
v_dual_sub_f32 v10, 1.0, v7 :: v_dual_sub_f32 v11, 1.0, v8
v_mul_f32_e32 v30, 0x3eaaaaab, v7
v_mul_f32_e32 v14, 0.5, v8
v_dual_add_f32 v15, 1.0, v4 :: v_dual_add_f32 v76, 2.0, v7
v_dual_add_f32 v17, 1.0, v7 :: v_dual_sub_f32 v20, 2.0, v8
v_dual_mul_f32 v29, 0x3eaaaaab, v4 :: v_dual_mul_f32 v78, -0.5, v9
v_dual_sub_f32 v32, 0x40400000, v4 :: v_dual_sub_f32 v33, 0x40400000, v7
v_dual_sub_f32 v34, 0x40400000, v8 :: v_dual_mul_f32 v13, v7, v13
v_dual_add_f32 v75, 2.0, v4 :: v_dual_mul_f32 v82, 0x3eaaaaab, v10
v_dual_mul_f32 v12, v4, v12 :: v_dual_mul_f32 v7, v7, v18
v_dual_mul_f32 v4, v4, v16 :: v_dual_mul_f32 v79, -0.5, v10
v_add_co_u32 v61, vcc_lo, s16, v25
v_add_co_ci_u32_e32 v62, vcc_lo, s17, v26, vcc_lo
v_add_co_u32 v63, vcc_lo, s18, v21
v_dual_add_f32 v19, 1.0, v8 :: v_dual_mul_f32 v14, v8, v14
v_dual_mul_f32 v31, 0x3eaaaaab, v8 :: v_dual_mul_f32 v80, -0.5, v11
v_dual_add_f32 v77, 2.0, v8 :: v_dual_fmac_f32 v4, v15, v9
v_dual_mul_f32 v8, v8, v20 :: v_dual_mul_f32 v81, 0x3eaaaaab, v9
v_fmac_f32_e32 v7, v17, v10
v_add_co_ci_u32_e32 v64, vcc_lo, s19, v22, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_fmac_f32_e32 v8, v19, v11
v_add_co_u32 v65, vcc_lo, s18, v23
v_add_co_ci_u32_e32 v66, vcc_lo, s19, v24, vcc_lo
v_add_co_u32 v67, vcc_lo, s18, v25
v_dual_mul_f32 v9, v9, v78 :: v_dual_mul_f32 v10, v10, v79
v_dual_mul_f32 v31, v31, v14 :: v_dual_mul_f32 v78, 0.5, v4
v_mul_f32_e32 v79, 0.5, v7
v_add_co_ci_u32_e32 v68, vcc_lo, s19, v26, vcc_lo
v_add_co_u32 v69, vcc_lo, s24, v21
v_add_co_ci_u32_e32 v70, vcc_lo, s25, v22, vcc_lo
v_dual_mul_f32 v83, 0x3eaaaaab, v11 :: v_dual_mul_f32 v30, v30, v13
v_dual_mul_f32 v11, v11, v80 :: v_dual_mul_f32 v16, v16, v78
v_mul_f32_e32 v80, 0.5, v8
v_dual_mul_f32 v29, v29, v12 :: v_dual_mul_f32 v18, v18, v79
v_add_co_u32 v71, vcc_lo, s24, v23
s_delay_alu instid0(VALU_DEP_3)
v_dual_mul_f32 v15, v15, v78 :: v_dual_mul_f32 v20, v20, v80
v_add_co_ci_u32_e32 v72, vcc_lo, s25, v24, vcc_lo
v_add_co_u32 v73, vcc_lo, s24, v25
v_fma_f32 v16, v75, -v9, v16
v_mul_f32_e32 v17, v17, v79
v_fma_f32 v18, v76, -v10, v18
v_mul_f32_e32 v19, v19, v80
v_add_co_ci_u32_e32 v74, vcc_lo, s25, v26, vcc_lo
v_add_co_u32 v21, vcc_lo, s26, v21
s_delay_alu instid0(VALU_DEP_4)
v_dual_mul_f32 v18, 0x3eaaaaab, v18 :: v_dual_fmac_f32 v15, v32, v12
v_add_co_ci_u32_e32 v22, vcc_lo, s27, v22, vcc_lo
v_add_co_u32 v23, vcc_lo, s26, v23
v_mul_f32_e64 v81, v81, -v9
v_fmac_f32_e32 v19, v34, v14
v_fma_f32 v20, v77, -v11, v20
v_dual_mul_f32 v16, 0x3eaaaaab, v16 :: v_dual_fmac_f32 v17, v33, v13
v_add_co_ci_u32_e32 v24, vcc_lo, s27, v24, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_dual_mul_f32 v20, 0x3eaaaaab, v20 :: v_dual_mul_f32 v15, 0x3eaaaaab, v15
v_add_co_u32 v25, vcc_lo, s26, v25
v_mul_f32_e64 v82, v82, -v10
v_add_co_ci_u32_e32 v26, vcc_lo, s27, v26, vcc_lo
v_fma_f32 v84, v4, -0.5, -v9
v_fma_f32 v85, v7, -0.5, -v10
v_fma_f32 v86, v8, -0.5, -v11
v_fma_f32 v4, v4, 0.5, -v12
v_fma_f32 v7, v7, 0.5, -v13
v_fma_f32 v8, v8, 0.5, -v14
v_mul_f32_e64 v83, v83, -v11
v_mul_f32_e32 v17, 0x3eaaaaab, v17
v_mul_f32_e32 v19, 0x3eaaaaab, v19
s_clause 0x3
global_store_b32 v[35:36], v81, off
global_store_b32 v[45:46], v16, off
global_store_b32 v[47:48], v15, off
global_store_b32 v[49:50], v29, off
s_clause 0x3
global_store_b32 v[37:38], v82, off
global_store_b32 v[51:52], v18, off
global_store_b32 v[53:54], v17, off
global_store_b32 v[55:56], v30, off
s_clause 0x3
global_store_b32 v[39:40], v83, off
global_store_b32 v[57:58], v20, off
global_store_b32 v[59:60], v19, off
global_store_b32 v[61:62], v31, off
s_clause 0x3
global_store_b32 v[41:42], v9, off
global_store_b32 v[63:64], v84, off
global_store_b32 v[65:66], v4, off
global_store_b32 v[67:68], v12, off
s_clause 0x3
global_store_b32 v[43:44], v10, off
global_store_b32 v[69:70], v85, off
global_store_b32 v[71:72], v7, off
global_store_b32 v[73:74], v13, off
s_clause 0x3
global_store_b32 v[27:28], v11, off
global_store_b32 v[21:22], v86, off
global_store_b32 v[23:24], v8, off
global_store_b32 v[25:26], v14, off
s_and_not1_b32 exec_lo, exec_lo, s23
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 376
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 87
.amdhsa_next_free_sgpr 32
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_, .Lfunc_end0-_Z14fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 80
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 88
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 96
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 104
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 112
.size: 8
.value_kind: global_buffer
- .offset: 120
.size: 4
.value_kind: hidden_block_count_x
- .offset: 124
.size: 4
.value_kind: hidden_block_count_y
- .offset: 128
.size: 4
.value_kind: hidden_block_count_z
- .offset: 132
.size: 2
.value_kind: hidden_group_size_x
- .offset: 134
.size: 2
.value_kind: hidden_group_size_y
- .offset: 136
.size: 2
.value_kind: hidden_group_size_z
- .offset: 138
.size: 2
.value_kind: hidden_remainder_x
- .offset: 140
.size: 2
.value_kind: hidden_remainder_y
- .offset: 142
.size: 2
.value_kind: hidden_remainder_z
- .offset: 160
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 168
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 176
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 184
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 376
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_
.private_segment_fixed_size: 0
.sgpr_count: 34
.sgpr_spill_count: 0
.symbol: _Z14fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 87
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void fill_bspline_4(const float4 *xyzq, const int ncoord, const float *recip, const int nfftx, const int nffty, const int nfftz, int *gix, int *giy, int *giz, float *charge, float *thetax, float *thetay, float *thetaz, float *dthetax, float *dthetay, float *dthetaz) {
// Position to xyzq and atomgrid
unsigned int pos = blockIdx.x*blockDim.x + threadIdx.x;
while (pos < ncoord) {
float4 xyzqi = xyzq[pos];
float x = xyzqi.x;
float y = xyzqi.y;
float z = xyzqi.z;
float q = xyzqi.w;
float w;
// NOTE: I don't think we need the +2.0f here..
w = x*recip[0] + y*recip[1] + z*recip[2] + 2.0f;
float frx = (float)(nfftx*(w - (floorf(w + 0.5f) - 0.5f)));
w = x*recip[3] + y*recip[4] + z*recip[5] + 2.0f;
float fry = (float)(nffty*(w - (floorf(w + 0.5f) - 0.5f)));
w = x*recip[6] + y*recip[7] + z*recip[8] + 2.0f;
float frz = (float)(nfftz*(w - (floorf(w + 0.5f) - 0.5f)));
int frxi = (int)(frx);
int fryi = (int)(fry);
int frzi = (int)(frz);
float wx = frx - (float)frxi;
float wy = fry - (float)fryi;
float wz = frz - (float)frzi;
gix[pos] = frxi;
giy[pos] = fryi;
giz[pos] = frzi;
charge[pos] = q;
float3 theta_tmp[4];
float3 dtheta_tmp[4];
theta_tmp[3].x = 0.0f;
theta_tmp[3].y = 0.0f;
theta_tmp[3].z = 0.0f;
theta_tmp[1].x = wx;
theta_tmp[1].y = wy;
theta_tmp[1].z = wz;
theta_tmp[0].x = 1.0f - wx;
theta_tmp[0].y = 1.0f - wy;
theta_tmp[0].z = 1.0f - wz;
// compute standard b-spline recursion
theta_tmp[2].x = 0.5f*wx*theta_tmp[1].x;
theta_tmp[2].y = 0.5f*wy*theta_tmp[1].y;
theta_tmp[2].z = 0.5f*wz*theta_tmp[1].z;
theta_tmp[1].x = 0.5f*((wx+1.0f)*theta_tmp[0].x + (2.0f-wx)*theta_tmp[1].x);
theta_tmp[1].y = 0.5f*((wy+1.0f)*theta_tmp[0].y + (2.0f-wy)*theta_tmp[1].y);
theta_tmp[1].z = 0.5f*((wz+1.0f)*theta_tmp[0].z + (2.0f-wz)*theta_tmp[1].z);
theta_tmp[0].x = 0.5f*(1.0f-wx)*theta_tmp[0].x;
theta_tmp[0].y = 0.5f*(1.0f-wy)*theta_tmp[0].y;
theta_tmp[0].z = 0.5f*(1.0f-wz)*theta_tmp[0].z;
// perform standard b-spline differentiationa
dtheta_tmp[0].x = -theta_tmp[0].x;
dtheta_tmp[0].y = -theta_tmp[0].y;
dtheta_tmp[0].z = -theta_tmp[0].z;
dtheta_tmp[1].x = theta_tmp[0].x - theta_tmp[1].x;
dtheta_tmp[1].y = theta_tmp[0].y - theta_tmp[1].y;
dtheta_tmp[1].z = theta_tmp[0].z - theta_tmp[1].z;
dtheta_tmp[2].x = theta_tmp[1].x - theta_tmp[2].x;
dtheta_tmp[2].y = theta_tmp[1].y - theta_tmp[2].y;
dtheta_tmp[2].z = theta_tmp[1].z - theta_tmp[2].z;
dtheta_tmp[3].x = theta_tmp[2].x - theta_tmp[3].x;
dtheta_tmp[3].y = theta_tmp[2].y - theta_tmp[3].y;
dtheta_tmp[3].z = theta_tmp[2].z - theta_tmp[3].z;
// one more recursion
theta_tmp[3].x = (1.0f/3.0f)*wx*theta_tmp[2].x;
theta_tmp[3].y = (1.0f/3.0f)*wy*theta_tmp[2].y;
theta_tmp[3].z = (1.0f/3.0f)*wz*theta_tmp[2].z;
theta_tmp[2].x = (1.0f/3.0f)*((wx+1.0f)*theta_tmp[1].x + (3.0f-wx)*theta_tmp[2].x);
theta_tmp[2].y = (1.0f/3.0f)*((wy+1.0f)*theta_tmp[1].y + (3.0f-wy)*theta_tmp[2].y);
theta_tmp[2].z = (1.0f/3.0f)*((wz+1.0f)*theta_tmp[1].z + (3.0f-wz)*theta_tmp[2].z);
theta_tmp[1].x = (1.0f/3.0f)*((wx+2.0f)*theta_tmp[0].x + (2.0f-wx)*theta_tmp[1].x);
theta_tmp[1].y = (1.0f/3.0f)*((wy+2.0f)*theta_tmp[0].y + (2.0f-wy)*theta_tmp[1].y);
theta_tmp[1].z = (1.0f/3.0f)*((wz+2.0f)*theta_tmp[0].z + (2.0f-wz)*theta_tmp[1].z);
theta_tmp[0].x = (1.0f/3.0f)*(1.0f-wx)*theta_tmp[0].x;
theta_tmp[0].y = (1.0f/3.0f)*(1.0f-wy)*theta_tmp[0].y;
theta_tmp[0].z = (1.0f/3.0f)*(1.0f-wz)*theta_tmp[0].z;
// Store theta_tmp and dtheta_tmp into global memory
int pos4 = pos*4;
thetax[pos4] = theta_tmp[0].x;
thetax[pos4+1] = theta_tmp[1].x;
thetax[pos4+2] = theta_tmp[2].x;
thetax[pos4+3] = theta_tmp[3].x;
thetay[pos4] = theta_tmp[0].y;
thetay[pos4+1] = theta_tmp[1].y;
thetay[pos4+2] = theta_tmp[2].y;
thetay[pos4+3] = theta_tmp[3].y;
thetaz[pos4] = theta_tmp[0].z;
thetaz[pos4+1] = theta_tmp[1].z;
thetaz[pos4+2] = theta_tmp[2].z;
thetaz[pos4+3] = theta_tmp[3].z;
dthetax[pos4] = dtheta_tmp[0].x;
dthetax[pos4+1] = dtheta_tmp[1].x;
dthetax[pos4+2] = dtheta_tmp[2].x;
dthetax[pos4+3] = dtheta_tmp[3].x;
dthetay[pos4] = dtheta_tmp[0].y;
dthetay[pos4+1] = dtheta_tmp[1].y;
dthetay[pos4+2] = dtheta_tmp[2].y;
dthetay[pos4+3] = dtheta_tmp[3].y;
dthetaz[pos4] = dtheta_tmp[0].z;
dthetaz[pos4+1] = dtheta_tmp[1].z;
dthetaz[pos4+2] = dtheta_tmp[2].z;
dthetaz[pos4+3] = dtheta_tmp[3].z;
pos += blockDim.x*gridDim.x;
}
} | .text
.file "fill_bspline_4.hip"
.globl _Z29__device_stub__fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_ # -- Begin function _Z29__device_stub__fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_
.p2align 4, 0x90
.type _Z29__device_stub__fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_,@function
_Z29__device_stub__fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_: # @_Z29__device_stub__fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 224(%rsp), %rax
movq %rax, 128(%rsp)
leaq 232(%rsp), %rax
movq %rax, 136(%rsp)
leaq 240(%rsp), %rax
movq %rax, 144(%rsp)
leaq 248(%rsp), %rax
movq %rax, 152(%rsp)
leaq 256(%rsp), %rax
movq %rax, 160(%rsp)
leaq 264(%rsp), %rax
movq %rax, 168(%rsp)
leaq 272(%rsp), %rax
movq %rax, 176(%rsp)
leaq 280(%rsp), %rax
movq %rax, 184(%rsp)
leaq 288(%rsp), %rax
movq %rax, 192(%rsp)
leaq 296(%rsp), %rax
movq %rax, 200(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end0:
.size _Z29__device_stub__fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_, .Lfunc_end0-_Z29__device_stub__fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_,@object # @_Z14fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_
.section .rodata,"a",@progbits
.globl _Z14fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_
.p2align 3, 0x0
_Z14fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_:
.quad _Z29__device_stub__fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_
.size _Z14fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_"
.size .L__unnamed_1, 80
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14fill_bspline_4PK6float4iPKfiiiPiS4_S4_PfS5_S5_S5_S5_S5_S5_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x168], PT ; /* 0x00005a0008007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ I2F R0, c[0x0][0x178] ; /* 0x00005e0000007b06 */
/* 0x000e220000201400 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fce0000000a00 */
/*0080*/ I2F R2, c[0x0][0x17c] ; /* 0x00005f0000027b06 */
/* 0x000e700000201400 */
/*0090*/ I2F R3, c[0x0][0x180] ; /* 0x0000600000037b06 */
/* 0x001ea40000201400 */
/*00a0*/ HFMA2.MMA R5, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff057435 */
/* 0x000fe200000001ff */
/*00b0*/ MOV R10, c[0x0][0x170] ; /* 0x00005c00000a7a02 */
/* 0x000fe40000000f00 */
/*00c0*/ MOV R11, c[0x0][0x174] ; /* 0x00005d00000b7a02 */
/* 0x000fca0000000f00 */
/*00d0*/ LDG.E R14, [R10.64+0x4] ; /* 0x000004040a0e7981 */
/* 0x000ee4000c1e1900 */
/*00e0*/ IMAD.WIDE.U32 R4, R8.reuse, R5, c[0x0][0x160] ; /* 0x0000580008047625 */
/* 0x040fe400078e0005 */
/*00f0*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x000f28000c1e1900 */
/*0100*/ LDG.E.128 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee8000c1e1d00 */
/*0110*/ LDG.E R16, [R10.64+0x8] ; /* 0x000008040a107981 */
/* 0x000f68000c1e1900 */
/*0120*/ LDG.E R18, [R10.64+0x10] ; /* 0x000010040a127981 */
/* 0x004ea8000c1e1900 */
/*0130*/ LDG.E R17, [R10.64+0xc] ; /* 0x00000c040a117981 */
/* 0x000ea8000c1e1900 */
/*0140*/ LDG.E R19, [R10.64+0x14] ; /* 0x000014040a137981 */
/* 0x000ea8000c1e1900 */
/*0150*/ LDG.E R12, [R10.64+0x1c] ; /* 0x00001c040a0c7981 */
/* 0x0000a8000c1e1900 */
/*0160*/ LDG.E R9, [R10.64+0x18] ; /* 0x000018040a097981 */
/* 0x0000a8000c1e1900 */
/*0170*/ LDG.E R13, [R10.64+0x20] ; /* 0x000020040a0d7981 */
/* 0x0000a2000c1e1900 */
/*0180*/ SHF.L.U32 R20, R8, 0x2, RZ ; /* 0x0000000208147819 */
/* 0x000fe200000006ff */
/*0190*/ FMUL R14, R5, R14 ; /* 0x0000000e050e7220 */
/* 0x008fc80000400000 */
/*01a0*/ FFMA R15, R4, R15, R14 ; /* 0x0000000f040f7223 */
/* 0x010fc8000000000e */
/*01b0*/ FFMA R15, R6, R16, R15 ; /* 0x00000010060f7223 */
/* 0x020fe4000000000f */
/*01c0*/ FMUL R18, R5, R18 ; /* 0x0000001205127220 */
/* 0x004fe40000400000 */
/*01d0*/ FADD R15, R15, 2 ; /* 0x400000000f0f7421 */
/* 0x000fe40000000000 */
/*01e0*/ FFMA R17, R4, R17, R18 ; /* 0x0000001104117223 */
/* 0x000fe40000000012 */
/*01f0*/ FADD R14, R15, 0.5 ; /* 0x3f0000000f0e7421 */
/* 0x000fe40000000000 */
/*0200*/ FFMA R17, R6, R19, R17 ; /* 0x0000001306117223 */
/* 0x000fc80000000011 */
/*0210*/ FRND.FLOOR R14, R14 ; /* 0x0000000e000e7307 */
/* 0x000ea20000205000 */
/*0220*/ FADD R17, R17, 2 ; /* 0x4000000011117421 */
/* 0x000fc80000000000 */
/*0230*/ FADD R11, R17, 0.5 ; /* 0x3f000000110b7421 */
/* 0x001fe40000000000 */
/*0240*/ FMUL R12, R5, R12 ; /* 0x0000000c050c7220 */
/* 0x000fc80000400000 */
/*0250*/ FRND.FLOOR R11, R11 ; /* 0x0000000b000b7307 */
/* 0x000e220000205000 */
/*0260*/ FFMA R9, R4, R9, R12 ; /* 0x0000000904097223 */
/* 0x000fe4000000000c */
/*0270*/ FADD R10, R14, -0.5 ; /* 0xbf0000000e0a7421 */
/* 0x004fc80000000000 */
/*0280*/ FADD R15, R15, -R10 ; /* 0x8000000a0f0f7221 */
/* 0x000fe40000000000 */
/*0290*/ FFMA R9, R6, R13, R9 ; /* 0x0000000d06097223 */
/* 0x000fe40000000009 */
/*02a0*/ FMUL R15, R0, R15 ; /* 0x0000000f000f7220 */
/* 0x000fe40000400000 */
/*02b0*/ FADD R9, R9, 2 ; /* 0x4000000009097421 */
/* 0x000fe40000000000 */
/*02c0*/ F2I.TRUNC.NTZ R27, R15 ; /* 0x0000000f001b7305 */
/* 0x000ea2000020f100 */
/*02d0*/ FADD R4, R11, -0.5 ; /* 0xbf0000000b047421 */
/* 0x001fe40000000000 */
/*02e0*/ FADD R10, R9, 0.5 ; /* 0x3f000000090a7421 */
/* 0x000fc40000000000 */
/*02f0*/ FADD R17, R17, -R4 ; /* 0x8000000411117221 */
/* 0x000fc80000000000 */
/*0300*/ FRND.FLOOR R10, R10 ; /* 0x0000000a000a7307 */
/* 0x000e220000205000 */
/*0310*/ FMUL R17, R2, R17 ; /* 0x0000001102117220 */
/* 0x002fce0000400000 */
/*0320*/ F2I.TRUNC.NTZ R29, R17 ; /* 0x00000011001d7305 */
/* 0x000e70000020f100 */
/*0330*/ I2F R6, R27 ; /* 0x0000001b00067306 */
/* 0x004ea20000201400 */
/*0340*/ FADD R4, R10, -0.5 ; /* 0xbf0000000a047421 */
/* 0x001fc80000000000 */
/*0350*/ FADD R4, R9, -R4 ; /* 0x8000000409047221 */
/* 0x000fc60000000000 */
/*0360*/ I2F R14, R29 ; /* 0x0000001d000e7306 */
/* 0x002e220000201400 */
/*0370*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0380*/ FADD R15, R15, -R6 ; /* 0x800000060f0f7221 */
/* 0x004fe40000000000 */
/*0390*/ FMUL R6, R3, R4 ; /* 0x0000000403067220 */
/* 0x000fc80000400000 */
/*03a0*/ F2I.TRUNC.NTZ R25, R6 ; /* 0x0000000600197305 */
/* 0x000e62000020f100 */
/*03b0*/ FADD R26, -R15, 2 ; /* 0x400000000f1a7421 */
/* 0x000fe40000000100 */
/*03c0*/ FADD R14, R17, -R14 ; /* 0x8000000e110e7221 */
/* 0x001fe40000000000 */
/*03d0*/ IMAD.WIDE.U32 R10, R8, R5, c[0x0][0x188] ; /* 0x00006200080a7625 */
/* 0x000fc800078e0005 */
/*03e0*/ FADD R23, -R15.reuse, 1 ; /* 0x3f8000000f177421 */
/* 0x040fe40000000100 */
/*03f0*/ FADD R12, R15.reuse, 1 ; /* 0x3f8000000f0c7421 */
/* 0x040fe40000000000 */
/*0400*/ FMUL R4, R15, R26 ; /* 0x0000001a0f047220 */
/* 0x000fe40000400000 */
/*0410*/ IMAD.WIDE.U32 R16, R8.reuse, R5.reuse, c[0x0][0x190] ; /* 0x0000640008107625 */
/* 0x0c0fe200078e0005 */
/*0420*/ STG.E [R10.64], R27 ; /* 0x0000001b0a007986 */
/* 0x000fe6000c101904 */
/*0430*/ IMAD.WIDE.U32 R18, R8, R5, c[0x0][0x198] ; /* 0x0000660008127625 */
/* 0x000fe200078e0005 */
/*0440*/ STG.E [R16.64], R29 ; /* 0x0000001d10007986 */
/* 0x000fe6000c101904 */
/*0450*/ FFMA R9, R23, R12, R4 ; /* 0x0000000c17097223 */
/* 0x000fe20000000004 */
/*0460*/ STG.E [R18.64], R25 ; /* 0x0000001912007986 */
/* 0x0021e2000c101904 */
/*0470*/ FMUL R4, R15, 0.5 ; /* 0x3f0000000f047820 */
/* 0x000fc40000400000 */
/*0480*/ FMUL R9, R9, 0.5 ; /* 0x3f00000009097820 */
/* 0x000fe40000400000 */
/*0490*/ FADD R24, -R14, 2 ; /* 0x400000000e187421 */
/* 0x000fe40000000100 */
/*04a0*/ FADD R28, -R15.reuse, 3 ; /* 0x404000000f1c7421 */
/* 0x040fe20000000100 */
/*04b0*/ I2F R25, R25 ; /* 0x0000001900197306 */
/* 0x001e220000201400 */
/*04c0*/ FMUL R4, R15, R4 ; /* 0x000000040f047220 */
/* 0x000fe40000400000 */
/*04d0*/ FMUL R13, R12, R9.reuse ; /* 0x000000090c0d7220 */
/* 0x080fe40000400000 */
/*04e0*/ FMUL R11, R26, R9 ; /* 0x000000091a0b7220 */
/* 0x000fc40000400000 */
/*04f0*/ FADD R21, -R14.reuse, 1 ; /* 0x3f8000000e157421 */
/* 0x040fe40000000100 */
/*0500*/ FADD R26, R14.reuse, 1 ; /* 0x3f8000000e1a7421 */
/* 0x040fe40000000000 */
/*0510*/ FMUL R10, R14, R24 ; /* 0x000000180e0a7220 */
/* 0x000fe40000400000 */
/*0520*/ FFMA R28, R4, R28, R13 ; /* 0x0000001c041c7223 */
/* 0x000fe4000000000d */
/*0530*/ IMAD.WIDE.U32 R12, R8, R5, c[0x0][0x1a0] ; /* 0x00006800080c7625 */
/* 0x000fc800078e0005 */
/*0540*/ FMUL R22, R23, 0.5 ; /* 0x3f00000017167820 */
/* 0x000fe40000400000 */
/*0550*/ FFMA R16, R21, R26, R10 ; /* 0x0000001a15107223 */
/* 0x000fe2000000000a */
/*0560*/ STG.E [R12.64], R7 ; /* 0x000000070c007986 */
/* 0x0001e2000c101904 */
/*0570*/ FADD R17, R15, 2 ; /* 0x400000000f117421 */
/* 0x000fe40000000000 */
/*0580*/ FMUL R22, R23, R22 ; /* 0x0000001617167220 */
/* 0x000fe40000400000 */
/*0590*/ FMUL R29, R15, 0.3333333432674407959 ; /* 0x3eaaaaab0f1d7820 */
/* 0x000fe40000400000 */
/*05a0*/ FMUL R27, R14, 0.5 ; /* 0x3f0000000e1b7820 */
/* 0x000fc40000400000 */
/*05b0*/ FMUL R15, R16, 0.5 ; /* 0x3f000000100f7820 */
/* 0x000fe40000400000 */
/*05c0*/ FMUL R23, R23, 0.3333333432674407959 ; /* 0x3eaaaaab17177820 */
/* 0x000fe40000400000 */
/*05d0*/ FADD R12, R6, -R25 ; /* 0x80000019060c7221 */
/* 0x001fe40000000000 */
/*05e0*/ FMUL R16, R14.reuse, R27 ; /* 0x0000001b0e107220 */
/* 0x040fe40000400000 */
/*05f0*/ FADD R19, -R14, 3 ; /* 0x404000000e137421 */
/* 0x000fe40000000100 */
/*0600*/ FMUL R26, R26, R15 ; /* 0x0000000f1a1a7220 */
/* 0x000fc40000400000 */
/*0610*/ FMUL R27, R22, R23 ; /* 0x00000017161b7220 */
/* 0x000fe40000400000 */
/*0620*/ FADD R23, -R12, 2 ; /* 0x400000000c177421 */
/* 0x000fe40000000100 */
/*0630*/ FFMA R13, R16, R19, R26 ; /* 0x00000013100d7223 */
/* 0x000fe4000000001a */
/*0640*/ FMUL R18, R21, 0.5 ; /* 0x3f00000015127820 */
/* 0x000fe40000400000 */
/*0650*/ FADD R19, -R12.reuse, 1 ; /* 0x3f8000000c137421 */
/* 0x040fe40000000100 */
/*0660*/ FADD R26, R12, 1 ; /* 0x3f8000000c1a7421 */
/* 0x000fc40000000000 */
/*0670*/ FMUL R6, R12, R23 ; /* 0x000000170c067220 */
/* 0x000fe40000400000 */
/*0680*/ FFMA R17, R22, R17, R11 ; /* 0x0000001116117223 */
/* 0x000fe4000000000b */
/*0690*/ FMUL R18, R21, R18 ; /* 0x0000001215127220 */
/* 0x000fe40000400000 */
/*06a0*/ FMUL R24, R24, R15 ; /* 0x0000000f18187220 */
/* 0x000fe40000400000 */
/*06b0*/ FADD R25, R14, 2 ; /* 0x400000000e197421 */
/* 0x000fe40000000000 */
/*06c0*/ FFMA R6, R19, R26, R6 ; /* 0x0000001a13067223 */
/* 0x000fc40000000006 */
/*06d0*/ IMAD.WIDE R10, R20, R5, c[0x0][0x1a8] ; /* 0x00006a00140a7625 */
/* 0x000fc800078e0205 */
/*06e0*/ FMUL R7, R28, 0.3333333432674407959 ; /* 0x3eaaaaab1c077820 */
/* 0x000fe40000400000 */
/*06f0*/ FMUL R28, R17, 0.3333333432674407959 ; /* 0x3eaaaaab111c7820 */
/* 0x000fe40000400000 */
/*0700*/ FFMA R25, R18, R25, R24 ; /* 0x0000001912197223 */
/* 0x000fe40000000018 */
/*0710*/ FMUL R29, R4, R29 ; /* 0x0000001d041d7220 */
/* 0x000fe40000400000 */
/*0720*/ FMUL R24, R19.reuse, 0.5 ; /* 0x3f00000013187820 */
/* 0x040fe40000400000 */
/*0730*/ FMUL R17, R6, 0.5 ; /* 0x3f00000006117820 */
/* 0x000fe20000400000 */
/*0740*/ STG.E [R10.64], R27 ; /* 0x0000001b0a007986 */
/* 0x0001e2000c101904 */
/*0750*/ FMUL R24, R19, R24 ; /* 0x0000001813187220 */
/* 0x000fc40000400000 */
/*0760*/ FMUL R23, R23, R17 ; /* 0x0000001117177220 */
/* 0x000fe20000400000 */
/*0770*/ STG.E [R10.64+0xc], R29 ; /* 0x00000c1d0a007986 */
/* 0x0003e2000c101904 */
/*0780*/ FMUL R21, R21, 0.3333333432674407959 ; /* 0x3eaaaaab15157820 */
/* 0x000fc60000400000 */
/*0790*/ STG.E [R10.64+0x8], R7 ; /* 0x000008070a007986 */
/* 0x0005e2000c101904 */
/*07a0*/ FMUL R27, R13, 0.3333333432674407959 ; /* 0x3eaaaaab0d1b7820 */
/* 0x001fc60000400000 */
/*07b0*/ STG.E [R10.64+0x4], R28 ; /* 0x0000041c0a007986 */
/* 0x0001e2000c101904 */
/*07c0*/ FADD R13, R12, 2 ; /* 0x400000000c0d7421 */
/* 0x000fe40000000000 */
/*07d0*/ FMUL R29, R18, R21 ; /* 0x00000015121d7220 */
/* 0x002fe40000400000 */
/*07e0*/ FFMA R13, R24, R13, R23 ; /* 0x0000000d180d7223 */
/* 0x000fe40000000017 */
/*07f0*/ IMAD.WIDE R6, R20, R5, c[0x0][0x1b0] ; /* 0x00006c0014067625 */
/* 0x004fc800078e0205 */
/*0800*/ FMUL R11, R12, 0.5 ; /* 0x3f0000000c0b7820 */
/* 0x001fe40000400000 */
/*0810*/ FMUL R23, R14, 0.3333333432674407959 ; /* 0x3eaaaaab0e177820 */
/* 0x000fe40000400000 */
/*0820*/ FADD R21, -R12.reuse, 3 ; /* 0x404000000c157421 */
/* 0x040fe40000000100 */
/*0830*/ FMUL R14, R12, R11 ; /* 0x0000000b0c0e7220 */
/* 0x000fe40000400000 */
/*0840*/ FMUL R26, R26, R17 ; /* 0x000000111a1a7220 */
/* 0x000fe20000400000 */
/*0850*/ STG.E [R6.64+0x8], R27 ; /* 0x0000081b06007986 */
/* 0x0001e2000c101904 */
/*0860*/ FMUL R25, R25, 0.3333333432674407959 ; /* 0x3eaaaaab19197820 */
/* 0x000fc40000400000 */
/*0870*/ FMUL R23, R16, R23 ; /* 0x0000001710177220 */
/* 0x000fe40000400000 */
/*0880*/ FFMA R21, R14, R21, R26 ; /* 0x000000150e157223 */
/* 0x000fe4000000001a */
/*0890*/ FMUL R19, R19, 0.3333333432674407959 ; /* 0x3eaaaaab13137820 */
/* 0x000fe20000400000 */
/*08a0*/ STG.E [R6.64+0x4], R25 ; /* 0x0000041906007986 */
/* 0x0003e2000c101904 */
/*08b0*/ FMUL R27, R13, 0.3333333432674407959 ; /* 0x3eaaaaab0d1b7820 */
/* 0x001fe40000400000 */
/*08c0*/ FMUL R13, R12, 0.3333333432674407959 ; /* 0x3eaaaaab0c0d7820 */
/* 0x000fe20000400000 */
/*08d0*/ STG.E [R6.64], R29 ; /* 0x0000001d06007986 */
/* 0x0001e2000c101904 */
/*08e0*/ FMUL R28, R24, R19 ; /* 0x00000013181c7220 */
/* 0x000fc40000400000 */
/*08f0*/ IMAD.WIDE R10, R20, R5, c[0x0][0x1b8] ; /* 0x00006e00140a7625 */
/* 0x000fe200078e0205 */
/*0900*/ STG.E [R6.64+0xc], R23 ; /* 0x00000c1706007986 */
/* 0x0005e6000c101904 */
/*0910*/ FMUL R25, R21, 0.3333333432674407959 ; /* 0x3eaaaaab15197820 */
/* 0x002fe40000400000 */
/*0920*/ FMUL R21, R14, R13 ; /* 0x0000000d0e157220 */
/* 0x000fe40000400000 */
/*0930*/ IMAD.WIDE R12, R20, R5, c[0x0][0x1c0] ; /* 0x00007000140c7625 */
/* 0x000fc800078e0205 */
/*0940*/ FADD R29, -R22, -RZ ; /* 0x800000ff161d7221 */
/* 0x001fe40000000100 */
/*0950*/ FADD R19, -R9, R22 ; /* 0x0000001609137221 */
/* 0x000fe40000000100 */
/*0960*/ FADD R23, -R4, R9 ; /* 0x0000000904177221 */
/* 0x004fe40000000100 */
/*0970*/ IMAD.WIDE R6, R20, R5, c[0x0][0x1c8] ; /* 0x0000720014067625 */
/* 0x000fe200078e0205 */
/*0980*/ STG.E [R10.64], R28 ; /* 0x0000001c0a007986 */
/* 0x000fe6000c101904 */
/*0990*/ FADD R9, -R15, R18 ; /* 0x000000120f097221 */
/* 0x000fe20000000100 */
/*09a0*/ STG.E [R10.64+0x4], R27 ; /* 0x0000041b0a007986 */
/* 0x0001e2000c101904 */
/*09b0*/ FADD R15, -R16, R15 ; /* 0x0000000f100f7221 */
/* 0x000fc60000000100 */
/*09c0*/ STG.E [R10.64+0x8], R25 ; /* 0x000008190a007986 */
/* 0x000fe8000c101904 */
/*09d0*/ STG.E [R10.64+0xc], R21 ; /* 0x00000c150a007986 */
/* 0x0003e8000c101904 */
/*09e0*/ STG.E [R12.64], R29 ; /* 0x0000001d0c007986 */
/* 0x000fe2000c101904 */
/*09f0*/ FADD R27, -R18, -RZ ; /* 0x800000ff121b7221 */
/* 0x001fc60000000100 */
/*0a00*/ STG.E [R12.64+0x4], R19 ; /* 0x000004130c007986 */
/* 0x000fe8000c101904 */
/*0a10*/ STG.E [R12.64+0x8], R23 ; /* 0x000008170c007986 */
/* 0x000fe2000c101904 */
/*0a20*/ IMAD.WIDE R20, R20, R5, c[0x0][0x1d0] ; /* 0x0000740014147625 */
/* 0x002fc600078e0205 */
/*0a30*/ STG.E [R12.64+0xc], R4 ; /* 0x00000c040c007986 */
/* 0x000fe2000c101904 */
/*0a40*/ FADD R5, -R17, R24 ; /* 0x0000001811057221 */
/* 0x000fe40000000100 */
/*0a50*/ FADD R11, -R24, -RZ ; /* 0x800000ff180b7221 */
/* 0x000fe20000000100 */
/*0a60*/ STG.E [R6.64+0x4], R9 ; /* 0x0000040906007986 */
/* 0x0001e2000c101904 */
/*0a70*/ FADD R17, -R14, R17 ; /* 0x000000110e117221 */
/* 0x000fc60000000100 */
/*0a80*/ STG.E [R6.64], R27 ; /* 0x0000001b06007986 */
/* 0x0003e8000c101904 */
/*0a90*/ STG.E [R6.64+0x8], R15 ; /* 0x0000080f06007986 */
/* 0x0003e2000c101904 */
/*0aa0*/ MOV R9, c[0x0][0x0] ; /* 0x0000000000097a02 */
/* 0x001fc60000000f00 */
/*0ab0*/ STG.E [R6.64+0xc], R16 ; /* 0x00000c1006007986 */
/* 0x0003e8000c101904 */
/*0ac0*/ STG.E [R20.64], R11 ; /* 0x0000000b14007986 */
/* 0x0003e2000c101904 */
/*0ad0*/ IMAD R8, R9, c[0x0][0xc], R8 ; /* 0x0000030009087a24 */
/* 0x000fc600078e0208 */
/*0ae0*/ STG.E [R20.64+0x4], R5 ; /* 0x0000040514007986 */
/* 0x0003e8000c101904 */
/*0af0*/ STG.E [R20.64+0x8], R17 ; /* 0x0000081114007986 */
/* 0x0003e8000c101904 */
/*0b00*/ STG.E [R20.64+0xc], R14 ; /* 0x00000c0e14007986 */
/* 0x0003e2000c101904 */
/*0b10*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x168], PT ; /* 0x00005a0008007a0c */
/* 0x000fda0003f06070 */
/*0b20*/ @!P0 BRA 0xa0 ; /* 0xfffff57000008947 */
/* 0x002fea000383ffff */
/*0b30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b40*/ BRA 0xb40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_
.globl _Z14fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_
.p2align 8
.type _Z14fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_,@function
_Z14fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x84
s_load_b32 s28, s[0:1], 0x8
s_add_u32 s2, s0, 0x78
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s29, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s29, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s28, v1
s_cbranch_execz .LBB0_3
s_clause 0x1
s_load_b128 s[20:23], s[0:1], 0x10
s_load_b32 s30, s[0:1], 0x20
s_load_b32 s31, s[2:3], 0x0
s_clause 0x3
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b256 s[4:11], s[0:1], 0x28
s_load_b256 s[12:19], s[0:1], 0x48
s_load_b128 s[24:27], s[0:1], 0x68
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v1
s_waitcnt lgkmcnt(0)
v_cvt_f32_i32_e32 v0, s22
v_cvt_f32_i32_e32 v5, s23
v_cvt_f32_i32_e32 v6, s30
s_mul_i32 s1, s31, s29
s_mov_b32 s23, 0
s_lshl_b32 s22, s1, 2
.LBB0_2:
v_lshlrev_b64 v[15:16], 4, v[1:2]
s_clause 0x1
global_load_b128 v[7:10], v2, s[20:21]
global_load_b128 v[11:14], v2, s[20:21] offset:16
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[19:20], 2, v[1:2]
v_add_co_u32 v15, vcc_lo, s2, v15
v_add_co_ci_u32_e32 v16, vcc_lo, s3, v16, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[27:28], 2, v[3:4]
v_add_co_u32 v29, s0, s4, v19
global_load_b128 v[15:18], v[15:16], off
global_load_b32 v75, v2, s[20:21] offset:32
v_add_nc_u32_e32 v21, 1, v3
v_add_nc_u32_e32 v1, s1, v1
v_add_co_ci_u32_e64 v30, s0, s5, v20, s0
v_add_co_u32 v31, s0, s6, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v32, s0, s7, v20, s0
v_add_co_u32 v33, s0, s8, v19
v_add_co_ci_u32_e64 v34, s0, s9, v20, s0
v_add_co_u32 v19, s0, s10, v19
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v20, s0, s11, v20, s0
s_waitcnt vmcnt(1)
v_mul_f32_e32 v4, v16, v8
v_mul_f32_e32 v8, v16, v11
v_add_nc_u32_e32 v23, 2, v3
v_mul_f32_e32 v11, v16, v14
v_cmp_le_u32_e32 vcc_lo, s28, v1
v_fmac_f32_e32 v4, v15, v7
v_dual_fmac_f32 v8, v15, v10 :: v_dual_add_nc_u32 v25, 3, v3
v_add_nc_u32_e32 v3, s22, v3
s_or_b32 s23, vcc_lo, s23
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v4, v17, v9
v_dual_fmac_f32 v8, v17, v12 :: v_dual_fmac_f32 v11, v15, v13
v_add_co_u32 v35, vcc_lo, s12, v27
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v4, 2.0, v4
v_add_f32_e32 v7, 2.0, v8
v_add_co_ci_u32_e32 v36, vcc_lo, s13, v28, vcc_lo
v_add_co_u32 v37, vcc_lo, s14, v27
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_add_f32 v9, 0.5, v4 :: v_dual_add_f32 v10, 0.5, v7
v_add_co_ci_u32_e32 v38, vcc_lo, s15, v28, vcc_lo
v_add_co_u32 v39, vcc_lo, s16, v27
v_floor_f32_e32 v9, v9
s_delay_alu instid0(VALU_DEP_4)
v_floor_f32_e32 v10, v10
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v11, v17, v75
v_ashrrev_i32_e32 v22, 31, v21
v_add_co_ci_u32_e32 v40, vcc_lo, s17, v28, vcc_lo
v_add_f32_e32 v10, -0.5, v10
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_add_f32 v8, 2.0, v11 :: v_dual_add_f32 v9, -0.5, v9
v_add_co_u32 v41, vcc_lo, s18, v27
v_ashrrev_i32_e32 v24, 31, v23
v_dual_add_f32 v11, 0.5, v8 :: v_dual_sub_f32 v4, v4, v9
v_add_co_ci_u32_e32 v42, vcc_lo, s19, v28, vcc_lo
v_lshlrev_b64 v[21:22], 2, v[21:22]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_floor_f32_e32 v11, v11
v_mul_f32_e32 v9, v4, v0
v_add_co_u32 v43, vcc_lo, s24, v27
v_ashrrev_i32_e32 v26, 31, v25
v_add_co_ci_u32_e32 v44, vcc_lo, s25, v28, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_cvt_i32_f32_e32 v9, v9
v_lshlrev_b64 v[23:24], 2, v[23:24]
v_add_co_u32 v27, vcc_lo, s26, v27
v_add_co_ci_u32_e32 v28, vcc_lo, s27, v28, vcc_lo
v_cvt_f32_i32_e32 v12, v9
v_lshlrev_b64 v[25:26], 2, v[25:26]
v_add_co_u32 v45, vcc_lo, s12, v21
v_add_co_ci_u32_e32 v46, vcc_lo, s13, v22, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_fma_f32 v4, v4, v0, -v12
v_sub_f32_e32 v7, v7, v10
v_add_co_u32 v47, vcc_lo, s12, v23
v_add_co_ci_u32_e32 v48, vcc_lo, s13, v24, vcc_lo
v_dual_mul_f32 v12, 0.5, v4 :: v_dual_add_f32 v11, -0.5, v11
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_mul_f32_e32 v10, v7, v5
v_add_co_u32 v49, vcc_lo, s12, v25
v_add_co_ci_u32_e32 v50, vcc_lo, s13, v26, vcc_lo
v_sub_f32_e32 v8, v8, v11
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cvt_i32_f32_e32 v10, v10
v_add_co_u32 v51, vcc_lo, s14, v21
v_add_co_ci_u32_e32 v52, vcc_lo, s15, v22, vcc_lo
v_mul_f32_e32 v11, v8, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cvt_f32_i32_e32 v13, v10
v_add_co_u32 v53, vcc_lo, s14, v23
v_add_co_ci_u32_e32 v54, vcc_lo, s15, v24, vcc_lo
v_cvt_i32_f32_e32 v11, v11
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_fma_f32 v7, v7, v5, -v13
v_add_co_u32 v55, vcc_lo, s14, v25
v_add_co_ci_u32_e32 v56, vcc_lo, s15, v26, vcc_lo
v_cvt_f32_i32_e32 v14, v11
v_add_co_u32 v57, vcc_lo, s16, v21
global_store_b32 v[19:20], v18, off
global_store_b32 v[29:30], v9, off
global_store_b32 v[31:32], v10, off
global_store_b32 v[33:34], v11, off
v_fma_f32 v8, v8, v6, -v14
v_dual_sub_f32 v9, 1.0, v4 :: v_dual_sub_f32 v18, 2.0, v7
v_dual_mul_f32 v13, 0.5, v7 :: v_dual_sub_f32 v16, 2.0, v4
v_add_co_ci_u32_e32 v58, vcc_lo, s17, v22, vcc_lo
v_add_co_u32 v59, vcc_lo, s16, v23
v_add_co_ci_u32_e32 v60, vcc_lo, s17, v24, vcc_lo
v_dual_sub_f32 v10, 1.0, v7 :: v_dual_sub_f32 v11, 1.0, v8
v_mul_f32_e32 v30, 0x3eaaaaab, v7
v_mul_f32_e32 v14, 0.5, v8
v_dual_add_f32 v15, 1.0, v4 :: v_dual_add_f32 v76, 2.0, v7
v_dual_add_f32 v17, 1.0, v7 :: v_dual_sub_f32 v20, 2.0, v8
v_dual_mul_f32 v29, 0x3eaaaaab, v4 :: v_dual_mul_f32 v78, -0.5, v9
v_dual_sub_f32 v32, 0x40400000, v4 :: v_dual_sub_f32 v33, 0x40400000, v7
v_dual_sub_f32 v34, 0x40400000, v8 :: v_dual_mul_f32 v13, v7, v13
v_dual_add_f32 v75, 2.0, v4 :: v_dual_mul_f32 v82, 0x3eaaaaab, v10
v_dual_mul_f32 v12, v4, v12 :: v_dual_mul_f32 v7, v7, v18
v_dual_mul_f32 v4, v4, v16 :: v_dual_mul_f32 v79, -0.5, v10
v_add_co_u32 v61, vcc_lo, s16, v25
v_add_co_ci_u32_e32 v62, vcc_lo, s17, v26, vcc_lo
v_add_co_u32 v63, vcc_lo, s18, v21
v_dual_add_f32 v19, 1.0, v8 :: v_dual_mul_f32 v14, v8, v14
v_dual_mul_f32 v31, 0x3eaaaaab, v8 :: v_dual_mul_f32 v80, -0.5, v11
v_dual_add_f32 v77, 2.0, v8 :: v_dual_fmac_f32 v4, v15, v9
v_dual_mul_f32 v8, v8, v20 :: v_dual_mul_f32 v81, 0x3eaaaaab, v9
v_fmac_f32_e32 v7, v17, v10
v_add_co_ci_u32_e32 v64, vcc_lo, s19, v22, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_fmac_f32_e32 v8, v19, v11
v_add_co_u32 v65, vcc_lo, s18, v23
v_add_co_ci_u32_e32 v66, vcc_lo, s19, v24, vcc_lo
v_add_co_u32 v67, vcc_lo, s18, v25
v_dual_mul_f32 v9, v9, v78 :: v_dual_mul_f32 v10, v10, v79
v_dual_mul_f32 v31, v31, v14 :: v_dual_mul_f32 v78, 0.5, v4
v_mul_f32_e32 v79, 0.5, v7
v_add_co_ci_u32_e32 v68, vcc_lo, s19, v26, vcc_lo
v_add_co_u32 v69, vcc_lo, s24, v21
v_add_co_ci_u32_e32 v70, vcc_lo, s25, v22, vcc_lo
v_dual_mul_f32 v83, 0x3eaaaaab, v11 :: v_dual_mul_f32 v30, v30, v13
v_dual_mul_f32 v11, v11, v80 :: v_dual_mul_f32 v16, v16, v78
v_mul_f32_e32 v80, 0.5, v8
v_dual_mul_f32 v29, v29, v12 :: v_dual_mul_f32 v18, v18, v79
v_add_co_u32 v71, vcc_lo, s24, v23
s_delay_alu instid0(VALU_DEP_3)
v_dual_mul_f32 v15, v15, v78 :: v_dual_mul_f32 v20, v20, v80
v_add_co_ci_u32_e32 v72, vcc_lo, s25, v24, vcc_lo
v_add_co_u32 v73, vcc_lo, s24, v25
v_fma_f32 v16, v75, -v9, v16
v_mul_f32_e32 v17, v17, v79
v_fma_f32 v18, v76, -v10, v18
v_mul_f32_e32 v19, v19, v80
v_add_co_ci_u32_e32 v74, vcc_lo, s25, v26, vcc_lo
v_add_co_u32 v21, vcc_lo, s26, v21
s_delay_alu instid0(VALU_DEP_4)
v_dual_mul_f32 v18, 0x3eaaaaab, v18 :: v_dual_fmac_f32 v15, v32, v12
v_add_co_ci_u32_e32 v22, vcc_lo, s27, v22, vcc_lo
v_add_co_u32 v23, vcc_lo, s26, v23
v_mul_f32_e64 v81, v81, -v9
v_fmac_f32_e32 v19, v34, v14
v_fma_f32 v20, v77, -v11, v20
v_dual_mul_f32 v16, 0x3eaaaaab, v16 :: v_dual_fmac_f32 v17, v33, v13
v_add_co_ci_u32_e32 v24, vcc_lo, s27, v24, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_dual_mul_f32 v20, 0x3eaaaaab, v20 :: v_dual_mul_f32 v15, 0x3eaaaaab, v15
v_add_co_u32 v25, vcc_lo, s26, v25
v_mul_f32_e64 v82, v82, -v10
v_add_co_ci_u32_e32 v26, vcc_lo, s27, v26, vcc_lo
v_fma_f32 v84, v4, -0.5, -v9
v_fma_f32 v85, v7, -0.5, -v10
v_fma_f32 v86, v8, -0.5, -v11
v_fma_f32 v4, v4, 0.5, -v12
v_fma_f32 v7, v7, 0.5, -v13
v_fma_f32 v8, v8, 0.5, -v14
v_mul_f32_e64 v83, v83, -v11
v_mul_f32_e32 v17, 0x3eaaaaab, v17
v_mul_f32_e32 v19, 0x3eaaaaab, v19
s_clause 0x3
global_store_b32 v[35:36], v81, off
global_store_b32 v[45:46], v16, off
global_store_b32 v[47:48], v15, off
global_store_b32 v[49:50], v29, off
s_clause 0x3
global_store_b32 v[37:38], v82, off
global_store_b32 v[51:52], v18, off
global_store_b32 v[53:54], v17, off
global_store_b32 v[55:56], v30, off
s_clause 0x3
global_store_b32 v[39:40], v83, off
global_store_b32 v[57:58], v20, off
global_store_b32 v[59:60], v19, off
global_store_b32 v[61:62], v31, off
s_clause 0x3
global_store_b32 v[41:42], v9, off
global_store_b32 v[63:64], v84, off
global_store_b32 v[65:66], v4, off
global_store_b32 v[67:68], v12, off
s_clause 0x3
global_store_b32 v[43:44], v10, off
global_store_b32 v[69:70], v85, off
global_store_b32 v[71:72], v7, off
global_store_b32 v[73:74], v13, off
s_clause 0x3
global_store_b32 v[27:28], v11, off
global_store_b32 v[21:22], v86, off
global_store_b32 v[23:24], v8, off
global_store_b32 v[25:26], v14, off
s_and_not1_b32 exec_lo, exec_lo, s23
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 376
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 87
.amdhsa_next_free_sgpr 32
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_, .Lfunc_end0-_Z14fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 80
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 88
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 96
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 104
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 112
.size: 8
.value_kind: global_buffer
- .offset: 120
.size: 4
.value_kind: hidden_block_count_x
- .offset: 124
.size: 4
.value_kind: hidden_block_count_y
- .offset: 128
.size: 4
.value_kind: hidden_block_count_z
- .offset: 132
.size: 2
.value_kind: hidden_group_size_x
- .offset: 134
.size: 2
.value_kind: hidden_group_size_y
- .offset: 136
.size: 2
.value_kind: hidden_group_size_z
- .offset: 138
.size: 2
.value_kind: hidden_remainder_x
- .offset: 140
.size: 2
.value_kind: hidden_remainder_y
- .offset: 142
.size: 2
.value_kind: hidden_remainder_z
- .offset: 160
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 168
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 176
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 184
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 376
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_
.private_segment_fixed_size: 0
.sgpr_count: 34
.sgpr_spill_count: 0
.symbol: _Z14fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 87
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0000f79c_00000000-6_fill_bspline_4.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z76__device_stub__Z14fill_bspline_4PK6float4iPKfiiiPiS4_S4_PfS5_S5_S5_S5_S5_S5_PK6float4iPKfiiiPiS4_S4_PfS5_S5_S5_S5_S5_S5_
.type _Z76__device_stub__Z14fill_bspline_4PK6float4iPKfiiiPiS4_S4_PfS5_S5_S5_S5_S5_S5_PK6float4iPKfiiiPiS4_S4_PfS5_S5_S5_S5_S5_S5_, @function
_Z76__device_stub__Z14fill_bspline_4PK6float4iPKfiiiPiS4_S4_PfS5_S5_S5_S5_S5_S5_PK6float4iPKfiiiPiS4_S4_PfS5_S5_S5_S5_S5_S5_:
.LFB2051:
.cfi_startproc
endbr64
subq $328, %rsp
.cfi_def_cfa_offset 336
movq %rdi, 104(%rsp)
movl %esi, 100(%rsp)
movq %rdx, 88(%rsp)
movl %ecx, 96(%rsp)
movl %r8d, 84(%rsp)
movl %r9d, 80(%rsp)
movq 336(%rsp), %rax
movq %rax, 72(%rsp)
movq 344(%rsp), %rax
movq %rax, 64(%rsp)
movq 352(%rsp), %rax
movq %rax, 56(%rsp)
movq 360(%rsp), %rax
movq %rax, 48(%rsp)
movq 368(%rsp), %rax
movq %rax, 40(%rsp)
movq 376(%rsp), %rax
movq %rax, 32(%rsp)
movq 384(%rsp), %rax
movq %rax, 24(%rsp)
movq 392(%rsp), %rax
movq %rax, 16(%rsp)
movq 400(%rsp), %rax
movq %rax, 8(%rsp)
movq 408(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 312(%rsp)
xorl %eax, %eax
leaq 104(%rsp), %rax
movq %rax, 176(%rsp)
leaq 100(%rsp), %rax
movq %rax, 184(%rsp)
leaq 88(%rsp), %rax
movq %rax, 192(%rsp)
leaq 96(%rsp), %rax
movq %rax, 200(%rsp)
leaq 84(%rsp), %rax
movq %rax, 208(%rsp)
leaq 80(%rsp), %rax
movq %rax, 216(%rsp)
leaq 72(%rsp), %rax
movq %rax, 224(%rsp)
leaq 64(%rsp), %rax
movq %rax, 232(%rsp)
leaq 56(%rsp), %rax
movq %rax, 240(%rsp)
leaq 48(%rsp), %rax
movq %rax, 248(%rsp)
leaq 40(%rsp), %rax
movq %rax, 256(%rsp)
leaq 32(%rsp), %rax
movq %rax, 264(%rsp)
leaq 24(%rsp), %rax
movq %rax, 272(%rsp)
leaq 16(%rsp), %rax
movq %rax, 280(%rsp)
leaq 8(%rsp), %rax
movq %rax, 288(%rsp)
movq %rsp, %rax
movq %rax, 296(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movl $1, 136(%rsp)
movl $1, 140(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
leaq 120(%rsp), %rcx
leaq 112(%rsp), %rdx
leaq 140(%rsp), %rsi
leaq 128(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 312(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $328, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 120(%rsp)
.cfi_def_cfa_offset 344
pushq 120(%rsp)
.cfi_def_cfa_offset 352
leaq 192(%rsp), %r9
movq 156(%rsp), %rcx
movl 164(%rsp), %r8d
movq 144(%rsp), %rsi
movl 152(%rsp), %edx
leaq _Z14fill_bspline_4PK6float4iPKfiiiPiS4_S4_PfS5_S5_S5_S5_S5_S5_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 336
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z76__device_stub__Z14fill_bspline_4PK6float4iPKfiiiPiS4_S4_PfS5_S5_S5_S5_S5_S5_PK6float4iPKfiiiPiS4_S4_PfS5_S5_S5_S5_S5_S5_, .-_Z76__device_stub__Z14fill_bspline_4PK6float4iPKfiiiPiS4_S4_PfS5_S5_S5_S5_S5_S5_PK6float4iPKfiiiPiS4_S4_PfS5_S5_S5_S5_S5_S5_
.globl _Z14fill_bspline_4PK6float4iPKfiiiPiS4_S4_PfS5_S5_S5_S5_S5_S5_
.type _Z14fill_bspline_4PK6float4iPKfiiiPiS4_S4_PfS5_S5_S5_S5_S5_S5_, @function
_Z14fill_bspline_4PK6float4iPKfiiiPiS4_S4_PfS5_S5_S5_S5_S5_S5_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 88(%rsp)
.cfi_def_cfa_offset 24
pushq 88(%rsp)
.cfi_def_cfa_offset 32
pushq 88(%rsp)
.cfi_def_cfa_offset 40
pushq 88(%rsp)
.cfi_def_cfa_offset 48
pushq 88(%rsp)
.cfi_def_cfa_offset 56
pushq 88(%rsp)
.cfi_def_cfa_offset 64
pushq 88(%rsp)
.cfi_def_cfa_offset 72
pushq 88(%rsp)
.cfi_def_cfa_offset 80
pushq 88(%rsp)
.cfi_def_cfa_offset 88
pushq 88(%rsp)
.cfi_def_cfa_offset 96
call _Z76__device_stub__Z14fill_bspline_4PK6float4iPKfiiiPiS4_S4_PfS5_S5_S5_S5_S5_S5_PK6float4iPKfiiiPiS4_S4_PfS5_S5_S5_S5_S5_S5_
addq $88, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14fill_bspline_4PK6float4iPKfiiiPiS4_S4_PfS5_S5_S5_S5_S5_S5_, .-_Z14fill_bspline_4PK6float4iPKfiiiPiS4_S4_PfS5_S5_S5_S5_S5_S5_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z14fill_bspline_4PK6float4iPKfiiiPiS4_S4_PfS5_S5_S5_S5_S5_S5_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14fill_bspline_4PK6float4iPKfiiiPiS4_S4_PfS5_S5_S5_S5_S5_S5_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "fill_bspline_4.hip"
.globl _Z29__device_stub__fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_ # -- Begin function _Z29__device_stub__fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_
.p2align 4, 0x90
.type _Z29__device_stub__fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_,@function
_Z29__device_stub__fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_: # @_Z29__device_stub__fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 224(%rsp), %rax
movq %rax, 128(%rsp)
leaq 232(%rsp), %rax
movq %rax, 136(%rsp)
leaq 240(%rsp), %rax
movq %rax, 144(%rsp)
leaq 248(%rsp), %rax
movq %rax, 152(%rsp)
leaq 256(%rsp), %rax
movq %rax, 160(%rsp)
leaq 264(%rsp), %rax
movq %rax, 168(%rsp)
leaq 272(%rsp), %rax
movq %rax, 176(%rsp)
leaq 280(%rsp), %rax
movq %rax, 184(%rsp)
leaq 288(%rsp), %rax
movq %rax, 192(%rsp)
leaq 296(%rsp), %rax
movq %rax, 200(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end0:
.size _Z29__device_stub__fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_, .Lfunc_end0-_Z29__device_stub__fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_,@object # @_Z14fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_
.section .rodata,"a",@progbits
.globl _Z14fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_
.p2align 3, 0x0
_Z14fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_:
.quad _Z29__device_stub__fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_
.size _Z14fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_"
.size .L__unnamed_1, 80
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14fill_bspline_4PK15HIP_vector_typeIfLj4EEiPKfiiiPiS5_S5_PfS6_S6_S6_S6_S6_S6_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <assert.h>
const int N = 1<<10;
__global__ void cuda_hello(int * a){
for (int i=threadIdx.x+blockIdx.x*blockDim.x; i < N; i+=gridDim.x*blockDim.x) {
a[i] *= 2;
}
}
int main(void) {
int *a;
cudaMallocManaged(&a, sizeof(int)*N);
for (int i=0; i<N; i++) {
a[i] = i;
}
int blocks = N/256;
cuda_hello<<<blocks,256>>>(a);
cudaDeviceSynchronize();
for (int i=0; i<N; i++) {
assert(a[i] == i*2);
}
cudaFree(a);
return 0;
} | code for sm_80
Function : _Z10cuda_helloPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R0, 0x3ff, PT ; /* 0x000003ff0000780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ MOV R7, c[0x0][0xc] ; /* 0x0000030000077a02 */
/* 0x000fca0000000f00 */
/*00b0*/ IMAD R0, R7, c[0x0][0x0], R0 ; /* 0x0000000007007a24 */
/* 0x000fca00078e0200 */
/*00c0*/ ISETP.GE.AND P0, PT, R0, 0x400, PT ; /* 0x000004000000780c */
/* 0x000fe40003f06270 */
/*00d0*/ SHF.L.U32 R5, R4, 0x1, RZ ; /* 0x0000000104057819 */
/* 0x004fca00000006ff */
/*00e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001ec000c101904 */
/*00f0*/ @!P0 BRA 0x70 ; /* 0xffffff7000008947 */
/* 0x000fea000383ffff */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <assert.h>
const int N = 1<<10;
__global__ void cuda_hello(int * a){
for (int i=threadIdx.x+blockIdx.x*blockDim.x; i < N; i+=gridDim.x*blockDim.x) {
a[i] *= 2;
}
}
int main(void) {
int *a;
cudaMallocManaged(&a, sizeof(int)*N);
for (int i=0; i<N; i++) {
a[i] = i;
}
int blocks = N/256;
cuda_hello<<<blocks,256>>>(a);
cudaDeviceSynchronize();
for (int i=0; i<N; i++) {
assert(a[i] == i*2);
}
cudaFree(a);
return 0;
} | .file "tmpxft_000ffce1_00000000-6_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z10cuda_helloPiPi
.type _Z30__device_stub__Z10cuda_helloPiPi, @function
_Z30__device_stub__Z10cuda_helloPiPi:
.LFB2052:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10cuda_helloPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z30__device_stub__Z10cuda_helloPiPi, .-_Z30__device_stub__Z10cuda_helloPiPi
.globl _Z10cuda_helloPi
.type _Z10cuda_helloPi, @function
_Z10cuda_helloPi:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10cuda_helloPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z10cuda_helloPi, .-_Z10cuda_helloPi
.globl main
.type main, @function
main:
.LFB2027:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $4096, %esi
call cudaMallocManaged@PLT
movl $0, %eax
.L12:
movq 8(%rsp), %rdx
movl %eax, (%rdx,%rax,4)
addq $1, %rax
cmpq $1024, %rax
jne .L12
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $4, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
call cudaDeviceSynchronize@PLT
movl $1024, %eax
.L14:
subl $1, %eax
jne .L14
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z30__device_stub__Z10cuda_helloPiPi
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10cuda_helloPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10cuda_helloPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <assert.h>
const int N = 1<<10;
__global__ void cuda_hello(int * a){
for (int i=threadIdx.x+blockIdx.x*blockDim.x; i < N; i+=gridDim.x*blockDim.x) {
a[i] *= 2;
}
}
int main(void) {
int *a;
cudaMallocManaged(&a, sizeof(int)*N);
for (int i=0; i<N; i++) {
a[i] = i;
}
int blocks = N/256;
cuda_hello<<<blocks,256>>>(a);
cudaDeviceSynchronize();
for (int i=0; i<N; i++) {
assert(a[i] == i*2);
}
cudaFree(a);
return 0;
} | #include <hip/hip_runtime.h>
#include <assert.h>
const int N = 1<<10;
__global__ void cuda_hello(int * a){
for (int i=threadIdx.x+blockIdx.x*blockDim.x; i < N; i+=gridDim.x*blockDim.x) {
a[i] *= 2;
}
}
int main(void) {
int *a;
hipMallocManaged(&a, sizeof(int)*N);
for (int i=0; i<N; i++) {
a[i] = i;
}
int blocks = N/256;
cuda_hello<<<blocks,256>>>(a);
hipDeviceSynchronize();
for (int i=0; i<N; i++) {
assert(a[i] == i*2);
}
hipFree(a);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <assert.h>
const int N = 1<<10;
__global__ void cuda_hello(int * a){
for (int i=threadIdx.x+blockIdx.x*blockDim.x; i < N; i+=gridDim.x*blockDim.x) {
a[i] *= 2;
}
}
int main(void) {
int *a;
hipMallocManaged(&a, sizeof(int)*N);
for (int i=0; i<N; i++) {
a[i] = i;
}
int blocks = N/256;
cuda_hello<<<blocks,256>>>(a);
hipDeviceSynchronize();
for (int i=0; i<N; i++) {
assert(a[i] == i*2);
}
hipFree(a);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10cuda_helloPi
.globl _Z10cuda_helloPi
.p2align 8
.type _Z10cuda_helloPi,@function
_Z10cuda_helloPi:
s_load_b32 s4, s[0:1], 0x14
s_add_u32 s2, s0, 8
s_addc_u32 s3, s1, 0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_cmpx_gt_i32_e32 0x400, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b64 s[0:1], s[0:1], 0x0
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s4
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v1, s2, v1
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 0x3ff, v1
global_load_b32 v0, v[2:3], off
s_or_b32 s3, vcc_lo, s3
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v0, 1, v0
global_store_b32 v[2:3], v0, off
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10cuda_helloPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10cuda_helloPi, .Lfunc_end0-_Z10cuda_helloPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10cuda_helloPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10cuda_helloPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <assert.h>
const int N = 1<<10;
__global__ void cuda_hello(int * a){
for (int i=threadIdx.x+blockIdx.x*blockDim.x; i < N; i+=gridDim.x*blockDim.x) {
a[i] *= 2;
}
}
int main(void) {
int *a;
hipMallocManaged(&a, sizeof(int)*N);
for (int i=0; i<N; i++) {
a[i] = i;
}
int blocks = N/256;
cuda_hello<<<blocks,256>>>(a);
hipDeviceSynchronize();
for (int i=0; i<N; i++) {
assert(a[i] == i*2);
}
hipFree(a);
return 0;
} | .text
.file "hello.hip"
.globl _Z25__device_stub__cuda_helloPi # -- Begin function _Z25__device_stub__cuda_helloPi
.p2align 4, 0x90
.type _Z25__device_stub__cuda_helloPi,@function
_Z25__device_stub__cuda_helloPi: # @_Z25__device_stub__cuda_helloPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10cuda_helloPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z25__device_stub__cuda_helloPi, .Lfunc_end0-_Z25__device_stub__cuda_helloPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
movl $1, %edx
callq hipMallocManaged
xorl %eax, %eax
movq 8(%rsp), %rcx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%rcx,%rax,4)
incq %rax
cmpq $1024, %rax # imm = 0x400
jne .LBB1_1
# %bb.2:
movabsq $4294967300, %rdi # imm = 0x100000004
leaq 252(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z10cuda_helloPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10cuda_helloPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10cuda_helloPi,@object # @_Z10cuda_helloPi
.section .rodata,"a",@progbits
.globl _Z10cuda_helloPi
.p2align 3, 0x0
_Z10cuda_helloPi:
.quad _Z25__device_stub__cuda_helloPi
.size _Z10cuda_helloPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10cuda_helloPi"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__cuda_helloPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10cuda_helloPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10cuda_helloPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R0, 0x3ff, PT ; /* 0x000003ff0000780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ MOV R7, c[0x0][0xc] ; /* 0x0000030000077a02 */
/* 0x000fca0000000f00 */
/*00b0*/ IMAD R0, R7, c[0x0][0x0], R0 ; /* 0x0000000007007a24 */
/* 0x000fca00078e0200 */
/*00c0*/ ISETP.GE.AND P0, PT, R0, 0x400, PT ; /* 0x000004000000780c */
/* 0x000fe40003f06270 */
/*00d0*/ SHF.L.U32 R5, R4, 0x1, RZ ; /* 0x0000000104057819 */
/* 0x004fca00000006ff */
/*00e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001ec000c101904 */
/*00f0*/ @!P0 BRA 0x70 ; /* 0xffffff7000008947 */
/* 0x000fea000383ffff */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10cuda_helloPi
.globl _Z10cuda_helloPi
.p2align 8
.type _Z10cuda_helloPi,@function
_Z10cuda_helloPi:
s_load_b32 s4, s[0:1], 0x14
s_add_u32 s2, s0, 8
s_addc_u32 s3, s1, 0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_cmpx_gt_i32_e32 0x400, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b64 s[0:1], s[0:1], 0x0
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s4
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v1, s2, v1
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 0x3ff, v1
global_load_b32 v0, v[2:3], off
s_or_b32 s3, vcc_lo, s3
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v0, 1, v0
global_store_b32 v[2:3], v0, off
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10cuda_helloPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10cuda_helloPi, .Lfunc_end0-_Z10cuda_helloPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10cuda_helloPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10cuda_helloPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ffce1_00000000-6_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z10cuda_helloPiPi
.type _Z30__device_stub__Z10cuda_helloPiPi, @function
_Z30__device_stub__Z10cuda_helloPiPi:
.LFB2052:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10cuda_helloPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z30__device_stub__Z10cuda_helloPiPi, .-_Z30__device_stub__Z10cuda_helloPiPi
.globl _Z10cuda_helloPi
.type _Z10cuda_helloPi, @function
_Z10cuda_helloPi:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10cuda_helloPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z10cuda_helloPi, .-_Z10cuda_helloPi
.globl main
.type main, @function
main:
.LFB2027:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $4096, %esi
call cudaMallocManaged@PLT
movl $0, %eax
.L12:
movq 8(%rsp), %rdx
movl %eax, (%rdx,%rax,4)
addq $1, %rax
cmpq $1024, %rax
jne .L12
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $4, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
call cudaDeviceSynchronize@PLT
movl $1024, %eax
.L14:
subl $1, %eax
jne .L14
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z30__device_stub__Z10cuda_helloPiPi
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10cuda_helloPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10cuda_helloPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hello.hip"
.globl _Z25__device_stub__cuda_helloPi # -- Begin function _Z25__device_stub__cuda_helloPi
.p2align 4, 0x90
.type _Z25__device_stub__cuda_helloPi,@function
_Z25__device_stub__cuda_helloPi: # @_Z25__device_stub__cuda_helloPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10cuda_helloPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z25__device_stub__cuda_helloPi, .Lfunc_end0-_Z25__device_stub__cuda_helloPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
movl $1, %edx
callq hipMallocManaged
xorl %eax, %eax
movq 8(%rsp), %rcx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%rcx,%rax,4)
incq %rax
cmpq $1024, %rax # imm = 0x400
jne .LBB1_1
# %bb.2:
movabsq $4294967300, %rdi # imm = 0x100000004
leaq 252(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z10cuda_helloPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10cuda_helloPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10cuda_helloPi,@object # @_Z10cuda_helloPi
.section .rodata,"a",@progbits
.globl _Z10cuda_helloPi
.p2align 3, 0x0
_Z10cuda_helloPi:
.quad _Z25__device_stub__cuda_helloPi
.size _Z10cuda_helloPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10cuda_helloPi"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__cuda_helloPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10cuda_helloPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__ void VecAdd(float * A, float * B, float * C)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
C[i] = A[i] + B[i];
}
void VecPrint(float * V, int len)
{
int to_print = 10;
if (to_print > len)
to_print = len;
for (int i=0; i<to_print; i++)
{
printf("%4.2f", V[i]);
if (i<to_print-1)
printf(", ");
}
if (to_print < len)
printf("...");
printf("\n");
}
int main()
{
int N = 1024;
size_t size = N * sizeof(float);
// Allocate input vectors h_A, h_B and h_C in host memory
float* h_A = (float*)malloc(size);
float* h_B = (float*)malloc(size);
float* h_C = (float*)malloc(size);
// Initialize input vectors
for (int i=0; i<N; i++)
{
h_A[i] = 2*i+1;
h_B[i] = 4*i+1;
h_C[i] = 0;
}
// Print initialised vectors
VecPrint(h_A, N);
VecPrint(h_B, N);
VecPrint(h_C, N);
// Allocate vectors in device memory
float* d_A;
cudaMalloc(&d_A, size);
float* d_B;
cudaMalloc(&d_B, size);
float* d_C;
cudaMalloc(&d_C, size);
// Copy vectors from host memory to device memory
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
// Run the add kernel
int blocks = 3;
int threads_per_block = N/blocks;
VecAdd<<<blocks, threads_per_block>>>(d_A, d_B, d_C);
// Print result
cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
VecPrint(h_C, N);
// Free device memory
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
// Free host memory
delete[] h_A;
delete[] h_B;
return 0;
} | code for sm_80
Function : _Z6VecAddPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00b0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__ void VecAdd(float * A, float * B, float * C)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
C[i] = A[i] + B[i];
}
void VecPrint(float * V, int len)
{
int to_print = 10;
if (to_print > len)
to_print = len;
for (int i=0; i<to_print; i++)
{
printf("%4.2f", V[i]);
if (i<to_print-1)
printf(", ");
}
if (to_print < len)
printf("...");
printf("\n");
}
int main()
{
int N = 1024;
size_t size = N * sizeof(float);
// Allocate input vectors h_A, h_B and h_C in host memory
float* h_A = (float*)malloc(size);
float* h_B = (float*)malloc(size);
float* h_C = (float*)malloc(size);
// Initialize input vectors
for (int i=0; i<N; i++)
{
h_A[i] = 2*i+1;
h_B[i] = 4*i+1;
h_C[i] = 0;
}
// Print initialised vectors
VecPrint(h_A, N);
VecPrint(h_B, N);
VecPrint(h_C, N);
// Allocate vectors in device memory
float* d_A;
cudaMalloc(&d_A, size);
float* d_B;
cudaMalloc(&d_B, size);
float* d_C;
cudaMalloc(&d_C, size);
// Copy vectors from host memory to device memory
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
// Run the add kernel
int blocks = 3;
int threads_per_block = N/blocks;
VecAdd<<<blocks, threads_per_block>>>(d_A, d_B, d_C);
// Print result
cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
VecPrint(h_C, N);
// Free device memory
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
// Free host memory
delete[] h_A;
delete[] h_B;
return 0;
} | .file "tmpxft_0006098b_00000000-6_vecadd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%4.2f"
.LC1:
.string ", "
.LC2:
.string "..."
.LC3:
.string "\n"
.text
.globl _Z8VecPrintPfi
.type _Z8VecPrintPfi, @function
_Z8VecPrintPfi:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movl %esi, %r15d
movl $10, %ebp
cmpl %ebp, %esi
cmovle %esi, %ebp
testl %esi, %esi
jle .L4
movq %rdi, %r12
movl $0, %ebx
leaq .LC0(%rip), %r14
leal -1(%rbp), %r13d
jmp .L6
.L5:
addq $1, %rbx
cmpl %ebx, %ebp
jle .L4
.L6:
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
cmpl %ebx, %r13d
jle .L5
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L5
.L4:
cmpl %ebp, %r15d
jg .L10
.L7:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L7
.cfi_endproc
.LFE2057:
.size _Z8VecPrintPfi, .-_Z8VecPrintPfi
.globl _Z29__device_stub__Z6VecAddPfS_S_PfS_S_
.type _Z29__device_stub__Z6VecAddPfS_S_PfS_S_, @function
_Z29__device_stub__Z6VecAddPfS_S_PfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6VecAddPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z29__device_stub__Z6VecAddPfS_S_PfS_S_, .-_Z29__device_stub__Z6VecAddPfS_S_PfS_S_
.globl _Z6VecAddPfS_S_
.type _Z6VecAddPfS_S_, @function
_Z6VecAddPfS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6VecAddPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z6VecAddPfS_S_, .-_Z6VecAddPfS_S_
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4096, %edi
call malloc@PLT
movq %rax, %rbp
movl $4096, %edi
call malloc@PLT
movq %rax, %rbx
movl $4096, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %eax
movl $1, %edx
.L20:
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, 0(%rbp,%rax)
leal 1(%rax), %ecx
pxor %xmm0, %xmm0
cvtsi2ssl %ecx, %xmm0
movss %xmm0, (%rbx,%rax)
movl $0x00000000, (%r12,%rax)
addl $2, %edx
addq $4, %rax
cmpl $2049, %edx
jne .L20
movl $1024, %esi
movq %rbp, %rdi
call _Z8VecPrintPfi
movl $1024, %esi
movq %rbx, %rdi
call _Z8VecPrintPfi
movl $1024, %esi
movq %r12, %rdi
call _Z8VecPrintPfi
leaq 8(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4096, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4096, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $341, 44(%rsp)
movl $1, 48(%rsp)
movl $3, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movl $2, %ecx
movl $4096, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $1024, %esi
movq %r12, %rdi
call _Z8VecPrintPfi
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z29__device_stub__Z6VecAddPfS_S_PfS_S_
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z6VecAddPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z6VecAddPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__ void VecAdd(float * A, float * B, float * C)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
C[i] = A[i] + B[i];
}
void VecPrint(float * V, int len)
{
int to_print = 10;
if (to_print > len)
to_print = len;
for (int i=0; i<to_print; i++)
{
printf("%4.2f", V[i]);
if (i<to_print-1)
printf(", ");
}
if (to_print < len)
printf("...");
printf("\n");
}
int main()
{
int N = 1024;
size_t size = N * sizeof(float);
// Allocate input vectors h_A, h_B and h_C in host memory
float* h_A = (float*)malloc(size);
float* h_B = (float*)malloc(size);
float* h_C = (float*)malloc(size);
// Initialize input vectors
for (int i=0; i<N; i++)
{
h_A[i] = 2*i+1;
h_B[i] = 4*i+1;
h_C[i] = 0;
}
// Print initialised vectors
VecPrint(h_A, N);
VecPrint(h_B, N);
VecPrint(h_C, N);
// Allocate vectors in device memory
float* d_A;
cudaMalloc(&d_A, size);
float* d_B;
cudaMalloc(&d_B, size);
float* d_C;
cudaMalloc(&d_C, size);
// Copy vectors from host memory to device memory
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
// Run the add kernel
int blocks = 3;
int threads_per_block = N/blocks;
VecAdd<<<blocks, threads_per_block>>>(d_A, d_B, d_C);
// Print result
cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
VecPrint(h_C, N);
// Free device memory
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
// Free host memory
delete[] h_A;
delete[] h_B;
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void VecAdd(float * A, float * B, float * C)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
C[i] = A[i] + B[i];
}
void VecPrint(float * V, int len)
{
int to_print = 10;
if (to_print > len)
to_print = len;
for (int i=0; i<to_print; i++)
{
printf("%4.2f", V[i]);
if (i<to_print-1)
printf(", ");
}
if (to_print < len)
printf("...");
printf("\n");
}
int main()
{
int N = 1024;
size_t size = N * sizeof(float);
// Allocate input vectors h_A, h_B and h_C in host memory
float* h_A = (float*)malloc(size);
float* h_B = (float*)malloc(size);
float* h_C = (float*)malloc(size);
// Initialize input vectors
for (int i=0; i<N; i++)
{
h_A[i] = 2*i+1;
h_B[i] = 4*i+1;
h_C[i] = 0;
}
// Print initialised vectors
VecPrint(h_A, N);
VecPrint(h_B, N);
VecPrint(h_C, N);
// Allocate vectors in device memory
float* d_A;
hipMalloc(&d_A, size);
float* d_B;
hipMalloc(&d_B, size);
float* d_C;
hipMalloc(&d_C, size);
// Copy vectors from host memory to device memory
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
// Run the add kernel
int blocks = 3;
int threads_per_block = N/blocks;
VecAdd<<<blocks, threads_per_block>>>(d_A, d_B, d_C);
// Print result
hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
VecPrint(h_C, N);
// Free device memory
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
// Free host memory
delete[] h_A;
delete[] h_B;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void VecAdd(float * A, float * B, float * C)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
C[i] = A[i] + B[i];
}
void VecPrint(float * V, int len)
{
int to_print = 10;
if (to_print > len)
to_print = len;
for (int i=0; i<to_print; i++)
{
printf("%4.2f", V[i]);
if (i<to_print-1)
printf(", ");
}
if (to_print < len)
printf("...");
printf("\n");
}
int main()
{
int N = 1024;
size_t size = N * sizeof(float);
// Allocate input vectors h_A, h_B and h_C in host memory
float* h_A = (float*)malloc(size);
float* h_B = (float*)malloc(size);
float* h_C = (float*)malloc(size);
// Initialize input vectors
for (int i=0; i<N; i++)
{
h_A[i] = 2*i+1;
h_B[i] = 4*i+1;
h_C[i] = 0;
}
// Print initialised vectors
VecPrint(h_A, N);
VecPrint(h_B, N);
VecPrint(h_C, N);
// Allocate vectors in device memory
float* d_A;
hipMalloc(&d_A, size);
float* d_B;
hipMalloc(&d_B, size);
float* d_C;
hipMalloc(&d_C, size);
// Copy vectors from host memory to device memory
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
// Run the add kernel
int blocks = 3;
int threads_per_block = N/blocks;
VecAdd<<<blocks, threads_per_block>>>(d_A, d_B, d_C);
// Print result
hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
VecPrint(h_C, N);
// Free device memory
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
// Free host memory
delete[] h_A;
delete[] h_B;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6VecAddPfS_S_
.globl _Z6VecAddPfS_S_
.p2align 8
.type _Z6VecAddPfS_S_,@function
_Z6VecAddPfS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6VecAddPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6VecAddPfS_S_, .Lfunc_end0-_Z6VecAddPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6VecAddPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6VecAddPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void VecAdd(float * A, float * B, float * C)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
C[i] = A[i] + B[i];
}
void VecPrint(float * V, int len)
{
int to_print = 10;
if (to_print > len)
to_print = len;
for (int i=0; i<to_print; i++)
{
printf("%4.2f", V[i]);
if (i<to_print-1)
printf(", ");
}
if (to_print < len)
printf("...");
printf("\n");
}
int main()
{
int N = 1024;
size_t size = N * sizeof(float);
// Allocate input vectors h_A, h_B and h_C in host memory
float* h_A = (float*)malloc(size);
float* h_B = (float*)malloc(size);
float* h_C = (float*)malloc(size);
// Initialize input vectors
for (int i=0; i<N; i++)
{
h_A[i] = 2*i+1;
h_B[i] = 4*i+1;
h_C[i] = 0;
}
// Print initialised vectors
VecPrint(h_A, N);
VecPrint(h_B, N);
VecPrint(h_C, N);
// Allocate vectors in device memory
float* d_A;
hipMalloc(&d_A, size);
float* d_B;
hipMalloc(&d_B, size);
float* d_C;
hipMalloc(&d_C, size);
// Copy vectors from host memory to device memory
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
// Run the add kernel
int blocks = 3;
int threads_per_block = N/blocks;
VecAdd<<<blocks, threads_per_block>>>(d_A, d_B, d_C);
// Print result
hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
VecPrint(h_C, N);
// Free device memory
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
// Free host memory
delete[] h_A;
delete[] h_B;
return 0;
} | .text
.file "vecadd.hip"
.globl _Z21__device_stub__VecAddPfS_S_ # -- Begin function _Z21__device_stub__VecAddPfS_S_
.p2align 4, 0x90
.type _Z21__device_stub__VecAddPfS_S_,@function
_Z21__device_stub__VecAddPfS_S_: # @_Z21__device_stub__VecAddPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6VecAddPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__VecAddPfS_S_, .Lfunc_end0-_Z21__device_stub__VecAddPfS_S_
.cfi_endproc
# -- End function
.globl _Z8VecPrintPfi # -- Begin function _Z8VecPrintPfi
.p2align 4, 0x90
.type _Z8VecPrintPfi,@function
_Z8VecPrintPfi: # @_Z8VecPrintPfi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %esi, %ebx
testl %esi, %esi
jle .LBB1_5
# %bb.1: # %.lr.ph
movq %rdi, %r14
cmpl $10, %ebx
movl $10, %r15d
cmovll %ebx, %r15d
leal -1(%r15), %eax
movslq %eax, %r12
xorl %r13d, %r13d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_4: # in Loop: Header=BB1_2 Depth=1
incq %r13
cmpq %r13, %r15
je .LBB1_5
.LBB1_2: # =>This Inner Loop Header: Depth=1
movss (%r14,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
cmpq %r12, %r13
jge .LBB1_4
# %bb.3: # in Loop: Header=BB1_2 Depth=1
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
jmp .LBB1_4
.LBB1_5: # %._crit_edge
cmpl $10, %ebx
jle .LBB1_7
# %bb.6:
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
.LBB1_7:
movl $10, %edi
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp putchar@PLT # TAILCALL
.Lfunc_end1:
.size _Z8VecPrintPfi, .Lfunc_end1-_Z8VecPrintPfi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r14
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %rbx
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r15
xorl %r12d, %r12d
movl $4096, %edx # imm = 0x1000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
movl $1, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
leal 1(%r12), %ecx
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%r14,%r12,2)
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%r12,2)
addl $4, %eax
addq $2, %r12
cmpq $2048, %r12 # imm = 0x800
jne .LBB2_1
# %bb.2: # %.preheader.preheader
xorl %r12d, %r12d
jmp .LBB2_3
.p2align 4, 0x90
.LBB2_5: # in Loop: Header=BB2_3 Depth=1
incq %r12
cmpq $10, %r12
je .LBB2_6
.LBB2_3: # %.preheader
# =>This Inner Loop Header: Depth=1
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
cmpq $8, %r12
ja .LBB2_5
# %bb.4: # in Loop: Header=BB2_3 Depth=1
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
jmp .LBB2_5
.LBB2_6: # %_Z8VecPrintPfi.exit
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
xorl %r12d, %r12d
jmp .LBB2_7
.p2align 4, 0x90
.LBB2_9: # in Loop: Header=BB2_7 Depth=1
incq %r12
cmpq $10, %r12
je .LBB2_10
.LBB2_7: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
cmpq $8, %r12
ja .LBB2_9
# %bb.8: # in Loop: Header=BB2_7 Depth=1
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
jmp .LBB2_9
.LBB2_10: # %_Z8VecPrintPfi.exit45
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
xorl %r12d, %r12d
jmp .LBB2_11
.p2align 4, 0x90
.LBB2_13: # in Loop: Header=BB2_11 Depth=1
incq %r12
cmpq $10, %r12
je .LBB2_14
.LBB2_11: # =>This Inner Loop Header: Depth=1
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
cmpq $8, %r12
ja .LBB2_13
# %bb.12: # in Loop: Header=BB2_11 Depth=1
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
jmp .LBB2_13
.LBB2_14: # %_Z8VecPrintPfi.exit50
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
leaq 16(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movq %rsp, %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movq 16(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967299, %rdi # imm = 0x100000003
leaq 338(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_16
# %bb.15:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6VecAddPfS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_16:
movq (%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
jmp .LBB2_17
.p2align 4, 0x90
.LBB2_19: # in Loop: Header=BB2_17 Depth=1
incq %r12
cmpq $10, %r12
je .LBB2_20
.LBB2_17: # =>This Inner Loop Header: Depth=1
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
cmpq $8, %r12
ja .LBB2_19
# %bb.18: # in Loop: Header=BB2_17 Depth=1
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
jmp .LBB2_19
.LBB2_20: # %_Z8VecPrintPfi.exit55
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
testq %r14, %r14
je .LBB2_22
# %bb.21:
movq %r14, %rdi
callq _ZdaPv
.LBB2_22:
testq %rbx, %rbx
je .LBB2_24
# %bb.23:
movq %rbx, %rdi
callq _ZdaPv
.LBB2_24:
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6VecAddPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6VecAddPfS_S_,@object # @_Z6VecAddPfS_S_
.section .rodata,"a",@progbits
.globl _Z6VecAddPfS_S_
.p2align 3, 0x0
_Z6VecAddPfS_S_:
.quad _Z21__device_stub__VecAddPfS_S_
.size _Z6VecAddPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%4.2f"
.size .L.str, 6
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz ", "
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "..."
.size .L.str.2, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6VecAddPfS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__VecAddPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6VecAddPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6VecAddPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00b0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6VecAddPfS_S_
.globl _Z6VecAddPfS_S_
.p2align 8
.type _Z6VecAddPfS_S_,@function
_Z6VecAddPfS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6VecAddPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6VecAddPfS_S_, .Lfunc_end0-_Z6VecAddPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6VecAddPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6VecAddPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0006098b_00000000-6_vecadd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%4.2f"
.LC1:
.string ", "
.LC2:
.string "..."
.LC3:
.string "\n"
.text
.globl _Z8VecPrintPfi
.type _Z8VecPrintPfi, @function
_Z8VecPrintPfi:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movl %esi, %r15d
movl $10, %ebp
cmpl %ebp, %esi
cmovle %esi, %ebp
testl %esi, %esi
jle .L4
movq %rdi, %r12
movl $0, %ebx
leaq .LC0(%rip), %r14
leal -1(%rbp), %r13d
jmp .L6
.L5:
addq $1, %rbx
cmpl %ebx, %ebp
jle .L4
.L6:
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
cmpl %ebx, %r13d
jle .L5
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L5
.L4:
cmpl %ebp, %r15d
jg .L10
.L7:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L7
.cfi_endproc
.LFE2057:
.size _Z8VecPrintPfi, .-_Z8VecPrintPfi
.globl _Z29__device_stub__Z6VecAddPfS_S_PfS_S_
.type _Z29__device_stub__Z6VecAddPfS_S_PfS_S_, @function
_Z29__device_stub__Z6VecAddPfS_S_PfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6VecAddPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z29__device_stub__Z6VecAddPfS_S_PfS_S_, .-_Z29__device_stub__Z6VecAddPfS_S_PfS_S_
.globl _Z6VecAddPfS_S_
.type _Z6VecAddPfS_S_, @function
_Z6VecAddPfS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6VecAddPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z6VecAddPfS_S_, .-_Z6VecAddPfS_S_
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4096, %edi
call malloc@PLT
movq %rax, %rbp
movl $4096, %edi
call malloc@PLT
movq %rax, %rbx
movl $4096, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %eax
movl $1, %edx
.L20:
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, 0(%rbp,%rax)
leal 1(%rax), %ecx
pxor %xmm0, %xmm0
cvtsi2ssl %ecx, %xmm0
movss %xmm0, (%rbx,%rax)
movl $0x00000000, (%r12,%rax)
addl $2, %edx
addq $4, %rax
cmpl $2049, %edx
jne .L20
movl $1024, %esi
movq %rbp, %rdi
call _Z8VecPrintPfi
movl $1024, %esi
movq %rbx, %rdi
call _Z8VecPrintPfi
movl $1024, %esi
movq %r12, %rdi
call _Z8VecPrintPfi
leaq 8(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4096, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4096, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $341, 44(%rsp)
movl $1, 48(%rsp)
movl $3, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movl $2, %ecx
movl $4096, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $1024, %esi
movq %r12, %rdi
call _Z8VecPrintPfi
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z29__device_stub__Z6VecAddPfS_S_PfS_S_
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z6VecAddPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z6VecAddPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vecadd.hip"
.globl _Z21__device_stub__VecAddPfS_S_ # -- Begin function _Z21__device_stub__VecAddPfS_S_
.p2align 4, 0x90
.type _Z21__device_stub__VecAddPfS_S_,@function
_Z21__device_stub__VecAddPfS_S_: # @_Z21__device_stub__VecAddPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6VecAddPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__VecAddPfS_S_, .Lfunc_end0-_Z21__device_stub__VecAddPfS_S_
.cfi_endproc
# -- End function
.globl _Z8VecPrintPfi # -- Begin function _Z8VecPrintPfi
.p2align 4, 0x90
.type _Z8VecPrintPfi,@function
_Z8VecPrintPfi: # @_Z8VecPrintPfi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %esi, %ebx
testl %esi, %esi
jle .LBB1_5
# %bb.1: # %.lr.ph
movq %rdi, %r14
cmpl $10, %ebx
movl $10, %r15d
cmovll %ebx, %r15d
leal -1(%r15), %eax
movslq %eax, %r12
xorl %r13d, %r13d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_4: # in Loop: Header=BB1_2 Depth=1
incq %r13
cmpq %r13, %r15
je .LBB1_5
.LBB1_2: # =>This Inner Loop Header: Depth=1
movss (%r14,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
cmpq %r12, %r13
jge .LBB1_4
# %bb.3: # in Loop: Header=BB1_2 Depth=1
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
jmp .LBB1_4
.LBB1_5: # %._crit_edge
cmpl $10, %ebx
jle .LBB1_7
# %bb.6:
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
.LBB1_7:
movl $10, %edi
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp putchar@PLT # TAILCALL
.Lfunc_end1:
.size _Z8VecPrintPfi, .Lfunc_end1-_Z8VecPrintPfi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r14
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %rbx
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r15
xorl %r12d, %r12d
movl $4096, %edx # imm = 0x1000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
movl $1, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
leal 1(%r12), %ecx
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%r14,%r12,2)
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%r12,2)
addl $4, %eax
addq $2, %r12
cmpq $2048, %r12 # imm = 0x800
jne .LBB2_1
# %bb.2: # %.preheader.preheader
xorl %r12d, %r12d
jmp .LBB2_3
.p2align 4, 0x90
.LBB2_5: # in Loop: Header=BB2_3 Depth=1
incq %r12
cmpq $10, %r12
je .LBB2_6
.LBB2_3: # %.preheader
# =>This Inner Loop Header: Depth=1
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
cmpq $8, %r12
ja .LBB2_5
# %bb.4: # in Loop: Header=BB2_3 Depth=1
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
jmp .LBB2_5
.LBB2_6: # %_Z8VecPrintPfi.exit
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
xorl %r12d, %r12d
jmp .LBB2_7
.p2align 4, 0x90
.LBB2_9: # in Loop: Header=BB2_7 Depth=1
incq %r12
cmpq $10, %r12
je .LBB2_10
.LBB2_7: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
cmpq $8, %r12
ja .LBB2_9
# %bb.8: # in Loop: Header=BB2_7 Depth=1
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
jmp .LBB2_9
.LBB2_10: # %_Z8VecPrintPfi.exit45
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
xorl %r12d, %r12d
jmp .LBB2_11
.p2align 4, 0x90
.LBB2_13: # in Loop: Header=BB2_11 Depth=1
incq %r12
cmpq $10, %r12
je .LBB2_14
.LBB2_11: # =>This Inner Loop Header: Depth=1
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
cmpq $8, %r12
ja .LBB2_13
# %bb.12: # in Loop: Header=BB2_11 Depth=1
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
jmp .LBB2_13
.LBB2_14: # %_Z8VecPrintPfi.exit50
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
leaq 16(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movq %rsp, %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movq 16(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967299, %rdi # imm = 0x100000003
leaq 338(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_16
# %bb.15:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6VecAddPfS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_16:
movq (%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
jmp .LBB2_17
.p2align 4, 0x90
.LBB2_19: # in Loop: Header=BB2_17 Depth=1
incq %r12
cmpq $10, %r12
je .LBB2_20
.LBB2_17: # =>This Inner Loop Header: Depth=1
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
cmpq $8, %r12
ja .LBB2_19
# %bb.18: # in Loop: Header=BB2_17 Depth=1
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
jmp .LBB2_19
.LBB2_20: # %_Z8VecPrintPfi.exit55
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
testq %r14, %r14
je .LBB2_22
# %bb.21:
movq %r14, %rdi
callq _ZdaPv
.LBB2_22:
testq %rbx, %rbx
je .LBB2_24
# %bb.23:
movq %rbx, %rdi
callq _ZdaPv
.LBB2_24:
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6VecAddPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6VecAddPfS_S_,@object # @_Z6VecAddPfS_S_
.section .rodata,"a",@progbits
.globl _Z6VecAddPfS_S_
.p2align 3, 0x0
_Z6VecAddPfS_S_:
.quad _Z21__device_stub__VecAddPfS_S_
.size _Z6VecAddPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%4.2f"
.size .L.str, 6
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz ", "
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "..."
.size .L.str.2, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6VecAddPfS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__VecAddPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6VecAddPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* madd_gpu.cu -- Device code for matrix additon benchmark
*
* Michael McThrow
*/
#define get_element_index(i, j, cols) ((i) * (cols) + (j))
__global__ void madd_kernel(unsigned int *a, unsigned int *b, unsigned int *c,
unsigned int rows, unsigned int cols)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int index = get_element_index(row, col, cols);
c[index] = a[index] + b[index];
} | code for sm_80
Function : _Z11madd_kernelPjS_S_jj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0050*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0060*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fc400078e0203 */
/*0080*/ IMAD R3, R2, c[0x0][0x0], R5 ; /* 0x0000000002037a24 */
/* 0x002fc800078e0205 */
/*0090*/ IMAD R0, R0, c[0x0][0x17c], R3 ; /* 0x00005f0000007a24 */
/* 0x000fc800078e0203 */
/*00a0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0207 */
/*00b0*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0207 */
/*00c0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0207 */
/*00f0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*0100*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* madd_gpu.cu -- Device code for matrix additon benchmark
*
* Michael McThrow
*/
#define get_element_index(i, j, cols) ((i) * (cols) + (j))
__global__ void madd_kernel(unsigned int *a, unsigned int *b, unsigned int *c,
unsigned int rows, unsigned int cols)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int index = get_element_index(row, col, cols);
c[index] = a[index] + b[index];
} | .file "tmpxft_0010420e_00000000-6_madd_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z11madd_kernelPjS_S_jjPjS_S_jj
.type _Z37__device_stub__Z11madd_kernelPjS_S_jjPjS_S_jj, @function
_Z37__device_stub__Z11madd_kernelPjS_S_jjPjS_S_jj:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11madd_kernelPjS_S_jj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z11madd_kernelPjS_S_jjPjS_S_jj, .-_Z37__device_stub__Z11madd_kernelPjS_S_jjPjS_S_jj
.globl _Z11madd_kernelPjS_S_jj
.type _Z11madd_kernelPjS_S_jj, @function
_Z11madd_kernelPjS_S_jj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z11madd_kernelPjS_S_jjPjS_S_jj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11madd_kernelPjS_S_jj, .-_Z11madd_kernelPjS_S_jj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11madd_kernelPjS_S_jj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11madd_kernelPjS_S_jj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* madd_gpu.cu -- Device code for matrix additon benchmark
*
* Michael McThrow
*/
#define get_element_index(i, j, cols) ((i) * (cols) + (j))
__global__ void madd_kernel(unsigned int *a, unsigned int *b, unsigned int *c,
unsigned int rows, unsigned int cols)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int index = get_element_index(row, col, cols);
c[index] = a[index] + b[index];
} | #include <hip/hip_runtime.h>
/*
* madd_gpu.cu -- Device code for matrix additon benchmark
*
* Michael McThrow
*/
#define get_element_index(i, j, cols) ((i) * (cols) + (j))
__global__ void madd_kernel(unsigned int *a, unsigned int *b, unsigned int *c,
unsigned int rows, unsigned int cols)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int index = get_element_index(row, col, cols);
c[index] = a[index] + b[index];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/*
* madd_gpu.cu -- Device code for matrix additon benchmark
*
* Michael McThrow
*/
#define get_element_index(i, j, cols) ((i) * (cols) + (j))
__global__ void madd_kernel(unsigned int *a, unsigned int *b, unsigned int *c,
unsigned int rows, unsigned int cols)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int index = get_element_index(row, col, cols);
c[index] = a[index] + b[index];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11madd_kernelPjS_S_jj
.globl _Z11madd_kernelPjS_S_jj
.p2align 8
.type _Z11madd_kernelPjS_S_jj,@function
_Z11madd_kernelPjS_S_jj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x1c
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_load_b128 s[4:7], s[0:1], 0x0
s_mul_i32 s14, s14, s2
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v2, s3
v_add3_u32 v0, s14, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11madd_kernelPjS_S_jj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11madd_kernelPjS_S_jj, .Lfunc_end0-_Z11madd_kernelPjS_S_jj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11madd_kernelPjS_S_jj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11madd_kernelPjS_S_jj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*
* madd_gpu.cu -- Device code for matrix additon benchmark
*
* Michael McThrow
*/
#define get_element_index(i, j, cols) ((i) * (cols) + (j))
__global__ void madd_kernel(unsigned int *a, unsigned int *b, unsigned int *c,
unsigned int rows, unsigned int cols)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int index = get_element_index(row, col, cols);
c[index] = a[index] + b[index];
} | .text
.file "madd_gpu.hip"
.globl _Z26__device_stub__madd_kernelPjS_S_jj # -- Begin function _Z26__device_stub__madd_kernelPjS_S_jj
.p2align 4, 0x90
.type _Z26__device_stub__madd_kernelPjS_S_jj,@function
_Z26__device_stub__madd_kernelPjS_S_jj: # @_Z26__device_stub__madd_kernelPjS_S_jj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11madd_kernelPjS_S_jj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__madd_kernelPjS_S_jj, .Lfunc_end0-_Z26__device_stub__madd_kernelPjS_S_jj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11madd_kernelPjS_S_jj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11madd_kernelPjS_S_jj,@object # @_Z11madd_kernelPjS_S_jj
.section .rodata,"a",@progbits
.globl _Z11madd_kernelPjS_S_jj
.p2align 3, 0x0
_Z11madd_kernelPjS_S_jj:
.quad _Z26__device_stub__madd_kernelPjS_S_jj
.size _Z11madd_kernelPjS_S_jj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11madd_kernelPjS_S_jj"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__madd_kernelPjS_S_jj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11madd_kernelPjS_S_jj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11madd_kernelPjS_S_jj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0050*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0060*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fc400078e0203 */
/*0080*/ IMAD R3, R2, c[0x0][0x0], R5 ; /* 0x0000000002037a24 */
/* 0x002fc800078e0205 */
/*0090*/ IMAD R0, R0, c[0x0][0x17c], R3 ; /* 0x00005f0000007a24 */
/* 0x000fc800078e0203 */
/*00a0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0207 */
/*00b0*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0207 */
/*00c0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0207 */
/*00f0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*0100*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11madd_kernelPjS_S_jj
.globl _Z11madd_kernelPjS_S_jj
.p2align 8
.type _Z11madd_kernelPjS_S_jj,@function
_Z11madd_kernelPjS_S_jj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x1c
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_load_b128 s[4:7], s[0:1], 0x0
s_mul_i32 s14, s14, s2
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v2, s3
v_add3_u32 v0, s14, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11madd_kernelPjS_S_jj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11madd_kernelPjS_S_jj, .Lfunc_end0-_Z11madd_kernelPjS_S_jj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11madd_kernelPjS_S_jj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11madd_kernelPjS_S_jj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010420e_00000000-6_madd_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z11madd_kernelPjS_S_jjPjS_S_jj
.type _Z37__device_stub__Z11madd_kernelPjS_S_jjPjS_S_jj, @function
_Z37__device_stub__Z11madd_kernelPjS_S_jjPjS_S_jj:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11madd_kernelPjS_S_jj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z11madd_kernelPjS_S_jjPjS_S_jj, .-_Z37__device_stub__Z11madd_kernelPjS_S_jjPjS_S_jj
.globl _Z11madd_kernelPjS_S_jj
.type _Z11madd_kernelPjS_S_jj, @function
_Z11madd_kernelPjS_S_jj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z11madd_kernelPjS_S_jjPjS_S_jj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11madd_kernelPjS_S_jj, .-_Z11madd_kernelPjS_S_jj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11madd_kernelPjS_S_jj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11madd_kernelPjS_S_jj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "madd_gpu.hip"
.globl _Z26__device_stub__madd_kernelPjS_S_jj # -- Begin function _Z26__device_stub__madd_kernelPjS_S_jj
.p2align 4, 0x90
.type _Z26__device_stub__madd_kernelPjS_S_jj,@function
_Z26__device_stub__madd_kernelPjS_S_jj: # @_Z26__device_stub__madd_kernelPjS_S_jj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11madd_kernelPjS_S_jj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__madd_kernelPjS_S_jj, .Lfunc_end0-_Z26__device_stub__madd_kernelPjS_S_jj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11madd_kernelPjS_S_jj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11madd_kernelPjS_S_jj,@object # @_Z11madd_kernelPjS_S_jj
.section .rodata,"a",@progbits
.globl _Z11madd_kernelPjS_S_jj
.p2align 3, 0x0
_Z11madd_kernelPjS_S_jj:
.quad _Z26__device_stub__madd_kernelPjS_S_jj
.size _Z11madd_kernelPjS_S_jj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11madd_kernelPjS_S_jj"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__madd_kernelPjS_S_jj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11madd_kernelPjS_S_jj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void reset_states_u_after_spikes_kernel(float *d_states_u, float * d_param_d, float* d_last_spike_time_of_each_neuron, float current_time_in_seconds, size_t total_number_of_neurons) {
int idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < total_number_of_neurons) {
if (d_last_spike_time_of_each_neuron[idx] == current_time_in_seconds) {
d_states_u[idx] += d_param_d[idx];
}
idx += blockDim.x * gridDim.x;
}
__syncthreads();
} | code for sm_80
Function : _Z34reset_states_u_after_spikes_kernelPfS_S_fm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ BSSY B0, 0x220 ; /* 0x000001f000007945 */
/* 0x000fe60003800000 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0050*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe40003f06070 */
/*0060*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x000fc80000011400 */
/*0070*/ ISETP.GE.U32.AND.EX P0, PT, R2, c[0x0][0x184], PT, P0 ; /* 0x0000610002007a0c */
/* 0x000fda0003f06100 */
/*0080*/ @P0 BRA 0x210 ; /* 0x0000018000000947 */
/* 0x000fea0003800000 */
/*0090*/ IMAD.MOV.U32 R5, RZ, RZ, R2 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0002 */
/*00a0*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0000 */
/*00b0*/ IMAD.SHL.U32 R2, R4.reuse, 0x4, RZ ; /* 0x0000000404027824 */
/* 0x040fe200078e00ff */
/*00c0*/ SHF.L.U64.HI R3, R4, 0x2, R5 ; /* 0x0000000204037819 */
/* 0x000fe20000010205 */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00e0*/ IADD3 R4, P0, R2, c[0x0][0x170], RZ ; /* 0x00005c0002047a10 */
/* 0x000fc80007f1e0ff */
/*00f0*/ IADD3.X R5, R3, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0003057a10 */
/* 0x000fca00007fe4ff */
/*0100*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*0110*/ FSETP.NEU.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0b */
/* 0x004fda0003f0d000 */
/*0120*/ @!P0 IADD3 R6, P1, R2.reuse, c[0x0][0x168], RZ ; /* 0x00005a0002068a10 */
/* 0x040fe40007f3e0ff */
/*0130*/ @!P0 IADD3 R2, P2, R2, c[0x0][0x160], RZ ; /* 0x0000580002028a10 */
/* 0x000fe40007f5e0ff */
/*0140*/ @!P0 IADD3.X R7, R3.reuse, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0003078a10 */
/* 0x040fe40000ffe4ff */
/*0150*/ @!P0 IADD3.X R3, R3, c[0x0][0x164], RZ, P2, !PT ; /* 0x0000590003038a10 */
/* 0x000fc800017fe4ff */
/*0160*/ @!P0 LDG.E R7, [R6.64] ; /* 0x0000000406078981 */
/* 0x000ea8000c1e1900 */
/*0170*/ @!P0 LDG.E R8, [R2.64] ; /* 0x0000000402088981 */
/* 0x000ea2000c1e1900 */
/*0180*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0b7624 */
/* 0x000fc800078e00ff */
/*0190*/ IMAD R4, R11, c[0x0][0xc], R0 ; /* 0x000003000b047a24 */
/* 0x000fc800078e0200 */
/*01a0*/ IMAD.MOV.U32 R0, RZ, RZ, R4.reuse ; /* 0x000000ffff007224 */
/* 0x100fe200078e0004 */
/*01b0*/ SHF.R.S32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x000fe20000011404 */
/*01c0*/ @!P0 FADD R9, R8, R7 ; /* 0x0000000708098221 */
/* 0x004fca0000000000 */
/*01d0*/ @!P0 STG.E [R2.64], R9 ; /* 0x0000000902008986 */
/* 0x0001e2000c101904 */
/*01e0*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x180], PT ; /* 0x0000600004007a0c */
/* 0x000fc80003f06070 */
/*01f0*/ ISETP.GE.U32.AND.EX P0, PT, R5, c[0x0][0x184], PT, P0 ; /* 0x0000610005007a0c */
/* 0x000fda0003f06100 */
/*0200*/ @!P0 BRA 0xb0 ; /* 0xfffffea000008947 */
/* 0x001fea000383ffff */
/*0210*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0220*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0230*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0240*/ BRA 0x240; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void reset_states_u_after_spikes_kernel(float *d_states_u, float * d_param_d, float* d_last_spike_time_of_each_neuron, float current_time_in_seconds, size_t total_number_of_neurons) {
int idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < total_number_of_neurons) {
if (d_last_spike_time_of_each_neuron[idx] == current_time_in_seconds) {
d_states_u[idx] += d_param_d[idx];
}
idx += blockDim.x * gridDim.x;
}
__syncthreads();
} | .file "tmpxft_000be3f8_00000000-6_reset_states_u_after_spikes_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z60__device_stub__Z34reset_states_u_after_spikes_kernelPfS_S_fmPfS_S_fm
.type _Z60__device_stub__Z34reset_states_u_after_spikes_kernelPfS_S_fmPfS_S_fm, @function
_Z60__device_stub__Z34reset_states_u_after_spikes_kernelPfS_S_fmPfS_S_fm:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movss %xmm0, 20(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z34reset_states_u_after_spikes_kernelPfS_S_fm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z60__device_stub__Z34reset_states_u_after_spikes_kernelPfS_S_fmPfS_S_fm, .-_Z60__device_stub__Z34reset_states_u_after_spikes_kernelPfS_S_fmPfS_S_fm
.globl _Z34reset_states_u_after_spikes_kernelPfS_S_fm
.type _Z34reset_states_u_after_spikes_kernelPfS_S_fm, @function
_Z34reset_states_u_after_spikes_kernelPfS_S_fm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z60__device_stub__Z34reset_states_u_after_spikes_kernelPfS_S_fmPfS_S_fm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z34reset_states_u_after_spikes_kernelPfS_S_fm, .-_Z34reset_states_u_after_spikes_kernelPfS_S_fm
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z34reset_states_u_after_spikes_kernelPfS_S_fm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z34reset_states_u_after_spikes_kernelPfS_S_fm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void reset_states_u_after_spikes_kernel(float *d_states_u, float * d_param_d, float* d_last_spike_time_of_each_neuron, float current_time_in_seconds, size_t total_number_of_neurons) {
int idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < total_number_of_neurons) {
if (d_last_spike_time_of_each_neuron[idx] == current_time_in_seconds) {
d_states_u[idx] += d_param_d[idx];
}
idx += blockDim.x * gridDim.x;
}
__syncthreads();
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void reset_states_u_after_spikes_kernel(float *d_states_u, float * d_param_d, float* d_last_spike_time_of_each_neuron, float current_time_in_seconds, size_t total_number_of_neurons) {
int idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < total_number_of_neurons) {
if (d_last_spike_time_of_each_neuron[idx] == current_time_in_seconds) {
d_states_u[idx] += d_param_d[idx];
}
idx += blockDim.x * gridDim.x;
}
__syncthreads();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void reset_states_u_after_spikes_kernel(float *d_states_u, float * d_param_d, float* d_last_spike_time_of_each_neuron, float current_time_in_seconds, size_t total_number_of_neurons) {
int idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < total_number_of_neurons) {
if (d_last_spike_time_of_each_neuron[idx] == current_time_in_seconds) {
d_states_u[idx] += d_param_d[idx];
}
idx += blockDim.x * gridDim.x;
}
__syncthreads();
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z34reset_states_u_after_spikes_kernelPfS_S_fm
.globl _Z34reset_states_u_after_spikes_kernelPfS_S_fm
.p2align 8
.type _Z34reset_states_u_after_spikes_kernelPfS_S_fm,@function
_Z34reset_states_u_after_spikes_kernelPfS_S_fm:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x20
s_add_u32 s4, s0, 40
s_addc_u32 s5, s1, 0
s_mov_b32 s10, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s11, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s15, s11, v[0:1]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[2:3], v[3:4]
s_cbranch_execz .LBB0_5
s_load_b32 s12, s[4:5], 0x0
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b32 s0, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_add_i32 s15, s15, s12
s_mul_i32 s1, s12, s11
v_mad_u64_u32 v[1:2], null, s15, s11, v[0:1]
s_mov_b32 s11, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s12
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[1:2]
v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
v_add_nc_u32_e32 v1, s1, v1
s_or_b32 s11, vcc_lo, s11
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execz .LBB0_5
.LBB0_3:
v_lshlrev_b64 v[2:3], 2, v[3:4]
s_mov_b32 s12, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
global_load_b32 v0, v[4:5], off
s_waitcnt vmcnt(0)
v_cmpx_eq_f32_e32 s0, v0
s_cbranch_execz .LBB0_2
v_add_co_u32 v4, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v4
global_store_b32 v[2:3], v0, off
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s10
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z34reset_states_u_after_spikes_kernelPfS_S_fm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z34reset_states_u_after_spikes_kernelPfS_S_fm, .Lfunc_end0-_Z34reset_states_u_after_spikes_kernelPfS_S_fm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z34reset_states_u_after_spikes_kernelPfS_S_fm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z34reset_states_u_after_spikes_kernelPfS_S_fm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void reset_states_u_after_spikes_kernel(float *d_states_u, float * d_param_d, float* d_last_spike_time_of_each_neuron, float current_time_in_seconds, size_t total_number_of_neurons) {
int idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < total_number_of_neurons) {
if (d_last_spike_time_of_each_neuron[idx] == current_time_in_seconds) {
d_states_u[idx] += d_param_d[idx];
}
idx += blockDim.x * gridDim.x;
}
__syncthreads();
} | .text
.file "reset_states_u_after_spikes_kernel.hip"
.globl _Z49__device_stub__reset_states_u_after_spikes_kernelPfS_S_fm # -- Begin function _Z49__device_stub__reset_states_u_after_spikes_kernelPfS_S_fm
.p2align 4, 0x90
.type _Z49__device_stub__reset_states_u_after_spikes_kernelPfS_S_fm,@function
_Z49__device_stub__reset_states_u_after_spikes_kernelPfS_S_fm: # @_Z49__device_stub__reset_states_u_after_spikes_kernelPfS_S_fm
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movss %xmm0, 12(%rsp)
movq %rcx, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z34reset_states_u_after_spikes_kernelPfS_S_fm, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z49__device_stub__reset_states_u_after_spikes_kernelPfS_S_fm, .Lfunc_end0-_Z49__device_stub__reset_states_u_after_spikes_kernelPfS_S_fm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z34reset_states_u_after_spikes_kernelPfS_S_fm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z34reset_states_u_after_spikes_kernelPfS_S_fm,@object # @_Z34reset_states_u_after_spikes_kernelPfS_S_fm
.section .rodata,"a",@progbits
.globl _Z34reset_states_u_after_spikes_kernelPfS_S_fm
.p2align 3, 0x0
_Z34reset_states_u_after_spikes_kernelPfS_S_fm:
.quad _Z49__device_stub__reset_states_u_after_spikes_kernelPfS_S_fm
.size _Z34reset_states_u_after_spikes_kernelPfS_S_fm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z34reset_states_u_after_spikes_kernelPfS_S_fm"
.size .L__unnamed_1, 47
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z49__device_stub__reset_states_u_after_spikes_kernelPfS_S_fm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z34reset_states_u_after_spikes_kernelPfS_S_fm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z34reset_states_u_after_spikes_kernelPfS_S_fm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ BSSY B0, 0x220 ; /* 0x000001f000007945 */
/* 0x000fe60003800000 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0050*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe40003f06070 */
/*0060*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x000fc80000011400 */
/*0070*/ ISETP.GE.U32.AND.EX P0, PT, R2, c[0x0][0x184], PT, P0 ; /* 0x0000610002007a0c */
/* 0x000fda0003f06100 */
/*0080*/ @P0 BRA 0x210 ; /* 0x0000018000000947 */
/* 0x000fea0003800000 */
/*0090*/ IMAD.MOV.U32 R5, RZ, RZ, R2 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0002 */
/*00a0*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0000 */
/*00b0*/ IMAD.SHL.U32 R2, R4.reuse, 0x4, RZ ; /* 0x0000000404027824 */
/* 0x040fe200078e00ff */
/*00c0*/ SHF.L.U64.HI R3, R4, 0x2, R5 ; /* 0x0000000204037819 */
/* 0x000fe20000010205 */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00e0*/ IADD3 R4, P0, R2, c[0x0][0x170], RZ ; /* 0x00005c0002047a10 */
/* 0x000fc80007f1e0ff */
/*00f0*/ IADD3.X R5, R3, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0003057a10 */
/* 0x000fca00007fe4ff */
/*0100*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*0110*/ FSETP.NEU.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0b */
/* 0x004fda0003f0d000 */
/*0120*/ @!P0 IADD3 R6, P1, R2.reuse, c[0x0][0x168], RZ ; /* 0x00005a0002068a10 */
/* 0x040fe40007f3e0ff */
/*0130*/ @!P0 IADD3 R2, P2, R2, c[0x0][0x160], RZ ; /* 0x0000580002028a10 */
/* 0x000fe40007f5e0ff */
/*0140*/ @!P0 IADD3.X R7, R3.reuse, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0003078a10 */
/* 0x040fe40000ffe4ff */
/*0150*/ @!P0 IADD3.X R3, R3, c[0x0][0x164], RZ, P2, !PT ; /* 0x0000590003038a10 */
/* 0x000fc800017fe4ff */
/*0160*/ @!P0 LDG.E R7, [R6.64] ; /* 0x0000000406078981 */
/* 0x000ea8000c1e1900 */
/*0170*/ @!P0 LDG.E R8, [R2.64] ; /* 0x0000000402088981 */
/* 0x000ea2000c1e1900 */
/*0180*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0b7624 */
/* 0x000fc800078e00ff */
/*0190*/ IMAD R4, R11, c[0x0][0xc], R0 ; /* 0x000003000b047a24 */
/* 0x000fc800078e0200 */
/*01a0*/ IMAD.MOV.U32 R0, RZ, RZ, R4.reuse ; /* 0x000000ffff007224 */
/* 0x100fe200078e0004 */
/*01b0*/ SHF.R.S32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x000fe20000011404 */
/*01c0*/ @!P0 FADD R9, R8, R7 ; /* 0x0000000708098221 */
/* 0x004fca0000000000 */
/*01d0*/ @!P0 STG.E [R2.64], R9 ; /* 0x0000000902008986 */
/* 0x0001e2000c101904 */
/*01e0*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x180], PT ; /* 0x0000600004007a0c */
/* 0x000fc80003f06070 */
/*01f0*/ ISETP.GE.U32.AND.EX P0, PT, R5, c[0x0][0x184], PT, P0 ; /* 0x0000610005007a0c */
/* 0x000fda0003f06100 */
/*0200*/ @!P0 BRA 0xb0 ; /* 0xfffffea000008947 */
/* 0x001fea000383ffff */
/*0210*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0220*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0230*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0240*/ BRA 0x240; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z34reset_states_u_after_spikes_kernelPfS_S_fm
.globl _Z34reset_states_u_after_spikes_kernelPfS_S_fm
.p2align 8
.type _Z34reset_states_u_after_spikes_kernelPfS_S_fm,@function
_Z34reset_states_u_after_spikes_kernelPfS_S_fm:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x20
s_add_u32 s4, s0, 40
s_addc_u32 s5, s1, 0
s_mov_b32 s10, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s11, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s15, s11, v[0:1]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[2:3], v[3:4]
s_cbranch_execz .LBB0_5
s_load_b32 s12, s[4:5], 0x0
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b32 s0, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_add_i32 s15, s15, s12
s_mul_i32 s1, s12, s11
v_mad_u64_u32 v[1:2], null, s15, s11, v[0:1]
s_mov_b32 s11, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s12
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[1:2]
v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
v_add_nc_u32_e32 v1, s1, v1
s_or_b32 s11, vcc_lo, s11
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execz .LBB0_5
.LBB0_3:
v_lshlrev_b64 v[2:3], 2, v[3:4]
s_mov_b32 s12, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
global_load_b32 v0, v[4:5], off
s_waitcnt vmcnt(0)
v_cmpx_eq_f32_e32 s0, v0
s_cbranch_execz .LBB0_2
v_add_co_u32 v4, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v4
global_store_b32 v[2:3], v0, off
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s10
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z34reset_states_u_after_spikes_kernelPfS_S_fm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z34reset_states_u_after_spikes_kernelPfS_S_fm, .Lfunc_end0-_Z34reset_states_u_after_spikes_kernelPfS_S_fm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z34reset_states_u_after_spikes_kernelPfS_S_fm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z34reset_states_u_after_spikes_kernelPfS_S_fm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000be3f8_00000000-6_reset_states_u_after_spikes_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z60__device_stub__Z34reset_states_u_after_spikes_kernelPfS_S_fmPfS_S_fm
.type _Z60__device_stub__Z34reset_states_u_after_spikes_kernelPfS_S_fmPfS_S_fm, @function
_Z60__device_stub__Z34reset_states_u_after_spikes_kernelPfS_S_fmPfS_S_fm:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movss %xmm0, 20(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z34reset_states_u_after_spikes_kernelPfS_S_fm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z60__device_stub__Z34reset_states_u_after_spikes_kernelPfS_S_fmPfS_S_fm, .-_Z60__device_stub__Z34reset_states_u_after_spikes_kernelPfS_S_fmPfS_S_fm
.globl _Z34reset_states_u_after_spikes_kernelPfS_S_fm
.type _Z34reset_states_u_after_spikes_kernelPfS_S_fm, @function
_Z34reset_states_u_after_spikes_kernelPfS_S_fm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z60__device_stub__Z34reset_states_u_after_spikes_kernelPfS_S_fmPfS_S_fm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z34reset_states_u_after_spikes_kernelPfS_S_fm, .-_Z34reset_states_u_after_spikes_kernelPfS_S_fm
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z34reset_states_u_after_spikes_kernelPfS_S_fm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z34reset_states_u_after_spikes_kernelPfS_S_fm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "reset_states_u_after_spikes_kernel.hip"
.globl _Z49__device_stub__reset_states_u_after_spikes_kernelPfS_S_fm # -- Begin function _Z49__device_stub__reset_states_u_after_spikes_kernelPfS_S_fm
.p2align 4, 0x90
.type _Z49__device_stub__reset_states_u_after_spikes_kernelPfS_S_fm,@function
_Z49__device_stub__reset_states_u_after_spikes_kernelPfS_S_fm: # @_Z49__device_stub__reset_states_u_after_spikes_kernelPfS_S_fm
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movss %xmm0, 12(%rsp)
movq %rcx, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z34reset_states_u_after_spikes_kernelPfS_S_fm, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z49__device_stub__reset_states_u_after_spikes_kernelPfS_S_fm, .Lfunc_end0-_Z49__device_stub__reset_states_u_after_spikes_kernelPfS_S_fm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z34reset_states_u_after_spikes_kernelPfS_S_fm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z34reset_states_u_after_spikes_kernelPfS_S_fm,@object # @_Z34reset_states_u_after_spikes_kernelPfS_S_fm
.section .rodata,"a",@progbits
.globl _Z34reset_states_u_after_spikes_kernelPfS_S_fm
.p2align 3, 0x0
_Z34reset_states_u_after_spikes_kernelPfS_S_fm:
.quad _Z49__device_stub__reset_states_u_after_spikes_kernelPfS_S_fm
.size _Z34reset_states_u_after_spikes_kernelPfS_S_fm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z34reset_states_u_after_spikes_kernelPfS_S_fm"
.size .L__unnamed_1, 47
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z49__device_stub__reset_states_u_after_spikes_kernelPfS_S_fm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z34reset_states_u_after_spikes_kernelPfS_S_fm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <stdio.h>
#include <math.h>
#include <time.h>
//============================= GPU Kernel ====================================
__global__
void d_add(int n, float *x, float *y)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
y[i] = x[i] + y[i];
}
//============================= CPU ===========================================
// function to add the elements of two arrays
void add(int n, float *x, float *y)
{
// loop through array and add element by element
for (int i = 0; i < n; i++)
y[i] = x[i] + y[i];
}
// CPU WRAPPER
int add_cpu(void){
int N = 1<<25; // 1M elements
printf("Number of elements: %d\n",N);
float *x = new float[N];
float *y = new float[N];
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
// Run kernel on 1M elements on the CPU
clock_t begin = clock();
add(N, x, y);
clock_t end = clock();
double time_spent = (double)(end - begin) / CLOCKS_PER_SEC;
printf("CPU Time: %f seconds\n", time_spent);
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(y[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;
// Free memory
delete [] x;
delete [] y;
return 0;
}
// GPU WRAPPER
int add_gpu(void){
int N = 1<<25;
float *x, *y;
// Allocate Unified Memory – accessible from CPU or GPU
cudaMallocManaged(&x, N*sizeof(float));
cudaMallocManaged(&y, N*sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
// Run kernel on 1M elements on the GPU
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
clock_t begin = clock();
d_add<<<numBlocks, blockSize>>>(N, x, y);
// Wait for GPU to finish before accessing on host
cudaDeviceSynchronize();
clock_t end = clock();
double time_spent = (double)(end - begin) / CLOCKS_PER_SEC;
printf("GPU Time: %f seconds\n", time_spent);
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(y[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;
// Free memory
cudaFree(x);
cudaFree(y);
return 0;
}
int main(void)
{
add_cpu();
add_gpu();
} | code for sm_80
Function : _Z5d_addiPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ; /* 0x0000580003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x320 ; /* 0x0000029000007945 */
/* 0x000fe60003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*00b0*/ IMAD.MOV R9, RZ, RZ, -R0 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a00 */
/*00c0*/ IADD3 R2, R0.reuse, R3, RZ ; /* 0x0000000300027210 */
/* 0x040fe40007ffe0ff */
/*00d0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45070 */
/*00e0*/ LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff077212 */
/* 0x000fc800078e33ff */
/*00f0*/ IADD3 R7, R7, c[0x0][0x160], R0 ; /* 0x0000580007077a10 */
/* 0x000fe20007ffe000 */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0130*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*0140*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x002fd200078e02ff */
/*0150*/ IMAD.HI.U32 R2, R5, R9, R4 ; /* 0x0000000905027227 */
/* 0x000fcc00078e0004 */
/*0160*/ IMAD.HI.U32 R2, R2, R7, RZ ; /* 0x0000000702027227 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD.MOV R4, RZ, RZ, -R2 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a02 */
/*0180*/ IMAD R7, R0, R4, R7 ; /* 0x0000000400077224 */
/* 0x000fca00078e0207 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f06070 */
/*01a0*/ @P0 IADD3 R7, -R0, R7, RZ ; /* 0x0000000700070210 */
/* 0x000fe40007ffe1ff */
/*01b0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*01d0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*01f0*/ IADD3 R4, R2.reuse, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x040fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0210*/ LOP3.LUT P0, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fda000780c0ff */
/*0220*/ @!P0 BRA 0x310 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0230*/ MOV R6, 0x4 ; /* 0x0000000400067802 */
/* 0x000fe20000000f00 */
/*0240*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0004 */
/*0250*/ IMAD.WIDE R4, R3, R6, c[0x0][0x170] ; /* 0x00005c0003047625 */
/* 0x000fc800078e0206 */
/*0260*/ IMAD.WIDE R6, R3, R6, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fc800078e0206 */
/*0270*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea8000c1e1900 */
/*0280*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x0000a2000c1e1900 */
/*0290*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*02a0*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*02b0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*02c0*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x001fc800078e0206 */
/*02d0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x004fca0000000000 */
/*02e0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e4000c101904 */
/*02f0*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x001fe200078e0204 */
/*0300*/ @P0 BRA 0x270 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0310*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0320*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0330*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x002fd400000001ff */
/*0340*/ IMAD.WIDE R4, R3, R6, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fc800078e0206 */
/*0350*/ IMAD.WIDE R6, R3, R6, c[0x0][0x170] ; /* 0x00005c0003067625 */
/* 0x000fe200078e0206 */
/*0360*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea8000c1e1900 */
/*0370*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea2000c1e1900 */
/*0380*/ IMAD.WIDE R10, R0, 0x4, R6 ; /* 0x00000004000a7825 */
/* 0x000fc800078e0206 */
/*0390*/ FADD R17, R2, R9 ; /* 0x0000000902117221 */
/* 0x004fe40000000000 */
/*03a0*/ IMAD.WIDE R8, R0, 0x4, R4 ; /* 0x0000000400087825 */
/* 0x000fc600078e0204 */
/*03b0*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x0001e8000c101904 */
/*03c0*/ LDG.E R2, [R10.64] ; /* 0x000000040a027981 */
/* 0x000ea8000c1e1900 */
/*03d0*/ LDG.E R13, [R8.64] ; /* 0x00000004080d7981 */
/* 0x000ea2000c1e1900 */
/*03e0*/ IMAD.WIDE R14, R0, 0x4, R10 ; /* 0x00000004000e7825 */
/* 0x000fc800078e020a */
/*03f0*/ FADD R19, R2, R13 ; /* 0x0000000d02137221 */
/* 0x004fe40000000000 */
/*0400*/ IMAD.WIDE R12, R0, 0x4, R8 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0208 */
/*0410*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x0003e8000c101904 */
/*0420*/ LDG.E R2, [R14.64] ; /* 0x000000040e027981 */
/* 0x000ea8000c1e1900 */
/*0430*/ LDG.E R5, [R12.64] ; /* 0x000000040c057981 */
/* 0x000ea2000c1e1900 */
/*0440*/ IMAD.WIDE R6, R0, 0x4, R14 ; /* 0x0000000400067825 */
/* 0x001fc800078e020e */
/*0450*/ FADD R21, R2, R5 ; /* 0x0000000502157221 */
/* 0x004fe40000000000 */
/*0460*/ IMAD.WIDE R4, R0, 0x4, R12 ; /* 0x0000000400047825 */
/* 0x000fc600078e020c */
/*0470*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0003e8000c101904 */
/*0480*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0490*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea2000c1e1900 */
/*04a0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*04b0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*04c0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ; /* 0x0000580003007a0c */
/* 0x000fe20003f06270 */
/*04d0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*04e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0003ee000c101904 */
/*04f0*/ @!P0 BRA 0x330 ; /* 0xfffffe3000008947 */
/* 0x000fea000383ffff */
/*0500*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0510*/ BRA 0x510; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <stdio.h>
#include <math.h>
#include <time.h>
//============================= GPU Kernel ====================================
__global__
void d_add(int n, float *x, float *y)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
y[i] = x[i] + y[i];
}
//============================= CPU ===========================================
// function to add the elements of two arrays
void add(int n, float *x, float *y)
{
// loop through array and add element by element
for (int i = 0; i < n; i++)
y[i] = x[i] + y[i];
}
// CPU WRAPPER
int add_cpu(void){
int N = 1<<25; // 1M elements
printf("Number of elements: %d\n",N);
float *x = new float[N];
float *y = new float[N];
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
// Run kernel on 1M elements on the CPU
clock_t begin = clock();
add(N, x, y);
clock_t end = clock();
double time_spent = (double)(end - begin) / CLOCKS_PER_SEC;
printf("CPU Time: %f seconds\n", time_spent);
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(y[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;
// Free memory
delete [] x;
delete [] y;
return 0;
}
// GPU WRAPPER
int add_gpu(void){
int N = 1<<25;
float *x, *y;
// Allocate Unified Memory – accessible from CPU or GPU
cudaMallocManaged(&x, N*sizeof(float));
cudaMallocManaged(&y, N*sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
// Run kernel on 1M elements on the GPU
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
clock_t begin = clock();
d_add<<<numBlocks, blockSize>>>(N, x, y);
// Wait for GPU to finish before accessing on host
cudaDeviceSynchronize();
clock_t end = clock();
double time_spent = (double)(end - begin) / CLOCKS_PER_SEC;
printf("GPU Time: %f seconds\n", time_spent);
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(y[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;
// Free memory
cudaFree(x);
cudaFree(y);
return 0;
}
int main(void)
{
add_cpu();
add_gpu();
} | .file "tmpxft_0019dfad_00000000-6_intro.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3675:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z3addiPfS_
.type _Z3addiPfS_, @function
_Z3addiPfS_:
.LFB3669:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L3
movslq %edi, %rdi
leaq 0(,%rdi,4), %rcx
movl $0, %eax
.L5:
movss (%rdx,%rax), %xmm0
addss (%rsi,%rax), %xmm0
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE3669:
.size _Z3addiPfS_, .-_Z3addiPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Number of elements: %d\n"
.LC5:
.string "CPU Time: %f seconds\n"
.LC8:
.string "Max error: "
.text
.globl _Z7add_cpuv
.type _Z7add_cpuv, @function
_Z7add_cpuv:
.LFB3670:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movl $33554432, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $134217728, %edi
call _Znam@PLT
movq %rax, %r12
movl $134217728, %edi
call _Znam@PLT
movq %rax, %rbp
movl $0, %eax
movss .LC2(%rip), %xmm1
movss .LC3(%rip), %xmm0
.L8:
movss %xmm1, (%r12,%rax)
movss %xmm0, 0(%rbp,%rax)
addq $4, %rax
cmpq $134217728, %rax
jne .L8
call clock@PLT
movq %rax, %rbx
movq %rbp, %rdx
movq %r12, %rsi
movl $33554432, %edi
call _Z3addiPfS_
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC4(%rip), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %rbx
leaq 134217728(%rbp), %r13
movl $0x00000000, 12(%rsp)
.L9:
movss (%rbx), %xmm0
subss .LC6(%rip), %xmm0
andps .LC7(%rip), %xmm0
movss 12(%rsp), %xmm1
call fmaxf@PLT
movss %xmm0, 12(%rsp)
addq $4, %rbx
cmpq %rbx, %r13
jne .L9
movl $11, %edx
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r13
testq %r13, %r13
je .L16
cmpb $0, 56(%r13)
je .L11
movzbl 67(%r13), %eax
.L12:
movsbl %al, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L11:
movq %r13, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%r13), %rax
movl $10, %esi
movq %r13, %rdi
call *48(%rax)
jmp .L12
.cfi_endproc
.LFE3670:
.size _Z7add_cpuv, .-_Z7add_cpuv
.globl _Z27__device_stub__Z5d_addiPfS_iPfS_
.type _Z27__device_stub__Z5d_addiPfS_iPfS_, @function
_Z27__device_stub__Z5d_addiPfS_iPfS_:
.LFB3697:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5d_addiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z27__device_stub__Z5d_addiPfS_iPfS_, .-_Z27__device_stub__Z5d_addiPfS_iPfS_
.globl _Z5d_addiPfS_
.type _Z5d_addiPfS_, @function
_Z5d_addiPfS_:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z5d_addiPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z5d_addiPfS_, .-_Z5d_addiPfS_
.section .rodata.str1.1
.LC9:
.string "GPU Time: %f seconds\n"
.text
.globl _Z7add_gpuv
.type _Z7add_gpuv, @function
_Z7add_gpuv:
.LFB3671:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
movl $1, %edx
movl $134217728, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $134217728, %esi
call cudaMallocManaged@PLT
movl $0, %eax
movss .LC2(%rip), %xmm1
movss .LC3(%rip), %xmm0
.L26:
movq 16(%rsp), %rdx
movss %xmm1, (%rdx,%rax)
movq 24(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $134217728, %rax
jne .L26
call clock@PLT
movq %rax, %rbx
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $131072, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L27:
call cudaDeviceSynchronize@PLT
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC4(%rip), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rbx
leaq 134217728(%rbx), %rbp
movl $0x00000000, 12(%rsp)
.L28:
movss (%rbx), %xmm0
subss .LC6(%rip), %xmm0
andps .LC7(%rip), %xmm0
movss 12(%rsp), %xmm1
call fmaxf@PLT
movss %xmm0, 12(%rsp)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L28
movl $11, %edx
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L38
cmpb $0, 56(%rbp)
je .L31
movzbl 67(%rbp), %eax
.L32:
movsbl %al, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L39
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movl $33554432, %edi
call _Z27__device_stub__Z5d_addiPfS_iPfS_
jmp .L27
.L38:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L40
call _ZSt16__throw_bad_castv@PLT
.L40:
call __stack_chk_fail@PLT
.L31:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
jmp .L32
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size _Z7add_gpuv, .-_Z7add_gpuv
.globl main
.type main, @function
main:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z7add_cpuv
call _Z7add_gpuv
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z5d_addiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z5d_addiPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1065353216
.align 4
.LC3:
.long 1073741824
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1093567616
.section .rodata.cst4
.align 4
.LC6:
.long 1077936128
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC7:
.long 2147483647
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <stdio.h>
#include <math.h>
#include <time.h>
//============================= GPU Kernel ====================================
__global__
void d_add(int n, float *x, float *y)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
y[i] = x[i] + y[i];
}
//============================= CPU ===========================================
// function to add the elements of two arrays
void add(int n, float *x, float *y)
{
// loop through array and add element by element
for (int i = 0; i < n; i++)
y[i] = x[i] + y[i];
}
// CPU WRAPPER
int add_cpu(void){
int N = 1<<25; // 1M elements
printf("Number of elements: %d\n",N);
float *x = new float[N];
float *y = new float[N];
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
// Run kernel on 1M elements on the CPU
clock_t begin = clock();
add(N, x, y);
clock_t end = clock();
double time_spent = (double)(end - begin) / CLOCKS_PER_SEC;
printf("CPU Time: %f seconds\n", time_spent);
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(y[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;
// Free memory
delete [] x;
delete [] y;
return 0;
}
// GPU WRAPPER
int add_gpu(void){
int N = 1<<25;
float *x, *y;
// Allocate Unified Memory – accessible from CPU or GPU
cudaMallocManaged(&x, N*sizeof(float));
cudaMallocManaged(&y, N*sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
// Run kernel on 1M elements on the GPU
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
clock_t begin = clock();
d_add<<<numBlocks, blockSize>>>(N, x, y);
// Wait for GPU to finish before accessing on host
cudaDeviceSynchronize();
clock_t end = clock();
double time_spent = (double)(end - begin) / CLOCKS_PER_SEC;
printf("GPU Time: %f seconds\n", time_spent);
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(y[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;
// Free memory
cudaFree(x);
cudaFree(y);
return 0;
}
int main(void)
{
add_cpu();
add_gpu();
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <math.h>
#include <time.h>
//============================= GPU Kernel ====================================
__global__
void d_add(int n, float *x, float *y)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
y[i] = x[i] + y[i];
}
//============================= CPU ===========================================
// function to add the elements of two arrays
void add(int n, float *x, float *y)
{
// loop through array and add element by element
for (int i = 0; i < n; i++)
y[i] = x[i] + y[i];
}
// CPU WRAPPER
int add_cpu(void){
int N = 1<<25; // 1M elements
printf("Number of elements: %d\n",N);
float *x = new float[N];
float *y = new float[N];
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
// Run kernel on 1M elements on the CPU
clock_t begin = clock();
add(N, x, y);
clock_t end = clock();
double time_spent = (double)(end - begin) / CLOCKS_PER_SEC;
printf("CPU Time: %f seconds\n", time_spent);
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(y[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;
// Free memory
delete [] x;
delete [] y;
return 0;
}
// GPU WRAPPER
int add_gpu(void){
int N = 1<<25;
float *x, *y;
// Allocate Unified Memory – accessible from CPU or GPU
hipMallocManaged(&x, N*sizeof(float));
hipMallocManaged(&y, N*sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
// Run kernel on 1M elements on the GPU
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
clock_t begin = clock();
d_add<<<numBlocks, blockSize>>>(N, x, y);
// Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
clock_t end = clock();
double time_spent = (double)(end - begin) / CLOCKS_PER_SEC;
printf("GPU Time: %f seconds\n", time_spent);
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(y[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;
// Free memory
hipFree(x);
hipFree(y);
return 0;
}
int main(void)
{
add_cpu();
add_gpu();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <math.h>
#include <time.h>
//============================= GPU Kernel ====================================
__global__
void d_add(int n, float *x, float *y)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
y[i] = x[i] + y[i];
}
//============================= CPU ===========================================
// function to add the elements of two arrays
void add(int n, float *x, float *y)
{
// loop through array and add element by element
for (int i = 0; i < n; i++)
y[i] = x[i] + y[i];
}
// CPU WRAPPER
int add_cpu(void){
int N = 1<<25; // 1M elements
printf("Number of elements: %d\n",N);
float *x = new float[N];
float *y = new float[N];
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
// Run kernel on 1M elements on the CPU
clock_t begin = clock();
add(N, x, y);
clock_t end = clock();
double time_spent = (double)(end - begin) / CLOCKS_PER_SEC;
printf("CPU Time: %f seconds\n", time_spent);
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(y[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;
// Free memory
delete [] x;
delete [] y;
return 0;
}
// GPU WRAPPER
int add_gpu(void){
int N = 1<<25;
float *x, *y;
// Allocate Unified Memory – accessible from CPU or GPU
hipMallocManaged(&x, N*sizeof(float));
hipMallocManaged(&y, N*sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
// Run kernel on 1M elements on the GPU
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
clock_t begin = clock();
d_add<<<numBlocks, blockSize>>>(N, x, y);
// Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
clock_t end = clock();
double time_spent = (double)(end - begin) / CLOCKS_PER_SEC;
printf("GPU Time: %f seconds\n", time_spent);
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(y[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;
// Free memory
hipFree(x);
hipFree(y);
return 0;
}
int main(void)
{
add_cpu();
add_gpu();
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5d_addiPfS_
.globl _Z5d_addiPfS_
.p2align 8
.type _Z5d_addiPfS_,@function
_Z5d_addiPfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s10, s[0:1], 0x0
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s10, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s8
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[2:3], 2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s8
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
v_add_nc_u32_e32 v1, s2, v1
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e64 s0, s10, v1
global_store_b32 v[6:7], v0, off
s_or_b32 s1, s0, s1
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5d_addiPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5d_addiPfS_, .Lfunc_end0-_Z5d_addiPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5d_addiPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5d_addiPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <math.h>
#include <time.h>
//============================= GPU Kernel ====================================
__global__
void d_add(int n, float *x, float *y)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
y[i] = x[i] + y[i];
}
//============================= CPU ===========================================
// function to add the elements of two arrays
void add(int n, float *x, float *y)
{
// loop through array and add element by element
for (int i = 0; i < n; i++)
y[i] = x[i] + y[i];
}
// CPU WRAPPER
int add_cpu(void){
int N = 1<<25; // 1M elements
printf("Number of elements: %d\n",N);
float *x = new float[N];
float *y = new float[N];
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
// Run kernel on 1M elements on the CPU
clock_t begin = clock();
add(N, x, y);
clock_t end = clock();
double time_spent = (double)(end - begin) / CLOCKS_PER_SEC;
printf("CPU Time: %f seconds\n", time_spent);
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(y[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;
// Free memory
delete [] x;
delete [] y;
return 0;
}
// GPU WRAPPER
int add_gpu(void){
int N = 1<<25;
float *x, *y;
// Allocate Unified Memory – accessible from CPU or GPU
hipMallocManaged(&x, N*sizeof(float));
hipMallocManaged(&y, N*sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
// Run kernel on 1M elements on the GPU
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
clock_t begin = clock();
d_add<<<numBlocks, blockSize>>>(N, x, y);
// Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
clock_t end = clock();
double time_spent = (double)(end - begin) / CLOCKS_PER_SEC;
printf("GPU Time: %f seconds\n", time_spent);
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(y[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;
// Free memory
hipFree(x);
hipFree(y);
return 0;
}
int main(void)
{
add_cpu();
add_gpu();
} | .text
.file "intro.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z20__device_stub__d_addiPfS_ # -- Begin function _Z20__device_stub__d_addiPfS_
.p2align 4, 0x90
.type _Z20__device_stub__d_addiPfS_,@function
_Z20__device_stub__d_addiPfS_: # @_Z20__device_stub__d_addiPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5d_addiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z20__device_stub__d_addiPfS_, .Lfunc_end0-_Z20__device_stub__d_addiPfS_
.cfi_endproc
# -- End function
.globl _Z3addiPfS_ # -- Begin function _Z3addiPfS_
.p2align 4, 0x90
.type _Z3addiPfS_,@function
_Z3addiPfS_: # @_Z3addiPfS_
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %edi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rsi,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rdx,%rcx,4), %xmm0
movss %xmm0, (%rdx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z3addiPfS_, .Lfunc_end1-_Z3addiPfS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7add_cpuv
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI2_1:
.long 0xc0400000 # float -3
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI2_2:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl _Z7add_cpuv
.p2align 4, 0x90
.type _Z7add_cpuv,@function
_Z7add_cpuv: # @_Z7add_cpuv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $24, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %r15d, %r15d
movl $.L.str, %edi
movl $33554432, %esi # imm = 0x2000000
xorl %eax, %eax
callq printf
movl $134217728, %edi # imm = 0x8000000
callq _Znam
movq %rax, %rbx
movl $134217728, %edi # imm = 0x8000000
callq _Znam
movq %rax, %r14
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%r15,4) # imm = 0x3F800000
movl $1073741824, (%r14,%r15,4) # imm = 0x40000000
incq %r15
cmpq $33554432, %r15 # imm = 0x2000000
jne .LBB2_1
# %bb.2:
xorl %r12d, %r12d
callq clock
movq %rax, %r15
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%r14,%r12,4), %xmm0
movss %xmm0, (%r14,%r12,4)
incq %r12
cmpq $33554432, %r12 # imm = 0x2000000
jne .LBB2_3
# %bb.4: # %_Z3addiPfS_.exit
callq clock
subq %r15, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
xorps %xmm2, %xmm2
xorl %eax, %eax
movss .LCPI2_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps .LCPI2_2(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movaps %xmm2, %xmm5
.p2align 4, 0x90
.LBB2_5: # =>This Inner Loop Header: Depth=1
movss (%r14,%rax,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
addss %xmm0, %xmm3
andps %xmm1, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andps %xmm3, %xmm4
maxss %xmm2, %xmm3
andnps %xmm3, %xmm5
orps %xmm4, %xmm5
incq %rax
movaps %xmm5, %xmm2
cmpq $33554432, %rax # imm = 0x2000000
jne .LBB2_5
# %bb.6:
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $11, %edx
movaps %xmm5, (%rsp) # 16-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movaps (%rsp), %xmm0 # 16-byte Reload
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB2_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB2_9
# %bb.8:
movzbl 67(%r15), %ecx
jmp .LBB2_10
.LBB2_9:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB2_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_11:
.cfi_def_cfa_offset 64
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size _Z7add_cpuv, .Lfunc_end2-_Z7add_cpuv
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7add_gpuv
.LCPI3_0:
.quad 0x412e848000000000 # double 1.0E+6
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI3_1:
.long 0xc0400000 # float -3
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI3_2:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl _Z7add_gpuv
.p2align 4, 0x90
.type _Z7add_gpuv,@function
_Z7add_gpuv: # @_Z7add_gpuv
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $152, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 16(%rsp), %rdi
movl $134217728, %esi # imm = 0x8000000
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $134217728, %esi # imm = 0x8000000
movl $1, %edx
callq hipMallocManaged
movq 16(%rsp), %rax
xorl %ecx, %ecx
movq 8(%rsp), %rdx
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rax,%rcx,4) # imm = 0x3F800000
movl $1073741824, (%rdx,%rcx,4) # imm = 0x40000000
incq %rcx
cmpq $33554432, %rcx # imm = 0x2000000
jne .LBB3_1
# %bb.2:
callq clock
movq %rax, %rbx
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 130816(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl $33554432, 28(%rsp) # imm = 0x2000000
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5d_addiPfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_4:
callq hipDeviceSynchronize
callq clock
subq %rbx, %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI3_0(%rip), %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
xorps %xmm2, %xmm2
xorl %eax, %eax
movq 8(%rsp), %rcx
movss .LCPI3_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps .LCPI3_2(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movaps %xmm2, %xmm5
.p2align 4, 0x90
.LBB3_5: # =>This Inner Loop Header: Depth=1
movss (%rcx,%rax,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
addss %xmm0, %xmm3
andps %xmm1, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andps %xmm3, %xmm4
maxss %xmm2, %xmm3
andnps %xmm3, %xmm5
orps %xmm4, %xmm5
incq %rax
movaps %xmm5, %xmm2
cmpq $33554432, %rax # imm = 0x2000000
jne .LBB3_5
# %bb.6:
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $11, %edx
movaps %xmm5, 128(%rsp) # 16-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movaps 128(%rsp), %xmm0 # 16-byte Reload
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB3_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB3_9
# %bb.8:
movzbl 67(%rbx), %ecx
jmp .LBB3_10
.LBB3_9:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB3_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB3_11:
.cfi_def_cfa_offset 176
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size _Z7add_gpuv, .Lfunc_end3-_Z7add_gpuv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq _Z7add_cpuv
callq _Z7add_gpuv
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5d_addiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5d_addiPfS_,@object # @_Z5d_addiPfS_
.section .rodata,"a",@progbits
.globl _Z5d_addiPfS_
.p2align 3, 0x0
_Z5d_addiPfS_:
.quad _Z20__device_stub__d_addiPfS_
.size _Z5d_addiPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Number of elements: %d\n"
.size .L.str, 24
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "CPU Time: %f seconds\n"
.size .L.str.1, 22
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Max error: "
.size .L.str.2, 12
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "GPU Time: %f seconds\n"
.size .L.str.3, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5d_addiPfS_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__d_addiPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5d_addiPfS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5d_addiPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ; /* 0x0000580003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x320 ; /* 0x0000029000007945 */
/* 0x000fe60003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*00b0*/ IMAD.MOV R9, RZ, RZ, -R0 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a00 */
/*00c0*/ IADD3 R2, R0.reuse, R3, RZ ; /* 0x0000000300027210 */
/* 0x040fe40007ffe0ff */
/*00d0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45070 */
/*00e0*/ LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff077212 */
/* 0x000fc800078e33ff */
/*00f0*/ IADD3 R7, R7, c[0x0][0x160], R0 ; /* 0x0000580007077a10 */
/* 0x000fe20007ffe000 */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0130*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*0140*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x002fd200078e02ff */
/*0150*/ IMAD.HI.U32 R2, R5, R9, R4 ; /* 0x0000000905027227 */
/* 0x000fcc00078e0004 */
/*0160*/ IMAD.HI.U32 R2, R2, R7, RZ ; /* 0x0000000702027227 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD.MOV R4, RZ, RZ, -R2 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a02 */
/*0180*/ IMAD R7, R0, R4, R7 ; /* 0x0000000400077224 */
/* 0x000fca00078e0207 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f06070 */
/*01a0*/ @P0 IADD3 R7, -R0, R7, RZ ; /* 0x0000000700070210 */
/* 0x000fe40007ffe1ff */
/*01b0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*01d0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*01f0*/ IADD3 R4, R2.reuse, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x040fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0210*/ LOP3.LUT P0, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fda000780c0ff */
/*0220*/ @!P0 BRA 0x310 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0230*/ MOV R6, 0x4 ; /* 0x0000000400067802 */
/* 0x000fe20000000f00 */
/*0240*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0004 */
/*0250*/ IMAD.WIDE R4, R3, R6, c[0x0][0x170] ; /* 0x00005c0003047625 */
/* 0x000fc800078e0206 */
/*0260*/ IMAD.WIDE R6, R3, R6, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fc800078e0206 */
/*0270*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea8000c1e1900 */
/*0280*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x0000a2000c1e1900 */
/*0290*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*02a0*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*02b0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*02c0*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x001fc800078e0206 */
/*02d0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x004fca0000000000 */
/*02e0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e4000c101904 */
/*02f0*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x001fe200078e0204 */
/*0300*/ @P0 BRA 0x270 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0310*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0320*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0330*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x002fd400000001ff */
/*0340*/ IMAD.WIDE R4, R3, R6, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fc800078e0206 */
/*0350*/ IMAD.WIDE R6, R3, R6, c[0x0][0x170] ; /* 0x00005c0003067625 */
/* 0x000fe200078e0206 */
/*0360*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea8000c1e1900 */
/*0370*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea2000c1e1900 */
/*0380*/ IMAD.WIDE R10, R0, 0x4, R6 ; /* 0x00000004000a7825 */
/* 0x000fc800078e0206 */
/*0390*/ FADD R17, R2, R9 ; /* 0x0000000902117221 */
/* 0x004fe40000000000 */
/*03a0*/ IMAD.WIDE R8, R0, 0x4, R4 ; /* 0x0000000400087825 */
/* 0x000fc600078e0204 */
/*03b0*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x0001e8000c101904 */
/*03c0*/ LDG.E R2, [R10.64] ; /* 0x000000040a027981 */
/* 0x000ea8000c1e1900 */
/*03d0*/ LDG.E R13, [R8.64] ; /* 0x00000004080d7981 */
/* 0x000ea2000c1e1900 */
/*03e0*/ IMAD.WIDE R14, R0, 0x4, R10 ; /* 0x00000004000e7825 */
/* 0x000fc800078e020a */
/*03f0*/ FADD R19, R2, R13 ; /* 0x0000000d02137221 */
/* 0x004fe40000000000 */
/*0400*/ IMAD.WIDE R12, R0, 0x4, R8 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0208 */
/*0410*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x0003e8000c101904 */
/*0420*/ LDG.E R2, [R14.64] ; /* 0x000000040e027981 */
/* 0x000ea8000c1e1900 */
/*0430*/ LDG.E R5, [R12.64] ; /* 0x000000040c057981 */
/* 0x000ea2000c1e1900 */
/*0440*/ IMAD.WIDE R6, R0, 0x4, R14 ; /* 0x0000000400067825 */
/* 0x001fc800078e020e */
/*0450*/ FADD R21, R2, R5 ; /* 0x0000000502157221 */
/* 0x004fe40000000000 */
/*0460*/ IMAD.WIDE R4, R0, 0x4, R12 ; /* 0x0000000400047825 */
/* 0x000fc600078e020c */
/*0470*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0003e8000c101904 */
/*0480*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0490*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea2000c1e1900 */
/*04a0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*04b0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*04c0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ; /* 0x0000580003007a0c */
/* 0x000fe20003f06270 */
/*04d0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*04e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0003ee000c101904 */
/*04f0*/ @!P0 BRA 0x330 ; /* 0xfffffe3000008947 */
/* 0x000fea000383ffff */
/*0500*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0510*/ BRA 0x510; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5d_addiPfS_
.globl _Z5d_addiPfS_
.p2align 8
.type _Z5d_addiPfS_,@function
_Z5d_addiPfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s10, s[0:1], 0x0
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s10, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s8
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[2:3], 2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s8
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
v_add_nc_u32_e32 v1, s2, v1
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e64 s0, s10, v1
global_store_b32 v[6:7], v0, off
s_or_b32 s1, s0, s1
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5d_addiPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5d_addiPfS_, .Lfunc_end0-_Z5d_addiPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5d_addiPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5d_addiPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019dfad_00000000-6_intro.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3675:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z3addiPfS_
.type _Z3addiPfS_, @function
_Z3addiPfS_:
.LFB3669:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L3
movslq %edi, %rdi
leaq 0(,%rdi,4), %rcx
movl $0, %eax
.L5:
movss (%rdx,%rax), %xmm0
addss (%rsi,%rax), %xmm0
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE3669:
.size _Z3addiPfS_, .-_Z3addiPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Number of elements: %d\n"
.LC5:
.string "CPU Time: %f seconds\n"
.LC8:
.string "Max error: "
.text
.globl _Z7add_cpuv
.type _Z7add_cpuv, @function
_Z7add_cpuv:
.LFB3670:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movl $33554432, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $134217728, %edi
call _Znam@PLT
movq %rax, %r12
movl $134217728, %edi
call _Znam@PLT
movq %rax, %rbp
movl $0, %eax
movss .LC2(%rip), %xmm1
movss .LC3(%rip), %xmm0
.L8:
movss %xmm1, (%r12,%rax)
movss %xmm0, 0(%rbp,%rax)
addq $4, %rax
cmpq $134217728, %rax
jne .L8
call clock@PLT
movq %rax, %rbx
movq %rbp, %rdx
movq %r12, %rsi
movl $33554432, %edi
call _Z3addiPfS_
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC4(%rip), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %rbx
leaq 134217728(%rbp), %r13
movl $0x00000000, 12(%rsp)
.L9:
movss (%rbx), %xmm0
subss .LC6(%rip), %xmm0
andps .LC7(%rip), %xmm0
movss 12(%rsp), %xmm1
call fmaxf@PLT
movss %xmm0, 12(%rsp)
addq $4, %rbx
cmpq %rbx, %r13
jne .L9
movl $11, %edx
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r13
testq %r13, %r13
je .L16
cmpb $0, 56(%r13)
je .L11
movzbl 67(%r13), %eax
.L12:
movsbl %al, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L11:
movq %r13, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%r13), %rax
movl $10, %esi
movq %r13, %rdi
call *48(%rax)
jmp .L12
.cfi_endproc
.LFE3670:
.size _Z7add_cpuv, .-_Z7add_cpuv
.globl _Z27__device_stub__Z5d_addiPfS_iPfS_
.type _Z27__device_stub__Z5d_addiPfS_iPfS_, @function
_Z27__device_stub__Z5d_addiPfS_iPfS_:
.LFB3697:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5d_addiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z27__device_stub__Z5d_addiPfS_iPfS_, .-_Z27__device_stub__Z5d_addiPfS_iPfS_
.globl _Z5d_addiPfS_
.type _Z5d_addiPfS_, @function
_Z5d_addiPfS_:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z5d_addiPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z5d_addiPfS_, .-_Z5d_addiPfS_
.section .rodata.str1.1
.LC9:
.string "GPU Time: %f seconds\n"
.text
.globl _Z7add_gpuv
.type _Z7add_gpuv, @function
_Z7add_gpuv:
.LFB3671:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
movl $1, %edx
movl $134217728, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $134217728, %esi
call cudaMallocManaged@PLT
movl $0, %eax
movss .LC2(%rip), %xmm1
movss .LC3(%rip), %xmm0
.L26:
movq 16(%rsp), %rdx
movss %xmm1, (%rdx,%rax)
movq 24(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $134217728, %rax
jne .L26
call clock@PLT
movq %rax, %rbx
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $131072, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L27:
call cudaDeviceSynchronize@PLT
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC4(%rip), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rbx
leaq 134217728(%rbx), %rbp
movl $0x00000000, 12(%rsp)
.L28:
movss (%rbx), %xmm0
subss .LC6(%rip), %xmm0
andps .LC7(%rip), %xmm0
movss 12(%rsp), %xmm1
call fmaxf@PLT
movss %xmm0, 12(%rsp)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L28
movl $11, %edx
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L38
cmpb $0, 56(%rbp)
je .L31
movzbl 67(%rbp), %eax
.L32:
movsbl %al, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L39
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movl $33554432, %edi
call _Z27__device_stub__Z5d_addiPfS_iPfS_
jmp .L27
.L38:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L40
call _ZSt16__throw_bad_castv@PLT
.L40:
call __stack_chk_fail@PLT
.L31:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
jmp .L32
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size _Z7add_gpuv, .-_Z7add_gpuv
.globl main
.type main, @function
main:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z7add_cpuv
call _Z7add_gpuv
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z5d_addiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z5d_addiPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1065353216
.align 4
.LC3:
.long 1073741824
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1093567616
.section .rodata.cst4
.align 4
.LC6:
.long 1077936128
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC7:
.long 2147483647
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "intro.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z20__device_stub__d_addiPfS_ # -- Begin function _Z20__device_stub__d_addiPfS_
.p2align 4, 0x90
.type _Z20__device_stub__d_addiPfS_,@function
_Z20__device_stub__d_addiPfS_: # @_Z20__device_stub__d_addiPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5d_addiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z20__device_stub__d_addiPfS_, .Lfunc_end0-_Z20__device_stub__d_addiPfS_
.cfi_endproc
# -- End function
.globl _Z3addiPfS_ # -- Begin function _Z3addiPfS_
.p2align 4, 0x90
.type _Z3addiPfS_,@function
_Z3addiPfS_: # @_Z3addiPfS_
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %edi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rsi,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rdx,%rcx,4), %xmm0
movss %xmm0, (%rdx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z3addiPfS_, .Lfunc_end1-_Z3addiPfS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7add_cpuv
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI2_1:
.long 0xc0400000 # float -3
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI2_2:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl _Z7add_cpuv
.p2align 4, 0x90
.type _Z7add_cpuv,@function
_Z7add_cpuv: # @_Z7add_cpuv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $24, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %r15d, %r15d
movl $.L.str, %edi
movl $33554432, %esi # imm = 0x2000000
xorl %eax, %eax
callq printf
movl $134217728, %edi # imm = 0x8000000
callq _Znam
movq %rax, %rbx
movl $134217728, %edi # imm = 0x8000000
callq _Znam
movq %rax, %r14
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%r15,4) # imm = 0x3F800000
movl $1073741824, (%r14,%r15,4) # imm = 0x40000000
incq %r15
cmpq $33554432, %r15 # imm = 0x2000000
jne .LBB2_1
# %bb.2:
xorl %r12d, %r12d
callq clock
movq %rax, %r15
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%r14,%r12,4), %xmm0
movss %xmm0, (%r14,%r12,4)
incq %r12
cmpq $33554432, %r12 # imm = 0x2000000
jne .LBB2_3
# %bb.4: # %_Z3addiPfS_.exit
callq clock
subq %r15, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
xorps %xmm2, %xmm2
xorl %eax, %eax
movss .LCPI2_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps .LCPI2_2(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movaps %xmm2, %xmm5
.p2align 4, 0x90
.LBB2_5: # =>This Inner Loop Header: Depth=1
movss (%r14,%rax,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
addss %xmm0, %xmm3
andps %xmm1, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andps %xmm3, %xmm4
maxss %xmm2, %xmm3
andnps %xmm3, %xmm5
orps %xmm4, %xmm5
incq %rax
movaps %xmm5, %xmm2
cmpq $33554432, %rax # imm = 0x2000000
jne .LBB2_5
# %bb.6:
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $11, %edx
movaps %xmm5, (%rsp) # 16-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movaps (%rsp), %xmm0 # 16-byte Reload
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB2_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB2_9
# %bb.8:
movzbl 67(%r15), %ecx
jmp .LBB2_10
.LBB2_9:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB2_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_11:
.cfi_def_cfa_offset 64
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size _Z7add_cpuv, .Lfunc_end2-_Z7add_cpuv
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7add_gpuv
.LCPI3_0:
.quad 0x412e848000000000 # double 1.0E+6
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI3_1:
.long 0xc0400000 # float -3
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI3_2:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl _Z7add_gpuv
.p2align 4, 0x90
.type _Z7add_gpuv,@function
_Z7add_gpuv: # @_Z7add_gpuv
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $152, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 16(%rsp), %rdi
movl $134217728, %esi # imm = 0x8000000
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $134217728, %esi # imm = 0x8000000
movl $1, %edx
callq hipMallocManaged
movq 16(%rsp), %rax
xorl %ecx, %ecx
movq 8(%rsp), %rdx
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rax,%rcx,4) # imm = 0x3F800000
movl $1073741824, (%rdx,%rcx,4) # imm = 0x40000000
incq %rcx
cmpq $33554432, %rcx # imm = 0x2000000
jne .LBB3_1
# %bb.2:
callq clock
movq %rax, %rbx
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 130816(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl $33554432, 28(%rsp) # imm = 0x2000000
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5d_addiPfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_4:
callq hipDeviceSynchronize
callq clock
subq %rbx, %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI3_0(%rip), %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
xorps %xmm2, %xmm2
xorl %eax, %eax
movq 8(%rsp), %rcx
movss .LCPI3_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps .LCPI3_2(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movaps %xmm2, %xmm5
.p2align 4, 0x90
.LBB3_5: # =>This Inner Loop Header: Depth=1
movss (%rcx,%rax,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
addss %xmm0, %xmm3
andps %xmm1, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andps %xmm3, %xmm4
maxss %xmm2, %xmm3
andnps %xmm3, %xmm5
orps %xmm4, %xmm5
incq %rax
movaps %xmm5, %xmm2
cmpq $33554432, %rax # imm = 0x2000000
jne .LBB3_5
# %bb.6:
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $11, %edx
movaps %xmm5, 128(%rsp) # 16-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movaps 128(%rsp), %xmm0 # 16-byte Reload
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB3_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB3_9
# %bb.8:
movzbl 67(%rbx), %ecx
jmp .LBB3_10
.LBB3_9:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB3_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB3_11:
.cfi_def_cfa_offset 176
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size _Z7add_gpuv, .Lfunc_end3-_Z7add_gpuv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq _Z7add_cpuv
callq _Z7add_gpuv
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5d_addiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5d_addiPfS_,@object # @_Z5d_addiPfS_
.section .rodata,"a",@progbits
.globl _Z5d_addiPfS_
.p2align 3, 0x0
_Z5d_addiPfS_:
.quad _Z20__device_stub__d_addiPfS_
.size _Z5d_addiPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Number of elements: %d\n"
.size .L.str, 24
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "CPU Time: %f seconds\n"
.size .L.str.1, 22
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Max error: "
.size .L.str.2, 12
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "GPU Time: %f seconds\n"
.size .L.str.3, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5d_addiPfS_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__d_addiPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5d_addiPfS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <stdio.h>
__global__ void Invert_Matrix(double mat[],double eye[]);
int main(void)
{
double *d_A, *d_B;
double mat3[36];
double mat[6][6]={{0.060471,0.291984,0.372410,0.052677,0.417744,0.698106},{0.399258,0.431651,0.198118,0.737858,0.983052,0.666528},{0.526876,0.015487,0.489688,0.269119,0.301455,0.178132},{0.416799,0.984064,0.339493,0.422836,0.701099,0.128014},{0.656860,0.167168,0.951630,0.547871,0.666339,0.999080},{0.627973,0.106216,0.920332,0.942737,0.539126,0.171121}};
double mat2[36];
for(int i =0; i<6; i++)
{
for(int j=0; j<6; j++)
{
mat2[i*6+j]=mat[i][j];
}
}
double eye[6][6];
double eye2[36];
for(int i =0; i<6; i++)
{
for(int j=0; j<6; j++)
{
if(j==i)
{
eye2[i*6+j]=1;
eye[i][i]=1;
}
else
{
eye2[i*6+j]=0;
eye[i][j]=0;
}
}
}
double temp1;
double temp2;
std::cout<<"haha"<<std::endl;
double ar[6*6] = {5,2,3,4,5,6,7,8,1,10,11,12,13,14,15,16,5,18,19,20,21,3,23,24,25,26,27,28,29,30,31,32,33,34,35,36};
std::cout<<"blah"<<std::endl;
/*
for(int r =0; r<6; r++)
{
for(int c=0; c<6; c++)
{
mat[r][c]= ar[r*6+c];
}
std::cout<<"hey"<<std::endl;
}
std::cout<<"what the?"<<std::endl;
*/
for(int x =0; x<6; x++)
{
for(int y =0; y<6; y++)
{
std::cout<<mat[x][y]<<'\t';
}
std::cout<<std::endl;
}
for(int r =0; r<6; r++)
{
for(int x =0; x<6; x++)
{
for(int y =0; y<6; y++)
{
std::cout<<eye[x][y]<<'\t';
}
std::cout<<std::endl;
}
std::cout<<std::endl;
temp1=mat[r][r];
for(int c =0; c<6; c++)
{
mat[r][c]=mat[r][c]/temp1;
eye[r][c]=eye[r][c]/temp1;
//std::cout<<'x'<<temp1<<std::endl;
//std::cout<<'y'<<r<<'c'<<c<<std::endl;
//std::cout<<mat[r][c]<<std::endl;
}
for(int i=0; i<6; i++)
{
if(i!=r)
{
temp2=mat[i][r];
for(int c =0; c<6; c++)
{
mat[i][c]-=(mat[r][c]*temp2);
eye[i][c]-=(eye[r][c]*temp2);
}
}
}
}
for(int r =0; r<6; r++)
{
for(int c =0; c<6; c++)
{
std::cout<<mat[r][c]<<'\t';
}
std::cout<<std::endl;
}
for(int r =0; r<6; r++)
{
for(int c =0; c<6; c++)
{
std::cout<<eye[r][c]<<'\t';
}
std::cout<<std::endl;
}
cudaMalloc(&d_A,sizeof(double)*36);
cudaMalloc(&d_B,sizeof(double)*36);
cudaMemcpy(d_A,mat2,sizeof(double)*36,cudaMemcpyHostToDevice);
cudaMemcpy(d_B,eye2,sizeof(double)*36,cudaMemcpyHostToDevice);
dim3 dimBlock(6, 6,1);
dim3 dimGrid(1,1,1);
cudaDeviceSynchronize();
Invert_Matrix<<<dimGrid, dimBlock>>>(d_A,d_B);
cudaDeviceSynchronize();
cudaMemcpy(mat3, d_A,sizeof(double)*36, cudaMemcpyDeviceToHost);
cudaMemcpy(eye2, d_B,sizeof(double)*36, cudaMemcpyDeviceToHost);
std::cout<<std::endl<<std::endl<<std::endl;
for(int r =0; r<6; r++)
{
for(int c =0; c<6; c++)
{
std::cout<<mat3[r*6+c]<<'\t';
}
std::cout<<std::endl;
}
}
__global__ void Invert_Matrix(double A[],double B[])
{
const int row = threadIdx.y;
const int col= threadIdx.x;
__shared__ double temp1;
__shared__ double temp2;
__shared__ double mat[6][6];
__shared__ double eye[6][6];
mat[row][col]=A[row*6+col];
eye[row][col]=B[row*6+col];
__syncthreads();
if(row == col)
{
for(int r =0; r<6; r++)
{
if(col==0)
{
temp1=mat[r][r];
}
__syncthreads();
mat[r][col]/=temp1;
eye[r][col]/=temp1;
for(int i=0; i<6; i++)
{
if(i!=r)
{
if(col==0)
{
temp2=mat[i][r];
}
__syncthreads();
mat[i][col]-=(mat[r][col]*temp2);
eye[i][col]-=(eye[r][col]*temp2);
}
}
}
}
A[row*6+col]=mat[row][col];
B[row*6+col]=eye[row][col];
__syncthreads();
printf("xx%fxx",A[row*6+col]);
if(row==0 && col==0)
{
for(int j =0; j<6; j++)
{
for(int i =0; i<6; i++)
{
printf("%f\t",A[j*6+i]);
}
printf("\n\n\n");
}
}
} | .file "tmpxft_0014623d_00000000-6_test_inv.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z13Invert_MatrixPdS_PdS_
.type _Z35__device_stub__Z13Invert_MatrixPdS_PdS_, @function
_Z35__device_stub__Z13Invert_MatrixPdS_PdS_:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13Invert_MatrixPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z35__device_stub__Z13Invert_MatrixPdS_PdS_, .-_Z35__device_stub__Z13Invert_MatrixPdS_PdS_
.globl _Z13Invert_MatrixPdS_
.type _Z13Invert_MatrixPdS_, @function
_Z13Invert_MatrixPdS_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z13Invert_MatrixPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z13Invert_MatrixPdS_, .-_Z13Invert_MatrixPdS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "haha"
.LC5:
.string "blah"
.section .rodata
.align 32
.LC0:
.long 246840360
.long 1068430862
.long -1463999732
.long 1070772189
.long -1062403110
.long 1071109520
.long -796871052
.long 1068169338
.long 1418095122
.long 1071299665
.long 1692698151
.long 1072060130
.long 1831511494
.long 1071222129
.long -2079176488
.long 1071357995
.long 1029692639
.long 1070160878
.long 1633874279
.long 1072143496
.long 2009632378
.long 1072657705
.long -2026125052
.long 1071993906
.long 245465971
.long 1071701035
.long -199561360
.long 1066383269
.long 1448056814
.long 1071601420
.long -437330750
.long 1070676286
.long -376582733
.long 1070811913
.long -2060484790
.long 1069993223
.long -1233102291
.long 1071295701
.long -920291232
.long 1072659827
.long -653384785
.long 1070971456
.long -1176202564
.long 1071321022
.long 730350599
.long 1072066407
.long 1136070389
.long 1069572803
.long 1128373808
.long 1071973631
.long -763885703
.long 1069901250
.long -1040412878
.long 1072591808
.long -1016223622
.long 1071745064
.long 715232314
.long 1071993510
.long -1631400378
.long 1072691318
.long -717706215
.long 1071913050
.long -967845110
.long 1069232376
.long 405719791
.long 1072526172
.long -923314889
.long 1072573158
.long 726502308
.long 1071726725
.long -44805099
.long 1069934410
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1576, %rsp
.cfi_def_cfa_offset 1632
movq %fs:40, %rax
movq %rax, 1560(%rsp)
xorl %eax, %eax
leaq 400(%rsp), %rdi
leaq .LC0(%rip), %rsi
movl $36, %ecx
rep movsq
leaq 400(%rsp), %rbx
leaq 688(%rsp), %rcx
movq %rbx, %rdx
movl $0, %esi
jmp .L12
.L89:
addl $6, %esi
addq $48, %rdx
addq $48, %rcx
cmpl $36, %esi
je .L88
.L12:
movl $0, %eax
.L13:
movsd (%rdx,%rax), %xmm0
movsd %xmm0, (%rcx,%rax)
addq $8, %rax
cmpq $48, %rax
jne .L13
jmp .L89
.L88:
leaq 976(%rsp), %r14
movq %r14, %rdi
movq %r14, %r8
movl $0, %r9d
movl $0, %esi
movsd .LC2(%rip), %xmm0
jmp .L14
.L15:
movslq %edx, %rcx
movq $0x000000000, 1264(%rsp,%rcx,8)
movq $0x000000000, (%rdi,%rax,8)
.L16:
addq $1, %rax
addl $1, %edx
cmpq $6, %rax
je .L90
.L17:
cmpl %eax, %esi
jne .L15
movslq %edx, %rcx
movsd %xmm0, 1264(%rsp,%rcx,8)
movsd %xmm0, (%r8)
jmp .L16
.L90:
addl $1, %esi
addq $56, %r8
addq $48, %rdi
addl $6, %r9d
cmpl $6, %esi
je .L18
.L14:
movl %r9d, %edx
movl $0, %eax
jmp .L17
.L18:
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC5(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 288(%rbx), %r12
movq %rbx, %r15
movq %rbp, %r13
jmp .L19
.L20:
movl $9, %esi
call _ZNSo3putEc@PLT
.L21:
addq $1, %rbp
cmpq $6, %rbp
je .L91
.L22:
movsd (%r15,%rbp,8), %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movb $9, 100(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L20
leaq 100(%rsp), %rsi
movl $1, %edx
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L21
.L91:
movq 0(%r13), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %rbp
testq %rbp, %rbp
je .L92
cmpb $0, 56(%rbp)
je .L25
movzbl 67(%rbp), %esi
.L26:
movsbl %sil, %esi
movq %r13, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $48, %r15
cmpq %r12, %r15
je .L93
.L19:
movl $0, %ebp
jmp .L22
.L92:
movq 1560(%rsp), %rax
subq %fs:40, %rax
jne .L94
call _ZSt16__throw_bad_castv@PLT
.L94:
call __stack_chk_fail@PLT
.L25:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L26
.L93:
leaq 48(%rbx), %r8
movq %rbx, 8(%rsp)
movl $0, %r13d
movl $0, %r15d
leaq _ZSt4cout(%rip), %rbp
movq %rbx, 48(%rsp)
movq %r14, %rbx
movq %r8, %r14
movq %r8, 40(%rsp)
movq %r12, 56(%rsp)
jmp .L27
.L28:
movl $9, %esi
call _ZNSo3putEc@PLT
.L29:
addq $1, %rbx
cmpq $6, %rbx
je .L95
.L30:
movsd (%r12,%rbx,8), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movb $9, 100(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L28
leaq 100(%rsp), %rsi
movl $1, %edx
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L29
.L95:
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbx
testq %rbx, %rbx
je .L96
cmpb $0, 56(%rbx)
je .L33
movzbl 67(%rbx), %esi
.L34:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $48, %r12
cmpq %r13, %r12
je .L35
.L45:
movl $0, %ebx
jmp .L30
.L96:
movq 1560(%rsp), %rax
subq %fs:40, %rax
jne .L97
call _ZSt16__throw_bad_castv@PLT
.L97:
call __stack_chk_fail@PLT
.L33:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L34
.L35:
movq 16(%rsp), %rbx
movq 24(%rsp), %r13
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L98
cmpb $0, 56(%r12)
je .L38
movzbl 67(%r12), %eax
.L39:
movsbl %al, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 8(%rsp), %rax
movsd (%rax), %xmm1
leaq -48(%r14), %rax
leaq 0(%r13,%rbx), %rdx
.L40:
movsd (%rax), %xmm0
divsd %xmm1, %xmm0
movsd %xmm0, (%rax)
movsd (%rdx), %xmm0
divsd %xmm1, %xmm0
movsd %xmm0, (%rdx)
addq $8, %rax
addq $8, %rdx
cmpq %r14, %rax
jne .L40
movq 40(%rsp), %rdi
movl $0, %ecx
movl $0, %r8d
jmp .L43
.L98:
movq 1560(%rsp), %rax
subq %fs:40, %rax
jne .L99
call _ZSt16__throw_bad_castv@PLT
.L99:
call __stack_chk_fail@PLT
.L38:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
jmp .L39
.L41:
addl $1, %r8d
subq $48, %rcx
addq $48, %rdi
cmpl $6, %r8d
je .L100
.L43:
cmpl %r15d, %r8d
je .L41
movsd -48(%rdi,%r15,8), %xmm1
leaq -48(%rdi), %rax
movq %rbx, %rdx
subq %rcx, %rdx
.L42:
leaq (%rax,%rcx), %rsi
movapd %xmm1, %xmm2
mulsd (%rsi,%r13), %xmm2
movsd (%rax), %xmm0
subsd %xmm2, %xmm0
movsd %xmm0, (%rax)
leaq (%rdx,%rcx), %rsi
movapd %xmm1, %xmm2
mulsd (%rsi,%r13), %xmm2
movsd (%rdx), %xmm0
subsd %xmm2, %xmm0
movsd %xmm0, (%rdx)
addq $8, %rax
addq $8, %rdx
cmpq %rdi, %rax
jne .L42
jmp .L41
.L100:
addq $1, %r15
addq $48, %r13
addq $48, %r14
addq $56, 8(%rsp)
cmpq $6, %r15
je .L101
.L27:
leaq 288(%rbx), %rax
movq %rax, 32(%rsp)
movq %rbx, %r12
movq %rbx, 16(%rsp)
movq %r13, 24(%rsp)
movq %rax, %r13
jmp .L45
.L101:
movq %rbx, %r14
movq 48(%rsp), %rbx
movq 56(%rsp), %r12
leaq _ZSt4cout(%rip), %r13
jmp .L44
.L46:
movl $9, %esi
call _ZNSo3putEc@PLT
.L47:
addq $1, %rbp
cmpq $6, %rbp
je .L102
.L48:
movsd (%rbx,%rbp,8), %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movb $9, 100(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L46
leaq 100(%rsp), %rsi
movl $1, %edx
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L47
.L102:
movq 0(%r13), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %rbp
testq %rbp, %rbp
je .L103
cmpb $0, 56(%rbp)
je .L51
movzbl 67(%rbp), %eax
.L52:
movsbl %al, %esi
movq %r13, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $48, %rbx
cmpq %r12, %rbx
je .L104
.L44:
movl $0, %ebp
jmp .L48
.L103:
movq 1560(%rsp), %rax
subq %fs:40, %rax
jne .L105
call _ZSt16__throw_bad_castv@PLT
.L105:
call __stack_chk_fail@PLT
.L51:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
jmp .L52
.L104:
leaq _ZSt4cout(%rip), %rbp
movq 32(%rsp), %r12
jmp .L53
.L54:
movl $9, %esi
call _ZNSo3putEc@PLT
.L55:
addq $1, %rbx
cmpq $6, %rbx
je .L106
.L56:
movsd (%r14,%rbx,8), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movb $9, 100(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L54
leaq 100(%rsp), %rsi
movl $1, %edx
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L55
.L106:
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbx
testq %rbx, %rbx
je .L107
cmpb $0, 56(%rbx)
je .L59
movzbl 67(%rbx), %eax
.L60:
movsbl %al, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $48, %r14
cmpq %r12, %r14
je .L61
.L53:
movl $0, %ebx
jmp .L56
.L107:
movq 1560(%rsp), %rax
subq %fs:40, %rax
jne .L108
call _ZSt16__throw_bad_castv@PLT
.L108:
call __stack_chk_fail@PLT
.L59:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L60
.L61:
leaq 72(%rsp), %rdi
movl $288, %esi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movl $288, %esi
call cudaMalloc@PLT
leaq 688(%rsp), %rsi
movl $1, %ecx
movl $288, %edx
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
leaq 1264(%rsp), %rsi
movl $1, %ecx
movl $288, %edx
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl $6, 88(%rsp)
movl $6, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
call cudaDeviceSynchronize@PLT
movl 96(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 88(%rsp), %rdx
movq 100(%rsp), %rdi
movl 108(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L109
.L62:
call cudaDeviceSynchronize@PLT
leaq 112(%rsp), %r12
movl $2, %ecx
movl $288, %edx
movq 72(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq 1264(%rsp), %rdi
movl $2, %ecx
movl $288, %edx
movq 80(%rsp), %rsi
call cudaMemcpy@PLT
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %r13d
leaq _ZSt4cout(%rip), %rbp
jmp .L63
.L109:
movq 80(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z35__device_stub__Z13Invert_MatrixPdS_PdS_
jmp .L62
.L64:
movl $9, %esi
call _ZNSo3putEc@PLT
.L65:
addq $1, %rbx
cmpq $6, %rbx
je .L110
.L66:
movsd (%r12,%rbx,8), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movb $9, 71(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L64
leaq 71(%rsp), %rsi
movl $1, %edx
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L65
.L110:
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbx
testq %rbx, %rbx
je .L111
cmpb $0, 56(%rbx)
je .L69
movzbl 67(%rbx), %eax
.L70:
movsbl %al, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $6, %r13d
addq $48, %r12
cmpl $36, %r13d
je .L71
.L63:
movl $0, %ebx
jmp .L66
.L111:
movq 1560(%rsp), %rax
subq %fs:40, %rax
jne .L112
call _ZSt16__throw_bad_castv@PLT
.L112:
call __stack_chk_fail@PLT
.L69:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L70
.L71:
movq 1560(%rsp), %rax
subq %fs:40, %rax
jne .L113
movl $0, %eax
addq $1576, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L113:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z13Invert_MatrixPdS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z13Invert_MatrixPdS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1072693248
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <stdio.h>
__global__ void Invert_Matrix(double mat[],double eye[]);
int main(void)
{
double *d_A, *d_B;
double mat3[36];
double mat[6][6]={{0.060471,0.291984,0.372410,0.052677,0.417744,0.698106},{0.399258,0.431651,0.198118,0.737858,0.983052,0.666528},{0.526876,0.015487,0.489688,0.269119,0.301455,0.178132},{0.416799,0.984064,0.339493,0.422836,0.701099,0.128014},{0.656860,0.167168,0.951630,0.547871,0.666339,0.999080},{0.627973,0.106216,0.920332,0.942737,0.539126,0.171121}};
double mat2[36];
for(int i =0; i<6; i++)
{
for(int j=0; j<6; j++)
{
mat2[i*6+j]=mat[i][j];
}
}
double eye[6][6];
double eye2[36];
for(int i =0; i<6; i++)
{
for(int j=0; j<6; j++)
{
if(j==i)
{
eye2[i*6+j]=1;
eye[i][i]=1;
}
else
{
eye2[i*6+j]=0;
eye[i][j]=0;
}
}
}
double temp1;
double temp2;
std::cout<<"haha"<<std::endl;
double ar[6*6] = {5,2,3,4,5,6,7,8,1,10,11,12,13,14,15,16,5,18,19,20,21,3,23,24,25,26,27,28,29,30,31,32,33,34,35,36};
std::cout<<"blah"<<std::endl;
/*
for(int r =0; r<6; r++)
{
for(int c=0; c<6; c++)
{
mat[r][c]= ar[r*6+c];
}
std::cout<<"hey"<<std::endl;
}
std::cout<<"what the?"<<std::endl;
*/
for(int x =0; x<6; x++)
{
for(int y =0; y<6; y++)
{
std::cout<<mat[x][y]<<'\t';
}
std::cout<<std::endl;
}
for(int r =0; r<6; r++)
{
for(int x =0; x<6; x++)
{
for(int y =0; y<6; y++)
{
std::cout<<eye[x][y]<<'\t';
}
std::cout<<std::endl;
}
std::cout<<std::endl;
temp1=mat[r][r];
for(int c =0; c<6; c++)
{
mat[r][c]=mat[r][c]/temp1;
eye[r][c]=eye[r][c]/temp1;
//std::cout<<'x'<<temp1<<std::endl;
//std::cout<<'y'<<r<<'c'<<c<<std::endl;
//std::cout<<mat[r][c]<<std::endl;
}
for(int i=0; i<6; i++)
{
if(i!=r)
{
temp2=mat[i][r];
for(int c =0; c<6; c++)
{
mat[i][c]-=(mat[r][c]*temp2);
eye[i][c]-=(eye[r][c]*temp2);
}
}
}
}
for(int r =0; r<6; r++)
{
for(int c =0; c<6; c++)
{
std::cout<<mat[r][c]<<'\t';
}
std::cout<<std::endl;
}
for(int r =0; r<6; r++)
{
for(int c =0; c<6; c++)
{
std::cout<<eye[r][c]<<'\t';
}
std::cout<<std::endl;
}
cudaMalloc(&d_A,sizeof(double)*36);
cudaMalloc(&d_B,sizeof(double)*36);
cudaMemcpy(d_A,mat2,sizeof(double)*36,cudaMemcpyHostToDevice);
cudaMemcpy(d_B,eye2,sizeof(double)*36,cudaMemcpyHostToDevice);
dim3 dimBlock(6, 6,1);
dim3 dimGrid(1,1,1);
cudaDeviceSynchronize();
Invert_Matrix<<<dimGrid, dimBlock>>>(d_A,d_B);
cudaDeviceSynchronize();
cudaMemcpy(mat3, d_A,sizeof(double)*36, cudaMemcpyDeviceToHost);
cudaMemcpy(eye2, d_B,sizeof(double)*36, cudaMemcpyDeviceToHost);
std::cout<<std::endl<<std::endl<<std::endl;
for(int r =0; r<6; r++)
{
for(int c =0; c<6; c++)
{
std::cout<<mat3[r*6+c]<<'\t';
}
std::cout<<std::endl;
}
}
__global__ void Invert_Matrix(double A[],double B[])
{
const int row = threadIdx.y;
const int col= threadIdx.x;
__shared__ double temp1;
__shared__ double temp2;
__shared__ double mat[6][6];
__shared__ double eye[6][6];
mat[row][col]=A[row*6+col];
eye[row][col]=B[row*6+col];
__syncthreads();
if(row == col)
{
for(int r =0; r<6; r++)
{
if(col==0)
{
temp1=mat[r][r];
}
__syncthreads();
mat[r][col]/=temp1;
eye[r][col]/=temp1;
for(int i=0; i<6; i++)
{
if(i!=r)
{
if(col==0)
{
temp2=mat[i][r];
}
__syncthreads();
mat[i][col]-=(mat[r][col]*temp2);
eye[i][col]-=(eye[r][col]*temp2);
}
}
}
}
A[row*6+col]=mat[row][col];
B[row*6+col]=eye[row][col];
__syncthreads();
printf("xx%fxx",A[row*6+col]);
if(row==0 && col==0)
{
for(int j =0; j<6; j++)
{
for(int i =0; i<6; i++)
{
printf("%f\t",A[j*6+i]);
}
printf("\n\n\n");
}
}
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
__global__ void Invert_Matrix(double mat[],double eye[]);
int main(void)
{
double *d_A, *d_B;
double mat3[36];
double mat[6][6]={{0.060471,0.291984,0.372410,0.052677,0.417744,0.698106},{0.399258,0.431651,0.198118,0.737858,0.983052,0.666528},{0.526876,0.015487,0.489688,0.269119,0.301455,0.178132},{0.416799,0.984064,0.339493,0.422836,0.701099,0.128014},{0.656860,0.167168,0.951630,0.547871,0.666339,0.999080},{0.627973,0.106216,0.920332,0.942737,0.539126,0.171121}};
double mat2[36];
for(int i =0; i<6; i++)
{
for(int j=0; j<6; j++)
{
mat2[i*6+j]=mat[i][j];
}
}
double eye[6][6];
double eye2[36];
for(int i =0; i<6; i++)
{
for(int j=0; j<6; j++)
{
if(j==i)
{
eye2[i*6+j]=1;
eye[i][i]=1;
}
else
{
eye2[i*6+j]=0;
eye[i][j]=0;
}
}
}
double temp1;
double temp2;
std::cout<<"haha"<<std::endl;
double ar[6*6] = {5,2,3,4,5,6,7,8,1,10,11,12,13,14,15,16,5,18,19,20,21,3,23,24,25,26,27,28,29,30,31,32,33,34,35,36};
std::cout<<"blah"<<std::endl;
/*
for(int r =0; r<6; r++)
{
for(int c=0; c<6; c++)
{
mat[r][c]= ar[r*6+c];
}
std::cout<<"hey"<<std::endl;
}
std::cout<<"what the?"<<std::endl;
*/
for(int x =0; x<6; x++)
{
for(int y =0; y<6; y++)
{
std::cout<<mat[x][y]<<'\t';
}
std::cout<<std::endl;
}
for(int r =0; r<6; r++)
{
for(int x =0; x<6; x++)
{
for(int y =0; y<6; y++)
{
std::cout<<eye[x][y]<<'\t';
}
std::cout<<std::endl;
}
std::cout<<std::endl;
temp1=mat[r][r];
for(int c =0; c<6; c++)
{
mat[r][c]=mat[r][c]/temp1;
eye[r][c]=eye[r][c]/temp1;
//std::cout<<'x'<<temp1<<std::endl;
//std::cout<<'y'<<r<<'c'<<c<<std::endl;
//std::cout<<mat[r][c]<<std::endl;
}
for(int i=0; i<6; i++)
{
if(i!=r)
{
temp2=mat[i][r];
for(int c =0; c<6; c++)
{
mat[i][c]-=(mat[r][c]*temp2);
eye[i][c]-=(eye[r][c]*temp2);
}
}
}
}
for(int r =0; r<6; r++)
{
for(int c =0; c<6; c++)
{
std::cout<<mat[r][c]<<'\t';
}
std::cout<<std::endl;
}
for(int r =0; r<6; r++)
{
for(int c =0; c<6; c++)
{
std::cout<<eye[r][c]<<'\t';
}
std::cout<<std::endl;
}
hipMalloc(&d_A,sizeof(double)*36);
hipMalloc(&d_B,sizeof(double)*36);
hipMemcpy(d_A,mat2,sizeof(double)*36,hipMemcpyHostToDevice);
hipMemcpy(d_B,eye2,sizeof(double)*36,hipMemcpyHostToDevice);
dim3 dimBlock(6, 6,1);
dim3 dimGrid(1,1,1);
hipDeviceSynchronize();
Invert_Matrix<<<dimGrid, dimBlock>>>(d_A,d_B);
hipDeviceSynchronize();
hipMemcpy(mat3, d_A,sizeof(double)*36, hipMemcpyDeviceToHost);
hipMemcpy(eye2, d_B,sizeof(double)*36, hipMemcpyDeviceToHost);
std::cout<<std::endl<<std::endl<<std::endl;
for(int r =0; r<6; r++)
{
for(int c =0; c<6; c++)
{
std::cout<<mat3[r*6+c]<<'\t';
}
std::cout<<std::endl;
}
}
__global__ void Invert_Matrix(double A[],double B[])
{
const int row = threadIdx.y;
const int col= threadIdx.x;
__shared__ double temp1;
__shared__ double temp2;
__shared__ double mat[6][6];
__shared__ double eye[6][6];
mat[row][col]=A[row*6+col];
eye[row][col]=B[row*6+col];
__syncthreads();
if(row == col)
{
for(int r =0; r<6; r++)
{
if(col==0)
{
temp1=mat[r][r];
}
__syncthreads();
mat[r][col]/=temp1;
eye[r][col]/=temp1;
for(int i=0; i<6; i++)
{
if(i!=r)
{
if(col==0)
{
temp2=mat[i][r];
}
__syncthreads();
mat[i][col]-=(mat[r][col]*temp2);
eye[i][col]-=(eye[r][col]*temp2);
}
}
}
}
A[row*6+col]=mat[row][col];
B[row*6+col]=eye[row][col];
__syncthreads();
printf("xx%fxx",A[row*6+col]);
if(row==0 && col==0)
{
for(int j =0; j<6; j++)
{
for(int i =0; i<6; i++)
{
printf("%f\t",A[j*6+i]);
}
printf("\n\n\n");
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
__global__ void Invert_Matrix(double mat[],double eye[]);
int main(void)
{
double *d_A, *d_B;
double mat3[36];
double mat[6][6]={{0.060471,0.291984,0.372410,0.052677,0.417744,0.698106},{0.399258,0.431651,0.198118,0.737858,0.983052,0.666528},{0.526876,0.015487,0.489688,0.269119,0.301455,0.178132},{0.416799,0.984064,0.339493,0.422836,0.701099,0.128014},{0.656860,0.167168,0.951630,0.547871,0.666339,0.999080},{0.627973,0.106216,0.920332,0.942737,0.539126,0.171121}};
double mat2[36];
for(int i =0; i<6; i++)
{
for(int j=0; j<6; j++)
{
mat2[i*6+j]=mat[i][j];
}
}
double eye[6][6];
double eye2[36];
for(int i =0; i<6; i++)
{
for(int j=0; j<6; j++)
{
if(j==i)
{
eye2[i*6+j]=1;
eye[i][i]=1;
}
else
{
eye2[i*6+j]=0;
eye[i][j]=0;
}
}
}
double temp1;
double temp2;
std::cout<<"haha"<<std::endl;
double ar[6*6] = {5,2,3,4,5,6,7,8,1,10,11,12,13,14,15,16,5,18,19,20,21,3,23,24,25,26,27,28,29,30,31,32,33,34,35,36};
std::cout<<"blah"<<std::endl;
/*
for(int r =0; r<6; r++)
{
for(int c=0; c<6; c++)
{
mat[r][c]= ar[r*6+c];
}
std::cout<<"hey"<<std::endl;
}
std::cout<<"what the?"<<std::endl;
*/
for(int x =0; x<6; x++)
{
for(int y =0; y<6; y++)
{
std::cout<<mat[x][y]<<'\t';
}
std::cout<<std::endl;
}
for(int r =0; r<6; r++)
{
for(int x =0; x<6; x++)
{
for(int y =0; y<6; y++)
{
std::cout<<eye[x][y]<<'\t';
}
std::cout<<std::endl;
}
std::cout<<std::endl;
temp1=mat[r][r];
for(int c =0; c<6; c++)
{
mat[r][c]=mat[r][c]/temp1;
eye[r][c]=eye[r][c]/temp1;
//std::cout<<'x'<<temp1<<std::endl;
//std::cout<<'y'<<r<<'c'<<c<<std::endl;
//std::cout<<mat[r][c]<<std::endl;
}
for(int i=0; i<6; i++)
{
if(i!=r)
{
temp2=mat[i][r];
for(int c =0; c<6; c++)
{
mat[i][c]-=(mat[r][c]*temp2);
eye[i][c]-=(eye[r][c]*temp2);
}
}
}
}
for(int r =0; r<6; r++)
{
for(int c =0; c<6; c++)
{
std::cout<<mat[r][c]<<'\t';
}
std::cout<<std::endl;
}
for(int r =0; r<6; r++)
{
for(int c =0; c<6; c++)
{
std::cout<<eye[r][c]<<'\t';
}
std::cout<<std::endl;
}
hipMalloc(&d_A,sizeof(double)*36);
hipMalloc(&d_B,sizeof(double)*36);
hipMemcpy(d_A,mat2,sizeof(double)*36,hipMemcpyHostToDevice);
hipMemcpy(d_B,eye2,sizeof(double)*36,hipMemcpyHostToDevice);
dim3 dimBlock(6, 6,1);
dim3 dimGrid(1,1,1);
hipDeviceSynchronize();
Invert_Matrix<<<dimGrid, dimBlock>>>(d_A,d_B);
hipDeviceSynchronize();
hipMemcpy(mat3, d_A,sizeof(double)*36, hipMemcpyDeviceToHost);
hipMemcpy(eye2, d_B,sizeof(double)*36, hipMemcpyDeviceToHost);
std::cout<<std::endl<<std::endl<<std::endl;
for(int r =0; r<6; r++)
{
for(int c =0; c<6; c++)
{
std::cout<<mat3[r*6+c]<<'\t';
}
std::cout<<std::endl;
}
}
__global__ void Invert_Matrix(double A[],double B[])
{
const int row = threadIdx.y;
const int col= threadIdx.x;
__shared__ double temp1;
__shared__ double temp2;
__shared__ double mat[6][6];
__shared__ double eye[6][6];
mat[row][col]=A[row*6+col];
eye[row][col]=B[row*6+col];
__syncthreads();
if(row == col)
{
for(int r =0; r<6; r++)
{
if(col==0)
{
temp1=mat[r][r];
}
__syncthreads();
mat[r][col]/=temp1;
eye[r][col]/=temp1;
for(int i=0; i<6; i++)
{
if(i!=r)
{
if(col==0)
{
temp2=mat[i][r];
}
__syncthreads();
mat[i][col]-=(mat[r][col]*temp2);
eye[i][col]-=(eye[r][col]*temp2);
}
}
}
}
A[row*6+col]=mat[row][col];
B[row*6+col]=eye[row][col];
__syncthreads();
printf("xx%fxx",A[row*6+col]);
if(row==0 && col==0)
{
for(int j =0; j<6; j++)
{
for(int i =0; i<6; i++)
{
printf("%f\t",A[j*6+i]);
}
printf("\n\n\n");
}
}
} | .text
.file "test_inv.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1544, %rsp # imm = 0x608
.cfi_def_cfa_offset 1600
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 384(%rsp), %rbx
movl $.L__const.main.mat, %esi
movl $288, %edx # imm = 0x120
movq %rbx, %rdi
callq memcpy@PLT
leaq 1248(%rsp), %rdi
movl $.L__const.main.mat, %esi
movl $288, %edx # imm = 0x120
callq memcpy@PLT
leaq 960(%rsp), %rax
leaq 672(%rsp), %rcx
xorl %edx, %edx
movabsq $4607182418800017408, %rsi # imm = 0x3FF0000000000000
jmp .LBB0_1
.p2align 4, 0x90
.LBB0_18: # in Loop: Header=BB0_1 Depth=1
incq %rdx
addq $48, %rax
addq $48, %rcx
cmpq $6, %rdx
je .LBB0_4
.LBB0_1: # %.preheader183
# =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
leaq (%rdx,%rdx,2), %rdi
shlq $4, %rdi
addq %rsp, %rdi
addq $672, %rdi # imm = 0x2A0
leaq (%rdi,%rdx,8), %rdi
xorl %r8d, %r8d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_16: # in Loop: Header=BB0_2 Depth=2
movq $0, (%rax,%r8,8)
movq $0, (%rcx,%r8,8)
.LBB0_17: # in Loop: Header=BB0_2 Depth=2
incq %r8
cmpq $6, %r8
je .LBB0_18
.LBB0_2: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
cmpq %r8, %rdx
jne .LBB0_16
# %bb.3: # in Loop: Header=BB0_2 Depth=2
movq %rsi, (%rax,%r8,8)
movq %rsi, (%rdi)
jmp .LBB0_17
.LBB0_4:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB0_98
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB0_7
# %bb.6:
movzbl 67(%r14), %eax
jmp .LBB0_8
.LBB0_7:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB0_98
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i123
cmpb $0, 56(%r14)
je .LBB0_11
# %bb.10:
movzbl 67(%r14), %eax
jmp .LBB0_12
.LBB0_11:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit126
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r12d, %r12d
leaq 96(%rsp), %r14
jmp .LBB0_13
.p2align 4, 0x90
.LBB0_22: # in Loop: Header=BB0_13 Depth=1
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_23: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit131
# in Loop: Header=BB0_13 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r12
addq $48, %rbx
cmpq $6, %r12
je .LBB0_24
.LBB0_13: # %.preheader182
# =>This Loop Header: Depth=1
# Child Loop BB0_14 Depth 2
xorl %r15d, %r15d
jmp .LBB0_14
.p2align 4, 0x90
.LBB0_29: # in Loop: Header=BB0_14 Depth=2
movq %rax, %rdi
movl $9, %esi
callq _ZNSo3putEc
.LBB0_30: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
# in Loop: Header=BB0_14 Depth=2
incq %r15
cmpq $6, %r15
je .LBB0_19
.LBB0_14: # Parent Loop BB0_13 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rbx,%r15,8), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movb $9, 96(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB0_29
# %bb.15: # in Loop: Header=BB0_14 Depth=2
movl $1, %edx
movq %rax, %rdi
movq %r14, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB0_30
.p2align 4, 0x90
.LBB0_19: # in Loop: Header=BB0_13 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB0_98
# %bb.20: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i128
# in Loop: Header=BB0_13 Depth=1
cmpb $0, 56(%r15)
je .LBB0_22
# %bb.21: # in Loop: Header=BB0_13 Depth=1
movzbl 67(%r15), %eax
jmp .LBB0_23
.LBB0_24: # %.preheader180.preheader
leaq 384(%rsp), %r15
leaq 672(%rsp), %r12
xorl %edi, %edi
leaq 96(%rsp), %rbx
movq %r12, %rbp
jmp .LBB0_25
.p2align 4, 0x90
.LBB0_42: # in Loop: Header=BB0_25 Depth=1
incq %rdi
addq $48, %r15
addq $48, %rbp
cmpq $6, %rdi
je .LBB0_43
.LBB0_25: # %.preheader180
# =>This Loop Header: Depth=1
# Child Loop BB0_26 Depth 2
# Child Loop BB0_27 Depth 3
# Child Loop BB0_36 Depth 2
# Child Loop BB0_38 Depth 2
# Child Loop BB0_40 Depth 3
movq %rdi, 40(%rsp) # 8-byte Spill
xorl %r13d, %r13d
jmp .LBB0_26
.p2align 4, 0x90
.LBB0_50: # in Loop: Header=BB0_26 Depth=2
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_51: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit141
# in Loop: Header=BB0_26 Depth=2
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r13
addq $48, %r12
cmpq $6, %r13
je .LBB0_31
.LBB0_26: # %.preheader178
# Parent Loop BB0_25 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_27 Depth 3
xorl %r14d, %r14d
jmp .LBB0_27
.p2align 4, 0x90
.LBB0_52: # in Loop: Header=BB0_27 Depth=3
movq %rax, %rdi
movl $9, %esi
callq _ZNSo3putEc
.LBB0_53: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit112
# in Loop: Header=BB0_27 Depth=3
incq %r14
cmpq $6, %r14
je .LBB0_47
.LBB0_27: # Parent Loop BB0_25 Depth=1
# Parent Loop BB0_26 Depth=2
# => This Inner Loop Header: Depth=3
movsd (%r12,%r14,8), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movb $9, 96(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB0_52
# %bb.28: # in Loop: Header=BB0_27 Depth=3
movl $1, %edx
movq %rax, %rdi
movq %rbx, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB0_53
.p2align 4, 0x90
.LBB0_47: # in Loop: Header=BB0_26 Depth=2
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB0_98
# %bb.48: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i138
# in Loop: Header=BB0_26 Depth=2
cmpb $0, 56(%r14)
je .LBB0_50
# %bb.49: # in Loop: Header=BB0_26 Depth=2
movzbl 67(%r14), %eax
jmp .LBB0_51
.p2align 4, 0x90
.LBB0_31: # in Loop: Header=BB0_25 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB0_98
# %bb.32: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i133
# in Loop: Header=BB0_25 Depth=1
cmpb $0, 56(%r14)
leaq 672(%rsp), %r12
je .LBB0_34
# %bb.33: # in Loop: Header=BB0_25 Depth=1
movzbl 67(%r14), %eax
jmp .LBB0_35
.p2align 4, 0x90
.LBB0_34: # in Loop: Header=BB0_25 Depth=1
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_35: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit136
# in Loop: Header=BB0_25 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 40(%rsp), %rdi # 8-byte Reload
leaq (%rdi,%rdi,2), %rax
shlq $4, %rax
addq %rsp, %rax
addq $384, %rax # imm = 0x180
movsd (%rax,%rdi,8), %xmm0 # xmm0 = mem[0],zero
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_36: # Parent Loop BB0_25 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r15,%rax,8), %xmm1 # xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movsd %xmm1, (%r15,%rax,8)
movsd (%rbp,%rax,8), %xmm1 # xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movsd %xmm1, (%rbp,%rax,8)
incq %rax
cmpq $6, %rax
jne .LBB0_36
# %bb.37: # %.preheader179.preheader
# in Loop: Header=BB0_25 Depth=1
movq %r12, %rax
leaq 384(%rsp), %rcx
xorl %edx, %edx
jmp .LBB0_38
.p2align 4, 0x90
.LBB0_41: # %.loopexit
# in Loop: Header=BB0_38 Depth=2
incq %rdx
addq $48, %rcx
addq $48, %rax
cmpq $6, %rdx
je .LBB0_42
.LBB0_38: # %.preheader179
# Parent Loop BB0_25 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_40 Depth 3
cmpq %rdi, %rdx
je .LBB0_41
# %bb.39: # in Loop: Header=BB0_38 Depth=2
leaq (%rdx,%rdx,2), %rsi
shlq $4, %rsi
addq %rsp, %rsi
addq $384, %rsi # imm = 0x180
movsd (%rsi,%rdi,8), %xmm0 # xmm0 = mem[0],zero
xorl %esi, %esi
.p2align 4, 0x90
.LBB0_40: # Parent Loop BB0_25 Depth=1
# Parent Loop BB0_38 Depth=2
# => This Inner Loop Header: Depth=3
movsd (%r15,%rsi,8), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm0, %xmm1
movsd (%rcx,%rsi,8), %xmm2 # xmm2 = mem[0],zero
subsd %xmm1, %xmm2
movsd %xmm2, (%rcx,%rsi,8)
movsd (%rbp,%rsi,8), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm0, %xmm1
movsd (%rax,%rsi,8), %xmm2 # xmm2 = mem[0],zero
subsd %xmm1, %xmm2
movsd %xmm2, (%rax,%rsi,8)
incq %rsi
cmpq $6, %rsi
jne .LBB0_40
jmp .LBB0_41
.LBB0_43: # %.preheader176.preheader
leaq 384(%rsp), %r15
xorl %r12d, %r12d
leaq 96(%rsp), %rbx
jmp .LBB0_44
.p2align 4, 0x90
.LBB0_56: # in Loop: Header=BB0_44 Depth=1
movzbl 67(%r14), %eax
.LBB0_58: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit146
# in Loop: Header=BB0_44 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r12
addq $48, %r15
cmpq $6, %r12
je .LBB0_59
.LBB0_44: # %.preheader176
# =>This Loop Header: Depth=1
# Child Loop BB0_45 Depth 2
xorl %r14d, %r14d
jmp .LBB0_45
.p2align 4, 0x90
.LBB0_46: # in Loop: Header=BB0_45 Depth=2
movl $1, %edx
movq %rax, %rdi
movq %rbx, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB0_64: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit115
# in Loop: Header=BB0_45 Depth=2
incq %r14
cmpq $6, %r14
je .LBB0_54
.LBB0_45: # Parent Loop BB0_44 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r15,%r14,8), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movb $9, 96(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
jne .LBB0_46
# %bb.63: # in Loop: Header=BB0_45 Depth=2
movq %rax, %rdi
movl $9, %esi
callq _ZNSo3putEc
jmp .LBB0_64
.p2align 4, 0x90
.LBB0_54: # in Loop: Header=BB0_44 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB0_98
# %bb.55: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i143
# in Loop: Header=BB0_44 Depth=1
cmpb $0, 56(%r14)
jne .LBB0_56
# %bb.57: # in Loop: Header=BB0_44 Depth=1
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
jmp .LBB0_58
.LBB0_59: # %.preheader174.preheader
leaq 672(%rsp), %r15
xorl %r12d, %r12d
leaq 96(%rsp), %rbx
jmp .LBB0_60
.p2align 4, 0x90
.LBB0_68: # in Loop: Header=BB0_60 Depth=1
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_69: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit151
# in Loop: Header=BB0_60 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r12
addq $48, %r15
cmpq $6, %r12
je .LBB0_70
.LBB0_60: # %.preheader174
# =>This Loop Header: Depth=1
# Child Loop BB0_61 Depth 2
xorl %r14d, %r14d
jmp .LBB0_61
.p2align 4, 0x90
.LBB0_62: # in Loop: Header=BB0_61 Depth=2
movl $1, %edx
movq %rax, %rdi
movq %rbx, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB0_76: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit118
# in Loop: Header=BB0_61 Depth=2
incq %r14
cmpq $6, %r14
je .LBB0_65
.LBB0_61: # Parent Loop BB0_60 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r15,%r14,8), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movb $9, 96(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
jne .LBB0_62
# %bb.75: # in Loop: Header=BB0_61 Depth=2
movq %rax, %rdi
movl $9, %esi
callq _ZNSo3putEc
jmp .LBB0_76
.p2align 4, 0x90
.LBB0_65: # in Loop: Header=BB0_60 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB0_98
# %bb.66: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i148
# in Loop: Header=BB0_60 Depth=1
cmpb $0, 56(%r14)
je .LBB0_68
# %bb.67: # in Loop: Header=BB0_60 Depth=1
movzbl 67(%r14), %eax
jmp .LBB0_69
.LBB0_70:
leaq 16(%rsp), %rdi
movl $288, %esi # imm = 0x120
callq hipMalloc
leaq 8(%rsp), %rdi
movl $288, %esi # imm = 0x120
callq hipMalloc
movq 16(%rsp), %rdi
leaq 1248(%rsp), %rsi
movl $288, %edx # imm = 0x120
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 960(%rsp), %rsi
movl $288, %edx # imm = 0x120
movl $1, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $25769803782, %rdx # imm = 0x600000006
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_72
# %bb.71:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13Invert_MatrixPdS_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_72:
callq hipDeviceSynchronize
movq 16(%rsp), %rsi
leaq 96(%rsp), %rbx
movl $288, %edx # imm = 0x120
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rsi
leaq 960(%rsp), %rdi
movl $288, %edx # imm = 0x120
movl $2, %ecx
callq hipMemcpy
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB0_98
# %bb.73: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i153
cmpb $0, 56(%r14)
je .LBB0_77
# %bb.74:
movzbl 67(%r14), %eax
jmp .LBB0_78
.LBB0_77:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_78: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit156
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB0_98
# %bb.79: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i158
cmpb $0, 56(%r14)
je .LBB0_81
# %bb.80:
movzbl 67(%r14), %ecx
jmp .LBB0_82
.LBB0_81:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB0_82: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit161
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB0_98
# %bb.83: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i163
cmpb $0, 56(%r14)
je .LBB0_85
# %bb.84:
movzbl 67(%r14), %ecx
jmp .LBB0_86
.LBB0_85:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB0_86: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit166
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r12d, %r12d
leaq 24(%rsp), %r14
jmp .LBB0_87
.p2align 4, 0x90
.LBB0_93: # in Loop: Header=BB0_87 Depth=1
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_94: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit171
# in Loop: Header=BB0_87 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r12
addq $48, %rbx
cmpq $6, %r12
je .LBB0_95
.LBB0_87: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_88 Depth 2
xorl %r15d, %r15d
jmp .LBB0_88
.p2align 4, 0x90
.LBB0_89: # in Loop: Header=BB0_88 Depth=2
movl $1, %edx
movq %rax, %rdi
movq %r14, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB0_97: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit121
# in Loop: Header=BB0_88 Depth=2
incq %r15
cmpq $6, %r15
je .LBB0_90
.LBB0_88: # Parent Loop BB0_87 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rbx,%r15,8), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movb $9, 24(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
jne .LBB0_89
# %bb.96: # in Loop: Header=BB0_88 Depth=2
movq %rax, %rdi
movl $9, %esi
callq _ZNSo3putEc
jmp .LBB0_97
.p2align 4, 0x90
.LBB0_90: # in Loop: Header=BB0_87 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB0_98
# %bb.91: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i168
# in Loop: Header=BB0_87 Depth=1
cmpb $0, 56(%r15)
je .LBB0_93
# %bb.92: # in Loop: Header=BB0_87 Depth=1
movzbl 67(%r15), %eax
jmp .LBB0_94
.LBB0_95:
xorl %eax, %eax
addq $1544, %rsp # imm = 0x608
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_98:
.cfi_def_cfa_offset 1600
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z28__device_stub__Invert_MatrixPdS_ # -- Begin function _Z28__device_stub__Invert_MatrixPdS_
.p2align 4, 0x90
.type _Z28__device_stub__Invert_MatrixPdS_,@function
_Z28__device_stub__Invert_MatrixPdS_: # @_Z28__device_stub__Invert_MatrixPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13Invert_MatrixPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z28__device_stub__Invert_MatrixPdS_, .Lfunc_end1-_Z28__device_stub__Invert_MatrixPdS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13Invert_MatrixPdS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L__const.main.mat,@object # @__const.main.mat
.section .rodata,"a",@progbits
.p2align 4, 0x0
.L__const.main.mat:
.quad 0x3faef60e0eb67c28 # double 0.060470999999999997
.quad 0x3fd2afdda8bd230c # double 0.29198400000000002
.quad 0x3fd7d590c0ad03da # double 0.37241000000000002
.quad 0x3faaf87ad080b674 # double 0.052677000000000002
.quad 0x3fdabc5154866a12 # double 0.417744
.quad 0x3fe656e264e48627 # double 0.698106
.quad 0x3fd98d716d2aa5c6 # double 0.399258
.quad 0x3fdba02b841248d8 # double 0.43165100000000001
.quad 0x3fc95bee3d5fdcdf # double 0.19811799999999999
.quad 0x3fe79c886162f167 # double 0.73785800000000001
.quad 0x3fef752977c88e7a # double 0.98305200000000004
.quad 0x3fe55432873bc904 # double 0.66652800000000001
.quad 0x3fe0dc2b0ea18373 # double 0.52687600000000001
.quad 0x3f8fb7a5f41aef70 # double 0.015487000000000001
.quad 0x3fdf570c564f97ee # double 0.48968800000000001
.quad 0x3fd1393ee5eedcc2 # double 0.269119
.quad 0x3fd34b09e98dcdb3 # double 0.30145499999999997
.quad 0x3fc6cd07852f7f4a # double 0.17813200000000001
.quad 0x3fdaacd5b6805a2d # double 0.41679899999999998
.quad 0x3fef7d73c9257860 # double 0.98406400000000004
.quad 0x3fd5ba40d90e23af # double 0.33949299999999999
.quad 0x3fdb0fbeb9e492bc # double 0.42283599999999999
.quad 0x3fe66f672b884407 # double 0.70109900000000003
.quad 0x3fc062c343b70ef5 # double 0.12801399999999999
.quad 0x3fe504ff43419e30 # double 0.65686
.quad 0x3fc565c2d2780779 # double 0.16716800000000001
.quad 0x3fee73c0c1fc8f32 # double 0.95162999999999998
.quad 0x3fe18828c36da87a # double 0.547871
.quad 0x3fe552a62aa1943a # double 0.66633900000000001
.quad 0x3feff8769ec2ce46 # double 0.99907999999999997
.quad 0x3fe4185ad538ac19 # double 0.627973
.quad 0x3fbb30f8c64fdb0a # double 0.106216
.quad 0x3fed735c182ecaef # double 0.92033200000000004
.quad 0x3fee2ae6c8f75537 # double 0.94273700000000005
.quad 0x3fe140852b4d8ba4 # double 0.53912599999999999
.quad 0x3fc5e74afd545415 # double 0.171121
.size .L__const.main.mat, 288
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "haha"
.size .L.str, 5
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "blah"
.size .L.str.1, 5
.type _Z13Invert_MatrixPdS_,@object # @_Z13Invert_MatrixPdS_
.section .rodata,"a",@progbits
.globl _Z13Invert_MatrixPdS_
.p2align 3, 0x0
_Z13Invert_MatrixPdS_:
.quad _Z28__device_stub__Invert_MatrixPdS_
.size _Z13Invert_MatrixPdS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13Invert_MatrixPdS_"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__Invert_MatrixPdS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cout
.addrsig_sym _Z13Invert_MatrixPdS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014623d_00000000-6_test_inv.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z13Invert_MatrixPdS_PdS_
.type _Z35__device_stub__Z13Invert_MatrixPdS_PdS_, @function
_Z35__device_stub__Z13Invert_MatrixPdS_PdS_:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13Invert_MatrixPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z35__device_stub__Z13Invert_MatrixPdS_PdS_, .-_Z35__device_stub__Z13Invert_MatrixPdS_PdS_
.globl _Z13Invert_MatrixPdS_
.type _Z13Invert_MatrixPdS_, @function
_Z13Invert_MatrixPdS_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z13Invert_MatrixPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z13Invert_MatrixPdS_, .-_Z13Invert_MatrixPdS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "haha"
.LC5:
.string "blah"
.section .rodata
.align 32
.LC0:
.long 246840360
.long 1068430862
.long -1463999732
.long 1070772189
.long -1062403110
.long 1071109520
.long -796871052
.long 1068169338
.long 1418095122
.long 1071299665
.long 1692698151
.long 1072060130
.long 1831511494
.long 1071222129
.long -2079176488
.long 1071357995
.long 1029692639
.long 1070160878
.long 1633874279
.long 1072143496
.long 2009632378
.long 1072657705
.long -2026125052
.long 1071993906
.long 245465971
.long 1071701035
.long -199561360
.long 1066383269
.long 1448056814
.long 1071601420
.long -437330750
.long 1070676286
.long -376582733
.long 1070811913
.long -2060484790
.long 1069993223
.long -1233102291
.long 1071295701
.long -920291232
.long 1072659827
.long -653384785
.long 1070971456
.long -1176202564
.long 1071321022
.long 730350599
.long 1072066407
.long 1136070389
.long 1069572803
.long 1128373808
.long 1071973631
.long -763885703
.long 1069901250
.long -1040412878
.long 1072591808
.long -1016223622
.long 1071745064
.long 715232314
.long 1071993510
.long -1631400378
.long 1072691318
.long -717706215
.long 1071913050
.long -967845110
.long 1069232376
.long 405719791
.long 1072526172
.long -923314889
.long 1072573158
.long 726502308
.long 1071726725
.long -44805099
.long 1069934410
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1576, %rsp
.cfi_def_cfa_offset 1632
movq %fs:40, %rax
movq %rax, 1560(%rsp)
xorl %eax, %eax
leaq 400(%rsp), %rdi
leaq .LC0(%rip), %rsi
movl $36, %ecx
rep movsq
leaq 400(%rsp), %rbx
leaq 688(%rsp), %rcx
movq %rbx, %rdx
movl $0, %esi
jmp .L12
.L89:
addl $6, %esi
addq $48, %rdx
addq $48, %rcx
cmpl $36, %esi
je .L88
.L12:
movl $0, %eax
.L13:
movsd (%rdx,%rax), %xmm0
movsd %xmm0, (%rcx,%rax)
addq $8, %rax
cmpq $48, %rax
jne .L13
jmp .L89
.L88:
leaq 976(%rsp), %r14
movq %r14, %rdi
movq %r14, %r8
movl $0, %r9d
movl $0, %esi
movsd .LC2(%rip), %xmm0
jmp .L14
.L15:
movslq %edx, %rcx
movq $0x000000000, 1264(%rsp,%rcx,8)
movq $0x000000000, (%rdi,%rax,8)
.L16:
addq $1, %rax
addl $1, %edx
cmpq $6, %rax
je .L90
.L17:
cmpl %eax, %esi
jne .L15
movslq %edx, %rcx
movsd %xmm0, 1264(%rsp,%rcx,8)
movsd %xmm0, (%r8)
jmp .L16
.L90:
addl $1, %esi
addq $56, %r8
addq $48, %rdi
addl $6, %r9d
cmpl $6, %esi
je .L18
.L14:
movl %r9d, %edx
movl $0, %eax
jmp .L17
.L18:
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC5(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 288(%rbx), %r12
movq %rbx, %r15
movq %rbp, %r13
jmp .L19
.L20:
movl $9, %esi
call _ZNSo3putEc@PLT
.L21:
addq $1, %rbp
cmpq $6, %rbp
je .L91
.L22:
movsd (%r15,%rbp,8), %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movb $9, 100(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L20
leaq 100(%rsp), %rsi
movl $1, %edx
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L21
.L91:
movq 0(%r13), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %rbp
testq %rbp, %rbp
je .L92
cmpb $0, 56(%rbp)
je .L25
movzbl 67(%rbp), %esi
.L26:
movsbl %sil, %esi
movq %r13, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $48, %r15
cmpq %r12, %r15
je .L93
.L19:
movl $0, %ebp
jmp .L22
.L92:
movq 1560(%rsp), %rax
subq %fs:40, %rax
jne .L94
call _ZSt16__throw_bad_castv@PLT
.L94:
call __stack_chk_fail@PLT
.L25:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L26
.L93:
leaq 48(%rbx), %r8
movq %rbx, 8(%rsp)
movl $0, %r13d
movl $0, %r15d
leaq _ZSt4cout(%rip), %rbp
movq %rbx, 48(%rsp)
movq %r14, %rbx
movq %r8, %r14
movq %r8, 40(%rsp)
movq %r12, 56(%rsp)
jmp .L27
.L28:
movl $9, %esi
call _ZNSo3putEc@PLT
.L29:
addq $1, %rbx
cmpq $6, %rbx
je .L95
.L30:
movsd (%r12,%rbx,8), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movb $9, 100(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L28
leaq 100(%rsp), %rsi
movl $1, %edx
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L29
.L95:
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbx
testq %rbx, %rbx
je .L96
cmpb $0, 56(%rbx)
je .L33
movzbl 67(%rbx), %esi
.L34:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $48, %r12
cmpq %r13, %r12
je .L35
.L45:
movl $0, %ebx
jmp .L30
.L96:
movq 1560(%rsp), %rax
subq %fs:40, %rax
jne .L97
call _ZSt16__throw_bad_castv@PLT
.L97:
call __stack_chk_fail@PLT
.L33:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L34
.L35:
movq 16(%rsp), %rbx
movq 24(%rsp), %r13
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L98
cmpb $0, 56(%r12)
je .L38
movzbl 67(%r12), %eax
.L39:
movsbl %al, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 8(%rsp), %rax
movsd (%rax), %xmm1
leaq -48(%r14), %rax
leaq 0(%r13,%rbx), %rdx
.L40:
movsd (%rax), %xmm0
divsd %xmm1, %xmm0
movsd %xmm0, (%rax)
movsd (%rdx), %xmm0
divsd %xmm1, %xmm0
movsd %xmm0, (%rdx)
addq $8, %rax
addq $8, %rdx
cmpq %r14, %rax
jne .L40
movq 40(%rsp), %rdi
movl $0, %ecx
movl $0, %r8d
jmp .L43
.L98:
movq 1560(%rsp), %rax
subq %fs:40, %rax
jne .L99
call _ZSt16__throw_bad_castv@PLT
.L99:
call __stack_chk_fail@PLT
.L38:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
jmp .L39
.L41:
addl $1, %r8d
subq $48, %rcx
addq $48, %rdi
cmpl $6, %r8d
je .L100
.L43:
cmpl %r15d, %r8d
je .L41
movsd -48(%rdi,%r15,8), %xmm1
leaq -48(%rdi), %rax
movq %rbx, %rdx
subq %rcx, %rdx
.L42:
leaq (%rax,%rcx), %rsi
movapd %xmm1, %xmm2
mulsd (%rsi,%r13), %xmm2
movsd (%rax), %xmm0
subsd %xmm2, %xmm0
movsd %xmm0, (%rax)
leaq (%rdx,%rcx), %rsi
movapd %xmm1, %xmm2
mulsd (%rsi,%r13), %xmm2
movsd (%rdx), %xmm0
subsd %xmm2, %xmm0
movsd %xmm0, (%rdx)
addq $8, %rax
addq $8, %rdx
cmpq %rdi, %rax
jne .L42
jmp .L41
.L100:
addq $1, %r15
addq $48, %r13
addq $48, %r14
addq $56, 8(%rsp)
cmpq $6, %r15
je .L101
.L27:
leaq 288(%rbx), %rax
movq %rax, 32(%rsp)
movq %rbx, %r12
movq %rbx, 16(%rsp)
movq %r13, 24(%rsp)
movq %rax, %r13
jmp .L45
.L101:
movq %rbx, %r14
movq 48(%rsp), %rbx
movq 56(%rsp), %r12
leaq _ZSt4cout(%rip), %r13
jmp .L44
.L46:
movl $9, %esi
call _ZNSo3putEc@PLT
.L47:
addq $1, %rbp
cmpq $6, %rbp
je .L102
.L48:
movsd (%rbx,%rbp,8), %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movb $9, 100(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L46
leaq 100(%rsp), %rsi
movl $1, %edx
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L47
.L102:
movq 0(%r13), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %rbp
testq %rbp, %rbp
je .L103
cmpb $0, 56(%rbp)
je .L51
movzbl 67(%rbp), %eax
.L52:
movsbl %al, %esi
movq %r13, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $48, %rbx
cmpq %r12, %rbx
je .L104
.L44:
movl $0, %ebp
jmp .L48
.L103:
movq 1560(%rsp), %rax
subq %fs:40, %rax
jne .L105
call _ZSt16__throw_bad_castv@PLT
.L105:
call __stack_chk_fail@PLT
.L51:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
jmp .L52
.L104:
leaq _ZSt4cout(%rip), %rbp
movq 32(%rsp), %r12
jmp .L53
.L54:
movl $9, %esi
call _ZNSo3putEc@PLT
.L55:
addq $1, %rbx
cmpq $6, %rbx
je .L106
.L56:
movsd (%r14,%rbx,8), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movb $9, 100(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L54
leaq 100(%rsp), %rsi
movl $1, %edx
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L55
.L106:
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbx
testq %rbx, %rbx
je .L107
cmpb $0, 56(%rbx)
je .L59
movzbl 67(%rbx), %eax
.L60:
movsbl %al, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $48, %r14
cmpq %r12, %r14
je .L61
.L53:
movl $0, %ebx
jmp .L56
.L107:
movq 1560(%rsp), %rax
subq %fs:40, %rax
jne .L108
call _ZSt16__throw_bad_castv@PLT
.L108:
call __stack_chk_fail@PLT
.L59:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L60
.L61:
leaq 72(%rsp), %rdi
movl $288, %esi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movl $288, %esi
call cudaMalloc@PLT
leaq 688(%rsp), %rsi
movl $1, %ecx
movl $288, %edx
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
leaq 1264(%rsp), %rsi
movl $1, %ecx
movl $288, %edx
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl $6, 88(%rsp)
movl $6, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
call cudaDeviceSynchronize@PLT
movl 96(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 88(%rsp), %rdx
movq 100(%rsp), %rdi
movl 108(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L109
.L62:
call cudaDeviceSynchronize@PLT
leaq 112(%rsp), %r12
movl $2, %ecx
movl $288, %edx
movq 72(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq 1264(%rsp), %rdi
movl $2, %ecx
movl $288, %edx
movq 80(%rsp), %rsi
call cudaMemcpy@PLT
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %r13d
leaq _ZSt4cout(%rip), %rbp
jmp .L63
.L109:
movq 80(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z35__device_stub__Z13Invert_MatrixPdS_PdS_
jmp .L62
.L64:
movl $9, %esi
call _ZNSo3putEc@PLT
.L65:
addq $1, %rbx
cmpq $6, %rbx
je .L110
.L66:
movsd (%r12,%rbx,8), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movb $9, 71(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L64
leaq 71(%rsp), %rsi
movl $1, %edx
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L65
.L110:
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbx
testq %rbx, %rbx
je .L111
cmpb $0, 56(%rbx)
je .L69
movzbl 67(%rbx), %eax
.L70:
movsbl %al, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $6, %r13d
addq $48, %r12
cmpl $36, %r13d
je .L71
.L63:
movl $0, %ebx
jmp .L66
.L111:
movq 1560(%rsp), %rax
subq %fs:40, %rax
jne .L112
call _ZSt16__throw_bad_castv@PLT
.L112:
call __stack_chk_fail@PLT
.L69:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L70
.L71:
movq 1560(%rsp), %rax
subq %fs:40, %rax
jne .L113
movl $0, %eax
addq $1576, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L113:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z13Invert_MatrixPdS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z13Invert_MatrixPdS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1072693248
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test_inv.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1544, %rsp # imm = 0x608
.cfi_def_cfa_offset 1600
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 384(%rsp), %rbx
movl $.L__const.main.mat, %esi
movl $288, %edx # imm = 0x120
movq %rbx, %rdi
callq memcpy@PLT
leaq 1248(%rsp), %rdi
movl $.L__const.main.mat, %esi
movl $288, %edx # imm = 0x120
callq memcpy@PLT
leaq 960(%rsp), %rax
leaq 672(%rsp), %rcx
xorl %edx, %edx
movabsq $4607182418800017408, %rsi # imm = 0x3FF0000000000000
jmp .LBB0_1
.p2align 4, 0x90
.LBB0_18: # in Loop: Header=BB0_1 Depth=1
incq %rdx
addq $48, %rax
addq $48, %rcx
cmpq $6, %rdx
je .LBB0_4
.LBB0_1: # %.preheader183
# =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
leaq (%rdx,%rdx,2), %rdi
shlq $4, %rdi
addq %rsp, %rdi
addq $672, %rdi # imm = 0x2A0
leaq (%rdi,%rdx,8), %rdi
xorl %r8d, %r8d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_16: # in Loop: Header=BB0_2 Depth=2
movq $0, (%rax,%r8,8)
movq $0, (%rcx,%r8,8)
.LBB0_17: # in Loop: Header=BB0_2 Depth=2
incq %r8
cmpq $6, %r8
je .LBB0_18
.LBB0_2: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
cmpq %r8, %rdx
jne .LBB0_16
# %bb.3: # in Loop: Header=BB0_2 Depth=2
movq %rsi, (%rax,%r8,8)
movq %rsi, (%rdi)
jmp .LBB0_17
.LBB0_4:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB0_98
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB0_7
# %bb.6:
movzbl 67(%r14), %eax
jmp .LBB0_8
.LBB0_7:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB0_98
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i123
cmpb $0, 56(%r14)
je .LBB0_11
# %bb.10:
movzbl 67(%r14), %eax
jmp .LBB0_12
.LBB0_11:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit126
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r12d, %r12d
leaq 96(%rsp), %r14
jmp .LBB0_13
.p2align 4, 0x90
.LBB0_22: # in Loop: Header=BB0_13 Depth=1
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_23: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit131
# in Loop: Header=BB0_13 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r12
addq $48, %rbx
cmpq $6, %r12
je .LBB0_24
.LBB0_13: # %.preheader182
# =>This Loop Header: Depth=1
# Child Loop BB0_14 Depth 2
xorl %r15d, %r15d
jmp .LBB0_14
.p2align 4, 0x90
.LBB0_29: # in Loop: Header=BB0_14 Depth=2
movq %rax, %rdi
movl $9, %esi
callq _ZNSo3putEc
.LBB0_30: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
# in Loop: Header=BB0_14 Depth=2
incq %r15
cmpq $6, %r15
je .LBB0_19
.LBB0_14: # Parent Loop BB0_13 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rbx,%r15,8), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movb $9, 96(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB0_29
# %bb.15: # in Loop: Header=BB0_14 Depth=2
movl $1, %edx
movq %rax, %rdi
movq %r14, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB0_30
.p2align 4, 0x90
.LBB0_19: # in Loop: Header=BB0_13 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB0_98
# %bb.20: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i128
# in Loop: Header=BB0_13 Depth=1
cmpb $0, 56(%r15)
je .LBB0_22
# %bb.21: # in Loop: Header=BB0_13 Depth=1
movzbl 67(%r15), %eax
jmp .LBB0_23
.LBB0_24: # %.preheader180.preheader
leaq 384(%rsp), %r15
leaq 672(%rsp), %r12
xorl %edi, %edi
leaq 96(%rsp), %rbx
movq %r12, %rbp
jmp .LBB0_25
.p2align 4, 0x90
.LBB0_42: # in Loop: Header=BB0_25 Depth=1
incq %rdi
addq $48, %r15
addq $48, %rbp
cmpq $6, %rdi
je .LBB0_43
.LBB0_25: # %.preheader180
# =>This Loop Header: Depth=1
# Child Loop BB0_26 Depth 2
# Child Loop BB0_27 Depth 3
# Child Loop BB0_36 Depth 2
# Child Loop BB0_38 Depth 2
# Child Loop BB0_40 Depth 3
movq %rdi, 40(%rsp) # 8-byte Spill
xorl %r13d, %r13d
jmp .LBB0_26
.p2align 4, 0x90
.LBB0_50: # in Loop: Header=BB0_26 Depth=2
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_51: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit141
# in Loop: Header=BB0_26 Depth=2
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r13
addq $48, %r12
cmpq $6, %r13
je .LBB0_31
.LBB0_26: # %.preheader178
# Parent Loop BB0_25 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_27 Depth 3
xorl %r14d, %r14d
jmp .LBB0_27
.p2align 4, 0x90
.LBB0_52: # in Loop: Header=BB0_27 Depth=3
movq %rax, %rdi
movl $9, %esi
callq _ZNSo3putEc
.LBB0_53: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit112
# in Loop: Header=BB0_27 Depth=3
incq %r14
cmpq $6, %r14
je .LBB0_47
.LBB0_27: # Parent Loop BB0_25 Depth=1
# Parent Loop BB0_26 Depth=2
# => This Inner Loop Header: Depth=3
movsd (%r12,%r14,8), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movb $9, 96(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB0_52
# %bb.28: # in Loop: Header=BB0_27 Depth=3
movl $1, %edx
movq %rax, %rdi
movq %rbx, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB0_53
.p2align 4, 0x90
.LBB0_47: # in Loop: Header=BB0_26 Depth=2
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB0_98
# %bb.48: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i138
# in Loop: Header=BB0_26 Depth=2
cmpb $0, 56(%r14)
je .LBB0_50
# %bb.49: # in Loop: Header=BB0_26 Depth=2
movzbl 67(%r14), %eax
jmp .LBB0_51
.p2align 4, 0x90
.LBB0_31: # in Loop: Header=BB0_25 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB0_98
# %bb.32: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i133
# in Loop: Header=BB0_25 Depth=1
cmpb $0, 56(%r14)
leaq 672(%rsp), %r12
je .LBB0_34
# %bb.33: # in Loop: Header=BB0_25 Depth=1
movzbl 67(%r14), %eax
jmp .LBB0_35
.p2align 4, 0x90
.LBB0_34: # in Loop: Header=BB0_25 Depth=1
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_35: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit136
# in Loop: Header=BB0_25 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 40(%rsp), %rdi # 8-byte Reload
leaq (%rdi,%rdi,2), %rax
shlq $4, %rax
addq %rsp, %rax
addq $384, %rax # imm = 0x180
movsd (%rax,%rdi,8), %xmm0 # xmm0 = mem[0],zero
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_36: # Parent Loop BB0_25 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r15,%rax,8), %xmm1 # xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movsd %xmm1, (%r15,%rax,8)
movsd (%rbp,%rax,8), %xmm1 # xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movsd %xmm1, (%rbp,%rax,8)
incq %rax
cmpq $6, %rax
jne .LBB0_36
# %bb.37: # %.preheader179.preheader
# in Loop: Header=BB0_25 Depth=1
movq %r12, %rax
leaq 384(%rsp), %rcx
xorl %edx, %edx
jmp .LBB0_38
.p2align 4, 0x90
.LBB0_41: # %.loopexit
# in Loop: Header=BB0_38 Depth=2
incq %rdx
addq $48, %rcx
addq $48, %rax
cmpq $6, %rdx
je .LBB0_42
.LBB0_38: # %.preheader179
# Parent Loop BB0_25 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_40 Depth 3
cmpq %rdi, %rdx
je .LBB0_41
# %bb.39: # in Loop: Header=BB0_38 Depth=2
leaq (%rdx,%rdx,2), %rsi
shlq $4, %rsi
addq %rsp, %rsi
addq $384, %rsi # imm = 0x180
movsd (%rsi,%rdi,8), %xmm0 # xmm0 = mem[0],zero
xorl %esi, %esi
.p2align 4, 0x90
.LBB0_40: # Parent Loop BB0_25 Depth=1
# Parent Loop BB0_38 Depth=2
# => This Inner Loop Header: Depth=3
movsd (%r15,%rsi,8), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm0, %xmm1
movsd (%rcx,%rsi,8), %xmm2 # xmm2 = mem[0],zero
subsd %xmm1, %xmm2
movsd %xmm2, (%rcx,%rsi,8)
movsd (%rbp,%rsi,8), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm0, %xmm1
movsd (%rax,%rsi,8), %xmm2 # xmm2 = mem[0],zero
subsd %xmm1, %xmm2
movsd %xmm2, (%rax,%rsi,8)
incq %rsi
cmpq $6, %rsi
jne .LBB0_40
jmp .LBB0_41
.LBB0_43: # %.preheader176.preheader
leaq 384(%rsp), %r15
xorl %r12d, %r12d
leaq 96(%rsp), %rbx
jmp .LBB0_44
.p2align 4, 0x90
.LBB0_56: # in Loop: Header=BB0_44 Depth=1
movzbl 67(%r14), %eax
.LBB0_58: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit146
# in Loop: Header=BB0_44 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r12
addq $48, %r15
cmpq $6, %r12
je .LBB0_59
.LBB0_44: # %.preheader176
# =>This Loop Header: Depth=1
# Child Loop BB0_45 Depth 2
xorl %r14d, %r14d
jmp .LBB0_45
.p2align 4, 0x90
.LBB0_46: # in Loop: Header=BB0_45 Depth=2
movl $1, %edx
movq %rax, %rdi
movq %rbx, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB0_64: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit115
# in Loop: Header=BB0_45 Depth=2
incq %r14
cmpq $6, %r14
je .LBB0_54
.LBB0_45: # Parent Loop BB0_44 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r15,%r14,8), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movb $9, 96(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
jne .LBB0_46
# %bb.63: # in Loop: Header=BB0_45 Depth=2
movq %rax, %rdi
movl $9, %esi
callq _ZNSo3putEc
jmp .LBB0_64
.p2align 4, 0x90
.LBB0_54: # in Loop: Header=BB0_44 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB0_98
# %bb.55: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i143
# in Loop: Header=BB0_44 Depth=1
cmpb $0, 56(%r14)
jne .LBB0_56
# %bb.57: # in Loop: Header=BB0_44 Depth=1
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
jmp .LBB0_58
.LBB0_59: # %.preheader174.preheader
leaq 672(%rsp), %r15
xorl %r12d, %r12d
leaq 96(%rsp), %rbx
jmp .LBB0_60
.p2align 4, 0x90
.LBB0_68: # in Loop: Header=BB0_60 Depth=1
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_69: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit151
# in Loop: Header=BB0_60 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r12
addq $48, %r15
cmpq $6, %r12
je .LBB0_70
.LBB0_60: # %.preheader174
# =>This Loop Header: Depth=1
# Child Loop BB0_61 Depth 2
xorl %r14d, %r14d
jmp .LBB0_61
.p2align 4, 0x90
.LBB0_62: # in Loop: Header=BB0_61 Depth=2
movl $1, %edx
movq %rax, %rdi
movq %rbx, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB0_76: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit118
# in Loop: Header=BB0_61 Depth=2
incq %r14
cmpq $6, %r14
je .LBB0_65
.LBB0_61: # Parent Loop BB0_60 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r15,%r14,8), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movb $9, 96(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
jne .LBB0_62
# %bb.75: # in Loop: Header=BB0_61 Depth=2
movq %rax, %rdi
movl $9, %esi
callq _ZNSo3putEc
jmp .LBB0_76
.p2align 4, 0x90
.LBB0_65: # in Loop: Header=BB0_60 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB0_98
# %bb.66: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i148
# in Loop: Header=BB0_60 Depth=1
cmpb $0, 56(%r14)
je .LBB0_68
# %bb.67: # in Loop: Header=BB0_60 Depth=1
movzbl 67(%r14), %eax
jmp .LBB0_69
.LBB0_70:
leaq 16(%rsp), %rdi
movl $288, %esi # imm = 0x120
callq hipMalloc
leaq 8(%rsp), %rdi
movl $288, %esi # imm = 0x120
callq hipMalloc
movq 16(%rsp), %rdi
leaq 1248(%rsp), %rsi
movl $288, %edx # imm = 0x120
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 960(%rsp), %rsi
movl $288, %edx # imm = 0x120
movl $1, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $25769803782, %rdx # imm = 0x600000006
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_72
# %bb.71:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13Invert_MatrixPdS_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_72:
callq hipDeviceSynchronize
movq 16(%rsp), %rsi
leaq 96(%rsp), %rbx
movl $288, %edx # imm = 0x120
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rsi
leaq 960(%rsp), %rdi
movl $288, %edx # imm = 0x120
movl $2, %ecx
callq hipMemcpy
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB0_98
# %bb.73: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i153
cmpb $0, 56(%r14)
je .LBB0_77
# %bb.74:
movzbl 67(%r14), %eax
jmp .LBB0_78
.LBB0_77:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_78: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit156
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB0_98
# %bb.79: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i158
cmpb $0, 56(%r14)
je .LBB0_81
# %bb.80:
movzbl 67(%r14), %ecx
jmp .LBB0_82
.LBB0_81:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB0_82: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit161
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB0_98
# %bb.83: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i163
cmpb $0, 56(%r14)
je .LBB0_85
# %bb.84:
movzbl 67(%r14), %ecx
jmp .LBB0_86
.LBB0_85:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB0_86: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit166
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r12d, %r12d
leaq 24(%rsp), %r14
jmp .LBB0_87
.p2align 4, 0x90
.LBB0_93: # in Loop: Header=BB0_87 Depth=1
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_94: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit171
# in Loop: Header=BB0_87 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r12
addq $48, %rbx
cmpq $6, %r12
je .LBB0_95
.LBB0_87: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_88 Depth 2
xorl %r15d, %r15d
jmp .LBB0_88
.p2align 4, 0x90
.LBB0_89: # in Loop: Header=BB0_88 Depth=2
movl $1, %edx
movq %rax, %rdi
movq %r14, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB0_97: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit121
# in Loop: Header=BB0_88 Depth=2
incq %r15
cmpq $6, %r15
je .LBB0_90
.LBB0_88: # Parent Loop BB0_87 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rbx,%r15,8), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movb $9, 24(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
jne .LBB0_89
# %bb.96: # in Loop: Header=BB0_88 Depth=2
movq %rax, %rdi
movl $9, %esi
callq _ZNSo3putEc
jmp .LBB0_97
.p2align 4, 0x90
.LBB0_90: # in Loop: Header=BB0_87 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB0_98
# %bb.91: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i168
# in Loop: Header=BB0_87 Depth=1
cmpb $0, 56(%r15)
je .LBB0_93
# %bb.92: # in Loop: Header=BB0_87 Depth=1
movzbl 67(%r15), %eax
jmp .LBB0_94
.LBB0_95:
xorl %eax, %eax
addq $1544, %rsp # imm = 0x608
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_98:
.cfi_def_cfa_offset 1600
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z28__device_stub__Invert_MatrixPdS_ # -- Begin function _Z28__device_stub__Invert_MatrixPdS_
.p2align 4, 0x90
.type _Z28__device_stub__Invert_MatrixPdS_,@function
_Z28__device_stub__Invert_MatrixPdS_: # @_Z28__device_stub__Invert_MatrixPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13Invert_MatrixPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z28__device_stub__Invert_MatrixPdS_, .Lfunc_end1-_Z28__device_stub__Invert_MatrixPdS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13Invert_MatrixPdS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L__const.main.mat,@object # @__const.main.mat
.section .rodata,"a",@progbits
.p2align 4, 0x0
.L__const.main.mat:
.quad 0x3faef60e0eb67c28 # double 0.060470999999999997
.quad 0x3fd2afdda8bd230c # double 0.29198400000000002
.quad 0x3fd7d590c0ad03da # double 0.37241000000000002
.quad 0x3faaf87ad080b674 # double 0.052677000000000002
.quad 0x3fdabc5154866a12 # double 0.417744
.quad 0x3fe656e264e48627 # double 0.698106
.quad 0x3fd98d716d2aa5c6 # double 0.399258
.quad 0x3fdba02b841248d8 # double 0.43165100000000001
.quad 0x3fc95bee3d5fdcdf # double 0.19811799999999999
.quad 0x3fe79c886162f167 # double 0.73785800000000001
.quad 0x3fef752977c88e7a # double 0.98305200000000004
.quad 0x3fe55432873bc904 # double 0.66652800000000001
.quad 0x3fe0dc2b0ea18373 # double 0.52687600000000001
.quad 0x3f8fb7a5f41aef70 # double 0.015487000000000001
.quad 0x3fdf570c564f97ee # double 0.48968800000000001
.quad 0x3fd1393ee5eedcc2 # double 0.269119
.quad 0x3fd34b09e98dcdb3 # double 0.30145499999999997
.quad 0x3fc6cd07852f7f4a # double 0.17813200000000001
.quad 0x3fdaacd5b6805a2d # double 0.41679899999999998
.quad 0x3fef7d73c9257860 # double 0.98406400000000004
.quad 0x3fd5ba40d90e23af # double 0.33949299999999999
.quad 0x3fdb0fbeb9e492bc # double 0.42283599999999999
.quad 0x3fe66f672b884407 # double 0.70109900000000003
.quad 0x3fc062c343b70ef5 # double 0.12801399999999999
.quad 0x3fe504ff43419e30 # double 0.65686
.quad 0x3fc565c2d2780779 # double 0.16716800000000001
.quad 0x3fee73c0c1fc8f32 # double 0.95162999999999998
.quad 0x3fe18828c36da87a # double 0.547871
.quad 0x3fe552a62aa1943a # double 0.66633900000000001
.quad 0x3feff8769ec2ce46 # double 0.99907999999999997
.quad 0x3fe4185ad538ac19 # double 0.627973
.quad 0x3fbb30f8c64fdb0a # double 0.106216
.quad 0x3fed735c182ecaef # double 0.92033200000000004
.quad 0x3fee2ae6c8f75537 # double 0.94273700000000005
.quad 0x3fe140852b4d8ba4 # double 0.53912599999999999
.quad 0x3fc5e74afd545415 # double 0.171121
.size .L__const.main.mat, 288
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "haha"
.size .L.str, 5
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "blah"
.size .L.str.1, 5
.type _Z13Invert_MatrixPdS_,@object # @_Z13Invert_MatrixPdS_
.section .rodata,"a",@progbits
.globl _Z13Invert_MatrixPdS_
.p2align 3, 0x0
_Z13Invert_MatrixPdS_:
.quad _Z28__device_stub__Invert_MatrixPdS_
.size _Z13Invert_MatrixPdS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13Invert_MatrixPdS_"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__Invert_MatrixPdS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cout
.addrsig_sym _Z13Invert_MatrixPdS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda.h"
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
const int iSize = 50;
__global__ void vector_addition_kernel(float *A, float *B, float *C, int n)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i<n)
C[i] = A[i] + B[i];
}
void vector_addition(float *h_A, float *h_B, float *h_C, int n)
{
dim3 DimGrid((n-1)/16+1,1,1);
dim3 DimBlock(16,1,1);
int size = n *sizeof(float);
float *d_A, *d_B, *d_C;
cudaMalloc((void**)&d_A,size);
cudaMemcpy(d_A,h_A,size,cudaMemcpyHostToDevice);
cudaMalloc((void**)&d_B,size);
cudaMemcpy(d_B,h_B,size,cudaMemcpyHostToDevice);
cudaMalloc((void**)&d_C,size);
vector_addition_kernel<<<DimGrid, DimBlock>>>(d_A, d_B, d_C, n);
cudaMemcpy(h_C, d_C,size,cudaMemcpyDeviceToHost);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
}
int main()
{
float h_A[iSize], h_B[iSize], h_C[iSize];
for(int i=0; i<iSize; i++){
h_A[i] = float(i);
h_B[i] = float(i*i);
}
vector_addition(h_A,h_B,h_C,iSize);
printf("The results are:\n");
for(int i=0; i<iSize; i++)
printf("%3.1f\t",h_C[i]);
return 0;
} | code for sm_80
Function : _Z22vector_addition_kernelPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda.h"
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
const int iSize = 50;
__global__ void vector_addition_kernel(float *A, float *B, float *C, int n)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i<n)
C[i] = A[i] + B[i];
}
void vector_addition(float *h_A, float *h_B, float *h_C, int n)
{
dim3 DimGrid((n-1)/16+1,1,1);
dim3 DimBlock(16,1,1);
int size = n *sizeof(float);
float *d_A, *d_B, *d_C;
cudaMalloc((void**)&d_A,size);
cudaMemcpy(d_A,h_A,size,cudaMemcpyHostToDevice);
cudaMalloc((void**)&d_B,size);
cudaMemcpy(d_B,h_B,size,cudaMemcpyHostToDevice);
cudaMalloc((void**)&d_C,size);
vector_addition_kernel<<<DimGrid, DimBlock>>>(d_A, d_B, d_C, n);
cudaMemcpy(h_C, d_C,size,cudaMemcpyDeviceToHost);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
}
int main()
{
float h_A[iSize], h_B[iSize], h_C[iSize];
for(int i=0; i<iSize; i++){
h_A[i] = float(i);
h_B[i] = float(i*i);
}
vector_addition(h_A,h_B,h_C,iSize);
printf("The results are:\n");
for(int i=0; i<iSize; i++)
printf("%3.1f\t",h_C[i]);
return 0;
} | .file "tmpxft_0003ce7d_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z22vector_addition_kernelPfS_S_iPfS_S_i
.type _Z47__device_stub__Z22vector_addition_kernelPfS_S_iPfS_S_i, @function
_Z47__device_stub__Z22vector_addition_kernelPfS_S_iPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22vector_addition_kernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z47__device_stub__Z22vector_addition_kernelPfS_S_iPfS_S_i, .-_Z47__device_stub__Z22vector_addition_kernelPfS_S_iPfS_S_i
.globl _Z22vector_addition_kernelPfS_S_i
.type _Z22vector_addition_kernelPfS_S_i, @function
_Z22vector_addition_kernelPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z22vector_addition_kernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z22vector_addition_kernelPfS_S_i, .-_Z22vector_addition_kernelPfS_S_i
.globl _Z15vector_additionPfS_S_i
.type _Z15vector_additionPfS_S_i, @function
_Z15vector_additionPfS_S_i:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r14
movq %rsi, %r13
movq %rdx, %r12
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leal 14(%rcx), %eax
movl %ecx, %edx
subl $1, %edx
cmovns %edx, %eax
sarl $4, %eax
addl $1, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $16, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leal 0(,%rcx,4), %ebx
movslq %ebx, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl %ebp, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z47__device_stub__Z22vector_addition_kernelPfS_S_iPfS_S_i
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z15vector_additionPfS_S_i, .-_Z15vector_additionPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "The results are:\n"
.LC1:
.string "%3.1f\t"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $624, %rsp
.cfi_def_cfa_offset 656
movq %fs:40, %rax
movq %rax, 616(%rsp)
xorl %eax, %eax
.L18:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rsp,%rax,4)
movl %eax, %edx
imull %eax, %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, 208(%rsp,%rax,4)
addq $1, %rax
cmpq $50, %rax
jne .L18
leaq 416(%rsp), %rbx
leaq 208(%rsp), %rsi
movq %rsp, %rdi
movl $50, %ecx
movq %rbx, %rdx
call _Z15vector_additionPfS_S_i
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 616(%rsp), %r12
leaq .LC1(%rip), %rbp
.L19:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L19
movq 616(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $624, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "_Z22vector_addition_kernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z22vector_addition_kernelPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda.h"
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
const int iSize = 50;
__global__ void vector_addition_kernel(float *A, float *B, float *C, int n)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i<n)
C[i] = A[i] + B[i];
}
void vector_addition(float *h_A, float *h_B, float *h_C, int n)
{
dim3 DimGrid((n-1)/16+1,1,1);
dim3 DimBlock(16,1,1);
int size = n *sizeof(float);
float *d_A, *d_B, *d_C;
cudaMalloc((void**)&d_A,size);
cudaMemcpy(d_A,h_A,size,cudaMemcpyHostToDevice);
cudaMalloc((void**)&d_B,size);
cudaMemcpy(d_B,h_B,size,cudaMemcpyHostToDevice);
cudaMalloc((void**)&d_C,size);
vector_addition_kernel<<<DimGrid, DimBlock>>>(d_A, d_B, d_C, n);
cudaMemcpy(h_C, d_C,size,cudaMemcpyDeviceToHost);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
}
int main()
{
float h_A[iSize], h_B[iSize], h_C[iSize];
for(int i=0; i<iSize; i++){
h_A[i] = float(i);
h_B[i] = float(i*i);
}
vector_addition(h_A,h_B,h_C,iSize);
printf("The results are:\n");
for(int i=0; i<iSize; i++)
printf("%3.1f\t",h_C[i]);
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
const int iSize = 50;
__global__ void vector_addition_kernel(float *A, float *B, float *C, int n)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i<n)
C[i] = A[i] + B[i];
}
void vector_addition(float *h_A, float *h_B, float *h_C, int n)
{
dim3 DimGrid((n-1)/16+1,1,1);
dim3 DimBlock(16,1,1);
int size = n *sizeof(float);
float *d_A, *d_B, *d_C;
hipMalloc((void**)&d_A,size);
hipMemcpy(d_A,h_A,size,hipMemcpyHostToDevice);
hipMalloc((void**)&d_B,size);
hipMemcpy(d_B,h_B,size,hipMemcpyHostToDevice);
hipMalloc((void**)&d_C,size);
vector_addition_kernel<<<DimGrid, DimBlock>>>(d_A, d_B, d_C, n);
hipMemcpy(h_C, d_C,size,hipMemcpyDeviceToHost);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
}
int main()
{
float h_A[iSize], h_B[iSize], h_C[iSize];
for(int i=0; i<iSize; i++){
h_A[i] = float(i);
h_B[i] = float(i*i);
}
vector_addition(h_A,h_B,h_C,iSize);
printf("The results are:\n");
for(int i=0; i<iSize; i++)
printf("%3.1f\t",h_C[i]);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
const int iSize = 50;
__global__ void vector_addition_kernel(float *A, float *B, float *C, int n)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i<n)
C[i] = A[i] + B[i];
}
void vector_addition(float *h_A, float *h_B, float *h_C, int n)
{
dim3 DimGrid((n-1)/16+1,1,1);
dim3 DimBlock(16,1,1);
int size = n *sizeof(float);
float *d_A, *d_B, *d_C;
hipMalloc((void**)&d_A,size);
hipMemcpy(d_A,h_A,size,hipMemcpyHostToDevice);
hipMalloc((void**)&d_B,size);
hipMemcpy(d_B,h_B,size,hipMemcpyHostToDevice);
hipMalloc((void**)&d_C,size);
vector_addition_kernel<<<DimGrid, DimBlock>>>(d_A, d_B, d_C, n);
hipMemcpy(h_C, d_C,size,hipMemcpyDeviceToHost);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
}
int main()
{
float h_A[iSize], h_B[iSize], h_C[iSize];
for(int i=0; i<iSize; i++){
h_A[i] = float(i);
h_B[i] = float(i*i);
}
vector_addition(h_A,h_B,h_C,iSize);
printf("The results are:\n");
for(int i=0; i<iSize; i++)
printf("%3.1f\t",h_C[i]);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22vector_addition_kernelPfS_S_i
.globl _Z22vector_addition_kernelPfS_S_i
.p2align 8
.type _Z22vector_addition_kernelPfS_S_i,@function
_Z22vector_addition_kernelPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22vector_addition_kernelPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22vector_addition_kernelPfS_S_i, .Lfunc_end0-_Z22vector_addition_kernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22vector_addition_kernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z22vector_addition_kernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
const int iSize = 50;
__global__ void vector_addition_kernel(float *A, float *B, float *C, int n)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i<n)
C[i] = A[i] + B[i];
}
void vector_addition(float *h_A, float *h_B, float *h_C, int n)
{
dim3 DimGrid((n-1)/16+1,1,1);
dim3 DimBlock(16,1,1);
int size = n *sizeof(float);
float *d_A, *d_B, *d_C;
hipMalloc((void**)&d_A,size);
hipMemcpy(d_A,h_A,size,hipMemcpyHostToDevice);
hipMalloc((void**)&d_B,size);
hipMemcpy(d_B,h_B,size,hipMemcpyHostToDevice);
hipMalloc((void**)&d_C,size);
vector_addition_kernel<<<DimGrid, DimBlock>>>(d_A, d_B, d_C, n);
hipMemcpy(h_C, d_C,size,hipMemcpyDeviceToHost);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
}
int main()
{
float h_A[iSize], h_B[iSize], h_C[iSize];
for(int i=0; i<iSize; i++){
h_A[i] = float(i);
h_B[i] = float(i*i);
}
vector_addition(h_A,h_B,h_C,iSize);
printf("The results are:\n");
for(int i=0; i<iSize; i++)
printf("%3.1f\t",h_C[i]);
return 0;
} | .text
.file "kernel.hip"
.globl _Z37__device_stub__vector_addition_kernelPfS_S_i # -- Begin function _Z37__device_stub__vector_addition_kernelPfS_S_i
.p2align 4, 0x90
.type _Z37__device_stub__vector_addition_kernelPfS_S_i,@function
_Z37__device_stub__vector_addition_kernelPfS_S_i: # @_Z37__device_stub__vector_addition_kernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22vector_addition_kernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z37__device_stub__vector_addition_kernelPfS_S_i, .Lfunc_end0-_Z37__device_stub__vector_addition_kernelPfS_S_i
.cfi_endproc
# -- End function
.globl _Z15vector_additionPfS_S_i # -- Begin function _Z15vector_additionPfS_S_i
.p2align 4, 0x90
.type _Z15vector_additionPfS_S_i,@function
_Z15vector_additionPfS_S_i: # @_Z15vector_additionPfS_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %r15d
movq %rdx, 32(%rsp) # 8-byte Spill
movq %rsi, %rbp
movq %rdi, %rbx
leal -1(%r15), %eax
leal 14(%r15), %r12d
testl %eax, %eax
cmovnsl %eax, %r12d
sarl $4, %r12d
incl %r12d
movabsq $4294967296, %r13 # imm = 0x100000000
orq %r13, %r12
leal (,%r15,4), %eax
movslq %eax, %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %rbp, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
orq $16, %r13
movq %r12, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %r15d, 28(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z22vector_addition_kernelPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
movq 32(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z15vector_additionPfS_S_i, .Lfunc_end1-_Z15vector_additionPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $624, %rsp # imm = 0x270
.cfi_def_cfa_offset 640
.cfi_offset %rbx, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movl %eax, %ecx
imull %eax, %ecx
xorps %xmm1, %xmm1
cvtsi2ss %ecx, %xmm1
movss %xmm0, 416(%rsp,%rax,4)
movss %xmm1, 208(%rsp,%rax,4)
incq %rax
cmpq $50, %rax
jne .LBB2_1
# %bb.2:
leaq 416(%rsp), %rdi
leaq 208(%rsp), %rsi
movq %rsp, %rdx
movl $50, %ecx
callq _Z15vector_additionPfS_S_i
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
movss (%rsp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %rbx
cmpq $50, %rbx
jne .LBB2_3
# %bb.4:
xorl %eax, %eax
addq $624, %rsp # imm = 0x270
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22vector_addition_kernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22vector_addition_kernelPfS_S_i,@object # @_Z22vector_addition_kernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z22vector_addition_kernelPfS_S_i
.p2align 3, 0x0
_Z22vector_addition_kernelPfS_S_i:
.quad _Z37__device_stub__vector_addition_kernelPfS_S_i
.size _Z22vector_addition_kernelPfS_S_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%3.1f\t"
.size .L.str.1, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z22vector_addition_kernelPfS_S_i"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "The results are:"
.size .Lstr, 17
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__vector_addition_kernelPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22vector_addition_kernelPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z22vector_addition_kernelPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22vector_addition_kernelPfS_S_i
.globl _Z22vector_addition_kernelPfS_S_i
.p2align 8
.type _Z22vector_addition_kernelPfS_S_i,@function
_Z22vector_addition_kernelPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22vector_addition_kernelPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22vector_addition_kernelPfS_S_i, .Lfunc_end0-_Z22vector_addition_kernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22vector_addition_kernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z22vector_addition_kernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003ce7d_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z22vector_addition_kernelPfS_S_iPfS_S_i
.type _Z47__device_stub__Z22vector_addition_kernelPfS_S_iPfS_S_i, @function
_Z47__device_stub__Z22vector_addition_kernelPfS_S_iPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22vector_addition_kernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z47__device_stub__Z22vector_addition_kernelPfS_S_iPfS_S_i, .-_Z47__device_stub__Z22vector_addition_kernelPfS_S_iPfS_S_i
.globl _Z22vector_addition_kernelPfS_S_i
.type _Z22vector_addition_kernelPfS_S_i, @function
_Z22vector_addition_kernelPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z22vector_addition_kernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z22vector_addition_kernelPfS_S_i, .-_Z22vector_addition_kernelPfS_S_i
.globl _Z15vector_additionPfS_S_i
.type _Z15vector_additionPfS_S_i, @function
_Z15vector_additionPfS_S_i:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r14
movq %rsi, %r13
movq %rdx, %r12
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leal 14(%rcx), %eax
movl %ecx, %edx
subl $1, %edx
cmovns %edx, %eax
sarl $4, %eax
addl $1, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $16, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leal 0(,%rcx,4), %ebx
movslq %ebx, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl %ebp, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z47__device_stub__Z22vector_addition_kernelPfS_S_iPfS_S_i
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z15vector_additionPfS_S_i, .-_Z15vector_additionPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "The results are:\n"
.LC1:
.string "%3.1f\t"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $624, %rsp
.cfi_def_cfa_offset 656
movq %fs:40, %rax
movq %rax, 616(%rsp)
xorl %eax, %eax
.L18:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rsp,%rax,4)
movl %eax, %edx
imull %eax, %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, 208(%rsp,%rax,4)
addq $1, %rax
cmpq $50, %rax
jne .L18
leaq 416(%rsp), %rbx
leaq 208(%rsp), %rsi
movq %rsp, %rdi
movl $50, %ecx
movq %rbx, %rdx
call _Z15vector_additionPfS_S_i
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 616(%rsp), %r12
leaq .LC1(%rip), %rbp
.L19:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L19
movq 616(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $624, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "_Z22vector_addition_kernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z22vector_addition_kernelPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z37__device_stub__vector_addition_kernelPfS_S_i # -- Begin function _Z37__device_stub__vector_addition_kernelPfS_S_i
.p2align 4, 0x90
.type _Z37__device_stub__vector_addition_kernelPfS_S_i,@function
_Z37__device_stub__vector_addition_kernelPfS_S_i: # @_Z37__device_stub__vector_addition_kernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22vector_addition_kernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z37__device_stub__vector_addition_kernelPfS_S_i, .Lfunc_end0-_Z37__device_stub__vector_addition_kernelPfS_S_i
.cfi_endproc
# -- End function
.globl _Z15vector_additionPfS_S_i # -- Begin function _Z15vector_additionPfS_S_i
.p2align 4, 0x90
.type _Z15vector_additionPfS_S_i,@function
_Z15vector_additionPfS_S_i: # @_Z15vector_additionPfS_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %r15d
movq %rdx, 32(%rsp) # 8-byte Spill
movq %rsi, %rbp
movq %rdi, %rbx
leal -1(%r15), %eax
leal 14(%r15), %r12d
testl %eax, %eax
cmovnsl %eax, %r12d
sarl $4, %r12d
incl %r12d
movabsq $4294967296, %r13 # imm = 0x100000000
orq %r13, %r12
leal (,%r15,4), %eax
movslq %eax, %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %rbp, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
orq $16, %r13
movq %r12, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %r15d, 28(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z22vector_addition_kernelPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
movq 32(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z15vector_additionPfS_S_i, .Lfunc_end1-_Z15vector_additionPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $624, %rsp # imm = 0x270
.cfi_def_cfa_offset 640
.cfi_offset %rbx, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movl %eax, %ecx
imull %eax, %ecx
xorps %xmm1, %xmm1
cvtsi2ss %ecx, %xmm1
movss %xmm0, 416(%rsp,%rax,4)
movss %xmm1, 208(%rsp,%rax,4)
incq %rax
cmpq $50, %rax
jne .LBB2_1
# %bb.2:
leaq 416(%rsp), %rdi
leaq 208(%rsp), %rsi
movq %rsp, %rdx
movl $50, %ecx
callq _Z15vector_additionPfS_S_i
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
movss (%rsp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %rbx
cmpq $50, %rbx
jne .LBB2_3
# %bb.4:
xorl %eax, %eax
addq $624, %rsp # imm = 0x270
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22vector_addition_kernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22vector_addition_kernelPfS_S_i,@object # @_Z22vector_addition_kernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z22vector_addition_kernelPfS_S_i
.p2align 3, 0x0
_Z22vector_addition_kernelPfS_S_i:
.quad _Z37__device_stub__vector_addition_kernelPfS_S_i
.size _Z22vector_addition_kernelPfS_S_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%3.1f\t"
.size .L.str.1, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z22vector_addition_kernelPfS_S_i"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "The results are:"
.size .Lstr, 17
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__vector_addition_kernelPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22vector_addition_kernelPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__
void saxpy(int n, float a, float* __restrict__ x, float* __restrict__ y)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < n) y[i] = a*x[i] + y[i];
} | code for sm_80
Function : _Z5saxpyifPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe400078e0205 */
/*00a0*/ LDG.E.CONSTANT R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e9900 */
/*00b0*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ FFMA R7, R2, c[0x0][0x164], R7 ; /* 0x0000590002077a23 */
/* 0x004fca0000000007 */
/*00d0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__
void saxpy(int n, float a, float* __restrict__ x, float* __restrict__ y)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < n) y[i] = a*x[i] + y[i];
} | .file "tmpxft_00006f44_00000000-6_example.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z5saxpyifPfS_ifPfS_
.type _Z28__device_stub__Z5saxpyifPfS_ifPfS_, @function
_Z28__device_stub__Z5saxpyifPfS_ifPfS_:
.LFB2081:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsi, 16(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
movq %rdx, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5saxpyifPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z28__device_stub__Z5saxpyifPfS_ifPfS_, .-_Z28__device_stub__Z5saxpyifPfS_ifPfS_
.globl _Z5saxpyifPfS_
.type _Z5saxpyifPfS_, @function
_Z5saxpyifPfS_:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z5saxpyifPfS_ifPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z5saxpyifPfS_, .-_Z5saxpyifPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5saxpyifPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5saxpyifPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__
void saxpy(int n, float a, float* __restrict__ x, float* __restrict__ y)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < n) y[i] = a*x[i] + y[i];
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__
void saxpy(int n, float a, float* __restrict__ x, float* __restrict__ y)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < n) y[i] = a*x[i] + y[i];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__
void saxpy(int n, float a, float* __restrict__ x, float* __restrict__ y)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < n) y[i] = a*x[i] + y[i];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5saxpyifPfS_
.globl _Z5saxpyifPfS_
.p2align 8
.type _Z5saxpyifPfS_,@function
_Z5saxpyifPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, s0, v2
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5saxpyifPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5saxpyifPfS_, .Lfunc_end0-_Z5saxpyifPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .actual_access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5saxpyifPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5saxpyifPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__
void saxpy(int n, float a, float* __restrict__ x, float* __restrict__ y)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < n) y[i] = a*x[i] + y[i];
} | .text
.file "example.hip"
.globl _Z20__device_stub__saxpyifPfS_ # -- Begin function _Z20__device_stub__saxpyifPfS_
.p2align 4, 0x90
.type _Z20__device_stub__saxpyifPfS_,@function
_Z20__device_stub__saxpyifPfS_: # @_Z20__device_stub__saxpyifPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5saxpyifPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__saxpyifPfS_, .Lfunc_end0-_Z20__device_stub__saxpyifPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5saxpyifPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5saxpyifPfS_,@object # @_Z5saxpyifPfS_
.section .rodata,"a",@progbits
.globl _Z5saxpyifPfS_
.p2align 3, 0x0
_Z5saxpyifPfS_:
.quad _Z20__device_stub__saxpyifPfS_
.size _Z5saxpyifPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5saxpyifPfS_"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__saxpyifPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5saxpyifPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5saxpyifPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe400078e0205 */
/*00a0*/ LDG.E.CONSTANT R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e9900 */
/*00b0*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ FFMA R7, R2, c[0x0][0x164], R7 ; /* 0x0000590002077a23 */
/* 0x004fca0000000007 */
/*00d0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5saxpyifPfS_
.globl _Z5saxpyifPfS_
.p2align 8
.type _Z5saxpyifPfS_,@function
_Z5saxpyifPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, s0, v2
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5saxpyifPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5saxpyifPfS_, .Lfunc_end0-_Z5saxpyifPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .actual_access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5saxpyifPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5saxpyifPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00006f44_00000000-6_example.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z5saxpyifPfS_ifPfS_
.type _Z28__device_stub__Z5saxpyifPfS_ifPfS_, @function
_Z28__device_stub__Z5saxpyifPfS_ifPfS_:
.LFB2081:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsi, 16(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
movq %rdx, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5saxpyifPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z28__device_stub__Z5saxpyifPfS_ifPfS_, .-_Z28__device_stub__Z5saxpyifPfS_ifPfS_
.globl _Z5saxpyifPfS_
.type _Z5saxpyifPfS_, @function
_Z5saxpyifPfS_:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z5saxpyifPfS_ifPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z5saxpyifPfS_, .-_Z5saxpyifPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5saxpyifPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5saxpyifPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "example.hip"
.globl _Z20__device_stub__saxpyifPfS_ # -- Begin function _Z20__device_stub__saxpyifPfS_
.p2align 4, 0x90
.type _Z20__device_stub__saxpyifPfS_,@function
_Z20__device_stub__saxpyifPfS_: # @_Z20__device_stub__saxpyifPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5saxpyifPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__saxpyifPfS_, .Lfunc_end0-_Z20__device_stub__saxpyifPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5saxpyifPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5saxpyifPfS_,@object # @_Z5saxpyifPfS_
.section .rodata,"a",@progbits
.globl _Z5saxpyifPfS_
.p2align 3, 0x0
_Z5saxpyifPfS_:
.quad _Z20__device_stub__saxpyifPfS_
.size _Z5saxpyifPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5saxpyifPfS_"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__saxpyifPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5saxpyifPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void ResetHeap_kernel(int *mplHeap, int *mplHeapPtr, int numBlock)
{
int index = threadIdx.x + blockDim.x * blockIdx.x;
if (index >= numBlock)
return;
if (index == 0)
mplHeapPtr[0] = numBlock - 1;
mplHeap[index] = numBlock - index - 1;
} | code for sm_80
Function : _Z16ResetHeap_kernelPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ISETP.NE.AND P0, PT, R4.reuse, RZ, PT ; /* 0x000000ff0400720c */
/* 0x040fe20003f05270 */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0080*/ LOP3.LUT R0, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff007212 */
/* 0x000fe200078e33ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe200078e0205 */
/*00b0*/ IADD3 R9, R0, c[0x0][0x170], RZ ; /* 0x00005c0000097a10 */
/* 0x000fce0007ffe0ff */
/*00c0*/ @!P0 MOV R7, c[0x0][0x170] ; /* 0x00005c0000078a02 */
/* 0x000fe20000000f00 */
/*00d0*/ @!P0 IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff028624 */
/* 0x000fe200078e00ff */
/*00e0*/ @!P0 MOV R3, c[0x0][0x16c] ; /* 0x00005b0000038a02 */
/* 0x000fe40000000f00 */
/*00f0*/ @!P0 IADD3 R7, R7, -0x1, RZ ; /* 0xffffffff07078810 */
/* 0x000fca0007ffe0ff */
/*0100*/ @!P0 STG.E [R2.64], R7 ; /* 0x0000000702008986 */
/* 0x000fe8000c101904 */
/*0110*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void ResetHeap_kernel(int *mplHeap, int *mplHeapPtr, int numBlock)
{
int index = threadIdx.x + blockDim.x * blockIdx.x;
if (index >= numBlock)
return;
if (index == 0)
mplHeapPtr[0] = numBlock - 1;
mplHeap[index] = numBlock - index - 1;
} | .file "tmpxft_00029cb4_00000000-6_ResetHeap_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z16ResetHeap_kernelPiS_iPiS_i
.type _Z39__device_stub__Z16ResetHeap_kernelPiS_iPiS_i, @function
_Z39__device_stub__Z16ResetHeap_kernelPiS_iPiS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16ResetHeap_kernelPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z16ResetHeap_kernelPiS_iPiS_i, .-_Z39__device_stub__Z16ResetHeap_kernelPiS_iPiS_i
.globl _Z16ResetHeap_kernelPiS_i
.type _Z16ResetHeap_kernelPiS_i, @function
_Z16ResetHeap_kernelPiS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z16ResetHeap_kernelPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16ResetHeap_kernelPiS_i, .-_Z16ResetHeap_kernelPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16ResetHeap_kernelPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16ResetHeap_kernelPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void ResetHeap_kernel(int *mplHeap, int *mplHeapPtr, int numBlock)
{
int index = threadIdx.x + blockDim.x * blockIdx.x;
if (index >= numBlock)
return;
if (index == 0)
mplHeapPtr[0] = numBlock - 1;
mplHeap[index] = numBlock - index - 1;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ResetHeap_kernel(int *mplHeap, int *mplHeapPtr, int numBlock)
{
int index = threadIdx.x + blockDim.x * blockIdx.x;
if (index >= numBlock)
return;
if (index == 0)
mplHeapPtr[0] = numBlock - 1;
mplHeap[index] = numBlock - index - 1;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ResetHeap_kernel(int *mplHeap, int *mplHeapPtr, int numBlock)
{
int index = threadIdx.x + blockDim.x * blockIdx.x;
if (index >= numBlock)
return;
if (index == 0)
mplHeapPtr[0] = numBlock - 1;
mplHeap[index] = numBlock - index - 1;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16ResetHeap_kernelPiS_i
.globl _Z16ResetHeap_kernelPiS_i
.p2align 8
.type _Z16ResetHeap_kernelPiS_i,@function
_Z16ResetHeap_kernelPiS_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s2, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_4
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v1
s_cbranch_execz .LBB0_3
s_load_b64 s[4:5], s[0:1], 0x8
s_add_i32 s6, s2, -1
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v2, s6
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v2, s[4:5]
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_xad_u32 v4, v1, -1, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16ResetHeap_kernelPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16ResetHeap_kernelPiS_i, .Lfunc_end0-_Z16ResetHeap_kernelPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16ResetHeap_kernelPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16ResetHeap_kernelPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ResetHeap_kernel(int *mplHeap, int *mplHeapPtr, int numBlock)
{
int index = threadIdx.x + blockDim.x * blockIdx.x;
if (index >= numBlock)
return;
if (index == 0)
mplHeapPtr[0] = numBlock - 1;
mplHeap[index] = numBlock - index - 1;
} | .text
.file "ResetHeap_kernel.hip"
.globl _Z31__device_stub__ResetHeap_kernelPiS_i # -- Begin function _Z31__device_stub__ResetHeap_kernelPiS_i
.p2align 4, 0x90
.type _Z31__device_stub__ResetHeap_kernelPiS_i,@function
_Z31__device_stub__ResetHeap_kernelPiS_i: # @_Z31__device_stub__ResetHeap_kernelPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16ResetHeap_kernelPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z31__device_stub__ResetHeap_kernelPiS_i, .Lfunc_end0-_Z31__device_stub__ResetHeap_kernelPiS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16ResetHeap_kernelPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16ResetHeap_kernelPiS_i,@object # @_Z16ResetHeap_kernelPiS_i
.section .rodata,"a",@progbits
.globl _Z16ResetHeap_kernelPiS_i
.p2align 3, 0x0
_Z16ResetHeap_kernelPiS_i:
.quad _Z31__device_stub__ResetHeap_kernelPiS_i
.size _Z16ResetHeap_kernelPiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16ResetHeap_kernelPiS_i"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__ResetHeap_kernelPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16ResetHeap_kernelPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16ResetHeap_kernelPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ISETP.NE.AND P0, PT, R4.reuse, RZ, PT ; /* 0x000000ff0400720c */
/* 0x040fe20003f05270 */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0080*/ LOP3.LUT R0, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff007212 */
/* 0x000fe200078e33ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe200078e0205 */
/*00b0*/ IADD3 R9, R0, c[0x0][0x170], RZ ; /* 0x00005c0000097a10 */
/* 0x000fce0007ffe0ff */
/*00c0*/ @!P0 MOV R7, c[0x0][0x170] ; /* 0x00005c0000078a02 */
/* 0x000fe20000000f00 */
/*00d0*/ @!P0 IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff028624 */
/* 0x000fe200078e00ff */
/*00e0*/ @!P0 MOV R3, c[0x0][0x16c] ; /* 0x00005b0000038a02 */
/* 0x000fe40000000f00 */
/*00f0*/ @!P0 IADD3 R7, R7, -0x1, RZ ; /* 0xffffffff07078810 */
/* 0x000fca0007ffe0ff */
/*0100*/ @!P0 STG.E [R2.64], R7 ; /* 0x0000000702008986 */
/* 0x000fe8000c101904 */
/*0110*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16ResetHeap_kernelPiS_i
.globl _Z16ResetHeap_kernelPiS_i
.p2align 8
.type _Z16ResetHeap_kernelPiS_i,@function
_Z16ResetHeap_kernelPiS_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s2, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_4
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v1
s_cbranch_execz .LBB0_3
s_load_b64 s[4:5], s[0:1], 0x8
s_add_i32 s6, s2, -1
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v2, s6
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v2, s[4:5]
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_xad_u32 v4, v1, -1, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16ResetHeap_kernelPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16ResetHeap_kernelPiS_i, .Lfunc_end0-_Z16ResetHeap_kernelPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16ResetHeap_kernelPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16ResetHeap_kernelPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00029cb4_00000000-6_ResetHeap_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z16ResetHeap_kernelPiS_iPiS_i
.type _Z39__device_stub__Z16ResetHeap_kernelPiS_iPiS_i, @function
_Z39__device_stub__Z16ResetHeap_kernelPiS_iPiS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16ResetHeap_kernelPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z16ResetHeap_kernelPiS_iPiS_i, .-_Z39__device_stub__Z16ResetHeap_kernelPiS_iPiS_i
.globl _Z16ResetHeap_kernelPiS_i
.type _Z16ResetHeap_kernelPiS_i, @function
_Z16ResetHeap_kernelPiS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z16ResetHeap_kernelPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16ResetHeap_kernelPiS_i, .-_Z16ResetHeap_kernelPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16ResetHeap_kernelPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16ResetHeap_kernelPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ResetHeap_kernel.hip"
.globl _Z31__device_stub__ResetHeap_kernelPiS_i # -- Begin function _Z31__device_stub__ResetHeap_kernelPiS_i
.p2align 4, 0x90
.type _Z31__device_stub__ResetHeap_kernelPiS_i,@function
_Z31__device_stub__ResetHeap_kernelPiS_i: # @_Z31__device_stub__ResetHeap_kernelPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16ResetHeap_kernelPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z31__device_stub__ResetHeap_kernelPiS_i, .Lfunc_end0-_Z31__device_stub__ResetHeap_kernelPiS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16ResetHeap_kernelPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16ResetHeap_kernelPiS_i,@object # @_Z16ResetHeap_kernelPiS_i
.section .rodata,"a",@progbits
.globl _Z16ResetHeap_kernelPiS_i
.p2align 3, 0x0
_Z16ResetHeap_kernelPiS_i:
.quad _Z31__device_stub__ResetHeap_kernelPiS_i
.size _Z16ResetHeap_kernelPiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16ResetHeap_kernelPiS_i"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__ResetHeap_kernelPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16ResetHeap_kernelPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <fstream>
#include <stdio.h>
#include <stdlib.h>
#include <vector>
#include <math.h>
using namespace std;
// CUDA KERNEL FUNCTIONS
__global__ void Hello()
{
//int globalidx = threadIdx.z * blockDim.x * blockDim.y + threadIdx.y * blockDim.x + threadIdx.x;
int globalidx = blockIdx.x * blockDim.x + threadIdx.x;
// printf("blockIdx.x %d\n",blockIdx.x);
printf("Hello from blockx = %d\t tx = %d\t ty=%d\t tz=%d\t gi=%d\n",blockIdx.x, threadIdx.x, threadIdx.y, threadIdx.z, globalidx);
}
__global__ void Bluring(int array_2D_size, int summary, int *array_1D_cuda, int *blured_1D_cuda, int *cu_kernel_1d)
{
int globalidx = blockIdx.x * blockDim.x + threadIdx.x;
// printf("Hello from blockx = %d\t tx = %d\t ty=%d\t tz=%d\t gi=%d\n",blockIdx.x, threadIdx.x, threadIdx.y, threadIdx.z, globalidx);
int N = array_2D_size;
if(globalidx<N*N)
{
if ((globalidx >= 0 && globalidx <= N-1) | (globalidx % N == 0) | (globalidx >= N*N-N) | (globalidx % N >= N -1 && globalidx % N <= N*N -1))
{
blured_1D_cuda[globalidx]=array_1D_cuda[globalidx];
/*
if (globalidx == 0)
{
printf("blured_1D_cuda[%d] = %d\n",globalidx,blured_1D_cuda[globalidx]);
}
*/
} else
{
int top, bottom, left, right;
top = -N + globalidx; // [i-1][j]
bottom = N + globalidx; // [i+1][j]
left = -1 + globalidx; // [i][j-1]
right = 1 + globalidx; // [i][j+1]
/*
if (globalidx == 6)
{
printf("top = %d\t bottom = %d\t left = %d\t right = %d\n", top,bottom,left,right);
}
*/
int cross1, cross2,cross3,cross4;
cross1 = globalidx - N - 1; // [i-1][j-1]
cross2 = globalidx - N + 1; // [i-1][j+1]
cross3 = globalidx + N - 1; // [i+1][j-1]
cross4 = globalidx + N + 1; // [i+1][j+1]
/*
if (globalidx == 6)
{
printf("cross1 = %d\t cross2 = %d\t cross3 = %d\t cross4 = %d\n", cross1, cross2,cross3,cross4);
}
*/
int T1,T2,T3,T4,T5,T6,T7,T8,T9;
int temp1,temp2,temp3;
T1 = array_1D_cuda[cross1] * cu_kernel_1d[0*3+0];
T2 = array_1D_cuda[top] * cu_kernel_1d[0*3+1];
T3 = array_1D_cuda[cross2] * cu_kernel_1d[0*3+2];
temp1 = T1 + T2 + T3;
/*
if (globalidx == 6)
{
printf("T1 = %d\t T2 = %d\t T3 = %d\t temp1 = %d\n", T1, T2,T3,temp1);
}
*/
T4 = array_1D_cuda[left] * cu_kernel_1d[1*3+0];
T5 = array_1D_cuda[globalidx] * cu_kernel_1d[1*3+1];
T6 = array_1D_cuda[right] * cu_kernel_1d[1*3+2];
temp2 = T4 + T5 + T6;
/*
if (globalidx == 6)
{
printf("T4 = %d\t T5 = %d\t T6 = %d\t temp1 = %d\n", T4, T5,T6,temp2);
}
*/
T7 = array_1D_cuda[cross3] * cu_kernel_1d[2*3+0];
T8 = array_1D_cuda[bottom] * cu_kernel_1d[2*3+1];
T9 = array_1D_cuda[cross4] * cu_kernel_1d[2*3+2];
temp3 = T7 + T8 + T9;
/*
if (globalidx == 6)
{
printf("T7 = %d\t T8 = %d\t T9 = %d\t temp3 = %d\n", T7, T8,T9,temp3);
}
*/
blured_1D_cuda[globalidx] = temp1+temp2+temp3;
}
}
}
// CPU FUNCTIONS
int ** malloc_matrix(int N)
{
int ** matrix = (int **)malloc(N * sizeof(int *));
for (int i = 0; i < N; ++i)
{
matrix[i] = (int *)malloc(N * sizeof(int));
}
return matrix;
}
float ** malloc_matrix_float(int N)
{
float ** matrix = (float **)malloc(N * sizeof(float *));
for (int i = 0; i < N; ++i)
{
matrix[i] = (float *)malloc(N * sizeof(float));
}
return matrix;
}
void print_matrix(int * matrix, int N)
{
for (int j = 0; j < N; j++)
{
cout << matrix[j] << " ";
}
cout << endl;
}
void print_matrix(int ** matrix, int N)
{
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
{
cout << matrix[i][j] << " ";
}
cout << endl;
}
cout << endl;
}
void print_matrix(float ** matrix, int N)
{
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
{
cout << matrix[i][j] << " ";
}
cout << endl;
}
cout << endl;
}
void print_matrix(float * matrix, int N)
{
for (int j = 0; j < N; j++)
{
cout << matrix[j] << " ";
}
cout << endl;
}
void convert_1d_to_2d (int array_size, int * array_1D)
{
int ** array_2D;
int array_2D_size = sqrt(array_size);
array_2D = malloc_matrix(array_2D_size);
for (int i = 0; i < array_2D_size; i++)
{
for (int j = 0; j < array_2D_size; j++)
{
array_2D[i][j] = array_1D[i*array_2D_size + j];
}
}
print_matrix(array_2D,array_2D_size);
}
void convert_1d_to_2d_float (int array_size, float * array_1D)
{
float ** array_2D;
int array_2D_size = sqrt(array_size);
array_2D = malloc_matrix_float(array_2D_size);
for (int i = 0; i < array_2D_size; i++)
{
for (int j = 0; j < array_2D_size; j++)
{
array_2D[i][j] = array_1D[i*array_2D_size + j];
}
}
print_matrix(array_2D,array_2D_size);
}
// MAIN FUNCTION
int main(int argc, char *argv[]){
// IMAGE TO ARRAY
ifstream file("image_array.txt");
vector<int> image;
if(file.is_open())
{
while (!file.eof())
{
int temp;
file >> temp;
image.push_back(temp);
}
}
file.close();
image.pop_back();
// ARRAY CREATION
int array_1D_size = image.size();
int *array_1D = (int*)malloc(sizeof(int)*array_1D_size);
for (int i = 0; i < array_1D_size; i++)
{
array_1D[i] = image[i];
}
//convert_1d_to_2d(array_1D_size, array_1D);
// CREATION OF CONVOLUTION
int **kernel;
kernel = malloc_matrix(3);
for (int i = 0; i < 3; i++)
{
for (int j = 0; j < 3; j++)
{
kernel[i][j] = 1;
}
}
//print_matrix(kernel,3);
// 2D KERNEL TO 1D KERNEL
int *kernel_1d = (int*)malloc(sizeof(int)*3*3);
for (int i = 0; i < 3; i++)
{
for (int j = 0; j < 3; j++)
{
kernel_1d[i*3 + j] = kernel[i][j];
}
}
//print_matrix(kernel_1d,3*3);
// SUM of 1D KERNEL
int summary = 0;
for (int j = 0; j < 3*3; j++)
{
summary += kernel_1d[j];
}
//printf("summary = %d\n", summary);
//printf("This is done by CPU before CUDA threads\n");
// ---------- CUDA ZONE -------------
//printf("Start to allocate summary in CUDA\n");
// CONV KERNEL kernel_1d TO DEVICE
int *cu_kernel_1d;
int kernel_1d_size = 9;
cudaMalloc(&cu_kernel_1d, sizeof(int)*kernel_1d_size);
cudaMemcpy(cu_kernel_1d, kernel_1d, kernel_1d_size * sizeof(int), cudaMemcpyHostToDevice);
// ARRAY TO DEVICE
int *array_1D_cuda;
cudaMalloc(&array_1D_cuda, sizeof(int)*array_1D_size);
cudaMemcpy(array_1D_cuda, array_1D, array_1D_size * sizeof(int), cudaMemcpyHostToDevice);
// BLURED ARRAY ON HOST
int blured_1D_size = array_1D_size;
int *blured_1D = (int*)malloc(sizeof(int)*blured_1D_size);
// BLURED ARRAY ON DEVICE
int *blured_1D_cuda;
cudaMalloc(&blured_1D_cuda, sizeof(int)*blured_1D_size);
cudaMemcpy(blured_1D_cuda, blured_1D, blured_1D_size * sizeof(int), cudaMemcpyHostToDevice);
cudaDeviceSynchronize();
// BLURING PROCESS
int blocksDim = 10;
int threadsDim = array_1D_size /blocksDim;
//printf("array_1D_size = %d\n",array_1D_size );
int array_2D_size = sqrt(array_1D_size);
Bluring<<<blocksDim,threadsDim>>>(array_2D_size, summary, array_1D_cuda, blured_1D_cuda,cu_kernel_1d);
cudaMemcpy(blured_1D, blured_1D_cuda, blured_1D_size*sizeof(int), cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
//convert_1d_to_2d(blured_1D_size, blured_1D);
// SCALE BLURED ARRAY
int *scaled_blured_1D = (int*)malloc(sizeof(int)*blured_1D_size);
for (int i = 0; i < blured_1D_size; i++)
{
scaled_blured_1D[i] = blured_1D[i] /summary;
//cout << scaled_blured_1D[i] << endl;
}
convert_1d_to_2d(blured_1D_size, scaled_blured_1D);
//printf("End of program");
return 0;
} | code for sm_80
Function : _Z7BluringiiPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R23, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff177624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0040*/ IMAD R5, R23, c[0x0][0x160], RZ ; /* 0x0000580017057a24 */
/* 0x000fe400078e02ff */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IABS R6, c[0x0][0x160] ; /* 0x0000580000067a13 */
/* 0x000fe20000000000 */
/*0090*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*00a0*/ IABS R8, R0 ; /* 0x0000000000087213 */
/* 0x000fe20000000000 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ I2F.RP R4, R6 ; /* 0x0000000600047306 */
/* 0x000e300000209400 */
/*00d0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*00e0*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fc40007ffe0ff */
/*00f0*/ LOP3.LUT R4, RZ, c[0x0][0x160], RZ, 0x33, !PT ; /* 0x00005800ff047a12 */
/* 0x000fc800078e33ff */
/*0100*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0110*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe200078e00ff */
/*0120*/ IADD3 R7, RZ, -R3, RZ ; /* 0x80000003ff077210 */
/* 0x002fca0007ffe0ff */
/*0130*/ IMAD R7, R7, R6, RZ ; /* 0x0000000607077224 */
/* 0x000fc800078e02ff */
/*0140*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fc800078e0002 */
/*0150*/ IMAD.MOV.U32 R7, RZ, RZ, R8 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0008 */
/*0160*/ IMAD.HI.U32 R3, R3, R7, RZ ; /* 0x0000000703037227 */
/* 0x000fca00078e00ff */
/*0170*/ IADD3 R3, -R3, RZ, RZ ; /* 0x000000ff03037210 */
/* 0x000fca0007ffe1ff */
/*0180*/ IMAD R3, R6, R3, R7 ; /* 0x0000000306037224 */
/* 0x000fe200078e0207 */
/*0190*/ IADD3 R7, R23, -0x1, RZ ; /* 0xffffffff17077810 */
/* 0x000fc80007ffe0ff */
/*01a0*/ ISETP.GT.U32.AND P0, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x000fda0003f04070 */
/*01b0*/ @!P0 IMAD.IADD R3, R3, 0x1, -R6 ; /* 0x0000000103038824 */
/* 0x000fe200078e0a06 */
/*01c0*/ ISETP.GE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc80003f06270 */
/*01d0*/ ISETP.GT.U32.AND P1, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x000fda0003f24070 */
/*01e0*/ @!P1 IADD3 R3, R3, -R6, RZ ; /* 0x8000000603039210 */
/* 0x000fe40007ffe0ff */
/*01f0*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x160], PT ; /* 0x00005800ff007a0c */
/* 0x000fc60003f25270 */
/*0200*/ @!P0 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff038224 */
/* 0x000fe200078e0a03 */
/*0210*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fc80003f06270 */
/*0220*/ SEL R2, R4, R3, !P1 ; /* 0x0000000304027207 */
/* 0x000fe40004800000 */
/*0230*/ ISETP.GT.AND P0, PT, R0, -0x1, !P0 ; /* 0xffffffff0000780c */
/* 0x000fe40004704270 */
/*0240*/ IADD3 R3, R5, -c[0x0][0x160], RZ ; /* 0x8000580005037a10 */
/* 0x000fe40007ffe0ff */
/*0250*/ ISETP.GE.AND P1, PT, R2.reuse, R7, PT ; /* 0x000000070200720c */
/* 0x040fe40003f26270 */
/*0260*/ ISETP.EQ.OR P0, PT, R2.reuse, RZ, P0 ; /* 0x000000ff0200720c */
/* 0x040fe40000702670 */
/*0270*/ ISETP.LT.AND P1, PT, R2, R5, P1 ; /* 0x000000050200720c */
/* 0x000fc40000f21270 */
/*0280*/ ISETP.GE.OR P0, PT, R0.reuse, R3, P0 ; /* 0x000000030000720c */
/* 0x040fe20000706670 */
/*0290*/ IMAD.WIDE R2, R0, R9, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fe200078e0209 */
/*02a0*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x000fe40000011400 */
/*02b0*/ PLOP3.LUT P0, PT, P1, P0, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f01570 */
/*02c0*/ @P0 BRA 0x560 ; /* 0x0000029000000947 */
/* 0x000fea0003800000 */
/*02d0*/ IMAD.IADD R24, R0, 0x1, R4 ; /* 0x0000000100187824 */
/* 0x000fe200078e0204 */
/*02e0*/ MOV R4, c[0x0][0x178] ; /* 0x00005e0000047a02 */
/* 0x000fe20000000f00 */
/*02f0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff057624 */
/* 0x000fe400078e00ff */
/*0300*/ IMAD.WIDE R24, R24, R9, c[0x0][0x168] ; /* 0x00005a0018187625 */
/* 0x000fc600078e0209 */
/*0310*/ LDG.E R13, [R4.64] ; /* 0x00000004040d7981 */
/* 0x000ea2000c1e1900 */
/*0320*/ IADD3 R8, R0, c[0x0][0x160], RZ ; /* 0x0000580000087a10 */
/* 0x000fc60007ffe0ff */
/*0330*/ LDG.E R12, [R24.64] ; /* 0x00000004180c7981 */
/* 0x0000a2000c1e1900 */
/*0340*/ IMAD.WIDE R6, R23, 0x4, R24 ; /* 0x0000000417067825 */
/* 0x000fc600078e0218 */
/*0350*/ LDG.E R0, [R4.64+0x4] ; /* 0x0000040404007981 */
/* 0x000ee8000c1e1900 */
/*0360*/ LDG.E R15, [R24.64+0x4] ; /* 0x00000404180f7981 */
/* 0x0000e2000c1e1900 */
/*0370*/ IADD3 R10, P0, R24, 0x4, RZ ; /* 0x00000004180a7810 */
/* 0x000fc60007f1e0ff */
/*0380*/ LDG.E R14, [R4.64+0x8] ; /* 0x00000804040e7981 */
/* 0x000f28000c1e1900 */
/*0390*/ LDG.E R17, [R24.64+0x8] ; /* 0x0000080418117981 */
/* 0x000122000c1e1900 */
/*03a0*/ IADD3.X R11, RZ, R25, RZ, P0, !PT ; /* 0x00000019ff0b7210 */
/* 0x000fe400007fe4ff */
/*03b0*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fe20007ffe0ff */
/*03c0*/ LDG.E R18, [R4.64+0xc] ; /* 0x00000c0404127981 */
/* 0x000f68000c1e1900 */
/*03d0*/ LDG.E R21, [R6.64] ; /* 0x0000000406157981 */
/* 0x000f62000c1e1900 */
/*03e0*/ IMAD.WIDE R10, R23, 0x4, R10 ; /* 0x00000004170a7825 */
/* 0x000fc600078e020a */
/*03f0*/ LDG.E R16, [R4.64+0x10] ; /* 0x0000100404107981 */
/* 0x000f62000c1e1900 */
/*0400*/ IMAD.WIDE R8, R8, R9, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fc600078e0209 */
/*0410*/ LDG.E R19, [R6.64+0x4] ; /* 0x0000040406137981 */
/* 0x000f62000c1e1900 */
/*0420*/ IMAD.WIDE R10, R23, 0x4, R10 ; /* 0x00000004170a7825 */
/* 0x000fc600078e020a */
/*0430*/ LDG.E R27, [R6.64+0x8] ; /* 0x00000804061b7981 */
/* 0x000f68000c1e1900 */
/*0440*/ LDG.E R20, [R4.64+0x14] ; /* 0x0000140404147981 */
/* 0x000f68000c1e1900 */
/*0450*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000f68000c1e1900 */
/*0460*/ LDG.E R25, [R4.64+0x18] ; /* 0x0000180404197981 */
/* 0x001f68000c1e1900 */
/*0470*/ LDG.E R22, [R4.64+0x1c] ; /* 0x00001c0404167981 */
/* 0x000f68000c1e1900 */
/*0480*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x000f68000c1e1900 */
/*0490*/ LDG.E R24, [R4.64+0x20] ; /* 0x0000200404187981 */
/* 0x000f68000c1e1900 */
/*04a0*/ LDG.E R29, [R10.64+0x4] ; /* 0x000004040a1d7981 */
/* 0x000f62000c1e1900 */
/*04b0*/ IMAD R12, R13, R12, RZ ; /* 0x0000000c0d0c7224 */
/* 0x004fc800078e02ff */
/*04c0*/ IMAD R0, R0, R15, R12 ; /* 0x0000000f00007224 */
/* 0x008fc800078e020c */
/*04d0*/ IMAD R0, R14, R17, R0 ; /* 0x000000110e007224 */
/* 0x010fc800078e0200 */
/*04e0*/ IMAD R0, R18, R21, R0 ; /* 0x0000001512007224 */
/* 0x020fc800078e0200 */
/*04f0*/ IMAD R0, R16, R19, R0 ; /* 0x0000001310007224 */
/* 0x000fc800078e0200 */
/*0500*/ IMAD R0, R20, R27, R0 ; /* 0x0000001b14007224 */
/* 0x000fc800078e0200 */
/*0510*/ IMAD R0, R25, R8, R0 ; /* 0x0000000819007224 */
/* 0x000fc800078e0200 */
/*0520*/ IMAD R0, R22, R23, R0 ; /* 0x0000001716007224 */
/* 0x000fc800078e0200 */
/*0530*/ IMAD R29, R24, R29, R0 ; /* 0x0000001d181d7224 */
/* 0x000fca00078e0200 */
/*0540*/ STG.E [R2.64], R29 ; /* 0x0000001d02007986 */
/* 0x000fe2000c101904 */
/*0550*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0560*/ LEA R4, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000047a11 */
/* 0x000fc800078010ff */
/*0570*/ LEA.HI.X R5, R0, c[0x0][0x16c], R5, 0x2, P0 ; /* 0x00005b0000057a11 */
/* 0x000fcc00000f1405 */
/*0580*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0590*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101904 */
/*05a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05b0*/ BRA 0x5b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z5Hellov
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e220000002100 */
/*0020*/ MOV R2, 0x8 ; /* 0x0000000800027802 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x0] ; /* 0x01000000ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ IADD3 R1, R1, -0x18, RZ ; /* 0xffffffe801017810 */
/* 0x000fe20007ffe0ff */
/*0050*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x4] ; /* 0x01000100ff057624 */
/* 0x000fe400078e00ff */
/*0070*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000e620000000a00 */
/*0080*/ S2R R11, SR_TID.Z ; /* 0x00000000000b7919 */
/* 0x000ea20000002300 */
/*0090*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fc60007f1e0ff */
/*00a0*/ S2R R10, SR_TID.Y ; /* 0x00000000000a7919 */
/* 0x000ea40000002200 */
/*00b0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe400000e06ff */
/*00c0*/ IMAD R0, R8, c[0x0][0x0], R9 ; /* 0x0000000008007a24 */
/* 0x001fe200078e0209 */
/*00d0*/ STL.64 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0001e80000100a00 */
/*00e0*/ STL [R1+0x10], R0 ; /* 0x0000100001007387 */
/* 0x0001e80000100800 */
/*00f0*/ STL.64 [R1+0x8], R10 ; /* 0x0000080a01007387 */
/* 0x0041e40000100a00 */
/*0100*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x003fe40000000000 */
/*0110*/ MOV R11, 0x180 ; /* 0x00000180000b7802 */
/* 0x000fe40000000f00 */
/*0120*/ MOV R20, 0x100 ; /* 0x0000010000147802 */
/* 0x000fc40000000f00 */
/*0130*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0150*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0160*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0170*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x000fea0003c00000 */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <fstream>
#include <stdio.h>
#include <stdlib.h>
#include <vector>
#include <math.h>
using namespace std;
// CUDA KERNEL FUNCTIONS
__global__ void Hello()
{
//int globalidx = threadIdx.z * blockDim.x * blockDim.y + threadIdx.y * blockDim.x + threadIdx.x;
int globalidx = blockIdx.x * blockDim.x + threadIdx.x;
// printf("blockIdx.x %d\n",blockIdx.x);
printf("Hello from blockx = %d\t tx = %d\t ty=%d\t tz=%d\t gi=%d\n",blockIdx.x, threadIdx.x, threadIdx.y, threadIdx.z, globalidx);
}
__global__ void Bluring(int array_2D_size, int summary, int *array_1D_cuda, int *blured_1D_cuda, int *cu_kernel_1d)
{
int globalidx = blockIdx.x * blockDim.x + threadIdx.x;
// printf("Hello from blockx = %d\t tx = %d\t ty=%d\t tz=%d\t gi=%d\n",blockIdx.x, threadIdx.x, threadIdx.y, threadIdx.z, globalidx);
int N = array_2D_size;
if(globalidx<N*N)
{
if ((globalidx >= 0 && globalidx <= N-1) | (globalidx % N == 0) | (globalidx >= N*N-N) | (globalidx % N >= N -1 && globalidx % N <= N*N -1))
{
blured_1D_cuda[globalidx]=array_1D_cuda[globalidx];
/*
if (globalidx == 0)
{
printf("blured_1D_cuda[%d] = %d\n",globalidx,blured_1D_cuda[globalidx]);
}
*/
} else
{
int top, bottom, left, right;
top = -N + globalidx; // [i-1][j]
bottom = N + globalidx; // [i+1][j]
left = -1 + globalidx; // [i][j-1]
right = 1 + globalidx; // [i][j+1]
/*
if (globalidx == 6)
{
printf("top = %d\t bottom = %d\t left = %d\t right = %d\n", top,bottom,left,right);
}
*/
int cross1, cross2,cross3,cross4;
cross1 = globalidx - N - 1; // [i-1][j-1]
cross2 = globalidx - N + 1; // [i-1][j+1]
cross3 = globalidx + N - 1; // [i+1][j-1]
cross4 = globalidx + N + 1; // [i+1][j+1]
/*
if (globalidx == 6)
{
printf("cross1 = %d\t cross2 = %d\t cross3 = %d\t cross4 = %d\n", cross1, cross2,cross3,cross4);
}
*/
int T1,T2,T3,T4,T5,T6,T7,T8,T9;
int temp1,temp2,temp3;
T1 = array_1D_cuda[cross1] * cu_kernel_1d[0*3+0];
T2 = array_1D_cuda[top] * cu_kernel_1d[0*3+1];
T3 = array_1D_cuda[cross2] * cu_kernel_1d[0*3+2];
temp1 = T1 + T2 + T3;
/*
if (globalidx == 6)
{
printf("T1 = %d\t T2 = %d\t T3 = %d\t temp1 = %d\n", T1, T2,T3,temp1);
}
*/
T4 = array_1D_cuda[left] * cu_kernel_1d[1*3+0];
T5 = array_1D_cuda[globalidx] * cu_kernel_1d[1*3+1];
T6 = array_1D_cuda[right] * cu_kernel_1d[1*3+2];
temp2 = T4 + T5 + T6;
/*
if (globalidx == 6)
{
printf("T4 = %d\t T5 = %d\t T6 = %d\t temp1 = %d\n", T4, T5,T6,temp2);
}
*/
T7 = array_1D_cuda[cross3] * cu_kernel_1d[2*3+0];
T8 = array_1D_cuda[bottom] * cu_kernel_1d[2*3+1];
T9 = array_1D_cuda[cross4] * cu_kernel_1d[2*3+2];
temp3 = T7 + T8 + T9;
/*
if (globalidx == 6)
{
printf("T7 = %d\t T8 = %d\t T9 = %d\t temp3 = %d\n", T7, T8,T9,temp3);
}
*/
blured_1D_cuda[globalidx] = temp1+temp2+temp3;
}
}
}
// CPU FUNCTIONS
int ** malloc_matrix(int N)
{
int ** matrix = (int **)malloc(N * sizeof(int *));
for (int i = 0; i < N; ++i)
{
matrix[i] = (int *)malloc(N * sizeof(int));
}
return matrix;
}
float ** malloc_matrix_float(int N)
{
float ** matrix = (float **)malloc(N * sizeof(float *));
for (int i = 0; i < N; ++i)
{
matrix[i] = (float *)malloc(N * sizeof(float));
}
return matrix;
}
void print_matrix(int * matrix, int N)
{
for (int j = 0; j < N; j++)
{
cout << matrix[j] << " ";
}
cout << endl;
}
void print_matrix(int ** matrix, int N)
{
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
{
cout << matrix[i][j] << " ";
}
cout << endl;
}
cout << endl;
}
void print_matrix(float ** matrix, int N)
{
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
{
cout << matrix[i][j] << " ";
}
cout << endl;
}
cout << endl;
}
void print_matrix(float * matrix, int N)
{
for (int j = 0; j < N; j++)
{
cout << matrix[j] << " ";
}
cout << endl;
}
void convert_1d_to_2d (int array_size, int * array_1D)
{
int ** array_2D;
int array_2D_size = sqrt(array_size);
array_2D = malloc_matrix(array_2D_size);
for (int i = 0; i < array_2D_size; i++)
{
for (int j = 0; j < array_2D_size; j++)
{
array_2D[i][j] = array_1D[i*array_2D_size + j];
}
}
print_matrix(array_2D,array_2D_size);
}
void convert_1d_to_2d_float (int array_size, float * array_1D)
{
float ** array_2D;
int array_2D_size = sqrt(array_size);
array_2D = malloc_matrix_float(array_2D_size);
for (int i = 0; i < array_2D_size; i++)
{
for (int j = 0; j < array_2D_size; j++)
{
array_2D[i][j] = array_1D[i*array_2D_size + j];
}
}
print_matrix(array_2D,array_2D_size);
}
// MAIN FUNCTION
int main(int argc, char *argv[]){
// IMAGE TO ARRAY
ifstream file("image_array.txt");
vector<int> image;
if(file.is_open())
{
while (!file.eof())
{
int temp;
file >> temp;
image.push_back(temp);
}
}
file.close();
image.pop_back();
// ARRAY CREATION
int array_1D_size = image.size();
int *array_1D = (int*)malloc(sizeof(int)*array_1D_size);
for (int i = 0; i < array_1D_size; i++)
{
array_1D[i] = image[i];
}
//convert_1d_to_2d(array_1D_size, array_1D);
// CREATION OF CONVOLUTION
int **kernel;
kernel = malloc_matrix(3);
for (int i = 0; i < 3; i++)
{
for (int j = 0; j < 3; j++)
{
kernel[i][j] = 1;
}
}
//print_matrix(kernel,3);
// 2D KERNEL TO 1D KERNEL
int *kernel_1d = (int*)malloc(sizeof(int)*3*3);
for (int i = 0; i < 3; i++)
{
for (int j = 0; j < 3; j++)
{
kernel_1d[i*3 + j] = kernel[i][j];
}
}
//print_matrix(kernel_1d,3*3);
// SUM of 1D KERNEL
int summary = 0;
for (int j = 0; j < 3*3; j++)
{
summary += kernel_1d[j];
}
//printf("summary = %d\n", summary);
//printf("This is done by CPU before CUDA threads\n");
// ---------- CUDA ZONE -------------
//printf("Start to allocate summary in CUDA\n");
// CONV KERNEL kernel_1d TO DEVICE
int *cu_kernel_1d;
int kernel_1d_size = 9;
cudaMalloc(&cu_kernel_1d, sizeof(int)*kernel_1d_size);
cudaMemcpy(cu_kernel_1d, kernel_1d, kernel_1d_size * sizeof(int), cudaMemcpyHostToDevice);
// ARRAY TO DEVICE
int *array_1D_cuda;
cudaMalloc(&array_1D_cuda, sizeof(int)*array_1D_size);
cudaMemcpy(array_1D_cuda, array_1D, array_1D_size * sizeof(int), cudaMemcpyHostToDevice);
// BLURED ARRAY ON HOST
int blured_1D_size = array_1D_size;
int *blured_1D = (int*)malloc(sizeof(int)*blured_1D_size);
// BLURED ARRAY ON DEVICE
int *blured_1D_cuda;
cudaMalloc(&blured_1D_cuda, sizeof(int)*blured_1D_size);
cudaMemcpy(blured_1D_cuda, blured_1D, blured_1D_size * sizeof(int), cudaMemcpyHostToDevice);
cudaDeviceSynchronize();
// BLURING PROCESS
int blocksDim = 10;
int threadsDim = array_1D_size /blocksDim;
//printf("array_1D_size = %d\n",array_1D_size );
int array_2D_size = sqrt(array_1D_size);
Bluring<<<blocksDim,threadsDim>>>(array_2D_size, summary, array_1D_cuda, blured_1D_cuda,cu_kernel_1d);
cudaMemcpy(blured_1D, blured_1D_cuda, blured_1D_size*sizeof(int), cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
//convert_1d_to_2d(blured_1D_size, blured_1D);
// SCALE BLURED ARRAY
int *scaled_blured_1D = (int*)malloc(sizeof(int)*blured_1D_size);
for (int i = 0; i < blured_1D_size; i++)
{
scaled_blured_1D[i] = blured_1D[i] /summary;
//cout << scaled_blured_1D[i] << endl;
}
convert_1d_to_2d(blured_1D_size, scaled_blured_1D);
//printf("End of program");
return 0;
} | .file "tmpxft_0019deb7_00000000-6_cuda_blur_2.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4184:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4184:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13malloc_matrixi
.type _Z13malloc_matrixi, @function
_Z13malloc_matrixi:
.LFB4163:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movslq %edi, %r12
leaq 0(,%r12,8), %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r13
testl %ebx, %ebx
jle .L3
salq $2, %r12
movq %rax, %rbx
addq %rax, %rbp
.L5:
movq %r12, %rdi
call malloc@PLT
movq %rax, (%rbx)
addq $8, %rbx
cmpq %rbp, %rbx
jne .L5
.L3:
movq %r13, %rax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4163:
.size _Z13malloc_matrixi, .-_Z13malloc_matrixi
.globl _Z19malloc_matrix_floati
.type _Z19malloc_matrix_floati, @function
_Z19malloc_matrix_floati:
.LFB4164:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movslq %edi, %r12
leaq 0(,%r12,8), %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r13
testl %ebx, %ebx
jle .L8
salq $2, %r12
movq %rax, %rbx
addq %rax, %rbp
.L10:
movq %r12, %rdi
call malloc@PLT
movq %rax, (%rbx)
addq $8, %rbx
cmpq %rbp, %rbx
jne .L10
.L8:
movq %r13, %rax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4164:
.size _Z19malloc_matrix_floati, .-_Z19malloc_matrix_floati
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " "
.text
.globl _Z12print_matrixPii
.type _Z12print_matrixPii, @function
_Z12print_matrixPii:
.LFB4165:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
testl %esi, %esi
jle .L14
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %r13
leaq _ZSt4cout(%rip), %r12
leaq .LC0(%rip), %rbp
.L15:
movl (%rbx), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %rbp, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbx, %r13
jne .L15
.L14:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %rbx
testq %rbx, %rbx
je .L21
cmpb $0, 56(%rbx)
je .L17
movzbl 67(%rbx), %esi
.L18:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L17:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L18
.cfi_endproc
.LFE4165:
.size _Z12print_matrixPii, .-_Z12print_matrixPii
.globl _Z12print_matrixPPii
.type _Z12print_matrixPPii, @function
_Z12print_matrixPPii:
.LFB4166:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
testl %esi, %esi
jle .L23
movq %rdi, %r12
movslq %esi, %rsi
leaq (%rdi,%rsi,8), %r15
leaq 0(,%rsi,4), %r13
leaq _ZSt4cout(%rip), %rbp
leaq .LC0(%rip), %r14
jmp .L24
.L34:
call _ZSt16__throw_bad_castv@PLT
.L27:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
.L28:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $8, %r12
cmpq %r12, %r15
je .L23
.L24:
movl $0, %ebx
.L25:
movq (%r12), %rax
movl (%rax,%rbx), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r14, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L25
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbx
testq %rbx, %rbx
je .L34
cmpb $0, 56(%rbx)
je .L27
movzbl 67(%rbx), %esi
jmp .L28
.L23:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %rbx
testq %rbx, %rbx
je .L35
cmpb $0, 56(%rbx)
je .L30
movzbl 67(%rbx), %eax
.L31:
movsbl %al, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L30:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L31
.cfi_endproc
.LFE4166:
.size _Z12print_matrixPPii, .-_Z12print_matrixPPii
.globl _Z12print_matrixPPfi
.type _Z12print_matrixPPfi, @function
_Z12print_matrixPPfi:
.LFB4167:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
testl %esi, %esi
jle .L37
movq %rdi, %r12
movslq %esi, %rsi
leaq (%rdi,%rsi,8), %r15
leaq 0(,%rsi,4), %r13
leaq _ZSt4cout(%rip), %rbp
leaq .LC0(%rip), %r14
jmp .L38
.L48:
call _ZSt16__throw_bad_castv@PLT
.L41:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
.L42:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $8, %r12
cmpq %r12, %r15
je .L37
.L38:
movl $0, %ebx
.L39:
movq (%r12), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbx), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %r14, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L39
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbx
testq %rbx, %rbx
je .L48
cmpb $0, 56(%rbx)
je .L41
movzbl 67(%rbx), %esi
jmp .L42
.L37:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %rbx
testq %rbx, %rbx
je .L49
cmpb $0, 56(%rbx)
je .L44
movzbl 67(%rbx), %eax
.L45:
movsbl %al, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L44:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L45
.cfi_endproc
.LFE4167:
.size _Z12print_matrixPPfi, .-_Z12print_matrixPPfi
.globl _Z12print_matrixPfi
.type _Z12print_matrixPfi, @function
_Z12print_matrixPfi:
.LFB4168:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
testl %esi, %esi
jle .L51
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %r13
leaq _ZSt4cout(%rip), %r12
leaq .LC0(%rip), %rbp
.L52:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %rbp, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbx, %r13
jne .L52
.L51:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %rbx
testq %rbx, %rbx
je .L58
cmpb $0, 56(%rbx)
je .L54
movzbl 67(%rbx), %esi
.L55:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L58:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L54:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L55
.cfi_endproc
.LFE4168:
.size _Z12print_matrixPfi, .-_Z12print_matrixPfi
.globl _Z16convert_1d_to_2diPi
.type _Z16convert_1d_to_2diPi, @function
_Z16convert_1d_to_2diPi:
.LFB4169:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbp
pxor %xmm0, %xmm0
cvtsi2sdl %edi, %xmm0
pxor %xmm1, %xmm1
ucomisd %xmm0, %xmm1
ja .L68
sqrtsd %xmm0, %xmm0
.L62:
cvttsd2sil %xmm0, %ebx
movl %ebx, %edi
call _Z13malloc_matrixi
testl %ebx, %ebx
jle .L63
movq %rax, %rdi
movslq %ebx, %rdx
leaq 0(,%rdx,4), %r9
movq %rbp, %r8
leaq (%rax,%rdx,8), %r10
.L64:
movl $0, %edx
.L65:
movl (%r8,%rdx), %esi
movq (%rdi), %rcx
movl %esi, (%rcx,%rdx)
addq $4, %rdx
cmpq %r9, %rdx
jne .L65
addq $8, %rdi
addq %r9, %r8
cmpq %r10, %rdi
jne .L64
.L63:
movl %ebx, %esi
movq %rax, %rdi
call _Z12print_matrixPPii
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L68:
.cfi_restore_state
call sqrt@PLT
jmp .L62
.cfi_endproc
.LFE4169:
.size _Z16convert_1d_to_2diPi, .-_Z16convert_1d_to_2diPi
.globl _Z22convert_1d_to_2d_floatiPf
.type _Z22convert_1d_to_2d_floatiPf, @function
_Z22convert_1d_to_2d_floatiPf:
.LFB4170:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbx
pxor %xmm0, %xmm0
cvtsi2sdl %edi, %xmm0
pxor %xmm1, %xmm1
ucomisd %xmm0, %xmm1
ja .L79
sqrtsd %xmm0, %xmm0
.L73:
cvttsd2sil %xmm0, %ebp
movl %ebp, %edi
call _Z19malloc_matrix_floati
testl %ebp, %ebp
jle .L74
movq %rax, %rsi
movslq %ebp, %rdx
leaq 0(,%rdx,4), %r8
movq %rbx, %rdi
leaq (%rax,%rdx,8), %r9
.L75:
movl $0, %edx
.L76:
movss (%rdi,%rdx), %xmm0
movq (%rsi), %rcx
movss %xmm0, (%rcx,%rdx)
addq $4, %rdx
cmpq %r8, %rdx
jne .L76
addq $8, %rsi
addq %r8, %rdi
cmpq %r9, %rsi
jne .L75
.L74:
movl %ebp, %esi
movq %rax, %rdi
call _Z12print_matrixPPfi
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L79:
.cfi_restore_state
call sqrt@PLT
jmp .L73
.cfi_endproc
.LFE4170:
.size _Z22convert_1d_to_2d_floatiPf, .-_Z22convert_1d_to_2d_floatiPf
.globl _Z23__device_stub__Z5Hellovv
.type _Z23__device_stub__Z5Hellovv, @function
_Z23__device_stub__Z5Hellovv:
.LFB4206:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L85
.L81:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L86
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L85:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z5Hellov(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L81
.L86:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4206:
.size _Z23__device_stub__Z5Hellovv, .-_Z23__device_stub__Z5Hellovv
.globl _Z5Hellov
.type _Z5Hellov, @function
_Z5Hellov:
.LFB4207:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z5Hellovv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4207:
.size _Z5Hellov, .-_Z5Hellov
.globl _Z32__device_stub__Z7BluringiiPiS_S_iiPiS_S_
.type _Z32__device_stub__Z7BluringiiPiS_S_iiPiS_S_, @function
_Z32__device_stub__Z7BluringiiPiS_S_iiPiS_S_:
.LFB4208:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L93
.L89:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L94
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L93:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7BluringiiPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L89
.L94:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4208:
.size _Z32__device_stub__Z7BluringiiPiS_S_iiPiS_S_, .-_Z32__device_stub__Z7BluringiiPiS_S_iiPiS_S_
.globl _Z7BluringiiPiS_S_
.type _Z7BluringiiPiS_S_, @function
_Z7BluringiiPiS_S_:
.LFB4209:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z7BluringiiPiS_S_iiPiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4209:
.size _Z7BluringiiPiS_S_, .-_Z7BluringiiPiS_S_
.section .rodata.str1.1
.LC2:
.string "_Z7BluringiiPiS_S_"
.LC3:
.string "_Z5Hellov"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4211:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z7BluringiiPiS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z5Hellov(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4211:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIiSaIiEED2Ev,"axG",@progbits,_ZNSt6vectorIiSaIiEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEED2Ev
.type _ZNSt6vectorIiSaIiEED2Ev, @function
_ZNSt6vectorIiSaIiEED2Ev:
.LFB4549:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L102
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L102:
ret
.cfi_endproc
.LFE4549:
.size _ZNSt6vectorIiSaIiEED2Ev, .-_ZNSt6vectorIiSaIiEED2Ev
.weak _ZNSt6vectorIiSaIiEED1Ev
.set _ZNSt6vectorIiSaIiEED1Ev,_ZNSt6vectorIiSaIiEED2Ev
.section .rodata._ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_.str1.1,"aMS",@progbits,1
.LC4:
.string "vector::_M_realloc_insert"
.section .text._ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_,"axG",@progbits,_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_
.type _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_, @function
_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_:
.LFB4740:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, (%rsp)
movq %rdx, 8(%rsp)
movq 8(%rdi), %rbp
movq (%rdi), %r13
movq %rbp, %rax
subq %r13, %rax
sarq $2, %rax
movabsq $2305843009213693951, %rdx
cmpq %rdx, %rax
je .L122
movq %rdi, %rbx
cmpq %r13, %rbp
movl $1, %edx
cmovne %rax, %rdx
addq %rdx, %rax
jc .L108
movabsq $2305843009213693951, %r14
cmpq %r14, %rax
cmovbe %rax, %r14
movq (%rsp), %r15
subq %r13, %r15
movl $0, %r12d
testq %rax, %rax
je .L109
jmp .L116
.L122:
leaq .LC4(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L123:
movq %r15, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memmove@PLT
leaq 4(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jg .L111
addq %rbp, %r15
movq 16(%rbx), %rsi
subq %r13, %rsi
jmp .L115
.L108:
movq (%rsp), %r15
subq %r13, %r15
movabsq $2305843009213693951, %r14
.L116:
leaq 0(,%r14,4), %rdi
call _Znwm@PLT
movq %rax, %r12
.L109:
movq 8(%rsp), %rax
movl (%rax), %eax
movl %eax, (%r12,%r15)
testq %r15, %r15
jg .L123
leaq 4(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jle .L113
.L111:
movq %rbp, %rdx
movq (%rsp), %rsi
movq %r15, %rdi
call memcpy@PLT
.L113:
addq %rbp, %r15
testq %r13, %r13
je .L114
movq 16(%rbx), %rsi
subq %r13, %rsi
.L115:
movq %r13, %rdi
call _ZdlPvm@PLT
.L114:
movq %r12, (%rbx)
movq %r15, 8(%rbx)
leaq (%r12,%r14,4), %rax
movq %rax, 16(%rbx)
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4740:
.size _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_, .-_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_
.section .rodata.str1.1
.LC5:
.string "image_array.txt"
.text
.globl main
.type main, @function
main:
.LFB4171:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4171
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $632, %rsp
.cfi_def_cfa_offset 688
movq %fs:40, %rax
movq %rax, 616(%rsp)
xorl %eax, %eax
leaq 96(%rsp), %rdi
movl $8, %edx
leaq .LC5(%rip), %rsi
.LEHB0:
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE0:
movq $0, 64(%rsp)
movq $0, 72(%rsp)
movq $0, 80(%rsp)
leaq 216(%rsp), %rdi
call _ZNKSt12__basic_fileIcE7is_openEv@PLT
testb %al, %al
je .L125
testb $2, 384(%rsp)
jne .L125
leaq 52(%rsp), %rbx
jmp .L128
.L156:
movq 72(%rsp), %rsi
cmpq 80(%rsp), %rsi
je .L126
movl 52(%rsp), %eax
movl %eax, (%rsi)
addq $4, %rsi
movq %rsi, 72(%rsp)
.L127:
testb $2, 384(%rsp)
jne .L125
.L128:
leaq 96(%rsp), %rdi
movq %rbx, %rsi
.LEHB1:
call _ZNSirsERi@PLT
jmp .L156
.L126:
leaq 64(%rsp), %rdi
movq %rbx, %rdx
call _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_
jmp .L127
.L125:
leaq 96(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv@PLT
movq 72(%rsp), %rax
leaq -4(%rax), %r12
movq %r12, 72(%rsp)
movq 64(%rsp), %rbx
subq %rbx, %r12
sarq $2, %r12
movl %r12d, 4(%rsp)
movslq %r12d, %r14
salq $2, %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %r13
testl %r12d, %r12d
jle .L129
leal -1(%r12), %ecx
movl $0, %eax
.L130:
movl (%rbx,%rax,4), %edx
movl %edx, 0(%r13,%rax,4)
movq %rax, %rdx
addq $1, %rax
cmpq %rcx, %rdx
jne .L130
.L129:
movl $3, %edi
call _Z13malloc_matrixi
movq %rax, %rbx
leaq 24(%rax), %rcx
.L131:
movq (%rax), %rdx
movl $1, (%rdx)
movq (%rax), %rdx
movl $1, 4(%rdx)
movq (%rax), %rdx
movl $1, 8(%rdx)
addq $8, %rax
cmpq %rcx, %rax
jne .L131
movl $36, %edi
call malloc@PLT
movq %rax, %r15
movq %rax, %rdx
movq %rax, %rsi
movl $0, %edi
jmp .L132
.L157:
addq $8, %rbx
addl $3, %edi
addq $12, %rsi
cmpl $9, %edi
je .L134
.L132:
movl $0, %eax
.L133:
movq (%rbx), %rcx
movl (%rcx,%rax), %ecx
movl %ecx, (%rsi,%rax)
addq $4, %rax
cmpq $12, %rax
jne .L133
jmp .L157
.L134:
leaq 36(%r15), %rax
movl $0, %ebx
.L135:
addl (%rdx), %ebx
movl %ebx, %ebp
addq $4, %rdx
cmpq %rax, %rdx
jne .L135
leaq 16(%rsp), %rdi
movl $36, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $36, %edx
movq %r15, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movq %r14, %rdi
call malloc@PLT
movq %rax, %r13
leaq 32(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r13, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
movslq %r12d, %r15
imulq $1717986919, %r15, %r15
sarq $34, %r15
movl %r12d, %eax
sarl $31, %eax
subl %eax, %r15d
pxor %xmm0, %xmm0
cvtsi2sdl %r12d, %xmm0
pxor %xmm1, %xmm1
ucomisd %xmm0, %xmm1
ja .L153
sqrtsd %xmm0, %xmm0
movsd %xmm0, 8(%rsp)
.L138:
movl %r15d, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $10, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
jmp .L158
.L153:
call sqrt@PLT
movsd %xmm0, 8(%rsp)
jmp .L138
.L158:
testl %eax, %eax
jne .L139
cvttsd2sil 8(%rsp), %edi
movq 16(%rsp), %r8
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movl %ebp, %esi
call _Z32__device_stub__Z7BluringiiPiS_S_iiPiS_S_
.L139:
movl $2, %ecx
movq %r14, %rdx
movq 32(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
movq %r14, %rdi
call malloc@PLT
movq %rax, %rsi
testl %r12d, %r12d
jle .L140
leal -1(%r12), %edi
movl $0, %ecx
.L141:
movl 0(%r13,%rcx,4), %eax
cltd
idivl %ebx
movl %eax, (%rsi,%rcx,4)
movq %rcx, %rax
addq $1, %rcx
cmpq %rax, %rdi
jne .L141
.L140:
movl 4(%rsp), %edi
call _Z16convert_1d_to_2diPi
.LEHE1:
leaq 64(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
leaq 96(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 616(%rsp), %rax
subq %fs:40, %rax
jne .L159
movl $0, %eax
addq $632, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L145:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
leaq 96(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 616(%rsp), %rax
subq %fs:40, %rax
je .L143
call __stack_chk_fail@PLT
.L143:
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.L159:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4171:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4171:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4171-.LLSDACSB4171
.LLSDACSB4171:
.uleb128 .LEHB0-.LFB4171
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4171
.uleb128 .LEHE1-.LEHB1
.uleb128 .L145-.LFB4171
.uleb128 0
.uleb128 .LEHB2-.LFB4171
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.LLSDACSE4171:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <fstream>
#include <stdio.h>
#include <stdlib.h>
#include <vector>
#include <math.h>
using namespace std;
// CUDA KERNEL FUNCTIONS
__global__ void Hello()
{
//int globalidx = threadIdx.z * blockDim.x * blockDim.y + threadIdx.y * blockDim.x + threadIdx.x;
int globalidx = blockIdx.x * blockDim.x + threadIdx.x;
// printf("blockIdx.x %d\n",blockIdx.x);
printf("Hello from blockx = %d\t tx = %d\t ty=%d\t tz=%d\t gi=%d\n",blockIdx.x, threadIdx.x, threadIdx.y, threadIdx.z, globalidx);
}
__global__ void Bluring(int array_2D_size, int summary, int *array_1D_cuda, int *blured_1D_cuda, int *cu_kernel_1d)
{
int globalidx = blockIdx.x * blockDim.x + threadIdx.x;
// printf("Hello from blockx = %d\t tx = %d\t ty=%d\t tz=%d\t gi=%d\n",blockIdx.x, threadIdx.x, threadIdx.y, threadIdx.z, globalidx);
int N = array_2D_size;
if(globalidx<N*N)
{
if ((globalidx >= 0 && globalidx <= N-1) | (globalidx % N == 0) | (globalidx >= N*N-N) | (globalidx % N >= N -1 && globalidx % N <= N*N -1))
{
blured_1D_cuda[globalidx]=array_1D_cuda[globalidx];
/*
if (globalidx == 0)
{
printf("blured_1D_cuda[%d] = %d\n",globalidx,blured_1D_cuda[globalidx]);
}
*/
} else
{
int top, bottom, left, right;
top = -N + globalidx; // [i-1][j]
bottom = N + globalidx; // [i+1][j]
left = -1 + globalidx; // [i][j-1]
right = 1 + globalidx; // [i][j+1]
/*
if (globalidx == 6)
{
printf("top = %d\t bottom = %d\t left = %d\t right = %d\n", top,bottom,left,right);
}
*/
int cross1, cross2,cross3,cross4;
cross1 = globalidx - N - 1; // [i-1][j-1]
cross2 = globalidx - N + 1; // [i-1][j+1]
cross3 = globalidx + N - 1; // [i+1][j-1]
cross4 = globalidx + N + 1; // [i+1][j+1]
/*
if (globalidx == 6)
{
printf("cross1 = %d\t cross2 = %d\t cross3 = %d\t cross4 = %d\n", cross1, cross2,cross3,cross4);
}
*/
int T1,T2,T3,T4,T5,T6,T7,T8,T9;
int temp1,temp2,temp3;
T1 = array_1D_cuda[cross1] * cu_kernel_1d[0*3+0];
T2 = array_1D_cuda[top] * cu_kernel_1d[0*3+1];
T3 = array_1D_cuda[cross2] * cu_kernel_1d[0*3+2];
temp1 = T1 + T2 + T3;
/*
if (globalidx == 6)
{
printf("T1 = %d\t T2 = %d\t T3 = %d\t temp1 = %d\n", T1, T2,T3,temp1);
}
*/
T4 = array_1D_cuda[left] * cu_kernel_1d[1*3+0];
T5 = array_1D_cuda[globalidx] * cu_kernel_1d[1*3+1];
T6 = array_1D_cuda[right] * cu_kernel_1d[1*3+2];
temp2 = T4 + T5 + T6;
/*
if (globalidx == 6)
{
printf("T4 = %d\t T5 = %d\t T6 = %d\t temp1 = %d\n", T4, T5,T6,temp2);
}
*/
T7 = array_1D_cuda[cross3] * cu_kernel_1d[2*3+0];
T8 = array_1D_cuda[bottom] * cu_kernel_1d[2*3+1];
T9 = array_1D_cuda[cross4] * cu_kernel_1d[2*3+2];
temp3 = T7 + T8 + T9;
/*
if (globalidx == 6)
{
printf("T7 = %d\t T8 = %d\t T9 = %d\t temp3 = %d\n", T7, T8,T9,temp3);
}
*/
blured_1D_cuda[globalidx] = temp1+temp2+temp3;
}
}
}
// CPU FUNCTIONS
int ** malloc_matrix(int N)
{
int ** matrix = (int **)malloc(N * sizeof(int *));
for (int i = 0; i < N; ++i)
{
matrix[i] = (int *)malloc(N * sizeof(int));
}
return matrix;
}
float ** malloc_matrix_float(int N)
{
float ** matrix = (float **)malloc(N * sizeof(float *));
for (int i = 0; i < N; ++i)
{
matrix[i] = (float *)malloc(N * sizeof(float));
}
return matrix;
}
void print_matrix(int * matrix, int N)
{
for (int j = 0; j < N; j++)
{
cout << matrix[j] << " ";
}
cout << endl;
}
void print_matrix(int ** matrix, int N)
{
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
{
cout << matrix[i][j] << " ";
}
cout << endl;
}
cout << endl;
}
void print_matrix(float ** matrix, int N)
{
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
{
cout << matrix[i][j] << " ";
}
cout << endl;
}
cout << endl;
}
void print_matrix(float * matrix, int N)
{
for (int j = 0; j < N; j++)
{
cout << matrix[j] << " ";
}
cout << endl;
}
void convert_1d_to_2d (int array_size, int * array_1D)
{
int ** array_2D;
int array_2D_size = sqrt(array_size);
array_2D = malloc_matrix(array_2D_size);
for (int i = 0; i < array_2D_size; i++)
{
for (int j = 0; j < array_2D_size; j++)
{
array_2D[i][j] = array_1D[i*array_2D_size + j];
}
}
print_matrix(array_2D,array_2D_size);
}
void convert_1d_to_2d_float (int array_size, float * array_1D)
{
float ** array_2D;
int array_2D_size = sqrt(array_size);
array_2D = malloc_matrix_float(array_2D_size);
for (int i = 0; i < array_2D_size; i++)
{
for (int j = 0; j < array_2D_size; j++)
{
array_2D[i][j] = array_1D[i*array_2D_size + j];
}
}
print_matrix(array_2D,array_2D_size);
}
// MAIN FUNCTION
int main(int argc, char *argv[]){
// IMAGE TO ARRAY
ifstream file("image_array.txt");
vector<int> image;
if(file.is_open())
{
while (!file.eof())
{
int temp;
file >> temp;
image.push_back(temp);
}
}
file.close();
image.pop_back();
// ARRAY CREATION
int array_1D_size = image.size();
int *array_1D = (int*)malloc(sizeof(int)*array_1D_size);
for (int i = 0; i < array_1D_size; i++)
{
array_1D[i] = image[i];
}
//convert_1d_to_2d(array_1D_size, array_1D);
// CREATION OF CONVOLUTION
int **kernel;
kernel = malloc_matrix(3);
for (int i = 0; i < 3; i++)
{
for (int j = 0; j < 3; j++)
{
kernel[i][j] = 1;
}
}
//print_matrix(kernel,3);
// 2D KERNEL TO 1D KERNEL
int *kernel_1d = (int*)malloc(sizeof(int)*3*3);
for (int i = 0; i < 3; i++)
{
for (int j = 0; j < 3; j++)
{
kernel_1d[i*3 + j] = kernel[i][j];
}
}
//print_matrix(kernel_1d,3*3);
// SUM of 1D KERNEL
int summary = 0;
for (int j = 0; j < 3*3; j++)
{
summary += kernel_1d[j];
}
//printf("summary = %d\n", summary);
//printf("This is done by CPU before CUDA threads\n");
// ---------- CUDA ZONE -------------
//printf("Start to allocate summary in CUDA\n");
// CONV KERNEL kernel_1d TO DEVICE
int *cu_kernel_1d;
int kernel_1d_size = 9;
cudaMalloc(&cu_kernel_1d, sizeof(int)*kernel_1d_size);
cudaMemcpy(cu_kernel_1d, kernel_1d, kernel_1d_size * sizeof(int), cudaMemcpyHostToDevice);
// ARRAY TO DEVICE
int *array_1D_cuda;
cudaMalloc(&array_1D_cuda, sizeof(int)*array_1D_size);
cudaMemcpy(array_1D_cuda, array_1D, array_1D_size * sizeof(int), cudaMemcpyHostToDevice);
// BLURED ARRAY ON HOST
int blured_1D_size = array_1D_size;
int *blured_1D = (int*)malloc(sizeof(int)*blured_1D_size);
// BLURED ARRAY ON DEVICE
int *blured_1D_cuda;
cudaMalloc(&blured_1D_cuda, sizeof(int)*blured_1D_size);
cudaMemcpy(blured_1D_cuda, blured_1D, blured_1D_size * sizeof(int), cudaMemcpyHostToDevice);
cudaDeviceSynchronize();
// BLURING PROCESS
int blocksDim = 10;
int threadsDim = array_1D_size /blocksDim;
//printf("array_1D_size = %d\n",array_1D_size );
int array_2D_size = sqrt(array_1D_size);
Bluring<<<blocksDim,threadsDim>>>(array_2D_size, summary, array_1D_cuda, blured_1D_cuda,cu_kernel_1d);
cudaMemcpy(blured_1D, blured_1D_cuda, blured_1D_size*sizeof(int), cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
//convert_1d_to_2d(blured_1D_size, blured_1D);
// SCALE BLURED ARRAY
int *scaled_blured_1D = (int*)malloc(sizeof(int)*blured_1D_size);
for (int i = 0; i < blured_1D_size; i++)
{
scaled_blured_1D[i] = blured_1D[i] /summary;
//cout << scaled_blured_1D[i] << endl;
}
convert_1d_to_2d(blured_1D_size, scaled_blured_1D);
//printf("End of program");
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <fstream>
#include <stdio.h>
#include <stdlib.h>
#include <vector>
#include <math.h>
using namespace std;
// CUDA KERNEL FUNCTIONS
__global__ void Hello()
{
//int globalidx = threadIdx.z * blockDim.x * blockDim.y + threadIdx.y * blockDim.x + threadIdx.x;
int globalidx = blockIdx.x * blockDim.x + threadIdx.x;
// printf("blockIdx.x %d\n",blockIdx.x);
printf("Hello from blockx = %d\t tx = %d\t ty=%d\t tz=%d\t gi=%d\n",blockIdx.x, threadIdx.x, threadIdx.y, threadIdx.z, globalidx);
}
__global__ void Bluring(int array_2D_size, int summary, int *array_1D_cuda, int *blured_1D_cuda, int *cu_kernel_1d)
{
int globalidx = blockIdx.x * blockDim.x + threadIdx.x;
// printf("Hello from blockx = %d\t tx = %d\t ty=%d\t tz=%d\t gi=%d\n",blockIdx.x, threadIdx.x, threadIdx.y, threadIdx.z, globalidx);
int N = array_2D_size;
if(globalidx<N*N)
{
if ((globalidx >= 0 && globalidx <= N-1) | (globalidx % N == 0) | (globalidx >= N*N-N) | (globalidx % N >= N -1 && globalidx % N <= N*N -1))
{
blured_1D_cuda[globalidx]=array_1D_cuda[globalidx];
/*
if (globalidx == 0)
{
printf("blured_1D_cuda[%d] = %d\n",globalidx,blured_1D_cuda[globalidx]);
}
*/
} else
{
int top, bottom, left, right;
top = -N + globalidx; // [i-1][j]
bottom = N + globalidx; // [i+1][j]
left = -1 + globalidx; // [i][j-1]
right = 1 + globalidx; // [i][j+1]
/*
if (globalidx == 6)
{
printf("top = %d\t bottom = %d\t left = %d\t right = %d\n", top,bottom,left,right);
}
*/
int cross1, cross2,cross3,cross4;
cross1 = globalidx - N - 1; // [i-1][j-1]
cross2 = globalidx - N + 1; // [i-1][j+1]
cross3 = globalidx + N - 1; // [i+1][j-1]
cross4 = globalidx + N + 1; // [i+1][j+1]
/*
if (globalidx == 6)
{
printf("cross1 = %d\t cross2 = %d\t cross3 = %d\t cross4 = %d\n", cross1, cross2,cross3,cross4);
}
*/
int T1,T2,T3,T4,T5,T6,T7,T8,T9;
int temp1,temp2,temp3;
T1 = array_1D_cuda[cross1] * cu_kernel_1d[0*3+0];
T2 = array_1D_cuda[top] * cu_kernel_1d[0*3+1];
T3 = array_1D_cuda[cross2] * cu_kernel_1d[0*3+2];
temp1 = T1 + T2 + T3;
/*
if (globalidx == 6)
{
printf("T1 = %d\t T2 = %d\t T3 = %d\t temp1 = %d\n", T1, T2,T3,temp1);
}
*/
T4 = array_1D_cuda[left] * cu_kernel_1d[1*3+0];
T5 = array_1D_cuda[globalidx] * cu_kernel_1d[1*3+1];
T6 = array_1D_cuda[right] * cu_kernel_1d[1*3+2];
temp2 = T4 + T5 + T6;
/*
if (globalidx == 6)
{
printf("T4 = %d\t T5 = %d\t T6 = %d\t temp1 = %d\n", T4, T5,T6,temp2);
}
*/
T7 = array_1D_cuda[cross3] * cu_kernel_1d[2*3+0];
T8 = array_1D_cuda[bottom] * cu_kernel_1d[2*3+1];
T9 = array_1D_cuda[cross4] * cu_kernel_1d[2*3+2];
temp3 = T7 + T8 + T9;
/*
if (globalidx == 6)
{
printf("T7 = %d\t T8 = %d\t T9 = %d\t temp3 = %d\n", T7, T8,T9,temp3);
}
*/
blured_1D_cuda[globalidx] = temp1+temp2+temp3;
}
}
}
// CPU FUNCTIONS
int ** malloc_matrix(int N)
{
int ** matrix = (int **)malloc(N * sizeof(int *));
for (int i = 0; i < N; ++i)
{
matrix[i] = (int *)malloc(N * sizeof(int));
}
return matrix;
}
float ** malloc_matrix_float(int N)
{
float ** matrix = (float **)malloc(N * sizeof(float *));
for (int i = 0; i < N; ++i)
{
matrix[i] = (float *)malloc(N * sizeof(float));
}
return matrix;
}
void print_matrix(int * matrix, int N)
{
for (int j = 0; j < N; j++)
{
cout << matrix[j] << " ";
}
cout << endl;
}
void print_matrix(int ** matrix, int N)
{
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
{
cout << matrix[i][j] << " ";
}
cout << endl;
}
cout << endl;
}
void print_matrix(float ** matrix, int N)
{
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
{
cout << matrix[i][j] << " ";
}
cout << endl;
}
cout << endl;
}
void print_matrix(float * matrix, int N)
{
for (int j = 0; j < N; j++)
{
cout << matrix[j] << " ";
}
cout << endl;
}
void convert_1d_to_2d (int array_size, int * array_1D)
{
int ** array_2D;
int array_2D_size = sqrt(array_size);
array_2D = malloc_matrix(array_2D_size);
for (int i = 0; i < array_2D_size; i++)
{
for (int j = 0; j < array_2D_size; j++)
{
array_2D[i][j] = array_1D[i*array_2D_size + j];
}
}
print_matrix(array_2D,array_2D_size);
}
void convert_1d_to_2d_float (int array_size, float * array_1D)
{
float ** array_2D;
int array_2D_size = sqrt(array_size);
array_2D = malloc_matrix_float(array_2D_size);
for (int i = 0; i < array_2D_size; i++)
{
for (int j = 0; j < array_2D_size; j++)
{
array_2D[i][j] = array_1D[i*array_2D_size + j];
}
}
print_matrix(array_2D,array_2D_size);
}
// MAIN FUNCTION
int main(int argc, char *argv[]){
// IMAGE TO ARRAY
ifstream file("image_array.txt");
vector<int> image;
if(file.is_open())
{
while (!file.eof())
{
int temp;
file >> temp;
image.push_back(temp);
}
}
file.close();
image.pop_back();
// ARRAY CREATION
int array_1D_size = image.size();
int *array_1D = (int*)malloc(sizeof(int)*array_1D_size);
for (int i = 0; i < array_1D_size; i++)
{
array_1D[i] = image[i];
}
//convert_1d_to_2d(array_1D_size, array_1D);
// CREATION OF CONVOLUTION
int **kernel;
kernel = malloc_matrix(3);
for (int i = 0; i < 3; i++)
{
for (int j = 0; j < 3; j++)
{
kernel[i][j] = 1;
}
}
//print_matrix(kernel,3);
// 2D KERNEL TO 1D KERNEL
int *kernel_1d = (int*)malloc(sizeof(int)*3*3);
for (int i = 0; i < 3; i++)
{
for (int j = 0; j < 3; j++)
{
kernel_1d[i*3 + j] = kernel[i][j];
}
}
//print_matrix(kernel_1d,3*3);
// SUM of 1D KERNEL
int summary = 0;
for (int j = 0; j < 3*3; j++)
{
summary += kernel_1d[j];
}
//printf("summary = %d\n", summary);
//printf("This is done by CPU before CUDA threads\n");
// ---------- CUDA ZONE -------------
//printf("Start to allocate summary in CUDA\n");
// CONV KERNEL kernel_1d TO DEVICE
int *cu_kernel_1d;
int kernel_1d_size = 9;
hipMalloc(&cu_kernel_1d, sizeof(int)*kernel_1d_size);
hipMemcpy(cu_kernel_1d, kernel_1d, kernel_1d_size * sizeof(int), hipMemcpyHostToDevice);
// ARRAY TO DEVICE
int *array_1D_cuda;
hipMalloc(&array_1D_cuda, sizeof(int)*array_1D_size);
hipMemcpy(array_1D_cuda, array_1D, array_1D_size * sizeof(int), hipMemcpyHostToDevice);
// BLURED ARRAY ON HOST
int blured_1D_size = array_1D_size;
int *blured_1D = (int*)malloc(sizeof(int)*blured_1D_size);
// BLURED ARRAY ON DEVICE
int *blured_1D_cuda;
hipMalloc(&blured_1D_cuda, sizeof(int)*blured_1D_size);
hipMemcpy(blured_1D_cuda, blured_1D, blured_1D_size * sizeof(int), hipMemcpyHostToDevice);
hipDeviceSynchronize();
// BLURING PROCESS
int blocksDim = 10;
int threadsDim = array_1D_size /blocksDim;
//printf("array_1D_size = %d\n",array_1D_size );
int array_2D_size = sqrt(array_1D_size);
Bluring<<<blocksDim,threadsDim>>>(array_2D_size, summary, array_1D_cuda, blured_1D_cuda,cu_kernel_1d);
hipMemcpy(blured_1D, blured_1D_cuda, blured_1D_size*sizeof(int), hipMemcpyDeviceToHost);
hipDeviceSynchronize();
//convert_1d_to_2d(blured_1D_size, blured_1D);
// SCALE BLURED ARRAY
int *scaled_blured_1D = (int*)malloc(sizeof(int)*blured_1D_size);
for (int i = 0; i < blured_1D_size; i++)
{
scaled_blured_1D[i] = blured_1D[i] /summary;
//cout << scaled_blured_1D[i] << endl;
}
convert_1d_to_2d(blured_1D_size, scaled_blured_1D);
//printf("End of program");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <fstream>
#include <stdio.h>
#include <stdlib.h>
#include <vector>
#include <math.h>
using namespace std;
// CUDA KERNEL FUNCTIONS
__global__ void Hello()
{
//int globalidx = threadIdx.z * blockDim.x * blockDim.y + threadIdx.y * blockDim.x + threadIdx.x;
int globalidx = blockIdx.x * blockDim.x + threadIdx.x;
// printf("blockIdx.x %d\n",blockIdx.x);
printf("Hello from blockx = %d\t tx = %d\t ty=%d\t tz=%d\t gi=%d\n",blockIdx.x, threadIdx.x, threadIdx.y, threadIdx.z, globalidx);
}
__global__ void Bluring(int array_2D_size, int summary, int *array_1D_cuda, int *blured_1D_cuda, int *cu_kernel_1d)
{
int globalidx = blockIdx.x * blockDim.x + threadIdx.x;
// printf("Hello from blockx = %d\t tx = %d\t ty=%d\t tz=%d\t gi=%d\n",blockIdx.x, threadIdx.x, threadIdx.y, threadIdx.z, globalidx);
int N = array_2D_size;
if(globalidx<N*N)
{
if ((globalidx >= 0 && globalidx <= N-1) | (globalidx % N == 0) | (globalidx >= N*N-N) | (globalidx % N >= N -1 && globalidx % N <= N*N -1))
{
blured_1D_cuda[globalidx]=array_1D_cuda[globalidx];
/*
if (globalidx == 0)
{
printf("blured_1D_cuda[%d] = %d\n",globalidx,blured_1D_cuda[globalidx]);
}
*/
} else
{
int top, bottom, left, right;
top = -N + globalidx; // [i-1][j]
bottom = N + globalidx; // [i+1][j]
left = -1 + globalidx; // [i][j-1]
right = 1 + globalidx; // [i][j+1]
/*
if (globalidx == 6)
{
printf("top = %d\t bottom = %d\t left = %d\t right = %d\n", top,bottom,left,right);
}
*/
int cross1, cross2,cross3,cross4;
cross1 = globalidx - N - 1; // [i-1][j-1]
cross2 = globalidx - N + 1; // [i-1][j+1]
cross3 = globalidx + N - 1; // [i+1][j-1]
cross4 = globalidx + N + 1; // [i+1][j+1]
/*
if (globalidx == 6)
{
printf("cross1 = %d\t cross2 = %d\t cross3 = %d\t cross4 = %d\n", cross1, cross2,cross3,cross4);
}
*/
int T1,T2,T3,T4,T5,T6,T7,T8,T9;
int temp1,temp2,temp3;
T1 = array_1D_cuda[cross1] * cu_kernel_1d[0*3+0];
T2 = array_1D_cuda[top] * cu_kernel_1d[0*3+1];
T3 = array_1D_cuda[cross2] * cu_kernel_1d[0*3+2];
temp1 = T1 + T2 + T3;
/*
if (globalidx == 6)
{
printf("T1 = %d\t T2 = %d\t T3 = %d\t temp1 = %d\n", T1, T2,T3,temp1);
}
*/
T4 = array_1D_cuda[left] * cu_kernel_1d[1*3+0];
T5 = array_1D_cuda[globalidx] * cu_kernel_1d[1*3+1];
T6 = array_1D_cuda[right] * cu_kernel_1d[1*3+2];
temp2 = T4 + T5 + T6;
/*
if (globalidx == 6)
{
printf("T4 = %d\t T5 = %d\t T6 = %d\t temp1 = %d\n", T4, T5,T6,temp2);
}
*/
T7 = array_1D_cuda[cross3] * cu_kernel_1d[2*3+0];
T8 = array_1D_cuda[bottom] * cu_kernel_1d[2*3+1];
T9 = array_1D_cuda[cross4] * cu_kernel_1d[2*3+2];
temp3 = T7 + T8 + T9;
/*
if (globalidx == 6)
{
printf("T7 = %d\t T8 = %d\t T9 = %d\t temp3 = %d\n", T7, T8,T9,temp3);
}
*/
blured_1D_cuda[globalidx] = temp1+temp2+temp3;
}
}
}
// CPU FUNCTIONS
int ** malloc_matrix(int N)
{
int ** matrix = (int **)malloc(N * sizeof(int *));
for (int i = 0; i < N; ++i)
{
matrix[i] = (int *)malloc(N * sizeof(int));
}
return matrix;
}
float ** malloc_matrix_float(int N)
{
float ** matrix = (float **)malloc(N * sizeof(float *));
for (int i = 0; i < N; ++i)
{
matrix[i] = (float *)malloc(N * sizeof(float));
}
return matrix;
}
void print_matrix(int * matrix, int N)
{
for (int j = 0; j < N; j++)
{
cout << matrix[j] << " ";
}
cout << endl;
}
void print_matrix(int ** matrix, int N)
{
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
{
cout << matrix[i][j] << " ";
}
cout << endl;
}
cout << endl;
}
void print_matrix(float ** matrix, int N)
{
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
{
cout << matrix[i][j] << " ";
}
cout << endl;
}
cout << endl;
}
void print_matrix(float * matrix, int N)
{
for (int j = 0; j < N; j++)
{
cout << matrix[j] << " ";
}
cout << endl;
}
void convert_1d_to_2d (int array_size, int * array_1D)
{
int ** array_2D;
int array_2D_size = sqrt(array_size);
array_2D = malloc_matrix(array_2D_size);
for (int i = 0; i < array_2D_size; i++)
{
for (int j = 0; j < array_2D_size; j++)
{
array_2D[i][j] = array_1D[i*array_2D_size + j];
}
}
print_matrix(array_2D,array_2D_size);
}
void convert_1d_to_2d_float (int array_size, float * array_1D)
{
float ** array_2D;
int array_2D_size = sqrt(array_size);
array_2D = malloc_matrix_float(array_2D_size);
for (int i = 0; i < array_2D_size; i++)
{
for (int j = 0; j < array_2D_size; j++)
{
array_2D[i][j] = array_1D[i*array_2D_size + j];
}
}
print_matrix(array_2D,array_2D_size);
}
// MAIN FUNCTION
int main(int argc, char *argv[]){
// IMAGE TO ARRAY
ifstream file("image_array.txt");
vector<int> image;
if(file.is_open())
{
while (!file.eof())
{
int temp;
file >> temp;
image.push_back(temp);
}
}
file.close();
image.pop_back();
// ARRAY CREATION
int array_1D_size = image.size();
int *array_1D = (int*)malloc(sizeof(int)*array_1D_size);
for (int i = 0; i < array_1D_size; i++)
{
array_1D[i] = image[i];
}
//convert_1d_to_2d(array_1D_size, array_1D);
// CREATION OF CONVOLUTION
int **kernel;
kernel = malloc_matrix(3);
for (int i = 0; i < 3; i++)
{
for (int j = 0; j < 3; j++)
{
kernel[i][j] = 1;
}
}
//print_matrix(kernel,3);
// 2D KERNEL TO 1D KERNEL
int *kernel_1d = (int*)malloc(sizeof(int)*3*3);
for (int i = 0; i < 3; i++)
{
for (int j = 0; j < 3; j++)
{
kernel_1d[i*3 + j] = kernel[i][j];
}
}
//print_matrix(kernel_1d,3*3);
// SUM of 1D KERNEL
int summary = 0;
for (int j = 0; j < 3*3; j++)
{
summary += kernel_1d[j];
}
//printf("summary = %d\n", summary);
//printf("This is done by CPU before CUDA threads\n");
// ---------- CUDA ZONE -------------
//printf("Start to allocate summary in CUDA\n");
// CONV KERNEL kernel_1d TO DEVICE
int *cu_kernel_1d;
int kernel_1d_size = 9;
hipMalloc(&cu_kernel_1d, sizeof(int)*kernel_1d_size);
hipMemcpy(cu_kernel_1d, kernel_1d, kernel_1d_size * sizeof(int), hipMemcpyHostToDevice);
// ARRAY TO DEVICE
int *array_1D_cuda;
hipMalloc(&array_1D_cuda, sizeof(int)*array_1D_size);
hipMemcpy(array_1D_cuda, array_1D, array_1D_size * sizeof(int), hipMemcpyHostToDevice);
// BLURED ARRAY ON HOST
int blured_1D_size = array_1D_size;
int *blured_1D = (int*)malloc(sizeof(int)*blured_1D_size);
// BLURED ARRAY ON DEVICE
int *blured_1D_cuda;
hipMalloc(&blured_1D_cuda, sizeof(int)*blured_1D_size);
hipMemcpy(blured_1D_cuda, blured_1D, blured_1D_size * sizeof(int), hipMemcpyHostToDevice);
hipDeviceSynchronize();
// BLURING PROCESS
int blocksDim = 10;
int threadsDim = array_1D_size /blocksDim;
//printf("array_1D_size = %d\n",array_1D_size );
int array_2D_size = sqrt(array_1D_size);
Bluring<<<blocksDim,threadsDim>>>(array_2D_size, summary, array_1D_cuda, blured_1D_cuda,cu_kernel_1d);
hipMemcpy(blured_1D, blured_1D_cuda, blured_1D_size*sizeof(int), hipMemcpyDeviceToHost);
hipDeviceSynchronize();
//convert_1d_to_2d(blured_1D_size, blured_1D);
// SCALE BLURED ARRAY
int *scaled_blured_1D = (int*)malloc(sizeof(int)*blured_1D_size);
for (int i = 0; i < blured_1D_size; i++)
{
scaled_blured_1D[i] = blured_1D[i] /summary;
//cout << scaled_blured_1D[i] << endl;
}
convert_1d_to_2d(blured_1D_size, scaled_blured_1D);
//printf("End of program");
return 0;
} | .text
.file "cuda_blur_2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z20__device_stub__Hellov # -- Begin function _Z20__device_stub__Hellov
.p2align 4, 0x90
.type _Z20__device_stub__Hellov,@function
_Z20__device_stub__Hellov: # @_Z20__device_stub__Hellov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5Hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z20__device_stub__Hellov, .Lfunc_end0-_Z20__device_stub__Hellov
.cfi_endproc
# -- End function
.globl _Z22__device_stub__BluringiiPiS_S_ # -- Begin function _Z22__device_stub__BluringiiPiS_S_
.p2align 4, 0x90
.type _Z22__device_stub__BluringiiPiS_S_,@function
_Z22__device_stub__BluringiiPiS_S_: # @_Z22__device_stub__BluringiiPiS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7BluringiiPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z22__device_stub__BluringiiPiS_S_, .Lfunc_end1-_Z22__device_stub__BluringiiPiS_S_
.cfi_endproc
# -- End function
.globl _Z13malloc_matrixi # -- Begin function _Z13malloc_matrixi
.p2align 4, 0x90
.type _Z13malloc_matrixi,@function
_Z13malloc_matrixi: # @_Z13malloc_matrixi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movslq %edi, %r15
leaq (,%r15,8), %rdi
callq malloc
movq %rax, %rbx
testl %r15d, %r15d
jle .LBB2_3
# %bb.1: # %.lr.ph
leaq (,%r15,4), %r14
movl %r15d, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_2: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
callq malloc
movq %rax, (%rbx,%r12,8)
incq %r12
cmpq %r12, %r15
jne .LBB2_2
.LBB2_3: # %._crit_edge
movq %rbx, %rax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z13malloc_matrixi, .Lfunc_end2-_Z13malloc_matrixi
.cfi_endproc
# -- End function
.globl _Z19malloc_matrix_floati # -- Begin function _Z19malloc_matrix_floati
.p2align 4, 0x90
.type _Z19malloc_matrix_floati,@function
_Z19malloc_matrix_floati: # @_Z19malloc_matrix_floati
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movslq %edi, %r15
leaq (,%r15,8), %rdi
callq malloc
movq %rax, %rbx
testl %r15d, %r15d
jle .LBB3_3
# %bb.1: # %.lr.ph
leaq (,%r15,4), %r14
movl %r15d, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_2: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
callq malloc
movq %rax, (%rbx,%r12,8)
incq %r12
cmpq %r12, %r15
jne .LBB3_2
.LBB3_3: # %._crit_edge
movq %rbx, %rax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z19malloc_matrix_floati, .Lfunc_end3-_Z19malloc_matrix_floati
.cfi_endproc
# -- End function
.globl _Z12print_matrixPii # -- Begin function _Z12print_matrixPii
.p2align 4, 0x90
.type _Z12print_matrixPii,@function
_Z12print_matrixPii: # @_Z12print_matrixPii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
testl %esi, %esi
jle .LBB4_3
# %bb.1: # %.lr.ph.preheader
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r15
cmpq %r15, %r14
jne .LBB4_2
.LBB4_3: # %._crit_edge
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB4_8
# %bb.4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB4_6
# %bb.5:
movzbl 67(%rbx), %eax
jmp .LBB4_7
.LBB4_6:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_7: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp _ZNSo5flushEv # TAILCALL
.LBB4_8:
.cfi_def_cfa_offset 32
callq _ZSt16__throw_bad_castv
.Lfunc_end4:
.size _Z12print_matrixPii, .Lfunc_end4-_Z12print_matrixPii
.cfi_endproc
# -- End function
.globl _Z12print_matrixPPii # -- Begin function _Z12print_matrixPPii
.p2align 4, 0x90
.type _Z12print_matrixPPii,@function
_Z12print_matrixPPii: # @_Z12print_matrixPPii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
testl %esi, %esi
jle .LBB5_7
# %bb.1: # %.preheader.lr.ph
movq %rdi, %rbx
movl %esi, %r15d
xorl %r12d, %r12d
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_12: # in Loop: Header=BB5_2 Depth=1
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB5_13: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit14
# in Loop: Header=BB5_2 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r12
cmpq %r15, %r12
je .LBB5_7
.LBB5_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB5_3 Depth 2
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB5_3: # Parent Loop BB5_2 Depth=1
# => This Inner Loop Header: Depth=2
movq (%rbx,%r12,8), %rax
movl (%rax,%r14,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r14
cmpq %r14, %r15
jne .LBB5_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB5_2 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB5_14
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i11
# in Loop: Header=BB5_2 Depth=1
cmpb $0, 56(%r14)
je .LBB5_12
# %bb.6: # in Loop: Header=BB5_2 Depth=1
movzbl 67(%r14), %eax
jmp .LBB5_13
.LBB5_7: # %._crit_edge17
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB5_14
# %bb.8: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB5_10
# %bb.9:
movzbl 67(%rbx), %eax
jmp .LBB5_11
.LBB5_10:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB5_11: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp _ZNSo5flushEv # TAILCALL
.LBB5_14:
.cfi_def_cfa_offset 48
callq _ZSt16__throw_bad_castv
.Lfunc_end5:
.size _Z12print_matrixPPii, .Lfunc_end5-_Z12print_matrixPPii
.cfi_endproc
# -- End function
.globl _Z12print_matrixPPfi # -- Begin function _Z12print_matrixPPfi
.p2align 4, 0x90
.type _Z12print_matrixPPfi,@function
_Z12print_matrixPPfi: # @_Z12print_matrixPPfi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
testl %esi, %esi
jle .LBB6_7
# %bb.1: # %.preheader.lr.ph
movq %rdi, %rbx
movl %esi, %r15d
xorl %r12d, %r12d
jmp .LBB6_2
.p2align 4, 0x90
.LBB6_12: # in Loop: Header=BB6_2 Depth=1
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB6_13: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit14
# in Loop: Header=BB6_2 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r12
cmpq %r15, %r12
je .LBB6_7
.LBB6_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB6_3 Depth 2
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB6_3: # Parent Loop BB6_2 Depth=1
# => This Inner Loop Header: Depth=2
movq (%rbx,%r12,8), %rax
movss (%rax,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r14
cmpq %r14, %r15
jne .LBB6_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB6_2 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB6_14
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i11
# in Loop: Header=BB6_2 Depth=1
cmpb $0, 56(%r14)
je .LBB6_12
# %bb.6: # in Loop: Header=BB6_2 Depth=1
movzbl 67(%r14), %eax
jmp .LBB6_13
.LBB6_7: # %._crit_edge17
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB6_14
# %bb.8: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB6_10
# %bb.9:
movzbl 67(%rbx), %eax
jmp .LBB6_11
.LBB6_10:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB6_11: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp _ZNSo5flushEv # TAILCALL
.LBB6_14:
.cfi_def_cfa_offset 48
callq _ZSt16__throw_bad_castv
.Lfunc_end6:
.size _Z12print_matrixPPfi, .Lfunc_end6-_Z12print_matrixPPfi
.cfi_endproc
# -- End function
.globl _Z12print_matrixPfi # -- Begin function _Z12print_matrixPfi
.p2align 4, 0x90
.type _Z12print_matrixPfi,@function
_Z12print_matrixPfi: # @_Z12print_matrixPfi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
testl %esi, %esi
jle .LBB7_3
# %bb.1: # %.lr.ph.preheader
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB7_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r15
cmpq %r15, %r14
jne .LBB7_2
.LBB7_3: # %._crit_edge
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB7_8
# %bb.4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB7_6
# %bb.5:
movzbl 67(%rbx), %eax
jmp .LBB7_7
.LBB7_6:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB7_7: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp _ZNSo5flushEv # TAILCALL
.LBB7_8:
.cfi_def_cfa_offset 32
callq _ZSt16__throw_bad_castv
.Lfunc_end7:
.size _Z12print_matrixPfi, .Lfunc_end7-_Z12print_matrixPfi
.cfi_endproc
# -- End function
.globl _Z16convert_1d_to_2diPi # -- Begin function _Z16convert_1d_to_2diPi
.p2align 4, 0x90
.type _Z16convert_1d_to_2diPi,@function
_Z16convert_1d_to_2diPi: # @_Z16convert_1d_to_2diPi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cvtsi2sd %edi, %xmm0
movq %rsi, %rbx
xorpd %xmm1, %xmm1
ucomisd %xmm1, %xmm0
jb .LBB8_2
# %bb.1:
sqrtsd %xmm0, %xmm0
jmp .LBB8_3
.LBB8_2: # %call.sqrt
callq sqrt
.LBB8_3: # %.split
cvttsd2si %xmm0, %ebp
movslq %ebp, %r15
leaq (,%r15,8), %rdi
callq malloc
movq %rax, %r14
testl %r15d, %r15d
jle .LBB8_6
# %bb.4: # %.lr.ph.i
shlq $2, %r15
movl %ebp, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB8_5: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
callq malloc
movq %rax, (%r14,%r13,8)
incq %r13
cmpq %r13, %r12
jne .LBB8_5
.LBB8_6: # %_Z13malloc_matrixi.exit
testl %ebp, %ebp
jle .LBB8_11
# %bb.7: # %.preheader.lr.ph
movl %ebp, %eax
xorl %ecx, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB8_8: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB8_9 Depth 2
movl %ecx, %esi
leaq (%rbx,%rsi,4), %rsi
movq (%r14,%rdx,8), %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB8_9: # Parent Loop BB8_8 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rsi,%r8,4), %r9d
movl %r9d, (%rdi,%r8,4)
incq %r8
cmpq %r8, %rax
jne .LBB8_9
# %bb.10: # %._crit_edge
# in Loop: Header=BB8_8 Depth=1
incq %rdx
addl %ebp, %ecx
cmpq %rax, %rdx
jne .LBB8_8
.LBB8_11: # %._crit_edge20
movq %r14, %rdi
movl %ebp, %esi
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp _Z12print_matrixPPii # TAILCALL
.Lfunc_end8:
.size _Z16convert_1d_to_2diPi, .Lfunc_end8-_Z16convert_1d_to_2diPi
.cfi_endproc
# -- End function
.globl _Z22convert_1d_to_2d_floatiPf # -- Begin function _Z22convert_1d_to_2d_floatiPf
.p2align 4, 0x90
.type _Z22convert_1d_to_2d_floatiPf,@function
_Z22convert_1d_to_2d_floatiPf: # @_Z22convert_1d_to_2d_floatiPf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cvtsi2sd %edi, %xmm0
movq %rsi, %rbx
xorpd %xmm1, %xmm1
ucomisd %xmm1, %xmm0
jb .LBB9_2
# %bb.1:
sqrtsd %xmm0, %xmm0
jmp .LBB9_3
.LBB9_2: # %call.sqrt
callq sqrt
.LBB9_3: # %.split
cvttsd2si %xmm0, %ebp
movslq %ebp, %r15
leaq (,%r15,8), %rdi
callq malloc
movq %rax, %r14
testl %r15d, %r15d
jle .LBB9_6
# %bb.4: # %.lr.ph.i
shlq $2, %r15
movl %ebp, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB9_5: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
callq malloc
movq %rax, (%r14,%r13,8)
incq %r13
cmpq %r13, %r12
jne .LBB9_5
.LBB9_6: # %_Z19malloc_matrix_floati.exit
testl %ebp, %ebp
jle .LBB9_11
# %bb.7: # %.preheader.lr.ph
movl %ebp, %eax
xorl %ecx, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB9_8: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB9_9 Depth 2
movl %ecx, %esi
leaq (%rbx,%rsi,4), %rsi
movq (%r14,%rdx,8), %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB9_9: # Parent Loop BB9_8 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rsi,%r8,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%rdi,%r8,4)
incq %r8
cmpq %r8, %rax
jne .LBB9_9
# %bb.10: # %._crit_edge
# in Loop: Header=BB9_8 Depth=1
incq %rdx
addl %ebp, %ecx
cmpq %rax, %rdx
jne .LBB9_8
.LBB9_11: # %._crit_edge20
movq %r14, %rdi
movl %ebp, %esi
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp _Z12print_matrixPPfi # TAILCALL
.Lfunc_end9:
.size _Z22convert_1d_to_2d_floatiPf, .Lfunc_end9-_Z22convert_1d_to_2d_floatiPf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $696, %rsp # imm = 0x2B8
.cfi_def_cfa_offset 752
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
.cfi_escape 0x2e, 0x00
leaq 176(%rsp), %rdi
movl $.L.str.1, %esi
movl $8, %edx
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
leaq 296(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNKSt12__basic_fileIcE7is_openEv
testb %al, %al
je .LBB10_1
# %bb.2: # %.preheader115
movq 176(%rsp), %rax
movq -24(%rax), %rax
testb $2, 208(%rsp,%rax)
jne .LBB10_1
# %bb.3: # %.lr.ph.preheader
xorl %r15d, %r15d
leaq 128(%rsp), %r13
xorl %ebp, %ebp
xorl %r14d, %r14d
jmp .LBB10_4
.p2align 4, 0x90
.LBB10_6: # in Loop: Header=BB10_4 Depth=1
movl 128(%rsp), %eax
movl %eax, (%rbp)
movq %r15, %rbx
.LBB10_23: # %_ZNSt6vectorIiSaIiEE9push_backERKi.exit
# in Loop: Header=BB10_4 Depth=1
addq $4, %rbp
movq 176(%rsp), %rax
movq -24(%rax), %rax
testb $2, 208(%rsp,%rax)
jne .LBB10_24
.LBB10_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
.Ltmp0:
.cfi_escape 0x2e, 0x00
leaq 176(%rsp), %rdi
movq %r13, %rsi
callq _ZNSirsERi
.Ltmp1:
# %bb.5: # in Loop: Header=BB10_4 Depth=1
cmpq %r14, %rbp
jne .LBB10_6
# %bb.7: # in Loop: Header=BB10_4 Depth=1
subq %r15, %rbp
movabsq $9223372036854775804, %rax # imm = 0x7FFFFFFFFFFFFFFC
cmpq %rax, %rbp
je .LBB10_8
# %bb.10: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i
# in Loop: Header=BB10_4 Depth=1
movq %rbp, %r14
sarq $2, %r14
cmpq $1, %r14
movq %r14, %rax
adcq $0, %rax
leaq (%rax,%r14), %rcx
movabsq $2305843009213693951, %r12 # imm = 0x1FFFFFFFFFFFFFFF
cmpq %r12, %rcx
jae .LBB10_11
# %bb.12: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i
# in Loop: Header=BB10_4 Depth=1
addq %r14, %rax
jae .LBB10_13
.LBB10_14: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i
# in Loop: Header=BB10_4 Depth=1
testq %r12, %r12
je .LBB10_15
.LBB10_16: # in Loop: Header=BB10_4 Depth=1
leaq (,%r12,4), %rdi
.Ltmp2:
.cfi_escape 0x2e, 0x00
callq _Znwm
.Ltmp3:
# %bb.17: # in Loop: Header=BB10_4 Depth=1
movq %rax, %rbx
jmp .LBB10_18
.LBB10_11: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i
# in Loop: Header=BB10_4 Depth=1
movq %r12, %rcx
addq %r14, %rax
jb .LBB10_14
.LBB10_13: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i
# in Loop: Header=BB10_4 Depth=1
movq %rcx, %r12
testq %r12, %r12
jne .LBB10_16
.LBB10_15: # in Loop: Header=BB10_4 Depth=1
xorl %ebx, %ebx
.LBB10_18: # %_ZNSt12_Vector_baseIiSaIiEE11_M_allocateEm.exit.i.i
# in Loop: Header=BB10_4 Depth=1
movl 128(%rsp), %eax
movl %eax, (%rbx,%r14,4)
testq %rbp, %rbp
jle .LBB10_20
# %bb.19: # in Loop: Header=BB10_4 Depth=1
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movq %r15, %rsi
movq %rbp, %rdx
callq memmove@PLT
.LBB10_20: # %_ZNSt6vectorIiSaIiEE11_S_relocateEPiS2_S2_RS0_.exit.i.i
# in Loop: Header=BB10_4 Depth=1
testq %r15, %r15
je .LBB10_22
# %bb.21: # in Loop: Header=BB10_4 Depth=1
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZdlPv
.LBB10_22: # %_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_.exit.i
# in Loop: Header=BB10_4 Depth=1
addq %rbx, %rbp
leaq (%rbx,%r12,4), %r14
movq %rbx, %r15
jmp .LBB10_23
.LBB10_1:
xorl %ebp, %ebp
xorl %ebx, %ebx
.LBB10_24: # %.loopexit
leaq 192(%rsp), %rdi
.Ltmp5:
.cfi_escape 0x2e, 0x00
movq %rbx, (%rsp) # 8-byte Spill
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp6:
# %bb.25: # %.noexc86
testq %rax, %rax
jne .LBB10_27
# %bb.26:
movq 176(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $176, %rdi
movl 208(%rsp,%rax), %esi
orl $4, %esi
.Ltmp7:
.cfi_escape 0x2e, 0x00
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp8:
.LBB10_27: # %_ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv.exit
subq %rbx, %rbp
addq $-4, %rbp
movq %rbp, %r14
shrq $2, %r14
shlq $30, %rbp
sarq $30, %rbp
.cfi_escape 0x2e, 0x00
movq %rbp, %rdi
callq malloc
movq %rax, %r15
movq %r14, %r13
testl %r14d, %r14d
jle .LBB10_30
# %bb.28: # %.lr.ph129.preheader
movl %r13d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB10_29: # %.lr.ph129
# =>This Inner Loop Header: Depth=1
movl (%rbx,%rcx,4), %edx
movl %edx, (%r15,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB10_29
.LBB10_30: # %._crit_edge
.cfi_escape 0x2e, 0x00
movl $24, %edi
callq malloc
movq %rax, %r12
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB10_31: # =>This Inner Loop Header: Depth=1
.cfi_escape 0x2e, 0x00
movl $12, %edi
callq malloc
movq %rax, (%r12,%rbx,8)
incq %rbx
cmpq $3, %rbx
jne .LBB10_31
# %bb.32: # %.preheader114.preheader
xorl %eax, %eax
movq %r13, %rbx
.p2align 4, 0x90
.LBB10_33: # %.preheader114
# =>This Loop Header: Depth=1
# Child Loop BB10_34 Depth 2
movq (%r12,%rax,8), %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB10_34: # Parent Loop BB10_33 Depth=1
# => This Inner Loop Header: Depth=2
movl $1, (%rcx,%rdx,4)
incq %rdx
cmpq $3, %rdx
jne .LBB10_34
# %bb.35: # %_Z13malloc_matrixi.exit
# in Loop: Header=BB10_33 Depth=1
incq %rax
cmpq $3, %rax
jne .LBB10_33
# %bb.36:
.cfi_escape 0x2e, 0x00
movl $36, %edi
callq malloc
movq %rax, %r13
xorl %eax, %eax
movq %r13, %rcx
.p2align 4, 0x90
.LBB10_37: # %.preheader113
# =>This Loop Header: Depth=1
# Child Loop BB10_38 Depth 2
movq (%r12,%rax,8), %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB10_38: # Parent Loop BB10_37 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rdx,%rsi,4), %edi
movl %edi, (%rcx,%rsi,4)
incq %rsi
cmpq $3, %rsi
jne .LBB10_38
# %bb.39: # in Loop: Header=BB10_37 Depth=1
incq %rax
addq $12, %rcx
cmpq $3, %rax
jne .LBB10_37
# %bb.40: # %.preheader.preheader
xorl %eax, %eax
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB10_41: # %.preheader
# =>This Inner Loop Header: Depth=1
addl (%r13,%rax,4), %r12d
incq %rax
cmpq $9, %rax
jne .LBB10_41
# %bb.42:
.Ltmp10:
.cfi_escape 0x2e, 0x00
leaq 48(%rsp), %rdi
movl $36, %esi
callq hipMalloc
.Ltmp11:
# %bb.43: # %_ZL9hipMallocIiE10hipError_tPPT_m.exit
movq 48(%rsp), %rdi
.Ltmp12:
.cfi_escape 0x2e, 0x00
movl $36, %edx
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp13:
# %bb.44:
.Ltmp15:
.cfi_escape 0x2e, 0x00
leaq 40(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
.Ltmp16:
# %bb.45: # %_ZL9hipMallocIiE10hipError_tPPT_m.exit90
movq 40(%rsp), %rdi
.Ltmp17:
.cfi_escape 0x2e, 0x00
movq %r15, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
.Ltmp18:
# %bb.46:
.cfi_escape 0x2e, 0x00
movq %rbp, %rdi
callq malloc
movq %rax, %r15
.Ltmp20:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
.Ltmp21:
# %bb.47: # %_ZL9hipMallocIiE10hipError_tPPT_m.exit92
movq 16(%rsp), %rdi
.Ltmp22:
.cfi_escape 0x2e, 0x00
movq %r15, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
.Ltmp23:
# %bb.48:
.Ltmp24:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.Ltmp25:
# %bb.49:
movslq %ebx, %rax
imulq $1717986919, %rax, %r14 # imm = 0x66666667
movq %r14, %rax
shrq $63, %rax
sarq $34, %r14
cvtsi2sd %ebx, %xmm0
addl %eax, %r14d
xorpd %xmm1, %xmm1
ucomisd %xmm1, %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
jb .LBB10_55
# %bb.50:
sqrtsd %xmm0, %xmm0
jmp .LBB10_56
.LBB10_55: # %call.sqrt
.cfi_escape 0x2e, 0x00
callq sqrt
.LBB10_56: # %.split
movsd %xmm0, 32(%rsp) # 8-byte Spill
movl %r14d, %eax
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rax, %rdx
.Ltmp27:
.cfi_escape 0x2e, 0x00
movabsq $4294967306, %rdi # imm = 0x10000000A
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp28:
# %bb.57:
testl %eax, %eax
jne .LBB10_60
# %bb.58:
cvttsd2si 32(%rsp), %eax # 8-byte Folded Reload
movq 40(%rsp), %rcx
movq 16(%rsp), %rdx
movq 48(%rsp), %rsi
movl %eax, 28(%rsp)
movl %r12d, 24(%rsp)
movq %rcx, 120(%rsp)
movq %rdx, 112(%rsp)
movq %rsi, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 120(%rsp), %rax
movq %rax, 144(%rsp)
leaq 112(%rsp), %rax
movq %rax, 152(%rsp)
leaq 104(%rsp), %rax
movq %rax, 160(%rsp)
.Ltmp29:
.cfi_escape 0x2e, 0x00
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp30:
# %bb.59: # %.noexc93
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
.Ltmp31:
.cfi_escape 0x2e, 0x10
leaq 128(%rsp), %r9
movl $_Z7BluringiiPiS_S_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp32:
.LBB10_60:
movq 16(%rsp), %rsi
.Ltmp33:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
.Ltmp34:
# %bb.61:
.Ltmp35:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.Ltmp36:
# %bb.62:
.cfi_escape 0x2e, 0x00
movq %rbp, %rdi
callq malloc
movq %rax, %r14
testl %ebx, %ebx
jle .LBB10_65
# %bb.63: # %.lr.ph138.preheader
movl %ebx, %ecx
xorl %esi, %esi
.p2align 4, 0x90
.LBB10_64: # %.lr.ph138
# =>This Inner Loop Header: Depth=1
movl (%r15,%rsi,4), %eax
cltd
idivl %r12d
movl %eax, (%r14,%rsi,4)
incq %rsi
cmpq %rsi, %rcx
jne .LBB10_64
.LBB10_65: # %._crit_edge139
xorpd %xmm1, %xmm1
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
ucomisd %xmm1, %xmm0
jb .LBB10_71
# %bb.66:
sqrtsd %xmm0, %xmm0
jmp .LBB10_72
.LBB10_71: # %call.sqrt195
.cfi_escape 0x2e, 0x00
callq sqrt
.LBB10_72: # %._crit_edge139.split
cvttsd2si %xmm0, %ebx
movslq %ebx, %r12
leaq (,%r12,8), %rdi
.cfi_escape 0x2e, 0x00
callq malloc
movl %ebx, %esi
movq %rax, %r15
testl %r12d, %r12d
jle .LBB10_78
# %bb.73: # %.lr.ph.i.i
shlq $2, %r12
movl %esi, 8(%rsp) # 4-byte Spill
movl %esi, %r13d
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB10_74: # =>This Inner Loop Header: Depth=1
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq malloc
movq %rax, (%r15,%rbx,8)
incq %rbx
cmpq %rbx, %r13
jne .LBB10_74
# %bb.75: # %_Z13malloc_matrixi.exit.i
movl 8(%rsp), %esi # 4-byte Reload
testl %esi, %esi
jle .LBB10_78
# %bb.76: # %.preheader.lr.ph.i
leaq (,%r13,4), %r12
xorl %ebx, %ebx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB10_77: # %.preheader.i
# =>This Inner Loop Header: Depth=1
movl %ebx, %eax
leaq (%r14,%rax,4), %rsi
movq (%r15,%rbp,8), %rdi
.cfi_escape 0x2e, 0x00
movq %r12, %rdx
callq memcpy@PLT
movl 8(%rsp), %esi # 4-byte Reload
incq %rbp
addl %esi, %ebx
cmpq %rbp, %r13
jne .LBB10_77
.LBB10_78: # %._crit_edge20.i
.Ltmp38:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _Z12print_matrixPPii
.Ltmp39:
# %bb.79: # %_Z16convert_1d_to_2diPi.exit
movq (%rsp), %rdi # 8-byte Reload
testq %rdi, %rdi
je .LBB10_81
# %bb.80:
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB10_81: # %_ZNSt6vectorIiSaIiEED2Ev.exit
.cfi_escape 0x2e, 0x00
leaq 176(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 432(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNSt8ios_baseD2Ev
xorl %eax, %eax
addq $696, %rsp # imm = 0x2B8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB10_8:
.cfi_def_cfa_offset 752
.Ltmp41:
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp42:
# %bb.9: # %.noexc
.LBB10_82:
.Ltmp40:
jmp .LBB10_83
.LBB10_51:
.Ltmp9:
jmp .LBB10_83
.LBB10_68:
.Ltmp19:
jmp .LBB10_83
.LBB10_67:
.Ltmp14:
jmp .LBB10_83
.LBB10_54: # %.loopexit.split-lp
.Ltmp43:
jmp .LBB10_53
.LBB10_69:
.Ltmp26:
jmp .LBB10_83
.LBB10_70:
.Ltmp37:
.LBB10_83:
movq %rax, %r14
jmp .LBB10_84
.LBB10_52: # %.loopexit116
.Ltmp4:
.LBB10_53:
movq %rax, %r14
movq %r15, (%rsp) # 8-byte Spill
.LBB10_84:
cmpq $0, (%rsp) # 8-byte Folded Reload
je .LBB10_86
# %bb.85:
.cfi_escape 0x2e, 0x00
movq (%rsp), %rdi # 8-byte Reload
callq _ZdlPv
.LBB10_86: # %_ZNSt6vectorIiSaIiEED2Ev.exit101
.cfi_escape 0x2e, 0x00
leaq 176(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 432(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNSt8ios_baseD2Ev
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end10:
.size main, .Lfunc_end10-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table10:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp3-.Ltmp0 # Call between .Ltmp0 and .Ltmp3
.uleb128 .Ltmp4-.Lfunc_begin0 # jumps to .Ltmp4
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp5-.Ltmp3 # Call between .Ltmp3 and .Ltmp5
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp5-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp8-.Ltmp5 # Call between .Ltmp5 and .Ltmp8
.uleb128 .Ltmp9-.Lfunc_begin0 # jumps to .Ltmp9
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp13-.Ltmp10 # Call between .Ltmp10 and .Ltmp13
.uleb128 .Ltmp14-.Lfunc_begin0 # jumps to .Ltmp14
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp18-.Ltmp15 # Call between .Ltmp15 and .Ltmp18
.uleb128 .Ltmp19-.Lfunc_begin0 # jumps to .Ltmp19
.byte 0 # On action: cleanup
.uleb128 .Ltmp20-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp25-.Ltmp20 # Call between .Ltmp20 and .Ltmp25
.uleb128 .Ltmp26-.Lfunc_begin0 # jumps to .Ltmp26
.byte 0 # On action: cleanup
.uleb128 .Ltmp27-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp36-.Ltmp27 # Call between .Ltmp27 and .Ltmp36
.uleb128 .Ltmp37-.Lfunc_begin0 # jumps to .Ltmp37
.byte 0 # On action: cleanup
.uleb128 .Ltmp36-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp38-.Ltmp36 # Call between .Ltmp36 and .Ltmp38
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp38-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp39-.Ltmp38 # Call between .Ltmp38 and .Ltmp39
.uleb128 .Ltmp40-.Lfunc_begin0 # jumps to .Ltmp40
.byte 0 # On action: cleanup
.uleb128 .Ltmp41-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp42-.Ltmp41 # Call between .Ltmp41 and .Ltmp42
.uleb128 .Ltmp43-.Lfunc_begin0 # jumps to .Ltmp43
.byte 0 # On action: cleanup
.uleb128 .Ltmp42-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Lfunc_end10-.Ltmp42 # Call between .Ltmp42 and .Lfunc_end10
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB11_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB11_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5Hellov, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7BluringiiPiS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end11:
.size __hip_module_ctor, .Lfunc_end11-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB12_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB12_2:
retq
.Lfunc_end12:
.size __hip_module_dtor, .Lfunc_end12-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5Hellov,@object # @_Z5Hellov
.section .rodata,"a",@progbits
.globl _Z5Hellov
.p2align 3, 0x0
_Z5Hellov:
.quad _Z20__device_stub__Hellov
.size _Z5Hellov, 8
.type _Z7BluringiiPiS_S_,@object # @_Z7BluringiiPiS_S_
.globl _Z7BluringiiPiS_S_
.p2align 3, 0x0
_Z7BluringiiPiS_S_:
.quad _Z22__device_stub__BluringiiPiS_S_
.size _Z7BluringiiPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "image_array.txt"
.size .L.str.1, 16
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "vector::_M_realloc_insert"
.size .L.str.2, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5Hellov"
.size .L__unnamed_1, 10
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7BluringiiPiS_S_"
.size .L__unnamed_2, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__Hellov
.addrsig_sym _Z22__device_stub__BluringiiPiS_S_
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z5Hellov
.addrsig_sym _Z7BluringiiPiS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
Name: Daniyal Manair
Student Number: 20064993
*/
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <vector>
#include <stdio.h>
#include <random>
#include <algorithm>
#include <chrono>
#include <map>
__global__ void MatrixMulGPU(float* A, float* B, float* C, const int N) {
unsigned int col = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int row = blockIdx.y * blockDim.y + threadIdx.y;
unsigned int idx = row * N + col;
if (row < N && col < N){
C[idx] = 0.0;
for (int i = 0; i < N; i++)
C[idx] += A[row * N + i] * B[i * N + col];
}
}
__global__ void MatrixMulGPUSingle(float* A, float* B, float* C, const int N) {
for (int row = 0; row < N; row++) {
for (int col = 0; col < N; col++) {
if (row < N && col < N) {
C[row * N + col] = 0.0;
for (int k = 0; k < N; k++)
C[row * N + col] += A[row * N + k] * B[k * N + col];
}
}
}
}
void initialData(float* matrix, const int N){
for (int i = 0; i < (N*N); i++)
matrix[i] = (float)(rand() & 0xFF) / 10.0f;
}
void MatrixMulCPU(float* A, float* B, float* C, const int N){
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
for (int k = 0; k < N; k++)
C[i * N + j] += A[i * N + k] * B[k * N + j];
}
}
}
void checkResult(float* CPU, float* GPU, const int N) {
double epsilon = 1.0E-8;
for (int i = 0; i < (N*N); i++){
if (abs(CPU[i] - GPU[i]) > epsilon){
printf("CPU %f GPU %f ", CPU[i], GPU[i]);
printf("Arrays do not match.\n\n");
return;
}
}
printf("Test PASSED\n\n");
}
void printArr(float* matrix, const int N) {
printf("[");
for (int i = 0; i < (N*N); i++)
printf("%f,", matrix[i]);
printf("\b]\n");
}
float GPUtest(float* C_A, float* C_B, float* CPUResult, const int blockSize, const int N){
// Initialize variables
cudaEvent_t gStart, gEnd;
float timeDuration;
float *G_A, *G_B, *G_C, *GPUResult;
size_t size = N * N * sizeof(float);
// Initialize GPU variables
cudaMalloc((void**)&G_A, size);
cudaMalloc((void**)&G_B, size);
cudaMalloc((void**)&G_C, size);
GPUResult = (float*)malloc(size);
memset(GPUResult, 0.0, size);
cudaEventCreate(&gStart);
cudaEventCreate(&gEnd);
// Copy over the data
cudaMemcpy(G_A, C_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(G_B, C_B, size, cudaMemcpyHostToDevice);
// Perform GPU comparison
if (blockSize == 0){
cudaEventRecord(gStart);
MatrixMulGPUSingle <<<1, 1>>> (G_A, G_B, G_C, N);
cudaEventRecord(gEnd);
} else {
// Create block
int numBlocks = N / blockSize;
if (N % blockSize) numBlocks++;
dim3 block(blockSize, blockSize, 1);
dim3 grid(numBlocks, numBlocks, 1);
cudaEventRecord(gStart);
MatrixMulGPU <<<grid, block >>> (G_A, G_B, G_C, N);
cudaEventRecord(gEnd);
}
cudaEventSynchronize(gEnd);
cudaEventElapsedTime(&timeDuration, gStart, gEnd);
cudaMemcpy(GPUResult, G_C, size, cudaMemcpyDeviceToHost);
checkResult(CPUResult, GPUResult, N);
cudaFree(G_A);
cudaFree(G_B);
cudaFree(G_C);
free(GPUResult);
return timeDuration;
}
void computeMatrix(const int N) {
// Initial prints
printf("------------------------------------------------------------------------\n\n");
printf("%dx%d matrix multiplication.\n\n", N, N);
// Initialize Host variables
float *C_A, *C_B, *C_C;
size_t size = N * N * sizeof(float);
FILE *fp;
// Initialize space
C_A = (float*)malloc(size);
C_B = (float*)malloc(size);
C_C = (float*)malloc(size);
fp=fopen("machineProblem3.csv","a");
// Set with random data
initialData(C_A, N);
initialData(C_B, N);
memset(C_C, 0.0, size);
// Serial Test CPU
auto cStart = std::chrono::high_resolution_clock::now();
MatrixMulCPU(C_A, C_B, C_C, N);
auto cEnd = std::chrono::high_resolution_clock::now();
auto timeElapse = (std::chrono::duration_cast<std::chrono::microseconds>(cEnd - cStart).count())/1000.0;
printf("The CPU took %f to perform the computation.\n\n", timeElapse);
fprintf(fp,"%d,CPU,0,%f\n",N,timeElapse);
// Test Complete parallel Computation
int blockSizes [] = {0, 2, 4, 10, 20, 25};
float timeDuration;
for (int i = 0; i < 6; i++){
timeDuration = GPUtest(C_A, C_B, C_C, blockSizes[i], N);
printf("The GPU took %f to perform the computation with block size %d.\n", timeDuration, blockSizes[i]);
fprintf(fp,"%d,GPU,%d,%f\n",N,blockSizes[i],timeDuration);
}
// Free all the memory
free(C_A);
free(C_B);
free(C_C);
fclose(fp);
cudaDeviceReset();
}
void transferTimes(const int N) {
printf("------------------------------------------------------------------------\n\n");
printf("Currently transfering between %dx%d matrixs\n", N, N);
FILE *fp;
fp = fopen("machineProblem3_transfer.csv", "a");
// Initialize matrices
float* C_A, *C_B, *G_A, *G_B;;
size_t size = N * N * sizeof(float);
float time = 0;
cudaEvent_t start, end;
C_A = (float*)malloc(size);
C_B = (float*)malloc(size);
cudaMalloc((void**)&G_A, size);
cudaMalloc((void**)&G_B, size);
cudaEventCreate(&start);
cudaEventCreate(&end);
// Populate input matrices
initialData(C_A, N);
initialData(C_B, N);
cudaEventRecord(start);
cudaEventSynchronize(start);
cudaMemcpy(G_A, C_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(G_B, C_B, size, cudaMemcpyHostToDevice);
cudaEventRecord(end);
cudaEventSynchronize(end);
cudaEventElapsedTime(&time, start, end);
printf("Transfered %dx%d matrix from CPU to GPU in %fms\n", N, N, time);
fprintf(fp, "%d,0,%f\n", N, time);
cudaEventRecord(start);
cudaEventSynchronize(start);
cudaMemcpy(C_A, G_A, size, cudaMemcpyDeviceToHost);
cudaMemcpy(C_B, G_B, size, cudaMemcpyDeviceToHost);
cudaEventRecord(end);
cudaEventSynchronize(end);
cudaEventElapsedTime(&time, start, end);
cudaEventDestroy(start);
cudaEventDestroy(end);
printf("Transfered %dx%d matrix from GPU to CPU in %fms\n", N, N, time);
fprintf(fp, "%d,1,%f\n", N, time);
cudaFree(G_A);
cudaFree(G_B);
free(C_A);
free(C_B);
fclose(fp);
}
int main(){
FILE *fp1, *fp2;
fp1=fopen("machineProblem3.csv","w");
fp2=fopen("machineProblem3_transfer.csv","w");
fprintf(fp1,"matrixSize,processor,blockSize,time\n");
fprintf(fp2,"matrixSize,case,time\n");
fclose(fp1);
fclose(fp2);
int matrixWidths [] = {100, 200, 500, 1000, 1500, 5000};
for (int i = 0; i < 6; i++){
computeMatrix(matrixWidths[i]);
transferTimes(matrixWidths[i]);
}
printf("------------------------------------------------------------------------\n\n");
return 0;
} | .file "tmpxft_000b19a3_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4873:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4873:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initialDataPfi
.type _Z11initialDataPfi, @function
_Z11initialDataPfi:
.LFB4861:
.cfi_startproc
endbr64
imull %esi, %esi
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
movzbl %al, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
divss .LC0(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE4861:
.size _Z11initialDataPfi, .-_Z11initialDataPfi
.globl _Z12MatrixMulCPUPfS_S_i
.type _Z12MatrixMulCPUPfS_S_i, @function
_Z12MatrixMulCPUPfS_S_i:
.LFB4862:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L19
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
movq %rsi, %rbp
movq %rdx, %rbx
movl %ecx, %r11d
movslq %ecx, %rsi
salq $2, %rsi
movq %rdi, %r10
addq %rsi, %rdi
movl $0, %r12d
movl $0, %r13d
jmp .L13
.L15:
leal 1(%r12), %eax
addq %rsi, %r10
addq %rsi, %rdi
addq %rsi, %rbx
cmpl %r9d, %r12d
je .L11
movl %eax, %r12d
.L13:
movq %rbp, %r8
movq %rbx, %rcx
movl %r13d, %r9d
.L16:
movq %r8, %rdx
movq %r10, %rax
.L14:
movss (%rax), %xmm0
mulss (%rdx), %xmm0
addss (%rcx), %xmm0
movss %xmm0, (%rcx)
addq $4, %rax
addq %rsi, %rdx
cmpq %rdi, %rax
jne .L14
leal 1(%r9), %eax
addq $4, %r8
addq $4, %rcx
cmpl %eax, %r11d
je .L15
movl %eax, %r9d
jmp .L16
.L11:
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
ret
.cfi_endproc
.LFE4862:
.size _Z12MatrixMulCPUPfS_S_i, .-_Z12MatrixMulCPUPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "CPU %f GPU %f "
.LC4:
.string "Arrays do not match.\n\n"
.LC5:
.string "Test PASSED\n\n"
.text
.globl _Z11checkResultPfS_i
.type _Z11checkResultPfS_i, @function
_Z11checkResultPfS_i:
.LFB4863:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
imull %edx, %edx
testl %edx, %edx
jle .L23
movslq %edx, %rdx
salq $2, %rdx
movl $0, %eax
movss .LC1(%rip), %xmm4
movsd .LC2(%rip), %xmm3
.L27:
movss (%rdi,%rax), %xmm0
movss (%rsi,%rax), %xmm1
movaps %xmm0, %xmm2
subss %xmm1, %xmm2
andps %xmm4, %xmm2
cvtss2sd %xmm2, %xmm2
comisd %xmm3, %xmm2
ja .L32
addq $4, %rax
cmpq %rdx, %rax
jne .L27
.L23:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L22:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L22
.cfi_endproc
.LFE4863:
.size _Z11checkResultPfS_i, .-_Z11checkResultPfS_i
.section .rodata.str1.1
.LC6:
.string "["
.LC7:
.string "%f,"
.LC8:
.string "\b]\n"
.text
.globl _Z8printArrPfi
.type _Z8printArrPfi, @function
_Z8printArrPfi:
.LFB4864:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbp
movl %esi, %ebx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %esi
imull %ebx, %esi
testl %esi, %esi
jle .L34
movq %rbp, %rbx
movslq %esi, %rsi
leaq 0(%rbp,%rsi,4), %r12
leaq .LC7(%rip), %rbp
.L35:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L35
.L34:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4864:
.size _Z8printArrPfi, .-_Z8printArrPfi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC9:
.string "------------------------------------------------------------------------\n\n"
.align 8
.LC10:
.string "Currently transfering between %dx%d matrixs\n"
.section .rodata.str1.1
.LC11:
.string "a"
.LC12:
.string "machineProblem3_transfer.csv"
.section .rodata.str1.8
.align 8
.LC14:
.string "Transfered %dx%d matrix from CPU to GPU in %fms\n"
.section .rodata.str1.1
.LC15:
.string "%d,0,%f\n"
.section .rodata.str1.8
.align 8
.LC16:
.string "Transfered %dx%d matrix from GPU to CPU in %fms\n"
.section .rodata.str1.1
.LC17:
.string "%d,1,%f\n"
.text
.globl _Z13transferTimesi
.type _Z13transferTimesi, @function
_Z13transferTimesi:
.LFB4869:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movl %edi, %ebx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq .LC9(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl %ebx, %ecx
movl %ebx, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC11(%rip), %rsi
leaq .LC12(%rip), %rdi
call fopen@PLT
movq %rax, %r13
movl %ebx, %ebp
imull %ebx, %ebp
movslq %ebp, %rbp
salq $2, %rbp
movl $0x00000000, 4(%rsp)
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r12
leaq 8(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl %ebx, %esi
movq %r14, %rdi
call _Z11initialDataPfi
movl %ebx, %esi
movq %r12, %rdi
call _Z11initialDataPfi
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %r15
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq %r15, %rdi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
movl %ebx, %ecx
movl %ebx, %edx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
movl %ebx, %ecx
leaq .LC15(%rip), %rdx
movl $2, %esi
movq %r13, %rdi
movl $1, %eax
call __fprintf_chk@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 8(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 16(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq %r15, %rdi
call cudaEventElapsedTime@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
movl %ebx, %ecx
movl %ebx, %edx
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
movl %ebx, %ecx
leaq .LC17(%rip), %rdx
movl $2, %esi
movq %r13, %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %r13, %rdi
call fclose@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L41
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4869:
.size _Z13transferTimesi, .-_Z13transferTimesi
.globl _Z37__device_stub__Z12MatrixMulGPUPfS_S_iPfS_S_i
.type _Z37__device_stub__Z12MatrixMulGPUPfS_S_iPfS_S_i, @function
_Z37__device_stub__Z12MatrixMulGPUPfS_S_iPfS_S_i:
.LFB4895:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L46
.L42:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L47
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12MatrixMulGPUPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L42
.L47:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4895:
.size _Z37__device_stub__Z12MatrixMulGPUPfS_S_iPfS_S_i, .-_Z37__device_stub__Z12MatrixMulGPUPfS_S_iPfS_S_i
.globl _Z12MatrixMulGPUPfS_S_i
.type _Z12MatrixMulGPUPfS_S_i, @function
_Z12MatrixMulGPUPfS_S_i:
.LFB4896:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12MatrixMulGPUPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4896:
.size _Z12MatrixMulGPUPfS_S_i, .-_Z12MatrixMulGPUPfS_S_i
.globl _Z43__device_stub__Z18MatrixMulGPUSinglePfS_S_iPfS_S_i
.type _Z43__device_stub__Z18MatrixMulGPUSinglePfS_S_iPfS_S_i, @function
_Z43__device_stub__Z18MatrixMulGPUSinglePfS_S_iPfS_S_i:
.LFB4897:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L54
.L50:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L55
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18MatrixMulGPUSinglePfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L50
.L55:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4897:
.size _Z43__device_stub__Z18MatrixMulGPUSinglePfS_S_iPfS_S_i, .-_Z43__device_stub__Z18MatrixMulGPUSinglePfS_S_iPfS_S_i
.globl _Z18MatrixMulGPUSinglePfS_S_i
.type _Z18MatrixMulGPUSinglePfS_S_i, @function
_Z18MatrixMulGPUSinglePfS_S_i:
.LFB4898:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z18MatrixMulGPUSinglePfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4898:
.size _Z18MatrixMulGPUSinglePfS_S_i, .-_Z18MatrixMulGPUSinglePfS_S_i
.globl _Z7GPUtestPfS_S_ii
.type _Z7GPUtestPfS_S_ii, @function
_Z7GPUtestPfS_S_ii:
.LFB4865:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %rdi, %r15
movq %rsi, %r14
movq %rdx, 8(%rsp)
movl %ecx, %r13d
movl %r8d, %ebp
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl %r8d, %ebx
imull %r8d, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbx, %rcx
movq %rbx, %rdx
movl $0, %esi
movq %rax, %rdi
call __memset_chk@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r15, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
testl %r13d, %r13d
je .L66
movl %ebp, %eax
cltd
idivl %r13d
cmpl $1, %edx
sbbl $-1, %eax
movl %r13d, 64(%rsp)
movl %r13d, 68(%rsp)
movl $1, 72(%rsp)
movl %eax, 76(%rsp)
movl %eax, 80(%rsp)
movl $1, 84(%rsp)
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L67
.L63:
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
.L61:
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 76(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 56(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl %ebp, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call _Z11checkResultPfS_i
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movss 76(%rsp), %xmm0
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L68
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L66:
.cfi_restore_state
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L69
.L60:
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
jmp .L61
.L69:
movl %ebp, %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z43__device_stub__Z18MatrixMulGPUSinglePfS_S_iPfS_S_i
jmp .L60
.L67:
movl %ebp, %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z37__device_stub__Z12MatrixMulGPUPfS_S_iPfS_S_i
jmp .L63
.L68:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4865:
.size _Z7GPUtestPfS_S_ii, .-_Z7GPUtestPfS_S_ii
.section .rodata.str1.8
.align 8
.LC18:
.string "%dx%d matrix multiplication.\n\n"
.section .rodata.str1.1
.LC19:
.string "machineProblem3.csv"
.section .rodata.str1.8
.align 8
.LC21:
.string "The CPU took %f to perform the computation.\n\n"
.section .rodata.str1.1
.LC22:
.string "%d,CPU,0,%f\n"
.section .rodata.str1.8
.align 8
.LC23:
.string "The GPU took %f to perform the computation with block size %d.\n"
.section .rodata.str1.1
.LC24:
.string "%d,GPU,%d,%f\n"
.text
.globl _Z13computeMatrixi
.type _Z13computeMatrixi, @function
_Z13computeMatrixi:
.LFB4866:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movl %edi, %r12d
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC9(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl %r12d, %ecx
movl %r12d, %edx
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %ebx
imull %r12d, %ebx
movslq %ebx, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r15
leaq .LC11(%rip), %rsi
leaq .LC19(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
movq %rax, 16(%rsp)
movl %r12d, %esi
movq %r14, %rdi
call _Z11initialDataPfi
movl %r12d, %esi
movq %r13, %rdi
call _Z11initialDataPfi
movq %rbx, %rcx
movq %rbx, %rdx
movl $0, %esi
movq %r15, %rdi
call __memset_chk@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
movl %r12d, %ecx
movq %r15, %rdx
movq %r13, %rsi
movq %r14, %rdi
call _Z12MatrixMulCPUPfS_S_i
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rcx
subq %rbx, %rcx
movabsq $2361183241434822607, %rdx
movq %rcx, %rax
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
subq %rcx, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
divsd .LC20(%rip), %xmm0
movq %xmm0, %rbx
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %xmm0
movl %r12d, %ecx
leaq .LC22(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
movl $0, 32(%rsp)
movl $2, 36(%rsp)
movl $4, 40(%rsp)
movl $10, 44(%rsp)
movl $20, 48(%rsp)
movl $25, 52(%rsp)
leaq 32(%rsp), %rbx
leaq 56(%rsp), %rax
movq %rax, 24(%rsp)
.L71:
movl (%rbx), %ebp
movl %r12d, %r8d
movl %ebp, %ecx
movq %r15, %rdx
movq %r13, %rsi
movq %r14, %rdi
call _Z7GPUtestPfS_S_ii
pxor %xmm1, %xmm1
cvtss2sd %xmm0, %xmm1
movsd %xmm1, 8(%rsp)
movl %ebp, %edx
movapd %xmm1, %xmm0
leaq .LC23(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
movl %ebp, %r8d
movl %r12d, %ecx
leaq .LC24(%rip), %rdx
movl $2, %esi
movq 16(%rsp), %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $4, %rbx
movq 24(%rsp), %rax
cmpq %rax, %rbx
jne .L71
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq 16(%rsp), %rdi
call fclose@PLT
call cudaDeviceReset@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L75
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L75:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4866:
.size _Z13computeMatrixi, .-_Z13computeMatrixi
.section .rodata.str1.1
.LC25:
.string "w"
.section .rodata.str1.8
.align 8
.LC26:
.string "matrixSize,processor,blockSize,time\n"
.section .rodata.str1.1
.LC27:
.string "matrixSize,case,time\n"
.text
.globl main
.type main, @function
main:
.LFB4870:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq .LC25(%rip), %rbx
movq %rbx, %rsi
leaq .LC19(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
movq %rbx, %rsi
leaq .LC12(%rip), %rdi
call fopen@PLT
movq %rax, %rbx
leaq .LC26(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC27(%rip), %rdx
movl $2, %esi
movq %rbx, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %rbp, %rdi
call fclose@PLT
movq %rbx, %rdi
call fclose@PLT
movl $100, (%rsp)
movl $200, 4(%rsp)
movl $500, 8(%rsp)
movl $1000, 12(%rsp)
movl $1500, 16(%rsp)
movl $5000, 20(%rsp)
movq %rsp, %rbx
leaq 24(%rsp), %r12
.L77:
movl (%rbx), %ebp
movl %ebp, %edi
call _Z13computeMatrixi
movl %ebp, %edi
call _Z13transferTimesi
addq $4, %rbx
cmpq %r12, %rbx
jne .L77
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L81
movl $0, %eax
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L81:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4870:
.size main, .-main
.section .rodata.str1.1
.LC28:
.string "_Z18MatrixMulGPUSinglePfS_S_i"
.LC29:
.string "_Z12MatrixMulGPUPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4900:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC28(%rip), %rdx
movq %rdx, %rcx
leaq _Z18MatrixMulGPUSinglePfS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC29(%rip), %rdx
movq %rdx, %rcx
leaq _Z12MatrixMulGPUPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4900:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1092616192
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC1:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long -500134854
.long 1044740494
.align 8
.LC20:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
Name: Daniyal Manair
Student Number: 20064993
*/
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <vector>
#include <stdio.h>
#include <random>
#include <algorithm>
#include <chrono>
#include <map>
__global__ void MatrixMulGPU(float* A, float* B, float* C, const int N) {
unsigned int col = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int row = blockIdx.y * blockDim.y + threadIdx.y;
unsigned int idx = row * N + col;
if (row < N && col < N){
C[idx] = 0.0;
for (int i = 0; i < N; i++)
C[idx] += A[row * N + i] * B[i * N + col];
}
}
__global__ void MatrixMulGPUSingle(float* A, float* B, float* C, const int N) {
for (int row = 0; row < N; row++) {
for (int col = 0; col < N; col++) {
if (row < N && col < N) {
C[row * N + col] = 0.0;
for (int k = 0; k < N; k++)
C[row * N + col] += A[row * N + k] * B[k * N + col];
}
}
}
}
void initialData(float* matrix, const int N){
for (int i = 0; i < (N*N); i++)
matrix[i] = (float)(rand() & 0xFF) / 10.0f;
}
void MatrixMulCPU(float* A, float* B, float* C, const int N){
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
for (int k = 0; k < N; k++)
C[i * N + j] += A[i * N + k] * B[k * N + j];
}
}
}
void checkResult(float* CPU, float* GPU, const int N) {
double epsilon = 1.0E-8;
for (int i = 0; i < (N*N); i++){
if (abs(CPU[i] - GPU[i]) > epsilon){
printf("CPU %f GPU %f ", CPU[i], GPU[i]);
printf("Arrays do not match.\n\n");
return;
}
}
printf("Test PASSED\n\n");
}
void printArr(float* matrix, const int N) {
printf("[");
for (int i = 0; i < (N*N); i++)
printf("%f,", matrix[i]);
printf("\b]\n");
}
float GPUtest(float* C_A, float* C_B, float* CPUResult, const int blockSize, const int N){
// Initialize variables
cudaEvent_t gStart, gEnd;
float timeDuration;
float *G_A, *G_B, *G_C, *GPUResult;
size_t size = N * N * sizeof(float);
// Initialize GPU variables
cudaMalloc((void**)&G_A, size);
cudaMalloc((void**)&G_B, size);
cudaMalloc((void**)&G_C, size);
GPUResult = (float*)malloc(size);
memset(GPUResult, 0.0, size);
cudaEventCreate(&gStart);
cudaEventCreate(&gEnd);
// Copy over the data
cudaMemcpy(G_A, C_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(G_B, C_B, size, cudaMemcpyHostToDevice);
// Perform GPU comparison
if (blockSize == 0){
cudaEventRecord(gStart);
MatrixMulGPUSingle <<<1, 1>>> (G_A, G_B, G_C, N);
cudaEventRecord(gEnd);
} else {
// Create block
int numBlocks = N / blockSize;
if (N % blockSize) numBlocks++;
dim3 block(blockSize, blockSize, 1);
dim3 grid(numBlocks, numBlocks, 1);
cudaEventRecord(gStart);
MatrixMulGPU <<<grid, block >>> (G_A, G_B, G_C, N);
cudaEventRecord(gEnd);
}
cudaEventSynchronize(gEnd);
cudaEventElapsedTime(&timeDuration, gStart, gEnd);
cudaMemcpy(GPUResult, G_C, size, cudaMemcpyDeviceToHost);
checkResult(CPUResult, GPUResult, N);
cudaFree(G_A);
cudaFree(G_B);
cudaFree(G_C);
free(GPUResult);
return timeDuration;
}
void computeMatrix(const int N) {
// Initial prints
printf("------------------------------------------------------------------------\n\n");
printf("%dx%d matrix multiplication.\n\n", N, N);
// Initialize Host variables
float *C_A, *C_B, *C_C;
size_t size = N * N * sizeof(float);
FILE *fp;
// Initialize space
C_A = (float*)malloc(size);
C_B = (float*)malloc(size);
C_C = (float*)malloc(size);
fp=fopen("machineProblem3.csv","a");
// Set with random data
initialData(C_A, N);
initialData(C_B, N);
memset(C_C, 0.0, size);
// Serial Test CPU
auto cStart = std::chrono::high_resolution_clock::now();
MatrixMulCPU(C_A, C_B, C_C, N);
auto cEnd = std::chrono::high_resolution_clock::now();
auto timeElapse = (std::chrono::duration_cast<std::chrono::microseconds>(cEnd - cStart).count())/1000.0;
printf("The CPU took %f to perform the computation.\n\n", timeElapse);
fprintf(fp,"%d,CPU,0,%f\n",N,timeElapse);
// Test Complete parallel Computation
int blockSizes [] = {0, 2, 4, 10, 20, 25};
float timeDuration;
for (int i = 0; i < 6; i++){
timeDuration = GPUtest(C_A, C_B, C_C, blockSizes[i], N);
printf("The GPU took %f to perform the computation with block size %d.\n", timeDuration, blockSizes[i]);
fprintf(fp,"%d,GPU,%d,%f\n",N,blockSizes[i],timeDuration);
}
// Free all the memory
free(C_A);
free(C_B);
free(C_C);
fclose(fp);
cudaDeviceReset();
}
void transferTimes(const int N) {
printf("------------------------------------------------------------------------\n\n");
printf("Currently transfering between %dx%d matrixs\n", N, N);
FILE *fp;
fp = fopen("machineProblem3_transfer.csv", "a");
// Initialize matrices
float* C_A, *C_B, *G_A, *G_B;;
size_t size = N * N * sizeof(float);
float time = 0;
cudaEvent_t start, end;
C_A = (float*)malloc(size);
C_B = (float*)malloc(size);
cudaMalloc((void**)&G_A, size);
cudaMalloc((void**)&G_B, size);
cudaEventCreate(&start);
cudaEventCreate(&end);
// Populate input matrices
initialData(C_A, N);
initialData(C_B, N);
cudaEventRecord(start);
cudaEventSynchronize(start);
cudaMemcpy(G_A, C_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(G_B, C_B, size, cudaMemcpyHostToDevice);
cudaEventRecord(end);
cudaEventSynchronize(end);
cudaEventElapsedTime(&time, start, end);
printf("Transfered %dx%d matrix from CPU to GPU in %fms\n", N, N, time);
fprintf(fp, "%d,0,%f\n", N, time);
cudaEventRecord(start);
cudaEventSynchronize(start);
cudaMemcpy(C_A, G_A, size, cudaMemcpyDeviceToHost);
cudaMemcpy(C_B, G_B, size, cudaMemcpyDeviceToHost);
cudaEventRecord(end);
cudaEventSynchronize(end);
cudaEventElapsedTime(&time, start, end);
cudaEventDestroy(start);
cudaEventDestroy(end);
printf("Transfered %dx%d matrix from GPU to CPU in %fms\n", N, N, time);
fprintf(fp, "%d,1,%f\n", N, time);
cudaFree(G_A);
cudaFree(G_B);
free(C_A);
free(C_B);
fclose(fp);
}
int main(){
FILE *fp1, *fp2;
fp1=fopen("machineProblem3.csv","w");
fp2=fopen("machineProblem3_transfer.csv","w");
fprintf(fp1,"matrixSize,processor,blockSize,time\n");
fprintf(fp2,"matrixSize,case,time\n");
fclose(fp1);
fclose(fp2);
int matrixWidths [] = {100, 200, 500, 1000, 1500, 5000};
for (int i = 0; i < 6; i++){
computeMatrix(matrixWidths[i]);
transferTimes(matrixWidths[i]);
}
printf("------------------------------------------------------------------------\n\n");
return 0;
} | /*
Name: Daniyal Manair
Student Number: 20064993
*/
#include "hip/hip_runtime.h"
#include <vector>
#include <stdio.h>
#include <random>
#include <algorithm>
#include <chrono>
#include <map>
__global__ void MatrixMulGPU(float* A, float* B, float* C, const int N) {
unsigned int col = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int row = blockIdx.y * blockDim.y + threadIdx.y;
unsigned int idx = row * N + col;
if (row < N && col < N){
C[idx] = 0.0;
for (int i = 0; i < N; i++)
C[idx] += A[row * N + i] * B[i * N + col];
}
}
__global__ void MatrixMulGPUSingle(float* A, float* B, float* C, const int N) {
for (int row = 0; row < N; row++) {
for (int col = 0; col < N; col++) {
if (row < N && col < N) {
C[row * N + col] = 0.0;
for (int k = 0; k < N; k++)
C[row * N + col] += A[row * N + k] * B[k * N + col];
}
}
}
}
void initialData(float* matrix, const int N){
for (int i = 0; i < (N*N); i++)
matrix[i] = (float)(rand() & 0xFF) / 10.0f;
}
void MatrixMulCPU(float* A, float* B, float* C, const int N){
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
for (int k = 0; k < N; k++)
C[i * N + j] += A[i * N + k] * B[k * N + j];
}
}
}
void checkResult(float* CPU, float* GPU, const int N) {
double epsilon = 1.0E-8;
for (int i = 0; i < (N*N); i++){
if (abs(CPU[i] - GPU[i]) > epsilon){
printf("CPU %f GPU %f ", CPU[i], GPU[i]);
printf("Arrays do not match.\n\n");
return;
}
}
printf("Test PASSED\n\n");
}
void printArr(float* matrix, const int N) {
printf("[");
for (int i = 0; i < (N*N); i++)
printf("%f,", matrix[i]);
printf("\b]\n");
}
float GPUtest(float* C_A, float* C_B, float* CPUResult, const int blockSize, const int N){
// Initialize variables
hipEvent_t gStart, gEnd;
float timeDuration;
float *G_A, *G_B, *G_C, *GPUResult;
size_t size = N * N * sizeof(float);
// Initialize GPU variables
hipMalloc((void**)&G_A, size);
hipMalloc((void**)&G_B, size);
hipMalloc((void**)&G_C, size);
GPUResult = (float*)malloc(size);
memset(GPUResult, 0.0, size);
hipEventCreate(&gStart);
hipEventCreate(&gEnd);
// Copy over the data
hipMemcpy(G_A, C_A, size, hipMemcpyHostToDevice);
hipMemcpy(G_B, C_B, size, hipMemcpyHostToDevice);
// Perform GPU comparison
if (blockSize == 0){
hipEventRecord(gStart);
MatrixMulGPUSingle <<<1, 1>>> (G_A, G_B, G_C, N);
hipEventRecord(gEnd);
} else {
// Create block
int numBlocks = N / blockSize;
if (N % blockSize) numBlocks++;
dim3 block(blockSize, blockSize, 1);
dim3 grid(numBlocks, numBlocks, 1);
hipEventRecord(gStart);
MatrixMulGPU <<<grid, block >>> (G_A, G_B, G_C, N);
hipEventRecord(gEnd);
}
hipEventSynchronize(gEnd);
hipEventElapsedTime(&timeDuration, gStart, gEnd);
hipMemcpy(GPUResult, G_C, size, hipMemcpyDeviceToHost);
checkResult(CPUResult, GPUResult, N);
hipFree(G_A);
hipFree(G_B);
hipFree(G_C);
free(GPUResult);
return timeDuration;
}
void computeMatrix(const int N) {
// Initial prints
printf("------------------------------------------------------------------------\n\n");
printf("%dx%d matrix multiplication.\n\n", N, N);
// Initialize Host variables
float *C_A, *C_B, *C_C;
size_t size = N * N * sizeof(float);
FILE *fp;
// Initialize space
C_A = (float*)malloc(size);
C_B = (float*)malloc(size);
C_C = (float*)malloc(size);
fp=fopen("machineProblem3.csv","a");
// Set with random data
initialData(C_A, N);
initialData(C_B, N);
memset(C_C, 0.0, size);
// Serial Test CPU
auto cStart = std::chrono::high_resolution_clock::now();
MatrixMulCPU(C_A, C_B, C_C, N);
auto cEnd = std::chrono::high_resolution_clock::now();
auto timeElapse = (std::chrono::duration_cast<std::chrono::microseconds>(cEnd - cStart).count())/1000.0;
printf("The CPU took %f to perform the computation.\n\n", timeElapse);
fprintf(fp,"%d,CPU,0,%f\n",N,timeElapse);
// Test Complete parallel Computation
int blockSizes [] = {0, 2, 4, 10, 20, 25};
float timeDuration;
for (int i = 0; i < 6; i++){
timeDuration = GPUtest(C_A, C_B, C_C, blockSizes[i], N);
printf("The GPU took %f to perform the computation with block size %d.\n", timeDuration, blockSizes[i]);
fprintf(fp,"%d,GPU,%d,%f\n",N,blockSizes[i],timeDuration);
}
// Free all the memory
free(C_A);
free(C_B);
free(C_C);
fclose(fp);
hipDeviceReset();
}
void transferTimes(const int N) {
printf("------------------------------------------------------------------------\n\n");
printf("Currently transfering between %dx%d matrixs\n", N, N);
FILE *fp;
fp = fopen("machineProblem3_transfer.csv", "a");
// Initialize matrices
float* C_A, *C_B, *G_A, *G_B;;
size_t size = N * N * sizeof(float);
float time = 0;
hipEvent_t start, end;
C_A = (float*)malloc(size);
C_B = (float*)malloc(size);
hipMalloc((void**)&G_A, size);
hipMalloc((void**)&G_B, size);
hipEventCreate(&start);
hipEventCreate(&end);
// Populate input matrices
initialData(C_A, N);
initialData(C_B, N);
hipEventRecord(start);
hipEventSynchronize(start);
hipMemcpy(G_A, C_A, size, hipMemcpyHostToDevice);
hipMemcpy(G_B, C_B, size, hipMemcpyHostToDevice);
hipEventRecord(end);
hipEventSynchronize(end);
hipEventElapsedTime(&time, start, end);
printf("Transfered %dx%d matrix from CPU to GPU in %fms\n", N, N, time);
fprintf(fp, "%d,0,%f\n", N, time);
hipEventRecord(start);
hipEventSynchronize(start);
hipMemcpy(C_A, G_A, size, hipMemcpyDeviceToHost);
hipMemcpy(C_B, G_B, size, hipMemcpyDeviceToHost);
hipEventRecord(end);
hipEventSynchronize(end);
hipEventElapsedTime(&time, start, end);
hipEventDestroy(start);
hipEventDestroy(end);
printf("Transfered %dx%d matrix from GPU to CPU in %fms\n", N, N, time);
fprintf(fp, "%d,1,%f\n", N, time);
hipFree(G_A);
hipFree(G_B);
free(C_A);
free(C_B);
fclose(fp);
}
int main(){
FILE *fp1, *fp2;
fp1=fopen("machineProblem3.csv","w");
fp2=fopen("machineProblem3_transfer.csv","w");
fprintf(fp1,"matrixSize,processor,blockSize,time\n");
fprintf(fp2,"matrixSize,case,time\n");
fclose(fp1);
fclose(fp2);
int matrixWidths [] = {100, 200, 500, 1000, 1500, 5000};
for (int i = 0; i < 6; i++){
computeMatrix(matrixWidths[i]);
transferTimes(matrixWidths[i]);
}
printf("------------------------------------------------------------------------\n\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
Name: Daniyal Manair
Student Number: 20064993
*/
#include "hip/hip_runtime.h"
#include <vector>
#include <stdio.h>
#include <random>
#include <algorithm>
#include <chrono>
#include <map>
__global__ void MatrixMulGPU(float* A, float* B, float* C, const int N) {
unsigned int col = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int row = blockIdx.y * blockDim.y + threadIdx.y;
unsigned int idx = row * N + col;
if (row < N && col < N){
C[idx] = 0.0;
for (int i = 0; i < N; i++)
C[idx] += A[row * N + i] * B[i * N + col];
}
}
__global__ void MatrixMulGPUSingle(float* A, float* B, float* C, const int N) {
for (int row = 0; row < N; row++) {
for (int col = 0; col < N; col++) {
if (row < N && col < N) {
C[row * N + col] = 0.0;
for (int k = 0; k < N; k++)
C[row * N + col] += A[row * N + k] * B[k * N + col];
}
}
}
}
void initialData(float* matrix, const int N){
for (int i = 0; i < (N*N); i++)
matrix[i] = (float)(rand() & 0xFF) / 10.0f;
}
void MatrixMulCPU(float* A, float* B, float* C, const int N){
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
for (int k = 0; k < N; k++)
C[i * N + j] += A[i * N + k] * B[k * N + j];
}
}
}
void checkResult(float* CPU, float* GPU, const int N) {
double epsilon = 1.0E-8;
for (int i = 0; i < (N*N); i++){
if (abs(CPU[i] - GPU[i]) > epsilon){
printf("CPU %f GPU %f ", CPU[i], GPU[i]);
printf("Arrays do not match.\n\n");
return;
}
}
printf("Test PASSED\n\n");
}
void printArr(float* matrix, const int N) {
printf("[");
for (int i = 0; i < (N*N); i++)
printf("%f,", matrix[i]);
printf("\b]\n");
}
float GPUtest(float* C_A, float* C_B, float* CPUResult, const int blockSize, const int N){
// Initialize variables
hipEvent_t gStart, gEnd;
float timeDuration;
float *G_A, *G_B, *G_C, *GPUResult;
size_t size = N * N * sizeof(float);
// Initialize GPU variables
hipMalloc((void**)&G_A, size);
hipMalloc((void**)&G_B, size);
hipMalloc((void**)&G_C, size);
GPUResult = (float*)malloc(size);
memset(GPUResult, 0.0, size);
hipEventCreate(&gStart);
hipEventCreate(&gEnd);
// Copy over the data
hipMemcpy(G_A, C_A, size, hipMemcpyHostToDevice);
hipMemcpy(G_B, C_B, size, hipMemcpyHostToDevice);
// Perform GPU comparison
if (blockSize == 0){
hipEventRecord(gStart);
MatrixMulGPUSingle <<<1, 1>>> (G_A, G_B, G_C, N);
hipEventRecord(gEnd);
} else {
// Create block
int numBlocks = N / blockSize;
if (N % blockSize) numBlocks++;
dim3 block(blockSize, blockSize, 1);
dim3 grid(numBlocks, numBlocks, 1);
hipEventRecord(gStart);
MatrixMulGPU <<<grid, block >>> (G_A, G_B, G_C, N);
hipEventRecord(gEnd);
}
hipEventSynchronize(gEnd);
hipEventElapsedTime(&timeDuration, gStart, gEnd);
hipMemcpy(GPUResult, G_C, size, hipMemcpyDeviceToHost);
checkResult(CPUResult, GPUResult, N);
hipFree(G_A);
hipFree(G_B);
hipFree(G_C);
free(GPUResult);
return timeDuration;
}
void computeMatrix(const int N) {
// Initial prints
printf("------------------------------------------------------------------------\n\n");
printf("%dx%d matrix multiplication.\n\n", N, N);
// Initialize Host variables
float *C_A, *C_B, *C_C;
size_t size = N * N * sizeof(float);
FILE *fp;
// Initialize space
C_A = (float*)malloc(size);
C_B = (float*)malloc(size);
C_C = (float*)malloc(size);
fp=fopen("machineProblem3.csv","a");
// Set with random data
initialData(C_A, N);
initialData(C_B, N);
memset(C_C, 0.0, size);
// Serial Test CPU
auto cStart = std::chrono::high_resolution_clock::now();
MatrixMulCPU(C_A, C_B, C_C, N);
auto cEnd = std::chrono::high_resolution_clock::now();
auto timeElapse = (std::chrono::duration_cast<std::chrono::microseconds>(cEnd - cStart).count())/1000.0;
printf("The CPU took %f to perform the computation.\n\n", timeElapse);
fprintf(fp,"%d,CPU,0,%f\n",N,timeElapse);
// Test Complete parallel Computation
int blockSizes [] = {0, 2, 4, 10, 20, 25};
float timeDuration;
for (int i = 0; i < 6; i++){
timeDuration = GPUtest(C_A, C_B, C_C, blockSizes[i], N);
printf("The GPU took %f to perform the computation with block size %d.\n", timeDuration, blockSizes[i]);
fprintf(fp,"%d,GPU,%d,%f\n",N,blockSizes[i],timeDuration);
}
// Free all the memory
free(C_A);
free(C_B);
free(C_C);
fclose(fp);
hipDeviceReset();
}
void transferTimes(const int N) {
printf("------------------------------------------------------------------------\n\n");
printf("Currently transfering between %dx%d matrixs\n", N, N);
FILE *fp;
fp = fopen("machineProblem3_transfer.csv", "a");
// Initialize matrices
float* C_A, *C_B, *G_A, *G_B;;
size_t size = N * N * sizeof(float);
float time = 0;
hipEvent_t start, end;
C_A = (float*)malloc(size);
C_B = (float*)malloc(size);
hipMalloc((void**)&G_A, size);
hipMalloc((void**)&G_B, size);
hipEventCreate(&start);
hipEventCreate(&end);
// Populate input matrices
initialData(C_A, N);
initialData(C_B, N);
hipEventRecord(start);
hipEventSynchronize(start);
hipMemcpy(G_A, C_A, size, hipMemcpyHostToDevice);
hipMemcpy(G_B, C_B, size, hipMemcpyHostToDevice);
hipEventRecord(end);
hipEventSynchronize(end);
hipEventElapsedTime(&time, start, end);
printf("Transfered %dx%d matrix from CPU to GPU in %fms\n", N, N, time);
fprintf(fp, "%d,0,%f\n", N, time);
hipEventRecord(start);
hipEventSynchronize(start);
hipMemcpy(C_A, G_A, size, hipMemcpyDeviceToHost);
hipMemcpy(C_B, G_B, size, hipMemcpyDeviceToHost);
hipEventRecord(end);
hipEventSynchronize(end);
hipEventElapsedTime(&time, start, end);
hipEventDestroy(start);
hipEventDestroy(end);
printf("Transfered %dx%d matrix from GPU to CPU in %fms\n", N, N, time);
fprintf(fp, "%d,1,%f\n", N, time);
hipFree(G_A);
hipFree(G_B);
free(C_A);
free(C_B);
fclose(fp);
}
int main(){
FILE *fp1, *fp2;
fp1=fopen("machineProblem3.csv","w");
fp2=fopen("machineProblem3_transfer.csv","w");
fprintf(fp1,"matrixSize,processor,blockSize,time\n");
fprintf(fp2,"matrixSize,case,time\n");
fclose(fp1);
fclose(fp2);
int matrixWidths [] = {100, 200, 500, 1000, 1500, 5000};
for (int i = 0; i < 6; i++){
computeMatrix(matrixWidths[i]);
transferTimes(matrixWidths[i]);
}
printf("------------------------------------------------------------------------\n\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12MatrixMulGPUPfS_S_i
.globl _Z12MatrixMulGPUPfS_S_i
.p2align 8
.type _Z12MatrixMulGPUPfS_S_i,@function
_Z12MatrixMulGPUPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_max_u32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s4, v2
s_cbranch_execz .LBB0_4
s_load_b64 s[2:3], s[0:1], 0x10
v_mul_lo_u32 v4, v1, s4
v_mov_b32_e32 v6, 0
s_cmp_lt_i32 s4, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, v4, v0
v_lshlrev_b64 v[2:3], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_store_b32 v[2:3], v6, off
s_cbranch_scc1 .LBB0_4
global_load_b32 v5, v[2:3], off
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_dual_mov_b32 v7, 0 :: v_dual_add_nc_u32 v6, s5, v4
s_add_i32 s5, s5, 1
s_cmp_lg_u32 s4, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v1, v7
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[8:9], 2, v[0:1]
v_add_nc_u32_e32 v0, s4, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s0, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
v_add_co_u32 v8, vcc_lo, s2, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
global_load_b32 v1, v[6:7], off
global_load_b32 v6, v[8:9], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v5, v1, v6
global_store_b32 v[2:3], v5, off
s_cbranch_scc1 .LBB0_3
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12MatrixMulGPUPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12MatrixMulGPUPfS_S_i, .Lfunc_end0-_Z12MatrixMulGPUPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z18MatrixMulGPUSinglePfS_S_i
.globl _Z18MatrixMulGPUSinglePfS_S_i
.p2align 8
.type _Z18MatrixMulGPUSinglePfS_S_i,@function
_Z18MatrixMulGPUSinglePfS_S_i:
s_load_b32 s16, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s16, 1
s_cbranch_scc1 .LBB1_7
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v0, 0
s_mov_b32 s3, 0
s_mov_b32 s17, 0
s_mov_b32 s8, s3
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB1_2:
s_mov_b32 s9, s3
s_mov_b32 s18, s3
s_lshl_b64 s[10:11], s[8:9], 2
s_mul_i32 s9, s17, s16
s_waitcnt lgkmcnt(0)
s_add_u32 s10, s4, s10
s_addc_u32 s11, s5, s11
.p2align 6
.LBB1_3:
s_add_i32 s2, s18, s9
v_mov_b32_e32 v1, 0
s_lshl_b64 s[12:13], s[2:3], 2
s_mov_b32 s19, 0
s_add_u32 s12, s0, s12
s_addc_u32 s13, s1, s13
s_mov_b64 s[14:15], s[10:11]
s_mov_b32 s2, s18
global_store_b32 v0, v0, s[12:13]
.LBB1_4:
s_lshl_b64 s[20:21], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s20, s6, s20
s_addc_u32 s21, s7, s21
s_clause 0x1
global_load_b32 v2, v0, s[14:15]
global_load_b32 v3, v0, s[20:21]
s_add_i32 s19, s19, 1
s_add_i32 s2, s2, s16
s_add_u32 s14, s14, 4
s_addc_u32 s15, s15, 0
s_cmp_lg_u32 s16, s19
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v1, v2, v3
global_store_b32 v0, v1, s[12:13]
s_cbranch_scc1 .LBB1_4
s_add_i32 s18, s18, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s18, s16
s_cbranch_scc0 .LBB1_3
s_add_i32 s17, s17, 1
s_add_i32 s8, s8, s16
s_cmp_eq_u32 s17, s16
s_cbranch_scc0 .LBB1_2
.LBB1_7:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18MatrixMulGPUSinglePfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 22
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z18MatrixMulGPUSinglePfS_S_i, .Lfunc_end1-_Z18MatrixMulGPUSinglePfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12MatrixMulGPUPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12MatrixMulGPUPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18MatrixMulGPUSinglePfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z18MatrixMulGPUSinglePfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
Name: Daniyal Manair
Student Number: 20064993
*/
#include "hip/hip_runtime.h"
#include <vector>
#include <stdio.h>
#include <random>
#include <algorithm>
#include <chrono>
#include <map>
__global__ void MatrixMulGPU(float* A, float* B, float* C, const int N) {
unsigned int col = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int row = blockIdx.y * blockDim.y + threadIdx.y;
unsigned int idx = row * N + col;
if (row < N && col < N){
C[idx] = 0.0;
for (int i = 0; i < N; i++)
C[idx] += A[row * N + i] * B[i * N + col];
}
}
__global__ void MatrixMulGPUSingle(float* A, float* B, float* C, const int N) {
for (int row = 0; row < N; row++) {
for (int col = 0; col < N; col++) {
if (row < N && col < N) {
C[row * N + col] = 0.0;
for (int k = 0; k < N; k++)
C[row * N + col] += A[row * N + k] * B[k * N + col];
}
}
}
}
void initialData(float* matrix, const int N){
for (int i = 0; i < (N*N); i++)
matrix[i] = (float)(rand() & 0xFF) / 10.0f;
}
void MatrixMulCPU(float* A, float* B, float* C, const int N){
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
for (int k = 0; k < N; k++)
C[i * N + j] += A[i * N + k] * B[k * N + j];
}
}
}
void checkResult(float* CPU, float* GPU, const int N) {
double epsilon = 1.0E-8;
for (int i = 0; i < (N*N); i++){
if (abs(CPU[i] - GPU[i]) > epsilon){
printf("CPU %f GPU %f ", CPU[i], GPU[i]);
printf("Arrays do not match.\n\n");
return;
}
}
printf("Test PASSED\n\n");
}
void printArr(float* matrix, const int N) {
printf("[");
for (int i = 0; i < (N*N); i++)
printf("%f,", matrix[i]);
printf("\b]\n");
}
float GPUtest(float* C_A, float* C_B, float* CPUResult, const int blockSize, const int N){
// Initialize variables
hipEvent_t gStart, gEnd;
float timeDuration;
float *G_A, *G_B, *G_C, *GPUResult;
size_t size = N * N * sizeof(float);
// Initialize GPU variables
hipMalloc((void**)&G_A, size);
hipMalloc((void**)&G_B, size);
hipMalloc((void**)&G_C, size);
GPUResult = (float*)malloc(size);
memset(GPUResult, 0.0, size);
hipEventCreate(&gStart);
hipEventCreate(&gEnd);
// Copy over the data
hipMemcpy(G_A, C_A, size, hipMemcpyHostToDevice);
hipMemcpy(G_B, C_B, size, hipMemcpyHostToDevice);
// Perform GPU comparison
if (blockSize == 0){
hipEventRecord(gStart);
MatrixMulGPUSingle <<<1, 1>>> (G_A, G_B, G_C, N);
hipEventRecord(gEnd);
} else {
// Create block
int numBlocks = N / blockSize;
if (N % blockSize) numBlocks++;
dim3 block(blockSize, blockSize, 1);
dim3 grid(numBlocks, numBlocks, 1);
hipEventRecord(gStart);
MatrixMulGPU <<<grid, block >>> (G_A, G_B, G_C, N);
hipEventRecord(gEnd);
}
hipEventSynchronize(gEnd);
hipEventElapsedTime(&timeDuration, gStart, gEnd);
hipMemcpy(GPUResult, G_C, size, hipMemcpyDeviceToHost);
checkResult(CPUResult, GPUResult, N);
hipFree(G_A);
hipFree(G_B);
hipFree(G_C);
free(GPUResult);
return timeDuration;
}
void computeMatrix(const int N) {
// Initial prints
printf("------------------------------------------------------------------------\n\n");
printf("%dx%d matrix multiplication.\n\n", N, N);
// Initialize Host variables
float *C_A, *C_B, *C_C;
size_t size = N * N * sizeof(float);
FILE *fp;
// Initialize space
C_A = (float*)malloc(size);
C_B = (float*)malloc(size);
C_C = (float*)malloc(size);
fp=fopen("machineProblem3.csv","a");
// Set with random data
initialData(C_A, N);
initialData(C_B, N);
memset(C_C, 0.0, size);
// Serial Test CPU
auto cStart = std::chrono::high_resolution_clock::now();
MatrixMulCPU(C_A, C_B, C_C, N);
auto cEnd = std::chrono::high_resolution_clock::now();
auto timeElapse = (std::chrono::duration_cast<std::chrono::microseconds>(cEnd - cStart).count())/1000.0;
printf("The CPU took %f to perform the computation.\n\n", timeElapse);
fprintf(fp,"%d,CPU,0,%f\n",N,timeElapse);
// Test Complete parallel Computation
int blockSizes [] = {0, 2, 4, 10, 20, 25};
float timeDuration;
for (int i = 0; i < 6; i++){
timeDuration = GPUtest(C_A, C_B, C_C, blockSizes[i], N);
printf("The GPU took %f to perform the computation with block size %d.\n", timeDuration, blockSizes[i]);
fprintf(fp,"%d,GPU,%d,%f\n",N,blockSizes[i],timeDuration);
}
// Free all the memory
free(C_A);
free(C_B);
free(C_C);
fclose(fp);
hipDeviceReset();
}
void transferTimes(const int N) {
printf("------------------------------------------------------------------------\n\n");
printf("Currently transfering between %dx%d matrixs\n", N, N);
FILE *fp;
fp = fopen("machineProblem3_transfer.csv", "a");
// Initialize matrices
float* C_A, *C_B, *G_A, *G_B;;
size_t size = N * N * sizeof(float);
float time = 0;
hipEvent_t start, end;
C_A = (float*)malloc(size);
C_B = (float*)malloc(size);
hipMalloc((void**)&G_A, size);
hipMalloc((void**)&G_B, size);
hipEventCreate(&start);
hipEventCreate(&end);
// Populate input matrices
initialData(C_A, N);
initialData(C_B, N);
hipEventRecord(start);
hipEventSynchronize(start);
hipMemcpy(G_A, C_A, size, hipMemcpyHostToDevice);
hipMemcpy(G_B, C_B, size, hipMemcpyHostToDevice);
hipEventRecord(end);
hipEventSynchronize(end);
hipEventElapsedTime(&time, start, end);
printf("Transfered %dx%d matrix from CPU to GPU in %fms\n", N, N, time);
fprintf(fp, "%d,0,%f\n", N, time);
hipEventRecord(start);
hipEventSynchronize(start);
hipMemcpy(C_A, G_A, size, hipMemcpyDeviceToHost);
hipMemcpy(C_B, G_B, size, hipMemcpyDeviceToHost);
hipEventRecord(end);
hipEventSynchronize(end);
hipEventElapsedTime(&time, start, end);
hipEventDestroy(start);
hipEventDestroy(end);
printf("Transfered %dx%d matrix from GPU to CPU in %fms\n", N, N, time);
fprintf(fp, "%d,1,%f\n", N, time);
hipFree(G_A);
hipFree(G_B);
free(C_A);
free(C_B);
fclose(fp);
}
int main(){
FILE *fp1, *fp2;
fp1=fopen("machineProblem3.csv","w");
fp2=fopen("machineProblem3_transfer.csv","w");
fprintf(fp1,"matrixSize,processor,blockSize,time\n");
fprintf(fp2,"matrixSize,case,time\n");
fclose(fp1);
fclose(fp2);
int matrixWidths [] = {100, 200, 500, 1000, 1500, 5000};
for (int i = 0; i < 6; i++){
computeMatrix(matrixWidths[i]);
transferTimes(matrixWidths[i]);
}
printf("------------------------------------------------------------------------\n\n");
return 0;
} | .text
.file "kernel.hip"
.globl _Z27__device_stub__MatrixMulGPUPfS_S_i # -- Begin function _Z27__device_stub__MatrixMulGPUPfS_S_i
.p2align 4, 0x90
.type _Z27__device_stub__MatrixMulGPUPfS_S_i,@function
_Z27__device_stub__MatrixMulGPUPfS_S_i: # @_Z27__device_stub__MatrixMulGPUPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12MatrixMulGPUPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__MatrixMulGPUPfS_S_i, .Lfunc_end0-_Z27__device_stub__MatrixMulGPUPfS_S_i
.cfi_endproc
# -- End function
.globl _Z33__device_stub__MatrixMulGPUSinglePfS_S_i # -- Begin function _Z33__device_stub__MatrixMulGPUSinglePfS_S_i
.p2align 4, 0x90
.type _Z33__device_stub__MatrixMulGPUSinglePfS_S_i,@function
_Z33__device_stub__MatrixMulGPUSinglePfS_S_i: # @_Z33__device_stub__MatrixMulGPUSinglePfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18MatrixMulGPUSinglePfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z33__device_stub__MatrixMulGPUSinglePfS_S_i, .Lfunc_end1-_Z33__device_stub__MatrixMulGPUSinglePfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z11initialDataPfi
.LCPI2_0:
.long 0x41200000 # float 10
.text
.globl _Z11initialDataPfi
.p2align 4, 0x90
.type _Z11initialDataPfi,@function
_Z11initialDataPfi: # @_Z11initialDataPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
je .LBB2_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %esi, %ebx
movq %rdi, %r14
imull %ebx, %ebx
cmpl $1, %ebx
adcl $0, %ebx
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
divss .LCPI2_0(%rip), %xmm0
movss %xmm0, (%r14,%r15,4)
incq %r15
cmpq %r15, %rbx
jne .LBB2_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB2_4: # %._crit_edge
retq
.Lfunc_end2:
.size _Z11initialDataPfi, .Lfunc_end2-_Z11initialDataPfi
.cfi_endproc
# -- End function
.globl _Z12MatrixMulCPUPfS_S_i # -- Begin function _Z12MatrixMulCPUPfS_S_i
.p2align 4, 0x90
.type _Z12MatrixMulCPUPfS_S_i,@function
_Z12MatrixMulCPUPfS_S_i: # @_Z12MatrixMulCPUPfS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB3_8
# %bb.1: # %.preheader23.lr.ph
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %eax
leaq (,%rax,4), %r8
xorl %r9d, %r9d
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB3_2: # %.preheader23
# =>This Loop Header: Depth=1
# Child Loop BB3_3 Depth 2
# Child Loop BB3_4 Depth 3
movl %r9d, %r11d
leaq (%rdi,%r11,4), %r11
movq %r10, %rbx
imulq %rax, %rbx
leaq (%rdx,%rbx,4), %rbx
movq %rsi, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_3: # %.preheader
# Parent Loop BB3_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_4 Depth 3
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %r14, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_4: # Parent Loop BB3_2 Depth=1
# Parent Loop BB3_3 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r11,%r13,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r12), %xmm1
addss %xmm1, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r13
addq %r8, %r12
cmpq %r13, %rax
jne .LBB3_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB3_3 Depth=2
incq %r15
addq $4, %r14
cmpq %rax, %r15
jne .LBB3_3
# %bb.6: # %._crit_edge26
# in Loop: Header=BB3_2 Depth=1
incq %r10
addl %ecx, %r9d
cmpq %rax, %r10
jne .LBB3_2
# %bb.7:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.LBB3_8: # %._crit_edge28
retq
.Lfunc_end3:
.size _Z12MatrixMulCPUPfS_S_i, .Lfunc_end3-_Z12MatrixMulCPUPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z11checkResultPfS_i
.LCPI4_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI4_1:
.quad 0x3e45798ee2308c3a # double 1.0E-8
.text
.globl _Z11checkResultPfS_i
.p2align 4, 0x90
.type _Z11checkResultPfS_i,@function
_Z11checkResultPfS_i: # @_Z11checkResultPfS_i
.cfi_startproc
# %bb.0:
# kill: def $edx killed $edx def $rdx
movq %rdi, %rax
movl $.Lstr.1, %edi
testl %edx, %edx
je puts@PLT # TAILCALL
# %bb.1: # %.lr.ph.preheader
imull %edx, %edx
cmpl $1, %edx
adcl $0, %edx
xorl %ecx, %ecx
movaps .LCPI4_0(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
movsd .LCPI4_1(%rip), %xmm1 # xmm1 = mem[0],zero
jmp .LBB4_3
.p2align 4, 0x90
.LBB4_2: # in Loop: Header=BB4_3 Depth=1
incq %rcx
cmpq %rcx, %rdx
je puts@PLT # TAILCALL
.LBB4_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rax,%rcx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss (%rsi,%rcx,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
movaps %xmm2, %xmm4
subss %xmm3, %xmm4
andps %xmm0, %xmm4
cvtss2sd %xmm4, %xmm4
ucomisd %xmm1, %xmm4
jbe .LBB4_2
# %bb.4:
pushq %rax
.cfi_def_cfa_offset 16
xorps %xmm0, %xmm0
cvtss2sd %xmm2, %xmm0
xorps %xmm1, %xmm1
cvtss2sd %xmm3, %xmm1
movl $.L.str, %edi
movb $2, %al
callq printf
movl $.Lstr, %edi
addq $8, %rsp
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end4:
.size _Z11checkResultPfS_i, .Lfunc_end4-_Z11checkResultPfS_i
.cfi_endproc
# -- End function
.globl _Z8printArrPfi # -- Begin function _Z8printArrPfi
.p2align 4, 0x90
.type _Z8printArrPfi,@function
_Z8printArrPfi: # @_Z8printArrPfi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %esi, %ebx
movq %rdi, %r14
movl $91, %edi
callq putchar@PLT
testl %ebx, %ebx
je .LBB5_3
# %bb.1: # %.lr.ph.preheader
imull %ebx, %ebx
cmpl $1, %ebx
adcl $0, %ebx
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB5_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %rbx
jne .LBB5_2
.LBB5_3: # %._crit_edge
movl $.Lstr.2, %edi
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end5:
.size _Z8printArrPfi, .Lfunc_end5-_Z8printArrPfi
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z7GPUtestPfS_S_ii
.LCPI6_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI6_1:
.quad 0x3e45798ee2308c3a # double 1.0E-8
.text
.globl _Z7GPUtestPfS_S_ii
.p2align 4, 0x90
.type _Z7GPUtestPfS_S_ii,@function
_Z7GPUtestPfS_S_ii: # @_Z7GPUtestPfS_S_ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %r13d
movq %rdx, %r14
movq %rsi, 176(%rsp) # 8-byte Spill
movq %rdi, 168(%rsp) # 8-byte Spill
movabsq $4294967297, %r12 # imm = 0x100000001
movl %r8d, 8(%rsp) # 4-byte Spill
movl %r8d, %ebp
imull %ebp, %ebp
leaq (,%rbp,4), %r15
leaq 32(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movq %r15, %rdi
callq malloc
movq %rax, %rbx
movq %rax, %rdi
xorl %esi, %esi
movq %r15, %rdx
callq memset@PLT
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 40(%rsp), %rdi
callq hipEventCreate
movq 32(%rsp), %rdi
movq 168(%rsp), %rsi # 8-byte Reload
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq 176(%rsp), %rsi # 8-byte Reload
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
testl %r13d, %r13d
je .LBB6_1
# %bb.3:
movl 8(%rsp), %eax # 4-byte Reload
cltd
idivl %r13d
# kill: def $eax killed $eax def $rax
cmpl $1, %edx
sbbl $-1, %eax
movl %r13d, %r13d
imulq %r12, %r13
imulq %rax, %r12
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r12, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movl 8(%rsp), %r12d # 4-byte Reload
jne .LBB6_6
# %bb.4:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl %r12d, 12(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z12MatrixMulGPUPfS_S_i, %edi
jmp .LBB6_5
.LBB6_1:
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r12, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movl 8(%rsp), %r12d # 4-byte Reload
jne .LBB6_6
# %bb.2:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl %r12d, 12(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z18MatrixMulGPUSinglePfS_S_i, %edi
.LBB6_5:
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_6:
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 40(%rsp), %rdi
callq hipEventSynchronize
movq 48(%rsp), %rsi
movq 40(%rsp), %rdx
leaq 128(%rsp), %rdi
callq hipEventElapsedTime
movq 16(%rsp), %rsi
movq %rbx, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.1, %edi
testl %r12d, %r12d
je .LBB6_11
# %bb.7: # %.lr.ph.preheader.i
cmpl $1, %ebp
adcl $0, %ebp
xorl %eax, %eax
movaps .LCPI6_0(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
movsd .LCPI6_1(%rip), %xmm1 # xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB6_9: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movss (%r14,%rax,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss (%rbx,%rax,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
movaps %xmm2, %xmm4
subss %xmm3, %xmm4
andps %xmm0, %xmm4
cvtss2sd %xmm4, %xmm4
ucomisd %xmm1, %xmm4
ja .LBB6_10
# %bb.8: # in Loop: Header=BB6_9 Depth=1
incq %rax
cmpq %rax, %rbp
jne .LBB6_9
jmp .LBB6_11
.LBB6_10:
xorps %xmm0, %xmm0
cvtss2sd %xmm2, %xmm0
xorps %xmm1, %xmm1
cvtss2sd %xmm3, %xmm1
movl $.L.str, %edi
movb $2, %al
callq printf
movl $.Lstr, %edi
.LBB6_11: # %_Z11checkResultPfS_i.exit
callq puts@PLT
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movss 128(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z7GPUtestPfS_S_ii, .Lfunc_end6-_Z7GPUtestPfS_S_ii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z13computeMatrixi
.LCPI7_0:
.long 0x41200000 # float 10
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI7_1:
.quad 0x408f400000000000 # double 1000
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI7_2:
.long 0 # 0x0
.long 2 # 0x2
.long 4 # 0x4
.long 10 # 0xa
.text
.globl _Z13computeMatrixi
.p2align 4, 0x90
.type _Z13computeMatrixi,@function
_Z13computeMatrixi: # @_Z13computeMatrixi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $56, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edi, %ebx
movl $.Lstr.5, %edi
callq puts@PLT
movl $.L.str.7, %edi
movl %ebx, %esi
movl %ebx, %edx
xorl %eax, %eax
callq printf
movl %ebx, %r13d
imull %r13d, %r13d
leaq (,%r13,4), %r12
movq %r12, %rdi
callq malloc
movq %rax, %r14
movq %r12, %rdi
callq malloc
movq %rax, %r15
movq %r12, 8(%rsp) # 8-byte Spill
movq %r12, %rdi
callq malloc
movq %rax, %r12
movl $.L.str.8, %edi
movl $.L.str.9, %esi
callq fopen
movq %rax, 16(%rsp) # 8-byte Spill
testl %ebx, %ebx
je .LBB7_6
# %bb.1: # %.lr.ph.preheader.i
cmpl $1, %r13d
movq %r13, 24(%rsp) # 8-byte Spill
# kill: def $r13d killed $r13d killed $r13 def $r13
adcl $0, %r13d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB7_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
movss .LCPI7_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
divss %xmm1, %xmm0
movss %xmm0, (%r14,%rbp,4)
incq %rbp
cmpq %rbp, %r13
jne .LBB7_2
# %bb.3: # %_Z11initialDataPfi.exit
testl %ebx, %ebx
movq 24(%rsp), %rbp # 8-byte Reload
je .LBB7_6
# %bb.4: # %.lr.ph.preheader.i38
cmpl $1, %ebp
adcl $0, %ebp
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB7_5: # %.lr.ph.i41
# =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
divss .LCPI7_0(%rip), %xmm0
movss %xmm0, (%r15,%r13,4)
incq %r13
cmpq %r13, %rbp
jne .LBB7_5
.LBB7_6: # %_Z11initialDataPfi.exit45
xorl %ebp, %ebp
movq %r12, %rdi
xorl %esi, %esi
movq 8(%rsp), %rdx # 8-byte Reload
callq memset@PLT
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, 8(%rsp) # 8-byte Spill
testl %ebx, %ebx
movq 16(%rsp), %r13 # 8-byte Reload
jle .LBB7_13
# %bb.7: # %.preheader23.lr.ph.i
movl %ebx, %eax
leaq (,%rax,4), %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB7_8: # %.preheader23.i
# =>This Loop Header: Depth=1
# Child Loop BB7_9 Depth 2
# Child Loop BB7_10 Depth 3
movl %ebp, %esi
leaq (%r14,%rsi,4), %rsi
movq %rdx, %rdi
imulq %rax, %rdi
leaq (%r12,%rdi,4), %rdi
movq %r15, %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB7_9: # %.preheader.i
# Parent Loop BB7_8 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB7_10 Depth 3
movss (%rdi,%r9,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %r8, %r10
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB7_10: # Parent Loop BB7_8 Depth=1
# Parent Loop BB7_9 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rsi,%r11), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r10), %xmm1
addss %xmm1, %xmm0
addq $4, %r11
addq %rcx, %r10
cmpq %r11, %rcx
jne .LBB7_10
# %bb.11: # %._crit_edge.i
# in Loop: Header=BB7_9 Depth=2
movss %xmm0, (%rdi,%r9,4)
incq %r9
addq $4, %r8
cmpq %rax, %r9
jne .LBB7_9
# %bb.12: # %._crit_edge26.i
# in Loop: Header=BB7_8 Depth=1
incq %rdx
addl %ebx, %ebp
cmpq %rax, %rdx
jne .LBB7_8
.LBB7_13: # %_Z12MatrixMulCPUPfS_S_i.exit
callq _ZNSt6chrono3_V212system_clock3nowEv
subq 8(%rsp), %rax # 8-byte Folded Reload
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
imulq %rcx
movq %rdx, %rax
shrq $63, %rax
sarq $7, %rdx
addq %rax, %rdx
xorps %xmm0, %xmm0
cvtsi2sd %rdx, %xmm0
divsd .LCPI7_1(%rip), %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
movl $.L.str.10, %edi
movb $1, %al
callq printf
movl $.L.str.11, %esi
movq %r13, %rdi
movl %ebx, %edx
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq fprintf
movaps .LCPI7_2(%rip), %xmm0 # xmm0 = [0,2,4,10]
movaps %xmm0, 32(%rsp)
movabsq $107374182420, %rax # imm = 0x1900000014
movq %rax, 48(%rsp)
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB7_14: # =>This Inner Loop Header: Depth=1
movl 32(%rsp,%r13,4), %ebp
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movl %ebp, %ecx
movl %ebx, %r8d
callq _Z7GPUtestPfS_S_ii
cvtss2sd %xmm0, %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
movl $.L.str.12, %edi
movl %ebp, %esi
movb $1, %al
callq printf
movl $.L.str.13, %esi
movq 16(%rsp), %rdi # 8-byte Reload
movl %ebx, %edx
movl %ebp, %ecx
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq fprintf
incq %r13
cmpq $6, %r13
jne .LBB7_14
# %bb.15:
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq 16(%rsp), %rdi # 8-byte Reload
callq fclose
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp hipDeviceReset # TAILCALL
.Lfunc_end7:
.size _Z13computeMatrixi, .Lfunc_end7-_Z13computeMatrixi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z13transferTimesi
.LCPI8_0:
.long 0x41200000 # float 10
.text
.globl _Z13transferTimesi
.p2align 4, 0x90
.type _Z13transferTimesi,@function
_Z13transferTimesi: # @_Z13transferTimesi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $56, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edi, %r13d
movl $.Lstr.5, %edi
callq puts@PLT
movl $.L.str.14, %edi
movl %r13d, %esi
movl %r13d, %edx
xorl %eax, %eax
callq printf
movl $.L.str.15, %edi
movl $.L.str.9, %esi
callq fopen
movq %rax, %rbp
movl %r13d, %ebx
imull %ebx, %ebx
leaq (,%rbx,4), %r12
movl $0, 4(%rsp)
movq %r12, %rdi
callq malloc
movq %rax, %r14
movq %r12, %rdi
callq malloc
movq %rax, %r15
leaq 40(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movl %r13d, 28(%rsp) # 4-byte Spill
testl %r13d, %r13d
je .LBB8_6
# %bb.1: # %.lr.ph.preheader.i
movq %rbp, 48(%rsp) # 8-byte Spill
cmpl $1, %ebx
movl %ebx, %r13d
adcl $0, %r13d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB8_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
movss .LCPI8_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
divss %xmm1, %xmm0
movss %xmm0, (%r14,%rbp,4)
incq %rbp
cmpq %rbp, %r13
jne .LBB8_2
# %bb.3: # %_Z11initialDataPfi.exit
cmpl $0, 28(%rsp) # 4-byte Folded Reload
movq 48(%rsp), %rbp # 8-byte Reload
je .LBB8_6
# %bb.4: # %.lr.ph.preheader.i31
cmpl $1, %ebx
adcl $0, %ebx
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB8_5: # %.lr.ph.i34
# =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
divss .LCPI8_0(%rip), %xmm0
movss %xmm0, (%r15,%r13,4)
incq %r13
cmpq %r13, %rbx
jne .LBB8_5
.LBB8_6: # %_Z11initialDataPfi.exit38
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 40(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movq %r15, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %r13
movq %r13, %rdi
callq hipEventElapsedTime
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.16, %edi
movl 28(%rsp), %ebx # 4-byte Reload
movl %ebx, %esi
movl %ebx, %edx
movb $1, %al
callq printf
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.17, %esi
movq %rbp, %rdi
movl %ebx, %edx
movb $1, %al
callq fprintf
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 40(%rsp), %rsi
movq %r14, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rsi
movq %r15, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
movq %r13, %rdi
callq hipEventElapsedTime
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.18, %edi
movl %ebx, %esi
movl %ebx, %edx
movb $1, %al
callq printf
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.19, %esi
movq %rbp, %rdi
movl %ebx, %edx
movb $1, %al
callq fprintf
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %rbp, %rdi
callq fclose
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size _Z13transferTimesi, .Lfunc_end8-_Z13transferTimesi
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI9_0:
.long 100 # 0x64
.long 200 # 0xc8
.long 500 # 0x1f4
.long 1000 # 0x3e8
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $24, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $.L.str.8, %edi
movl $.L.str.20, %esi
callq fopen
movq %rax, %rbx
movl $.L.str.15, %edi
movl $.L.str.20, %esi
callq fopen
movq %rax, %r14
movl $.L.str.21, %edi
movl $36, %esi
movl $1, %edx
movq %rbx, %rcx
callq fwrite@PLT
movl $.L.str.22, %edi
movl $21, %esi
movl $1, %edx
movq %r14, %rcx
callq fwrite@PLT
movq %rbx, %rdi
callq fclose
movq %r14, %rdi
callq fclose
movaps .LCPI9_0(%rip), %xmm0 # xmm0 = [100,200,500,1000]
movaps %xmm0, (%rsp)
movabsq $21474836481500, %rax # imm = 0x1388000005DC
movq %rax, 16(%rsp)
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB9_1: # =>This Inner Loop Header: Depth=1
movl (%rsp,%r14,4), %ebx
movl %ebx, %edi
callq _Z13computeMatrixi
movl %ebx, %edi
callq _Z13transferTimesi
incq %r14
cmpq $6, %r14
jne .LBB9_1
# %bb.2:
movl $.Lstr.5, %edi
callq puts@PLT
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end9:
.size main, .Lfunc_end9-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB10_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB10_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12MatrixMulGPUPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18MatrixMulGPUSinglePfS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end10:
.size __hip_module_ctor, .Lfunc_end10-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB11_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB11_2:
retq
.Lfunc_end11:
.size __hip_module_dtor, .Lfunc_end11-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12MatrixMulGPUPfS_S_i,@object # @_Z12MatrixMulGPUPfS_S_i
.section .rodata,"a",@progbits
.globl _Z12MatrixMulGPUPfS_S_i
.p2align 3, 0x0
_Z12MatrixMulGPUPfS_S_i:
.quad _Z27__device_stub__MatrixMulGPUPfS_S_i
.size _Z12MatrixMulGPUPfS_S_i, 8
.type _Z18MatrixMulGPUSinglePfS_S_i,@object # @_Z18MatrixMulGPUSinglePfS_S_i
.globl _Z18MatrixMulGPUSinglePfS_S_i
.p2align 3, 0x0
_Z18MatrixMulGPUSinglePfS_S_i:
.quad _Z33__device_stub__MatrixMulGPUSinglePfS_S_i
.size _Z18MatrixMulGPUSinglePfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CPU %f GPU %f "
.size .L.str, 15
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%f,"
.size .L.str.4, 4
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%dx%d matrix multiplication.\n\n"
.size .L.str.7, 31
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "machineProblem3.csv"
.size .L.str.8, 20
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "a"
.size .L.str.9, 2
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "The CPU took %f to perform the computation.\n\n"
.size .L.str.10, 46
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "%d,CPU,0,%f\n"
.size .L.str.11, 13
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "The GPU took %f to perform the computation with block size %d.\n"
.size .L.str.12, 64
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "%d,GPU,%d,%f\n"
.size .L.str.13, 14
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Currently transfering between %dx%d matrixs\n"
.size .L.str.14, 45
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "machineProblem3_transfer.csv"
.size .L.str.15, 29
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "Transfered %dx%d matrix from CPU to GPU in %fms\n"
.size .L.str.16, 49
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "%d,0,%f\n"
.size .L.str.17, 9
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "Transfered %dx%d matrix from GPU to CPU in %fms\n"
.size .L.str.18, 49
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "%d,1,%f\n"
.size .L.str.19, 9
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "w"
.size .L.str.20, 2
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "matrixSize,processor,blockSize,time\n"
.size .L.str.21, 37
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz "matrixSize,case,time\n"
.size .L.str.22, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12MatrixMulGPUPfS_S_i"
.size .L__unnamed_1, 24
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z18MatrixMulGPUSinglePfS_S_i"
.size .L__unnamed_2, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Arrays do not match.\n"
.size .Lstr, 22
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Test PASSED\n"
.size .Lstr.1, 13
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\b]"
.size .Lstr.2, 3
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "------------------------------------------------------------------------\n"
.size .Lstr.5, 74
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__MatrixMulGPUPfS_S_i
.addrsig_sym _Z33__device_stub__MatrixMulGPUSinglePfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12MatrixMulGPUPfS_S_i
.addrsig_sym _Z18MatrixMulGPUSinglePfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime_api.h>
#include <math.h>
#include "link.h"
using namespace std;
__global__ void link(float **var, int **intVar){
const int npcn = 2000;
int nseg = *intVar[7];
int *bin = intVar[12];
int *list = intVar[13];
int *bnei = intVar[14];
int nxbin = *intVar[15];
int nybin = *intVar[16];
int nzbin = *intVar[17];
int *bnum = intVar[31];
int *potCon = intVar[32];
int *potConSize = intVar[33];
int mi = blockIdx.x;
int tid = threadIdx.x;
int miBin = bnum[mi];
int nextBin = bnei[miBin + tid*nxbin*nybin*nzbin];
int nextTot = bin[nextBin];
int nj, i, pos;
if (tid == 0){
potConSize[mi] = 0;
}
__syncthreads();
for (i = 0; i < nextTot; i++){
nj = list[nextBin + i*nxbin*nybin*nzbin];
// skip when segments are connected
if (mi >= nj){
continue;
}
if ((mi - (mi / nseg)*nseg) != 0 && nj == mi - 1){
continue;
}
if ((nj - (nj / nseg)*nseg) != 0 && mi == nj - 1){
continue;
}
if ((mi - (mi / nseg)*nseg) != nseg - 1 && nj == mi + 1){
continue;
}
if ((nj - (nj / nseg)*nseg) != nseg - 1 && mi == nj + 1){
continue;
}
//printf("link mi nj %4d %4d\n", mi, nj);
pos = atomicAdd(potConSize + mi, 1);
if (pos >= npcn - 1) printf("allocate more space for potCon pos %4d\n", pos);
potCon[mi * npcn + pos] = nj;
}
} | .file "tmpxft_0018884f_00000000-6_link.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z4linkPPfPPiPPfPPi
.type _Z27__device_stub__Z4linkPPfPPiPPfPPi, @function
_Z27__device_stub__Z4linkPPfPPiPPfPPi:
.LFB2081:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4linkPPfPPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z27__device_stub__Z4linkPPfPPiPPfPPi, .-_Z27__device_stub__Z4linkPPfPPiPPfPPi
.globl _Z4linkPPfPPi
.type _Z4linkPPfPPi, @function
_Z4linkPPfPPi:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z4linkPPfPPiPPfPPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z4linkPPfPPi, .-_Z4linkPPfPPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4linkPPfPPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4linkPPfPPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime_api.h>
#include <math.h>
#include "link.h"
using namespace std;
__global__ void link(float **var, int **intVar){
const int npcn = 2000;
int nseg = *intVar[7];
int *bin = intVar[12];
int *list = intVar[13];
int *bnei = intVar[14];
int nxbin = *intVar[15];
int nybin = *intVar[16];
int nzbin = *intVar[17];
int *bnum = intVar[31];
int *potCon = intVar[32];
int *potConSize = intVar[33];
int mi = blockIdx.x;
int tid = threadIdx.x;
int miBin = bnum[mi];
int nextBin = bnei[miBin + tid*nxbin*nybin*nzbin];
int nextTot = bin[nextBin];
int nj, i, pos;
if (tid == 0){
potConSize[mi] = 0;
}
__syncthreads();
for (i = 0; i < nextTot; i++){
nj = list[nextBin + i*nxbin*nybin*nzbin];
// skip when segments are connected
if (mi >= nj){
continue;
}
if ((mi - (mi / nseg)*nseg) != 0 && nj == mi - 1){
continue;
}
if ((nj - (nj / nseg)*nseg) != 0 && mi == nj - 1){
continue;
}
if ((mi - (mi / nseg)*nseg) != nseg - 1 && nj == mi + 1){
continue;
}
if ((nj - (nj / nseg)*nseg) != nseg - 1 && mi == nj + 1){
continue;
}
//printf("link mi nj %4d %4d\n", mi, nj);
pos = atomicAdd(potConSize + mi, 1);
if (pos >= npcn - 1) printf("allocate more space for potCon pos %4d\n", pos);
potCon[mi * npcn + pos] = nj;
}
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime_api.h>
#include <math.h>
#include "link.h"
using namespace std;
__global__ void link(float **var, int **intVar){
const int npcn = 2000;
int nseg = *intVar[7];
int *bin = intVar[12];
int *list = intVar[13];
int *bnei = intVar[14];
int nxbin = *intVar[15];
int nybin = *intVar[16];
int nzbin = *intVar[17];
int *bnum = intVar[31];
int *potCon = intVar[32];
int *potConSize = intVar[33];
int mi = blockIdx.x;
int tid = threadIdx.x;
int miBin = bnum[mi];
int nextBin = bnei[miBin + tid*nxbin*nybin*nzbin];
int nextTot = bin[nextBin];
int nj, i, pos;
if (tid == 0){
potConSize[mi] = 0;
}
__syncthreads();
for (i = 0; i < nextTot; i++){
nj = list[nextBin + i*nxbin*nybin*nzbin];
// skip when segments are connected
if (mi >= nj){
continue;
}
if ((mi - (mi / nseg)*nseg) != 0 && nj == mi - 1){
continue;
}
if ((nj - (nj / nseg)*nseg) != 0 && mi == nj - 1){
continue;
}
if ((mi - (mi / nseg)*nseg) != nseg - 1 && nj == mi + 1){
continue;
}
if ((nj - (nj / nseg)*nseg) != nseg - 1 && mi == nj + 1){
continue;
}
//printf("link mi nj %4d %4d\n", mi, nj);
pos = atomicAdd(potConSize + mi, 1);
if (pos >= npcn - 1) printf("allocate more space for potCon pos %4d\n", pos);
potCon[mi * npcn + pos] = nj;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime_api.h>
#include <math.h>
#include "link.h"
using namespace std;
__global__ void link(float **var, int **intVar){
const int npcn = 2000;
int nseg = *intVar[7];
int *bin = intVar[12];
int *list = intVar[13];
int *bnei = intVar[14];
int nxbin = *intVar[15];
int nybin = *intVar[16];
int nzbin = *intVar[17];
int *bnum = intVar[31];
int *potCon = intVar[32];
int *potConSize = intVar[33];
int mi = blockIdx.x;
int tid = threadIdx.x;
int miBin = bnum[mi];
int nextBin = bnei[miBin + tid*nxbin*nybin*nzbin];
int nextTot = bin[nextBin];
int nj, i, pos;
if (tid == 0){
potConSize[mi] = 0;
}
__syncthreads();
for (i = 0; i < nextTot; i++){
nj = list[nextBin + i*nxbin*nybin*nzbin];
// skip when segments are connected
if (mi >= nj){
continue;
}
if ((mi - (mi / nseg)*nseg) != 0 && nj == mi - 1){
continue;
}
if ((nj - (nj / nseg)*nseg) != 0 && mi == nj - 1){
continue;
}
if ((mi - (mi / nseg)*nseg) != nseg - 1 && nj == mi + 1){
continue;
}
if ((nj - (nj / nseg)*nseg) != nseg - 1 && mi == nj + 1){
continue;
}
//printf("link mi nj %4d %4d\n", mi, nj);
pos = atomicAdd(potConSize + mi, 1);
if (pos >= npcn - 1) printf("allocate more space for potCon pos %4d\n", pos);
potCon[mi * npcn + pos] = nj;
}
} | .text
.file "link.hip"
.globl _Z19__device_stub__linkPPfPPi # -- Begin function _Z19__device_stub__linkPPfPPi
.p2align 4, 0x90
.type _Z19__device_stub__linkPPfPPi,@function
_Z19__device_stub__linkPPfPPi: # @_Z19__device_stub__linkPPfPPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4linkPPfPPi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z19__device_stub__linkPPfPPi, .Lfunc_end0-_Z19__device_stub__linkPPfPPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4linkPPfPPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4linkPPfPPi,@object # @_Z4linkPPfPPi
.section .rodata,"a",@progbits
.globl _Z4linkPPfPPi
.p2align 3, 0x0
_Z4linkPPfPPi:
.quad _Z19__device_stub__linkPPfPPi
.size _Z4linkPPfPPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4linkPPfPPi"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__linkPPfPPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4linkPPfPPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018884f_00000000-6_link.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z4linkPPfPPiPPfPPi
.type _Z27__device_stub__Z4linkPPfPPiPPfPPi, @function
_Z27__device_stub__Z4linkPPfPPiPPfPPi:
.LFB2081:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4linkPPfPPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z27__device_stub__Z4linkPPfPPiPPfPPi, .-_Z27__device_stub__Z4linkPPfPPiPPfPPi
.globl _Z4linkPPfPPi
.type _Z4linkPPfPPi, @function
_Z4linkPPfPPi:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z4linkPPfPPiPPfPPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z4linkPPfPPi, .-_Z4linkPPfPPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4linkPPfPPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4linkPPfPPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "link.hip"
.globl _Z19__device_stub__linkPPfPPi # -- Begin function _Z19__device_stub__linkPPfPPi
.p2align 4, 0x90
.type _Z19__device_stub__linkPPfPPi,@function
_Z19__device_stub__linkPPfPPi: # @_Z19__device_stub__linkPPfPPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4linkPPfPPi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z19__device_stub__linkPPfPPi, .Lfunc_end0-_Z19__device_stub__linkPPfPPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4linkPPfPPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4linkPPfPPi,@object # @_Z4linkPPfPPi
.section .rodata,"a",@progbits
.globl _Z4linkPPfPPi
.p2align 3, 0x0
_Z4linkPPfPPi:
.quad _Z19__device_stub__linkPPfPPi
.size _Z4linkPPfPPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4linkPPfPPi"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__linkPPfPPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4linkPPfPPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <string.h>
#include <sys/types.h>
#include <sys/time.h>
#include <cuda.h>
#define BW 16 // Block Width
#define BH 32 // Block Height
#define COUNT 0
// Kernel Function handles first nested for loop
__global__ void kernelBlur(int *d_Rnew, int *d_Gnew, int *d_Bnew, int *d_R, int *d_G, int *d_B, int rowsize, int colsize) {
// Set-up
int row = blockIdx.y*blockDim.y + threadIdx.y;
int col = blockIdx.x*blockDim.x + threadIdx.x;
// Run Some Calculations
if (col < colsize && row < rowsize) {
if (row != 0 && row != (rowsize-1) && col != 0 && col != (colsize-1)) {
d_Rnew[row * colsize + col] = (d_R[(row + 1) * colsize + col]+d_R[(row - 1) * colsize + col]+d_R[row * colsize + (col + 1)]+d_R[row * colsize + (col - 1)])/4;
d_Gnew[row * colsize + col] = (d_G[(row + 1) * colsize + col]+d_G[(row - 1) * colsize + col]+d_G[row * colsize + (col + 1)]+d_G[row * colsize + (col - 1)])/4;
d_Bnew[row * colsize + col] = (d_B[(row + 1) * colsize + col]+d_B[(row - 1) * colsize + col]+d_B[row * colsize + (col + 1)]+d_B[row * colsize + (col - 1)])/4;
}
else if (row == 0 && col != 0 && col != (colsize-1)){
d_Rnew[row * colsize + col] = (d_R[(row + 1) * colsize + col]+d_R[row * colsize + (col + 1)]+d_R[row * colsize + (col - 1)])/3;
d_Gnew[row * colsize + col] = (d_G[(row + 1) * colsize + col]+d_G[row * colsize + (col + 1)]+d_G[row * colsize + (col - 1)])/3;
d_Bnew[row * colsize + col] = (d_B[(row + 1) * colsize + col]+d_B[row * colsize + (col + 1)]+d_B[row * colsize + (col - 1)])/3;
}
else if (row == (rowsize-1) && col != 0 && col != (colsize-1)){
d_Rnew[row * colsize + col] = (d_R[(row - 1) * colsize + col]+d_R[row * colsize + (col + 1)]+d_R[row * colsize + (col - 1)])/3;
d_Gnew[row * colsize + col] = (d_G[(row - 1) * colsize + col]+d_G[row * colsize + (col + 1)]+d_G[row * colsize + (col - 1)])/3;
d_Bnew[row * colsize + col] = (d_B[(row - 1) * colsize + col]+d_B[row * colsize + (col + 1)]+d_B[row * colsize + (col - 1)])/3;
}
else if (col == 0 && row != 0 && row != (rowsize-1)){
d_Rnew[row * colsize + col] = (d_R[(row + 1) * colsize + col]+d_R[(row - 1) * colsize + col]+d_R[row * colsize + (col + 1)])/3;
d_Gnew[row * colsize + col] = (d_G[(row + 1) * colsize + col]+d_G[(row - 1) * colsize + col]+d_G[row * colsize + (col + 1)])/3;
d_Bnew[row * colsize + col] = (d_B[(row + 1) * colsize + col]+d_B[(row - 1) * colsize + col]+d_B[row * colsize + (col + 1)])/3;
}
else if (col == (colsize-1) && row != 0 && row != (rowsize-1)){
d_Rnew[row * colsize + col] = (d_R[(row + 1) * colsize + col]+d_R[(row - 1) * colsize + col]+d_R[row * colsize + (col + 1)])/3;
d_Gnew[row * colsize + col] = (d_G[(row + 1) * colsize + col]+d_G[(row - 1) * colsize + col]+d_G[row * colsize + (col + 1)])/3;
d_Bnew[row * colsize + col] = (d_B[(row + 1) * colsize + col]+d_B[(row - 1) * colsize + col]+d_B[row * colsize + (col + 1)])/3;
}
else if (row==0 &&col==0){
d_Rnew[row * colsize + col] = (d_R[row * colsize + (col + 1)]+d_R[(row + 1) * colsize + col])/2;
d_Gnew[row * colsize + col] = (d_G[row * colsize + (col + 1)]+d_G[(row + 1) * colsize + col])/2;
d_Bnew[row * colsize + col] = (d_B[row * colsize + (col + 1)]+d_B[(row + 1) * colsize + col])/2;
}
else if (row==0 &&col==(colsize-1)){
d_Rnew[row * colsize + col] = (d_R[row * colsize + (col - 1)]+d_R[(row + 1) * colsize + col])/2;
d_Gnew[row * colsize + col] = (d_G[row * colsize + (col - 1)]+d_G[(row + 1) * colsize + col])/2;
d_Bnew[row * colsize + col] = (d_B[row * colsize + (col - 1)]+d_B[(row + 1) * colsize + col])/2;
}
else if (row==(rowsize-1) &&col==0){
d_Rnew[row * colsize + col] = (d_R[row * colsize + (col + 1)]+d_R[(row - 1) * colsize + col])/2;
d_Gnew[row * colsize + col] = (d_G[row * colsize + (col + 1)]+d_G[(row - 1) * colsize + col])/2;
d_Bnew[row * colsize + col] = (d_B[row * colsize + (col + 1)]+d_B[(row - 1) * colsize + col])/2;
}
else if (row==(rowsize-1) &&col==(colsize-1)){
d_Rnew[row * colsize + col] = (d_R[row * colsize + (col - 1)]+d_R[(row - 1) * colsize + col])/2;
d_Gnew[row * colsize + col] = (d_G[row * colsize + (col - 1)]+d_G[(row - 1) * colsize + col])/2;
d_Bnew[row * colsize + col] = (d_B[row * colsize + (col - 1)]+d_B[(row - 1) * colsize + col])/2;
}
}
}
// Kernel Function handles second nested for loop updates RGB values to new calculated values
__global__ void kernelCopy(int *d_Rnew, int *d_Gnew, int *d_Bnew, int *d_R, int *d_G, int *d_B, int rowsize, int colsize) {
// Set-up
int row = blockIdx.y*blockDim.y+threadIdx.y;
int col = blockIdx.x*blockDim.x+threadIdx.x;
if (col < colsize && row < rowsize) {
d_R[row * colsize + col] = d_Rnew[row * colsize + col];
d_G[row * colsize + col] = d_Gnew[row * colsize + col];
d_B[row * colsize + col] = d_Bnew[row * colsize + col];
}
}
void performBlurs(int *h_R, int *h_G, int *h_B, int *h_Rnew, int *h_Gnew, int *h_Bnew, int rowsize, int colsize, int nblurs) {
// Assign Memory on GPU
// Step 1 Assign Memory on GPU
int k;
int sizei = sizeof(int)*rowsize*colsize;
int *d_R, *d_G, *d_B, *d_Rnew, *d_Gnew, *d_Bnew;
struct timeval tim;
gettimeofday(&tim, NULL);
double t1=tim.tv_sec+(tim.tv_usec/1000000.0);
cudaMalloc((void **)&d_R,sizei);
cudaMalloc((void **)&d_G,sizei);
cudaMalloc((void **)&d_B,sizei);
cudaMalloc((void **)&d_Rnew,sizei);
cudaMalloc((void **)&d_Gnew,sizei);
cudaMalloc((void **)&d_Bnew,sizei);
gettimeofday(&tim, NULL);
double t2=tim.tv_sec+(tim.tv_usec/1000000.0);
printf("Assigning Memory to GPU > %.6lf seconds elapsed\n", t2-t1);
// Transfer to Device
gettimeofday(&tim, NULL);
t1=tim.tv_sec+(tim.tv_usec/1000000.0);
cudaMemcpy(d_R, h_R, sizei, cudaMemcpyHostToDevice);
cudaMemcpy(d_G, h_G, sizei, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, sizei, cudaMemcpyHostToDevice);
cudaMemcpy(d_Rnew, h_Rnew, sizei, cudaMemcpyHostToDevice);
cudaMemcpy(d_Gnew, h_Gnew, sizei, cudaMemcpyHostToDevice);
cudaMemcpy(d_Bnew, h_Bnew, sizei, cudaMemcpyHostToDevice);
t2=tim.tv_sec+(tim.tv_usec/1000000.0);
printf("Transferring from host to device memory > %.6lf seconds elapsed\n", t2-t1);
// Set up Blocks
dim3 dimGrid(ceil(colsize/(float)BW), ceil(rowsize/(float)BH), 1);
dim3 dimBlock(BW,BH);
nblurs = 10; // Modify as Needed
gettimeofday(&tim, NULL);
t1=tim.tv_sec+(tim.tv_usec/1000000.0);
for (k = 0; k < nblurs; ++k) {
kernelBlur<<<dimGrid, dimBlock>>>(d_Rnew, d_Gnew, d_Bnew, d_R, d_G, d_B, rowsize, colsize);
kernelCopy<<<dimGrid, dimBlock>>>(d_Rnew, d_Gnew, d_Bnew, d_R, d_G, d_B, rowsize, colsize);
}
t2=tim.tv_sec+(tim.tv_usec/1000000.0);
printf("Blurring Operation > %.6lf seconds elapsed\n", t2-t1);
// Step 4 output copied from GPU to Host get the RGB values
cudaMemcpy(h_R, d_R, sizei, cudaMemcpyDeviceToHost);
cudaMemcpy(h_G, d_G, sizei, cudaMemcpyDeviceToHost);
cudaMemcpy(h_B, d_B, sizei, cudaMemcpyDeviceToHost);
// Step 5 Free Memory
cudaFree(d_R); cudaFree(d_G); cudaFree(d_B); cudaFree(d_Rnew); cudaFree(d_Gnew); cudaFree(d_Bnew);
}
int main (int argc, const char * argv[]) {
// Assignment of initial Variables
static int const maxlen = 200, rowsize = 521, colsize = 428, linelen = 12;
static char str[200], lines[5][200];
FILE *fp, *fout;
int nlines = 0;
unsigned int h1, h2, h3;
char *sptr;
// Define Host Arrays
int *h_R, *h_G, *h_B;
int *h_Rnew, *h_Gnew, *h_Bnew;
int size = sizeof(int) * rowsize * colsize;
h_R = (int *)malloc(size);
h_G = (int *)malloc(size);
h_B = (int *)malloc(size);
h_Rnew = (int *)malloc(size);
h_Gnew = (int *)malloc(size);
h_Bnew = (int *)malloc(size);
// Allocate Overall Size of ROw
int row = 0, col = 0, nblurs = 0, lineno=0, k;
// Read input file
struct timeval tim;
gettimeofday(&tim, NULL);
double t1=tim.tv_sec+(tim.tv_usec/1000000.0);
fp = fopen("sample.ps", "r");
while(! feof(fp))
{
fscanf(fp, "\n%[^\n]", str);
if (nlines < 5) {strcpy((char *)lines[nlines++],(char *)str);}
else{
for (sptr=&str[0];*sptr != '\0';sptr+=6){
sscanf(sptr,"%2x",&h1);
sscanf(sptr+2,"%2x",&h2);
sscanf(sptr+4,"%2x",&h3);
if (col==colsize){
col = 0;
row++;
}
if (row < rowsize) {
h_R[row * colsize + col] = h1;
h_G[row * colsize + col] = h2;
h_B[row * colsize + col] = h3;
}
col++;
}
}
}
fclose(fp);
gettimeofday(&tim, NULL);
double t2=tim.tv_sec+(tim.tv_usec/1000000.0);
printf("Reading Input File > %.6lf seconds elapsed\n", t2-t1);
// Run Code
performBlurs(h_R, h_G, h_B, h_Rnew, h_Gnew, h_Bnew, rowsize, colsize, nblurs);
gettimeofday(&tim, NULL);
t1=tim.tv_sec+(tim.tv_usec/1000000.0);
fout= fopen("sampleBlurCU.ps", "w");
for (k=0;k<nlines;k++) fprintf(fout,"\n%s", lines[k]);
fprintf(fout,"\n");
for(row=0;row<rowsize;row++){
for (col=0;col<colsize;col++){
fprintf(fout,"%02x%02x%02x",h_R[row * colsize + col],h_G[row * colsize + col],h_B[row * colsize + col]);
lineno++;
if (lineno==linelen){
fprintf(fout,"\n");
lineno = 0;
}
}
}
gettimeofday(&tim, NULL);
t2=tim.tv_sec+(tim.tv_usec/1000000.0);
printf("Outputting File > %.6lf seconds elapsed\n", t2-t1);
fclose(fout);
return 0;
} | .file "tmpxft_001388d5_00000000-6_blurCUDA.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z10kernelBlurPiS_S_S_S_S_iiPiS_S_S_S_S_ii
.type _Z42__device_stub__Z10kernelBlurPiS_S_S_S_S_iiPiS_S_S_S_S_ii, @function
_Z42__device_stub__Z10kernelBlurPiS_S_S_S_S_iiPiS_S_S_S_S_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10kernelBlurPiS_S_S_S_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z42__device_stub__Z10kernelBlurPiS_S_S_S_S_iiPiS_S_S_S_S_ii, .-_Z42__device_stub__Z10kernelBlurPiS_S_S_S_S_iiPiS_S_S_S_S_ii
.globl _Z10kernelBlurPiS_S_S_S_S_ii
.type _Z10kernelBlurPiS_S_S_S_S_ii, @function
_Z10kernelBlurPiS_S_S_S_S_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z42__device_stub__Z10kernelBlurPiS_S_S_S_S_iiPiS_S_S_S_S_ii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z10kernelBlurPiS_S_S_S_S_ii, .-_Z10kernelBlurPiS_S_S_S_S_ii
.globl _Z42__device_stub__Z10kernelCopyPiS_S_S_S_S_iiPiS_S_S_S_S_ii
.type _Z42__device_stub__Z10kernelCopyPiS_S_S_S_S_iiPiS_S_S_S_S_ii, @function
_Z42__device_stub__Z10kernelCopyPiS_S_S_S_S_iiPiS_S_S_S_S_ii:
.LFB2085:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10kernelCopyPiS_S_S_S_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z42__device_stub__Z10kernelCopyPiS_S_S_S_S_iiPiS_S_S_S_S_ii, .-_Z42__device_stub__Z10kernelCopyPiS_S_S_S_S_iiPiS_S_S_S_S_ii
.globl _Z10kernelCopyPiS_S_S_S_S_ii
.type _Z10kernelCopyPiS_S_S_S_S_ii, @function
_Z10kernelCopyPiS_S_S_S_S_ii:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z42__device_stub__Z10kernelCopyPiS_S_S_S_S_iiPiS_S_S_S_S_ii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z10kernelCopyPiS_S_S_S_S_ii, .-_Z10kernelCopyPiS_S_S_S_S_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Assigning Memory to GPU > %.6lf seconds elapsed\n"
.align 8
.LC2:
.string "Transferring from host to device memory > %.6lf seconds elapsed\n"
.align 8
.LC8:
.string "Blurring Operation > %.6lf seconds elapsed\n"
.text
.globl _Z12performBlursPiS_S_S_S_S_iii
.type _Z12performBlursPiS_S_S_S_S_iii, @function
_Z12performBlursPiS_S_S_S_S_iii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $168, %rsp
.cfi_def_cfa_offset 224
movq %rdi, %r15
movq %rsi, %r14
movq %rdx, 8(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 32(%rsp)
movq %r9, 40(%rsp)
movl 224(%rsp), %r12d
movl 232(%rsp), %r13d
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 128(%rsp), %rbx
movl $0, %esi
movq %rbx, %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 136(%rsp), %xmm0
divsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 128(%rsp), %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, 16(%rsp)
movl %r12d, %ebp
imull %r13d, %ebp
sall $2, %ebp
movslq %ebp, %rbp
leaq 56(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 96(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $0, %esi
movq %rbx, %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 136(%rsp), %xmm0
divsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 128(%rsp), %xmm1
addsd %xmm1, %xmm0
subsd 16(%rsp), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %esi
movq %rbx, %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 136(%rsp), %xmm0
divsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 128(%rsp), %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, 16(%rsp)
movl $1, %ecx
movq %rbp, %rdx
movq %r15, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r14, %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq 8(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq 24(%rsp), %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq 32(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq 40(%rsp), %rsi
movq 96(%rsp), %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 136(%rsp), %xmm0
divsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 128(%rsp), %xmm1
addsd %xmm1, %xmm0
subsd 16(%rsp), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %r12d, %xmm0
mulss .LC3(%rip), %xmm0
movaps %xmm0, %xmm1
movss .LC9(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC4(%rip), %xmm4
ucomiss %xmm2, %xmm4
jbe .L20
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm1
movss .LC6(%rip), %xmm4
andps %xmm4, %xmm1
addss %xmm2, %xmm1
andnps %xmm0, %xmm3
orps %xmm3, %xmm1
.L20:
pxor %xmm0, %xmm0
cvtsi2ssl %r13d, %xmm0
mulss .LC7(%rip), %xmm0
movaps %xmm0, %xmm4
movss .LC9(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC4(%rip), %xmm5
ucomiss %xmm2, %xmm5
jbe .L21
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm4
movss .LC6(%rip), %xmm5
andps %xmm5, %xmm4
addss %xmm2, %xmm4
andnps %xmm0, %xmm3
orps %xmm3, %xmm4
.L21:
cvttss2siq %xmm4, %rax
movl %eax, 104(%rsp)
cvttss2siq %xmm1, %rax
movl %eax, 108(%rsp)
movl $1, 112(%rsp)
movl $16, 116(%rsp)
movl $32, 120(%rsp)
movl $1, 124(%rsp)
leaq 128(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 136(%rsp), %xmm0
divsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 128(%rsp), %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, 16(%rsp)
movl $10, %ebx
jmp .L24
.L29:
pushq %r13
.cfi_def_cfa_offset 232
pushq %r12
.cfi_def_cfa_offset 240
movq 88(%rsp), %r9
movq 80(%rsp), %r8
movq 72(%rsp), %rcx
movq 112(%rsp), %rdx
movq 104(%rsp), %rsi
movq 96(%rsp), %rdi
call _Z42__device_stub__Z10kernelBlurPiS_S_S_S_S_iiPiS_S_S_S_S_ii
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L22
.L23:
subl $1, %ebx
je .L28
.L24:
movl 124(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 116(%rsp), %rdx
movq 104(%rsp), %rdi
movl 112(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L22:
movl 124(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 116(%rsp), %rdx
movq 104(%rsp), %rdi
movl 112(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L23
pushq %r13
.cfi_def_cfa_offset 232
pushq %r12
.cfi_def_cfa_offset 240
movq 88(%rsp), %r9
movq 80(%rsp), %r8
movq 72(%rsp), %rcx
movq 112(%rsp), %rdx
movq 104(%rsp), %rsi
movq 96(%rsp), %rdi
call _Z42__device_stub__Z10kernelCopyPiS_S_S_S_S_iiPiS_S_S_S_S_ii
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L23
.L28:
pxor %xmm0, %xmm0
cvtsi2sdq 136(%rsp), %xmm0
divsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 128(%rsp), %xmm1
addsd %xmm1, %xmm0
subsd 16(%rsp), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 56(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 64(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 72(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z12performBlursPiS_S_S_S_S_iii, .-_Z12performBlursPiS_S_S_S_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC10:
.string "r"
.LC11:
.string "sample.ps"
.LC12:
.string "\n%[^\n]"
.LC13:
.string "%2x"
.section .rodata.str1.8
.align 8
.LC14:
.string "Reading Input File > %.6lf seconds elapsed\n"
.section .rodata.str1.1
.LC15:
.string "w"
.LC16:
.string "sampleBlurCU.ps"
.LC17:
.string "\n%s"
.LC18:
.string "\n"
.LC19:
.string "%02x%02x%02x"
.section .rodata.str1.8
.align 8
.LC20:
.string "Outputting File > %.6lf seconds elapsed\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl $891952, %edi
call malloc@PLT
movq %rax, 8(%rsp)
movl $891952, %edi
call malloc@PLT
movq %rax, 16(%rsp)
movl $891952, %edi
call malloc@PLT
movq %rax, 24(%rsp)
movl $891952, %edi
call malloc@PLT
movq %rax, 48(%rsp)
movl $891952, %edi
call malloc@PLT
movq %rax, 56(%rsp)
movl $891952, %edi
call malloc@PLT
movq %rax, %rbp
leaq 96(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 104(%rsp), %xmm0
divsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 96(%rsp), %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, 64(%rsp)
leaq .LC10(%rip), %rsi
leaq .LC11(%rip), %rdi
call fopen@PLT
movq %rax, 32(%rsp)
movl $0, %r12d
movl $0, %r14d
movl $0, %ebx
leaq _ZZ4mainE3str(%rip), %r15
leaq .LC13(%rip), %r13
movq %rbp, 72(%rsp)
.L32:
movq 32(%rsp), %rdi
call feof@PLT
movl %eax, 44(%rsp)
testl %eax, %eax
jne .L53
movq %r15, %rdx
leaq .LC12(%rip), %rsi
movq 32(%rsp), %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $4, %ebx
jg .L54
leal 1(%rbx), %ebp
movslq %ebx, %rbx
leaq (%rbx,%rbx,4), %rax
leaq (%rax,%rax,4), %rax
salq $3, %rax
movl $1000, %edx
cmpq %rdx, %rax
cmovnb %rax, %rdx
subq %rax, %rdx
leaq _ZZ4mainE5lines(%rip), %rsi
leaq (%rax,%rsi), %rdi
movq %r15, %rsi
call __strcpy_chk@PLT
movl %ebp, %ebx
jmp .L32
.L54:
leaq _ZZ4mainE3str(%rip), %rbp
cmpb $0, (%r15)
jne .L34
jmp .L32
.L55:
addl $1, %r14d
movl 44(%rsp), %r12d
jmp .L36
.L37:
addl $1, %r12d
addq $6, %rbp
cmpb $0, 0(%rbp)
je .L32
.L34:
leaq 84(%rsp), %rdx
movq %r13, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_sscanf@PLT
leaq 88(%rsp), %rdx
leaq 2(%rbp), %rdi
movq %r13, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
leaq 92(%rsp), %rdx
leaq 4(%rbp), %rdi
movq %r13, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
cmpl $428, %r12d
je .L55
.L36:
cmpl $520, %r14d
jg .L37
imull $428, %r14d, %eax
addl %r12d, %eax
cltq
movl 84(%rsp), %edx
movq 8(%rsp), %rsi
movl %edx, (%rsi,%rax,4)
movl 88(%rsp), %edx
movq 16(%rsp), %rsi
movl %edx, (%rsi,%rax,4)
movl 92(%rsp), %edx
movq 24(%rsp), %rsi
movl %edx, (%rsi,%rax,4)
jmp .L37
.L53:
movq 72(%rsp), %rbp
movq 32(%rsp), %rdi
call fclose@PLT
leaq 96(%rsp), %r12
movl $0, %esi
movq %r12, %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 104(%rsp), %xmm0
divsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 96(%rsp), %xmm1
addsd %xmm1, %xmm0
subsd 64(%rsp), %xmm0
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
subq $8, %rsp
.cfi_def_cfa_offset 200
pushq $0
.cfi_def_cfa_offset 208
pushq $428
.cfi_def_cfa_offset 216
pushq $521
.cfi_def_cfa_offset 224
movq %rbp, %r9
movq 88(%rsp), %r8
movq 80(%rsp), %rcx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z12performBlursPiS_S_S_S_S_iii
addq $32, %rsp
.cfi_def_cfa_offset 192
movl $0, %esi
movq %r12, %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 104(%rsp), %xmm0
divsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 96(%rsp), %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, 32(%rsp)
leaq .LC15(%rip), %rsi
leaq .LC16(%rip), %rdi
call fopen@PLT
movq %rax, %r12
testl %ebx, %ebx
jle .L39
leaq _ZZ4mainE5lines(%rip), %rbp
movslq %ebx, %rbx
leaq (%rbx,%rbx,4), %rax
leaq (%rax,%rax,4), %rax
leaq 0(%rbp,%rax,8), %r13
leaq .LC17(%rip), %rbx
.L40:
movq %rbp, %rcx
movq %rbx, %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $200, %rbp
cmpq %r13, %rbp
jne .L40
.L39:
leaq .LC18(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 24(%rsp), %rax
movq %rax, %r15
movq 16(%rsp), %r14
movq 8(%rsp), %r13
addq $891952, %rax
movq %rax, 8(%rsp)
movl $0, %ebp
jmp .L41
.L42:
addq $4, %rbx
cmpq $1712, %rbx
je .L56
.L43:
movl 0(%r13,%rbx), %ecx
movl (%r15,%rbx), %r9d
movl (%r14,%rbx), %r8d
leaq .LC19(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1, %ebp
cmpl $12, %ebp
jne .L42
leaq .LC18(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %ebp
jmp .L42
.L56:
addq $1712, %r15
addq $1712, %r14
addq $1712, %r13
movq 8(%rsp), %rax
cmpq %rax, %r15
je .L44
.L41:
movl $0, %ebx
jmp .L43
.L44:
leaq 96(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 104(%rsp), %xmm0
divsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 96(%rsp), %xmm1
addsd %xmm1, %xmm0
subsd 32(%rsp), %xmm0
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r12, %rdi
call fclose@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L57
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L57:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC21:
.string "_Z10kernelCopyPiS_S_S_S_S_ii"
.LC22:
.string "_Z10kernelBlurPiS_S_S_S_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _Z10kernelCopyPiS_S_S_S_S_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC22(%rip), %rdx
movq %rdx, %rcx
leaq _Z10kernelBlurPiS_S_S_S_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZZ4mainE5lines
.comm _ZZ4mainE5lines,1000,32
.local _ZZ4mainE3str
.comm _ZZ4mainE3str,200,32
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 1023410176
.align 4
.LC4:
.long 1258291200
.align 4
.LC6:
.long 1065353216
.align 4
.LC7:
.long 1031798784
.align 4
.LC9:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <string.h>
#include <sys/types.h>
#include <sys/time.h>
#include <cuda.h>
#define BW 16 // Block Width
#define BH 32 // Block Height
#define COUNT 0
// Kernel Function handles first nested for loop
__global__ void kernelBlur(int *d_Rnew, int *d_Gnew, int *d_Bnew, int *d_R, int *d_G, int *d_B, int rowsize, int colsize) {
// Set-up
int row = blockIdx.y*blockDim.y + threadIdx.y;
int col = blockIdx.x*blockDim.x + threadIdx.x;
// Run Some Calculations
if (col < colsize && row < rowsize) {
if (row != 0 && row != (rowsize-1) && col != 0 && col != (colsize-1)) {
d_Rnew[row * colsize + col] = (d_R[(row + 1) * colsize + col]+d_R[(row - 1) * colsize + col]+d_R[row * colsize + (col + 1)]+d_R[row * colsize + (col - 1)])/4;
d_Gnew[row * colsize + col] = (d_G[(row + 1) * colsize + col]+d_G[(row - 1) * colsize + col]+d_G[row * colsize + (col + 1)]+d_G[row * colsize + (col - 1)])/4;
d_Bnew[row * colsize + col] = (d_B[(row + 1) * colsize + col]+d_B[(row - 1) * colsize + col]+d_B[row * colsize + (col + 1)]+d_B[row * colsize + (col - 1)])/4;
}
else if (row == 0 && col != 0 && col != (colsize-1)){
d_Rnew[row * colsize + col] = (d_R[(row + 1) * colsize + col]+d_R[row * colsize + (col + 1)]+d_R[row * colsize + (col - 1)])/3;
d_Gnew[row * colsize + col] = (d_G[(row + 1) * colsize + col]+d_G[row * colsize + (col + 1)]+d_G[row * colsize + (col - 1)])/3;
d_Bnew[row * colsize + col] = (d_B[(row + 1) * colsize + col]+d_B[row * colsize + (col + 1)]+d_B[row * colsize + (col - 1)])/3;
}
else if (row == (rowsize-1) && col != 0 && col != (colsize-1)){
d_Rnew[row * colsize + col] = (d_R[(row - 1) * colsize + col]+d_R[row * colsize + (col + 1)]+d_R[row * colsize + (col - 1)])/3;
d_Gnew[row * colsize + col] = (d_G[(row - 1) * colsize + col]+d_G[row * colsize + (col + 1)]+d_G[row * colsize + (col - 1)])/3;
d_Bnew[row * colsize + col] = (d_B[(row - 1) * colsize + col]+d_B[row * colsize + (col + 1)]+d_B[row * colsize + (col - 1)])/3;
}
else if (col == 0 && row != 0 && row != (rowsize-1)){
d_Rnew[row * colsize + col] = (d_R[(row + 1) * colsize + col]+d_R[(row - 1) * colsize + col]+d_R[row * colsize + (col + 1)])/3;
d_Gnew[row * colsize + col] = (d_G[(row + 1) * colsize + col]+d_G[(row - 1) * colsize + col]+d_G[row * colsize + (col + 1)])/3;
d_Bnew[row * colsize + col] = (d_B[(row + 1) * colsize + col]+d_B[(row - 1) * colsize + col]+d_B[row * colsize + (col + 1)])/3;
}
else if (col == (colsize-1) && row != 0 && row != (rowsize-1)){
d_Rnew[row * colsize + col] = (d_R[(row + 1) * colsize + col]+d_R[(row - 1) * colsize + col]+d_R[row * colsize + (col + 1)])/3;
d_Gnew[row * colsize + col] = (d_G[(row + 1) * colsize + col]+d_G[(row - 1) * colsize + col]+d_G[row * colsize + (col + 1)])/3;
d_Bnew[row * colsize + col] = (d_B[(row + 1) * colsize + col]+d_B[(row - 1) * colsize + col]+d_B[row * colsize + (col + 1)])/3;
}
else if (row==0 &&col==0){
d_Rnew[row * colsize + col] = (d_R[row * colsize + (col + 1)]+d_R[(row + 1) * colsize + col])/2;
d_Gnew[row * colsize + col] = (d_G[row * colsize + (col + 1)]+d_G[(row + 1) * colsize + col])/2;
d_Bnew[row * colsize + col] = (d_B[row * colsize + (col + 1)]+d_B[(row + 1) * colsize + col])/2;
}
else if (row==0 &&col==(colsize-1)){
d_Rnew[row * colsize + col] = (d_R[row * colsize + (col - 1)]+d_R[(row + 1) * colsize + col])/2;
d_Gnew[row * colsize + col] = (d_G[row * colsize + (col - 1)]+d_G[(row + 1) * colsize + col])/2;
d_Bnew[row * colsize + col] = (d_B[row * colsize + (col - 1)]+d_B[(row + 1) * colsize + col])/2;
}
else if (row==(rowsize-1) &&col==0){
d_Rnew[row * colsize + col] = (d_R[row * colsize + (col + 1)]+d_R[(row - 1) * colsize + col])/2;
d_Gnew[row * colsize + col] = (d_G[row * colsize + (col + 1)]+d_G[(row - 1) * colsize + col])/2;
d_Bnew[row * colsize + col] = (d_B[row * colsize + (col + 1)]+d_B[(row - 1) * colsize + col])/2;
}
else if (row==(rowsize-1) &&col==(colsize-1)){
d_Rnew[row * colsize + col] = (d_R[row * colsize + (col - 1)]+d_R[(row - 1) * colsize + col])/2;
d_Gnew[row * colsize + col] = (d_G[row * colsize + (col - 1)]+d_G[(row - 1) * colsize + col])/2;
d_Bnew[row * colsize + col] = (d_B[row * colsize + (col - 1)]+d_B[(row - 1) * colsize + col])/2;
}
}
}
// Kernel Function handles second nested for loop updates RGB values to new calculated values
__global__ void kernelCopy(int *d_Rnew, int *d_Gnew, int *d_Bnew, int *d_R, int *d_G, int *d_B, int rowsize, int colsize) {
// Set-up
int row = blockIdx.y*blockDim.y+threadIdx.y;
int col = blockIdx.x*blockDim.x+threadIdx.x;
if (col < colsize && row < rowsize) {
d_R[row * colsize + col] = d_Rnew[row * colsize + col];
d_G[row * colsize + col] = d_Gnew[row * colsize + col];
d_B[row * colsize + col] = d_Bnew[row * colsize + col];
}
}
void performBlurs(int *h_R, int *h_G, int *h_B, int *h_Rnew, int *h_Gnew, int *h_Bnew, int rowsize, int colsize, int nblurs) {
// Assign Memory on GPU
// Step 1 Assign Memory on GPU
int k;
int sizei = sizeof(int)*rowsize*colsize;
int *d_R, *d_G, *d_B, *d_Rnew, *d_Gnew, *d_Bnew;
struct timeval tim;
gettimeofday(&tim, NULL);
double t1=tim.tv_sec+(tim.tv_usec/1000000.0);
cudaMalloc((void **)&d_R,sizei);
cudaMalloc((void **)&d_G,sizei);
cudaMalloc((void **)&d_B,sizei);
cudaMalloc((void **)&d_Rnew,sizei);
cudaMalloc((void **)&d_Gnew,sizei);
cudaMalloc((void **)&d_Bnew,sizei);
gettimeofday(&tim, NULL);
double t2=tim.tv_sec+(tim.tv_usec/1000000.0);
printf("Assigning Memory to GPU > %.6lf seconds elapsed\n", t2-t1);
// Transfer to Device
gettimeofday(&tim, NULL);
t1=tim.tv_sec+(tim.tv_usec/1000000.0);
cudaMemcpy(d_R, h_R, sizei, cudaMemcpyHostToDevice);
cudaMemcpy(d_G, h_G, sizei, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, sizei, cudaMemcpyHostToDevice);
cudaMemcpy(d_Rnew, h_Rnew, sizei, cudaMemcpyHostToDevice);
cudaMemcpy(d_Gnew, h_Gnew, sizei, cudaMemcpyHostToDevice);
cudaMemcpy(d_Bnew, h_Bnew, sizei, cudaMemcpyHostToDevice);
t2=tim.tv_sec+(tim.tv_usec/1000000.0);
printf("Transferring from host to device memory > %.6lf seconds elapsed\n", t2-t1);
// Set up Blocks
dim3 dimGrid(ceil(colsize/(float)BW), ceil(rowsize/(float)BH), 1);
dim3 dimBlock(BW,BH);
nblurs = 10; // Modify as Needed
gettimeofday(&tim, NULL);
t1=tim.tv_sec+(tim.tv_usec/1000000.0);
for (k = 0; k < nblurs; ++k) {
kernelBlur<<<dimGrid, dimBlock>>>(d_Rnew, d_Gnew, d_Bnew, d_R, d_G, d_B, rowsize, colsize);
kernelCopy<<<dimGrid, dimBlock>>>(d_Rnew, d_Gnew, d_Bnew, d_R, d_G, d_B, rowsize, colsize);
}
t2=tim.tv_sec+(tim.tv_usec/1000000.0);
printf("Blurring Operation > %.6lf seconds elapsed\n", t2-t1);
// Step 4 output copied from GPU to Host get the RGB values
cudaMemcpy(h_R, d_R, sizei, cudaMemcpyDeviceToHost);
cudaMemcpy(h_G, d_G, sizei, cudaMemcpyDeviceToHost);
cudaMemcpy(h_B, d_B, sizei, cudaMemcpyDeviceToHost);
// Step 5 Free Memory
cudaFree(d_R); cudaFree(d_G); cudaFree(d_B); cudaFree(d_Rnew); cudaFree(d_Gnew); cudaFree(d_Bnew);
}
int main (int argc, const char * argv[]) {
// Assignment of initial Variables
static int const maxlen = 200, rowsize = 521, colsize = 428, linelen = 12;
static char str[200], lines[5][200];
FILE *fp, *fout;
int nlines = 0;
unsigned int h1, h2, h3;
char *sptr;
// Define Host Arrays
int *h_R, *h_G, *h_B;
int *h_Rnew, *h_Gnew, *h_Bnew;
int size = sizeof(int) * rowsize * colsize;
h_R = (int *)malloc(size);
h_G = (int *)malloc(size);
h_B = (int *)malloc(size);
h_Rnew = (int *)malloc(size);
h_Gnew = (int *)malloc(size);
h_Bnew = (int *)malloc(size);
// Allocate Overall Size of ROw
int row = 0, col = 0, nblurs = 0, lineno=0, k;
// Read input file
struct timeval tim;
gettimeofday(&tim, NULL);
double t1=tim.tv_sec+(tim.tv_usec/1000000.0);
fp = fopen("sample.ps", "r");
while(! feof(fp))
{
fscanf(fp, "\n%[^\n]", str);
if (nlines < 5) {strcpy((char *)lines[nlines++],(char *)str);}
else{
for (sptr=&str[0];*sptr != '\0';sptr+=6){
sscanf(sptr,"%2x",&h1);
sscanf(sptr+2,"%2x",&h2);
sscanf(sptr+4,"%2x",&h3);
if (col==colsize){
col = 0;
row++;
}
if (row < rowsize) {
h_R[row * colsize + col] = h1;
h_G[row * colsize + col] = h2;
h_B[row * colsize + col] = h3;
}
col++;
}
}
}
fclose(fp);
gettimeofday(&tim, NULL);
double t2=tim.tv_sec+(tim.tv_usec/1000000.0);
printf("Reading Input File > %.6lf seconds elapsed\n", t2-t1);
// Run Code
performBlurs(h_R, h_G, h_B, h_Rnew, h_Gnew, h_Bnew, rowsize, colsize, nblurs);
gettimeofday(&tim, NULL);
t1=tim.tv_sec+(tim.tv_usec/1000000.0);
fout= fopen("sampleBlurCU.ps", "w");
for (k=0;k<nlines;k++) fprintf(fout,"\n%s", lines[k]);
fprintf(fout,"\n");
for(row=0;row<rowsize;row++){
for (col=0;col<colsize;col++){
fprintf(fout,"%02x%02x%02x",h_R[row * colsize + col],h_G[row * colsize + col],h_B[row * colsize + col]);
lineno++;
if (lineno==linelen){
fprintf(fout,"\n");
lineno = 0;
}
}
}
gettimeofday(&tim, NULL);
t2=tim.tv_sec+(tim.tv_usec/1000000.0);
printf("Outputting File > %.6lf seconds elapsed\n", t2-t1);
fclose(fout);
return 0;
} | #include <stdio.h>
#include <string.h>
#include <sys/types.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
#define BW 16 // Block Width
#define BH 32 // Block Height
#define COUNT 0
// Kernel Function handles first nested for loop
__global__ void kernelBlur(int *d_Rnew, int *d_Gnew, int *d_Bnew, int *d_R, int *d_G, int *d_B, int rowsize, int colsize) {
// Set-up
int row = blockIdx.y*blockDim.y + threadIdx.y;
int col = blockIdx.x*blockDim.x + threadIdx.x;
// Run Some Calculations
if (col < colsize && row < rowsize) {
if (row != 0 && row != (rowsize-1) && col != 0 && col != (colsize-1)) {
d_Rnew[row * colsize + col] = (d_R[(row + 1) * colsize + col]+d_R[(row - 1) * colsize + col]+d_R[row * colsize + (col + 1)]+d_R[row * colsize + (col - 1)])/4;
d_Gnew[row * colsize + col] = (d_G[(row + 1) * colsize + col]+d_G[(row - 1) * colsize + col]+d_G[row * colsize + (col + 1)]+d_G[row * colsize + (col - 1)])/4;
d_Bnew[row * colsize + col] = (d_B[(row + 1) * colsize + col]+d_B[(row - 1) * colsize + col]+d_B[row * colsize + (col + 1)]+d_B[row * colsize + (col - 1)])/4;
}
else if (row == 0 && col != 0 && col != (colsize-1)){
d_Rnew[row * colsize + col] = (d_R[(row + 1) * colsize + col]+d_R[row * colsize + (col + 1)]+d_R[row * colsize + (col - 1)])/3;
d_Gnew[row * colsize + col] = (d_G[(row + 1) * colsize + col]+d_G[row * colsize + (col + 1)]+d_G[row * colsize + (col - 1)])/3;
d_Bnew[row * colsize + col] = (d_B[(row + 1) * colsize + col]+d_B[row * colsize + (col + 1)]+d_B[row * colsize + (col - 1)])/3;
}
else if (row == (rowsize-1) && col != 0 && col != (colsize-1)){
d_Rnew[row * colsize + col] = (d_R[(row - 1) * colsize + col]+d_R[row * colsize + (col + 1)]+d_R[row * colsize + (col - 1)])/3;
d_Gnew[row * colsize + col] = (d_G[(row - 1) * colsize + col]+d_G[row * colsize + (col + 1)]+d_G[row * colsize + (col - 1)])/3;
d_Bnew[row * colsize + col] = (d_B[(row - 1) * colsize + col]+d_B[row * colsize + (col + 1)]+d_B[row * colsize + (col - 1)])/3;
}
else if (col == 0 && row != 0 && row != (rowsize-1)){
d_Rnew[row * colsize + col] = (d_R[(row + 1) * colsize + col]+d_R[(row - 1) * colsize + col]+d_R[row * colsize + (col + 1)])/3;
d_Gnew[row * colsize + col] = (d_G[(row + 1) * colsize + col]+d_G[(row - 1) * colsize + col]+d_G[row * colsize + (col + 1)])/3;
d_Bnew[row * colsize + col] = (d_B[(row + 1) * colsize + col]+d_B[(row - 1) * colsize + col]+d_B[row * colsize + (col + 1)])/3;
}
else if (col == (colsize-1) && row != 0 && row != (rowsize-1)){
d_Rnew[row * colsize + col] = (d_R[(row + 1) * colsize + col]+d_R[(row - 1) * colsize + col]+d_R[row * colsize + (col + 1)])/3;
d_Gnew[row * colsize + col] = (d_G[(row + 1) * colsize + col]+d_G[(row - 1) * colsize + col]+d_G[row * colsize + (col + 1)])/3;
d_Bnew[row * colsize + col] = (d_B[(row + 1) * colsize + col]+d_B[(row - 1) * colsize + col]+d_B[row * colsize + (col + 1)])/3;
}
else if (row==0 &&col==0){
d_Rnew[row * colsize + col] = (d_R[row * colsize + (col + 1)]+d_R[(row + 1) * colsize + col])/2;
d_Gnew[row * colsize + col] = (d_G[row * colsize + (col + 1)]+d_G[(row + 1) * colsize + col])/2;
d_Bnew[row * colsize + col] = (d_B[row * colsize + (col + 1)]+d_B[(row + 1) * colsize + col])/2;
}
else if (row==0 &&col==(colsize-1)){
d_Rnew[row * colsize + col] = (d_R[row * colsize + (col - 1)]+d_R[(row + 1) * colsize + col])/2;
d_Gnew[row * colsize + col] = (d_G[row * colsize + (col - 1)]+d_G[(row + 1) * colsize + col])/2;
d_Bnew[row * colsize + col] = (d_B[row * colsize + (col - 1)]+d_B[(row + 1) * colsize + col])/2;
}
else if (row==(rowsize-1) &&col==0){
d_Rnew[row * colsize + col] = (d_R[row * colsize + (col + 1)]+d_R[(row - 1) * colsize + col])/2;
d_Gnew[row * colsize + col] = (d_G[row * colsize + (col + 1)]+d_G[(row - 1) * colsize + col])/2;
d_Bnew[row * colsize + col] = (d_B[row * colsize + (col + 1)]+d_B[(row - 1) * colsize + col])/2;
}
else if (row==(rowsize-1) &&col==(colsize-1)){
d_Rnew[row * colsize + col] = (d_R[row * colsize + (col - 1)]+d_R[(row - 1) * colsize + col])/2;
d_Gnew[row * colsize + col] = (d_G[row * colsize + (col - 1)]+d_G[(row - 1) * colsize + col])/2;
d_Bnew[row * colsize + col] = (d_B[row * colsize + (col - 1)]+d_B[(row - 1) * colsize + col])/2;
}
}
}
// Kernel Function handles second nested for loop updates RGB values to new calculated values
__global__ void kernelCopy(int *d_Rnew, int *d_Gnew, int *d_Bnew, int *d_R, int *d_G, int *d_B, int rowsize, int colsize) {
// Set-up
int row = blockIdx.y*blockDim.y+threadIdx.y;
int col = blockIdx.x*blockDim.x+threadIdx.x;
if (col < colsize && row < rowsize) {
d_R[row * colsize + col] = d_Rnew[row * colsize + col];
d_G[row * colsize + col] = d_Gnew[row * colsize + col];
d_B[row * colsize + col] = d_Bnew[row * colsize + col];
}
}
void performBlurs(int *h_R, int *h_G, int *h_B, int *h_Rnew, int *h_Gnew, int *h_Bnew, int rowsize, int colsize, int nblurs) {
// Assign Memory on GPU
// Step 1 Assign Memory on GPU
int k;
int sizei = sizeof(int)*rowsize*colsize;
int *d_R, *d_G, *d_B, *d_Rnew, *d_Gnew, *d_Bnew;
struct timeval tim;
gettimeofday(&tim, NULL);
double t1=tim.tv_sec+(tim.tv_usec/1000000.0);
hipMalloc((void **)&d_R,sizei);
hipMalloc((void **)&d_G,sizei);
hipMalloc((void **)&d_B,sizei);
hipMalloc((void **)&d_Rnew,sizei);
hipMalloc((void **)&d_Gnew,sizei);
hipMalloc((void **)&d_Bnew,sizei);
gettimeofday(&tim, NULL);
double t2=tim.tv_sec+(tim.tv_usec/1000000.0);
printf("Assigning Memory to GPU > %.6lf seconds elapsed\n", t2-t1);
// Transfer to Device
gettimeofday(&tim, NULL);
t1=tim.tv_sec+(tim.tv_usec/1000000.0);
hipMemcpy(d_R, h_R, sizei, hipMemcpyHostToDevice);
hipMemcpy(d_G, h_G, sizei, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, sizei, hipMemcpyHostToDevice);
hipMemcpy(d_Rnew, h_Rnew, sizei, hipMemcpyHostToDevice);
hipMemcpy(d_Gnew, h_Gnew, sizei, hipMemcpyHostToDevice);
hipMemcpy(d_Bnew, h_Bnew, sizei, hipMemcpyHostToDevice);
t2=tim.tv_sec+(tim.tv_usec/1000000.0);
printf("Transferring from host to device memory > %.6lf seconds elapsed\n", t2-t1);
// Set up Blocks
dim3 dimGrid(ceil(colsize/(float)BW), ceil(rowsize/(float)BH), 1);
dim3 dimBlock(BW,BH);
nblurs = 10; // Modify as Needed
gettimeofday(&tim, NULL);
t1=tim.tv_sec+(tim.tv_usec/1000000.0);
for (k = 0; k < nblurs; ++k) {
kernelBlur<<<dimGrid, dimBlock>>>(d_Rnew, d_Gnew, d_Bnew, d_R, d_G, d_B, rowsize, colsize);
kernelCopy<<<dimGrid, dimBlock>>>(d_Rnew, d_Gnew, d_Bnew, d_R, d_G, d_B, rowsize, colsize);
}
t2=tim.tv_sec+(tim.tv_usec/1000000.0);
printf("Blurring Operation > %.6lf seconds elapsed\n", t2-t1);
// Step 4 output copied from GPU to Host get the RGB values
hipMemcpy(h_R, d_R, sizei, hipMemcpyDeviceToHost);
hipMemcpy(h_G, d_G, sizei, hipMemcpyDeviceToHost);
hipMemcpy(h_B, d_B, sizei, hipMemcpyDeviceToHost);
// Step 5 Free Memory
hipFree(d_R); hipFree(d_G); hipFree(d_B); hipFree(d_Rnew); hipFree(d_Gnew); hipFree(d_Bnew);
}
int main (int argc, const char * argv[]) {
// Assignment of initial Variables
static int const maxlen = 200, rowsize = 521, colsize = 428, linelen = 12;
static char str[200], lines[5][200];
FILE *fp, *fout;
int nlines = 0;
unsigned int h1, h2, h3;
char *sptr;
// Define Host Arrays
int *h_R, *h_G, *h_B;
int *h_Rnew, *h_Gnew, *h_Bnew;
int size = sizeof(int) * rowsize * colsize;
h_R = (int *)malloc(size);
h_G = (int *)malloc(size);
h_B = (int *)malloc(size);
h_Rnew = (int *)malloc(size);
h_Gnew = (int *)malloc(size);
h_Bnew = (int *)malloc(size);
// Allocate Overall Size of ROw
int row = 0, col = 0, nblurs = 0, lineno=0, k;
// Read input file
struct timeval tim;
gettimeofday(&tim, NULL);
double t1=tim.tv_sec+(tim.tv_usec/1000000.0);
fp = fopen("sample.ps", "r");
while(! feof(fp))
{
fscanf(fp, "\n%[^\n]", str);
if (nlines < 5) {strcpy((char *)lines[nlines++],(char *)str);}
else{
for (sptr=&str[0];*sptr != '\0';sptr+=6){
sscanf(sptr,"%2x",&h1);
sscanf(sptr+2,"%2x",&h2);
sscanf(sptr+4,"%2x",&h3);
if (col==colsize){
col = 0;
row++;
}
if (row < rowsize) {
h_R[row * colsize + col] = h1;
h_G[row * colsize + col] = h2;
h_B[row * colsize + col] = h3;
}
col++;
}
}
}
fclose(fp);
gettimeofday(&tim, NULL);
double t2=tim.tv_sec+(tim.tv_usec/1000000.0);
printf("Reading Input File > %.6lf seconds elapsed\n", t2-t1);
// Run Code
performBlurs(h_R, h_G, h_B, h_Rnew, h_Gnew, h_Bnew, rowsize, colsize, nblurs);
gettimeofday(&tim, NULL);
t1=tim.tv_sec+(tim.tv_usec/1000000.0);
fout= fopen("sampleBlurCU.ps", "w");
for (k=0;k<nlines;k++) fprintf(fout,"\n%s", lines[k]);
fprintf(fout,"\n");
for(row=0;row<rowsize;row++){
for (col=0;col<colsize;col++){
fprintf(fout,"%02x%02x%02x",h_R[row * colsize + col],h_G[row * colsize + col],h_B[row * colsize + col]);
lineno++;
if (lineno==linelen){
fprintf(fout,"\n");
lineno = 0;
}
}
}
gettimeofday(&tim, NULL);
t2=tim.tv_sec+(tim.tv_usec/1000000.0);
printf("Outputting File > %.6lf seconds elapsed\n", t2-t1);
fclose(fout);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <string.h>
#include <sys/types.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
#define BW 16 // Block Width
#define BH 32 // Block Height
#define COUNT 0
// Kernel Function handles first nested for loop
__global__ void kernelBlur(int *d_Rnew, int *d_Gnew, int *d_Bnew, int *d_R, int *d_G, int *d_B, int rowsize, int colsize) {
// Set-up
int row = blockIdx.y*blockDim.y + threadIdx.y;
int col = blockIdx.x*blockDim.x + threadIdx.x;
// Run Some Calculations
if (col < colsize && row < rowsize) {
if (row != 0 && row != (rowsize-1) && col != 0 && col != (colsize-1)) {
d_Rnew[row * colsize + col] = (d_R[(row + 1) * colsize + col]+d_R[(row - 1) * colsize + col]+d_R[row * colsize + (col + 1)]+d_R[row * colsize + (col - 1)])/4;
d_Gnew[row * colsize + col] = (d_G[(row + 1) * colsize + col]+d_G[(row - 1) * colsize + col]+d_G[row * colsize + (col + 1)]+d_G[row * colsize + (col - 1)])/4;
d_Bnew[row * colsize + col] = (d_B[(row + 1) * colsize + col]+d_B[(row - 1) * colsize + col]+d_B[row * colsize + (col + 1)]+d_B[row * colsize + (col - 1)])/4;
}
else if (row == 0 && col != 0 && col != (colsize-1)){
d_Rnew[row * colsize + col] = (d_R[(row + 1) * colsize + col]+d_R[row * colsize + (col + 1)]+d_R[row * colsize + (col - 1)])/3;
d_Gnew[row * colsize + col] = (d_G[(row + 1) * colsize + col]+d_G[row * colsize + (col + 1)]+d_G[row * colsize + (col - 1)])/3;
d_Bnew[row * colsize + col] = (d_B[(row + 1) * colsize + col]+d_B[row * colsize + (col + 1)]+d_B[row * colsize + (col - 1)])/3;
}
else if (row == (rowsize-1) && col != 0 && col != (colsize-1)){
d_Rnew[row * colsize + col] = (d_R[(row - 1) * colsize + col]+d_R[row * colsize + (col + 1)]+d_R[row * colsize + (col - 1)])/3;
d_Gnew[row * colsize + col] = (d_G[(row - 1) * colsize + col]+d_G[row * colsize + (col + 1)]+d_G[row * colsize + (col - 1)])/3;
d_Bnew[row * colsize + col] = (d_B[(row - 1) * colsize + col]+d_B[row * colsize + (col + 1)]+d_B[row * colsize + (col - 1)])/3;
}
else if (col == 0 && row != 0 && row != (rowsize-1)){
d_Rnew[row * colsize + col] = (d_R[(row + 1) * colsize + col]+d_R[(row - 1) * colsize + col]+d_R[row * colsize + (col + 1)])/3;
d_Gnew[row * colsize + col] = (d_G[(row + 1) * colsize + col]+d_G[(row - 1) * colsize + col]+d_G[row * colsize + (col + 1)])/3;
d_Bnew[row * colsize + col] = (d_B[(row + 1) * colsize + col]+d_B[(row - 1) * colsize + col]+d_B[row * colsize + (col + 1)])/3;
}
else if (col == (colsize-1) && row != 0 && row != (rowsize-1)){
d_Rnew[row * colsize + col] = (d_R[(row + 1) * colsize + col]+d_R[(row - 1) * colsize + col]+d_R[row * colsize + (col + 1)])/3;
d_Gnew[row * colsize + col] = (d_G[(row + 1) * colsize + col]+d_G[(row - 1) * colsize + col]+d_G[row * colsize + (col + 1)])/3;
d_Bnew[row * colsize + col] = (d_B[(row + 1) * colsize + col]+d_B[(row - 1) * colsize + col]+d_B[row * colsize + (col + 1)])/3;
}
else if (row==0 &&col==0){
d_Rnew[row * colsize + col] = (d_R[row * colsize + (col + 1)]+d_R[(row + 1) * colsize + col])/2;
d_Gnew[row * colsize + col] = (d_G[row * colsize + (col + 1)]+d_G[(row + 1) * colsize + col])/2;
d_Bnew[row * colsize + col] = (d_B[row * colsize + (col + 1)]+d_B[(row + 1) * colsize + col])/2;
}
else if (row==0 &&col==(colsize-1)){
d_Rnew[row * colsize + col] = (d_R[row * colsize + (col - 1)]+d_R[(row + 1) * colsize + col])/2;
d_Gnew[row * colsize + col] = (d_G[row * colsize + (col - 1)]+d_G[(row + 1) * colsize + col])/2;
d_Bnew[row * colsize + col] = (d_B[row * colsize + (col - 1)]+d_B[(row + 1) * colsize + col])/2;
}
else if (row==(rowsize-1) &&col==0){
d_Rnew[row * colsize + col] = (d_R[row * colsize + (col + 1)]+d_R[(row - 1) * colsize + col])/2;
d_Gnew[row * colsize + col] = (d_G[row * colsize + (col + 1)]+d_G[(row - 1) * colsize + col])/2;
d_Bnew[row * colsize + col] = (d_B[row * colsize + (col + 1)]+d_B[(row - 1) * colsize + col])/2;
}
else if (row==(rowsize-1) &&col==(colsize-1)){
d_Rnew[row * colsize + col] = (d_R[row * colsize + (col - 1)]+d_R[(row - 1) * colsize + col])/2;
d_Gnew[row * colsize + col] = (d_G[row * colsize + (col - 1)]+d_G[(row - 1) * colsize + col])/2;
d_Bnew[row * colsize + col] = (d_B[row * colsize + (col - 1)]+d_B[(row - 1) * colsize + col])/2;
}
}
}
// Kernel Function handles second nested for loop updates RGB values to new calculated values
__global__ void kernelCopy(int *d_Rnew, int *d_Gnew, int *d_Bnew, int *d_R, int *d_G, int *d_B, int rowsize, int colsize) {
// Set-up
int row = blockIdx.y*blockDim.y+threadIdx.y;
int col = blockIdx.x*blockDim.x+threadIdx.x;
if (col < colsize && row < rowsize) {
d_R[row * colsize + col] = d_Rnew[row * colsize + col];
d_G[row * colsize + col] = d_Gnew[row * colsize + col];
d_B[row * colsize + col] = d_Bnew[row * colsize + col];
}
}
void performBlurs(int *h_R, int *h_G, int *h_B, int *h_Rnew, int *h_Gnew, int *h_Bnew, int rowsize, int colsize, int nblurs) {
// Assign Memory on GPU
// Step 1 Assign Memory on GPU
int k;
int sizei = sizeof(int)*rowsize*colsize;
int *d_R, *d_G, *d_B, *d_Rnew, *d_Gnew, *d_Bnew;
struct timeval tim;
gettimeofday(&tim, NULL);
double t1=tim.tv_sec+(tim.tv_usec/1000000.0);
hipMalloc((void **)&d_R,sizei);
hipMalloc((void **)&d_G,sizei);
hipMalloc((void **)&d_B,sizei);
hipMalloc((void **)&d_Rnew,sizei);
hipMalloc((void **)&d_Gnew,sizei);
hipMalloc((void **)&d_Bnew,sizei);
gettimeofday(&tim, NULL);
double t2=tim.tv_sec+(tim.tv_usec/1000000.0);
printf("Assigning Memory to GPU > %.6lf seconds elapsed\n", t2-t1);
// Transfer to Device
gettimeofday(&tim, NULL);
t1=tim.tv_sec+(tim.tv_usec/1000000.0);
hipMemcpy(d_R, h_R, sizei, hipMemcpyHostToDevice);
hipMemcpy(d_G, h_G, sizei, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, sizei, hipMemcpyHostToDevice);
hipMemcpy(d_Rnew, h_Rnew, sizei, hipMemcpyHostToDevice);
hipMemcpy(d_Gnew, h_Gnew, sizei, hipMemcpyHostToDevice);
hipMemcpy(d_Bnew, h_Bnew, sizei, hipMemcpyHostToDevice);
t2=tim.tv_sec+(tim.tv_usec/1000000.0);
printf("Transferring from host to device memory > %.6lf seconds elapsed\n", t2-t1);
// Set up Blocks
dim3 dimGrid(ceil(colsize/(float)BW), ceil(rowsize/(float)BH), 1);
dim3 dimBlock(BW,BH);
nblurs = 10; // Modify as Needed
gettimeofday(&tim, NULL);
t1=tim.tv_sec+(tim.tv_usec/1000000.0);
for (k = 0; k < nblurs; ++k) {
kernelBlur<<<dimGrid, dimBlock>>>(d_Rnew, d_Gnew, d_Bnew, d_R, d_G, d_B, rowsize, colsize);
kernelCopy<<<dimGrid, dimBlock>>>(d_Rnew, d_Gnew, d_Bnew, d_R, d_G, d_B, rowsize, colsize);
}
t2=tim.tv_sec+(tim.tv_usec/1000000.0);
printf("Blurring Operation > %.6lf seconds elapsed\n", t2-t1);
// Step 4 output copied from GPU to Host get the RGB values
hipMemcpy(h_R, d_R, sizei, hipMemcpyDeviceToHost);
hipMemcpy(h_G, d_G, sizei, hipMemcpyDeviceToHost);
hipMemcpy(h_B, d_B, sizei, hipMemcpyDeviceToHost);
// Step 5 Free Memory
hipFree(d_R); hipFree(d_G); hipFree(d_B); hipFree(d_Rnew); hipFree(d_Gnew); hipFree(d_Bnew);
}
int main (int argc, const char * argv[]) {
// Assignment of initial Variables
static int const maxlen = 200, rowsize = 521, colsize = 428, linelen = 12;
static char str[200], lines[5][200];
FILE *fp, *fout;
int nlines = 0;
unsigned int h1, h2, h3;
char *sptr;
// Define Host Arrays
int *h_R, *h_G, *h_B;
int *h_Rnew, *h_Gnew, *h_Bnew;
int size = sizeof(int) * rowsize * colsize;
h_R = (int *)malloc(size);
h_G = (int *)malloc(size);
h_B = (int *)malloc(size);
h_Rnew = (int *)malloc(size);
h_Gnew = (int *)malloc(size);
h_Bnew = (int *)malloc(size);
// Allocate Overall Size of ROw
int row = 0, col = 0, nblurs = 0, lineno=0, k;
// Read input file
struct timeval tim;
gettimeofday(&tim, NULL);
double t1=tim.tv_sec+(tim.tv_usec/1000000.0);
fp = fopen("sample.ps", "r");
while(! feof(fp))
{
fscanf(fp, "\n%[^\n]", str);
if (nlines < 5) {strcpy((char *)lines[nlines++],(char *)str);}
else{
for (sptr=&str[0];*sptr != '\0';sptr+=6){
sscanf(sptr,"%2x",&h1);
sscanf(sptr+2,"%2x",&h2);
sscanf(sptr+4,"%2x",&h3);
if (col==colsize){
col = 0;
row++;
}
if (row < rowsize) {
h_R[row * colsize + col] = h1;
h_G[row * colsize + col] = h2;
h_B[row * colsize + col] = h3;
}
col++;
}
}
}
fclose(fp);
gettimeofday(&tim, NULL);
double t2=tim.tv_sec+(tim.tv_usec/1000000.0);
printf("Reading Input File > %.6lf seconds elapsed\n", t2-t1);
// Run Code
performBlurs(h_R, h_G, h_B, h_Rnew, h_Gnew, h_Bnew, rowsize, colsize, nblurs);
gettimeofday(&tim, NULL);
t1=tim.tv_sec+(tim.tv_usec/1000000.0);
fout= fopen("sampleBlurCU.ps", "w");
for (k=0;k<nlines;k++) fprintf(fout,"\n%s", lines[k]);
fprintf(fout,"\n");
for(row=0;row<rowsize;row++){
for (col=0;col<colsize;col++){
fprintf(fout,"%02x%02x%02x",h_R[row * colsize + col],h_G[row * colsize + col],h_B[row * colsize + col]);
lineno++;
if (lineno==linelen){
fprintf(fout,"\n");
lineno = 0;
}
}
}
gettimeofday(&tim, NULL);
t2=tim.tv_sec+(tim.tv_usec/1000000.0);
printf("Outputting File > %.6lf seconds elapsed\n", t2-t1);
fclose(fout);
return 0;
} | .text
.file "blurCUDA.hip"
.globl _Z25__device_stub__kernelBlurPiS_S_S_S_S_ii # -- Begin function _Z25__device_stub__kernelBlurPiS_S_S_S_S_ii
.p2align 4, 0x90
.type _Z25__device_stub__kernelBlurPiS_S_S_S_S_ii,@function
_Z25__device_stub__kernelBlurPiS_S_S_S_S_ii: # @_Z25__device_stub__kernelBlurPiS_S_S_S_S_ii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10kernelBlurPiS_S_S_S_S_ii, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z25__device_stub__kernelBlurPiS_S_S_S_S_ii, .Lfunc_end0-_Z25__device_stub__kernelBlurPiS_S_S_S_S_ii
.cfi_endproc
# -- End function
.globl _Z25__device_stub__kernelCopyPiS_S_S_S_S_ii # -- Begin function _Z25__device_stub__kernelCopyPiS_S_S_S_S_ii
.p2align 4, 0x90
.type _Z25__device_stub__kernelCopyPiS_S_S_S_S_ii,@function
_Z25__device_stub__kernelCopyPiS_S_S_S_S_ii: # @_Z25__device_stub__kernelCopyPiS_S_S_S_S_ii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10kernelCopyPiS_S_S_S_S_ii, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end1:
.size _Z25__device_stub__kernelCopyPiS_S_S_S_S_ii, .Lfunc_end1-_Z25__device_stub__kernelCopyPiS_S_S_S_S_ii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z12performBlursPiS_S_S_S_S_iii
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI2_1:
.long 0x3d800000 # float 0.0625
.LCPI2_2:
.long 0x3d000000 # float 0.03125
.text
.globl _Z12performBlursPiS_S_S_S_S_iii
.p2align 4, 0x90
.type _Z12performBlursPiS_S_S_S_S_iii,@function
_Z12performBlursPiS_S_S_S_S_iii: # @_Z12performBlursPiS_S_S_S_S_iii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 352
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, 96(%rsp) # 8-byte Spill
movq %r8, 88(%rsp) # 8-byte Spill
movq %rcx, 80(%rsp) # 8-byte Spill
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %rbx
movl 352(%rsp), %ebp
movabsq $137438953488, %r13 # imm = 0x2000000010
imull 360(%rsp), %ebp
shll $2, %ebp
leaq 64(%rsp), %r12
movq %r12, %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 64(%rsp), %xmm0
cvtsi2sdq 72(%rsp), %xmm1
divsd .LCPI2_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 104(%rsp) # 8-byte Spill
movslq %ebp, %rbp
leaq 32(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 56(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movq %r12, %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq 64(%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 72(%rsp), %xmm0
divsd .LCPI2_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd 104(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str, %edi
movb $1, %al
callq printf
movq %r12, %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 64(%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 72(%rsp), %xmm1
divsd .LCPI2_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 272(%rsp) # 8-byte Spill
movq 32(%rsp), %rdi
movq %rbx, 280(%rsp) # 8-byte Spill
movq %rbx, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq %r15, 288(%rsp) # 8-byte Spill
movq %r15, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r14, 104(%rsp) # 8-byte Spill
movq %r14, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rdi
movq 80(%rsp), %rsi # 8-byte Reload
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movq 88(%rsp), %rsi # 8-byte Reload
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movq 96(%rsp), %rsi # 8-byte Reload
movq %rbp, 96(%rsp) # 8-byte Spill
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movsd 272(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
subsd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
xorps %xmm0, %xmm0
cvtsi2ssl 360(%rsp), %xmm0
mulss .LCPI2_1(%rip), %xmm0
callq ceilf@PLT
xorps %xmm1, %xmm1
cvtsi2ssl 352(%rsp), %xmm1
cvttss2si %xmm0, %r14
mulss .LCPI2_2(%rip), %xmm1
movaps %xmm1, %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %rbp
movl %r14d, %eax
shlq $32, %rbp
orq %rax, %rbp
movq %r12, %rdi
xorl %esi, %esi
callq gettimeofday
movq 64(%rsp), %rax
movq %rax, 88(%rsp) # 8-byte Spill
movq 72(%rsp), %rax
movq %rax, 80(%rsp) # 8-byte Spill
movl $10, %r14d
leaq 200(%rsp), %r15
leaq 192(%rsp), %r12
leaq 208(%rsp), %rbx
jmp .LBB2_1
.p2align 4, 0x90
.LBB2_5: # in Loop: Header=BB2_1 Depth=1
decl %r14d
je .LBB2_6
.LBB2_1: # =>This Inner Loop Header: Depth=1
movq %rbp, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_3
# %bb.2: # in Loop: Header=BB2_1 Depth=1
movq 56(%rsp), %rax
movq %rax, 184(%rsp)
movq 48(%rsp), %rax
movq %rax, 176(%rsp)
movq 40(%rsp), %rax
movq %rax, 168(%rsp)
movq 32(%rsp), %rax
movq %rax, 160(%rsp)
movq 24(%rsp), %rax
movq %rax, 152(%rsp)
movq 16(%rsp), %rax
movq %rax, 144(%rsp)
movl 352(%rsp), %eax
movl %eax, 12(%rsp)
movl 360(%rsp), %eax
movl %eax, 8(%rsp)
leaq 184(%rsp), %rax
movq %rax, 208(%rsp)
leaq 176(%rsp), %rax
movq %rax, 216(%rsp)
leaq 168(%rsp), %rax
movq %rax, 224(%rsp)
leaq 160(%rsp), %rax
movq %rax, 232(%rsp)
leaq 152(%rsp), %rax
movq %rax, 240(%rsp)
leaq 144(%rsp), %rax
movq %rax, 248(%rsp)
leaq 12(%rsp), %rax
movq %rax, 256(%rsp)
leaq 8(%rsp), %rax
movq %rax, 264(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
movq %r15, %rdx
movq %r12, %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
movl $_Z10kernelBlurPiS_S_S_S_S_ii, %edi
movq %rbx, %r9
pushq 192(%rsp)
.cfi_adjust_cfa_offset 8
pushq 208(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_3: # in Loop: Header=BB2_1 Depth=1
movq %rbp, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4: # in Loop: Header=BB2_1 Depth=1
movq 56(%rsp), %rax
movq %rax, 184(%rsp)
movq 48(%rsp), %rax
movq %rax, 176(%rsp)
movq 40(%rsp), %rax
movq %rax, 168(%rsp)
movq 32(%rsp), %rax
movq %rax, 160(%rsp)
movq 24(%rsp), %rax
movq %rax, 152(%rsp)
movq 16(%rsp), %rax
movq %rax, 144(%rsp)
movl 352(%rsp), %eax
movl %eax, 12(%rsp)
movl 360(%rsp), %eax
movl %eax, 8(%rsp)
leaq 184(%rsp), %rax
movq %rax, 208(%rsp)
leaq 176(%rsp), %rax
movq %rax, 216(%rsp)
leaq 168(%rsp), %rax
movq %rax, 224(%rsp)
leaq 160(%rsp), %rax
movq %rax, 232(%rsp)
leaq 152(%rsp), %rax
movq %rax, 240(%rsp)
leaq 144(%rsp), %rax
movq %rax, 248(%rsp)
leaq 12(%rsp), %rax
movq %rax, 256(%rsp)
leaq 8(%rsp), %rax
movq %rax, 264(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
movq %r15, %rdx
movq %r12, %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
movl $_Z10kernelCopyPiS_S_S_S_S_ii, %edi
movq %rbx, %r9
pushq 192(%rsp)
.cfi_adjust_cfa_offset 8
pushq 208(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_5
.LBB2_6:
xorps %xmm1, %xmm1
cvtsi2sdq 88(%rsp), %xmm1 # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sdq 80(%rsp), %xmm0 # 8-byte Folded Reload
divsd .LCPI2_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rsi
movq 280(%rsp), %rdi # 8-byte Reload
movq 96(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rsi
movq 288(%rsp), %rdi # 8-byte Reload
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rsi
movq 104(%rsp), %rdi # 8-byte Reload
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
addq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z12performBlursPiS_S_S_S_S_iii, .Lfunc_end2-_Z12performBlursPiS_S_S_S_S_iii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $88, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $891952, %edi # imm = 0xD9C30
callq malloc
movq %rax, (%rsp) # 8-byte Spill
movl $891952, %edi # imm = 0xD9C30
callq malloc
movq %rax, %r14
movl $891952, %edi # imm = 0xD9C30
callq malloc
movq %rax, %r15
movl $891952, %edi # imm = 0xD9C30
callq malloc
movq %rax, 80(%rsp) # 8-byte Spill
movl $891952, %edi # imm = 0xD9C30
callq malloc
movq %rax, 72(%rsp) # 8-byte Spill
movl $891952, %edi # imm = 0xD9C30
callq malloc
movq %rax, 64(%rsp) # 8-byte Spill
xorl %r13d, %r13d
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm0
cvtsi2sdq 16(%rsp), %xmm1
divsd .LCPI3_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 56(%rsp) # 8-byte Spill
movl $.L.str.3, %edi
movl $.L.str.4, %esi
callq fopen
movq %rax, %rbx
movq %rax, %rdi
callq feof
testl %eax, %eax
je .LBB3_1
.LBB3_10: # %._crit_edge
movq %rbx, %rdi
callq fclose
leaq 8(%rsp), %r12
movq %r12, %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq 8(%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 16(%rsp), %xmm0
divsd .LCPI3_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd 56(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.7, %edi
movb $1, %al
callq printf
subq $16, %rsp
.cfi_adjust_cfa_offset 16
movq 16(%rsp), %rdi # 8-byte Reload
movq %r14, %rsi
movq %r15, %rdx
movq 96(%rsp), %rcx # 8-byte Reload
movq 88(%rsp), %r8 # 8-byte Reload
movq 80(%rsp), %r9 # 8-byte Reload
pushq $428 # imm = 0x1AC
.cfi_adjust_cfa_offset 8
pushq $521 # imm = 0x209
.cfi_adjust_cfa_offset 8
callq _Z12performBlursPiS_S_S_S_S_iii
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movq %r12, %rdi
xorl %esi, %esi
callq gettimeofday
movq 8(%rsp), %rax
movq %rax, 32(%rsp) # 8-byte Spill
movq 16(%rsp), %rax
movq %rax, 24(%rsp) # 8-byte Spill
movl $.L.str.8, %edi
movl $.L.str.9, %esi
callq fopen
movq %rax, %r12
testl %r13d, %r13d
jle .LBB3_13
# %bb.11: # %.lr.ph93.preheader
movl %r13d, %ebx
movl $_ZZ4mainE5lines, %r13d
.p2align 4, 0x90
.LBB3_12: # %.lr.ph93
# =>This Inner Loop Header: Depth=1
movl $.L.str.10, %esi
movq %r12, %rdi
movq %r13, %rdx
xorl %eax, %eax
callq fprintf
addq $200, %r13
decq %rbx
jne .LBB3_12
.LBB3_13: # %._crit_edge94
movl $10, %edi
movq %r12, %rsi
callq fputc@PLT
xorl %eax, %eax
xorl %ebp, %ebp
movq (%rsp), %rbx # 8-byte Reload
jmp .LBB3_14
.p2align 4, 0x90
.LBB3_18: # in Loop: Header=BB3_14 Depth=1
movq (%rsp), %rax # 8-byte Reload
incq %rax
addq $1712, %r15 # imm = 0x6B0
addq $1712, %r14 # imm = 0x6B0
addq $1712, %rbx # imm = 0x6B0
cmpq $521, %rax # imm = 0x209
je .LBB3_19
.LBB3_14: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_15 Depth 2
movq %rax, (%rsp) # 8-byte Spill
xorl %r13d, %r13d
jmp .LBB3_15
.p2align 4, 0x90
.LBB3_17: # in Loop: Header=BB3_15 Depth=2
incq %r13
cmpq $428, %r13 # imm = 0x1AC
je .LBB3_18
.LBB3_15: # Parent Loop BB3_14 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r13,4), %edx
movl (%r14,%r13,4), %ecx
movl (%r15,%r13,4), %r8d
movl $.L.str.12, %esi
movq %r12, %rdi
xorl %eax, %eax
callq fprintf
incl %ebp
cmpl $12, %ebp
jne .LBB3_17
# %bb.16: # in Loop: Header=BB3_15 Depth=2
movl $10, %edi
movq %r12, %rsi
callq fputc@PLT
xorl %ebp, %ebp
jmp .LBB3_17
.LBB3_19:
xorps %xmm0, %xmm0
cvtsi2sdq 32(%rsp), %xmm0 # 8-byte Folded Reload
cvtsi2sdq 24(%rsp), %xmm1 # 8-byte Folded Reload
divsd .LCPI3_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, (%rsp) # 8-byte Spill
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq 8(%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 16(%rsp), %xmm0
divsd .LCPI3_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd (%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.13, %edi
movb $1, %al
callq printf
movq %r12, %rdi
callq fclose
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_1: # %.lr.ph89.preheader
.cfi_def_cfa_offset 144
xorl %r13d, %r13d
xorl %ebp, %ebp
xorl %r12d, %r12d
movq %rbx, 32(%rsp) # 8-byte Spill
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_20: # in Loop: Header=BB3_2 Depth=1
movslq %r13d, %rax
incl %r13d
imulq $200, %rax, %rax
leaq _ZZ4mainE5lines(%rax), %rdi
movl $_ZZ4mainE3str, %esi
callq strcpy
.LBB3_9: # %.loopexit
# in Loop: Header=BB3_2 Depth=1
movq 32(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
callq feof
testl %eax, %eax
jne .LBB3_10
.LBB3_2: # %.lr.ph89
# =>This Loop Header: Depth=1
# Child Loop BB3_5 Depth 2
movl $.L.str.5, %esi
movl $_ZZ4mainE3str, %edx
movq %rbx, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $5, %r13d
jl .LBB3_20
# %bb.3: # %.preheader79
# in Loop: Header=BB3_2 Depth=1
cmpb $0, _ZZ4mainE3str(%rip)
je .LBB3_9
# %bb.4: # %.lr.ph.preheader
# in Loop: Header=BB3_2 Depth=1
movq %r13, 24(%rsp) # 8-byte Spill
movl $_ZZ4mainE3str, %r13d
jmp .LBB3_5
.p2align 4, 0x90
.LBB3_7: # in Loop: Header=BB3_5 Depth=2
incl %ebp
cmpb $0, 2(%r13)
leaq 2(%r13), %r13
je .LBB3_8
.LBB3_5: # %.lr.ph
# Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movl %r12d, %ebx
movl $.L.str.6, %esi
movq %r13, %rdi
leaq 52(%rsp), %rdx
xorl %eax, %eax
callq __isoc23_sscanf
leaq 2(%r13), %rdi
movl $.L.str.6, %esi
leaq 48(%rsp), %rdx
xorl %eax, %eax
callq __isoc23_sscanf
addq $4, %r13
movl $.L.str.6, %esi
movq %r13, %rdi
leaq 44(%rsp), %rdx
xorl %eax, %eax
callq __isoc23_sscanf
xorl %r12d, %r12d
cmpl $428, %ebp # imm = 0x1AC
sete %r12b
movl $0, %eax
cmovel %eax, %ebp
addl %ebx, %r12d
cmpl $520, %r12d # imm = 0x208
jg .LBB3_7
# %bb.6: # in Loop: Header=BB3_5 Depth=2
movl 52(%rsp), %eax
imull $428, %r12d, %ecx # imm = 0x1AC
addl %ebp, %ecx
movslq %ecx, %rcx
movq (%rsp), %rdx # 8-byte Reload
movl %eax, (%rdx,%rcx,4)
movl 48(%rsp), %eax
movl %eax, (%r14,%rcx,4)
movl 44(%rsp), %eax
movl %eax, (%r15,%rcx,4)
jmp .LBB3_7
.p2align 4, 0x90
.LBB3_8: # in Loop: Header=BB3_2 Depth=1
movq 24(%rsp), %r13 # 8-byte Reload
jmp .LBB3_9
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10kernelBlurPiS_S_S_S_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10kernelCopyPiS_S_S_S_S_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10kernelBlurPiS_S_S_S_S_ii,@object # @_Z10kernelBlurPiS_S_S_S_S_ii
.section .rodata,"a",@progbits
.globl _Z10kernelBlurPiS_S_S_S_S_ii
.p2align 3, 0x0
_Z10kernelBlurPiS_S_S_S_S_ii:
.quad _Z25__device_stub__kernelBlurPiS_S_S_S_S_ii
.size _Z10kernelBlurPiS_S_S_S_S_ii, 8
.type _Z10kernelCopyPiS_S_S_S_S_ii,@object # @_Z10kernelCopyPiS_S_S_S_S_ii
.globl _Z10kernelCopyPiS_S_S_S_S_ii
.p2align 3, 0x0
_Z10kernelCopyPiS_S_S_S_S_ii:
.quad _Z25__device_stub__kernelCopyPiS_S_S_S_S_ii
.size _Z10kernelCopyPiS_S_S_S_S_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Assigning Memory to GPU > %.6lf seconds elapsed\n"
.size .L.str, 49
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Transferring from host to device memory > %.6lf seconds elapsed\n"
.size .L.str.1, 65
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Blurring Operation > %.6lf seconds elapsed\n"
.size .L.str.2, 44
.type _ZZ4mainE3str,@object # @_ZZ4mainE3str
.local _ZZ4mainE3str
.comm _ZZ4mainE3str,200,16
.type _ZZ4mainE5lines,@object # @_ZZ4mainE5lines
.local _ZZ4mainE5lines
.comm _ZZ4mainE5lines,1000,16
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "sample.ps"
.size .L.str.3, 10
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "r"
.size .L.str.4, 2
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\n%[^\n]"
.size .L.str.5, 7
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%2x"
.size .L.str.6, 4
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Reading Input File > %.6lf seconds elapsed\n"
.size .L.str.7, 44
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "sampleBlurCU.ps"
.size .L.str.8, 16
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "w"
.size .L.str.9, 2
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "\n%s"
.size .L.str.10, 4
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "%02x%02x%02x"
.size .L.str.12, 13
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Outputting File > %.6lf seconds elapsed\n"
.size .L.str.13, 41
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10kernelBlurPiS_S_S_S_S_ii"
.size .L__unnamed_1, 29
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10kernelCopyPiS_S_S_S_S_ii"
.size .L__unnamed_2, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__kernelBlurPiS_S_S_S_S_ii
.addrsig_sym _Z25__device_stub__kernelCopyPiS_S_S_S_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10kernelBlurPiS_S_S_S_S_ii
.addrsig_sym _Z10kernelCopyPiS_S_S_S_S_ii
.addrsig_sym _ZZ4mainE3str
.addrsig_sym _ZZ4mainE5lines
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001388d5_00000000-6_blurCUDA.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z10kernelBlurPiS_S_S_S_S_iiPiS_S_S_S_S_ii
.type _Z42__device_stub__Z10kernelBlurPiS_S_S_S_S_iiPiS_S_S_S_S_ii, @function
_Z42__device_stub__Z10kernelBlurPiS_S_S_S_S_iiPiS_S_S_S_S_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10kernelBlurPiS_S_S_S_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z42__device_stub__Z10kernelBlurPiS_S_S_S_S_iiPiS_S_S_S_S_ii, .-_Z42__device_stub__Z10kernelBlurPiS_S_S_S_S_iiPiS_S_S_S_S_ii
.globl _Z10kernelBlurPiS_S_S_S_S_ii
.type _Z10kernelBlurPiS_S_S_S_S_ii, @function
_Z10kernelBlurPiS_S_S_S_S_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z42__device_stub__Z10kernelBlurPiS_S_S_S_S_iiPiS_S_S_S_S_ii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z10kernelBlurPiS_S_S_S_S_ii, .-_Z10kernelBlurPiS_S_S_S_S_ii
.globl _Z42__device_stub__Z10kernelCopyPiS_S_S_S_S_iiPiS_S_S_S_S_ii
.type _Z42__device_stub__Z10kernelCopyPiS_S_S_S_S_iiPiS_S_S_S_S_ii, @function
_Z42__device_stub__Z10kernelCopyPiS_S_S_S_S_iiPiS_S_S_S_S_ii:
.LFB2085:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10kernelCopyPiS_S_S_S_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z42__device_stub__Z10kernelCopyPiS_S_S_S_S_iiPiS_S_S_S_S_ii, .-_Z42__device_stub__Z10kernelCopyPiS_S_S_S_S_iiPiS_S_S_S_S_ii
.globl _Z10kernelCopyPiS_S_S_S_S_ii
.type _Z10kernelCopyPiS_S_S_S_S_ii, @function
_Z10kernelCopyPiS_S_S_S_S_ii:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z42__device_stub__Z10kernelCopyPiS_S_S_S_S_iiPiS_S_S_S_S_ii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z10kernelCopyPiS_S_S_S_S_ii, .-_Z10kernelCopyPiS_S_S_S_S_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Assigning Memory to GPU > %.6lf seconds elapsed\n"
.align 8
.LC2:
.string "Transferring from host to device memory > %.6lf seconds elapsed\n"
.align 8
.LC8:
.string "Blurring Operation > %.6lf seconds elapsed\n"
.text
.globl _Z12performBlursPiS_S_S_S_S_iii
.type _Z12performBlursPiS_S_S_S_S_iii, @function
_Z12performBlursPiS_S_S_S_S_iii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $168, %rsp
.cfi_def_cfa_offset 224
movq %rdi, %r15
movq %rsi, %r14
movq %rdx, 8(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 32(%rsp)
movq %r9, 40(%rsp)
movl 224(%rsp), %r12d
movl 232(%rsp), %r13d
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 128(%rsp), %rbx
movl $0, %esi
movq %rbx, %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 136(%rsp), %xmm0
divsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 128(%rsp), %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, 16(%rsp)
movl %r12d, %ebp
imull %r13d, %ebp
sall $2, %ebp
movslq %ebp, %rbp
leaq 56(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 96(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $0, %esi
movq %rbx, %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 136(%rsp), %xmm0
divsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 128(%rsp), %xmm1
addsd %xmm1, %xmm0
subsd 16(%rsp), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %esi
movq %rbx, %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 136(%rsp), %xmm0
divsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 128(%rsp), %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, 16(%rsp)
movl $1, %ecx
movq %rbp, %rdx
movq %r15, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r14, %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq 8(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq 24(%rsp), %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq 32(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq 40(%rsp), %rsi
movq 96(%rsp), %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 136(%rsp), %xmm0
divsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 128(%rsp), %xmm1
addsd %xmm1, %xmm0
subsd 16(%rsp), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %r12d, %xmm0
mulss .LC3(%rip), %xmm0
movaps %xmm0, %xmm1
movss .LC9(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC4(%rip), %xmm4
ucomiss %xmm2, %xmm4
jbe .L20
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm1
movss .LC6(%rip), %xmm4
andps %xmm4, %xmm1
addss %xmm2, %xmm1
andnps %xmm0, %xmm3
orps %xmm3, %xmm1
.L20:
pxor %xmm0, %xmm0
cvtsi2ssl %r13d, %xmm0
mulss .LC7(%rip), %xmm0
movaps %xmm0, %xmm4
movss .LC9(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC4(%rip), %xmm5
ucomiss %xmm2, %xmm5
jbe .L21
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm4
movss .LC6(%rip), %xmm5
andps %xmm5, %xmm4
addss %xmm2, %xmm4
andnps %xmm0, %xmm3
orps %xmm3, %xmm4
.L21:
cvttss2siq %xmm4, %rax
movl %eax, 104(%rsp)
cvttss2siq %xmm1, %rax
movl %eax, 108(%rsp)
movl $1, 112(%rsp)
movl $16, 116(%rsp)
movl $32, 120(%rsp)
movl $1, 124(%rsp)
leaq 128(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 136(%rsp), %xmm0
divsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 128(%rsp), %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, 16(%rsp)
movl $10, %ebx
jmp .L24
.L29:
pushq %r13
.cfi_def_cfa_offset 232
pushq %r12
.cfi_def_cfa_offset 240
movq 88(%rsp), %r9
movq 80(%rsp), %r8
movq 72(%rsp), %rcx
movq 112(%rsp), %rdx
movq 104(%rsp), %rsi
movq 96(%rsp), %rdi
call _Z42__device_stub__Z10kernelBlurPiS_S_S_S_S_iiPiS_S_S_S_S_ii
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L22
.L23:
subl $1, %ebx
je .L28
.L24:
movl 124(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 116(%rsp), %rdx
movq 104(%rsp), %rdi
movl 112(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L22:
movl 124(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 116(%rsp), %rdx
movq 104(%rsp), %rdi
movl 112(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L23
pushq %r13
.cfi_def_cfa_offset 232
pushq %r12
.cfi_def_cfa_offset 240
movq 88(%rsp), %r9
movq 80(%rsp), %r8
movq 72(%rsp), %rcx
movq 112(%rsp), %rdx
movq 104(%rsp), %rsi
movq 96(%rsp), %rdi
call _Z42__device_stub__Z10kernelCopyPiS_S_S_S_S_iiPiS_S_S_S_S_ii
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L23
.L28:
pxor %xmm0, %xmm0
cvtsi2sdq 136(%rsp), %xmm0
divsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 128(%rsp), %xmm1
addsd %xmm1, %xmm0
subsd 16(%rsp), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 56(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 64(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 72(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z12performBlursPiS_S_S_S_S_iii, .-_Z12performBlursPiS_S_S_S_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC10:
.string "r"
.LC11:
.string "sample.ps"
.LC12:
.string "\n%[^\n]"
.LC13:
.string "%2x"
.section .rodata.str1.8
.align 8
.LC14:
.string "Reading Input File > %.6lf seconds elapsed\n"
.section .rodata.str1.1
.LC15:
.string "w"
.LC16:
.string "sampleBlurCU.ps"
.LC17:
.string "\n%s"
.LC18:
.string "\n"
.LC19:
.string "%02x%02x%02x"
.section .rodata.str1.8
.align 8
.LC20:
.string "Outputting File > %.6lf seconds elapsed\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl $891952, %edi
call malloc@PLT
movq %rax, 8(%rsp)
movl $891952, %edi
call malloc@PLT
movq %rax, 16(%rsp)
movl $891952, %edi
call malloc@PLT
movq %rax, 24(%rsp)
movl $891952, %edi
call malloc@PLT
movq %rax, 48(%rsp)
movl $891952, %edi
call malloc@PLT
movq %rax, 56(%rsp)
movl $891952, %edi
call malloc@PLT
movq %rax, %rbp
leaq 96(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 104(%rsp), %xmm0
divsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 96(%rsp), %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, 64(%rsp)
leaq .LC10(%rip), %rsi
leaq .LC11(%rip), %rdi
call fopen@PLT
movq %rax, 32(%rsp)
movl $0, %r12d
movl $0, %r14d
movl $0, %ebx
leaq _ZZ4mainE3str(%rip), %r15
leaq .LC13(%rip), %r13
movq %rbp, 72(%rsp)
.L32:
movq 32(%rsp), %rdi
call feof@PLT
movl %eax, 44(%rsp)
testl %eax, %eax
jne .L53
movq %r15, %rdx
leaq .LC12(%rip), %rsi
movq 32(%rsp), %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $4, %ebx
jg .L54
leal 1(%rbx), %ebp
movslq %ebx, %rbx
leaq (%rbx,%rbx,4), %rax
leaq (%rax,%rax,4), %rax
salq $3, %rax
movl $1000, %edx
cmpq %rdx, %rax
cmovnb %rax, %rdx
subq %rax, %rdx
leaq _ZZ4mainE5lines(%rip), %rsi
leaq (%rax,%rsi), %rdi
movq %r15, %rsi
call __strcpy_chk@PLT
movl %ebp, %ebx
jmp .L32
.L54:
leaq _ZZ4mainE3str(%rip), %rbp
cmpb $0, (%r15)
jne .L34
jmp .L32
.L55:
addl $1, %r14d
movl 44(%rsp), %r12d
jmp .L36
.L37:
addl $1, %r12d
addq $6, %rbp
cmpb $0, 0(%rbp)
je .L32
.L34:
leaq 84(%rsp), %rdx
movq %r13, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_sscanf@PLT
leaq 88(%rsp), %rdx
leaq 2(%rbp), %rdi
movq %r13, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
leaq 92(%rsp), %rdx
leaq 4(%rbp), %rdi
movq %r13, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
cmpl $428, %r12d
je .L55
.L36:
cmpl $520, %r14d
jg .L37
imull $428, %r14d, %eax
addl %r12d, %eax
cltq
movl 84(%rsp), %edx
movq 8(%rsp), %rsi
movl %edx, (%rsi,%rax,4)
movl 88(%rsp), %edx
movq 16(%rsp), %rsi
movl %edx, (%rsi,%rax,4)
movl 92(%rsp), %edx
movq 24(%rsp), %rsi
movl %edx, (%rsi,%rax,4)
jmp .L37
.L53:
movq 72(%rsp), %rbp
movq 32(%rsp), %rdi
call fclose@PLT
leaq 96(%rsp), %r12
movl $0, %esi
movq %r12, %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 104(%rsp), %xmm0
divsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 96(%rsp), %xmm1
addsd %xmm1, %xmm0
subsd 64(%rsp), %xmm0
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
subq $8, %rsp
.cfi_def_cfa_offset 200
pushq $0
.cfi_def_cfa_offset 208
pushq $428
.cfi_def_cfa_offset 216
pushq $521
.cfi_def_cfa_offset 224
movq %rbp, %r9
movq 88(%rsp), %r8
movq 80(%rsp), %rcx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z12performBlursPiS_S_S_S_S_iii
addq $32, %rsp
.cfi_def_cfa_offset 192
movl $0, %esi
movq %r12, %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 104(%rsp), %xmm0
divsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 96(%rsp), %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, 32(%rsp)
leaq .LC15(%rip), %rsi
leaq .LC16(%rip), %rdi
call fopen@PLT
movq %rax, %r12
testl %ebx, %ebx
jle .L39
leaq _ZZ4mainE5lines(%rip), %rbp
movslq %ebx, %rbx
leaq (%rbx,%rbx,4), %rax
leaq (%rax,%rax,4), %rax
leaq 0(%rbp,%rax,8), %r13
leaq .LC17(%rip), %rbx
.L40:
movq %rbp, %rcx
movq %rbx, %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $200, %rbp
cmpq %r13, %rbp
jne .L40
.L39:
leaq .LC18(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 24(%rsp), %rax
movq %rax, %r15
movq 16(%rsp), %r14
movq 8(%rsp), %r13
addq $891952, %rax
movq %rax, 8(%rsp)
movl $0, %ebp
jmp .L41
.L42:
addq $4, %rbx
cmpq $1712, %rbx
je .L56
.L43:
movl 0(%r13,%rbx), %ecx
movl (%r15,%rbx), %r9d
movl (%r14,%rbx), %r8d
leaq .LC19(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1, %ebp
cmpl $12, %ebp
jne .L42
leaq .LC18(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %ebp
jmp .L42
.L56:
addq $1712, %r15
addq $1712, %r14
addq $1712, %r13
movq 8(%rsp), %rax
cmpq %rax, %r15
je .L44
.L41:
movl $0, %ebx
jmp .L43
.L44:
leaq 96(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 104(%rsp), %xmm0
divsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 96(%rsp), %xmm1
addsd %xmm1, %xmm0
subsd 32(%rsp), %xmm0
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r12, %rdi
call fclose@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L57
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L57:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC21:
.string "_Z10kernelCopyPiS_S_S_S_S_ii"
.LC22:
.string "_Z10kernelBlurPiS_S_S_S_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _Z10kernelCopyPiS_S_S_S_S_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC22(%rip), %rdx
movq %rdx, %rcx
leaq _Z10kernelBlurPiS_S_S_S_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZZ4mainE5lines
.comm _ZZ4mainE5lines,1000,32
.local _ZZ4mainE3str
.comm _ZZ4mainE3str,200,32
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 1023410176
.align 4
.LC4:
.long 1258291200
.align 4
.LC6:
.long 1065353216
.align 4
.LC7:
.long 1031798784
.align 4
.LC9:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "blurCUDA.hip"
.globl _Z25__device_stub__kernelBlurPiS_S_S_S_S_ii # -- Begin function _Z25__device_stub__kernelBlurPiS_S_S_S_S_ii
.p2align 4, 0x90
.type _Z25__device_stub__kernelBlurPiS_S_S_S_S_ii,@function
_Z25__device_stub__kernelBlurPiS_S_S_S_S_ii: # @_Z25__device_stub__kernelBlurPiS_S_S_S_S_ii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10kernelBlurPiS_S_S_S_S_ii, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z25__device_stub__kernelBlurPiS_S_S_S_S_ii, .Lfunc_end0-_Z25__device_stub__kernelBlurPiS_S_S_S_S_ii
.cfi_endproc
# -- End function
.globl _Z25__device_stub__kernelCopyPiS_S_S_S_S_ii # -- Begin function _Z25__device_stub__kernelCopyPiS_S_S_S_S_ii
.p2align 4, 0x90
.type _Z25__device_stub__kernelCopyPiS_S_S_S_S_ii,@function
_Z25__device_stub__kernelCopyPiS_S_S_S_S_ii: # @_Z25__device_stub__kernelCopyPiS_S_S_S_S_ii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10kernelCopyPiS_S_S_S_S_ii, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end1:
.size _Z25__device_stub__kernelCopyPiS_S_S_S_S_ii, .Lfunc_end1-_Z25__device_stub__kernelCopyPiS_S_S_S_S_ii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z12performBlursPiS_S_S_S_S_iii
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI2_1:
.long 0x3d800000 # float 0.0625
.LCPI2_2:
.long 0x3d000000 # float 0.03125
.text
.globl _Z12performBlursPiS_S_S_S_S_iii
.p2align 4, 0x90
.type _Z12performBlursPiS_S_S_S_S_iii,@function
_Z12performBlursPiS_S_S_S_S_iii: # @_Z12performBlursPiS_S_S_S_S_iii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 352
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, 96(%rsp) # 8-byte Spill
movq %r8, 88(%rsp) # 8-byte Spill
movq %rcx, 80(%rsp) # 8-byte Spill
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %rbx
movl 352(%rsp), %ebp
movabsq $137438953488, %r13 # imm = 0x2000000010
imull 360(%rsp), %ebp
shll $2, %ebp
leaq 64(%rsp), %r12
movq %r12, %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 64(%rsp), %xmm0
cvtsi2sdq 72(%rsp), %xmm1
divsd .LCPI2_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 104(%rsp) # 8-byte Spill
movslq %ebp, %rbp
leaq 32(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 56(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movq %r12, %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq 64(%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 72(%rsp), %xmm0
divsd .LCPI2_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd 104(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str, %edi
movb $1, %al
callq printf
movq %r12, %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 64(%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 72(%rsp), %xmm1
divsd .LCPI2_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 272(%rsp) # 8-byte Spill
movq 32(%rsp), %rdi
movq %rbx, 280(%rsp) # 8-byte Spill
movq %rbx, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq %r15, 288(%rsp) # 8-byte Spill
movq %r15, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r14, 104(%rsp) # 8-byte Spill
movq %r14, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rdi
movq 80(%rsp), %rsi # 8-byte Reload
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movq 88(%rsp), %rsi # 8-byte Reload
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movq 96(%rsp), %rsi # 8-byte Reload
movq %rbp, 96(%rsp) # 8-byte Spill
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movsd 272(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
subsd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
xorps %xmm0, %xmm0
cvtsi2ssl 360(%rsp), %xmm0
mulss .LCPI2_1(%rip), %xmm0
callq ceilf@PLT
xorps %xmm1, %xmm1
cvtsi2ssl 352(%rsp), %xmm1
cvttss2si %xmm0, %r14
mulss .LCPI2_2(%rip), %xmm1
movaps %xmm1, %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %rbp
movl %r14d, %eax
shlq $32, %rbp
orq %rax, %rbp
movq %r12, %rdi
xorl %esi, %esi
callq gettimeofday
movq 64(%rsp), %rax
movq %rax, 88(%rsp) # 8-byte Spill
movq 72(%rsp), %rax
movq %rax, 80(%rsp) # 8-byte Spill
movl $10, %r14d
leaq 200(%rsp), %r15
leaq 192(%rsp), %r12
leaq 208(%rsp), %rbx
jmp .LBB2_1
.p2align 4, 0x90
.LBB2_5: # in Loop: Header=BB2_1 Depth=1
decl %r14d
je .LBB2_6
.LBB2_1: # =>This Inner Loop Header: Depth=1
movq %rbp, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_3
# %bb.2: # in Loop: Header=BB2_1 Depth=1
movq 56(%rsp), %rax
movq %rax, 184(%rsp)
movq 48(%rsp), %rax
movq %rax, 176(%rsp)
movq 40(%rsp), %rax
movq %rax, 168(%rsp)
movq 32(%rsp), %rax
movq %rax, 160(%rsp)
movq 24(%rsp), %rax
movq %rax, 152(%rsp)
movq 16(%rsp), %rax
movq %rax, 144(%rsp)
movl 352(%rsp), %eax
movl %eax, 12(%rsp)
movl 360(%rsp), %eax
movl %eax, 8(%rsp)
leaq 184(%rsp), %rax
movq %rax, 208(%rsp)
leaq 176(%rsp), %rax
movq %rax, 216(%rsp)
leaq 168(%rsp), %rax
movq %rax, 224(%rsp)
leaq 160(%rsp), %rax
movq %rax, 232(%rsp)
leaq 152(%rsp), %rax
movq %rax, 240(%rsp)
leaq 144(%rsp), %rax
movq %rax, 248(%rsp)
leaq 12(%rsp), %rax
movq %rax, 256(%rsp)
leaq 8(%rsp), %rax
movq %rax, 264(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
movq %r15, %rdx
movq %r12, %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
movl $_Z10kernelBlurPiS_S_S_S_S_ii, %edi
movq %rbx, %r9
pushq 192(%rsp)
.cfi_adjust_cfa_offset 8
pushq 208(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_3: # in Loop: Header=BB2_1 Depth=1
movq %rbp, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4: # in Loop: Header=BB2_1 Depth=1
movq 56(%rsp), %rax
movq %rax, 184(%rsp)
movq 48(%rsp), %rax
movq %rax, 176(%rsp)
movq 40(%rsp), %rax
movq %rax, 168(%rsp)
movq 32(%rsp), %rax
movq %rax, 160(%rsp)
movq 24(%rsp), %rax
movq %rax, 152(%rsp)
movq 16(%rsp), %rax
movq %rax, 144(%rsp)
movl 352(%rsp), %eax
movl %eax, 12(%rsp)
movl 360(%rsp), %eax
movl %eax, 8(%rsp)
leaq 184(%rsp), %rax
movq %rax, 208(%rsp)
leaq 176(%rsp), %rax
movq %rax, 216(%rsp)
leaq 168(%rsp), %rax
movq %rax, 224(%rsp)
leaq 160(%rsp), %rax
movq %rax, 232(%rsp)
leaq 152(%rsp), %rax
movq %rax, 240(%rsp)
leaq 144(%rsp), %rax
movq %rax, 248(%rsp)
leaq 12(%rsp), %rax
movq %rax, 256(%rsp)
leaq 8(%rsp), %rax
movq %rax, 264(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
movq %r15, %rdx
movq %r12, %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
movl $_Z10kernelCopyPiS_S_S_S_S_ii, %edi
movq %rbx, %r9
pushq 192(%rsp)
.cfi_adjust_cfa_offset 8
pushq 208(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_5
.LBB2_6:
xorps %xmm1, %xmm1
cvtsi2sdq 88(%rsp), %xmm1 # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sdq 80(%rsp), %xmm0 # 8-byte Folded Reload
divsd .LCPI2_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rsi
movq 280(%rsp), %rdi # 8-byte Reload
movq 96(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rsi
movq 288(%rsp), %rdi # 8-byte Reload
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rsi
movq 104(%rsp), %rdi # 8-byte Reload
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
addq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z12performBlursPiS_S_S_S_S_iii, .Lfunc_end2-_Z12performBlursPiS_S_S_S_S_iii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $88, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $891952, %edi # imm = 0xD9C30
callq malloc
movq %rax, (%rsp) # 8-byte Spill
movl $891952, %edi # imm = 0xD9C30
callq malloc
movq %rax, %r14
movl $891952, %edi # imm = 0xD9C30
callq malloc
movq %rax, %r15
movl $891952, %edi # imm = 0xD9C30
callq malloc
movq %rax, 80(%rsp) # 8-byte Spill
movl $891952, %edi # imm = 0xD9C30
callq malloc
movq %rax, 72(%rsp) # 8-byte Spill
movl $891952, %edi # imm = 0xD9C30
callq malloc
movq %rax, 64(%rsp) # 8-byte Spill
xorl %r13d, %r13d
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm0
cvtsi2sdq 16(%rsp), %xmm1
divsd .LCPI3_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 56(%rsp) # 8-byte Spill
movl $.L.str.3, %edi
movl $.L.str.4, %esi
callq fopen
movq %rax, %rbx
movq %rax, %rdi
callq feof
testl %eax, %eax
je .LBB3_1
.LBB3_10: # %._crit_edge
movq %rbx, %rdi
callq fclose
leaq 8(%rsp), %r12
movq %r12, %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq 8(%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 16(%rsp), %xmm0
divsd .LCPI3_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd 56(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.7, %edi
movb $1, %al
callq printf
subq $16, %rsp
.cfi_adjust_cfa_offset 16
movq 16(%rsp), %rdi # 8-byte Reload
movq %r14, %rsi
movq %r15, %rdx
movq 96(%rsp), %rcx # 8-byte Reload
movq 88(%rsp), %r8 # 8-byte Reload
movq 80(%rsp), %r9 # 8-byte Reload
pushq $428 # imm = 0x1AC
.cfi_adjust_cfa_offset 8
pushq $521 # imm = 0x209
.cfi_adjust_cfa_offset 8
callq _Z12performBlursPiS_S_S_S_S_iii
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movq %r12, %rdi
xorl %esi, %esi
callq gettimeofday
movq 8(%rsp), %rax
movq %rax, 32(%rsp) # 8-byte Spill
movq 16(%rsp), %rax
movq %rax, 24(%rsp) # 8-byte Spill
movl $.L.str.8, %edi
movl $.L.str.9, %esi
callq fopen
movq %rax, %r12
testl %r13d, %r13d
jle .LBB3_13
# %bb.11: # %.lr.ph93.preheader
movl %r13d, %ebx
movl $_ZZ4mainE5lines, %r13d
.p2align 4, 0x90
.LBB3_12: # %.lr.ph93
# =>This Inner Loop Header: Depth=1
movl $.L.str.10, %esi
movq %r12, %rdi
movq %r13, %rdx
xorl %eax, %eax
callq fprintf
addq $200, %r13
decq %rbx
jne .LBB3_12
.LBB3_13: # %._crit_edge94
movl $10, %edi
movq %r12, %rsi
callq fputc@PLT
xorl %eax, %eax
xorl %ebp, %ebp
movq (%rsp), %rbx # 8-byte Reload
jmp .LBB3_14
.p2align 4, 0x90
.LBB3_18: # in Loop: Header=BB3_14 Depth=1
movq (%rsp), %rax # 8-byte Reload
incq %rax
addq $1712, %r15 # imm = 0x6B0
addq $1712, %r14 # imm = 0x6B0
addq $1712, %rbx # imm = 0x6B0
cmpq $521, %rax # imm = 0x209
je .LBB3_19
.LBB3_14: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_15 Depth 2
movq %rax, (%rsp) # 8-byte Spill
xorl %r13d, %r13d
jmp .LBB3_15
.p2align 4, 0x90
.LBB3_17: # in Loop: Header=BB3_15 Depth=2
incq %r13
cmpq $428, %r13 # imm = 0x1AC
je .LBB3_18
.LBB3_15: # Parent Loop BB3_14 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r13,4), %edx
movl (%r14,%r13,4), %ecx
movl (%r15,%r13,4), %r8d
movl $.L.str.12, %esi
movq %r12, %rdi
xorl %eax, %eax
callq fprintf
incl %ebp
cmpl $12, %ebp
jne .LBB3_17
# %bb.16: # in Loop: Header=BB3_15 Depth=2
movl $10, %edi
movq %r12, %rsi
callq fputc@PLT
xorl %ebp, %ebp
jmp .LBB3_17
.LBB3_19:
xorps %xmm0, %xmm0
cvtsi2sdq 32(%rsp), %xmm0 # 8-byte Folded Reload
cvtsi2sdq 24(%rsp), %xmm1 # 8-byte Folded Reload
divsd .LCPI3_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, (%rsp) # 8-byte Spill
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq 8(%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 16(%rsp), %xmm0
divsd .LCPI3_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd (%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.13, %edi
movb $1, %al
callq printf
movq %r12, %rdi
callq fclose
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_1: # %.lr.ph89.preheader
.cfi_def_cfa_offset 144
xorl %r13d, %r13d
xorl %ebp, %ebp
xorl %r12d, %r12d
movq %rbx, 32(%rsp) # 8-byte Spill
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_20: # in Loop: Header=BB3_2 Depth=1
movslq %r13d, %rax
incl %r13d
imulq $200, %rax, %rax
leaq _ZZ4mainE5lines(%rax), %rdi
movl $_ZZ4mainE3str, %esi
callq strcpy
.LBB3_9: # %.loopexit
# in Loop: Header=BB3_2 Depth=1
movq 32(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
callq feof
testl %eax, %eax
jne .LBB3_10
.LBB3_2: # %.lr.ph89
# =>This Loop Header: Depth=1
# Child Loop BB3_5 Depth 2
movl $.L.str.5, %esi
movl $_ZZ4mainE3str, %edx
movq %rbx, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $5, %r13d
jl .LBB3_20
# %bb.3: # %.preheader79
# in Loop: Header=BB3_2 Depth=1
cmpb $0, _ZZ4mainE3str(%rip)
je .LBB3_9
# %bb.4: # %.lr.ph.preheader
# in Loop: Header=BB3_2 Depth=1
movq %r13, 24(%rsp) # 8-byte Spill
movl $_ZZ4mainE3str, %r13d
jmp .LBB3_5
.p2align 4, 0x90
.LBB3_7: # in Loop: Header=BB3_5 Depth=2
incl %ebp
cmpb $0, 2(%r13)
leaq 2(%r13), %r13
je .LBB3_8
.LBB3_5: # %.lr.ph
# Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movl %r12d, %ebx
movl $.L.str.6, %esi
movq %r13, %rdi
leaq 52(%rsp), %rdx
xorl %eax, %eax
callq __isoc23_sscanf
leaq 2(%r13), %rdi
movl $.L.str.6, %esi
leaq 48(%rsp), %rdx
xorl %eax, %eax
callq __isoc23_sscanf
addq $4, %r13
movl $.L.str.6, %esi
movq %r13, %rdi
leaq 44(%rsp), %rdx
xorl %eax, %eax
callq __isoc23_sscanf
xorl %r12d, %r12d
cmpl $428, %ebp # imm = 0x1AC
sete %r12b
movl $0, %eax
cmovel %eax, %ebp
addl %ebx, %r12d
cmpl $520, %r12d # imm = 0x208
jg .LBB3_7
# %bb.6: # in Loop: Header=BB3_5 Depth=2
movl 52(%rsp), %eax
imull $428, %r12d, %ecx # imm = 0x1AC
addl %ebp, %ecx
movslq %ecx, %rcx
movq (%rsp), %rdx # 8-byte Reload
movl %eax, (%rdx,%rcx,4)
movl 48(%rsp), %eax
movl %eax, (%r14,%rcx,4)
movl 44(%rsp), %eax
movl %eax, (%r15,%rcx,4)
jmp .LBB3_7
.p2align 4, 0x90
.LBB3_8: # in Loop: Header=BB3_2 Depth=1
movq 24(%rsp), %r13 # 8-byte Reload
jmp .LBB3_9
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10kernelBlurPiS_S_S_S_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10kernelCopyPiS_S_S_S_S_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10kernelBlurPiS_S_S_S_S_ii,@object # @_Z10kernelBlurPiS_S_S_S_S_ii
.section .rodata,"a",@progbits
.globl _Z10kernelBlurPiS_S_S_S_S_ii
.p2align 3, 0x0
_Z10kernelBlurPiS_S_S_S_S_ii:
.quad _Z25__device_stub__kernelBlurPiS_S_S_S_S_ii
.size _Z10kernelBlurPiS_S_S_S_S_ii, 8
.type _Z10kernelCopyPiS_S_S_S_S_ii,@object # @_Z10kernelCopyPiS_S_S_S_S_ii
.globl _Z10kernelCopyPiS_S_S_S_S_ii
.p2align 3, 0x0
_Z10kernelCopyPiS_S_S_S_S_ii:
.quad _Z25__device_stub__kernelCopyPiS_S_S_S_S_ii
.size _Z10kernelCopyPiS_S_S_S_S_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Assigning Memory to GPU > %.6lf seconds elapsed\n"
.size .L.str, 49
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Transferring from host to device memory > %.6lf seconds elapsed\n"
.size .L.str.1, 65
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Blurring Operation > %.6lf seconds elapsed\n"
.size .L.str.2, 44
.type _ZZ4mainE3str,@object # @_ZZ4mainE3str
.local _ZZ4mainE3str
.comm _ZZ4mainE3str,200,16
.type _ZZ4mainE5lines,@object # @_ZZ4mainE5lines
.local _ZZ4mainE5lines
.comm _ZZ4mainE5lines,1000,16
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "sample.ps"
.size .L.str.3, 10
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "r"
.size .L.str.4, 2
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\n%[^\n]"
.size .L.str.5, 7
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%2x"
.size .L.str.6, 4
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Reading Input File > %.6lf seconds elapsed\n"
.size .L.str.7, 44
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "sampleBlurCU.ps"
.size .L.str.8, 16
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "w"
.size .L.str.9, 2
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "\n%s"
.size .L.str.10, 4
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "%02x%02x%02x"
.size .L.str.12, 13
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Outputting File > %.6lf seconds elapsed\n"
.size .L.str.13, 41
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10kernelBlurPiS_S_S_S_S_ii"
.size .L__unnamed_1, 29
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10kernelCopyPiS_S_S_S_S_ii"
.size .L__unnamed_2, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__kernelBlurPiS_S_S_S_S_ii
.addrsig_sym _Z25__device_stub__kernelCopyPiS_S_S_S_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10kernelBlurPiS_S_S_S_S_ii
.addrsig_sym _Z10kernelCopyPiS_S_S_S_S_ii
.addrsig_sym _ZZ4mainE3str
.addrsig_sym _ZZ4mainE5lines
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
__global__ void transpose(int *a, int *t){
int n = threadIdx.x, m = blockIdx.x, size = blockDim.x, size1 = gridDim.x;
t[n*size1+m] = a[m*size+n];
}
int main(){
int *a,*t,m,n,i,j,*da,*dt;
printf("Enter m: ");
scanf("%d",&m);
printf("Enter n: ");
scanf("%d",&n);
int size = sizeof(int)*m*n;
a = (int *)malloc(size);
t = (int *)malloc(size);
printf("Enter the matrix:\n");
for(i=0;i<m*n;i++)
scanf("%d",&a[i]);
cudaMalloc((void **)&da,size);
cudaMalloc((void **)&dt,size);
cudaMemcpy(da,a,size,cudaMemcpyHostToDevice);
transpose<<<m,n>>>(da,dt);
cudaMemcpy(t,dt,size,cudaMemcpyDeviceToHost);
printf("Result:\n");
for(i=0;i<n;i++){
for(j=0;j<m;j++)
printf("%d ",t[i*m+j]);
printf("\n");
}
cudaFree(da);
cudaFree(dt);
return 0;
} | code for sm_80
Function : _Z9transposePiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R2, R5, c[0x0][0x0], R4 ; /* 0x0000000005027a24 */
/* 0x001fca00078e0204 */
/*0060*/ IMAD.WIDE R2, R2, R7, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0207 */
/*0070*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD R4, R4, c[0x0][0xc], R5 ; /* 0x0000030004047a24 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.WIDE R4, R4, R7, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0207 */
/*00a0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
__global__ void transpose(int *a, int *t){
int n = threadIdx.x, m = blockIdx.x, size = blockDim.x, size1 = gridDim.x;
t[n*size1+m] = a[m*size+n];
}
int main(){
int *a,*t,m,n,i,j,*da,*dt;
printf("Enter m: ");
scanf("%d",&m);
printf("Enter n: ");
scanf("%d",&n);
int size = sizeof(int)*m*n;
a = (int *)malloc(size);
t = (int *)malloc(size);
printf("Enter the matrix:\n");
for(i=0;i<m*n;i++)
scanf("%d",&a[i]);
cudaMalloc((void **)&da,size);
cudaMalloc((void **)&dt,size);
cudaMemcpy(da,a,size,cudaMemcpyHostToDevice);
transpose<<<m,n>>>(da,dt);
cudaMemcpy(t,dt,size,cudaMemcpyDeviceToHost);
printf("Result:\n");
for(i=0;i<n;i++){
for(j=0;j<m;j++)
printf("%d ",t[i*m+j]);
printf("\n");
}
cudaFree(da);
cudaFree(dt);
return 0;
} | .file "tmpxft_0016d77c_00000000-6_e.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z9transposePiS_PiS_
.type _Z30__device_stub__Z9transposePiS_PiS_, @function
_Z30__device_stub__Z9transposePiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9transposePiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z9transposePiS_PiS_, .-_Z30__device_stub__Z9transposePiS_PiS_
.globl _Z9transposePiS_
.type _Z9transposePiS_, @function
_Z9transposePiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9transposePiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9transposePiS_, .-_Z9transposePiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter m: "
.LC1:
.string "%d"
.LC2:
.string "Enter n: "
.LC3:
.string "Enter the matrix:\n"
.LC4:
.string "Result:\n"
.LC5:
.string "%d "
.LC6:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 8(%rsp), %rsi
leaq .LC1(%rip), %rbx
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 12(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 12(%rsp), %r13d
imull 8(%rsp), %r13d
sall $2, %r13d
movslq %r13d, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %r15
movq %r13, %rdi
call malloc@PLT
movq %rax, %r12
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 8(%rsp), %eax
imull 12(%rsp), %eax
testl %eax, %eax
jle .L12
movq %r15, %rbp
movl $0, %ebx
leaq .LC1(%rip), %r14
.L13:
movq %rbp, %rsi
movq %r14, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
addq $4, %rbp
movl 8(%rsp), %eax
imull 12(%rsp), %eax
cmpl %ebx, %eax
jg .L13
.L12:
leaq 16(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %r15, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl 12(%rsp), %eax
movl %eax, 44(%rsp)
movl $1, 48(%rsp)
movl 8(%rsp), %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L14:
movl $2, %ecx
movq %r13, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebp
leaq .LC5(%rip), %r13
leaq .LC6(%rip), %r14
cmpl $0, 12(%rsp)
jg .L15
.L16:
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z30__device_stub__Z9transposePiS_PiS_
jmp .L14
.L17:
imull %ebp, %eax
addl %ebx, %eax
cltq
movl (%r12,%rax,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
movl 8(%rsp), %eax
cmpl %ebx, %eax
jg .L17
.L18:
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebp
cmpl %ebp, 12(%rsp)
jle .L16
.L15:
movl 8(%rsp), %eax
movl $0, %ebx
testl %eax, %eax
jg .L17
jmp .L18
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z9transposePiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z9transposePiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
__global__ void transpose(int *a, int *t){
int n = threadIdx.x, m = blockIdx.x, size = blockDim.x, size1 = gridDim.x;
t[n*size1+m] = a[m*size+n];
}
int main(){
int *a,*t,m,n,i,j,*da,*dt;
printf("Enter m: ");
scanf("%d",&m);
printf("Enter n: ");
scanf("%d",&n);
int size = sizeof(int)*m*n;
a = (int *)malloc(size);
t = (int *)malloc(size);
printf("Enter the matrix:\n");
for(i=0;i<m*n;i++)
scanf("%d",&a[i]);
cudaMalloc((void **)&da,size);
cudaMalloc((void **)&dt,size);
cudaMemcpy(da,a,size,cudaMemcpyHostToDevice);
transpose<<<m,n>>>(da,dt);
cudaMemcpy(t,dt,size,cudaMemcpyDeviceToHost);
printf("Result:\n");
for(i=0;i<n;i++){
for(j=0;j<m;j++)
printf("%d ",t[i*m+j]);
printf("\n");
}
cudaFree(da);
cudaFree(dt);
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
__global__ void transpose(int *a, int *t){
int n = threadIdx.x, m = blockIdx.x, size = blockDim.x, size1 = gridDim.x;
t[n*size1+m] = a[m*size+n];
}
int main(){
int *a,*t,m,n,i,j,*da,*dt;
printf("Enter m: ");
scanf("%d",&m);
printf("Enter n: ");
scanf("%d",&n);
int size = sizeof(int)*m*n;
a = (int *)malloc(size);
t = (int *)malloc(size);
printf("Enter the matrix:\n");
for(i=0;i<m*n;i++)
scanf("%d",&a[i]);
hipMalloc((void **)&da,size);
hipMalloc((void **)&dt,size);
hipMemcpy(da,a,size,hipMemcpyHostToDevice);
transpose<<<m,n>>>(da,dt);
hipMemcpy(t,dt,size,hipMemcpyDeviceToHost);
printf("Result:\n");
for(i=0;i<n;i++){
for(j=0;j<m;j++)
printf("%d ",t[i*m+j]);
printf("\n");
}
hipFree(da);
hipFree(dt);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
__global__ void transpose(int *a, int *t){
int n = threadIdx.x, m = blockIdx.x, size = blockDim.x, size1 = gridDim.x;
t[n*size1+m] = a[m*size+n];
}
int main(){
int *a,*t,m,n,i,j,*da,*dt;
printf("Enter m: ");
scanf("%d",&m);
printf("Enter n: ");
scanf("%d",&n);
int size = sizeof(int)*m*n;
a = (int *)malloc(size);
t = (int *)malloc(size);
printf("Enter the matrix:\n");
for(i=0;i<m*n;i++)
scanf("%d",&a[i]);
hipMalloc((void **)&da,size);
hipMalloc((void **)&dt,size);
hipMemcpy(da,a,size,hipMemcpyHostToDevice);
transpose<<<m,n>>>(da,dt);
hipMemcpy(t,dt,size,hipMemcpyDeviceToHost);
printf("Result:\n");
for(i=0;i<n;i++){
for(j=0;j<m;j++)
printf("%d ",t[i*m+j]);
printf("\n");
}
hipFree(da);
hipFree(dt);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9transposePiS_
.globl _Z9transposePiS_
.p2align 8
.type _Z9transposePiS_,@function
_Z9transposePiS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_load_b32 s0, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v3, v[1:2], off
v_mad_u64_u32 v[1:2], null, s0, v0, s[2:3]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9transposePiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9transposePiS_, .Lfunc_end0-_Z9transposePiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9transposePiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9transposePiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
__global__ void transpose(int *a, int *t){
int n = threadIdx.x, m = blockIdx.x, size = blockDim.x, size1 = gridDim.x;
t[n*size1+m] = a[m*size+n];
}
int main(){
int *a,*t,m,n,i,j,*da,*dt;
printf("Enter m: ");
scanf("%d",&m);
printf("Enter n: ");
scanf("%d",&n);
int size = sizeof(int)*m*n;
a = (int *)malloc(size);
t = (int *)malloc(size);
printf("Enter the matrix:\n");
for(i=0;i<m*n;i++)
scanf("%d",&a[i]);
hipMalloc((void **)&da,size);
hipMalloc((void **)&dt,size);
hipMemcpy(da,a,size,hipMemcpyHostToDevice);
transpose<<<m,n>>>(da,dt);
hipMemcpy(t,dt,size,hipMemcpyDeviceToHost);
printf("Result:\n");
for(i=0;i<n;i++){
for(j=0;j<m;j++)
printf("%d ",t[i*m+j]);
printf("\n");
}
hipFree(da);
hipFree(dt);
return 0;
} | .text
.file "e.hip"
.globl _Z24__device_stub__transposePiS_ # -- Begin function _Z24__device_stub__transposePiS_
.p2align 4, 0x90
.type _Z24__device_stub__transposePiS_,@function
_Z24__device_stub__transposePiS_: # @_Z24__device_stub__transposePiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9transposePiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__transposePiS_, .Lfunc_end0-_Z24__device_stub__transposePiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 12(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
leaq 8(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 12(%rsp), %eax
imull 8(%rsp), %eax
shll $2, %eax
movslq %eax, %r14
movq %r14, %rdi
callq malloc
movq %rax, %r15
movq %r14, %rdi
callq malloc
movq %rax, %rbx
movl $.Lstr, %edi
callq puts@PLT
movl 8(%rsp), %eax
imull 12(%rsp), %eax
testl %eax, %eax
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movq %r15, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edi
movq %r12, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r13
movslq 12(%rsp), %rax
movslq 8(%rsp), %rcx
imulq %rax, %rcx
addq $4, %r12
cmpq %rcx, %r13
jl .LBB1_2
.LBB1_3: # %._crit_edge
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl 12(%rsp), %edi
movl 8(%rsp), %edx
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9transposePiS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
movq 16(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.1, %edi
callq puts@PLT
cmpl $0, 8(%rsp)
jle .LBB1_11
# %bb.6: # %.preheader.preheader
xorl %ebp, %ebp
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_10: # %._crit_edge29
# in Loop: Header=BB1_7 Depth=1
movl $10, %edi
callq putchar@PLT
incl %ebp
cmpl 8(%rsp), %ebp
jge .LBB1_11
.LBB1_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_9 Depth 2
movl 12(%rsp), %eax
testl %eax, %eax
jle .LBB1_10
# %bb.8: # %.lr.ph28.preheader
# in Loop: Header=BB1_7 Depth=1
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_9: # %.lr.ph28
# Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
imull %ebp, %eax
cltq
addq %r14, %rax
movl (%rbx,%rax,4), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl 12(%rsp), %eax
incq %r14
cmpl %eax, %r14d
jl .LBB1_9
jmp .LBB1_10
.LBB1_11: # %._crit_edge31
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9transposePiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9transposePiS_,@object # @_Z9transposePiS_
.section .rodata,"a",@progbits
.globl _Z9transposePiS_
.p2align 3, 0x0
_Z9transposePiS_:
.quad _Z24__device_stub__transposePiS_
.size _Z9transposePiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter m: "
.size .L.str, 10
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Enter n: "
.size .L.str.2, 10
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d "
.size .L.str.5, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9transposePiS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Enter the matrix:"
.size .Lstr, 18
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Result:"
.size .Lstr.1, 8
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__transposePiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9transposePiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9transposePiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R2, R5, c[0x0][0x0], R4 ; /* 0x0000000005027a24 */
/* 0x001fca00078e0204 */
/*0060*/ IMAD.WIDE R2, R2, R7, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0207 */
/*0070*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD R4, R4, c[0x0][0xc], R5 ; /* 0x0000030004047a24 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.WIDE R4, R4, R7, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0207 */
/*00a0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9transposePiS_
.globl _Z9transposePiS_
.p2align 8
.type _Z9transposePiS_,@function
_Z9transposePiS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_load_b32 s0, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v3, v[1:2], off
v_mad_u64_u32 v[1:2], null, s0, v0, s[2:3]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9transposePiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9transposePiS_, .Lfunc_end0-_Z9transposePiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9transposePiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9transposePiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016d77c_00000000-6_e.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z9transposePiS_PiS_
.type _Z30__device_stub__Z9transposePiS_PiS_, @function
_Z30__device_stub__Z9transposePiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9transposePiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z9transposePiS_PiS_, .-_Z30__device_stub__Z9transposePiS_PiS_
.globl _Z9transposePiS_
.type _Z9transposePiS_, @function
_Z9transposePiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9transposePiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9transposePiS_, .-_Z9transposePiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter m: "
.LC1:
.string "%d"
.LC2:
.string "Enter n: "
.LC3:
.string "Enter the matrix:\n"
.LC4:
.string "Result:\n"
.LC5:
.string "%d "
.LC6:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 8(%rsp), %rsi
leaq .LC1(%rip), %rbx
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 12(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 12(%rsp), %r13d
imull 8(%rsp), %r13d
sall $2, %r13d
movslq %r13d, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %r15
movq %r13, %rdi
call malloc@PLT
movq %rax, %r12
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 8(%rsp), %eax
imull 12(%rsp), %eax
testl %eax, %eax
jle .L12
movq %r15, %rbp
movl $0, %ebx
leaq .LC1(%rip), %r14
.L13:
movq %rbp, %rsi
movq %r14, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
addq $4, %rbp
movl 8(%rsp), %eax
imull 12(%rsp), %eax
cmpl %ebx, %eax
jg .L13
.L12:
leaq 16(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %r15, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl 12(%rsp), %eax
movl %eax, 44(%rsp)
movl $1, 48(%rsp)
movl 8(%rsp), %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L14:
movl $2, %ecx
movq %r13, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebp
leaq .LC5(%rip), %r13
leaq .LC6(%rip), %r14
cmpl $0, 12(%rsp)
jg .L15
.L16:
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z30__device_stub__Z9transposePiS_PiS_
jmp .L14
.L17:
imull %ebp, %eax
addl %ebx, %eax
cltq
movl (%r12,%rax,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
movl 8(%rsp), %eax
cmpl %ebx, %eax
jg .L17
.L18:
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebp
cmpl %ebp, 12(%rsp)
jle .L16
.L15:
movl 8(%rsp), %eax
movl $0, %ebx
testl %eax, %eax
jg .L17
jmp .L18
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z9transposePiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z9transposePiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "e.hip"
.globl _Z24__device_stub__transposePiS_ # -- Begin function _Z24__device_stub__transposePiS_
.p2align 4, 0x90
.type _Z24__device_stub__transposePiS_,@function
_Z24__device_stub__transposePiS_: # @_Z24__device_stub__transposePiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9transposePiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__transposePiS_, .Lfunc_end0-_Z24__device_stub__transposePiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 12(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
leaq 8(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 12(%rsp), %eax
imull 8(%rsp), %eax
shll $2, %eax
movslq %eax, %r14
movq %r14, %rdi
callq malloc
movq %rax, %r15
movq %r14, %rdi
callq malloc
movq %rax, %rbx
movl $.Lstr, %edi
callq puts@PLT
movl 8(%rsp), %eax
imull 12(%rsp), %eax
testl %eax, %eax
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movq %r15, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edi
movq %r12, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r13
movslq 12(%rsp), %rax
movslq 8(%rsp), %rcx
imulq %rax, %rcx
addq $4, %r12
cmpq %rcx, %r13
jl .LBB1_2
.LBB1_3: # %._crit_edge
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl 12(%rsp), %edi
movl 8(%rsp), %edx
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9transposePiS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
movq 16(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.1, %edi
callq puts@PLT
cmpl $0, 8(%rsp)
jle .LBB1_11
# %bb.6: # %.preheader.preheader
xorl %ebp, %ebp
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_10: # %._crit_edge29
# in Loop: Header=BB1_7 Depth=1
movl $10, %edi
callq putchar@PLT
incl %ebp
cmpl 8(%rsp), %ebp
jge .LBB1_11
.LBB1_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_9 Depth 2
movl 12(%rsp), %eax
testl %eax, %eax
jle .LBB1_10
# %bb.8: # %.lr.ph28.preheader
# in Loop: Header=BB1_7 Depth=1
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_9: # %.lr.ph28
# Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
imull %ebp, %eax
cltq
addq %r14, %rax
movl (%rbx,%rax,4), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl 12(%rsp), %eax
incq %r14
cmpl %eax, %r14d
jl .LBB1_9
jmp .LBB1_10
.LBB1_11: # %._crit_edge31
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9transposePiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9transposePiS_,@object # @_Z9transposePiS_
.section .rodata,"a",@progbits
.globl _Z9transposePiS_
.p2align 3, 0x0
_Z9transposePiS_:
.quad _Z24__device_stub__transposePiS_
.size _Z9transposePiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter m: "
.size .L.str, 10
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Enter n: "
.size .L.str.2, 10
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d "
.size .L.str.5, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9transposePiS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Enter the matrix:"
.size .Lstr, 18
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Result:"
.size .Lstr.1, 8
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__transposePiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9transposePiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Babak Poursartip
// 09/28/2020
// section 2: video 20
#include <iostream>
__global__ void print_details_of_warps() {
int gid = blockIdx.y + gridDim.x * blockDim.x + blockIdx.x * blockDim.x +
threadIdx.x;
int warp_id = threadIdx.x / 32;
int gbid = blockIdx.y * gridDim.x + blockIdx.x;
printf(" tid: %d, bid.x: %2d, bid.y: %d, gid: %3d, warp_id: %d, gbid: %d\n",
threadIdx.x, blockIdx.x, blockIdx.y, gid, warp_id, gbid);
}
int main() {
printf(" starts ...\n");
dim3 block(42);
dim3 grid(2, 2);
print_details_of_warps<<<grid, block>>>();
cudaDeviceSynchronize();
printf(" finished \n");
cudaDeviceReset();
return EXIT_SUCCESS;
} | code for sm_80
Function : _Z22print_details_of_warpsv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002500 */
/*0020*/ IADD3 R1, R1, -0x18, RZ ; /* 0xffffffe801017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*0040*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */
/* 0x000e620000002100 */
/*0050*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*0070*/ S2R R12, SR_CTAID.Y ; /* 0x00000000000c7919 */
/* 0x000ea40000002600 */
/*0080*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*0090*/ IADD3 R13, R11, c[0x0][0xc], RZ ; /* 0x000003000b0d7a10 */
/* 0x001fc40007ffe0ff */
/*00a0*/ SHF.R.U32.HI R2, RZ, 0x5, R10 ; /* 0x00000005ff027819 */
/* 0x002fe2000001160a */
/*00b0*/ STL.64 [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0001e20000100a00 */
/*00c0*/ IMAD.IADD R0, R10, 0x1, R12 ; /* 0x000000010a007824 */
/* 0x004fe400078e020c */
/*00d0*/ IMAD R3, R12, c[0x0][0xc], R11 ; /* 0x000003000c037a24 */
/* 0x000fe400078e020b */
/*00e0*/ IMAD R13, R13, c[0x0][0x0], R0 ; /* 0x000000000d0d7a24 */
/* 0x000fe200078e0200 */
/*00f0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0100*/ STL.64 [R1+0x10], R2 ; /* 0x0000100201007387 */
/* 0x0001e40000100a00 */
/*0110*/ LDC.64 R8, c[0x4][R0] ; /* 0x0100000000087b82 */
/* 0x0000640000000a00 */
/*0120*/ STL.64 [R1+0x8], R12 ; /* 0x0000080c01007387 */
/* 0x0001e40000100a00 */
/*0130*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x001fe40000000000 */
/*0140*/ MOV R11, 0x1b0 ; /* 0x000001b0000b7802 */
/* 0x000fe40000000f00 */
/*0150*/ MOV R20, 0x130 ; /* 0x0000013000147802 */
/* 0x000fc40000000f00 */
/*0160*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0170*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0180*/ IADD3 R20, P0, P1, -R20, R11, R2 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e102 */
/*0190*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*01a0*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x002fea0003c00000 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Babak Poursartip
// 09/28/2020
// section 2: video 20
#include <iostream>
__global__ void print_details_of_warps() {
int gid = blockIdx.y + gridDim.x * blockDim.x + blockIdx.x * blockDim.x +
threadIdx.x;
int warp_id = threadIdx.x / 32;
int gbid = blockIdx.y * gridDim.x + blockIdx.x;
printf(" tid: %d, bid.x: %2d, bid.y: %d, gid: %3d, warp_id: %d, gbid: %d\n",
threadIdx.x, blockIdx.x, blockIdx.y, gid, warp_id, gbid);
}
int main() {
printf(" starts ...\n");
dim3 block(42);
dim3 grid(2, 2);
print_details_of_warps<<<grid, block>>>();
cudaDeviceSynchronize();
printf(" finished \n");
cudaDeviceReset();
return EXIT_SUCCESS;
} | .file "tmpxft_00071efc_00000000-6_1_warp_id_thread_id.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z22print_details_of_warpsvv
.type _Z41__device_stub__Z22print_details_of_warpsvv, @function
_Z41__device_stub__Z22print_details_of_warpsvv:
.LFB3694:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z22print_details_of_warpsv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z41__device_stub__Z22print_details_of_warpsvv, .-_Z41__device_stub__Z22print_details_of_warpsvv
.globl _Z22print_details_of_warpsv
.type _Z22print_details_of_warpsv, @function
_Z22print_details_of_warpsv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z22print_details_of_warpsvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z22print_details_of_warpsv, .-_Z22print_details_of_warpsv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " starts ...\n"
.LC1:
.string " finished \n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $42, 8(%rsp)
movl $1, 12(%rsp)
movl $2, 20(%rsp)
movl $2, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z41__device_stub__Z22print_details_of_warpsvv
jmp .L12
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z22print_details_of_warpsv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z22print_details_of_warpsv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Babak Poursartip
// 09/28/2020
// section 2: video 20
#include <iostream>
__global__ void print_details_of_warps() {
int gid = blockIdx.y + gridDim.x * blockDim.x + blockIdx.x * blockDim.x +
threadIdx.x;
int warp_id = threadIdx.x / 32;
int gbid = blockIdx.y * gridDim.x + blockIdx.x;
printf(" tid: %d, bid.x: %2d, bid.y: %d, gid: %3d, warp_id: %d, gbid: %d\n",
threadIdx.x, blockIdx.x, blockIdx.y, gid, warp_id, gbid);
}
int main() {
printf(" starts ...\n");
dim3 block(42);
dim3 grid(2, 2);
print_details_of_warps<<<grid, block>>>();
cudaDeviceSynchronize();
printf(" finished \n");
cudaDeviceReset();
return EXIT_SUCCESS;
} | // Babak Poursartip
// 09/28/2020
// section 2: video 20
#include <hip/hip_runtime.h>
#include <iostream>
__global__ void print_details_of_warps() {
int gid = blockIdx.y + gridDim.x * blockDim.x + blockIdx.x * blockDim.x +
threadIdx.x;
int warp_id = threadIdx.x / 32;
int gbid = blockIdx.y * gridDim.x + blockIdx.x;
printf(" tid: %d, bid.x: %2d, bid.y: %d, gid: %3d, warp_id: %d, gbid: %d\n",
threadIdx.x, blockIdx.x, blockIdx.y, gid, warp_id, gbid);
}
int main() {
printf(" starts ...\n");
dim3 block(42);
dim3 grid(2, 2);
print_details_of_warps<<<grid, block>>>();
hipDeviceSynchronize();
printf(" finished \n");
hipDeviceReset();
return EXIT_SUCCESS;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Babak Poursartip
// 09/28/2020
// section 2: video 20
#include <hip/hip_runtime.h>
#include <iostream>
__global__ void print_details_of_warps() {
int gid = blockIdx.y + gridDim.x * blockDim.x + blockIdx.x * blockDim.x +
threadIdx.x;
int warp_id = threadIdx.x / 32;
int gbid = blockIdx.y * gridDim.x + blockIdx.x;
printf(" tid: %d, bid.x: %2d, bid.y: %d, gid: %3d, warp_id: %d, gbid: %d\n",
threadIdx.x, blockIdx.x, blockIdx.y, gid, warp_id, gbid);
}
int main() {
printf(" starts ...\n");
dim3 block(42);
dim3 grid(2, 2);
print_details_of_warps<<<grid, block>>>();
hipDeviceSynchronize();
printf(" finished \n");
hipDeviceReset();
return EXIT_SUCCESS;
} | .text
.file "1_warp_id_thread_id.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z37__device_stub__print_details_of_warpsv # -- Begin function _Z37__device_stub__print_details_of_warpsv
.p2align 4, 0x90
.type _Z37__device_stub__print_details_of_warpsv,@function
_Z37__device_stub__print_details_of_warpsv: # @_Z37__device_stub__print_details_of_warpsv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z22print_details_of_warpsv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z37__device_stub__print_details_of_warpsv, .Lfunc_end0-_Z37__device_stub__print_details_of_warpsv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.Lstr, %edi
callq puts@PLT
movabsq $8589934594, %rdi # imm = 0x200000002
movabsq $4294967338, %rdx # imm = 0x10000002A
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z22print_details_of_warpsv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movl $.Lstr.1, %edi
callq puts@PLT
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22print_details_of_warpsv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22print_details_of_warpsv,@object # @_Z22print_details_of_warpsv
.section .rodata,"a",@progbits
.globl _Z22print_details_of_warpsv
.p2align 3, 0x0
_Z22print_details_of_warpsv:
.quad _Z37__device_stub__print_details_of_warpsv
.size _Z22print_details_of_warpsv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z22print_details_of_warpsv"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz " starts ..."
.size .Lstr, 12
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz " finished "
.size .Lstr.1, 11
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__print_details_of_warpsv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22print_details_of_warpsv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00071efc_00000000-6_1_warp_id_thread_id.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z22print_details_of_warpsvv
.type _Z41__device_stub__Z22print_details_of_warpsvv, @function
_Z41__device_stub__Z22print_details_of_warpsvv:
.LFB3694:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z22print_details_of_warpsv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z41__device_stub__Z22print_details_of_warpsvv, .-_Z41__device_stub__Z22print_details_of_warpsvv
.globl _Z22print_details_of_warpsv
.type _Z22print_details_of_warpsv, @function
_Z22print_details_of_warpsv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z22print_details_of_warpsvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z22print_details_of_warpsv, .-_Z22print_details_of_warpsv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " starts ...\n"
.LC1:
.string " finished \n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $42, 8(%rsp)
movl $1, 12(%rsp)
movl $2, 20(%rsp)
movl $2, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z41__device_stub__Z22print_details_of_warpsvv
jmp .L12
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z22print_details_of_warpsv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z22print_details_of_warpsv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "1_warp_id_thread_id.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z37__device_stub__print_details_of_warpsv # -- Begin function _Z37__device_stub__print_details_of_warpsv
.p2align 4, 0x90
.type _Z37__device_stub__print_details_of_warpsv,@function
_Z37__device_stub__print_details_of_warpsv: # @_Z37__device_stub__print_details_of_warpsv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z22print_details_of_warpsv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z37__device_stub__print_details_of_warpsv, .Lfunc_end0-_Z37__device_stub__print_details_of_warpsv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.Lstr, %edi
callq puts@PLT
movabsq $8589934594, %rdi # imm = 0x200000002
movabsq $4294967338, %rdx # imm = 0x10000002A
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z22print_details_of_warpsv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movl $.Lstr.1, %edi
callq puts@PLT
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22print_details_of_warpsv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22print_details_of_warpsv,@object # @_Z22print_details_of_warpsv
.section .rodata,"a",@progbits
.globl _Z22print_details_of_warpsv
.p2align 3, 0x0
_Z22print_details_of_warpsv:
.quad _Z37__device_stub__print_details_of_warpsv
.size _Z22print_details_of_warpsv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z22print_details_of_warpsv"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz " starts ..."
.size .Lstr, 12
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz " finished "
.size .Lstr.1, 11
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__print_details_of_warpsv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22print_details_of_warpsv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void shiftRightPixels(int16_t *bayImg, size_t width, size_t height, int bppMult)
{
int2 pixelCoord = make_int2(blockIdx.x * blockDim.x + threadIdx.x, blockIdx.y * blockDim.y + threadIdx.y);
if (pixelCoord.x < width && pixelCoord.y < height)
{
bayImg[pixelCoord.y * width + pixelCoord.x] >>= bppMult;
}
} | code for sm_80
Function : _Z16shiftRightPixelsPsmmi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002200 */
/*0030*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R0 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.U32.AND P1, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fe40003f26070 */
/*0070*/ SHF.R.S32.HI R0, RZ, 0x1f, R3 ; /* 0x0000001fff007819 */
/* 0x000fe20000011403 */
/*0080*/ IMAD R4, R4, c[0x0][0x0], R5 ; /* 0x0000000004047a24 */
/* 0x002fc600078e0205 */
/*0090*/ ISETP.GE.U32.AND.EX P1, PT, R0, c[0x0][0x174], PT, P1 ; /* 0x00005d0000007a0c */
/* 0x000fe40003f26110 */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x000fe40003f06070 */
/*00b0*/ SHF.R.S32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x000fc80000011404 */
/*00c0*/ ISETP.GE.U32.OR.EX P0, PT, R5, c[0x0][0x16c], P1, P0 ; /* 0x00005b0005007a0c */
/* 0x000fda0000f06500 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ IMAD R0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000007a24 */
/* 0x000fe200078e02ff */
/*00f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0100*/ IMAD.WIDE.U32 R4, R3, c[0x0][0x168], R4 ; /* 0x00005a0003047a25 */
/* 0x000fc800078e0004 */
/*0110*/ IMAD R3, R3, c[0x0][0x16c], R0 ; /* 0x00005b0003037a24 */
/* 0x000fe200078e0200 */
/*0120*/ LEA R2, P0, R4, c[0x0][0x160], 0x1 ; /* 0x0000580004027a11 */
/* 0x000fc600078008ff */
/*0130*/ IMAD.IADD R3, R5, 0x1, R3 ; /* 0x0000000105037824 */
/* 0x000fca00078e0203 */
/*0140*/ LEA.HI.X R3, R4, c[0x0][0x164], R3, 0x1, P0 ; /* 0x0000590004037a11 */
/* 0x000fca00000f0c03 */
/*0150*/ LDG.E.S16 R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1700 */
/*0160*/ SHF.R.S32.HI R5, RZ, c[0x0][0x178], R0 ; /* 0x00005e00ff057a19 */
/* 0x004fca0000011400 */
/*0170*/ STG.E.U16 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101504 */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
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