system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void shiftRightPixels(int16_t *bayImg, size_t width, size_t height, int bppMult)
{
int2 pixelCoord = make_int2(blockIdx.x * blockDim.x + threadIdx.x, blockIdx.y * blockDim.y + threadIdx.y);
if (pixelCoord.x < width && pixelCoord.y < height)
{
bayImg[pixelCoord.y * width + pixelCoord.x] >>= bppMult;
}
} | .file "tmpxft_0014bbdc_00000000-6_shiftRightPixels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z16shiftRightPixelsPsmmiPsmmi
.type _Z39__device_stub__Z16shiftRightPixelsPsmmiPsmmi, @function
_Z39__device_stub__Z16shiftRightPixelsPsmmiPsmmi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16shiftRightPixelsPsmmi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z16shiftRightPixelsPsmmiPsmmi, .-_Z39__device_stub__Z16shiftRightPixelsPsmmiPsmmi
.globl _Z16shiftRightPixelsPsmmi
.type _Z16shiftRightPixelsPsmmi, @function
_Z16shiftRightPixelsPsmmi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z16shiftRightPixelsPsmmiPsmmi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16shiftRightPixelsPsmmi, .-_Z16shiftRightPixelsPsmmi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16shiftRightPixelsPsmmi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16shiftRightPixelsPsmmi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void shiftRightPixels(int16_t *bayImg, size_t width, size_t height, int bppMult)
{
int2 pixelCoord = make_int2(blockIdx.x * blockDim.x + threadIdx.x, blockIdx.y * blockDim.y + threadIdx.y);
if (pixelCoord.x < width && pixelCoord.y < height)
{
bayImg[pixelCoord.y * width + pixelCoord.x] >>= bppMult;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void shiftRightPixels(int16_t *bayImg, size_t width, size_t height, int bppMult)
{
int2 pixelCoord = make_int2(blockIdx.x * blockDim.x + threadIdx.x, blockIdx.y * blockDim.y + threadIdx.y);
if (pixelCoord.x < width && pixelCoord.y < height)
{
bayImg[pixelCoord.y * width + pixelCoord.x] >>= bppMult;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void shiftRightPixels(int16_t *bayImg, size_t width, size_t height, int bppMult)
{
int2 pixelCoord = make_int2(blockIdx.x * blockDim.x + threadIdx.x, blockIdx.y * blockDim.y + threadIdx.y);
if (pixelCoord.x < width && pixelCoord.y < height)
{
bayImg[pixelCoord.y * width + pixelCoord.x] >>= bppMult;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16shiftRightPixelsPsmmi
.globl _Z16shiftRightPixelsPsmmi
.p2align 8
.type _Z16shiftRightPixelsPsmmi,@function
_Z16shiftRightPixelsPsmmi:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x8
v_and_b32_e32 v3, 0x3ff, v0
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s6, v[3:4]
s_mov_b32 s6, exec_lo
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_3
s_load_b32 s6, s[4:5], 0xc
s_load_b64 s[4:5], s[0:1], 0x10
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s6, s6, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, s15, s6, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[3:4]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_3
s_load_b64 s[4:5], s[0:1], 0x0
v_mul_lo_u32 v0, v4, s2
v_mul_lo_u32 v6, v3, s3
v_mad_u64_u32 v[4:5], null, v3, s2, 0
s_load_b32 s0, s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add3_u32 v5, v5, v6, v0
v_lshlrev_b64 v[0:1], 1, v[1:2]
v_lshlrev_b64 v[3:4], 1, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo
global_load_i16 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v2, s0, v2
global_store_b16 v[0:1], v2, off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16shiftRightPixelsPsmmi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16shiftRightPixelsPsmmi, .Lfunc_end0-_Z16shiftRightPixelsPsmmi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16shiftRightPixelsPsmmi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16shiftRightPixelsPsmmi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void shiftRightPixels(int16_t *bayImg, size_t width, size_t height, int bppMult)
{
int2 pixelCoord = make_int2(blockIdx.x * blockDim.x + threadIdx.x, blockIdx.y * blockDim.y + threadIdx.y);
if (pixelCoord.x < width && pixelCoord.y < height)
{
bayImg[pixelCoord.y * width + pixelCoord.x] >>= bppMult;
}
} | .text
.file "shiftRightPixels.hip"
.globl _Z31__device_stub__shiftRightPixelsPsmmi # -- Begin function _Z31__device_stub__shiftRightPixelsPsmmi
.p2align 4, 0x90
.type _Z31__device_stub__shiftRightPixelsPsmmi,@function
_Z31__device_stub__shiftRightPixelsPsmmi: # @_Z31__device_stub__shiftRightPixelsPsmmi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16shiftRightPixelsPsmmi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z31__device_stub__shiftRightPixelsPsmmi, .Lfunc_end0-_Z31__device_stub__shiftRightPixelsPsmmi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16shiftRightPixelsPsmmi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16shiftRightPixelsPsmmi,@object # @_Z16shiftRightPixelsPsmmi
.section .rodata,"a",@progbits
.globl _Z16shiftRightPixelsPsmmi
.p2align 3, 0x0
_Z16shiftRightPixelsPsmmi:
.quad _Z31__device_stub__shiftRightPixelsPsmmi
.size _Z16shiftRightPixelsPsmmi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16shiftRightPixelsPsmmi"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__shiftRightPixelsPsmmi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16shiftRightPixelsPsmmi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16shiftRightPixelsPsmmi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002200 */
/*0030*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R0 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.U32.AND P1, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fe40003f26070 */
/*0070*/ SHF.R.S32.HI R0, RZ, 0x1f, R3 ; /* 0x0000001fff007819 */
/* 0x000fe20000011403 */
/*0080*/ IMAD R4, R4, c[0x0][0x0], R5 ; /* 0x0000000004047a24 */
/* 0x002fc600078e0205 */
/*0090*/ ISETP.GE.U32.AND.EX P1, PT, R0, c[0x0][0x174], PT, P1 ; /* 0x00005d0000007a0c */
/* 0x000fe40003f26110 */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x000fe40003f06070 */
/*00b0*/ SHF.R.S32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x000fc80000011404 */
/*00c0*/ ISETP.GE.U32.OR.EX P0, PT, R5, c[0x0][0x16c], P1, P0 ; /* 0x00005b0005007a0c */
/* 0x000fda0000f06500 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ IMAD R0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000007a24 */
/* 0x000fe200078e02ff */
/*00f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0100*/ IMAD.WIDE.U32 R4, R3, c[0x0][0x168], R4 ; /* 0x00005a0003047a25 */
/* 0x000fc800078e0004 */
/*0110*/ IMAD R3, R3, c[0x0][0x16c], R0 ; /* 0x00005b0003037a24 */
/* 0x000fe200078e0200 */
/*0120*/ LEA R2, P0, R4, c[0x0][0x160], 0x1 ; /* 0x0000580004027a11 */
/* 0x000fc600078008ff */
/*0130*/ IMAD.IADD R3, R5, 0x1, R3 ; /* 0x0000000105037824 */
/* 0x000fca00078e0203 */
/*0140*/ LEA.HI.X R3, R4, c[0x0][0x164], R3, 0x1, P0 ; /* 0x0000590004037a11 */
/* 0x000fca00000f0c03 */
/*0150*/ LDG.E.S16 R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1700 */
/*0160*/ SHF.R.S32.HI R5, RZ, c[0x0][0x178], R0 ; /* 0x00005e00ff057a19 */
/* 0x004fca0000011400 */
/*0170*/ STG.E.U16 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101504 */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16shiftRightPixelsPsmmi
.globl _Z16shiftRightPixelsPsmmi
.p2align 8
.type _Z16shiftRightPixelsPsmmi,@function
_Z16shiftRightPixelsPsmmi:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x8
v_and_b32_e32 v3, 0x3ff, v0
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s6, v[3:4]
s_mov_b32 s6, exec_lo
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_3
s_load_b32 s6, s[4:5], 0xc
s_load_b64 s[4:5], s[0:1], 0x10
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s6, s6, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, s15, s6, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[3:4]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_3
s_load_b64 s[4:5], s[0:1], 0x0
v_mul_lo_u32 v0, v4, s2
v_mul_lo_u32 v6, v3, s3
v_mad_u64_u32 v[4:5], null, v3, s2, 0
s_load_b32 s0, s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add3_u32 v5, v5, v6, v0
v_lshlrev_b64 v[0:1], 1, v[1:2]
v_lshlrev_b64 v[3:4], 1, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo
global_load_i16 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v2, s0, v2
global_store_b16 v[0:1], v2, off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16shiftRightPixelsPsmmi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16shiftRightPixelsPsmmi, .Lfunc_end0-_Z16shiftRightPixelsPsmmi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16shiftRightPixelsPsmmi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16shiftRightPixelsPsmmi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014bbdc_00000000-6_shiftRightPixels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z16shiftRightPixelsPsmmiPsmmi
.type _Z39__device_stub__Z16shiftRightPixelsPsmmiPsmmi, @function
_Z39__device_stub__Z16shiftRightPixelsPsmmiPsmmi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16shiftRightPixelsPsmmi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z16shiftRightPixelsPsmmiPsmmi, .-_Z39__device_stub__Z16shiftRightPixelsPsmmiPsmmi
.globl _Z16shiftRightPixelsPsmmi
.type _Z16shiftRightPixelsPsmmi, @function
_Z16shiftRightPixelsPsmmi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z16shiftRightPixelsPsmmiPsmmi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16shiftRightPixelsPsmmi, .-_Z16shiftRightPixelsPsmmi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16shiftRightPixelsPsmmi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16shiftRightPixelsPsmmi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "shiftRightPixels.hip"
.globl _Z31__device_stub__shiftRightPixelsPsmmi # -- Begin function _Z31__device_stub__shiftRightPixelsPsmmi
.p2align 4, 0x90
.type _Z31__device_stub__shiftRightPixelsPsmmi,@function
_Z31__device_stub__shiftRightPixelsPsmmi: # @_Z31__device_stub__shiftRightPixelsPsmmi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16shiftRightPixelsPsmmi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z31__device_stub__shiftRightPixelsPsmmi, .Lfunc_end0-_Z31__device_stub__shiftRightPixelsPsmmi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16shiftRightPixelsPsmmi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16shiftRightPixelsPsmmi,@object # @_Z16shiftRightPixelsPsmmi
.section .rodata,"a",@progbits
.globl _Z16shiftRightPixelsPsmmi
.p2align 3, 0x0
_Z16shiftRightPixelsPsmmi:
.quad _Z31__device_stub__shiftRightPixelsPsmmi
.size _Z16shiftRightPixelsPsmmi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16shiftRightPixelsPsmmi"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__shiftRightPixelsPsmmi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16shiftRightPixelsPsmmi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <stdlib.h>
using namespace std;
#define CUDA true
__global__ void multiadd(int N, float a, float* x, float* y);
int main(int argc, char* argv[]){
cout << "This is test CUDA in visual studio!" << endl;
int N = 1 << 20;
int size = sizeof(float) * N;
float* x = (float*)malloc(size);
float* y = (float*)malloc(size);
float *dx, *dy;
cudaMalloc(&dx, size);
cudaMalloc(&dy, size);
for (int i = 0; i < N; i++){
x[i] = 1.0;
y[i] = 2.0;
}
if (CUDA){
cudaMemcpy(dx, x, size, cudaMemcpyHostToDevice);
cudaMemcpy(dy, y, size, cudaMemcpyHostToDevice);
multiadd <<< (N + 255) / 256, 256 >>>(N, 3, dx, dy);
cudaMemcpy(y, dy, size, cudaMemcpyDeviceToHost);
}
else{
for (int i = 0; i < N; i++){
y[i] = 3 * x[i] + y[i];
}
}
int counter = 0;
for (int i = 0; i < N; i++){
if (y[i] != 5.0) counter++;
}
cout << "Error number is: " << counter << endl;
return 0;
}
__global__ void multiadd(int N, float a, float* x, float* y){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N) y[i] = a * x[i] + y[i];
} | code for sm_80
Function : _Z8multiaddifPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe400078e0205 */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ FFMA R7, R2, c[0x0][0x164], R7 ; /* 0x0000590002077a23 */
/* 0x004fca0000000007 */
/*00d0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <stdlib.h>
using namespace std;
#define CUDA true
__global__ void multiadd(int N, float a, float* x, float* y);
int main(int argc, char* argv[]){
cout << "This is test CUDA in visual studio!" << endl;
int N = 1 << 20;
int size = sizeof(float) * N;
float* x = (float*)malloc(size);
float* y = (float*)malloc(size);
float *dx, *dy;
cudaMalloc(&dx, size);
cudaMalloc(&dy, size);
for (int i = 0; i < N; i++){
x[i] = 1.0;
y[i] = 2.0;
}
if (CUDA){
cudaMemcpy(dx, x, size, cudaMemcpyHostToDevice);
cudaMemcpy(dy, y, size, cudaMemcpyHostToDevice);
multiadd <<< (N + 255) / 256, 256 >>>(N, 3, dx, dy);
cudaMemcpy(y, dy, size, cudaMemcpyDeviceToHost);
}
else{
for (int i = 0; i < N; i++){
y[i] = 3 * x[i] + y[i];
}
}
int counter = 0;
for (int i = 0; i < N; i++){
if (y[i] != 5.0) counter++;
}
cout << "Error number is: " << counter << endl;
return 0;
}
__global__ void multiadd(int N, float a, float* x, float* y){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N) y[i] = a * x[i] + y[i];
} | .file "tmpxft_001041eb_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z8multiaddifPfS_ifPfS_
.type _Z31__device_stub__Z8multiaddifPfS_ifPfS_, @function
_Z31__device_stub__Z8multiaddifPfS_ifPfS_:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movss %xmm0, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8multiaddifPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z31__device_stub__Z8multiaddifPfS_ifPfS_, .-_Z31__device_stub__Z8multiaddifPfS_ifPfS_
.globl _Z8multiaddifPfS_
.type _Z8multiaddifPfS_, @function
_Z8multiaddifPfS_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8multiaddifPfS_ifPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z8multiaddifPfS_, .-_Z8multiaddifPfS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "This is test CUDA in visual studio!"
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "Error number is: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movq %rsp, %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $0, %eax
movss .LC1(%rip), %xmm1
movss .LC2(%rip), %xmm0
.L12:
movss %xmm1, 0(%rbp,%rax)
movss %xmm0, (%rbx,%rax)
addq $4, %rax
cmpq $4194304, %rax
jne .L12
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $4096, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L13:
movl $2, %ecx
movl $4194304, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rax
addq $4194304, %rbx
movl $0, %ebp
jmp .L16
.L22:
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movss .LC3(%rip), %xmm0
movl $1048576, %edi
call _Z31__device_stub__Z8multiaddifPfS_ifPfS_
jmp .L13
.L18:
addl $1, %ebp
.L14:
addq $4, %rax
cmpq %rbx, %rax
je .L23
.L16:
movss (%rax), %xmm0
ucomiss .LC4(%rip), %xmm0
jp .L18
je .L14
jmp .L18
.L23:
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebp, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z8multiaddifPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z8multiaddifPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1073741824
.align 4
.LC3:
.long 1077936128
.align 4
.LC4:
.long 1084227584
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <stdlib.h>
using namespace std;
#define CUDA true
__global__ void multiadd(int N, float a, float* x, float* y);
int main(int argc, char* argv[]){
cout << "This is test CUDA in visual studio!" << endl;
int N = 1 << 20;
int size = sizeof(float) * N;
float* x = (float*)malloc(size);
float* y = (float*)malloc(size);
float *dx, *dy;
cudaMalloc(&dx, size);
cudaMalloc(&dy, size);
for (int i = 0; i < N; i++){
x[i] = 1.0;
y[i] = 2.0;
}
if (CUDA){
cudaMemcpy(dx, x, size, cudaMemcpyHostToDevice);
cudaMemcpy(dy, y, size, cudaMemcpyHostToDevice);
multiadd <<< (N + 255) / 256, 256 >>>(N, 3, dx, dy);
cudaMemcpy(y, dy, size, cudaMemcpyDeviceToHost);
}
else{
for (int i = 0; i < N; i++){
y[i] = 3 * x[i] + y[i];
}
}
int counter = 0;
for (int i = 0; i < N; i++){
if (y[i] != 5.0) counter++;
}
cout << "Error number is: " << counter << endl;
return 0;
}
__global__ void multiadd(int N, float a, float* x, float* y){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N) y[i] = a * x[i] + y[i];
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdlib.h>
using namespace std;
#define CUDA true
__global__ void multiadd(int N, float a, float* x, float* y);
int main(int argc, char* argv[]){
cout << "This is test CUDA in visual studio!" << endl;
int N = 1 << 20;
int size = sizeof(float) * N;
float* x = (float*)malloc(size);
float* y = (float*)malloc(size);
float *dx, *dy;
hipMalloc(&dx, size);
hipMalloc(&dy, size);
for (int i = 0; i < N; i++){
x[i] = 1.0;
y[i] = 2.0;
}
if (CUDA){
hipMemcpy(dx, x, size, hipMemcpyHostToDevice);
hipMemcpy(dy, y, size, hipMemcpyHostToDevice);
multiadd <<< (N + 255) / 256, 256 >>>(N, 3, dx, dy);
hipMemcpy(y, dy, size, hipMemcpyDeviceToHost);
}
else{
for (int i = 0; i < N; i++){
y[i] = 3 * x[i] + y[i];
}
}
int counter = 0;
for (int i = 0; i < N; i++){
if (y[i] != 5.0) counter++;
}
cout << "Error number is: " << counter << endl;
return 0;
}
__global__ void multiadd(int N, float a, float* x, float* y){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N) y[i] = a * x[i] + y[i];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdlib.h>
using namespace std;
#define CUDA true
__global__ void multiadd(int N, float a, float* x, float* y);
int main(int argc, char* argv[]){
cout << "This is test CUDA in visual studio!" << endl;
int N = 1 << 20;
int size = sizeof(float) * N;
float* x = (float*)malloc(size);
float* y = (float*)malloc(size);
float *dx, *dy;
hipMalloc(&dx, size);
hipMalloc(&dy, size);
for (int i = 0; i < N; i++){
x[i] = 1.0;
y[i] = 2.0;
}
if (CUDA){
hipMemcpy(dx, x, size, hipMemcpyHostToDevice);
hipMemcpy(dy, y, size, hipMemcpyHostToDevice);
multiadd <<< (N + 255) / 256, 256 >>>(N, 3, dx, dy);
hipMemcpy(y, dy, size, hipMemcpyDeviceToHost);
}
else{
for (int i = 0; i < N; i++){
y[i] = 3 * x[i] + y[i];
}
}
int counter = 0;
for (int i = 0; i < N; i++){
if (y[i] != 5.0) counter++;
}
cout << "Error number is: " << counter << endl;
return 0;
}
__global__ void multiadd(int N, float a, float* x, float* y){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N) y[i] = a * x[i] + y[i];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8multiaddifPfS_
.globl _Z8multiaddifPfS_
.p2align 8
.type _Z8multiaddifPfS_,@function
_Z8multiaddifPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, s0, v2
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8multiaddifPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8multiaddifPfS_, .Lfunc_end0-_Z8multiaddifPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8multiaddifPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8multiaddifPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdlib.h>
using namespace std;
#define CUDA true
__global__ void multiadd(int N, float a, float* x, float* y);
int main(int argc, char* argv[]){
cout << "This is test CUDA in visual studio!" << endl;
int N = 1 << 20;
int size = sizeof(float) * N;
float* x = (float*)malloc(size);
float* y = (float*)malloc(size);
float *dx, *dy;
hipMalloc(&dx, size);
hipMalloc(&dy, size);
for (int i = 0; i < N; i++){
x[i] = 1.0;
y[i] = 2.0;
}
if (CUDA){
hipMemcpy(dx, x, size, hipMemcpyHostToDevice);
hipMemcpy(dy, y, size, hipMemcpyHostToDevice);
multiadd <<< (N + 255) / 256, 256 >>>(N, 3, dx, dy);
hipMemcpy(y, dy, size, hipMemcpyDeviceToHost);
}
else{
for (int i = 0; i < N; i++){
y[i] = 3 * x[i] + y[i];
}
}
int counter = 0;
for (int i = 0; i < N; i++){
if (y[i] != 5.0) counter++;
}
cout << "Error number is: " << counter << endl;
return 0;
}
__global__ void multiadd(int N, float a, float* x, float* y){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N) y[i] = a * x[i] + y[i];
} | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x40a00000 # float 5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $136, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $35, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_15
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB0_4
.LBB0_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_5: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%r14,%rax,4) # imm = 0x3F800000
movl $1073741824, (%rbx,%rax,4) # imm = 0x40000000
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB0_5
# %bb.6:
movq 24(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 3840(%rdx), %rdi
xorl %r14d, %r14d
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_8
# %bb.7:
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
movl $1048576, 20(%rsp) # imm = 0x100000
movl $1077936128, 16(%rsp) # imm = 0x40400000
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8multiaddifPfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_8:
movq 8(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movss .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_9: # =>This Inner Loop Header: Depth=1
movss (%rbx,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cmpneqss %xmm0, %xmm1
movd %xmm1, %ecx
subl %ecx, %r14d
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB0_9
# %bb.10:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r14d, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_15
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i31
cmpb $0, 56(%rbx)
je .LBB0_13
# %bb.12:
movzbl 67(%rbx), %ecx
jmp .LBB0_14
.LBB0_13:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit34
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_15:
.cfi_def_cfa_offset 160
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z23__device_stub__multiaddifPfS_ # -- Begin function _Z23__device_stub__multiaddifPfS_
.p2align 4, 0x90
.type _Z23__device_stub__multiaddifPfS_,@function
_Z23__device_stub__multiaddifPfS_: # @_Z23__device_stub__multiaddifPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8multiaddifPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z23__device_stub__multiaddifPfS_, .Lfunc_end1-_Z23__device_stub__multiaddifPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8multiaddifPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "This is test CUDA in visual studio!"
.size .L.str, 36
.type _Z8multiaddifPfS_,@object # @_Z8multiaddifPfS_
.section .rodata,"a",@progbits
.globl _Z8multiaddifPfS_
.p2align 3, 0x0
_Z8multiaddifPfS_:
.quad _Z23__device_stub__multiaddifPfS_
.size _Z8multiaddifPfS_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Error number is: "
.size .L.str.1, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8multiaddifPfS_"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__multiaddifPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cout
.addrsig_sym _Z8multiaddifPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8multiaddifPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe400078e0205 */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ FFMA R7, R2, c[0x0][0x164], R7 ; /* 0x0000590002077a23 */
/* 0x004fca0000000007 */
/*00d0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8multiaddifPfS_
.globl _Z8multiaddifPfS_
.p2align 8
.type _Z8multiaddifPfS_,@function
_Z8multiaddifPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, s0, v2
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8multiaddifPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8multiaddifPfS_, .Lfunc_end0-_Z8multiaddifPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8multiaddifPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8multiaddifPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001041eb_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z8multiaddifPfS_ifPfS_
.type _Z31__device_stub__Z8multiaddifPfS_ifPfS_, @function
_Z31__device_stub__Z8multiaddifPfS_ifPfS_:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movss %xmm0, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8multiaddifPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z31__device_stub__Z8multiaddifPfS_ifPfS_, .-_Z31__device_stub__Z8multiaddifPfS_ifPfS_
.globl _Z8multiaddifPfS_
.type _Z8multiaddifPfS_, @function
_Z8multiaddifPfS_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8multiaddifPfS_ifPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z8multiaddifPfS_, .-_Z8multiaddifPfS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "This is test CUDA in visual studio!"
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "Error number is: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movq %rsp, %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $0, %eax
movss .LC1(%rip), %xmm1
movss .LC2(%rip), %xmm0
.L12:
movss %xmm1, 0(%rbp,%rax)
movss %xmm0, (%rbx,%rax)
addq $4, %rax
cmpq $4194304, %rax
jne .L12
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $4096, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L13:
movl $2, %ecx
movl $4194304, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rax
addq $4194304, %rbx
movl $0, %ebp
jmp .L16
.L22:
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movss .LC3(%rip), %xmm0
movl $1048576, %edi
call _Z31__device_stub__Z8multiaddifPfS_ifPfS_
jmp .L13
.L18:
addl $1, %ebp
.L14:
addq $4, %rax
cmpq %rbx, %rax
je .L23
.L16:
movss (%rax), %xmm0
ucomiss .LC4(%rip), %xmm0
jp .L18
je .L14
jmp .L18
.L23:
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebp, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z8multiaddifPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z8multiaddifPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1073741824
.align 4
.LC3:
.long 1077936128
.align 4
.LC4:
.long 1084227584
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x40a00000 # float 5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $136, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $35, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_15
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB0_4
.LBB0_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_5: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%r14,%rax,4) # imm = 0x3F800000
movl $1073741824, (%rbx,%rax,4) # imm = 0x40000000
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB0_5
# %bb.6:
movq 24(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 3840(%rdx), %rdi
xorl %r14d, %r14d
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_8
# %bb.7:
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
movl $1048576, 20(%rsp) # imm = 0x100000
movl $1077936128, 16(%rsp) # imm = 0x40400000
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8multiaddifPfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_8:
movq 8(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movss .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_9: # =>This Inner Loop Header: Depth=1
movss (%rbx,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cmpneqss %xmm0, %xmm1
movd %xmm1, %ecx
subl %ecx, %r14d
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB0_9
# %bb.10:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r14d, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_15
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i31
cmpb $0, 56(%rbx)
je .LBB0_13
# %bb.12:
movzbl 67(%rbx), %ecx
jmp .LBB0_14
.LBB0_13:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit34
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_15:
.cfi_def_cfa_offset 160
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z23__device_stub__multiaddifPfS_ # -- Begin function _Z23__device_stub__multiaddifPfS_
.p2align 4, 0x90
.type _Z23__device_stub__multiaddifPfS_,@function
_Z23__device_stub__multiaddifPfS_: # @_Z23__device_stub__multiaddifPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8multiaddifPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z23__device_stub__multiaddifPfS_, .Lfunc_end1-_Z23__device_stub__multiaddifPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8multiaddifPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "This is test CUDA in visual studio!"
.size .L.str, 36
.type _Z8multiaddifPfS_,@object # @_Z8multiaddifPfS_
.section .rodata,"a",@progbits
.globl _Z8multiaddifPfS_
.p2align 3, 0x0
_Z8multiaddifPfS_:
.quad _Z23__device_stub__multiaddifPfS_
.size _Z8multiaddifPfS_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Error number is: "
.size .L.str.1, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8multiaddifPfS_"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__multiaddifPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cout
.addrsig_sym _Z8multiaddifPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime.h>
#include <stdio.h>
__global__ void checkIndx(void)
{
printf("threadIdx:(%d, %d, %d) "
"blockIdx:(%d, %d, %d) "
"blockDim:(%d, %d, %d) "
"gridDim:(%d, %d, %d)\n",
threadIdx.x, threadIdx.y, threadIdx.z,
blockIdx.x, blockIdx.y, blockIdx.z,
blockDim.x, blockDim.y, blockDim.z,
gridDim.x, gridDim.y, gridDim.z);
}
int main()
{
int nElem = 64;
/**
*here, we define 2 blocks, each of which has 3 threads.
*/
for (int i = 1; i < 5; ++i)
{
if (i == 1 || i % 2 == 0) {
dim3 block (nElem / i);
dim3 grid ((nElem + block.x - 1) / block.x);
printf("grid.x %d grid.y %d grid.z %d\n", grid.x, grid.y, grid.z);
printf("block.x %d, block.y %d, block.z %d\n", block.x, block.y, block.z);
checkIndx <<<grid, block>>>();
}
}
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _Z9checkIndxv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002500 */
/*0020*/ IADD3 R1, R1, -0x30, RZ ; /* 0xffffffd001017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0e7624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R18, c[0x0][0x10] ; /* 0x0000040000127a02 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R10, SR_TID.Z ; /* 0x00000000000a7919 */
/* 0x000e220000002300 */
/*0060*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x4] ; /* 0x00000100ff0f7624 */
/* 0x000fe200078e00ff */
/*0070*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0080*/ IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x8] ; /* 0x00000200ff107624 */
/* 0x000fe200078e00ff */
/*0090*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000e220000002200 */
/*00a0*/ IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff117624 */
/* 0x000fe200078e00ff */
/*00b0*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0002a20000000a00 */
/*00c0*/ IMAD.MOV.U32 R19, RZ, RZ, c[0x0][0x14] ; /* 0x00000500ff137624 */
/* 0x000fe200078e00ff */
/*00d0*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*00e0*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*00f0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0100*/ MOV R5, c[0x4][0xc] ; /* 0x0100030000057a02 */
/* 0x000fe20000000f00 */
/*0110*/ S2R R13, SR_CTAID.Z ; /* 0x00000000000d7919 */
/* 0x000ee40000002700 */
/*0120*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fc400000e06ff */
/*0130*/ S2R R12, SR_CTAID.Y ; /* 0x00000000000c7919 */
/* 0x000ee80000002600 */
/*0140*/ STL.128 [R1+0x20], R16 ; /* 0x0000201001007387 */
/* 0x0003e80000100c00 */
/*0150*/ STL.128 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0013e80000100c00 */
/*0160*/ STL.128 [R1+0x10], R12 ; /* 0x0000100c01007387 */
/* 0x0083e40000100c00 */
/*0170*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x006fe40000000000 */
/*0180*/ MOV R11, 0x1f0 ; /* 0x000001f0000b7802 */
/* 0x000fe40000000f00 */
/*0190*/ MOV R20, 0x170 ; /* 0x0000017000147802 */
/* 0x000fc40000000f00 */
/*01a0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*01b0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*01c0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*01d0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*01e0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x000fea0003c00000 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
#include <stdio.h>
__global__ void checkIndx(void)
{
printf("threadIdx:(%d, %d, %d) "
"blockIdx:(%d, %d, %d) "
"blockDim:(%d, %d, %d) "
"gridDim:(%d, %d, %d)\n",
threadIdx.x, threadIdx.y, threadIdx.z,
blockIdx.x, blockIdx.y, blockIdx.z,
blockDim.x, blockDim.y, blockDim.z,
gridDim.x, gridDim.y, gridDim.z);
}
int main()
{
int nElem = 64;
/**
*here, we define 2 blocks, each of which has 3 threads.
*/
for (int i = 1; i < 5; ++i)
{
if (i == 1 || i % 2 == 0) {
dim3 block (nElem / i);
dim3 grid ((nElem + block.x - 1) / block.x);
printf("grid.x %d grid.y %d grid.z %d\n", grid.x, grid.y, grid.z);
printf("block.x %d, block.y %d, block.z %d\n", block.x, block.y, block.z);
checkIndx <<<grid, block>>>();
}
}
cudaDeviceReset();
return 0;
} | .file "tmpxft_00021d96_00000000-6_checkIndx.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z9checkIndxvv
.type _Z27__device_stub__Z9checkIndxvv, @function
_Z27__device_stub__Z9checkIndxvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z9checkIndxv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z9checkIndxvv, .-_Z27__device_stub__Z9checkIndxvv
.globl _Z9checkIndxv
.type _Z9checkIndxv, @function
_Z9checkIndxv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z9checkIndxvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9checkIndxv, .-_Z9checkIndxv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "grid.x %d grid.y %d grid.z %d\n"
.align 8
.LC1:
.string "block.x %d, block.y %d, block.z %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl $1, %ebx
movl $64, %r13d
leaq .LC0(%rip), %r15
leaq .LC1(%rip), %r14
jmp .L15
.L18:
call _Z27__device_stub__Z9checkIndxvv
.L13:
addl $1, %ebx
cmpl $5, %ebx
je .L22
.L15:
cmpl $1, %ebx
je .L12
testb $1, %bl
jne .L13
movl %r13d, %eax
cltd
idivl %ebx
movl %eax, %ebp
leal 63(%rax), %eax
movl $0, %edx
divl %ebp
movl %eax, %r12d
movl $1, %r8d
movl $1, %ecx
movl %eax, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %r8d
movl $1, %ecx
movl %ebp, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, 20(%rsp)
movl $1, 24(%rsp)
movl %ebp, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L13
jmp .L18
.L12:
movl $64, %eax
movl $0, %edx
idivl %ebx
movl %eax, %ebp
leal 63(%rax), %eax
movl $0, %edx
divl %ebp
movl %eax, %r12d
movl $1, %r8d
movl $1, %ecx
movl %eax, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %r8d
movl $1, %ecx
movl %ebp, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, 20(%rsp)
movl $1, 24(%rsp)
movl %ebp, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
addl $1, %ebx
jmp .L15
.L22:
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z9checkIndxv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z9checkIndxv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
#include <stdio.h>
__global__ void checkIndx(void)
{
printf("threadIdx:(%d, %d, %d) "
"blockIdx:(%d, %d, %d) "
"blockDim:(%d, %d, %d) "
"gridDim:(%d, %d, %d)\n",
threadIdx.x, threadIdx.y, threadIdx.z,
blockIdx.x, blockIdx.y, blockIdx.z,
blockDim.x, blockDim.y, blockDim.z,
gridDim.x, gridDim.y, gridDim.z);
}
int main()
{
int nElem = 64;
/**
*here, we define 2 blocks, each of which has 3 threads.
*/
for (int i = 1; i < 5; ++i)
{
if (i == 1 || i % 2 == 0) {
dim3 block (nElem / i);
dim3 grid ((nElem + block.x - 1) / block.x);
printf("grid.x %d grid.y %d grid.z %d\n", grid.x, grid.y, grid.z);
printf("block.x %d, block.y %d, block.z %d\n", block.x, block.y, block.z);
checkIndx <<<grid, block>>>();
}
}
cudaDeviceReset();
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void checkIndx(void)
{
printf("threadIdx:(%d, %d, %d) "
"blockIdx:(%d, %d, %d) "
"blockDim:(%d, %d, %d) "
"gridDim:(%d, %d, %d)\n",
threadIdx.x, threadIdx.y, threadIdx.z,
blockIdx.x, blockIdx.y, blockIdx.z,
blockDim.x, blockDim.y, blockDim.z,
gridDim.x, gridDim.y, gridDim.z);
}
int main()
{
int nElem = 64;
/**
*here, we define 2 blocks, each of which has 3 threads.
*/
for (int i = 1; i < 5; ++i)
{
if (i == 1 || i % 2 == 0) {
dim3 block (nElem / i);
dim3 grid ((nElem + block.x - 1) / block.x);
printf("grid.x %d grid.y %d grid.z %d\n", grid.x, grid.y, grid.z);
printf("block.x %d, block.y %d, block.z %d\n", block.x, block.y, block.z);
checkIndx <<<grid, block>>>();
}
}
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void checkIndx(void)
{
printf("threadIdx:(%d, %d, %d) "
"blockIdx:(%d, %d, %d) "
"blockDim:(%d, %d, %d) "
"gridDim:(%d, %d, %d)\n",
threadIdx.x, threadIdx.y, threadIdx.z,
blockIdx.x, blockIdx.y, blockIdx.z,
blockDim.x, blockDim.y, blockDim.z,
gridDim.x, gridDim.y, gridDim.z);
}
int main()
{
int nElem = 64;
/**
*here, we define 2 blocks, each of which has 3 threads.
*/
for (int i = 1; i < 5; ++i)
{
if (i == 1 || i % 2 == 0) {
dim3 block (nElem / i);
dim3 grid ((nElem + block.x - 1) / block.x);
printf("grid.x %d grid.y %d grid.z %d\n", grid.x, grid.y, grid.z);
printf("block.x %d, block.y %d, block.z %d\n", block.x, block.y, block.z);
checkIndx <<<grid, block>>>();
}
}
hipDeviceReset();
return 0;
} | .text
.file "checkIndx.hip"
.globl _Z24__device_stub__checkIndxv # -- Begin function _Z24__device_stub__checkIndxv
.p2align 4, 0x90
.type _Z24__device_stub__checkIndxv,@function
_Z24__device_stub__checkIndxv: # @_Z24__device_stub__checkIndxv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z9checkIndxv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z24__device_stub__checkIndxv, .Lfunc_end0-_Z24__device_stub__checkIndxv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $56, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967296, %r15 # imm = 0x100000000
movl $1, %r12d
leaq 48(%rsp), %r13
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_1 Depth=1
incl %r12d
cmpl $5, %r12d
je .LBB1_6
.LBB1_1: # =>This Inner Loop Header: Depth=1
cmpl $1, %r12d
je .LBB1_3
# %bb.2: # in Loop: Header=BB1_1 Depth=1
movl %r12d, %eax
andl $1, %eax
jne .LBB1_5
.LBB1_3: # in Loop: Header=BB1_1 Depth=1
movl $64, %eax
xorl %edx, %edx
divl %r12d
movl %eax, %ebp
movq %rbp, %rbx
orq %r15, %rbx
leal 63(%rbp), %eax
xorl %edx, %edx
divl %ebp
# kill: def $eax killed $eax def $rax
movq %rax, %r14
orq %r15, %r14
movl $.L.str, %edi
movl %eax, %esi
movl $1, %edx
movl $1, %ecx
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl %ebp, %esi
movl $1, %edx
movl $1, %ecx
xorl %eax, %eax
callq printf
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4: # in Loop: Header=BB1_1 Depth=1
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
movl $_Z9checkIndxv, %edi
movq %r13, %r9
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_5
.LBB1_6:
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9checkIndxv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9checkIndxv,@object # @_Z9checkIndxv
.section .rodata,"a",@progbits
.globl _Z9checkIndxv
.p2align 3, 0x0
_Z9checkIndxv:
.quad _Z24__device_stub__checkIndxv
.size _Z9checkIndxv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "grid.x %d grid.y %d grid.z %d\n"
.size .L.str, 31
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "block.x %d, block.y %d, block.z %d\n"
.size .L.str.1, 36
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9checkIndxv"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__checkIndxv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9checkIndxv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00021d96_00000000-6_checkIndx.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z9checkIndxvv
.type _Z27__device_stub__Z9checkIndxvv, @function
_Z27__device_stub__Z9checkIndxvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z9checkIndxv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z9checkIndxvv, .-_Z27__device_stub__Z9checkIndxvv
.globl _Z9checkIndxv
.type _Z9checkIndxv, @function
_Z9checkIndxv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z9checkIndxvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9checkIndxv, .-_Z9checkIndxv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "grid.x %d grid.y %d grid.z %d\n"
.align 8
.LC1:
.string "block.x %d, block.y %d, block.z %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl $1, %ebx
movl $64, %r13d
leaq .LC0(%rip), %r15
leaq .LC1(%rip), %r14
jmp .L15
.L18:
call _Z27__device_stub__Z9checkIndxvv
.L13:
addl $1, %ebx
cmpl $5, %ebx
je .L22
.L15:
cmpl $1, %ebx
je .L12
testb $1, %bl
jne .L13
movl %r13d, %eax
cltd
idivl %ebx
movl %eax, %ebp
leal 63(%rax), %eax
movl $0, %edx
divl %ebp
movl %eax, %r12d
movl $1, %r8d
movl $1, %ecx
movl %eax, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %r8d
movl $1, %ecx
movl %ebp, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, 20(%rsp)
movl $1, 24(%rsp)
movl %ebp, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L13
jmp .L18
.L12:
movl $64, %eax
movl $0, %edx
idivl %ebx
movl %eax, %ebp
leal 63(%rax), %eax
movl $0, %edx
divl %ebp
movl %eax, %r12d
movl $1, %r8d
movl $1, %ecx
movl %eax, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %r8d
movl $1, %ecx
movl %ebp, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, 20(%rsp)
movl $1, 24(%rsp)
movl %ebp, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
addl $1, %ebx
jmp .L15
.L22:
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z9checkIndxv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z9checkIndxv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "checkIndx.hip"
.globl _Z24__device_stub__checkIndxv # -- Begin function _Z24__device_stub__checkIndxv
.p2align 4, 0x90
.type _Z24__device_stub__checkIndxv,@function
_Z24__device_stub__checkIndxv: # @_Z24__device_stub__checkIndxv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z9checkIndxv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z24__device_stub__checkIndxv, .Lfunc_end0-_Z24__device_stub__checkIndxv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $56, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967296, %r15 # imm = 0x100000000
movl $1, %r12d
leaq 48(%rsp), %r13
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_1 Depth=1
incl %r12d
cmpl $5, %r12d
je .LBB1_6
.LBB1_1: # =>This Inner Loop Header: Depth=1
cmpl $1, %r12d
je .LBB1_3
# %bb.2: # in Loop: Header=BB1_1 Depth=1
movl %r12d, %eax
andl $1, %eax
jne .LBB1_5
.LBB1_3: # in Loop: Header=BB1_1 Depth=1
movl $64, %eax
xorl %edx, %edx
divl %r12d
movl %eax, %ebp
movq %rbp, %rbx
orq %r15, %rbx
leal 63(%rbp), %eax
xorl %edx, %edx
divl %ebp
# kill: def $eax killed $eax def $rax
movq %rax, %r14
orq %r15, %r14
movl $.L.str, %edi
movl %eax, %esi
movl $1, %edx
movl $1, %ecx
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl %ebp, %esi
movl $1, %edx
movl $1, %ecx
xorl %eax, %eax
callq printf
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4: # in Loop: Header=BB1_1 Depth=1
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
movl $_Z9checkIndxv, %edi
movq %r13, %r9
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_5
.LBB1_6:
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9checkIndxv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9checkIndxv,@object # @_Z9checkIndxv
.section .rodata,"a",@progbits
.globl _Z9checkIndxv
.p2align 3, 0x0
_Z9checkIndxv:
.quad _Z24__device_stub__checkIndxv
.size _Z9checkIndxv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "grid.x %d grid.y %d grid.z %d\n"
.size .L.str, 31
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "block.x %d, block.y %d, block.z %d\n"
.size .L.str.1, 36
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9checkIndxv"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__checkIndxv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9checkIndxv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
__global__ void dot_prod(int n, int *a, int *b, int *c)
{
int index = threadIdx.x;
int stride = blockDim.x;
for (int i = index; i < n; i += stride){ // T threads per iteration
c[i] = a[i] * b[i];
}
}
int main(int argc, char **argv){
int sum = 0;
int N = 100;
int size = N * sizeof(int);
// Create counter
cudaEvent_t start, stop;
float elapsedTime;
int *a, *b, *c; // Host copies of a, b, c
int *dev_a, *dev_b, *dev_c; // Device copies of a, b, c
// Allocate space for device copies a, b, c
cudaMalloc((void **) &dev_a, size);
cudaMalloc((void **) &dev_b, size);
cudaMalloc((void **) &dev_c, size);
a = (int *) malloc(size);
b = (int *) malloc(size);
c = (int *) malloc(size);
// initialization of the arrays
for(int i = 0; i < N; i++){
a[i] = b[i] = 1;
}
// Start counter
cudaEventCreate(&start);
cudaEventRecord(start,0);
// Copy inputs to device
cudaMemcpy(dev_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, size, cudaMemcpyHostToDevice);
//dot_prod<<<1,N>>>(dev_a, dev_b, dev_c); // 1 block, N threads (block size)
dot_prod<<<1,64>>>(N, dev_a, dev_b, dev_c);
// Copy result back to host
cudaMemcpy(c, dev_c, size, cudaMemcpyDeviceToHost);
for( int i = 0; i < N; i++ ){
sum += c[i];
}
// Stop counter
cudaEventCreate(&stop);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start,stop);
for( int i = 0; i < N; i++ ){
printf("%d ", c[i]);
}
printf("Dot Product: %d\n", sum);
printf("Elapsed time: %f ms\n", elapsedTime);
// Clean up
free(a); free(b);
cudaFree(dev_a); cudaFree(dev_b); cudaFree(dev_c);
return 0;
} | code for sm_80
Function : _Z8dot_prodiPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ I2F.U32.RP R5, c[0x0][0x0] ; /* 0x0000000000057b06 */
/* 0x000e220000209000 */
/*0050*/ LOP3.LUT R4, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff047212 */
/* 0x000fe200078e33ff */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0070*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fe20003f45070 */
/*0080*/ BSSY B0, 0x2f0 ; /* 0x0000026000007945 */
/* 0x000fe20003800000 */
/*0090*/ IADD3 R4, R4, c[0x0][0x160], RZ ; /* 0x0000580004047a10 */
/* 0x000fc60007ffe0ff */
/*00a0*/ MUFU.RCP R5, R5 ; /* 0x0000000500057308 */
/* 0x001e240000001000 */
/*00b0*/ IADD3 R2, R5, 0xffffffe, RZ ; /* 0x0ffffffe05027810 */
/* 0x001fcc0007ffe0ff */
/*00c0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00d0*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*00e0*/ IADD3 R7, RZ, -R3, RZ ; /* 0x80000003ff077210 */
/* 0x002fca0007ffe0ff */
/*00f0*/ IMAD R7, R7, c[0x0][0x0], RZ ; /* 0x0000000007077a24 */
/* 0x000fc800078e02ff */
/*0100*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*0110*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fca00078e00ff */
/*0120*/ IADD3 R5, -R3, RZ, RZ ; /* 0x000000ff03057210 */
/* 0x000fca0007ffe1ff */
/*0130*/ IMAD R4, R5, c[0x0][0x0], R4 ; /* 0x0000000005047a24 */
/* 0x000fca00078e0204 */
/*0140*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x0], PT ; /* 0x0000000004007a0c */
/* 0x000fda0003f06070 */
/*0150*/ @P0 IADD3 R4, R4, -c[0x0][0x0], RZ ; /* 0x8000000004040a10 */
/* 0x000fe40007ffe0ff */
/*0160*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fe40007ffe0ff */
/*0170*/ ISETP.GE.U32.AND P1, PT, R4, c[0x0][0x0], PT ; /* 0x0000000004007a0c */
/* 0x000fda0003f26070 */
/*0180*/ @P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103031810 */
/* 0x000fe40007ffe0ff */
/*0190*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x0], RZ, 0x33, !PT ; /* 0x00000000ff03aa12 */
/* 0x000fc800078e33ff */
/*01a0*/ IADD3 R2, R3.reuse, 0x1, RZ ; /* 0x0000000103027810 */
/* 0x040fe40007ffe0ff */
/*01b0*/ ISETP.GE.U32.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f26070 */
/*01c0*/ LOP3.LUT P0, R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fda000780c0ff */
/*01d0*/ @!P0 BRA 0x2e0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*01e0*/ MOV R11, 0x4 ; /* 0x00000004000b7802 */
/* 0x000fe40000000f00 */
/*01f0*/ MOV R8, R2 ; /* 0x0000000200087202 */
/* 0x000fc60000000f00 */
/*0200*/ IMAD.WIDE R2, R0, R11, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fc800078e020b */
/*0210*/ IMAD.WIDE R4, R0, R11, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fc800078e020b */
/*0220*/ IMAD.WIDE R6, R0, R11, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x000fc800078e020b */
/*0230*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x0000a8000c1e1900 */
/*0240*/ LDG.E R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x0002a2000c1e1900 */
/*0250*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fe40007ffe0ff */
/*0260*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x000fe40007ffe0ff */
/*0270*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0280*/ IMAD.WIDE R4, R11, c[0x0][0x0], R4 ; /* 0x000000000b047a25 */
/* 0x001fc800078e0204 */
/*0290*/ IMAD.WIDE R6, R11, c[0x0][0x0], R6 ; /* 0x000000000b067a25 */
/* 0x002fc800078e0206 */
/*02a0*/ IMAD R9, R9, R10, RZ ; /* 0x0000000a09097224 */
/* 0x004fca00078e02ff */
/*02b0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e4000c101904 */
/*02c0*/ IMAD.WIDE R2, R11, c[0x0][0x0], R2 ; /* 0x000000000b027a25 */
/* 0x001fe200078e0202 */
/*02d0*/ @P0 BRA 0x230 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*02e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02f0*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0300*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x002fd400000001ff */
/*0310*/ IMAD.WIDE R6, R0, R3, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0203 */
/*0320*/ IMAD.WIDE R4, R0.reuse, R3.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe200078e0203 */
/*0330*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea8000c1e1900 */
/*0340*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x000ea2000c1e1900 */
/*0350*/ IMAD.WIDE R8, R0, R3, c[0x0][0x178] ; /* 0x00005e0000087625 */
/* 0x000fc800078e0203 */
/*0360*/ IMAD.WIDE R12, R3, c[0x0][0x0], R6 ; /* 0x00000000030c7a25 */
/* 0x000fc800078e0206 */
/*0370*/ IMAD R19, R2, R11, RZ ; /* 0x0000000b02137224 */
/* 0x004fe400078e02ff */
/*0380*/ IMAD.WIDE R10, R3, c[0x0][0x0], R4 ; /* 0x00000000030a7a25 */
/* 0x000fc600078e0204 */
/*0390*/ STG.E [R8.64], R19 ; /* 0x0000001308007986 */
/* 0x0001e8000c101904 */
/*03a0*/ LDG.E R2, [R12.64] ; /* 0x000000040c027981 */
/* 0x000ea8000c1e1900 */
/*03b0*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x000ea2000c1e1900 */
/*03c0*/ IMAD.WIDE R14, R3, c[0x0][0x0], R8 ; /* 0x00000000030e7a25 */
/* 0x000fc800078e0208 */
/*03d0*/ IMAD.WIDE R6, R3, c[0x0][0x0], R12 ; /* 0x0000000003067a25 */
/* 0x000fc800078e020c */
/*03e0*/ IMAD.WIDE R4, R3, c[0x0][0x0], R10 ; /* 0x0000000003047a25 */
/* 0x000fc800078e020a */
/*03f0*/ IMAD R21, R2, R17, RZ ; /* 0x0000001102157224 */
/* 0x004fca00078e02ff */
/*0400*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0003e8000c101904 */
/*0410*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea8000c1e1900 */
/*0420*/ LDG.E R23, [R4.64] ; /* 0x0000000404177981 */
/* 0x000ea2000c1e1900 */
/*0430*/ IMAD.WIDE R16, R3, c[0x0][0x0], R14 ; /* 0x0000000003107a25 */
/* 0x000fc800078e020e */
/*0440*/ IMAD.WIDE R12, R3, c[0x0][0x0], R6 ; /* 0x00000000030c7a25 */
/* 0x000fc800078e0206 */
/*0450*/ IMAD.WIDE R8, R3, c[0x0][0x0], R4 ; /* 0x0000000003087a25 */
/* 0x001fc800078e0204 */
/*0460*/ IMAD R23, R2, R23, RZ ; /* 0x0000001702177224 */
/* 0x004fca00078e02ff */
/*0470*/ STG.E [R16.64], R23 ; /* 0x0000001710007986 */
/* 0x0003e8000c101904 */
/*0480*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea8000c1e1900 */
/*0490*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*04a0*/ MOV R7, c[0x0][0x0] ; /* 0x0000000000077a02 */
/* 0x000fe20000000f00 */
/*04b0*/ IMAD.WIDE R2, R3, c[0x0][0x0], R16 ; /* 0x0000000003027a25 */
/* 0x000fe200078e0210 */
/*04c0*/ MOV R5, c[0x0][0x0] ; /* 0x0000000000057a02 */
/* 0x000fc40000000f00 */
/*04d0*/ LEA R0, R7, R0, 0x1 ; /* 0x0000000007007211 */
/* 0x000fc800078e08ff */
/*04e0*/ LEA R0, R5, R0, 0x1 ; /* 0x0000000005007211 */
/* 0x000fc800078e08ff */
/*04f0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fe20003f06270 */
/*0500*/ IMAD R11, R12, R9, RZ ; /* 0x000000090c0b7224 */
/* 0x004fca00078e02ff */
/*0510*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003ee000c101904 */
/*0520*/ @!P0 BRA 0x300 ; /* 0xfffffdd000008947 */
/* 0x000fea000383ffff */
/*0530*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0540*/ BRA 0x540; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
__global__ void dot_prod(int n, int *a, int *b, int *c)
{
int index = threadIdx.x;
int stride = blockDim.x;
for (int i = index; i < n; i += stride){ // T threads per iteration
c[i] = a[i] * b[i];
}
}
int main(int argc, char **argv){
int sum = 0;
int N = 100;
int size = N * sizeof(int);
// Create counter
cudaEvent_t start, stop;
float elapsedTime;
int *a, *b, *c; // Host copies of a, b, c
int *dev_a, *dev_b, *dev_c; // Device copies of a, b, c
// Allocate space for device copies a, b, c
cudaMalloc((void **) &dev_a, size);
cudaMalloc((void **) &dev_b, size);
cudaMalloc((void **) &dev_c, size);
a = (int *) malloc(size);
b = (int *) malloc(size);
c = (int *) malloc(size);
// initialization of the arrays
for(int i = 0; i < N; i++){
a[i] = b[i] = 1;
}
// Start counter
cudaEventCreate(&start);
cudaEventRecord(start,0);
// Copy inputs to device
cudaMemcpy(dev_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, size, cudaMemcpyHostToDevice);
//dot_prod<<<1,N>>>(dev_a, dev_b, dev_c); // 1 block, N threads (block size)
dot_prod<<<1,64>>>(N, dev_a, dev_b, dev_c);
// Copy result back to host
cudaMemcpy(c, dev_c, size, cudaMemcpyDeviceToHost);
for( int i = 0; i < N; i++ ){
sum += c[i];
}
// Stop counter
cudaEventCreate(&stop);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start,stop);
for( int i = 0; i < N; i++ ){
printf("%d ", c[i]);
}
printf("Dot Product: %d\n", sum);
printf("Elapsed time: %f ms\n", elapsedTime);
// Clean up
free(a); free(b);
cudaFree(dev_a); cudaFree(dev_b); cudaFree(dev_c);
return 0;
} | .file "tmpxft_000e0cc5_00000000-6_dot_product.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z8dot_prodiPiS_S_iPiS_S_
.type _Z32__device_stub__Z8dot_prodiPiS_S_iPiS_S_, @function
_Z32__device_stub__Z8dot_prodiPiS_S_iPiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8dot_prodiPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z8dot_prodiPiS_S_iPiS_S_, .-_Z32__device_stub__Z8dot_prodiPiS_S_iPiS_S_
.globl _Z8dot_prodiPiS_S_
.type _Z8dot_prodiPiS_S_, @function
_Z8dot_prodiPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8dot_prodiPiS_S_iPiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8dot_prodiPiS_S_, .-_Z8dot_prodiPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "Dot Product: %d\n"
.LC2:
.string "Elapsed time: %f ms\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
movl $400, %edi
call malloc@PLT
movq %rax, %r13
movl $400, %edi
call malloc@PLT
movq %rax, %r12
movl $400, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, %eax
.L12:
movl $1, (%r12,%rax)
movl $1, 0(%r13,%rax)
addq $4, %rax
cmpq $400, %rax
jne .L12
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movl $400, %edx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $400, %edx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $64, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 56(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L13:
movl $2, %ecx
movl $400, %edx
movq 32(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rbp
leaq 400(%rbx), %r14
movq %rbx, %rax
movl $0, %edx
.L14:
movl %edx, %ebx
addl (%rax), %ebx
movl %ebx, %edx
addq $4, %rax
cmpq %r14, %rax
jne .L14
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 44(%rsp), %rdi
movq 56(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC0(%rip), %r15
.L15:
movl 0(%rbp), %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbp
cmpq %r14, %rbp
jne .L15
movl %ebx, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 44(%rsp), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movl $100, %edi
call _Z32__device_stub__Z8dot_prodiPiS_S_iPiS_S_
jmp .L13
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z8dot_prodiPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z8dot_prodiPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
__global__ void dot_prod(int n, int *a, int *b, int *c)
{
int index = threadIdx.x;
int stride = blockDim.x;
for (int i = index; i < n; i += stride){ // T threads per iteration
c[i] = a[i] * b[i];
}
}
int main(int argc, char **argv){
int sum = 0;
int N = 100;
int size = N * sizeof(int);
// Create counter
cudaEvent_t start, stop;
float elapsedTime;
int *a, *b, *c; // Host copies of a, b, c
int *dev_a, *dev_b, *dev_c; // Device copies of a, b, c
// Allocate space for device copies a, b, c
cudaMalloc((void **) &dev_a, size);
cudaMalloc((void **) &dev_b, size);
cudaMalloc((void **) &dev_c, size);
a = (int *) malloc(size);
b = (int *) malloc(size);
c = (int *) malloc(size);
// initialization of the arrays
for(int i = 0; i < N; i++){
a[i] = b[i] = 1;
}
// Start counter
cudaEventCreate(&start);
cudaEventRecord(start,0);
// Copy inputs to device
cudaMemcpy(dev_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, size, cudaMemcpyHostToDevice);
//dot_prod<<<1,N>>>(dev_a, dev_b, dev_c); // 1 block, N threads (block size)
dot_prod<<<1,64>>>(N, dev_a, dev_b, dev_c);
// Copy result back to host
cudaMemcpy(c, dev_c, size, cudaMemcpyDeviceToHost);
for( int i = 0; i < N; i++ ){
sum += c[i];
}
// Stop counter
cudaEventCreate(&stop);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start,stop);
for( int i = 0; i < N; i++ ){
printf("%d ", c[i]);
}
printf("Dot Product: %d\n", sum);
printf("Elapsed time: %f ms\n", elapsedTime);
// Clean up
free(a); free(b);
cudaFree(dev_a); cudaFree(dev_b); cudaFree(dev_c);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void dot_prod(int n, int *a, int *b, int *c)
{
int index = threadIdx.x;
int stride = blockDim.x;
for (int i = index; i < n; i += stride){ // T threads per iteration
c[i] = a[i] * b[i];
}
}
int main(int argc, char **argv){
int sum = 0;
int N = 100;
int size = N * sizeof(int);
// Create counter
hipEvent_t start, stop;
float elapsedTime;
int *a, *b, *c; // Host copies of a, b, c
int *dev_a, *dev_b, *dev_c; // Device copies of a, b, c
// Allocate space for device copies a, b, c
hipMalloc((void **) &dev_a, size);
hipMalloc((void **) &dev_b, size);
hipMalloc((void **) &dev_c, size);
a = (int *) malloc(size);
b = (int *) malloc(size);
c = (int *) malloc(size);
// initialization of the arrays
for(int i = 0; i < N; i++){
a[i] = b[i] = 1;
}
// Start counter
hipEventCreate(&start);
hipEventRecord(start,0);
// Copy inputs to device
hipMemcpy(dev_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(dev_b, b, size, hipMemcpyHostToDevice);
//dot_prod<<<1,N>>>(dev_a, dev_b, dev_c); // 1 block, N threads (block size)
dot_prod<<<1,64>>>(N, dev_a, dev_b, dev_c);
// Copy result back to host
hipMemcpy(c, dev_c, size, hipMemcpyDeviceToHost);
for( int i = 0; i < N; i++ ){
sum += c[i];
}
// Stop counter
hipEventCreate(&stop);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start,stop);
for( int i = 0; i < N; i++ ){
printf("%d ", c[i]);
}
printf("Dot Product: %d\n", sum);
printf("Elapsed time: %f ms\n", elapsedTime);
// Clean up
free(a); free(b);
hipFree(dev_a); hipFree(dev_b); hipFree(dev_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void dot_prod(int n, int *a, int *b, int *c)
{
int index = threadIdx.x;
int stride = blockDim.x;
for (int i = index; i < n; i += stride){ // T threads per iteration
c[i] = a[i] * b[i];
}
}
int main(int argc, char **argv){
int sum = 0;
int N = 100;
int size = N * sizeof(int);
// Create counter
hipEvent_t start, stop;
float elapsedTime;
int *a, *b, *c; // Host copies of a, b, c
int *dev_a, *dev_b, *dev_c; // Device copies of a, b, c
// Allocate space for device copies a, b, c
hipMalloc((void **) &dev_a, size);
hipMalloc((void **) &dev_b, size);
hipMalloc((void **) &dev_c, size);
a = (int *) malloc(size);
b = (int *) malloc(size);
c = (int *) malloc(size);
// initialization of the arrays
for(int i = 0; i < N; i++){
a[i] = b[i] = 1;
}
// Start counter
hipEventCreate(&start);
hipEventRecord(start,0);
// Copy inputs to device
hipMemcpy(dev_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(dev_b, b, size, hipMemcpyHostToDevice);
//dot_prod<<<1,N>>>(dev_a, dev_b, dev_c); // 1 block, N threads (block size)
dot_prod<<<1,64>>>(N, dev_a, dev_b, dev_c);
// Copy result back to host
hipMemcpy(c, dev_c, size, hipMemcpyDeviceToHost);
for( int i = 0; i < N; i++ ){
sum += c[i];
}
// Stop counter
hipEventCreate(&stop);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start,stop);
for( int i = 0; i < N; i++ ){
printf("%d ", c[i]);
}
printf("Dot Product: %d\n", sum);
printf("Elapsed time: %f ms\n", elapsedTime);
// Clean up
free(a); free(b);
hipFree(dev_a); hipFree(dev_b); hipFree(dev_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8dot_prodiPiS_S_
.globl _Z8dot_prodiPiS_S_
.p2align 8
.type _Z8dot_prodiPiS_S_,@function
_Z8dot_prodiPiS_S_:
s_load_b32 s8, s[0:1], 0x0
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s8, v0
s_cbranch_execz .LBB0_3
s_clause 0x2
s_load_b32 s9, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x18
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 2, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s9, 0xffff
s_mov_b32 s9, 0
s_lshl_b32 s10, s1, 2
s_mov_b32 s11, s9
.p2align 6
.LBB0_2:
v_add_co_u32 v3, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v2, vcc_lo
v_add_nc_u32_e32 v0, s1, v0
global_load_b32 v7, v[3:4], off
global_load_b32 v5, v[5:6], off
v_add_co_u32 v3, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s8, v0
v_add_co_u32 v1, s0, v1, s10
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, s0, s9, v2, s0
s_or_b32 s11, vcc_lo, s11
s_waitcnt vmcnt(0)
v_mul_lo_u32 v5, v5, v7
global_store_b32 v[3:4], v5, off
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8dot_prodiPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 12
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8dot_prodiPiS_S_, .Lfunc_end0-_Z8dot_prodiPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8dot_prodiPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 14
.sgpr_spill_count: 0
.symbol: _Z8dot_prodiPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void dot_prod(int n, int *a, int *b, int *c)
{
int index = threadIdx.x;
int stride = blockDim.x;
for (int i = index; i < n; i += stride){ // T threads per iteration
c[i] = a[i] * b[i];
}
}
int main(int argc, char **argv){
int sum = 0;
int N = 100;
int size = N * sizeof(int);
// Create counter
hipEvent_t start, stop;
float elapsedTime;
int *a, *b, *c; // Host copies of a, b, c
int *dev_a, *dev_b, *dev_c; // Device copies of a, b, c
// Allocate space for device copies a, b, c
hipMalloc((void **) &dev_a, size);
hipMalloc((void **) &dev_b, size);
hipMalloc((void **) &dev_c, size);
a = (int *) malloc(size);
b = (int *) malloc(size);
c = (int *) malloc(size);
// initialization of the arrays
for(int i = 0; i < N; i++){
a[i] = b[i] = 1;
}
// Start counter
hipEventCreate(&start);
hipEventRecord(start,0);
// Copy inputs to device
hipMemcpy(dev_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(dev_b, b, size, hipMemcpyHostToDevice);
//dot_prod<<<1,N>>>(dev_a, dev_b, dev_c); // 1 block, N threads (block size)
dot_prod<<<1,64>>>(N, dev_a, dev_b, dev_c);
// Copy result back to host
hipMemcpy(c, dev_c, size, hipMemcpyDeviceToHost);
for( int i = 0; i < N; i++ ){
sum += c[i];
}
// Stop counter
hipEventCreate(&stop);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start,stop);
for( int i = 0; i < N; i++ ){
printf("%d ", c[i]);
}
printf("Dot Product: %d\n", sum);
printf("Elapsed time: %f ms\n", elapsedTime);
// Clean up
free(a); free(b);
hipFree(dev_a); hipFree(dev_b); hipFree(dev_c);
return 0;
} | .text
.file "dot_product.hip"
.globl _Z23__device_stub__dot_prodiPiS_S_ # -- Begin function _Z23__device_stub__dot_prodiPiS_S_
.p2align 4, 0x90
.type _Z23__device_stub__dot_prodiPiS_S_,@function
_Z23__device_stub__dot_prodiPiS_S_: # @_Z23__device_stub__dot_prodiPiS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8dot_prodiPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__dot_prodiPiS_S_, .Lfunc_end0-_Z23__device_stub__dot_prodiPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $160, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
leaq 16(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
leaq 8(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %rbx
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %r14
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1, (%r14,%rax,4)
movl $1, (%rbx,%rax,4)
incq %rax
cmpq $100, %rax
jne .LBB1_1
# %bb.2:
leaq 56(%rsp), %rdi
callq hipEventCreate
movq 56(%rsp), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
movl $400, %edx # imm = 0x190
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $400, %edx # imm = 0x190
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 63(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl $100, 36(%rsp)
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
leaq 36(%rsp), %rax
movq %rax, 64(%rsp)
leaq 152(%rsp), %rax
movq %rax, 72(%rsp)
leaq 144(%rsp), %rax
movq %rax, 80(%rsp)
leaq 136(%rsp), %rax
movq %rax, 88(%rsp)
leaq 40(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8dot_prodiPiS_S_, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $400, %edx # imm = 0x190
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
addl (%r15,%rax,4), %r12d
incq %rax
cmpq $100, %rax
jne .LBB1_5
# %bb.6:
leaq 64(%rsp), %rdi
callq hipEventCreate
movq 64(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 64(%rsp), %rdi
callq hipEventSynchronize
movq 56(%rsp), %rsi
movq 64(%rsp), %rdx
leaq 40(%rsp), %rdi
callq hipEventElapsedTime
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movl (%r15,%r13,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r13
cmpq $100, %r13
jne .LBB1_7
# %bb.8:
movl $.L.str.1, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
movss 40(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $160, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8dot_prodiPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8dot_prodiPiS_S_,@object # @_Z8dot_prodiPiS_S_
.section .rodata,"a",@progbits
.globl _Z8dot_prodiPiS_S_
.p2align 3, 0x0
_Z8dot_prodiPiS_S_:
.quad _Z23__device_stub__dot_prodiPiS_S_
.size _Z8dot_prodiPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Dot Product: %d\n"
.size .L.str.1, 17
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Elapsed time: %f ms\n"
.size .L.str.2, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8dot_prodiPiS_S_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__dot_prodiPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8dot_prodiPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8dot_prodiPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ I2F.U32.RP R5, c[0x0][0x0] ; /* 0x0000000000057b06 */
/* 0x000e220000209000 */
/*0050*/ LOP3.LUT R4, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff047212 */
/* 0x000fe200078e33ff */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0070*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fe20003f45070 */
/*0080*/ BSSY B0, 0x2f0 ; /* 0x0000026000007945 */
/* 0x000fe20003800000 */
/*0090*/ IADD3 R4, R4, c[0x0][0x160], RZ ; /* 0x0000580004047a10 */
/* 0x000fc60007ffe0ff */
/*00a0*/ MUFU.RCP R5, R5 ; /* 0x0000000500057308 */
/* 0x001e240000001000 */
/*00b0*/ IADD3 R2, R5, 0xffffffe, RZ ; /* 0x0ffffffe05027810 */
/* 0x001fcc0007ffe0ff */
/*00c0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00d0*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*00e0*/ IADD3 R7, RZ, -R3, RZ ; /* 0x80000003ff077210 */
/* 0x002fca0007ffe0ff */
/*00f0*/ IMAD R7, R7, c[0x0][0x0], RZ ; /* 0x0000000007077a24 */
/* 0x000fc800078e02ff */
/*0100*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*0110*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fca00078e00ff */
/*0120*/ IADD3 R5, -R3, RZ, RZ ; /* 0x000000ff03057210 */
/* 0x000fca0007ffe1ff */
/*0130*/ IMAD R4, R5, c[0x0][0x0], R4 ; /* 0x0000000005047a24 */
/* 0x000fca00078e0204 */
/*0140*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x0], PT ; /* 0x0000000004007a0c */
/* 0x000fda0003f06070 */
/*0150*/ @P0 IADD3 R4, R4, -c[0x0][0x0], RZ ; /* 0x8000000004040a10 */
/* 0x000fe40007ffe0ff */
/*0160*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fe40007ffe0ff */
/*0170*/ ISETP.GE.U32.AND P1, PT, R4, c[0x0][0x0], PT ; /* 0x0000000004007a0c */
/* 0x000fda0003f26070 */
/*0180*/ @P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103031810 */
/* 0x000fe40007ffe0ff */
/*0190*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x0], RZ, 0x33, !PT ; /* 0x00000000ff03aa12 */
/* 0x000fc800078e33ff */
/*01a0*/ IADD3 R2, R3.reuse, 0x1, RZ ; /* 0x0000000103027810 */
/* 0x040fe40007ffe0ff */
/*01b0*/ ISETP.GE.U32.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f26070 */
/*01c0*/ LOP3.LUT P0, R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fda000780c0ff */
/*01d0*/ @!P0 BRA 0x2e0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*01e0*/ MOV R11, 0x4 ; /* 0x00000004000b7802 */
/* 0x000fe40000000f00 */
/*01f0*/ MOV R8, R2 ; /* 0x0000000200087202 */
/* 0x000fc60000000f00 */
/*0200*/ IMAD.WIDE R2, R0, R11, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fc800078e020b */
/*0210*/ IMAD.WIDE R4, R0, R11, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fc800078e020b */
/*0220*/ IMAD.WIDE R6, R0, R11, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x000fc800078e020b */
/*0230*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x0000a8000c1e1900 */
/*0240*/ LDG.E R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x0002a2000c1e1900 */
/*0250*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fe40007ffe0ff */
/*0260*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x000fe40007ffe0ff */
/*0270*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0280*/ IMAD.WIDE R4, R11, c[0x0][0x0], R4 ; /* 0x000000000b047a25 */
/* 0x001fc800078e0204 */
/*0290*/ IMAD.WIDE R6, R11, c[0x0][0x0], R6 ; /* 0x000000000b067a25 */
/* 0x002fc800078e0206 */
/*02a0*/ IMAD R9, R9, R10, RZ ; /* 0x0000000a09097224 */
/* 0x004fca00078e02ff */
/*02b0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e4000c101904 */
/*02c0*/ IMAD.WIDE R2, R11, c[0x0][0x0], R2 ; /* 0x000000000b027a25 */
/* 0x001fe200078e0202 */
/*02d0*/ @P0 BRA 0x230 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*02e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02f0*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0300*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x002fd400000001ff */
/*0310*/ IMAD.WIDE R6, R0, R3, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0203 */
/*0320*/ IMAD.WIDE R4, R0.reuse, R3.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe200078e0203 */
/*0330*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea8000c1e1900 */
/*0340*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x000ea2000c1e1900 */
/*0350*/ IMAD.WIDE R8, R0, R3, c[0x0][0x178] ; /* 0x00005e0000087625 */
/* 0x000fc800078e0203 */
/*0360*/ IMAD.WIDE R12, R3, c[0x0][0x0], R6 ; /* 0x00000000030c7a25 */
/* 0x000fc800078e0206 */
/*0370*/ IMAD R19, R2, R11, RZ ; /* 0x0000000b02137224 */
/* 0x004fe400078e02ff */
/*0380*/ IMAD.WIDE R10, R3, c[0x0][0x0], R4 ; /* 0x00000000030a7a25 */
/* 0x000fc600078e0204 */
/*0390*/ STG.E [R8.64], R19 ; /* 0x0000001308007986 */
/* 0x0001e8000c101904 */
/*03a0*/ LDG.E R2, [R12.64] ; /* 0x000000040c027981 */
/* 0x000ea8000c1e1900 */
/*03b0*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x000ea2000c1e1900 */
/*03c0*/ IMAD.WIDE R14, R3, c[0x0][0x0], R8 ; /* 0x00000000030e7a25 */
/* 0x000fc800078e0208 */
/*03d0*/ IMAD.WIDE R6, R3, c[0x0][0x0], R12 ; /* 0x0000000003067a25 */
/* 0x000fc800078e020c */
/*03e0*/ IMAD.WIDE R4, R3, c[0x0][0x0], R10 ; /* 0x0000000003047a25 */
/* 0x000fc800078e020a */
/*03f0*/ IMAD R21, R2, R17, RZ ; /* 0x0000001102157224 */
/* 0x004fca00078e02ff */
/*0400*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0003e8000c101904 */
/*0410*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea8000c1e1900 */
/*0420*/ LDG.E R23, [R4.64] ; /* 0x0000000404177981 */
/* 0x000ea2000c1e1900 */
/*0430*/ IMAD.WIDE R16, R3, c[0x0][0x0], R14 ; /* 0x0000000003107a25 */
/* 0x000fc800078e020e */
/*0440*/ IMAD.WIDE R12, R3, c[0x0][0x0], R6 ; /* 0x00000000030c7a25 */
/* 0x000fc800078e0206 */
/*0450*/ IMAD.WIDE R8, R3, c[0x0][0x0], R4 ; /* 0x0000000003087a25 */
/* 0x001fc800078e0204 */
/*0460*/ IMAD R23, R2, R23, RZ ; /* 0x0000001702177224 */
/* 0x004fca00078e02ff */
/*0470*/ STG.E [R16.64], R23 ; /* 0x0000001710007986 */
/* 0x0003e8000c101904 */
/*0480*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea8000c1e1900 */
/*0490*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*04a0*/ MOV R7, c[0x0][0x0] ; /* 0x0000000000077a02 */
/* 0x000fe20000000f00 */
/*04b0*/ IMAD.WIDE R2, R3, c[0x0][0x0], R16 ; /* 0x0000000003027a25 */
/* 0x000fe200078e0210 */
/*04c0*/ MOV R5, c[0x0][0x0] ; /* 0x0000000000057a02 */
/* 0x000fc40000000f00 */
/*04d0*/ LEA R0, R7, R0, 0x1 ; /* 0x0000000007007211 */
/* 0x000fc800078e08ff */
/*04e0*/ LEA R0, R5, R0, 0x1 ; /* 0x0000000005007211 */
/* 0x000fc800078e08ff */
/*04f0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fe20003f06270 */
/*0500*/ IMAD R11, R12, R9, RZ ; /* 0x000000090c0b7224 */
/* 0x004fca00078e02ff */
/*0510*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003ee000c101904 */
/*0520*/ @!P0 BRA 0x300 ; /* 0xfffffdd000008947 */
/* 0x000fea000383ffff */
/*0530*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0540*/ BRA 0x540; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8dot_prodiPiS_S_
.globl _Z8dot_prodiPiS_S_
.p2align 8
.type _Z8dot_prodiPiS_S_,@function
_Z8dot_prodiPiS_S_:
s_load_b32 s8, s[0:1], 0x0
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s8, v0
s_cbranch_execz .LBB0_3
s_clause 0x2
s_load_b32 s9, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x18
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 2, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s9, 0xffff
s_mov_b32 s9, 0
s_lshl_b32 s10, s1, 2
s_mov_b32 s11, s9
.p2align 6
.LBB0_2:
v_add_co_u32 v3, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v2, vcc_lo
v_add_nc_u32_e32 v0, s1, v0
global_load_b32 v7, v[3:4], off
global_load_b32 v5, v[5:6], off
v_add_co_u32 v3, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s8, v0
v_add_co_u32 v1, s0, v1, s10
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, s0, s9, v2, s0
s_or_b32 s11, vcc_lo, s11
s_waitcnt vmcnt(0)
v_mul_lo_u32 v5, v5, v7
global_store_b32 v[3:4], v5, off
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8dot_prodiPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 12
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8dot_prodiPiS_S_, .Lfunc_end0-_Z8dot_prodiPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8dot_prodiPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 14
.sgpr_spill_count: 0
.symbol: _Z8dot_prodiPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e0cc5_00000000-6_dot_product.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z8dot_prodiPiS_S_iPiS_S_
.type _Z32__device_stub__Z8dot_prodiPiS_S_iPiS_S_, @function
_Z32__device_stub__Z8dot_prodiPiS_S_iPiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8dot_prodiPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z8dot_prodiPiS_S_iPiS_S_, .-_Z32__device_stub__Z8dot_prodiPiS_S_iPiS_S_
.globl _Z8dot_prodiPiS_S_
.type _Z8dot_prodiPiS_S_, @function
_Z8dot_prodiPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8dot_prodiPiS_S_iPiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8dot_prodiPiS_S_, .-_Z8dot_prodiPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "Dot Product: %d\n"
.LC2:
.string "Elapsed time: %f ms\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
movl $400, %edi
call malloc@PLT
movq %rax, %r13
movl $400, %edi
call malloc@PLT
movq %rax, %r12
movl $400, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, %eax
.L12:
movl $1, (%r12,%rax)
movl $1, 0(%r13,%rax)
addq $4, %rax
cmpq $400, %rax
jne .L12
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movl $400, %edx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $400, %edx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $64, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 56(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L13:
movl $2, %ecx
movl $400, %edx
movq 32(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rbp
leaq 400(%rbx), %r14
movq %rbx, %rax
movl $0, %edx
.L14:
movl %edx, %ebx
addl (%rax), %ebx
movl %ebx, %edx
addq $4, %rax
cmpq %r14, %rax
jne .L14
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 44(%rsp), %rdi
movq 56(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC0(%rip), %r15
.L15:
movl 0(%rbp), %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbp
cmpq %r14, %rbp
jne .L15
movl %ebx, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 44(%rsp), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movl $100, %edi
call _Z32__device_stub__Z8dot_prodiPiS_S_iPiS_S_
jmp .L13
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z8dot_prodiPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z8dot_prodiPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "dot_product.hip"
.globl _Z23__device_stub__dot_prodiPiS_S_ # -- Begin function _Z23__device_stub__dot_prodiPiS_S_
.p2align 4, 0x90
.type _Z23__device_stub__dot_prodiPiS_S_,@function
_Z23__device_stub__dot_prodiPiS_S_: # @_Z23__device_stub__dot_prodiPiS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8dot_prodiPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__dot_prodiPiS_S_, .Lfunc_end0-_Z23__device_stub__dot_prodiPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $160, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
leaq 16(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
leaq 8(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %rbx
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %r14
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1, (%r14,%rax,4)
movl $1, (%rbx,%rax,4)
incq %rax
cmpq $100, %rax
jne .LBB1_1
# %bb.2:
leaq 56(%rsp), %rdi
callq hipEventCreate
movq 56(%rsp), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
movl $400, %edx # imm = 0x190
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $400, %edx # imm = 0x190
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 63(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl $100, 36(%rsp)
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
leaq 36(%rsp), %rax
movq %rax, 64(%rsp)
leaq 152(%rsp), %rax
movq %rax, 72(%rsp)
leaq 144(%rsp), %rax
movq %rax, 80(%rsp)
leaq 136(%rsp), %rax
movq %rax, 88(%rsp)
leaq 40(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8dot_prodiPiS_S_, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $400, %edx # imm = 0x190
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
addl (%r15,%rax,4), %r12d
incq %rax
cmpq $100, %rax
jne .LBB1_5
# %bb.6:
leaq 64(%rsp), %rdi
callq hipEventCreate
movq 64(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 64(%rsp), %rdi
callq hipEventSynchronize
movq 56(%rsp), %rsi
movq 64(%rsp), %rdx
leaq 40(%rsp), %rdi
callq hipEventElapsedTime
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movl (%r15,%r13,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r13
cmpq $100, %r13
jne .LBB1_7
# %bb.8:
movl $.L.str.1, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
movss 40(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $160, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8dot_prodiPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8dot_prodiPiS_S_,@object # @_Z8dot_prodiPiS_S_
.section .rodata,"a",@progbits
.globl _Z8dot_prodiPiS_S_
.p2align 3, 0x0
_Z8dot_prodiPiS_S_:
.quad _Z23__device_stub__dot_prodiPiS_S_
.size _Z8dot_prodiPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Dot Product: %d\n"
.size .L.str.1, 17
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Elapsed time: %f ms\n"
.size .L.str.2, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8dot_prodiPiS_S_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__dot_prodiPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8dot_prodiPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <stdio.h>
__global__ void K1() {
unsigned num = 0;
unsigned id = blockIdx.x * blockDim.x + threadIdx.x;
for (unsigned ii = 0; ii < id; ++ii)
num += ii;
printf("K1: %d\n", threadIdx.x);
}
__global__ void K2() {
unsigned num = 0;
unsigned id = blockIdx.x * blockDim.x + threadIdx.x;
for (unsigned ii = 0; ii < id; ++ii)
num += ii;
__syncthreads();
printf("K2: %d\n", threadIdx.x);
}
__global__ void K3() {
printf("\tK3\n");
}
int main() {
int *ptr;
cudaStream_t s1, s2, s3;
cudaStreamCreate(&s1);
cudaStreamCreate(&s2);
cudaStreamCreate(&s3);
K1<<<32, 32, 0, s1>>>();
cudaHostAlloc(&ptr, sizeof(int), 0);
K2<<<1, 1024, 0, s2>>>();
K3<<<1, 32, 0, s3>>>();
cudaDeviceSynchronize();
return 0;
} | code for sm_80
Function : _Z2K3v
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x18] ; /* 0x01000600ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x1c] ; /* 0x01000700ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z2K2v
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0050*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0060*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fc800078e00ff */
/*0080*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0002a20000000a00 */
/*0090*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*00a0*/ STL [R1], R8 ; /* 0x0000000801007387 */
/* 0x0013ec0000100800 */
/*00b0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x002fe40000000000 */
/*00c0*/ MOV R11, 0x130 ; /* 0x00000130000b7802 */
/* 0x000fe40000000f00 */
/*00d0*/ MOV R20, 0xb0 ; /* 0x000000b000147802 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0100*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0110*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0120*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x004fea0003c00000 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z2K1v
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0050*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0060*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe40007f1e0ff */
/*0070*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0002a60000000a00 */
/*0080*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*0090*/ STL [R1], R8 ; /* 0x0000000801007387 */
/* 0x0013e80000100800 */
/*00a0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x002fc60000000000 */
/*00b0*/ MOV R11, 0x120 ; /* 0x00000120000b7802 */
/* 0x000fe40000000f00 */
/*00c0*/ MOV R20, 0xa0 ; /* 0x000000a000147802 */
/* 0x000fc40000000f00 */
/*00d0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*00f0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0100*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0110*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x004fea0003c00000 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <stdio.h>
__global__ void K1() {
unsigned num = 0;
unsigned id = blockIdx.x * blockDim.x + threadIdx.x;
for (unsigned ii = 0; ii < id; ++ii)
num += ii;
printf("K1: %d\n", threadIdx.x);
}
__global__ void K2() {
unsigned num = 0;
unsigned id = blockIdx.x * blockDim.x + threadIdx.x;
for (unsigned ii = 0; ii < id; ++ii)
num += ii;
__syncthreads();
printf("K2: %d\n", threadIdx.x);
}
__global__ void K3() {
printf("\tK3\n");
}
int main() {
int *ptr;
cudaStream_t s1, s2, s3;
cudaStreamCreate(&s1);
cudaStreamCreate(&s2);
cudaStreamCreate(&s3);
K1<<<32, 32, 0, s1>>>();
cudaHostAlloc(&ptr, sizeof(int), 0);
K2<<<1, 1024, 0, s2>>>();
K3<<<1, 32, 0, s3>>>();
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_0005d27a_00000000-6_stream3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z20__device_stub__Z2K1vv
.type _Z20__device_stub__Z2K1vv, @function
_Z20__device_stub__Z2K1vv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z2K1v(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z20__device_stub__Z2K1vv, .-_Z20__device_stub__Z2K1vv
.globl _Z2K1v
.type _Z2K1v, @function
_Z2K1v:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z20__device_stub__Z2K1vv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z2K1v, .-_Z2K1v
.globl _Z20__device_stub__Z2K2vv
.type _Z20__device_stub__Z2K2vv, @function
_Z20__device_stub__Z2K2vv:
.LFB2084:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z2K2v(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z20__device_stub__Z2K2vv, .-_Z20__device_stub__Z2K2vv
.globl _Z2K2v
.type _Z2K2v, @function
_Z2K2v:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z20__device_stub__Z2K2vv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z2K2v, .-_Z2K2v
.globl _Z20__device_stub__Z2K3vv
.type _Z20__device_stub__Z2K3vv, @function
_Z20__device_stub__Z2K3vv:
.LFB2086:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z2K3v(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z20__device_stub__Z2K3vv, .-_Z20__device_stub__Z2K3vv
.globl _Z2K3v
.type _Z2K3v, @function
_Z2K3v:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z20__device_stub__Z2K3vv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z2K3v, .-_Z2K3v
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
call cudaStreamCreate@PLT
leaq 16(%rsp), %rdi
call cudaStreamCreate@PLT
leaq 24(%rsp), %rdi
call cudaStreamCreate@PLT
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $32, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movq 8(%rsp), %r9
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L28:
movq %rsp, %rdi
movl $0, %edx
movl $4, %esi
call cudaHostAlloc@PLT
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movq 16(%rsp), %r9
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L29:
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movq 24(%rsp), %r9
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L30:
call cudaDeviceSynchronize@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
call _Z20__device_stub__Z2K1vv
jmp .L28
.L34:
call _Z20__device_stub__Z2K2vv
jmp .L29
.L35:
call _Z20__device_stub__Z2K3vv
jmp .L30
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z2K3v"
.LC1:
.string "_Z2K2v"
.LC2:
.string "_Z2K1v"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z2K3v(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z2K2v(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z2K1v(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <stdio.h>
__global__ void K1() {
unsigned num = 0;
unsigned id = blockIdx.x * blockDim.x + threadIdx.x;
for (unsigned ii = 0; ii < id; ++ii)
num += ii;
printf("K1: %d\n", threadIdx.x);
}
__global__ void K2() {
unsigned num = 0;
unsigned id = blockIdx.x * blockDim.x + threadIdx.x;
for (unsigned ii = 0; ii < id; ++ii)
num += ii;
__syncthreads();
printf("K2: %d\n", threadIdx.x);
}
__global__ void K3() {
printf("\tK3\n");
}
int main() {
int *ptr;
cudaStream_t s1, s2, s3;
cudaStreamCreate(&s1);
cudaStreamCreate(&s2);
cudaStreamCreate(&s3);
K1<<<32, 32, 0, s1>>>();
cudaHostAlloc(&ptr, sizeof(int), 0);
K2<<<1, 1024, 0, s2>>>();
K3<<<1, 32, 0, s3>>>();
cudaDeviceSynchronize();
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void K1() {
unsigned num = 0;
unsigned id = blockIdx.x * blockDim.x + threadIdx.x;
for (unsigned ii = 0; ii < id; ++ii)
num += ii;
printf("K1: %d\n", threadIdx.x);
}
__global__ void K2() {
unsigned num = 0;
unsigned id = blockIdx.x * blockDim.x + threadIdx.x;
for (unsigned ii = 0; ii < id; ++ii)
num += ii;
__syncthreads();
printf("K2: %d\n", threadIdx.x);
}
__global__ void K3() {
printf("\tK3\n");
}
int main() {
int *ptr;
hipStream_t s1, s2, s3;
hipStreamCreate(&s1);
hipStreamCreate(&s2);
hipStreamCreate(&s3);
K1<<<32, 32, 0, s1>>>();
hipHostAlloc(&ptr, sizeof(int), 0);
K2<<<1, 1024, 0, s2>>>();
K3<<<1, 32, 0, s3>>>();
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void K1() {
unsigned num = 0;
unsigned id = blockIdx.x * blockDim.x + threadIdx.x;
for (unsigned ii = 0; ii < id; ++ii)
num += ii;
printf("K1: %d\n", threadIdx.x);
}
__global__ void K2() {
unsigned num = 0;
unsigned id = blockIdx.x * blockDim.x + threadIdx.x;
for (unsigned ii = 0; ii < id; ++ii)
num += ii;
__syncthreads();
printf("K2: %d\n", threadIdx.x);
}
__global__ void K3() {
printf("\tK3\n");
}
int main() {
int *ptr;
hipStream_t s1, s2, s3;
hipStreamCreate(&s1);
hipStreamCreate(&s2);
hipStreamCreate(&s3);
K1<<<32, 32, 0, s1>>>();
hipHostAlloc(&ptr, sizeof(int), 0);
K2<<<1, 1024, 0, s2>>>();
K3<<<1, 32, 0, s3>>>();
hipDeviceSynchronize();
return 0;
} | .text
.file "stream3.hip"
.globl _Z17__device_stub__K1v # -- Begin function _Z17__device_stub__K1v
.p2align 4, 0x90
.type _Z17__device_stub__K1v,@function
_Z17__device_stub__K1v: # @_Z17__device_stub__K1v
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z2K1v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z17__device_stub__K1v, .Lfunc_end0-_Z17__device_stub__K1v
.cfi_endproc
# -- End function
.globl _Z17__device_stub__K2v # -- Begin function _Z17__device_stub__K2v
.p2align 4, 0x90
.type _Z17__device_stub__K2v,@function
_Z17__device_stub__K2v: # @_Z17__device_stub__K2v
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z2K2v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end1:
.size _Z17__device_stub__K2v, .Lfunc_end1-_Z17__device_stub__K2v
.cfi_endproc
# -- End function
.globl _Z17__device_stub__K3v # -- Begin function _Z17__device_stub__K3v
.p2align 4, 0x90
.type _Z17__device_stub__K3v,@function
_Z17__device_stub__K3v: # @_Z17__device_stub__K3v
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z2K3v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end2:
.size _Z17__device_stub__K3v, .Lfunc_end2-_Z17__device_stub__K3v
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $88, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movabsq $4294967328, %rbx # imm = 0x100000020
leaq 72(%rsp), %rdi
callq hipStreamCreate
leaq 64(%rsp), %rdi
callq hipStreamCreate
leaq 56(%rsp), %rdi
callq hipStreamCreate
movq 72(%rsp), %r9
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z2K1v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
leaq 80(%rsp), %rdi
movl $4, %esi
xorl %edx, %edx
callq hipHostAlloc
movq 64(%rsp), %r9
leaq -31(%rbx), %r14
leaq 992(%rbx), %rdx
movq %r14, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z2K2v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_4:
movq 56(%rsp), %r9
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z2K3v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z2K1v, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z2K2v, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z2K3v, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z2K1v,@object # @_Z2K1v
.section .rodata,"a",@progbits
.globl _Z2K1v
.p2align 3, 0x0
_Z2K1v:
.quad _Z17__device_stub__K1v
.size _Z2K1v, 8
.type _Z2K2v,@object # @_Z2K2v
.globl _Z2K2v
.p2align 3, 0x0
_Z2K2v:
.quad _Z17__device_stub__K2v
.size _Z2K2v, 8
.type _Z2K3v,@object # @_Z2K3v
.globl _Z2K3v
.p2align 3, 0x0
_Z2K3v:
.quad _Z17__device_stub__K3v
.size _Z2K3v, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z2K1v"
.size .L__unnamed_1, 7
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z2K2v"
.size .L__unnamed_2, 7
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z2K3v"
.size .L__unnamed_3, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z17__device_stub__K1v
.addrsig_sym _Z17__device_stub__K2v
.addrsig_sym _Z17__device_stub__K3v
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z2K1v
.addrsig_sym _Z2K2v
.addrsig_sym _Z2K3v
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005d27a_00000000-6_stream3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z20__device_stub__Z2K1vv
.type _Z20__device_stub__Z2K1vv, @function
_Z20__device_stub__Z2K1vv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z2K1v(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z20__device_stub__Z2K1vv, .-_Z20__device_stub__Z2K1vv
.globl _Z2K1v
.type _Z2K1v, @function
_Z2K1v:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z20__device_stub__Z2K1vv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z2K1v, .-_Z2K1v
.globl _Z20__device_stub__Z2K2vv
.type _Z20__device_stub__Z2K2vv, @function
_Z20__device_stub__Z2K2vv:
.LFB2084:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z2K2v(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z20__device_stub__Z2K2vv, .-_Z20__device_stub__Z2K2vv
.globl _Z2K2v
.type _Z2K2v, @function
_Z2K2v:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z20__device_stub__Z2K2vv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z2K2v, .-_Z2K2v
.globl _Z20__device_stub__Z2K3vv
.type _Z20__device_stub__Z2K3vv, @function
_Z20__device_stub__Z2K3vv:
.LFB2086:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z2K3v(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z20__device_stub__Z2K3vv, .-_Z20__device_stub__Z2K3vv
.globl _Z2K3v
.type _Z2K3v, @function
_Z2K3v:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z20__device_stub__Z2K3vv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z2K3v, .-_Z2K3v
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
call cudaStreamCreate@PLT
leaq 16(%rsp), %rdi
call cudaStreamCreate@PLT
leaq 24(%rsp), %rdi
call cudaStreamCreate@PLT
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $32, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movq 8(%rsp), %r9
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L28:
movq %rsp, %rdi
movl $0, %edx
movl $4, %esi
call cudaHostAlloc@PLT
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movq 16(%rsp), %r9
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L29:
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movq 24(%rsp), %r9
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L30:
call cudaDeviceSynchronize@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
call _Z20__device_stub__Z2K1vv
jmp .L28
.L34:
call _Z20__device_stub__Z2K2vv
jmp .L29
.L35:
call _Z20__device_stub__Z2K3vv
jmp .L30
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z2K3v"
.LC1:
.string "_Z2K2v"
.LC2:
.string "_Z2K1v"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z2K3v(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z2K2v(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z2K1v(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "stream3.hip"
.globl _Z17__device_stub__K1v # -- Begin function _Z17__device_stub__K1v
.p2align 4, 0x90
.type _Z17__device_stub__K1v,@function
_Z17__device_stub__K1v: # @_Z17__device_stub__K1v
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z2K1v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z17__device_stub__K1v, .Lfunc_end0-_Z17__device_stub__K1v
.cfi_endproc
# -- End function
.globl _Z17__device_stub__K2v # -- Begin function _Z17__device_stub__K2v
.p2align 4, 0x90
.type _Z17__device_stub__K2v,@function
_Z17__device_stub__K2v: # @_Z17__device_stub__K2v
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z2K2v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end1:
.size _Z17__device_stub__K2v, .Lfunc_end1-_Z17__device_stub__K2v
.cfi_endproc
# -- End function
.globl _Z17__device_stub__K3v # -- Begin function _Z17__device_stub__K3v
.p2align 4, 0x90
.type _Z17__device_stub__K3v,@function
_Z17__device_stub__K3v: # @_Z17__device_stub__K3v
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z2K3v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end2:
.size _Z17__device_stub__K3v, .Lfunc_end2-_Z17__device_stub__K3v
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $88, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movabsq $4294967328, %rbx # imm = 0x100000020
leaq 72(%rsp), %rdi
callq hipStreamCreate
leaq 64(%rsp), %rdi
callq hipStreamCreate
leaq 56(%rsp), %rdi
callq hipStreamCreate
movq 72(%rsp), %r9
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z2K1v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
leaq 80(%rsp), %rdi
movl $4, %esi
xorl %edx, %edx
callq hipHostAlloc
movq 64(%rsp), %r9
leaq -31(%rbx), %r14
leaq 992(%rbx), %rdx
movq %r14, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z2K2v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_4:
movq 56(%rsp), %r9
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z2K3v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z2K1v, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z2K2v, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z2K3v, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z2K1v,@object # @_Z2K1v
.section .rodata,"a",@progbits
.globl _Z2K1v
.p2align 3, 0x0
_Z2K1v:
.quad _Z17__device_stub__K1v
.size _Z2K1v, 8
.type _Z2K2v,@object # @_Z2K2v
.globl _Z2K2v
.p2align 3, 0x0
_Z2K2v:
.quad _Z17__device_stub__K2v
.size _Z2K2v, 8
.type _Z2K3v,@object # @_Z2K3v
.globl _Z2K3v
.p2align 3, 0x0
_Z2K3v:
.quad _Z17__device_stub__K3v
.size _Z2K3v, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z2K1v"
.size .L__unnamed_1, 7
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z2K2v"
.size .L__unnamed_2, 7
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z2K3v"
.size .L__unnamed_3, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z17__device_stub__K1v
.addrsig_sym _Z17__device_stub__K2v
.addrsig_sym _Z17__device_stub__K3v
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z2K1v
.addrsig_sym _Z2K2v
.addrsig_sym _Z2K3v
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // nnCount: B*M
// nnDist: B*M*nnSample
// Weight: B*M*nnSample
__global__ void cal_weight(int B, int M, int nnSample, int weightType, float radius,
const int* nnCount, const float* nnDist, float* Weight)
{
// get the neighbor indices
for(int i=blockIdx.x;i<B;i+=gridDim.x)
{
for(int j=threadIdx.x;j<M;j+=blockDim.x)
{
int K = nnCount[i*M+j];
for(int k=0;k<K;k++)
{
float dist = max(nnDist[i*M*nnSample+j*nnSample+k],1e-15);
if (weightType==0)
{
Weight[i*M*nnSample+j*nnSample+k] = float(1)/dist; // inverse sqrt distance
}
else
{
Weight[i*M*nnSample+j*nnSample+k] = max(0.0, 1 - dist/radius); // bilinear like
}
}
}
}
}
void buildSampleWeightLauncher(int B, int M, int nnSample, int weightType, float radius,
const int* nnCount, const float* nnDist, float* Weight)
{
cal_weight<<<B,1024>>>(B, M, nnSample, weightType, radius, nnCount, nnDist, Weight);
} | .file "tmpxft_0001406b_00000000-6_tf_dist2weight_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z10cal_weightiiiifPKiPKfPfiiiifPKiPKfPf
.type _Z41__device_stub__Z10cal_weightiiiifPKiPKfPfiiiifPKiPKfPf, @function
_Z41__device_stub__Z10cal_weightiiiifPKiPKfPfiiiifPKiPKfPf:
.LFB2052:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movl %ecx, 32(%rsp)
movss %xmm0, 28(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq 208(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movq %rsp, %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10cal_weightiiiifPKiPKfPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z41__device_stub__Z10cal_weightiiiifPKiPKfPfiiiifPKiPKfPf, .-_Z41__device_stub__Z10cal_weightiiiifPKiPKfPfiiiifPKiPKfPf
.globl _Z10cal_weightiiiifPKiPKfPf
.type _Z10cal_weightiiiifPKiPKfPf, @function
_Z10cal_weightiiiifPKiPKfPf:
.LFB2053:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z41__device_stub__Z10cal_weightiiiifPKiPKfPfiiiifPKiPKfPf
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z10cal_weightiiiifPKiPKfPf, .-_Z10cal_weightiiiifPKiPKfPf
.globl _Z25buildSampleWeightLauncheriiiifPKiPKfPf
.type _Z25buildSampleWeightLauncheriiiifPKiPKfPf, @function
_Z25buildSampleWeightLauncheriiiifPKiPKfPf:
.LFB2027:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movl %edi, %ebx
movl %esi, %ebp
movl %edx, %r12d
movl %ecx, %r13d
movss %xmm0, 12(%rsp)
movq %r8, %r14
movq %r9, %r15
movl $1024, 36(%rsp)
movl $1, 40(%rsp)
movl %edi, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 120
pushq 120(%rsp)
.cfi_def_cfa_offset 128
movq %r15, %r9
movq %r14, %r8
movss 28(%rsp), %xmm0
movl %r13d, %ecx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z41__device_stub__Z10cal_weightiiiifPKiPKfPfiiiifPKiPKfPf
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z25buildSampleWeightLauncheriiiifPKiPKfPf, .-_Z25buildSampleWeightLauncheriiiifPKiPKfPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10cal_weightiiiifPKiPKfPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10cal_weightiiiifPKiPKfPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // nnCount: B*M
// nnDist: B*M*nnSample
// Weight: B*M*nnSample
__global__ void cal_weight(int B, int M, int nnSample, int weightType, float radius,
const int* nnCount, const float* nnDist, float* Weight)
{
// get the neighbor indices
for(int i=blockIdx.x;i<B;i+=gridDim.x)
{
for(int j=threadIdx.x;j<M;j+=blockDim.x)
{
int K = nnCount[i*M+j];
for(int k=0;k<K;k++)
{
float dist = max(nnDist[i*M*nnSample+j*nnSample+k],1e-15);
if (weightType==0)
{
Weight[i*M*nnSample+j*nnSample+k] = float(1)/dist; // inverse sqrt distance
}
else
{
Weight[i*M*nnSample+j*nnSample+k] = max(0.0, 1 - dist/radius); // bilinear like
}
}
}
}
}
void buildSampleWeightLauncher(int B, int M, int nnSample, int weightType, float radius,
const int* nnCount, const float* nnDist, float* Weight)
{
cal_weight<<<B,1024>>>(B, M, nnSample, weightType, radius, nnCount, nnDist, Weight);
} | #include <hip/hip_runtime.h>
// nnCount: B*M
// nnDist: B*M*nnSample
// Weight: B*M*nnSample
__global__ void cal_weight(int B, int M, int nnSample, int weightType, float radius,
const int* nnCount, const float* nnDist, float* Weight)
{
// get the neighbor indices
for(int i=blockIdx.x;i<B;i+=gridDim.x)
{
for(int j=threadIdx.x;j<M;j+=blockDim.x)
{
int K = nnCount[i*M+j];
for(int k=0;k<K;k++)
{
float dist = max(nnDist[i*M*nnSample+j*nnSample+k],1e-15);
if (weightType==0)
{
Weight[i*M*nnSample+j*nnSample+k] = float(1)/dist; // inverse sqrt distance
}
else
{
Weight[i*M*nnSample+j*nnSample+k] = max(0.0, 1 - dist/radius); // bilinear like
}
}
}
}
}
void buildSampleWeightLauncher(int B, int M, int nnSample, int weightType, float radius,
const int* nnCount, const float* nnDist, float* Weight)
{
cal_weight<<<B,1024>>>(B, M, nnSample, weightType, radius, nnCount, nnDist, Weight);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
// nnCount: B*M
// nnDist: B*M*nnSample
// Weight: B*M*nnSample
__global__ void cal_weight(int B, int M, int nnSample, int weightType, float radius,
const int* nnCount, const float* nnDist, float* Weight)
{
// get the neighbor indices
for(int i=blockIdx.x;i<B;i+=gridDim.x)
{
for(int j=threadIdx.x;j<M;j+=blockDim.x)
{
int K = nnCount[i*M+j];
for(int k=0;k<K;k++)
{
float dist = max(nnDist[i*M*nnSample+j*nnSample+k],1e-15);
if (weightType==0)
{
Weight[i*M*nnSample+j*nnSample+k] = float(1)/dist; // inverse sqrt distance
}
else
{
Weight[i*M*nnSample+j*nnSample+k] = max(0.0, 1 - dist/radius); // bilinear like
}
}
}
}
}
void buildSampleWeightLauncher(int B, int M, int nnSample, int weightType, float radius,
const int* nnCount, const float* nnDist, float* Weight)
{
cal_weight<<<B,1024>>>(B, M, nnSample, weightType, radius, nnCount, nnDist, Weight);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10cal_weightiiiifPKiPKfPf
.globl _Z10cal_weightiiiifPKiPKfPf
.p2align 8
.type _Z10cal_weightiiiifPKiPKfPf,@function
_Z10cal_weightiiiifPKiPKfPf:
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s3
s_cbranch_scc1 .LBB0_13
s_clause 0x3
s_load_b128 s[4:7], s[0:1], 0x4
s_load_b32 s14, s[0:1], 0x30
s_load_b64 s[12:13], s[0:1], 0x28
s_load_b128 s[8:11], s[0:1], 0x18
s_mov_b32 s19, 0x3cd203af
s_mov_b32 s18, 0x9ee75616
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_cmp_lg_u32 s6, 0
v_cmp_gt_i32_e64 s2, s4, v0
s_cselect_b32 s6, -1, 0
s_add_u32 s16, s0, 48
s_mul_i32 s0, s14, s5
s_addc_u32 s17, s1, 0
s_delay_alu instid0(VALU_DEP_2)
v_mul_lo_u32 v6, s5, v1
s_mul_i32 s1, s0, s4
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s20
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v6, s1, v6
s_add_i32 s15, s14, s15
s_cmp_ge_i32 s15, s3
s_cbranch_scc1 .LBB0_13
.LBB0_3:
s_and_saveexec_b32 s20, s2
s_cbranch_execz .LBB0_2
s_load_b32 s0, s[16:17], 0xc
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v1, v6
v_mov_b32_e32 v7, v0
s_mul_i32 s22, s15, s4
s_mov_b32 s24, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s21, s0, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s23, s5, s21
s_branch .LBB0_6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s25
v_add_nc_u32_e32 v7, s21, v7
v_add_nc_u32_e32 v1, s23, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s4, v7
s_or_b32 s24, vcc_lo, s24
s_and_not1_b32 exec_lo, exec_lo, s24
s_cbranch_execz .LBB0_2
.LBB0_6:
v_add_nc_u32_e32 v2, s22, v7
s_mov_b32 s25, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
global_load_b32 v8, v[2:3], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e32 0, v8
s_cbranch_execz .LBB0_5
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s26, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s12, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s13, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s10, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
s_branch .LBB0_9
.LBB0_8:
v_add_nc_u32_e32 v8, -1, v8
global_store_b32 v[2:3], v10, off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v8
v_add_co_u32 v4, s0, v4, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v5, s0, 0, v5, s0
s_or_b32 s26, vcc_lo, s26
s_and_not1_b32 exec_lo, exec_lo, s26
s_cbranch_execz .LBB0_5
.LBB0_9:
global_load_b32 v9, v[4:5], off
s_and_b32 vcc_lo, exec_lo, s6
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[9:10], v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_f64 v[9:10], v[9:10], s[18:19]
v_cvt_f32_f64_e32 v9, v[9:10]
s_cbranch_vccz .LBB0_11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v10, null, s7, s7, v9
v_rcp_f32_e32 v11, v10
s_waitcnt_depctr 0xfff
v_fma_f32 v12, -v10, v11, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v11, v12, v11
v_div_scale_f32 v12, vcc_lo, v9, s7, v9
v_mul_f32_e32 v13, v12, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v14, -v10, v13, v12
v_fmac_f32_e32 v13, v14, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v10, -v10, v13, v12
v_div_fmas_f32 v10, v10, v11, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v10, v10, s7, v9
v_sub_f32_e32 v10, 1.0, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[10:11], v10
v_max_f64 v[10:11], v[10:11], 0
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v10, v[10:11]
s_cbranch_execnz .LBB0_8
s_branch .LBB0_12
.LBB0_11:
.LBB0_12:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v10, null, v9, v9, 1.0
v_rcp_f32_e32 v11, v10
s_waitcnt_depctr 0xfff
v_fma_f32 v12, -v10, v11, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v11, v12, v11
v_div_scale_f32 v12, vcc_lo, 1.0, v9, 1.0
v_mul_f32_e32 v13, v12, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v14, -v10, v13, v12
v_fmac_f32_e32 v13, v14, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v10, -v10, v13, v12
v_div_fmas_f32 v10, v10, v11, v13
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v10, v10, v9, 1.0
s_branch .LBB0_8
.LBB0_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10cal_weightiiiifPKiPKfPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 27
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10cal_weightiiiifPKiPKfPf, .Lfunc_end0-_Z10cal_weightiiiifPKiPKfPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10cal_weightiiiifPKiPKfPf
.private_segment_fixed_size: 0
.sgpr_count: 29
.sgpr_spill_count: 0
.symbol: _Z10cal_weightiiiifPKiPKfPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
// nnCount: B*M
// nnDist: B*M*nnSample
// Weight: B*M*nnSample
__global__ void cal_weight(int B, int M, int nnSample, int weightType, float radius,
const int* nnCount, const float* nnDist, float* Weight)
{
// get the neighbor indices
for(int i=blockIdx.x;i<B;i+=gridDim.x)
{
for(int j=threadIdx.x;j<M;j+=blockDim.x)
{
int K = nnCount[i*M+j];
for(int k=0;k<K;k++)
{
float dist = max(nnDist[i*M*nnSample+j*nnSample+k],1e-15);
if (weightType==0)
{
Weight[i*M*nnSample+j*nnSample+k] = float(1)/dist; // inverse sqrt distance
}
else
{
Weight[i*M*nnSample+j*nnSample+k] = max(0.0, 1 - dist/radius); // bilinear like
}
}
}
}
}
void buildSampleWeightLauncher(int B, int M, int nnSample, int weightType, float radius,
const int* nnCount, const float* nnDist, float* Weight)
{
cal_weight<<<B,1024>>>(B, M, nnSample, weightType, radius, nnCount, nnDist, Weight);
} | .text
.file "tf_dist2weight_gpu.hip"
.globl _Z25__device_stub__cal_weightiiiifPKiPKfPf # -- Begin function _Z25__device_stub__cal_weightiiiifPKiPKfPf
.p2align 4, 0x90
.type _Z25__device_stub__cal_weightiiiifPKiPKfPf,@function
_Z25__device_stub__cal_weightiiiifPKiPKfPf: # @_Z25__device_stub__cal_weightiiiifPKiPKfPf
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %r8, 88(%rsp)
movq %r9, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rax
movq %rax, 144(%rsp)
leaq 176(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10cal_weightiiiifPKiPKfPf, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z25__device_stub__cal_weightiiiifPKiPKfPf, .Lfunc_end0-_Z25__device_stub__cal_weightiiiifPKiPKfPf
.cfi_endproc
# -- End function
.globl _Z25buildSampleWeightLauncheriiiifPKiPKfPf # -- Begin function _Z25buildSampleWeightLauncheriiiifPKiPKfPf
.p2align 4, 0x90
.type _Z25buildSampleWeightLauncheriiiifPKiPKfPf,@function
_Z25buildSampleWeightLauncheriiiifPKiPKfPf: # @_Z25buildSampleWeightLauncheriiiifPKiPKfPf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movq %r8, %r14
movss %xmm0, (%rsp) # 4-byte Spill
movl %ecx, %ebp
movl %edx, %r15d
movl %esi, %r12d
movl %edi, %r13d
movl %edi, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 224(%rsp), %rax
movl %r13d, 20(%rsp)
movl %r12d, 16(%rsp)
movl %r15d, 12(%rsp)
movl %ebp, 8(%rsp)
movss (%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 4(%rsp)
movq %r14, 88(%rsp)
movq %rbx, 80(%rsp)
movq %rax, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10cal_weightiiiifPKiPKfPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z25buildSampleWeightLauncheriiiifPKiPKfPf, .Lfunc_end1-_Z25buildSampleWeightLauncheriiiifPKiPKfPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10cal_weightiiiifPKiPKfPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10cal_weightiiiifPKiPKfPf,@object # @_Z10cal_weightiiiifPKiPKfPf
.section .rodata,"a",@progbits
.globl _Z10cal_weightiiiifPKiPKfPf
.p2align 3, 0x0
_Z10cal_weightiiiifPKiPKfPf:
.quad _Z25__device_stub__cal_weightiiiifPKiPKfPf
.size _Z10cal_weightiiiifPKiPKfPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10cal_weightiiiifPKiPKfPf"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__cal_weightiiiifPKiPKfPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10cal_weightiiiifPKiPKfPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001406b_00000000-6_tf_dist2weight_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z10cal_weightiiiifPKiPKfPfiiiifPKiPKfPf
.type _Z41__device_stub__Z10cal_weightiiiifPKiPKfPfiiiifPKiPKfPf, @function
_Z41__device_stub__Z10cal_weightiiiifPKiPKfPfiiiifPKiPKfPf:
.LFB2052:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movl %ecx, 32(%rsp)
movss %xmm0, 28(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq 208(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movq %rsp, %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10cal_weightiiiifPKiPKfPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z41__device_stub__Z10cal_weightiiiifPKiPKfPfiiiifPKiPKfPf, .-_Z41__device_stub__Z10cal_weightiiiifPKiPKfPfiiiifPKiPKfPf
.globl _Z10cal_weightiiiifPKiPKfPf
.type _Z10cal_weightiiiifPKiPKfPf, @function
_Z10cal_weightiiiifPKiPKfPf:
.LFB2053:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z41__device_stub__Z10cal_weightiiiifPKiPKfPfiiiifPKiPKfPf
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z10cal_weightiiiifPKiPKfPf, .-_Z10cal_weightiiiifPKiPKfPf
.globl _Z25buildSampleWeightLauncheriiiifPKiPKfPf
.type _Z25buildSampleWeightLauncheriiiifPKiPKfPf, @function
_Z25buildSampleWeightLauncheriiiifPKiPKfPf:
.LFB2027:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movl %edi, %ebx
movl %esi, %ebp
movl %edx, %r12d
movl %ecx, %r13d
movss %xmm0, 12(%rsp)
movq %r8, %r14
movq %r9, %r15
movl $1024, 36(%rsp)
movl $1, 40(%rsp)
movl %edi, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 120
pushq 120(%rsp)
.cfi_def_cfa_offset 128
movq %r15, %r9
movq %r14, %r8
movss 28(%rsp), %xmm0
movl %r13d, %ecx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z41__device_stub__Z10cal_weightiiiifPKiPKfPfiiiifPKiPKfPf
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z25buildSampleWeightLauncheriiiifPKiPKfPf, .-_Z25buildSampleWeightLauncheriiiifPKiPKfPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10cal_weightiiiifPKiPKfPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10cal_weightiiiifPKiPKfPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "tf_dist2weight_gpu.hip"
.globl _Z25__device_stub__cal_weightiiiifPKiPKfPf # -- Begin function _Z25__device_stub__cal_weightiiiifPKiPKfPf
.p2align 4, 0x90
.type _Z25__device_stub__cal_weightiiiifPKiPKfPf,@function
_Z25__device_stub__cal_weightiiiifPKiPKfPf: # @_Z25__device_stub__cal_weightiiiifPKiPKfPf
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %r8, 88(%rsp)
movq %r9, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rax
movq %rax, 144(%rsp)
leaq 176(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10cal_weightiiiifPKiPKfPf, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z25__device_stub__cal_weightiiiifPKiPKfPf, .Lfunc_end0-_Z25__device_stub__cal_weightiiiifPKiPKfPf
.cfi_endproc
# -- End function
.globl _Z25buildSampleWeightLauncheriiiifPKiPKfPf # -- Begin function _Z25buildSampleWeightLauncheriiiifPKiPKfPf
.p2align 4, 0x90
.type _Z25buildSampleWeightLauncheriiiifPKiPKfPf,@function
_Z25buildSampleWeightLauncheriiiifPKiPKfPf: # @_Z25buildSampleWeightLauncheriiiifPKiPKfPf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movq %r8, %r14
movss %xmm0, (%rsp) # 4-byte Spill
movl %ecx, %ebp
movl %edx, %r15d
movl %esi, %r12d
movl %edi, %r13d
movl %edi, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 224(%rsp), %rax
movl %r13d, 20(%rsp)
movl %r12d, 16(%rsp)
movl %r15d, 12(%rsp)
movl %ebp, 8(%rsp)
movss (%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 4(%rsp)
movq %r14, 88(%rsp)
movq %rbx, 80(%rsp)
movq %rax, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10cal_weightiiiifPKiPKfPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z25buildSampleWeightLauncheriiiifPKiPKfPf, .Lfunc_end1-_Z25buildSampleWeightLauncheriiiifPKiPKfPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10cal_weightiiiifPKiPKfPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10cal_weightiiiifPKiPKfPf,@object # @_Z10cal_weightiiiifPKiPKfPf
.section .rodata,"a",@progbits
.globl _Z10cal_weightiiiifPKiPKfPf
.p2align 3, 0x0
_Z10cal_weightiiiifPKiPKfPf:
.quad _Z25__device_stub__cal_weightiiiifPKiPKfPf
.size _Z10cal_weightiiiifPKiPKfPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10cal_weightiiiifPKiPKfPf"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__cal_weightiiiifPKiPKfPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10cal_weightiiiifPKiPKfPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void zero_vector_int(int *vec, const int n)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
if ( xIndex < n ){
int z=0;
vec[xIndex]=z;
}
} | code for sm_80
Function : _Z15zero_vector_intPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0003 */
/*0090*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void zero_vector_int(int *vec, const int n)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
if ( xIndex < n ){
int z=0;
vec[xIndex]=z;
}
} | .file "tmpxft_000ebd3a_00000000-6_zero_vector_int.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z15zero_vector_intPiiPii
.type _Z36__device_stub__Z15zero_vector_intPiiPii, @function
_Z36__device_stub__Z15zero_vector_intPiiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15zero_vector_intPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z15zero_vector_intPiiPii, .-_Z36__device_stub__Z15zero_vector_intPiiPii
.globl _Z15zero_vector_intPii
.type _Z15zero_vector_intPii, @function
_Z15zero_vector_intPii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z15zero_vector_intPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15zero_vector_intPii, .-_Z15zero_vector_intPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15zero_vector_intPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15zero_vector_intPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void zero_vector_int(int *vec, const int n)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
if ( xIndex < n ){
int z=0;
vec[xIndex]=z;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void zero_vector_int(int *vec, const int n)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
if ( xIndex < n ){
int z=0;
vec[xIndex]=z;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void zero_vector_int(int *vec, const int n)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
if ( xIndex < n ){
int z=0;
vec[xIndex]=z;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15zero_vector_intPii
.globl _Z15zero_vector_intPii
.p2align 8
.type _Z15zero_vector_intPii,@function
_Z15zero_vector_intPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15zero_vector_intPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15zero_vector_intPii, .Lfunc_end0-_Z15zero_vector_intPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15zero_vector_intPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15zero_vector_intPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void zero_vector_int(int *vec, const int n)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
if ( xIndex < n ){
int z=0;
vec[xIndex]=z;
}
} | .text
.file "zero_vector_int.hip"
.globl _Z30__device_stub__zero_vector_intPii # -- Begin function _Z30__device_stub__zero_vector_intPii
.p2align 4, 0x90
.type _Z30__device_stub__zero_vector_intPii,@function
_Z30__device_stub__zero_vector_intPii: # @_Z30__device_stub__zero_vector_intPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z15zero_vector_intPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z30__device_stub__zero_vector_intPii, .Lfunc_end0-_Z30__device_stub__zero_vector_intPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15zero_vector_intPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15zero_vector_intPii,@object # @_Z15zero_vector_intPii
.section .rodata,"a",@progbits
.globl _Z15zero_vector_intPii
.p2align 3, 0x0
_Z15zero_vector_intPii:
.quad _Z30__device_stub__zero_vector_intPii
.size _Z15zero_vector_intPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15zero_vector_intPii"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__zero_vector_intPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15zero_vector_intPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15zero_vector_intPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0003 */
/*0090*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15zero_vector_intPii
.globl _Z15zero_vector_intPii
.p2align 8
.type _Z15zero_vector_intPii,@function
_Z15zero_vector_intPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15zero_vector_intPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15zero_vector_intPii, .Lfunc_end0-_Z15zero_vector_intPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15zero_vector_intPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15zero_vector_intPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ebd3a_00000000-6_zero_vector_int.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z15zero_vector_intPiiPii
.type _Z36__device_stub__Z15zero_vector_intPiiPii, @function
_Z36__device_stub__Z15zero_vector_intPiiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15zero_vector_intPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z15zero_vector_intPiiPii, .-_Z36__device_stub__Z15zero_vector_intPiiPii
.globl _Z15zero_vector_intPii
.type _Z15zero_vector_intPii, @function
_Z15zero_vector_intPii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z15zero_vector_intPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15zero_vector_intPii, .-_Z15zero_vector_intPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15zero_vector_intPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15zero_vector_intPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "zero_vector_int.hip"
.globl _Z30__device_stub__zero_vector_intPii # -- Begin function _Z30__device_stub__zero_vector_intPii
.p2align 4, 0x90
.type _Z30__device_stub__zero_vector_intPii,@function
_Z30__device_stub__zero_vector_intPii: # @_Z30__device_stub__zero_vector_intPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z15zero_vector_intPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z30__device_stub__zero_vector_intPii, .Lfunc_end0-_Z30__device_stub__zero_vector_intPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15zero_vector_intPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15zero_vector_intPii,@object # @_Z15zero_vector_intPii
.section .rodata,"a",@progbits
.globl _Z15zero_vector_intPii
.p2align 3, 0x0
_Z15zero_vector_intPii:
.quad _Z30__device_stub__zero_vector_intPii
.size _Z15zero_vector_intPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15zero_vector_intPii"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__zero_vector_intPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15zero_vector_intPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void kernel(float *id, float *od, int w, int h, int depth)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int z = blockIdx.z * blockDim.z + threadIdx.z;
const int dataTotalSize = w * h * depth;
const int radius = 2;
const int filter_size = 2*radius + 1;
const int sW = 6; /* sW == 2 * filter_radius + blockDim.x (or same as 2 * filter_radius + blockDim.y) */
/* boarder do not concerned */
if(x >= w || y >= h || z >= depth)
return;
else
{
//global defined
int idx = z*w*h+y*w+x;
//3d grid(blocks) 2d block(threads)
int threadsPerBlock = blockDim.x * blockDim.y;
int blockId = blockIdx.x + blockIdx.y * gridDim.x
+ gridDim.x * gridDim.y * blockIdx.z;
int threadId = (blockId * threadsPerBlock)
+ (threadIdx.y * blockDim.x) + threadIdx.x;
int g_Idx = threadId;
//2d shared memory working
__shared__ unsigned char smem[sW][sW];
int s_Idx = threadIdx.x + (threadIdx.y * sW);
int s_IdxY = s_Idx / sW;
int s_IdxX = s_Idx % sW;
//Here: definition error, need edit, haven't finished yet.
//int g_IdxY = s_IdxY + (blockIdx.y * blockDim.y);
//int g_IdxX = s_IdxX + (blockIdx.x * blockDim.x);
//int g_Idx = g_IdxX + (g_IdxY * w);
//32 threads working together per warp
if(s_IdxY < sW && s_IdxX < sW) //Here: boarder concerned error, need edit
{
if(x >= 0 && y < w && y >= 0 && y < h && z >= 0 && z < depth ) //Here: boarder concerned error, need edit
smem[s_IdxY][s_IdxX] = id[g_Idx];
else
smem[s_IdxY][s_IdxX] = 0;
__syncthreads();
}
/*compute the sum using shared memory*/
float avg = 0.0;
for (int i = -radius; i <= radius; i++){
if(s_IdxY + i < 0 /*|| g_IdxY > h*/ ) //Here: boarder concerned error, need edit
avg += 0.0;
else
avg += smem[s_IdxY+i][s_IdxX];
}
/*register to global, by now thread*/
avg /= filter_size;
if(idx < dataTotalSize)
od[idx] = avg;
}
} | code for sm_80
Function : _Z6kernelPfS_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R11, SR_TID.Y ; /* 0x00000000000b7919 */
/* 0x000e280000002200 */
/*0030*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e680000002500 */
/*0040*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e680000002100 */
/*0050*/ S2R R5, SR_CTAID.Z ; /* 0x0000000000057919 */
/* 0x000ea80000002700 */
/*0060*/ S2R R4, SR_TID.Z ; /* 0x0000000000047919 */
/* 0x000ea20000002300 */
/*0070*/ IMAD R3, R0, c[0x0][0x4], R11 ; /* 0x0000010000037a24 */
/* 0x001fca00078e020b */
/*0080*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */
/* 0x000fe20003f06270 */
/*0090*/ IMAD R2, R9, c[0x0][0x0], R6 ; /* 0x0000000009027a24 */
/* 0x002fca00078e0206 */
/*00a0*/ ISETP.GE.OR P0, PT, R2, c[0x0][0x170], P0 ; /* 0x00005c0002007a0c */
/* 0x000fe20000706670 */
/*00b0*/ IMAD R4, R5, c[0x0][0x8], R4 ; /* 0x0000020005047a24 */
/* 0x004fca00078e0204 */
/*00c0*/ ISETP.GE.OR P0, PT, R4, c[0x0][0x178], P0 ; /* 0x00005e0004007a0c */
/* 0x000fda0000706670 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ IMAD R7, R11, 0x6, R6 ; /* 0x000000060b077824 */
/* 0x000fe200078e0206 */
/*00f0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0100*/ IMAD R0, R5, c[0x0][0x10], R0 ; /* 0x0000040005007a24 */
/* 0x000fe400078e0200 */
/*0110*/ IMAD.HI R5, R7.reuse, 0x2aaaaaab, RZ ; /* 0x2aaaaaab07057827 */
/* 0x040fe200078e02ff */
/*0120*/ ISETP.GT.AND P0, PT, R7, 0x23, PT ; /* 0x000000230700780c */
/* 0x000fc60003f04270 */
/*0130*/ IMAD R0, R0, c[0x0][0xc], R9 ; /* 0x0000030000007a24 */
/* 0x000fe200078e0209 */
/*0140*/ LEA.HI R8, R5, R5, RZ, 0x1 ; /* 0x0000000505087211 */
/* 0x000fe200078f08ff */
/*0150*/ IMAD R5, R4, c[0x0][0x174], R3 ; /* 0x00005d0004057a24 */
/* 0x000fe400078e0203 */
/*0160*/ IMAD R0, R0, c[0x0][0x4], R11 ; /* 0x0000010000007a24 */
/* 0x000fe400078e020b */
/*0170*/ IMAD R9, R8, -0x6, R7 ; /* 0xfffffffa08097824 */
/* 0x000fe400078e0207 */
/*0180*/ IMAD R6, R0, c[0x0][0x0], R6 ; /* 0x0000000000067a24 */
/* 0x000fe400078e0206 */
/*0190*/ IMAD R9, R8, 0x6, R9 ; /* 0x0000000608097824 */
/* 0x000fc400078e0209 */
/*01a0*/ IMAD R0, R5, c[0x0][0x170], R2 ; /* 0x00005c0005007a24 */
/* 0x000fe200078e0202 */
/*01b0*/ @P0 BRA 0x280 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*01c0*/ LOP3.LUT R2, R4, R2, R3, 0xfe, !PT ; /* 0x0000000204027212 */
/* 0x000fe400078efe03 */
/*01d0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fc80003f06270 */
/*01e0*/ ISETP.GT.AND P0, PT, R2, -0x1, !P0 ; /* 0xffffffff0200780c */
/* 0x000fda0004704270 */
/*01f0*/ @!P0 STS.U8 [R9], RZ ; /* 0x000000ff09008388 */
/* 0x0001e20000000000 */
/*0200*/ @!P0 BRA 0x260 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0210*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0220*/ IMAD.WIDE R2, R6, R3, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fcc00078e0203 */
/*0230*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea4000c1e1900 */
/*0240*/ F2I.U32.TRUNC.NTZ R4, R2 ; /* 0x0000000200047305 */
/* 0x004e64000020f000 */
/*0250*/ STS.U8 [R9], R4 ; /* 0x0000000409007388 */
/* 0x0023e40000000000 */
/*0260*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0270*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0280*/ ISETP.GE.AND P3, PT, R7.reuse, 0xc, PT ; /* 0x0000000c0700780c */
/* 0x040fe20003f66270 */
/*0290*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe200078e00ff */
/*02a0*/ ISETP.GE.AND P4, PT, R7.reuse, 0x6, PT ; /* 0x000000060700780c */
/* 0x040fe20003f86270 */
/*02b0*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000a00 */
/*02c0*/ ISETP.GE.AND P2, PT, R7.reuse, -0x5, PT ; /* 0xfffffffb0700780c */
/* 0x040fe20003f46270 */
/*02d0*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*02e0*/ ISETP.GE.AND P0, PT, R7, -0xb, PT ; /* 0xfffffff50700780c */
/* 0x000fc40003f06270 */
/*02f0*/ ISETP.GE.AND P1, PT, R7, -0x11, PT ; /* 0xffffffef0700780c */
/* 0x000fe20003f26270 */
/*0300*/ ULDC UR5, c[0x0][0x178] ; /* 0x00005e0000057ab9 */
/* 0x000fe40000000800 */
/*0310*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fe4000f8e023f */
/*0320*/ @P3 LDS.U8 R3, [R9+-0xc] ; /* 0xfffff40009033984 */
/* 0x000ea80000000000 */
/*0330*/ @P4 LDS.U8 R5, [R9+-0x6] ; /* 0xfffffa0009054984 */
/* 0x000ee80000000000 */
/*0340*/ @P2 LDS.U8 R6, [R9] ; /* 0x0000000009062984 */
/* 0x000f280000000000 */
/*0350*/ @P0 LDS.U8 R8, [R9+0x6] ; /* 0x0000060009080984 */
/* 0x000f680000000000 */
/*0360*/ @P1 LDS.U8 R10, [R9+0xc] ; /* 0x00000c00090a1984 */
/* 0x000e220000000000 */
/*0370*/ @P3 I2F.U16 R2, R3 ; /* 0x0000000300023306 */
/* 0x004fe20000101000 */
/*0380*/ ISETP.GE.AND P3, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fce000bf66270 */
/*0390*/ @P4 I2F.U16 R5, R5 ; /* 0x0000000500054306 */
/* 0x008eb00000101000 */
/*03a0*/ @P2 I2F.U16 R7, R6 ; /* 0x0000000600072306 */
/* 0x010ef00000101000 */
/*03b0*/ @P0 I2F.U16 R11, R8 ; /* 0x00000008000b0306 */
/* 0x020f220000101000 */
/*03c0*/ @P4 FADD R4, R5, R2 ; /* 0x0000000205044221 */
/* 0x006fc40000000000 */
/*03d0*/ @!P4 FADD R4, RZ, R2 ; /* 0x00000002ff04c221 */
/* 0x000fca0000000000 */
/*03e0*/ @P1 I2F.U16 R10, R10 ; /* 0x0000000a000a1306 */
/* 0x001e220000101000 */
/*03f0*/ @P2 FADD R2, R7, R4.reuse ; /* 0x0000000407022221 */
/* 0x108fe40000000000 */
/*0400*/ @!P2 FADD R2, RZ, R4 ; /* 0x00000004ff02a221 */
/* 0x000fc80000000000 */
/*0410*/ @P0 FADD R3, R11, R2 ; /* 0x000000020b030221 */
/* 0x010fe20000000000 */
/*0420*/ @P3 EXIT ; /* 0x000000000000394d */
/* 0x000fec0003800000 */
/*0430*/ @!P0 FADD R3, RZ, R2 ; /* 0x00000002ff038221 */
/* 0x000fe20000000000 */
/*0440*/ BSSY B1, 0x550 ; /* 0x0000010000017945 */
/* 0x000fe20003800000 */
/*0450*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3e4ccccd ; /* 0x3e4ccccdff057424 */
/* 0x000fe400078e00ff */
/*0460*/ @P1 FADD R2, R10, R3.reuse ; /* 0x000000030a021221 */
/* 0x101fe40000000000 */
/*0470*/ @!P1 FADD R2, RZ, R3 ; /* 0x00000003ff029221 */
/* 0x000fe40000000000 */
/*0480*/ IMAD.MOV.U32 R4, RZ, RZ, 0x40a00000 ; /* 0x40a00000ff047424 */
/* 0x000fe400078e00ff */
/*0490*/ FCHK P0, R2, 5 ; /* 0x40a0000002007902 */
/* 0x000e240000000000 */
/*04a0*/ FFMA R4, R5, -R4, 1 ; /* 0x3f80000005047423 */
/* 0x000fc80000000804 */
/*04b0*/ FFMA R3, R4, R5, 0.20000000298023223877 ; /* 0x3e4ccccd04037423 */
/* 0x000fc80000000005 */
/*04c0*/ FFMA R4, R3, R2, RZ ; /* 0x0000000203047223 */
/* 0x000fc800000000ff */
/*04d0*/ FFMA R5, R4, -5, R2 ; /* 0xc0a0000004057823 */
/* 0x000fc80000000002 */
/*04e0*/ FFMA R5, R3, R5, R4 ; /* 0x0000000503057223 */
/* 0x000fe20000000004 */
/*04f0*/ @!P0 BRA 0x540 ; /* 0x0000004000008947 */
/* 0x001fea0003800000 */
/*0500*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*0510*/ MOV R2, 0x530 ; /* 0x0000053000027802 */
/* 0x000fe40000000f00 */
/*0520*/ CALL.REL.NOINC 0x590 ; /* 0x0000006000007944 */
/* 0x000fea0003c00000 */
/*0530*/ MOV R5, R7 ; /* 0x0000000700057202 */
/* 0x001fe40000000f00 */
/*0540*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0550*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0560*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0203 */
/*0570*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101906 */
/*0580*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0590*/ SHF.R.U32.HI R3, RZ, 0x17, R7.reuse ; /* 0x00000017ff037819 */
/* 0x100fe20000011607 */
/*05a0*/ BSSY B0, 0xb70 ; /* 0x000005c000007945 */
/* 0x000fe20003800000 */
/*05b0*/ BSSY B2, 0x760 ; /* 0x000001a000027945 */
/* 0x000fe40003800000 */
/*05c0*/ LOP3.LUT R5, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff03057812 */
/* 0x000fe200078ec0ff */
/*05d0*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fc600078e0007 */
/*05e0*/ IADD3 R6, R5, -0x1, RZ ; /* 0xffffffff05067810 */
/* 0x000fc80007ffe0ff */
/*05f0*/ ISETP.GT.U32.OR P0, PT, R6, 0xfd, !PT ; /* 0x000000fd0600780c */
/* 0x000fda0007f04470 */
/*0600*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff048224 */
/* 0x000fe200078e00ff */
/*0610*/ @!P0 BRA 0x750 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0620*/ FSETP.GTU.FTZ.AND P0, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fda0003f1c200 */
/*0630*/ @P0 BREAK B2 ; /* 0x0000000000020942 */
/* 0x000fe20003800000 */
/*0640*/ @P0 BRA 0xb50 ; /* 0x0000050000000947 */
/* 0x000fea0003800000 */
/*0650*/ IMAD.MOV.U32 R4, RZ, RZ, 0x40a00000 ; /* 0x40a00000ff047424 */
/* 0x000fca00078e00ff */
/*0660*/ LOP3.LUT P0, RZ, R4, 0x7fffffff, R3, 0xc8, !PT ; /* 0x7fffffff04ff7812 */
/* 0x000fda000780c803 */
/*0670*/ @!P0 BREAK B2 ; /* 0x0000000000028942 */
/* 0x000fe20003800000 */
/*0680*/ @!P0 BRA 0xb30 ; /* 0x000004a000008947 */
/* 0x000fea0003800000 */
/*0690*/ LOP3.LUT P0, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff03ff7812 */
/* 0x000fda000780c0ff */
/*06a0*/ @!P0 BREAK B2 ; /* 0x0000000000028942 */
/* 0x000fe20003800000 */
/*06b0*/ @!P0 BRA 0xb10 ; /* 0x0000045000008947 */
/* 0x000fea0003800000 */
/*06c0*/ FSETP.NEU.FTZ.AND P1, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fe40003f3d200 */
/*06d0*/ LOP3.LUT P0, RZ, R4, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff04ff7812 */
/* 0x000fc8000780c0ff */
/*06e0*/ PLOP3.LUT P0, PT, P1, P0, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f00572 */
/*06f0*/ @P0 BREAK B2 ; /* 0x0000000000020942 */
/* 0x000fe20003800000 */
/*0700*/ @P0 BRA 0xae0 ; /* 0x000003d000000947 */
/* 0x000fea0003800000 */
/*0710*/ ISETP.GE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f06270 */
/*0720*/ @P0 MOV R4, RZ ; /* 0x000000ff00040202 */
/* 0x000fe20000000f00 */
/*0730*/ @!P0 FFMA R3, R7, 1.84467440737095516160e+19, RZ ; /* 0x5f80000007038823 */
/* 0x000fe400000000ff */
/*0740*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, -0x40 ; /* 0xffffffc0ff048424 */
/* 0x000fe400078e00ff */
/*0750*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0760*/ UMOV UR4, 0x40a00000 ; /* 0x40a0000000047882 */
/* 0x000fe20000000000 */
/*0770*/ IADD3 R5, R5, -0x7f, RZ ; /* 0xffffff8105057810 */
/* 0x000fe20007ffe0ff */
/*0780*/ UIADD3 UR4, UR4, -0x1000000, URZ ; /* 0xff00000004047890 */
/* 0x000fe2000fffe03f */
/*0790*/ BSSY B2, 0xad0 ; /* 0x0000033000027945 */
/* 0x000fe40003800000 */
/*07a0*/ IADD3 R4, R4, -0x2, R5 ; /* 0xfffffffe04047810 */
/* 0x000fe20007ffe005 */
/*07b0*/ IMAD R3, R5, -0x800000, R3 ; /* 0xff80000005037824 */
/* 0x000fe400078e0203 */
/*07c0*/ FADD.FTZ R8, -RZ, -UR4 ; /* 0x80000004ff087e21 */
/* 0x000fc60008010100 */
/*07d0*/ MUFU.RCP R6, UR4 ; /* 0x0000000400067d08 */
/* 0x000e240008001000 */
/*07e0*/ FFMA R7, R6, R8, 1 ; /* 0x3f80000006077423 */
/* 0x001fc80000000008 */
/*07f0*/ FFMA R6, R6, R7, R6 ; /* 0x0000000706067223 */
/* 0x000fc80000000006 */
/*0800*/ FFMA R7, R3, R6, RZ ; /* 0x0000000603077223 */
/* 0x000fc800000000ff */
/*0810*/ FFMA R9, R8, R7, R3 ; /* 0x0000000708097223 */
/* 0x000fc80000000003 */
/*0820*/ FFMA R9, R6, R9, R7 ; /* 0x0000000906097223 */
/* 0x000fc80000000007 */
/*0830*/ FFMA R8, R8, R9, R3 ; /* 0x0000000908087223 */
/* 0x000fc80000000003 */
/*0840*/ FFMA R7, R6, R8, R9 ; /* 0x0000000806077223 */
/* 0x000fca0000000009 */
/*0850*/ SHF.R.U32.HI R3, RZ, 0x17, R7 ; /* 0x00000017ff037819 */
/* 0x000fc80000011607 */
/*0860*/ LOP3.LUT R3, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff03037812 */
/* 0x000fca00078ec0ff */
/*0870*/ IMAD.IADD R10, R3, 0x1, R4 ; /* 0x00000001030a7824 */
/* 0x000fca00078e0204 */
/*0880*/ IADD3 R3, R10, -0x1, RZ ; /* 0xffffffff0a037810 */
/* 0x000fc80007ffe0ff */
/*0890*/ ISETP.GE.U32.AND P0, PT, R3, 0xfe, PT ; /* 0x000000fe0300780c */
/* 0x000fda0003f06070 */
/*08a0*/ @!P0 BRA 0xab0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*08b0*/ ISETP.GT.AND P0, PT, R10, 0xfe, PT ; /* 0x000000fe0a00780c */
/* 0x000fda0003f04270 */
/*08c0*/ @P0 BRA 0xa80 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*08d0*/ ISETP.GE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fda0003f06270 */
/*08e0*/ @P0 BRA 0xac0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*08f0*/ ISETP.GE.AND P0, PT, R10, -0x18, PT ; /* 0xffffffe80a00780c */
/* 0x000fe40003f06270 */
/*0900*/ LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000007077812 */
/* 0x000fd600078ec0ff */
/*0910*/ @!P0 BRA 0xac0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0920*/ FFMA.RZ R3, R6, R8.reuse, R9.reuse ; /* 0x0000000806037223 */
/* 0x180fe2000000c009 */
/*0930*/ IADD3 R5, R10.reuse, 0x20, RZ ; /* 0x000000200a057810 */
/* 0x040fe40007ffe0ff */
/*0940*/ ISETP.NE.AND P2, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f45270 */
/*0950*/ LOP3.LUT R4, R3, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff03047812 */
/* 0x000fe200078ec0ff */
/*0960*/ FFMA.RP R3, R6, R8.reuse, R9.reuse ; /* 0x0000000806037223 */
/* 0x180fe20000008009 */
/*0970*/ ISETP.NE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f25270 */
/*0980*/ FFMA.RM R6, R6, R8, R9 ; /* 0x0000000806067223 */
/* 0x000fe20000004009 */
/*0990*/ LOP3.LUT R4, R4, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000004047812 */
/* 0x000fe200078efcff */
/*09a0*/ IMAD.MOV R8, RZ, RZ, -R10 ; /* 0x000000ffff087224 */
/* 0x000fc600078e0a0a */
/*09b0*/ SHF.L.U32 R5, R4, R5, RZ ; /* 0x0000000504057219 */
/* 0x000fe400000006ff */
/*09c0*/ FSETP.NEU.FTZ.AND P0, PT, R3, R6, PT ; /* 0x000000060300720b */
/* 0x000fe40003f1d000 */
/*09d0*/ SEL R3, R8, RZ, P2 ; /* 0x000000ff08037207 */
/* 0x000fe40001000000 */
/*09e0*/ ISETP.NE.AND P1, PT, R5, RZ, P1 ; /* 0x000000ff0500720c */
/* 0x000fe40000f25270 */
/*09f0*/ SHF.R.U32.HI R3, RZ, R3, R4 ; /* 0x00000003ff037219 */
/* 0x000fe40000011604 */
/*0a00*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*0a10*/ SHF.R.U32.HI R5, RZ, 0x1, R3 ; /* 0x00000001ff057819 */
/* 0x000fe40000011603 */
/*0a20*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*0a30*/ LOP3.LUT R4, R4, 0x1, R5, 0xf8, !PT ; /* 0x0000000104047812 */
/* 0x000fc800078ef805 */
/*0a40*/ LOP3.LUT R4, R4, R3, RZ, 0xc0, !PT ; /* 0x0000000304047212 */
/* 0x000fc800078ec0ff */
/*0a50*/ IADD3 R4, R5, R4, RZ ; /* 0x0000000405047210 */
/* 0x000fc80007ffe0ff */
/*0a60*/ LOP3.LUT R7, R4, R7, RZ, 0xfc, !PT ; /* 0x0000000704077212 */
/* 0x000fe200078efcff */
/*0a70*/ BRA 0xac0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0a80*/ LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000007077812 */
/* 0x000fc800078ec0ff */
/*0a90*/ LOP3.LUT R7, R7, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000007077812 */
/* 0x000fe200078efcff */
/*0aa0*/ BRA 0xac0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0ab0*/ IMAD R7, R4, 0x800000, R7 ; /* 0x0080000004077824 */
/* 0x000fe400078e0207 */
/*0ac0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0ad0*/ BRA 0xb60 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0ae0*/ LOP3.LUT R3, R4, 0x80000000, R3, 0x48, !PT ; /* 0x8000000004037812 */
/* 0x000fc800078e4803 */
/*0af0*/ LOP3.LUT R7, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003077812 */
/* 0x000fe200078efcff */
/*0b00*/ BRA 0xb60 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0b10*/ LOP3.LUT R7, R4, 0x80000000, R3, 0x48, !PT ; /* 0x8000000004077812 */
/* 0x000fe200078e4803 */
/*0b20*/ BRA 0xb60 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0b30*/ MUFU.RSQ R7, -QNAN ; /* 0xffc0000000077908 */
/* 0x000e220000001400 */
/*0b40*/ BRA 0xb60 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0b50*/ FADD.FTZ R7, R7, 5 ; /* 0x40a0000007077421 */
/* 0x000fe40000010000 */
/*0b60*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0b70*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0b80*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff47002007950 */
/* 0x000fea0003c3ffff */
/*0b90*/ BRA 0xb90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kernel(float *id, float *od, int w, int h, int depth)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int z = blockIdx.z * blockDim.z + threadIdx.z;
const int dataTotalSize = w * h * depth;
const int radius = 2;
const int filter_size = 2*radius + 1;
const int sW = 6; /* sW == 2 * filter_radius + blockDim.x (or same as 2 * filter_radius + blockDim.y) */
/* boarder do not concerned */
if(x >= w || y >= h || z >= depth)
return;
else
{
//global defined
int idx = z*w*h+y*w+x;
//3d grid(blocks) 2d block(threads)
int threadsPerBlock = blockDim.x * blockDim.y;
int blockId = blockIdx.x + blockIdx.y * gridDim.x
+ gridDim.x * gridDim.y * blockIdx.z;
int threadId = (blockId * threadsPerBlock)
+ (threadIdx.y * blockDim.x) + threadIdx.x;
int g_Idx = threadId;
//2d shared memory working
__shared__ unsigned char smem[sW][sW];
int s_Idx = threadIdx.x + (threadIdx.y * sW);
int s_IdxY = s_Idx / sW;
int s_IdxX = s_Idx % sW;
//Here: definition error, need edit, haven't finished yet.
//int g_IdxY = s_IdxY + (blockIdx.y * blockDim.y);
//int g_IdxX = s_IdxX + (blockIdx.x * blockDim.x);
//int g_Idx = g_IdxX + (g_IdxY * w);
//32 threads working together per warp
if(s_IdxY < sW && s_IdxX < sW) //Here: boarder concerned error, need edit
{
if(x >= 0 && y < w && y >= 0 && y < h && z >= 0 && z < depth ) //Here: boarder concerned error, need edit
smem[s_IdxY][s_IdxX] = id[g_Idx];
else
smem[s_IdxY][s_IdxX] = 0;
__syncthreads();
}
/*compute the sum using shared memory*/
float avg = 0.0;
for (int i = -radius; i <= radius; i++){
if(s_IdxY + i < 0 /*|| g_IdxY > h*/ ) //Here: boarder concerned error, need edit
avg += 0.0;
else
avg += smem[s_IdxY+i][s_IdxX];
}
/*register to global, by now thread*/
avg /= filter_size;
if(idx < dataTotalSize)
od[idx] = avg;
}
} | .file "tmpxft_000409e6_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6kernelPfS_iiiPfS_iii
.type _Z30__device_stub__Z6kernelPfS_iiiPfS_iii, @function
_Z30__device_stub__Z6kernelPfS_iiiPfS_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6kernelPfS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z6kernelPfS_iiiPfS_iii, .-_Z30__device_stub__Z6kernelPfS_iiiPfS_iii
.globl _Z6kernelPfS_iii
.type _Z6kernelPfS_iii, @function
_Z6kernelPfS_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6kernelPfS_iiiPfS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6kernelPfS_iii, .-_Z6kernelPfS_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kernelPfS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPfS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kernel(float *id, float *od, int w, int h, int depth)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int z = blockIdx.z * blockDim.z + threadIdx.z;
const int dataTotalSize = w * h * depth;
const int radius = 2;
const int filter_size = 2*radius + 1;
const int sW = 6; /* sW == 2 * filter_radius + blockDim.x (or same as 2 * filter_radius + blockDim.y) */
/* boarder do not concerned */
if(x >= w || y >= h || z >= depth)
return;
else
{
//global defined
int idx = z*w*h+y*w+x;
//3d grid(blocks) 2d block(threads)
int threadsPerBlock = blockDim.x * blockDim.y;
int blockId = blockIdx.x + blockIdx.y * gridDim.x
+ gridDim.x * gridDim.y * blockIdx.z;
int threadId = (blockId * threadsPerBlock)
+ (threadIdx.y * blockDim.x) + threadIdx.x;
int g_Idx = threadId;
//2d shared memory working
__shared__ unsigned char smem[sW][sW];
int s_Idx = threadIdx.x + (threadIdx.y * sW);
int s_IdxY = s_Idx / sW;
int s_IdxX = s_Idx % sW;
//Here: definition error, need edit, haven't finished yet.
//int g_IdxY = s_IdxY + (blockIdx.y * blockDim.y);
//int g_IdxX = s_IdxX + (blockIdx.x * blockDim.x);
//int g_Idx = g_IdxX + (g_IdxY * w);
//32 threads working together per warp
if(s_IdxY < sW && s_IdxX < sW) //Here: boarder concerned error, need edit
{
if(x >= 0 && y < w && y >= 0 && y < h && z >= 0 && z < depth ) //Here: boarder concerned error, need edit
smem[s_IdxY][s_IdxX] = id[g_Idx];
else
smem[s_IdxY][s_IdxX] = 0;
__syncthreads();
}
/*compute the sum using shared memory*/
float avg = 0.0;
for (int i = -radius; i <= radius; i++){
if(s_IdxY + i < 0 /*|| g_IdxY > h*/ ) //Here: boarder concerned error, need edit
avg += 0.0;
else
avg += smem[s_IdxY+i][s_IdxX];
}
/*register to global, by now thread*/
avg /= filter_size;
if(idx < dataTotalSize)
od[idx] = avg;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel(float *id, float *od, int w, int h, int depth)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int z = blockIdx.z * blockDim.z + threadIdx.z;
const int dataTotalSize = w * h * depth;
const int radius = 2;
const int filter_size = 2*radius + 1;
const int sW = 6; /* sW == 2 * filter_radius + blockDim.x (or same as 2 * filter_radius + blockDim.y) */
/* boarder do not concerned */
if(x >= w || y >= h || z >= depth)
return;
else
{
//global defined
int idx = z*w*h+y*w+x;
//3d grid(blocks) 2d block(threads)
int threadsPerBlock = blockDim.x * blockDim.y;
int blockId = blockIdx.x + blockIdx.y * gridDim.x
+ gridDim.x * gridDim.y * blockIdx.z;
int threadId = (blockId * threadsPerBlock)
+ (threadIdx.y * blockDim.x) + threadIdx.x;
int g_Idx = threadId;
//2d shared memory working
__shared__ unsigned char smem[sW][sW];
int s_Idx = threadIdx.x + (threadIdx.y * sW);
int s_IdxY = s_Idx / sW;
int s_IdxX = s_Idx % sW;
//Here: definition error, need edit, haven't finished yet.
//int g_IdxY = s_IdxY + (blockIdx.y * blockDim.y);
//int g_IdxX = s_IdxX + (blockIdx.x * blockDim.x);
//int g_Idx = g_IdxX + (g_IdxY * w);
//32 threads working together per warp
if(s_IdxY < sW && s_IdxX < sW) //Here: boarder concerned error, need edit
{
if(x >= 0 && y < w && y >= 0 && y < h && z >= 0 && z < depth ) //Here: boarder concerned error, need edit
smem[s_IdxY][s_IdxX] = id[g_Idx];
else
smem[s_IdxY][s_IdxX] = 0;
__syncthreads();
}
/*compute the sum using shared memory*/
float avg = 0.0;
for (int i = -radius; i <= radius; i++){
if(s_IdxY + i < 0 /*|| g_IdxY > h*/ ) //Here: boarder concerned error, need edit
avg += 0.0;
else
avg += smem[s_IdxY+i][s_IdxX];
}
/*register to global, by now thread*/
avg /= filter_size;
if(idx < dataTotalSize)
od[idx] = avg;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel(float *id, float *od, int w, int h, int depth)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int z = blockIdx.z * blockDim.z + threadIdx.z;
const int dataTotalSize = w * h * depth;
const int radius = 2;
const int filter_size = 2*radius + 1;
const int sW = 6; /* sW == 2 * filter_radius + blockDim.x (or same as 2 * filter_radius + blockDim.y) */
/* boarder do not concerned */
if(x >= w || y >= h || z >= depth)
return;
else
{
//global defined
int idx = z*w*h+y*w+x;
//3d grid(blocks) 2d block(threads)
int threadsPerBlock = blockDim.x * blockDim.y;
int blockId = blockIdx.x + blockIdx.y * gridDim.x
+ gridDim.x * gridDim.y * blockIdx.z;
int threadId = (blockId * threadsPerBlock)
+ (threadIdx.y * blockDim.x) + threadIdx.x;
int g_Idx = threadId;
//2d shared memory working
__shared__ unsigned char smem[sW][sW];
int s_Idx = threadIdx.x + (threadIdx.y * sW);
int s_IdxY = s_Idx / sW;
int s_IdxX = s_Idx % sW;
//Here: definition error, need edit, haven't finished yet.
//int g_IdxY = s_IdxY + (blockIdx.y * blockDim.y);
//int g_IdxX = s_IdxX + (blockIdx.x * blockDim.x);
//int g_Idx = g_IdxX + (g_IdxY * w);
//32 threads working together per warp
if(s_IdxY < sW && s_IdxX < sW) //Here: boarder concerned error, need edit
{
if(x >= 0 && y < w && y >= 0 && y < h && z >= 0 && z < depth ) //Here: boarder concerned error, need edit
smem[s_IdxY][s_IdxX] = id[g_Idx];
else
smem[s_IdxY][s_IdxX] = 0;
__syncthreads();
}
/*compute the sum using shared memory*/
float avg = 0.0;
for (int i = -radius; i <= radius; i++){
if(s_IdxY + i < 0 /*|| g_IdxY > h*/ ) //Here: boarder concerned error, need edit
avg += 0.0;
else
avg += smem[s_IdxY+i][s_IdxX];
}
/*register to global, by now thread*/
avg /= filter_size;
if(idx < dataTotalSize)
od[idx] = avg;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPfS_iii
.globl _Z6kernelPfS_iii
.p2align 8
.type _Z6kernelPfS_iii,@function
_Z6kernelPfS_iii:
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b32 s8, s[0:1], 0x18
v_and_b32_e32 v4, 0x3ff, v0
v_bfe_u32 v5, v0, 10, 10
v_bfe_u32 v6, v0, 20, 10
s_add_u32 s6, s0, 32
s_addc_u32 s7, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s2, 0xffff
s_lshr_b32 s10, s2, 16
v_mad_u64_u32 v[0:1], null, s13, s9, v[4:5]
s_and_b32 s2, s3, 0xffff
v_mad_u64_u32 v[1:2], null, s14, s10, v[5:6]
v_mad_u64_u32 v[2:3], null, s15, s2, v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e32 vcc_lo, s4, v0
v_cmp_gt_i32_e64 s2, s5, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e64 s3, s8, v2
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_13
v_mad_u32_u24 v3, v5, 6, v4
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_mul_hi_u32 v6, v3, 0xaaaaaaab
v_cmpx_gt_u32_e32 36, v3
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v7, 0
s_mov_b32 s11, exec_lo
v_cmpx_lt_i32_e32 -1, v0
s_cbranch_execz .LBB0_6
v_or_b32_e32 v7, v2, v1
v_cmp_gt_i32_e32 vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_lt_i32_e64 s2, -1, v7
v_mov_b32_e32 v7, 0
s_and_b32 s12, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s12
s_cbranch_execz .LBB0_5
s_load_b64 s[6:7], s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s7, s7, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s14
s_mul_i32 s6, s7, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s6, s6, s13
v_mad_u64_u32 v[7:8], null, s6, s10, v[5:6]
s_load_b64 s[6:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[8:9], null, v7, s9, v[4:5]
v_ashrrev_i32_e32 v9, 31, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[8:9]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s6, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v7, v4
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s11
ds_store_b8 v3, v7
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v4, 2, v6
s_mov_b32 s2, -12
v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v5, -2, v4
s_branch .LBB0_9
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_dual_add_f32 v4, v4, v6 :: v_dual_add_nc_u32 v5, 1, v5
s_add_i32 s2, s2, 6
s_cmp_eq_u32 s2, 18
s_cbranch_scc1 .LBB0_11
.LBB0_9:
v_mov_b32_e32 v6, 0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_lt_i32_e32 -1, v5
s_cbranch_execz .LBB0_8
v_add_nc_u32_e32 v6, s2, v3
ds_load_u8 v6, v6
s_waitcnt lgkmcnt(0)
v_cvt_f32_ubyte0_e32 v6, v6
s_branch .LBB0_8
.LBB0_11:
v_mad_u64_u32 v[5:6], null, v2, s5, v[1:2]
s_mul_i32 s2, s5, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s2, s2, s8
v_mad_u64_u32 v[1:2], null, v5, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_13
v_div_scale_f32 v0, null, 0x40a00000, 0x40a00000, v4
v_div_scale_f32 v5, vcc_lo, v4, 0x40a00000, v4
s_load_b64 s[0:1], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v3, v0
s_waitcnt_depctr 0xfff
v_fma_f32 v2, -v0, v3, 1.0
v_fmac_f32_e32 v3, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v5, v3
v_fma_f32 v2, -v0, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v6, v2, v3
v_ashrrev_i32_e32 v2, 31, v1
v_fma_f32 v0, -v0, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fmas_f32 v3, v0, v3, v6
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fixup_f32 v2, v3, 0x40a00000, v4
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPfS_iii
.amdhsa_group_segment_fixed_size 36
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPfS_iii, .Lfunc_end0-_Z6kernelPfS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 36
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPfS_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPfS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel(float *id, float *od, int w, int h, int depth)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int z = blockIdx.z * blockDim.z + threadIdx.z;
const int dataTotalSize = w * h * depth;
const int radius = 2;
const int filter_size = 2*radius + 1;
const int sW = 6; /* sW == 2 * filter_radius + blockDim.x (or same as 2 * filter_radius + blockDim.y) */
/* boarder do not concerned */
if(x >= w || y >= h || z >= depth)
return;
else
{
//global defined
int idx = z*w*h+y*w+x;
//3d grid(blocks) 2d block(threads)
int threadsPerBlock = blockDim.x * blockDim.y;
int blockId = blockIdx.x + blockIdx.y * gridDim.x
+ gridDim.x * gridDim.y * blockIdx.z;
int threadId = (blockId * threadsPerBlock)
+ (threadIdx.y * blockDim.x) + threadIdx.x;
int g_Idx = threadId;
//2d shared memory working
__shared__ unsigned char smem[sW][sW];
int s_Idx = threadIdx.x + (threadIdx.y * sW);
int s_IdxY = s_Idx / sW;
int s_IdxX = s_Idx % sW;
//Here: definition error, need edit, haven't finished yet.
//int g_IdxY = s_IdxY + (blockIdx.y * blockDim.y);
//int g_IdxX = s_IdxX + (blockIdx.x * blockDim.x);
//int g_Idx = g_IdxX + (g_IdxY * w);
//32 threads working together per warp
if(s_IdxY < sW && s_IdxX < sW) //Here: boarder concerned error, need edit
{
if(x >= 0 && y < w && y >= 0 && y < h && z >= 0 && z < depth ) //Here: boarder concerned error, need edit
smem[s_IdxY][s_IdxX] = id[g_Idx];
else
smem[s_IdxY][s_IdxX] = 0;
__syncthreads();
}
/*compute the sum using shared memory*/
float avg = 0.0;
for (int i = -radius; i <= radius; i++){
if(s_IdxY + i < 0 /*|| g_IdxY > h*/ ) //Here: boarder concerned error, need edit
avg += 0.0;
else
avg += smem[s_IdxY+i][s_IdxX];
}
/*register to global, by now thread*/
avg /= filter_size;
if(idx < dataTotalSize)
od[idx] = avg;
}
} | .text
.file "kernel.hip"
.globl _Z21__device_stub__kernelPfS_iii # -- Begin function _Z21__device_stub__kernelPfS_iii
.p2align 4, 0x90
.type _Z21__device_stub__kernelPfS_iii,@function
_Z21__device_stub__kernelPfS_iii: # @_Z21__device_stub__kernelPfS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelPfS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPfS_iii, .Lfunc_end0-_Z21__device_stub__kernelPfS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPfS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPfS_iii,@object # @_Z6kernelPfS_iii
.section .rodata,"a",@progbits
.globl _Z6kernelPfS_iii
.p2align 3, 0x0
_Z6kernelPfS_iii:
.quad _Z21__device_stub__kernelPfS_iii
.size _Z6kernelPfS_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelPfS_iii"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPfS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPfS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kernelPfS_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R11, SR_TID.Y ; /* 0x00000000000b7919 */
/* 0x000e280000002200 */
/*0030*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e680000002500 */
/*0040*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e680000002100 */
/*0050*/ S2R R5, SR_CTAID.Z ; /* 0x0000000000057919 */
/* 0x000ea80000002700 */
/*0060*/ S2R R4, SR_TID.Z ; /* 0x0000000000047919 */
/* 0x000ea20000002300 */
/*0070*/ IMAD R3, R0, c[0x0][0x4], R11 ; /* 0x0000010000037a24 */
/* 0x001fca00078e020b */
/*0080*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */
/* 0x000fe20003f06270 */
/*0090*/ IMAD R2, R9, c[0x0][0x0], R6 ; /* 0x0000000009027a24 */
/* 0x002fca00078e0206 */
/*00a0*/ ISETP.GE.OR P0, PT, R2, c[0x0][0x170], P0 ; /* 0x00005c0002007a0c */
/* 0x000fe20000706670 */
/*00b0*/ IMAD R4, R5, c[0x0][0x8], R4 ; /* 0x0000020005047a24 */
/* 0x004fca00078e0204 */
/*00c0*/ ISETP.GE.OR P0, PT, R4, c[0x0][0x178], P0 ; /* 0x00005e0004007a0c */
/* 0x000fda0000706670 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ IMAD R7, R11, 0x6, R6 ; /* 0x000000060b077824 */
/* 0x000fe200078e0206 */
/*00f0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0100*/ IMAD R0, R5, c[0x0][0x10], R0 ; /* 0x0000040005007a24 */
/* 0x000fe400078e0200 */
/*0110*/ IMAD.HI R5, R7.reuse, 0x2aaaaaab, RZ ; /* 0x2aaaaaab07057827 */
/* 0x040fe200078e02ff */
/*0120*/ ISETP.GT.AND P0, PT, R7, 0x23, PT ; /* 0x000000230700780c */
/* 0x000fc60003f04270 */
/*0130*/ IMAD R0, R0, c[0x0][0xc], R9 ; /* 0x0000030000007a24 */
/* 0x000fe200078e0209 */
/*0140*/ LEA.HI R8, R5, R5, RZ, 0x1 ; /* 0x0000000505087211 */
/* 0x000fe200078f08ff */
/*0150*/ IMAD R5, R4, c[0x0][0x174], R3 ; /* 0x00005d0004057a24 */
/* 0x000fe400078e0203 */
/*0160*/ IMAD R0, R0, c[0x0][0x4], R11 ; /* 0x0000010000007a24 */
/* 0x000fe400078e020b */
/*0170*/ IMAD R9, R8, -0x6, R7 ; /* 0xfffffffa08097824 */
/* 0x000fe400078e0207 */
/*0180*/ IMAD R6, R0, c[0x0][0x0], R6 ; /* 0x0000000000067a24 */
/* 0x000fe400078e0206 */
/*0190*/ IMAD R9, R8, 0x6, R9 ; /* 0x0000000608097824 */
/* 0x000fc400078e0209 */
/*01a0*/ IMAD R0, R5, c[0x0][0x170], R2 ; /* 0x00005c0005007a24 */
/* 0x000fe200078e0202 */
/*01b0*/ @P0 BRA 0x280 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*01c0*/ LOP3.LUT R2, R4, R2, R3, 0xfe, !PT ; /* 0x0000000204027212 */
/* 0x000fe400078efe03 */
/*01d0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fc80003f06270 */
/*01e0*/ ISETP.GT.AND P0, PT, R2, -0x1, !P0 ; /* 0xffffffff0200780c */
/* 0x000fda0004704270 */
/*01f0*/ @!P0 STS.U8 [R9], RZ ; /* 0x000000ff09008388 */
/* 0x0001e20000000000 */
/*0200*/ @!P0 BRA 0x260 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0210*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0220*/ IMAD.WIDE R2, R6, R3, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fcc00078e0203 */
/*0230*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea4000c1e1900 */
/*0240*/ F2I.U32.TRUNC.NTZ R4, R2 ; /* 0x0000000200047305 */
/* 0x004e64000020f000 */
/*0250*/ STS.U8 [R9], R4 ; /* 0x0000000409007388 */
/* 0x0023e40000000000 */
/*0260*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0270*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0280*/ ISETP.GE.AND P3, PT, R7.reuse, 0xc, PT ; /* 0x0000000c0700780c */
/* 0x040fe20003f66270 */
/*0290*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe200078e00ff */
/*02a0*/ ISETP.GE.AND P4, PT, R7.reuse, 0x6, PT ; /* 0x000000060700780c */
/* 0x040fe20003f86270 */
/*02b0*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000a00 */
/*02c0*/ ISETP.GE.AND P2, PT, R7.reuse, -0x5, PT ; /* 0xfffffffb0700780c */
/* 0x040fe20003f46270 */
/*02d0*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*02e0*/ ISETP.GE.AND P0, PT, R7, -0xb, PT ; /* 0xfffffff50700780c */
/* 0x000fc40003f06270 */
/*02f0*/ ISETP.GE.AND P1, PT, R7, -0x11, PT ; /* 0xffffffef0700780c */
/* 0x000fe20003f26270 */
/*0300*/ ULDC UR5, c[0x0][0x178] ; /* 0x00005e0000057ab9 */
/* 0x000fe40000000800 */
/*0310*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fe4000f8e023f */
/*0320*/ @P3 LDS.U8 R3, [R9+-0xc] ; /* 0xfffff40009033984 */
/* 0x000ea80000000000 */
/*0330*/ @P4 LDS.U8 R5, [R9+-0x6] ; /* 0xfffffa0009054984 */
/* 0x000ee80000000000 */
/*0340*/ @P2 LDS.U8 R6, [R9] ; /* 0x0000000009062984 */
/* 0x000f280000000000 */
/*0350*/ @P0 LDS.U8 R8, [R9+0x6] ; /* 0x0000060009080984 */
/* 0x000f680000000000 */
/*0360*/ @P1 LDS.U8 R10, [R9+0xc] ; /* 0x00000c00090a1984 */
/* 0x000e220000000000 */
/*0370*/ @P3 I2F.U16 R2, R3 ; /* 0x0000000300023306 */
/* 0x004fe20000101000 */
/*0380*/ ISETP.GE.AND P3, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fce000bf66270 */
/*0390*/ @P4 I2F.U16 R5, R5 ; /* 0x0000000500054306 */
/* 0x008eb00000101000 */
/*03a0*/ @P2 I2F.U16 R7, R6 ; /* 0x0000000600072306 */
/* 0x010ef00000101000 */
/*03b0*/ @P0 I2F.U16 R11, R8 ; /* 0x00000008000b0306 */
/* 0x020f220000101000 */
/*03c0*/ @P4 FADD R4, R5, R2 ; /* 0x0000000205044221 */
/* 0x006fc40000000000 */
/*03d0*/ @!P4 FADD R4, RZ, R2 ; /* 0x00000002ff04c221 */
/* 0x000fca0000000000 */
/*03e0*/ @P1 I2F.U16 R10, R10 ; /* 0x0000000a000a1306 */
/* 0x001e220000101000 */
/*03f0*/ @P2 FADD R2, R7, R4.reuse ; /* 0x0000000407022221 */
/* 0x108fe40000000000 */
/*0400*/ @!P2 FADD R2, RZ, R4 ; /* 0x00000004ff02a221 */
/* 0x000fc80000000000 */
/*0410*/ @P0 FADD R3, R11, R2 ; /* 0x000000020b030221 */
/* 0x010fe20000000000 */
/*0420*/ @P3 EXIT ; /* 0x000000000000394d */
/* 0x000fec0003800000 */
/*0430*/ @!P0 FADD R3, RZ, R2 ; /* 0x00000002ff038221 */
/* 0x000fe20000000000 */
/*0440*/ BSSY B1, 0x550 ; /* 0x0000010000017945 */
/* 0x000fe20003800000 */
/*0450*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3e4ccccd ; /* 0x3e4ccccdff057424 */
/* 0x000fe400078e00ff */
/*0460*/ @P1 FADD R2, R10, R3.reuse ; /* 0x000000030a021221 */
/* 0x101fe40000000000 */
/*0470*/ @!P1 FADD R2, RZ, R3 ; /* 0x00000003ff029221 */
/* 0x000fe40000000000 */
/*0480*/ IMAD.MOV.U32 R4, RZ, RZ, 0x40a00000 ; /* 0x40a00000ff047424 */
/* 0x000fe400078e00ff */
/*0490*/ FCHK P0, R2, 5 ; /* 0x40a0000002007902 */
/* 0x000e240000000000 */
/*04a0*/ FFMA R4, R5, -R4, 1 ; /* 0x3f80000005047423 */
/* 0x000fc80000000804 */
/*04b0*/ FFMA R3, R4, R5, 0.20000000298023223877 ; /* 0x3e4ccccd04037423 */
/* 0x000fc80000000005 */
/*04c0*/ FFMA R4, R3, R2, RZ ; /* 0x0000000203047223 */
/* 0x000fc800000000ff */
/*04d0*/ FFMA R5, R4, -5, R2 ; /* 0xc0a0000004057823 */
/* 0x000fc80000000002 */
/*04e0*/ FFMA R5, R3, R5, R4 ; /* 0x0000000503057223 */
/* 0x000fe20000000004 */
/*04f0*/ @!P0 BRA 0x540 ; /* 0x0000004000008947 */
/* 0x001fea0003800000 */
/*0500*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*0510*/ MOV R2, 0x530 ; /* 0x0000053000027802 */
/* 0x000fe40000000f00 */
/*0520*/ CALL.REL.NOINC 0x590 ; /* 0x0000006000007944 */
/* 0x000fea0003c00000 */
/*0530*/ MOV R5, R7 ; /* 0x0000000700057202 */
/* 0x001fe40000000f00 */
/*0540*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0550*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0560*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0203 */
/*0570*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101906 */
/*0580*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0590*/ SHF.R.U32.HI R3, RZ, 0x17, R7.reuse ; /* 0x00000017ff037819 */
/* 0x100fe20000011607 */
/*05a0*/ BSSY B0, 0xb70 ; /* 0x000005c000007945 */
/* 0x000fe20003800000 */
/*05b0*/ BSSY B2, 0x760 ; /* 0x000001a000027945 */
/* 0x000fe40003800000 */
/*05c0*/ LOP3.LUT R5, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff03057812 */
/* 0x000fe200078ec0ff */
/*05d0*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fc600078e0007 */
/*05e0*/ IADD3 R6, R5, -0x1, RZ ; /* 0xffffffff05067810 */
/* 0x000fc80007ffe0ff */
/*05f0*/ ISETP.GT.U32.OR P0, PT, R6, 0xfd, !PT ; /* 0x000000fd0600780c */
/* 0x000fda0007f04470 */
/*0600*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff048224 */
/* 0x000fe200078e00ff */
/*0610*/ @!P0 BRA 0x750 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0620*/ FSETP.GTU.FTZ.AND P0, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fda0003f1c200 */
/*0630*/ @P0 BREAK B2 ; /* 0x0000000000020942 */
/* 0x000fe20003800000 */
/*0640*/ @P0 BRA 0xb50 ; /* 0x0000050000000947 */
/* 0x000fea0003800000 */
/*0650*/ IMAD.MOV.U32 R4, RZ, RZ, 0x40a00000 ; /* 0x40a00000ff047424 */
/* 0x000fca00078e00ff */
/*0660*/ LOP3.LUT P0, RZ, R4, 0x7fffffff, R3, 0xc8, !PT ; /* 0x7fffffff04ff7812 */
/* 0x000fda000780c803 */
/*0670*/ @!P0 BREAK B2 ; /* 0x0000000000028942 */
/* 0x000fe20003800000 */
/*0680*/ @!P0 BRA 0xb30 ; /* 0x000004a000008947 */
/* 0x000fea0003800000 */
/*0690*/ LOP3.LUT P0, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff03ff7812 */
/* 0x000fda000780c0ff */
/*06a0*/ @!P0 BREAK B2 ; /* 0x0000000000028942 */
/* 0x000fe20003800000 */
/*06b0*/ @!P0 BRA 0xb10 ; /* 0x0000045000008947 */
/* 0x000fea0003800000 */
/*06c0*/ FSETP.NEU.FTZ.AND P1, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fe40003f3d200 */
/*06d0*/ LOP3.LUT P0, RZ, R4, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff04ff7812 */
/* 0x000fc8000780c0ff */
/*06e0*/ PLOP3.LUT P0, PT, P1, P0, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f00572 */
/*06f0*/ @P0 BREAK B2 ; /* 0x0000000000020942 */
/* 0x000fe20003800000 */
/*0700*/ @P0 BRA 0xae0 ; /* 0x000003d000000947 */
/* 0x000fea0003800000 */
/*0710*/ ISETP.GE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f06270 */
/*0720*/ @P0 MOV R4, RZ ; /* 0x000000ff00040202 */
/* 0x000fe20000000f00 */
/*0730*/ @!P0 FFMA R3, R7, 1.84467440737095516160e+19, RZ ; /* 0x5f80000007038823 */
/* 0x000fe400000000ff */
/*0740*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, -0x40 ; /* 0xffffffc0ff048424 */
/* 0x000fe400078e00ff */
/*0750*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0760*/ UMOV UR4, 0x40a00000 ; /* 0x40a0000000047882 */
/* 0x000fe20000000000 */
/*0770*/ IADD3 R5, R5, -0x7f, RZ ; /* 0xffffff8105057810 */
/* 0x000fe20007ffe0ff */
/*0780*/ UIADD3 UR4, UR4, -0x1000000, URZ ; /* 0xff00000004047890 */
/* 0x000fe2000fffe03f */
/*0790*/ BSSY B2, 0xad0 ; /* 0x0000033000027945 */
/* 0x000fe40003800000 */
/*07a0*/ IADD3 R4, R4, -0x2, R5 ; /* 0xfffffffe04047810 */
/* 0x000fe20007ffe005 */
/*07b0*/ IMAD R3, R5, -0x800000, R3 ; /* 0xff80000005037824 */
/* 0x000fe400078e0203 */
/*07c0*/ FADD.FTZ R8, -RZ, -UR4 ; /* 0x80000004ff087e21 */
/* 0x000fc60008010100 */
/*07d0*/ MUFU.RCP R6, UR4 ; /* 0x0000000400067d08 */
/* 0x000e240008001000 */
/*07e0*/ FFMA R7, R6, R8, 1 ; /* 0x3f80000006077423 */
/* 0x001fc80000000008 */
/*07f0*/ FFMA R6, R6, R7, R6 ; /* 0x0000000706067223 */
/* 0x000fc80000000006 */
/*0800*/ FFMA R7, R3, R6, RZ ; /* 0x0000000603077223 */
/* 0x000fc800000000ff */
/*0810*/ FFMA R9, R8, R7, R3 ; /* 0x0000000708097223 */
/* 0x000fc80000000003 */
/*0820*/ FFMA R9, R6, R9, R7 ; /* 0x0000000906097223 */
/* 0x000fc80000000007 */
/*0830*/ FFMA R8, R8, R9, R3 ; /* 0x0000000908087223 */
/* 0x000fc80000000003 */
/*0840*/ FFMA R7, R6, R8, R9 ; /* 0x0000000806077223 */
/* 0x000fca0000000009 */
/*0850*/ SHF.R.U32.HI R3, RZ, 0x17, R7 ; /* 0x00000017ff037819 */
/* 0x000fc80000011607 */
/*0860*/ LOP3.LUT R3, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff03037812 */
/* 0x000fca00078ec0ff */
/*0870*/ IMAD.IADD R10, R3, 0x1, R4 ; /* 0x00000001030a7824 */
/* 0x000fca00078e0204 */
/*0880*/ IADD3 R3, R10, -0x1, RZ ; /* 0xffffffff0a037810 */
/* 0x000fc80007ffe0ff */
/*0890*/ ISETP.GE.U32.AND P0, PT, R3, 0xfe, PT ; /* 0x000000fe0300780c */
/* 0x000fda0003f06070 */
/*08a0*/ @!P0 BRA 0xab0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*08b0*/ ISETP.GT.AND P0, PT, R10, 0xfe, PT ; /* 0x000000fe0a00780c */
/* 0x000fda0003f04270 */
/*08c0*/ @P0 BRA 0xa80 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*08d0*/ ISETP.GE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fda0003f06270 */
/*08e0*/ @P0 BRA 0xac0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*08f0*/ ISETP.GE.AND P0, PT, R10, -0x18, PT ; /* 0xffffffe80a00780c */
/* 0x000fe40003f06270 */
/*0900*/ LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000007077812 */
/* 0x000fd600078ec0ff */
/*0910*/ @!P0 BRA 0xac0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0920*/ FFMA.RZ R3, R6, R8.reuse, R9.reuse ; /* 0x0000000806037223 */
/* 0x180fe2000000c009 */
/*0930*/ IADD3 R5, R10.reuse, 0x20, RZ ; /* 0x000000200a057810 */
/* 0x040fe40007ffe0ff */
/*0940*/ ISETP.NE.AND P2, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f45270 */
/*0950*/ LOP3.LUT R4, R3, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff03047812 */
/* 0x000fe200078ec0ff */
/*0960*/ FFMA.RP R3, R6, R8.reuse, R9.reuse ; /* 0x0000000806037223 */
/* 0x180fe20000008009 */
/*0970*/ ISETP.NE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f25270 */
/*0980*/ FFMA.RM R6, R6, R8, R9 ; /* 0x0000000806067223 */
/* 0x000fe20000004009 */
/*0990*/ LOP3.LUT R4, R4, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000004047812 */
/* 0x000fe200078efcff */
/*09a0*/ IMAD.MOV R8, RZ, RZ, -R10 ; /* 0x000000ffff087224 */
/* 0x000fc600078e0a0a */
/*09b0*/ SHF.L.U32 R5, R4, R5, RZ ; /* 0x0000000504057219 */
/* 0x000fe400000006ff */
/*09c0*/ FSETP.NEU.FTZ.AND P0, PT, R3, R6, PT ; /* 0x000000060300720b */
/* 0x000fe40003f1d000 */
/*09d0*/ SEL R3, R8, RZ, P2 ; /* 0x000000ff08037207 */
/* 0x000fe40001000000 */
/*09e0*/ ISETP.NE.AND P1, PT, R5, RZ, P1 ; /* 0x000000ff0500720c */
/* 0x000fe40000f25270 */
/*09f0*/ SHF.R.U32.HI R3, RZ, R3, R4 ; /* 0x00000003ff037219 */
/* 0x000fe40000011604 */
/*0a00*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*0a10*/ SHF.R.U32.HI R5, RZ, 0x1, R3 ; /* 0x00000001ff057819 */
/* 0x000fe40000011603 */
/*0a20*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*0a30*/ LOP3.LUT R4, R4, 0x1, R5, 0xf8, !PT ; /* 0x0000000104047812 */
/* 0x000fc800078ef805 */
/*0a40*/ LOP3.LUT R4, R4, R3, RZ, 0xc0, !PT ; /* 0x0000000304047212 */
/* 0x000fc800078ec0ff */
/*0a50*/ IADD3 R4, R5, R4, RZ ; /* 0x0000000405047210 */
/* 0x000fc80007ffe0ff */
/*0a60*/ LOP3.LUT R7, R4, R7, RZ, 0xfc, !PT ; /* 0x0000000704077212 */
/* 0x000fe200078efcff */
/*0a70*/ BRA 0xac0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0a80*/ LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000007077812 */
/* 0x000fc800078ec0ff */
/*0a90*/ LOP3.LUT R7, R7, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000007077812 */
/* 0x000fe200078efcff */
/*0aa0*/ BRA 0xac0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0ab0*/ IMAD R7, R4, 0x800000, R7 ; /* 0x0080000004077824 */
/* 0x000fe400078e0207 */
/*0ac0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0ad0*/ BRA 0xb60 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0ae0*/ LOP3.LUT R3, R4, 0x80000000, R3, 0x48, !PT ; /* 0x8000000004037812 */
/* 0x000fc800078e4803 */
/*0af0*/ LOP3.LUT R7, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003077812 */
/* 0x000fe200078efcff */
/*0b00*/ BRA 0xb60 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0b10*/ LOP3.LUT R7, R4, 0x80000000, R3, 0x48, !PT ; /* 0x8000000004077812 */
/* 0x000fe200078e4803 */
/*0b20*/ BRA 0xb60 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0b30*/ MUFU.RSQ R7, -QNAN ; /* 0xffc0000000077908 */
/* 0x000e220000001400 */
/*0b40*/ BRA 0xb60 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0b50*/ FADD.FTZ R7, R7, 5 ; /* 0x40a0000007077421 */
/* 0x000fe40000010000 */
/*0b60*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0b70*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0b80*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff47002007950 */
/* 0x000fea0003c3ffff */
/*0b90*/ BRA 0xb90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPfS_iii
.globl _Z6kernelPfS_iii
.p2align 8
.type _Z6kernelPfS_iii,@function
_Z6kernelPfS_iii:
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b32 s8, s[0:1], 0x18
v_and_b32_e32 v4, 0x3ff, v0
v_bfe_u32 v5, v0, 10, 10
v_bfe_u32 v6, v0, 20, 10
s_add_u32 s6, s0, 32
s_addc_u32 s7, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s2, 0xffff
s_lshr_b32 s10, s2, 16
v_mad_u64_u32 v[0:1], null, s13, s9, v[4:5]
s_and_b32 s2, s3, 0xffff
v_mad_u64_u32 v[1:2], null, s14, s10, v[5:6]
v_mad_u64_u32 v[2:3], null, s15, s2, v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e32 vcc_lo, s4, v0
v_cmp_gt_i32_e64 s2, s5, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e64 s3, s8, v2
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_13
v_mad_u32_u24 v3, v5, 6, v4
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_mul_hi_u32 v6, v3, 0xaaaaaaab
v_cmpx_gt_u32_e32 36, v3
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v7, 0
s_mov_b32 s11, exec_lo
v_cmpx_lt_i32_e32 -1, v0
s_cbranch_execz .LBB0_6
v_or_b32_e32 v7, v2, v1
v_cmp_gt_i32_e32 vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_lt_i32_e64 s2, -1, v7
v_mov_b32_e32 v7, 0
s_and_b32 s12, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s12
s_cbranch_execz .LBB0_5
s_load_b64 s[6:7], s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s7, s7, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s14
s_mul_i32 s6, s7, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s6, s6, s13
v_mad_u64_u32 v[7:8], null, s6, s10, v[5:6]
s_load_b64 s[6:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[8:9], null, v7, s9, v[4:5]
v_ashrrev_i32_e32 v9, 31, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[8:9]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s6, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v7, v4
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s11
ds_store_b8 v3, v7
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v4, 2, v6
s_mov_b32 s2, -12
v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v5, -2, v4
s_branch .LBB0_9
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_dual_add_f32 v4, v4, v6 :: v_dual_add_nc_u32 v5, 1, v5
s_add_i32 s2, s2, 6
s_cmp_eq_u32 s2, 18
s_cbranch_scc1 .LBB0_11
.LBB0_9:
v_mov_b32_e32 v6, 0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_lt_i32_e32 -1, v5
s_cbranch_execz .LBB0_8
v_add_nc_u32_e32 v6, s2, v3
ds_load_u8 v6, v6
s_waitcnt lgkmcnt(0)
v_cvt_f32_ubyte0_e32 v6, v6
s_branch .LBB0_8
.LBB0_11:
v_mad_u64_u32 v[5:6], null, v2, s5, v[1:2]
s_mul_i32 s2, s5, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s2, s2, s8
v_mad_u64_u32 v[1:2], null, v5, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_13
v_div_scale_f32 v0, null, 0x40a00000, 0x40a00000, v4
v_div_scale_f32 v5, vcc_lo, v4, 0x40a00000, v4
s_load_b64 s[0:1], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v3, v0
s_waitcnt_depctr 0xfff
v_fma_f32 v2, -v0, v3, 1.0
v_fmac_f32_e32 v3, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v5, v3
v_fma_f32 v2, -v0, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v6, v2, v3
v_ashrrev_i32_e32 v2, 31, v1
v_fma_f32 v0, -v0, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fmas_f32 v3, v0, v3, v6
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fixup_f32 v2, v3, 0x40a00000, v4
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPfS_iii
.amdhsa_group_segment_fixed_size 36
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPfS_iii, .Lfunc_end0-_Z6kernelPfS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 36
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPfS_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPfS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000409e6_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6kernelPfS_iiiPfS_iii
.type _Z30__device_stub__Z6kernelPfS_iiiPfS_iii, @function
_Z30__device_stub__Z6kernelPfS_iiiPfS_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6kernelPfS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z6kernelPfS_iiiPfS_iii, .-_Z30__device_stub__Z6kernelPfS_iiiPfS_iii
.globl _Z6kernelPfS_iii
.type _Z6kernelPfS_iii, @function
_Z6kernelPfS_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6kernelPfS_iiiPfS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6kernelPfS_iii, .-_Z6kernelPfS_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kernelPfS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPfS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z21__device_stub__kernelPfS_iii # -- Begin function _Z21__device_stub__kernelPfS_iii
.p2align 4, 0x90
.type _Z21__device_stub__kernelPfS_iii,@function
_Z21__device_stub__kernelPfS_iii: # @_Z21__device_stub__kernelPfS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelPfS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPfS_iii, .Lfunc_end0-_Z21__device_stub__kernelPfS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPfS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPfS_iii,@object # @_Z6kernelPfS_iii
.section .rodata,"a",@progbits
.globl _Z6kernelPfS_iii
.p2align 3, 0x0
_Z6kernelPfS_iii:
.quad _Z21__device_stub__kernelPfS_iii
.size _Z6kernelPfS_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelPfS_iii"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPfS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPfS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #ifndef __lcl_constants
#define __lcl_constants
//#include <thrust/device_vector.h>
#include <cuda.h>
#include <vector>
#include <cufft.h>
#include <cufftXt.h>
#include <stdio.h>
typedef float decimal;
struct MicData {
cufftDoubleComplex** micData;
int* waveLengths;
int numberOfBatches;
};
struct Distances {
decimal* distances;
};
struct Coordinate {
decimal x;
decimal y;
};
struct FftResult {
decimal frequency;
decimal offset;
};
struct FftBatch {
FftResult* fftResults;
unsigned int size;
};
struct WavePair {
int waveIdx1;
int waveIdx2;
decimal offset;
};
struct WavePairContainer{
int firstFFT;
int secondFFT;
WavePair* wavePairArray;
int wavePairCount;
//thrust::device_vector<WavePair> wavePairArray;
};
struct WaveMatches {
std::vector<bool*> matches;
std::vector<unsigned int> widths;
std::vector<unsigned int> heights;
std::vector<int> widthBatches;
std::vector<int> heightBatches;
};
struct GpuWaveMatches {
bool** matches;
unsigned int matchesCount;
unsigned int* widths;
unsigned int widthsCount;
unsigned int* heights;
unsigned int heightsCount;
int* widthBatches;
unsigned int widthBatchesCount;
int* heightBatches;
unsigned int heightBatchesCount;
};
void GpuWaveMatchesToHost(GpuWaveMatches* h_gpuWaveMatches, GpuWaveMatches* d_gpuWaveMatches)
{
h_gpuWaveMatches = (GpuWaveMatches*)malloc(sizeof(GpuWaveMatches));
cudaMemcpy(h_gpuWaveMatches, d_gpuWaveMatches, sizeof(GpuWaveMatches), cudaMemcpyDeviceToHost);
printf("gwmth 1\r\n"); fflush(NULL);
unsigned int* tempWidths = (unsigned int*)malloc( sizeof(unsigned int) * h_gpuWaveMatches->widthsCount);
cudaMemcpy(tempWidths, &h_gpuWaveMatches->widths, sizeof(unsigned int) * h_gpuWaveMatches->widthsCount, cudaMemcpyDeviceToHost);
h_gpuWaveMatches->widths = tempWidths;
printf("gwmth 2\r\n"); fflush(NULL);
unsigned int* tempHeights = (unsigned int*)malloc( sizeof(unsigned int) * h_gpuWaveMatches->heightsCount);
cudaMemcpy(tempHeights, &h_gpuWaveMatches->heights, sizeof(unsigned int) * h_gpuWaveMatches->heightsCount, cudaMemcpyDeviceToHost);
printf("gwmth 3\r\n"); fflush(NULL);
h_gpuWaveMatches->heights = tempHeights;
int* tempWidthBatches = (int*)malloc( sizeof(int) * h_gpuWaveMatches->widthBatchesCount);
cudaMemcpy(tempWidthBatches, &h_gpuWaveMatches->widthBatches, sizeof(int) * h_gpuWaveMatches->widthBatchesCount, cudaMemcpyDeviceToHost);
h_gpuWaveMatches->widthBatches = tempWidthBatches;
printf("gwmth 4\r\n"); fflush(NULL);
int* tempHeightBatches = (int*)malloc( sizeof(int) * h_gpuWaveMatches->heightBatchesCount);
cudaMemcpy(tempHeightBatches, &h_gpuWaveMatches->heightBatches, sizeof(int) * h_gpuWaveMatches->heightBatchesCount, cudaMemcpyDeviceToHost);
h_gpuWaveMatches->heightBatches = tempHeightBatches;
//copy matches
cudaMemcpy(&h_gpuWaveMatches->matches, &d_gpuWaveMatches->matches, sizeof(bool*) * h_gpuWaveMatches->matchesCount, cudaMemcpyDeviceToHost);
for (unsigned int i = 0; i < h_gpuWaveMatches->matchesCount; i++){
printf("widths: %i , heights: %i\r\n", h_gpuWaveMatches->widths[i], h_gpuWaveMatches->heights[i]);
bool* tempMatches = (bool*)malloc( sizeof(bool) * h_gpuWaveMatches->widths[i] * h_gpuWaveMatches->heights[i] );
printf("brianIs");
cudaMemcpy(tempMatches, &h_gpuWaveMatches->matches[i], sizeof(bool) * h_gpuWaveMatches->widths[i] * h_gpuWaveMatches->heights[i], cudaMemcpyDeviceToHost);
printf("notReal");
h_gpuWaveMatches->matches[i] = tempMatches;
printf("its a thing here\r\n");fflush(NULL);
}
}
void freeGpuWaveMatches(GpuWaveMatches* gpuMatches)
{
GpuWaveMatches* h_gpuMatches = (GpuWaveMatches*)malloc(sizeof(GpuWaveMatches));
cudaMemcpy(h_gpuMatches, gpuMatches, sizeof(GpuWaveMatches), cudaMemcpyDeviceToHost);
for (unsigned int i = 0; i < h_gpuMatches->matchesCount; i++)
{
cudaFree(&h_gpuMatches->matches[i]);
}
printf("stuff n things\r\n"); fflush(NULL);
cudaFree(&h_gpuMatches->widths);
cudaFree(&h_gpuMatches->heights);
cudaFree(&h_gpuMatches->widthBatches);
cudaFree(&h_gpuMatches->heightBatches);
free(h_gpuMatches);
cudaFree(gpuMatches);
}
void WaveMatchesToGpu(const WaveMatches& matches, GpuWaveMatches* gpuMatches)
{
//allocate memory for the GpuWaveMatches struct
cudaMalloc(&gpuMatches, sizeof(GpuWaveMatches));
GpuWaveMatches* h_gpuMatches = (GpuWaveMatches*)malloc(sizeof(GpuWaveMatches));
//copy the the matches array and all match matrix
bool** gpuMatchesArray;
cudaMalloc(&gpuMatchesArray, sizeof(bool*) * matches.matches.size());
bool** h_gpuMatchesArray = (bool**)malloc(sizeof(bool*) * matches.matches.size());
for (unsigned int i = 0; i < matches.matches.size(); i++)
{
bool* gpuMatchMatrix;
cudaMalloc(&gpuMatchMatrix, sizeof(bool) * matches.widths[i] * matches.heights[i]);
cudaMemcpy(gpuMatchMatrix, matches.matches[i], sizeof(bool) * matches.widths[i] * matches.heights[i], cudaMemcpyHostToDevice);
h_gpuMatchesArray[i] = gpuMatchMatrix;
}
cudaMemcpy(gpuMatchesArray, h_gpuMatchesArray, sizeof(bool*) * matches.matches.size(), cudaMemcpyHostToDevice);
h_gpuMatches->matches = gpuMatchesArray;
h_gpuMatches->matchesCount = matches.matches.size();
//copy the stored widths
unsigned int* gpuWidths;
cudaMalloc(&gpuWidths, sizeof(unsigned int) * matches.widths.size());
cudaMemcpy(gpuWidths, &matches.widths[0], sizeof(unsigned int) * matches.widths.size(), cudaMemcpyHostToDevice);
h_gpuMatches->widths = gpuWidths;
h_gpuMatches->widthsCount = matches.widths.size();
//copy the stored heights
unsigned int* gpuHeights;
cudaMalloc(&gpuHeights, sizeof(unsigned int) * matches.heights.size());
cudaMemcpy(gpuHeights, &matches.heights[0], sizeof(unsigned int) * matches.heights.size(), cudaMemcpyHostToDevice);
h_gpuMatches->heights = gpuHeights;
h_gpuMatches->heightsCount = matches.heights.size();
//copy stored widthBatches
int* gpuWidthBatches;
cudaMalloc(&gpuWidthBatches, sizeof(int) * matches.widthBatches.size());
cudaMemcpy(gpuWidthBatches, &matches.widthBatches[0], sizeof(int) * matches.widthBatches.size(), cudaMemcpyHostToDevice);
h_gpuMatches->widthBatches = gpuWidthBatches;
h_gpuMatches->widthBatchesCount = matches.widthBatches.size();
//copy stored heightBatches
int* gpuHeightBatches;
cudaMalloc(&gpuHeightBatches, sizeof(int) * matches.heightBatches.size());
cudaMemcpy(gpuHeightBatches, &matches.heightBatches[0], sizeof(int) * matches.heightBatches.size(), cudaMemcpyHostToDevice);
h_gpuMatches->heightBatches = gpuHeightBatches;
h_gpuMatches->heightBatchesCount = matches.heightBatches.size();
cudaMemcpy(gpuMatches, h_gpuMatches, sizeof(GpuWaveMatches), cudaMemcpyHostToDevice);
//TODO: free host memory;
}
#endif | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #ifndef __lcl_constants
#define __lcl_constants
//#include <thrust/device_vector.h>
#include <cuda.h>
#include <vector>
#include <cufft.h>
#include <cufftXt.h>
#include <stdio.h>
typedef float decimal;
struct MicData {
cufftDoubleComplex** micData;
int* waveLengths;
int numberOfBatches;
};
struct Distances {
decimal* distances;
};
struct Coordinate {
decimal x;
decimal y;
};
struct FftResult {
decimal frequency;
decimal offset;
};
struct FftBatch {
FftResult* fftResults;
unsigned int size;
};
struct WavePair {
int waveIdx1;
int waveIdx2;
decimal offset;
};
struct WavePairContainer{
int firstFFT;
int secondFFT;
WavePair* wavePairArray;
int wavePairCount;
//thrust::device_vector<WavePair> wavePairArray;
};
struct WaveMatches {
std::vector<bool*> matches;
std::vector<unsigned int> widths;
std::vector<unsigned int> heights;
std::vector<int> widthBatches;
std::vector<int> heightBatches;
};
struct GpuWaveMatches {
bool** matches;
unsigned int matchesCount;
unsigned int* widths;
unsigned int widthsCount;
unsigned int* heights;
unsigned int heightsCount;
int* widthBatches;
unsigned int widthBatchesCount;
int* heightBatches;
unsigned int heightBatchesCount;
};
void GpuWaveMatchesToHost(GpuWaveMatches* h_gpuWaveMatches, GpuWaveMatches* d_gpuWaveMatches)
{
h_gpuWaveMatches = (GpuWaveMatches*)malloc(sizeof(GpuWaveMatches));
cudaMemcpy(h_gpuWaveMatches, d_gpuWaveMatches, sizeof(GpuWaveMatches), cudaMemcpyDeviceToHost);
printf("gwmth 1\r\n"); fflush(NULL);
unsigned int* tempWidths = (unsigned int*)malloc( sizeof(unsigned int) * h_gpuWaveMatches->widthsCount);
cudaMemcpy(tempWidths, &h_gpuWaveMatches->widths, sizeof(unsigned int) * h_gpuWaveMatches->widthsCount, cudaMemcpyDeviceToHost);
h_gpuWaveMatches->widths = tempWidths;
printf("gwmth 2\r\n"); fflush(NULL);
unsigned int* tempHeights = (unsigned int*)malloc( sizeof(unsigned int) * h_gpuWaveMatches->heightsCount);
cudaMemcpy(tempHeights, &h_gpuWaveMatches->heights, sizeof(unsigned int) * h_gpuWaveMatches->heightsCount, cudaMemcpyDeviceToHost);
printf("gwmth 3\r\n"); fflush(NULL);
h_gpuWaveMatches->heights = tempHeights;
int* tempWidthBatches = (int*)malloc( sizeof(int) * h_gpuWaveMatches->widthBatchesCount);
cudaMemcpy(tempWidthBatches, &h_gpuWaveMatches->widthBatches, sizeof(int) * h_gpuWaveMatches->widthBatchesCount, cudaMemcpyDeviceToHost);
h_gpuWaveMatches->widthBatches = tempWidthBatches;
printf("gwmth 4\r\n"); fflush(NULL);
int* tempHeightBatches = (int*)malloc( sizeof(int) * h_gpuWaveMatches->heightBatchesCount);
cudaMemcpy(tempHeightBatches, &h_gpuWaveMatches->heightBatches, sizeof(int) * h_gpuWaveMatches->heightBatchesCount, cudaMemcpyDeviceToHost);
h_gpuWaveMatches->heightBatches = tempHeightBatches;
//copy matches
cudaMemcpy(&h_gpuWaveMatches->matches, &d_gpuWaveMatches->matches, sizeof(bool*) * h_gpuWaveMatches->matchesCount, cudaMemcpyDeviceToHost);
for (unsigned int i = 0; i < h_gpuWaveMatches->matchesCount; i++){
printf("widths: %i , heights: %i\r\n", h_gpuWaveMatches->widths[i], h_gpuWaveMatches->heights[i]);
bool* tempMatches = (bool*)malloc( sizeof(bool) * h_gpuWaveMatches->widths[i] * h_gpuWaveMatches->heights[i] );
printf("brianIs");
cudaMemcpy(tempMatches, &h_gpuWaveMatches->matches[i], sizeof(bool) * h_gpuWaveMatches->widths[i] * h_gpuWaveMatches->heights[i], cudaMemcpyDeviceToHost);
printf("notReal");
h_gpuWaveMatches->matches[i] = tempMatches;
printf("its a thing here\r\n");fflush(NULL);
}
}
void freeGpuWaveMatches(GpuWaveMatches* gpuMatches)
{
GpuWaveMatches* h_gpuMatches = (GpuWaveMatches*)malloc(sizeof(GpuWaveMatches));
cudaMemcpy(h_gpuMatches, gpuMatches, sizeof(GpuWaveMatches), cudaMemcpyDeviceToHost);
for (unsigned int i = 0; i < h_gpuMatches->matchesCount; i++)
{
cudaFree(&h_gpuMatches->matches[i]);
}
printf("stuff n things\r\n"); fflush(NULL);
cudaFree(&h_gpuMatches->widths);
cudaFree(&h_gpuMatches->heights);
cudaFree(&h_gpuMatches->widthBatches);
cudaFree(&h_gpuMatches->heightBatches);
free(h_gpuMatches);
cudaFree(gpuMatches);
}
void WaveMatchesToGpu(const WaveMatches& matches, GpuWaveMatches* gpuMatches)
{
//allocate memory for the GpuWaveMatches struct
cudaMalloc(&gpuMatches, sizeof(GpuWaveMatches));
GpuWaveMatches* h_gpuMatches = (GpuWaveMatches*)malloc(sizeof(GpuWaveMatches));
//copy the the matches array and all match matrix
bool** gpuMatchesArray;
cudaMalloc(&gpuMatchesArray, sizeof(bool*) * matches.matches.size());
bool** h_gpuMatchesArray = (bool**)malloc(sizeof(bool*) * matches.matches.size());
for (unsigned int i = 0; i < matches.matches.size(); i++)
{
bool* gpuMatchMatrix;
cudaMalloc(&gpuMatchMatrix, sizeof(bool) * matches.widths[i] * matches.heights[i]);
cudaMemcpy(gpuMatchMatrix, matches.matches[i], sizeof(bool) * matches.widths[i] * matches.heights[i], cudaMemcpyHostToDevice);
h_gpuMatchesArray[i] = gpuMatchMatrix;
}
cudaMemcpy(gpuMatchesArray, h_gpuMatchesArray, sizeof(bool*) * matches.matches.size(), cudaMemcpyHostToDevice);
h_gpuMatches->matches = gpuMatchesArray;
h_gpuMatches->matchesCount = matches.matches.size();
//copy the stored widths
unsigned int* gpuWidths;
cudaMalloc(&gpuWidths, sizeof(unsigned int) * matches.widths.size());
cudaMemcpy(gpuWidths, &matches.widths[0], sizeof(unsigned int) * matches.widths.size(), cudaMemcpyHostToDevice);
h_gpuMatches->widths = gpuWidths;
h_gpuMatches->widthsCount = matches.widths.size();
//copy the stored heights
unsigned int* gpuHeights;
cudaMalloc(&gpuHeights, sizeof(unsigned int) * matches.heights.size());
cudaMemcpy(gpuHeights, &matches.heights[0], sizeof(unsigned int) * matches.heights.size(), cudaMemcpyHostToDevice);
h_gpuMatches->heights = gpuHeights;
h_gpuMatches->heightsCount = matches.heights.size();
//copy stored widthBatches
int* gpuWidthBatches;
cudaMalloc(&gpuWidthBatches, sizeof(int) * matches.widthBatches.size());
cudaMemcpy(gpuWidthBatches, &matches.widthBatches[0], sizeof(int) * matches.widthBatches.size(), cudaMemcpyHostToDevice);
h_gpuMatches->widthBatches = gpuWidthBatches;
h_gpuMatches->widthBatchesCount = matches.widthBatches.size();
//copy stored heightBatches
int* gpuHeightBatches;
cudaMalloc(&gpuHeightBatches, sizeof(int) * matches.heightBatches.size());
cudaMemcpy(gpuHeightBatches, &matches.heightBatches[0], sizeof(int) * matches.heightBatches.size(), cudaMemcpyHostToDevice);
h_gpuMatches->heightBatches = gpuHeightBatches;
h_gpuMatches->heightBatchesCount = matches.heightBatches.size();
cudaMemcpy(gpuMatches, h_gpuMatches, sizeof(GpuWaveMatches), cudaMemcpyHostToDevice);
//TODO: free host memory;
}
#endif | .file "tmpxft_0007cd1d_00000000-6_constants.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2955:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2955:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "gwmth 1\r\n"
.LC1:
.string "gwmth 2\r\n"
.LC2:
.string "gwmth 3\r\n"
.LC3:
.string "gwmth 4\r\n"
.LC4:
.string "widths: %i , heights: %i\r\n"
.LC5:
.string "brianIs"
.LC6:
.string "notReal"
.LC7:
.string "its a thing here\r\n"
.text
.globl _Z20GpuWaveMatchesToHostP14GpuWaveMatchesS0_
.type _Z20GpuWaveMatchesToHostP14GpuWaveMatchesS0_, @function
_Z20GpuWaveMatchesToHostP14GpuWaveMatchesS0_:
.LFB2950:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rsi, %rbp
movl $80, %edi
call malloc@PLT
movq %rax, %rbx
movl $2, %ecx
movl $80, %edx
movq %rbp, %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call fflush@PLT
movl 24(%rbx), %r13d
salq $2, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %r12
leaq 16(%rbx), %rsi
movl $2, %ecx
movq %r13, %rdx
movq %rax, %rdi
call cudaMemcpy@PLT
movq %r12, 16(%rbx)
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call fflush@PLT
movl 40(%rbx), %r13d
salq $2, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %r12
leaq 32(%rbx), %rsi
movl $2, %ecx
movq %r13, %rdx
movq %rax, %rdi
call cudaMemcpy@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call fflush@PLT
movq %r12, 32(%rbx)
movl 56(%rbx), %r13d
salq $2, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %r12
leaq 48(%rbx), %rsi
movl $2, %ecx
movq %r13, %rdx
movq %rax, %rdi
call cudaMemcpy@PLT
movq %r12, 48(%rbx)
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call fflush@PLT
movl 72(%rbx), %r13d
salq $2, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %r12
leaq 64(%rbx), %rsi
movl $2, %ecx
movq %r13, %rdx
movq %rax, %rdi
call cudaMemcpy@PLT
movq %r12, 64(%rbx)
movl 8(%rbx), %edx
salq $3, %rdx
movl $2, %ecx
movq %rbp, %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
cmpl $0, 8(%rbx)
je .L3
movl $0, %ebp
leaq .LC4(%rip), %r15
leaq .LC5(%rip), %r14
leaq .LC6(%rip), %r13
.L5:
movq 32(%rbx), %rax
movl (%rax,%rbp,4), %ecx
movq 16(%rbx), %rax
movl (%rax,%rbp,4), %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 16(%rbx), %rax
movl (%rax,%rbp,4), %edi
movq 32(%rbx), %rax
movl (%rax,%rbp,4), %eax
imulq %rax, %rdi
call malloc@PLT
movq %rax, %r12
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 16(%rbx), %rax
movl (%rax,%rbp,4), %edx
movq 32(%rbx), %rax
movl (%rax,%rbp,4), %eax
imulq %rax, %rdx
movq (%rbx), %rax
leaq (%rax,%rbp,8), %rsi
movl $2, %ecx
movq %r12, %rdi
call cudaMemcpy@PLT
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rbx), %rax
movq %r12, (%rax,%rbp,8)
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call fflush@PLT
addq $1, %rbp
cmpl 8(%rbx), %ebp
jb .L5
.L3:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2950:
.size _Z20GpuWaveMatchesToHostP14GpuWaveMatchesS0_, .-_Z20GpuWaveMatchesToHostP14GpuWaveMatchesS0_
.section .rodata.str1.1
.LC8:
.string "stuff n things\r\n"
.text
.globl _Z18freeGpuWaveMatchesP14GpuWaveMatches
.type _Z18freeGpuWaveMatchesP14GpuWaveMatches, @function
_Z18freeGpuWaveMatchesP14GpuWaveMatches:
.LFB2951:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r12
movl $80, %edi
call malloc@PLT
movq %rax, %rbp
movl $2, %ecx
movl $80, %edx
movq %r12, %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
cmpl $0, 8(%rbp)
je .L9
movl $0, %ebx
.L10:
movq 0(%rbp), %rax
leaq (%rax,%rbx,8), %rdi
call cudaFree@PLT
addq $1, %rbx
cmpl 8(%rbp), %ebx
jb .L10
.L9:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call fflush@PLT
leaq 16(%rbp), %rdi
call cudaFree@PLT
leaq 32(%rbp), %rdi
call cudaFree@PLT
leaq 48(%rbp), %rdi
call cudaFree@PLT
leaq 64(%rbp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call cudaFree@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2951:
.size _Z18freeGpuWaveMatchesP14GpuWaveMatches, .-_Z18freeGpuWaveMatchesP14GpuWaveMatches
.globl _Z16WaveMatchesToGpuRK11WaveMatchesP14GpuWaveMatches
.type _Z16WaveMatchesToGpuRK11WaveMatchesP14GpuWaveMatches, @function
_Z16WaveMatchesToGpuRK11WaveMatchesP14GpuWaveMatches:
.LFB2952:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %rbx
movq %rsi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
movl $80, %edi
call malloc@PLT
movq %rax, %r14
movq 8(%rbx), %rsi
subq (%rbx), %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
movq 8(%rbx), %r12
subq (%rbx), %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %r15
testq %r12, %r12
je .L14
movl $0, %r13d
movl $0, %ebp
leaq 48(%rsp), %rax
movq %rax, (%rsp)
.L15:
movq 24(%rbx), %rax
movl (%rax,%rbp,4), %esi
movq 48(%rbx), %rax
movl (%rax,%rbp,4), %eax
imulq %rax, %rsi
movq (%rsp), %rdi
call cudaMalloc@PLT
movq 24(%rbx), %rax
movl (%rax,%rbp,4), %edx
movq 48(%rbx), %rax
movl (%rax,%rbp,4), %eax
imulq %rax, %rdx
movq (%rbx), %rax
movq (%rax,%rbp,8), %rsi
movl $1, %ecx
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movq 48(%rsp), %rax
movq %rax, (%r15,%rbp,8)
addl $1, %r13d
movl %r13d, %ebp
movq 8(%rbx), %r12
subq (%rbx), %r12
movq %r12, %rax
sarq $3, %rax
cmpq %rax, %rbp
jb .L15
.L14:
movl $1, %ecx
movq %r12, %rdx
movq %r15, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movq 16(%rsp), %rax
movq %rax, (%r14)
movq 8(%rbx), %rax
subq (%rbx), %rax
sarq $3, %rax
movl %eax, 8(%r14)
movq 32(%rbx), %rsi
subq 24(%rbx), %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
movq 24(%rbx), %rsi
movq 32(%rbx), %rdx
subq %rsi, %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rax
movq %rax, 16(%r14)
movq 32(%rbx), %rax
subq 24(%rbx), %rax
sarq $2, %rax
movl %eax, 24(%r14)
movq 56(%rbx), %rsi
subq 48(%rbx), %rsi
leaq 32(%rsp), %rdi
call cudaMalloc@PLT
movq 48(%rbx), %rsi
movq 56(%rbx), %rdx
subq %rsi, %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movq 32(%rsp), %rax
movq %rax, 32(%r14)
movq 56(%rbx), %rax
subq 48(%rbx), %rax
sarq $2, %rax
movl %eax, 40(%r14)
movq 80(%rbx), %rsi
subq 72(%rbx), %rsi
leaq 40(%rsp), %rdi
call cudaMalloc@PLT
movq 72(%rbx), %rsi
movq 80(%rbx), %rdx
subq %rsi, %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rax
movq %rax, 48(%r14)
movq 80(%rbx), %rax
subq 72(%rbx), %rax
sarq $2, %rax
movl %eax, 56(%r14)
movq 104(%rbx), %rsi
subq 96(%rbx), %rsi
leaq 48(%rsp), %rdi
call cudaMalloc@PLT
movq 96(%rbx), %rsi
movq 104(%rbx), %rdx
subq %rsi, %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movq 48(%rsp), %rax
movq %rax, 64(%r14)
movq 104(%rbx), %rax
subq 96(%rbx), %rax
sarq $2, %rax
movl %eax, 72(%r14)
movl $1, %ecx
movl $80, %edx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2952:
.size _Z16WaveMatchesToGpuRK11WaveMatchesP14GpuWaveMatches, .-_Z16WaveMatchesToGpuRK11WaveMatchesP14GpuWaveMatches
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2978:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2978:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #ifndef __lcl_constants
#define __lcl_constants
//#include <thrust/device_vector.h>
#include <cuda.h>
#include <vector>
#include <cufft.h>
#include <cufftXt.h>
#include <stdio.h>
typedef float decimal;
struct MicData {
cufftDoubleComplex** micData;
int* waveLengths;
int numberOfBatches;
};
struct Distances {
decimal* distances;
};
struct Coordinate {
decimal x;
decimal y;
};
struct FftResult {
decimal frequency;
decimal offset;
};
struct FftBatch {
FftResult* fftResults;
unsigned int size;
};
struct WavePair {
int waveIdx1;
int waveIdx2;
decimal offset;
};
struct WavePairContainer{
int firstFFT;
int secondFFT;
WavePair* wavePairArray;
int wavePairCount;
//thrust::device_vector<WavePair> wavePairArray;
};
struct WaveMatches {
std::vector<bool*> matches;
std::vector<unsigned int> widths;
std::vector<unsigned int> heights;
std::vector<int> widthBatches;
std::vector<int> heightBatches;
};
struct GpuWaveMatches {
bool** matches;
unsigned int matchesCount;
unsigned int* widths;
unsigned int widthsCount;
unsigned int* heights;
unsigned int heightsCount;
int* widthBatches;
unsigned int widthBatchesCount;
int* heightBatches;
unsigned int heightBatchesCount;
};
void GpuWaveMatchesToHost(GpuWaveMatches* h_gpuWaveMatches, GpuWaveMatches* d_gpuWaveMatches)
{
h_gpuWaveMatches = (GpuWaveMatches*)malloc(sizeof(GpuWaveMatches));
cudaMemcpy(h_gpuWaveMatches, d_gpuWaveMatches, sizeof(GpuWaveMatches), cudaMemcpyDeviceToHost);
printf("gwmth 1\r\n"); fflush(NULL);
unsigned int* tempWidths = (unsigned int*)malloc( sizeof(unsigned int) * h_gpuWaveMatches->widthsCount);
cudaMemcpy(tempWidths, &h_gpuWaveMatches->widths, sizeof(unsigned int) * h_gpuWaveMatches->widthsCount, cudaMemcpyDeviceToHost);
h_gpuWaveMatches->widths = tempWidths;
printf("gwmth 2\r\n"); fflush(NULL);
unsigned int* tempHeights = (unsigned int*)malloc( sizeof(unsigned int) * h_gpuWaveMatches->heightsCount);
cudaMemcpy(tempHeights, &h_gpuWaveMatches->heights, sizeof(unsigned int) * h_gpuWaveMatches->heightsCount, cudaMemcpyDeviceToHost);
printf("gwmth 3\r\n"); fflush(NULL);
h_gpuWaveMatches->heights = tempHeights;
int* tempWidthBatches = (int*)malloc( sizeof(int) * h_gpuWaveMatches->widthBatchesCount);
cudaMemcpy(tempWidthBatches, &h_gpuWaveMatches->widthBatches, sizeof(int) * h_gpuWaveMatches->widthBatchesCount, cudaMemcpyDeviceToHost);
h_gpuWaveMatches->widthBatches = tempWidthBatches;
printf("gwmth 4\r\n"); fflush(NULL);
int* tempHeightBatches = (int*)malloc( sizeof(int) * h_gpuWaveMatches->heightBatchesCount);
cudaMemcpy(tempHeightBatches, &h_gpuWaveMatches->heightBatches, sizeof(int) * h_gpuWaveMatches->heightBatchesCount, cudaMemcpyDeviceToHost);
h_gpuWaveMatches->heightBatches = tempHeightBatches;
//copy matches
cudaMemcpy(&h_gpuWaveMatches->matches, &d_gpuWaveMatches->matches, sizeof(bool*) * h_gpuWaveMatches->matchesCount, cudaMemcpyDeviceToHost);
for (unsigned int i = 0; i < h_gpuWaveMatches->matchesCount; i++){
printf("widths: %i , heights: %i\r\n", h_gpuWaveMatches->widths[i], h_gpuWaveMatches->heights[i]);
bool* tempMatches = (bool*)malloc( sizeof(bool) * h_gpuWaveMatches->widths[i] * h_gpuWaveMatches->heights[i] );
printf("brianIs");
cudaMemcpy(tempMatches, &h_gpuWaveMatches->matches[i], sizeof(bool) * h_gpuWaveMatches->widths[i] * h_gpuWaveMatches->heights[i], cudaMemcpyDeviceToHost);
printf("notReal");
h_gpuWaveMatches->matches[i] = tempMatches;
printf("its a thing here\r\n");fflush(NULL);
}
}
void freeGpuWaveMatches(GpuWaveMatches* gpuMatches)
{
GpuWaveMatches* h_gpuMatches = (GpuWaveMatches*)malloc(sizeof(GpuWaveMatches));
cudaMemcpy(h_gpuMatches, gpuMatches, sizeof(GpuWaveMatches), cudaMemcpyDeviceToHost);
for (unsigned int i = 0; i < h_gpuMatches->matchesCount; i++)
{
cudaFree(&h_gpuMatches->matches[i]);
}
printf("stuff n things\r\n"); fflush(NULL);
cudaFree(&h_gpuMatches->widths);
cudaFree(&h_gpuMatches->heights);
cudaFree(&h_gpuMatches->widthBatches);
cudaFree(&h_gpuMatches->heightBatches);
free(h_gpuMatches);
cudaFree(gpuMatches);
}
void WaveMatchesToGpu(const WaveMatches& matches, GpuWaveMatches* gpuMatches)
{
//allocate memory for the GpuWaveMatches struct
cudaMalloc(&gpuMatches, sizeof(GpuWaveMatches));
GpuWaveMatches* h_gpuMatches = (GpuWaveMatches*)malloc(sizeof(GpuWaveMatches));
//copy the the matches array and all match matrix
bool** gpuMatchesArray;
cudaMalloc(&gpuMatchesArray, sizeof(bool*) * matches.matches.size());
bool** h_gpuMatchesArray = (bool**)malloc(sizeof(bool*) * matches.matches.size());
for (unsigned int i = 0; i < matches.matches.size(); i++)
{
bool* gpuMatchMatrix;
cudaMalloc(&gpuMatchMatrix, sizeof(bool) * matches.widths[i] * matches.heights[i]);
cudaMemcpy(gpuMatchMatrix, matches.matches[i], sizeof(bool) * matches.widths[i] * matches.heights[i], cudaMemcpyHostToDevice);
h_gpuMatchesArray[i] = gpuMatchMatrix;
}
cudaMemcpy(gpuMatchesArray, h_gpuMatchesArray, sizeof(bool*) * matches.matches.size(), cudaMemcpyHostToDevice);
h_gpuMatches->matches = gpuMatchesArray;
h_gpuMatches->matchesCount = matches.matches.size();
//copy the stored widths
unsigned int* gpuWidths;
cudaMalloc(&gpuWidths, sizeof(unsigned int) * matches.widths.size());
cudaMemcpy(gpuWidths, &matches.widths[0], sizeof(unsigned int) * matches.widths.size(), cudaMemcpyHostToDevice);
h_gpuMatches->widths = gpuWidths;
h_gpuMatches->widthsCount = matches.widths.size();
//copy the stored heights
unsigned int* gpuHeights;
cudaMalloc(&gpuHeights, sizeof(unsigned int) * matches.heights.size());
cudaMemcpy(gpuHeights, &matches.heights[0], sizeof(unsigned int) * matches.heights.size(), cudaMemcpyHostToDevice);
h_gpuMatches->heights = gpuHeights;
h_gpuMatches->heightsCount = matches.heights.size();
//copy stored widthBatches
int* gpuWidthBatches;
cudaMalloc(&gpuWidthBatches, sizeof(int) * matches.widthBatches.size());
cudaMemcpy(gpuWidthBatches, &matches.widthBatches[0], sizeof(int) * matches.widthBatches.size(), cudaMemcpyHostToDevice);
h_gpuMatches->widthBatches = gpuWidthBatches;
h_gpuMatches->widthBatchesCount = matches.widthBatches.size();
//copy stored heightBatches
int* gpuHeightBatches;
cudaMalloc(&gpuHeightBatches, sizeof(int) * matches.heightBatches.size());
cudaMemcpy(gpuHeightBatches, &matches.heightBatches[0], sizeof(int) * matches.heightBatches.size(), cudaMemcpyHostToDevice);
h_gpuMatches->heightBatches = gpuHeightBatches;
h_gpuMatches->heightBatchesCount = matches.heightBatches.size();
cudaMemcpy(gpuMatches, h_gpuMatches, sizeof(GpuWaveMatches), cudaMemcpyHostToDevice);
//TODO: free host memory;
}
#endif | #ifndef __lcl_constants
#define __lcl_constants
//#include <thrust/device_vector.h>
#include <hip/hip_runtime.h>
#include <vector>
#include <hipfft/hipfft.h>
#include <hipfft/hipfftXt.h>
#include <stdio.h>
typedef float decimal;
struct MicData {
hipfftDoubleComplex** micData;
int* waveLengths;
int numberOfBatches;
};
struct Distances {
decimal* distances;
};
struct Coordinate {
decimal x;
decimal y;
};
struct FftResult {
decimal frequency;
decimal offset;
};
struct FftBatch {
FftResult* fftResults;
unsigned int size;
};
struct WavePair {
int waveIdx1;
int waveIdx2;
decimal offset;
};
struct WavePairContainer{
int firstFFT;
int secondFFT;
WavePair* wavePairArray;
int wavePairCount;
//thrust::device_vector<WavePair> wavePairArray;
};
struct WaveMatches {
std::vector<bool*> matches;
std::vector<unsigned int> widths;
std::vector<unsigned int> heights;
std::vector<int> widthBatches;
std::vector<int> heightBatches;
};
struct GpuWaveMatches {
bool** matches;
unsigned int matchesCount;
unsigned int* widths;
unsigned int widthsCount;
unsigned int* heights;
unsigned int heightsCount;
int* widthBatches;
unsigned int widthBatchesCount;
int* heightBatches;
unsigned int heightBatchesCount;
};
void GpuWaveMatchesToHost(GpuWaveMatches* h_gpuWaveMatches, GpuWaveMatches* d_gpuWaveMatches)
{
h_gpuWaveMatches = (GpuWaveMatches*)malloc(sizeof(GpuWaveMatches));
hipMemcpy(h_gpuWaveMatches, d_gpuWaveMatches, sizeof(GpuWaveMatches), hipMemcpyDeviceToHost);
printf("gwmth 1\r\n"); fflush(NULL);
unsigned int* tempWidths = (unsigned int*)malloc( sizeof(unsigned int) * h_gpuWaveMatches->widthsCount);
hipMemcpy(tempWidths, &h_gpuWaveMatches->widths, sizeof(unsigned int) * h_gpuWaveMatches->widthsCount, hipMemcpyDeviceToHost);
h_gpuWaveMatches->widths = tempWidths;
printf("gwmth 2\r\n"); fflush(NULL);
unsigned int* tempHeights = (unsigned int*)malloc( sizeof(unsigned int) * h_gpuWaveMatches->heightsCount);
hipMemcpy(tempHeights, &h_gpuWaveMatches->heights, sizeof(unsigned int) * h_gpuWaveMatches->heightsCount, hipMemcpyDeviceToHost);
printf("gwmth 3\r\n"); fflush(NULL);
h_gpuWaveMatches->heights = tempHeights;
int* tempWidthBatches = (int*)malloc( sizeof(int) * h_gpuWaveMatches->widthBatchesCount);
hipMemcpy(tempWidthBatches, &h_gpuWaveMatches->widthBatches, sizeof(int) * h_gpuWaveMatches->widthBatchesCount, hipMemcpyDeviceToHost);
h_gpuWaveMatches->widthBatches = tempWidthBatches;
printf("gwmth 4\r\n"); fflush(NULL);
int* tempHeightBatches = (int*)malloc( sizeof(int) * h_gpuWaveMatches->heightBatchesCount);
hipMemcpy(tempHeightBatches, &h_gpuWaveMatches->heightBatches, sizeof(int) * h_gpuWaveMatches->heightBatchesCount, hipMemcpyDeviceToHost);
h_gpuWaveMatches->heightBatches = tempHeightBatches;
//copy matches
hipMemcpy(&h_gpuWaveMatches->matches, &d_gpuWaveMatches->matches, sizeof(bool*) * h_gpuWaveMatches->matchesCount, hipMemcpyDeviceToHost);
for (unsigned int i = 0; i < h_gpuWaveMatches->matchesCount; i++){
printf("widths: %i , heights: %i\r\n", h_gpuWaveMatches->widths[i], h_gpuWaveMatches->heights[i]);
bool* tempMatches = (bool*)malloc( sizeof(bool) * h_gpuWaveMatches->widths[i] * h_gpuWaveMatches->heights[i] );
printf("brianIs");
hipMemcpy(tempMatches, &h_gpuWaveMatches->matches[i], sizeof(bool) * h_gpuWaveMatches->widths[i] * h_gpuWaveMatches->heights[i], hipMemcpyDeviceToHost);
printf("notReal");
h_gpuWaveMatches->matches[i] = tempMatches;
printf("its a thing here\r\n");fflush(NULL);
}
}
void freeGpuWaveMatches(GpuWaveMatches* gpuMatches)
{
GpuWaveMatches* h_gpuMatches = (GpuWaveMatches*)malloc(sizeof(GpuWaveMatches));
hipMemcpy(h_gpuMatches, gpuMatches, sizeof(GpuWaveMatches), hipMemcpyDeviceToHost);
for (unsigned int i = 0; i < h_gpuMatches->matchesCount; i++)
{
hipFree(&h_gpuMatches->matches[i]);
}
printf("stuff n things\r\n"); fflush(NULL);
hipFree(&h_gpuMatches->widths);
hipFree(&h_gpuMatches->heights);
hipFree(&h_gpuMatches->widthBatches);
hipFree(&h_gpuMatches->heightBatches);
free(h_gpuMatches);
hipFree(gpuMatches);
}
void WaveMatchesToGpu(const WaveMatches& matches, GpuWaveMatches* gpuMatches)
{
//allocate memory for the GpuWaveMatches struct
hipMalloc(&gpuMatches, sizeof(GpuWaveMatches));
GpuWaveMatches* h_gpuMatches = (GpuWaveMatches*)malloc(sizeof(GpuWaveMatches));
//copy the the matches array and all match matrix
bool** gpuMatchesArray;
hipMalloc(&gpuMatchesArray, sizeof(bool*) * matches.matches.size());
bool** h_gpuMatchesArray = (bool**)malloc(sizeof(bool*) * matches.matches.size());
for (unsigned int i = 0; i < matches.matches.size(); i++)
{
bool* gpuMatchMatrix;
hipMalloc(&gpuMatchMatrix, sizeof(bool) * matches.widths[i] * matches.heights[i]);
hipMemcpy(gpuMatchMatrix, matches.matches[i], sizeof(bool) * matches.widths[i] * matches.heights[i], hipMemcpyHostToDevice);
h_gpuMatchesArray[i] = gpuMatchMatrix;
}
hipMemcpy(gpuMatchesArray, h_gpuMatchesArray, sizeof(bool*) * matches.matches.size(), hipMemcpyHostToDevice);
h_gpuMatches->matches = gpuMatchesArray;
h_gpuMatches->matchesCount = matches.matches.size();
//copy the stored widths
unsigned int* gpuWidths;
hipMalloc(&gpuWidths, sizeof(unsigned int) * matches.widths.size());
hipMemcpy(gpuWidths, &matches.widths[0], sizeof(unsigned int) * matches.widths.size(), hipMemcpyHostToDevice);
h_gpuMatches->widths = gpuWidths;
h_gpuMatches->widthsCount = matches.widths.size();
//copy the stored heights
unsigned int* gpuHeights;
hipMalloc(&gpuHeights, sizeof(unsigned int) * matches.heights.size());
hipMemcpy(gpuHeights, &matches.heights[0], sizeof(unsigned int) * matches.heights.size(), hipMemcpyHostToDevice);
h_gpuMatches->heights = gpuHeights;
h_gpuMatches->heightsCount = matches.heights.size();
//copy stored widthBatches
int* gpuWidthBatches;
hipMalloc(&gpuWidthBatches, sizeof(int) * matches.widthBatches.size());
hipMemcpy(gpuWidthBatches, &matches.widthBatches[0], sizeof(int) * matches.widthBatches.size(), hipMemcpyHostToDevice);
h_gpuMatches->widthBatches = gpuWidthBatches;
h_gpuMatches->widthBatchesCount = matches.widthBatches.size();
//copy stored heightBatches
int* gpuHeightBatches;
hipMalloc(&gpuHeightBatches, sizeof(int) * matches.heightBatches.size());
hipMemcpy(gpuHeightBatches, &matches.heightBatches[0], sizeof(int) * matches.heightBatches.size(), hipMemcpyHostToDevice);
h_gpuMatches->heightBatches = gpuHeightBatches;
h_gpuMatches->heightBatchesCount = matches.heightBatches.size();
hipMemcpy(gpuMatches, h_gpuMatches, sizeof(GpuWaveMatches), hipMemcpyHostToDevice);
//TODO: free host memory;
}
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #ifndef __lcl_constants
#define __lcl_constants
//#include <thrust/device_vector.h>
#include <hip/hip_runtime.h>
#include <vector>
#include <hipfft/hipfft.h>
#include <hipfft/hipfftXt.h>
#include <stdio.h>
typedef float decimal;
struct MicData {
hipfftDoubleComplex** micData;
int* waveLengths;
int numberOfBatches;
};
struct Distances {
decimal* distances;
};
struct Coordinate {
decimal x;
decimal y;
};
struct FftResult {
decimal frequency;
decimal offset;
};
struct FftBatch {
FftResult* fftResults;
unsigned int size;
};
struct WavePair {
int waveIdx1;
int waveIdx2;
decimal offset;
};
struct WavePairContainer{
int firstFFT;
int secondFFT;
WavePair* wavePairArray;
int wavePairCount;
//thrust::device_vector<WavePair> wavePairArray;
};
struct WaveMatches {
std::vector<bool*> matches;
std::vector<unsigned int> widths;
std::vector<unsigned int> heights;
std::vector<int> widthBatches;
std::vector<int> heightBatches;
};
struct GpuWaveMatches {
bool** matches;
unsigned int matchesCount;
unsigned int* widths;
unsigned int widthsCount;
unsigned int* heights;
unsigned int heightsCount;
int* widthBatches;
unsigned int widthBatchesCount;
int* heightBatches;
unsigned int heightBatchesCount;
};
void GpuWaveMatchesToHost(GpuWaveMatches* h_gpuWaveMatches, GpuWaveMatches* d_gpuWaveMatches)
{
h_gpuWaveMatches = (GpuWaveMatches*)malloc(sizeof(GpuWaveMatches));
hipMemcpy(h_gpuWaveMatches, d_gpuWaveMatches, sizeof(GpuWaveMatches), hipMemcpyDeviceToHost);
printf("gwmth 1\r\n"); fflush(NULL);
unsigned int* tempWidths = (unsigned int*)malloc( sizeof(unsigned int) * h_gpuWaveMatches->widthsCount);
hipMemcpy(tempWidths, &h_gpuWaveMatches->widths, sizeof(unsigned int) * h_gpuWaveMatches->widthsCount, hipMemcpyDeviceToHost);
h_gpuWaveMatches->widths = tempWidths;
printf("gwmth 2\r\n"); fflush(NULL);
unsigned int* tempHeights = (unsigned int*)malloc( sizeof(unsigned int) * h_gpuWaveMatches->heightsCount);
hipMemcpy(tempHeights, &h_gpuWaveMatches->heights, sizeof(unsigned int) * h_gpuWaveMatches->heightsCount, hipMemcpyDeviceToHost);
printf("gwmth 3\r\n"); fflush(NULL);
h_gpuWaveMatches->heights = tempHeights;
int* tempWidthBatches = (int*)malloc( sizeof(int) * h_gpuWaveMatches->widthBatchesCount);
hipMemcpy(tempWidthBatches, &h_gpuWaveMatches->widthBatches, sizeof(int) * h_gpuWaveMatches->widthBatchesCount, hipMemcpyDeviceToHost);
h_gpuWaveMatches->widthBatches = tempWidthBatches;
printf("gwmth 4\r\n"); fflush(NULL);
int* tempHeightBatches = (int*)malloc( sizeof(int) * h_gpuWaveMatches->heightBatchesCount);
hipMemcpy(tempHeightBatches, &h_gpuWaveMatches->heightBatches, sizeof(int) * h_gpuWaveMatches->heightBatchesCount, hipMemcpyDeviceToHost);
h_gpuWaveMatches->heightBatches = tempHeightBatches;
//copy matches
hipMemcpy(&h_gpuWaveMatches->matches, &d_gpuWaveMatches->matches, sizeof(bool*) * h_gpuWaveMatches->matchesCount, hipMemcpyDeviceToHost);
for (unsigned int i = 0; i < h_gpuWaveMatches->matchesCount; i++){
printf("widths: %i , heights: %i\r\n", h_gpuWaveMatches->widths[i], h_gpuWaveMatches->heights[i]);
bool* tempMatches = (bool*)malloc( sizeof(bool) * h_gpuWaveMatches->widths[i] * h_gpuWaveMatches->heights[i] );
printf("brianIs");
hipMemcpy(tempMatches, &h_gpuWaveMatches->matches[i], sizeof(bool) * h_gpuWaveMatches->widths[i] * h_gpuWaveMatches->heights[i], hipMemcpyDeviceToHost);
printf("notReal");
h_gpuWaveMatches->matches[i] = tempMatches;
printf("its a thing here\r\n");fflush(NULL);
}
}
void freeGpuWaveMatches(GpuWaveMatches* gpuMatches)
{
GpuWaveMatches* h_gpuMatches = (GpuWaveMatches*)malloc(sizeof(GpuWaveMatches));
hipMemcpy(h_gpuMatches, gpuMatches, sizeof(GpuWaveMatches), hipMemcpyDeviceToHost);
for (unsigned int i = 0; i < h_gpuMatches->matchesCount; i++)
{
hipFree(&h_gpuMatches->matches[i]);
}
printf("stuff n things\r\n"); fflush(NULL);
hipFree(&h_gpuMatches->widths);
hipFree(&h_gpuMatches->heights);
hipFree(&h_gpuMatches->widthBatches);
hipFree(&h_gpuMatches->heightBatches);
free(h_gpuMatches);
hipFree(gpuMatches);
}
void WaveMatchesToGpu(const WaveMatches& matches, GpuWaveMatches* gpuMatches)
{
//allocate memory for the GpuWaveMatches struct
hipMalloc(&gpuMatches, sizeof(GpuWaveMatches));
GpuWaveMatches* h_gpuMatches = (GpuWaveMatches*)malloc(sizeof(GpuWaveMatches));
//copy the the matches array and all match matrix
bool** gpuMatchesArray;
hipMalloc(&gpuMatchesArray, sizeof(bool*) * matches.matches.size());
bool** h_gpuMatchesArray = (bool**)malloc(sizeof(bool*) * matches.matches.size());
for (unsigned int i = 0; i < matches.matches.size(); i++)
{
bool* gpuMatchMatrix;
hipMalloc(&gpuMatchMatrix, sizeof(bool) * matches.widths[i] * matches.heights[i]);
hipMemcpy(gpuMatchMatrix, matches.matches[i], sizeof(bool) * matches.widths[i] * matches.heights[i], hipMemcpyHostToDevice);
h_gpuMatchesArray[i] = gpuMatchMatrix;
}
hipMemcpy(gpuMatchesArray, h_gpuMatchesArray, sizeof(bool*) * matches.matches.size(), hipMemcpyHostToDevice);
h_gpuMatches->matches = gpuMatchesArray;
h_gpuMatches->matchesCount = matches.matches.size();
//copy the stored widths
unsigned int* gpuWidths;
hipMalloc(&gpuWidths, sizeof(unsigned int) * matches.widths.size());
hipMemcpy(gpuWidths, &matches.widths[0], sizeof(unsigned int) * matches.widths.size(), hipMemcpyHostToDevice);
h_gpuMatches->widths = gpuWidths;
h_gpuMatches->widthsCount = matches.widths.size();
//copy the stored heights
unsigned int* gpuHeights;
hipMalloc(&gpuHeights, sizeof(unsigned int) * matches.heights.size());
hipMemcpy(gpuHeights, &matches.heights[0], sizeof(unsigned int) * matches.heights.size(), hipMemcpyHostToDevice);
h_gpuMatches->heights = gpuHeights;
h_gpuMatches->heightsCount = matches.heights.size();
//copy stored widthBatches
int* gpuWidthBatches;
hipMalloc(&gpuWidthBatches, sizeof(int) * matches.widthBatches.size());
hipMemcpy(gpuWidthBatches, &matches.widthBatches[0], sizeof(int) * matches.widthBatches.size(), hipMemcpyHostToDevice);
h_gpuMatches->widthBatches = gpuWidthBatches;
h_gpuMatches->widthBatchesCount = matches.widthBatches.size();
//copy stored heightBatches
int* gpuHeightBatches;
hipMalloc(&gpuHeightBatches, sizeof(int) * matches.heightBatches.size());
hipMemcpy(gpuHeightBatches, &matches.heightBatches[0], sizeof(int) * matches.heightBatches.size(), hipMemcpyHostToDevice);
h_gpuMatches->heightBatches = gpuHeightBatches;
h_gpuMatches->heightBatchesCount = matches.heightBatches.size();
hipMemcpy(gpuMatches, h_gpuMatches, sizeof(GpuWaveMatches), hipMemcpyHostToDevice);
//TODO: free host memory;
}
#endif | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #ifndef __lcl_constants
#define __lcl_constants
//#include <thrust/device_vector.h>
#include <hip/hip_runtime.h>
#include <vector>
#include <hipfft/hipfft.h>
#include <hipfft/hipfftXt.h>
#include <stdio.h>
typedef float decimal;
struct MicData {
hipfftDoubleComplex** micData;
int* waveLengths;
int numberOfBatches;
};
struct Distances {
decimal* distances;
};
struct Coordinate {
decimal x;
decimal y;
};
struct FftResult {
decimal frequency;
decimal offset;
};
struct FftBatch {
FftResult* fftResults;
unsigned int size;
};
struct WavePair {
int waveIdx1;
int waveIdx2;
decimal offset;
};
struct WavePairContainer{
int firstFFT;
int secondFFT;
WavePair* wavePairArray;
int wavePairCount;
//thrust::device_vector<WavePair> wavePairArray;
};
struct WaveMatches {
std::vector<bool*> matches;
std::vector<unsigned int> widths;
std::vector<unsigned int> heights;
std::vector<int> widthBatches;
std::vector<int> heightBatches;
};
struct GpuWaveMatches {
bool** matches;
unsigned int matchesCount;
unsigned int* widths;
unsigned int widthsCount;
unsigned int* heights;
unsigned int heightsCount;
int* widthBatches;
unsigned int widthBatchesCount;
int* heightBatches;
unsigned int heightBatchesCount;
};
void GpuWaveMatchesToHost(GpuWaveMatches* h_gpuWaveMatches, GpuWaveMatches* d_gpuWaveMatches)
{
h_gpuWaveMatches = (GpuWaveMatches*)malloc(sizeof(GpuWaveMatches));
hipMemcpy(h_gpuWaveMatches, d_gpuWaveMatches, sizeof(GpuWaveMatches), hipMemcpyDeviceToHost);
printf("gwmth 1\r\n"); fflush(NULL);
unsigned int* tempWidths = (unsigned int*)malloc( sizeof(unsigned int) * h_gpuWaveMatches->widthsCount);
hipMemcpy(tempWidths, &h_gpuWaveMatches->widths, sizeof(unsigned int) * h_gpuWaveMatches->widthsCount, hipMemcpyDeviceToHost);
h_gpuWaveMatches->widths = tempWidths;
printf("gwmth 2\r\n"); fflush(NULL);
unsigned int* tempHeights = (unsigned int*)malloc( sizeof(unsigned int) * h_gpuWaveMatches->heightsCount);
hipMemcpy(tempHeights, &h_gpuWaveMatches->heights, sizeof(unsigned int) * h_gpuWaveMatches->heightsCount, hipMemcpyDeviceToHost);
printf("gwmth 3\r\n"); fflush(NULL);
h_gpuWaveMatches->heights = tempHeights;
int* tempWidthBatches = (int*)malloc( sizeof(int) * h_gpuWaveMatches->widthBatchesCount);
hipMemcpy(tempWidthBatches, &h_gpuWaveMatches->widthBatches, sizeof(int) * h_gpuWaveMatches->widthBatchesCount, hipMemcpyDeviceToHost);
h_gpuWaveMatches->widthBatches = tempWidthBatches;
printf("gwmth 4\r\n"); fflush(NULL);
int* tempHeightBatches = (int*)malloc( sizeof(int) * h_gpuWaveMatches->heightBatchesCount);
hipMemcpy(tempHeightBatches, &h_gpuWaveMatches->heightBatches, sizeof(int) * h_gpuWaveMatches->heightBatchesCount, hipMemcpyDeviceToHost);
h_gpuWaveMatches->heightBatches = tempHeightBatches;
//copy matches
hipMemcpy(&h_gpuWaveMatches->matches, &d_gpuWaveMatches->matches, sizeof(bool*) * h_gpuWaveMatches->matchesCount, hipMemcpyDeviceToHost);
for (unsigned int i = 0; i < h_gpuWaveMatches->matchesCount; i++){
printf("widths: %i , heights: %i\r\n", h_gpuWaveMatches->widths[i], h_gpuWaveMatches->heights[i]);
bool* tempMatches = (bool*)malloc( sizeof(bool) * h_gpuWaveMatches->widths[i] * h_gpuWaveMatches->heights[i] );
printf("brianIs");
hipMemcpy(tempMatches, &h_gpuWaveMatches->matches[i], sizeof(bool) * h_gpuWaveMatches->widths[i] * h_gpuWaveMatches->heights[i], hipMemcpyDeviceToHost);
printf("notReal");
h_gpuWaveMatches->matches[i] = tempMatches;
printf("its a thing here\r\n");fflush(NULL);
}
}
void freeGpuWaveMatches(GpuWaveMatches* gpuMatches)
{
GpuWaveMatches* h_gpuMatches = (GpuWaveMatches*)malloc(sizeof(GpuWaveMatches));
hipMemcpy(h_gpuMatches, gpuMatches, sizeof(GpuWaveMatches), hipMemcpyDeviceToHost);
for (unsigned int i = 0; i < h_gpuMatches->matchesCount; i++)
{
hipFree(&h_gpuMatches->matches[i]);
}
printf("stuff n things\r\n"); fflush(NULL);
hipFree(&h_gpuMatches->widths);
hipFree(&h_gpuMatches->heights);
hipFree(&h_gpuMatches->widthBatches);
hipFree(&h_gpuMatches->heightBatches);
free(h_gpuMatches);
hipFree(gpuMatches);
}
void WaveMatchesToGpu(const WaveMatches& matches, GpuWaveMatches* gpuMatches)
{
//allocate memory for the GpuWaveMatches struct
hipMalloc(&gpuMatches, sizeof(GpuWaveMatches));
GpuWaveMatches* h_gpuMatches = (GpuWaveMatches*)malloc(sizeof(GpuWaveMatches));
//copy the the matches array and all match matrix
bool** gpuMatchesArray;
hipMalloc(&gpuMatchesArray, sizeof(bool*) * matches.matches.size());
bool** h_gpuMatchesArray = (bool**)malloc(sizeof(bool*) * matches.matches.size());
for (unsigned int i = 0; i < matches.matches.size(); i++)
{
bool* gpuMatchMatrix;
hipMalloc(&gpuMatchMatrix, sizeof(bool) * matches.widths[i] * matches.heights[i]);
hipMemcpy(gpuMatchMatrix, matches.matches[i], sizeof(bool) * matches.widths[i] * matches.heights[i], hipMemcpyHostToDevice);
h_gpuMatchesArray[i] = gpuMatchMatrix;
}
hipMemcpy(gpuMatchesArray, h_gpuMatchesArray, sizeof(bool*) * matches.matches.size(), hipMemcpyHostToDevice);
h_gpuMatches->matches = gpuMatchesArray;
h_gpuMatches->matchesCount = matches.matches.size();
//copy the stored widths
unsigned int* gpuWidths;
hipMalloc(&gpuWidths, sizeof(unsigned int) * matches.widths.size());
hipMemcpy(gpuWidths, &matches.widths[0], sizeof(unsigned int) * matches.widths.size(), hipMemcpyHostToDevice);
h_gpuMatches->widths = gpuWidths;
h_gpuMatches->widthsCount = matches.widths.size();
//copy the stored heights
unsigned int* gpuHeights;
hipMalloc(&gpuHeights, sizeof(unsigned int) * matches.heights.size());
hipMemcpy(gpuHeights, &matches.heights[0], sizeof(unsigned int) * matches.heights.size(), hipMemcpyHostToDevice);
h_gpuMatches->heights = gpuHeights;
h_gpuMatches->heightsCount = matches.heights.size();
//copy stored widthBatches
int* gpuWidthBatches;
hipMalloc(&gpuWidthBatches, sizeof(int) * matches.widthBatches.size());
hipMemcpy(gpuWidthBatches, &matches.widthBatches[0], sizeof(int) * matches.widthBatches.size(), hipMemcpyHostToDevice);
h_gpuMatches->widthBatches = gpuWidthBatches;
h_gpuMatches->widthBatchesCount = matches.widthBatches.size();
//copy stored heightBatches
int* gpuHeightBatches;
hipMalloc(&gpuHeightBatches, sizeof(int) * matches.heightBatches.size());
hipMemcpy(gpuHeightBatches, &matches.heightBatches[0], sizeof(int) * matches.heightBatches.size(), hipMemcpyHostToDevice);
h_gpuMatches->heightBatches = gpuHeightBatches;
h_gpuMatches->heightBatchesCount = matches.heightBatches.size();
hipMemcpy(gpuMatches, h_gpuMatches, sizeof(GpuWaveMatches), hipMemcpyHostToDevice);
//TODO: free host memory;
}
#endif | .text
.file "constants.hip"
.globl _Z20GpuWaveMatchesToHostP14GpuWaveMatchesS0_ # -- Begin function _Z20GpuWaveMatchesToHostP14GpuWaveMatchesS0_
.p2align 4, 0x90
.type _Z20GpuWaveMatchesToHostP14GpuWaveMatchesS0_,@function
_Z20GpuWaveMatchesToHostP14GpuWaveMatchesS0_: # @_Z20GpuWaveMatchesToHostP14GpuWaveMatchesS0_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %r14
movl $80, %edi
callq malloc
movq %rax, %rbx
movl $80, %edx
movq %rax, %rdi
movq %r14, %rsi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
xorl %edi, %edi
callq fflush
movl 24(%rbx), %r15d
shlq $2, %r15
movq %r15, %rdi
callq malloc
movq %rax, %r12
leaq 16(%rbx), %rsi
movq %rax, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movq %r12, 16(%rbx)
movl $.Lstr.1, %edi
callq puts@PLT
xorl %edi, %edi
callq fflush
movl 40(%rbx), %r15d
shlq $2, %r15
movq %r15, %rdi
callq malloc
movq %rax, %r12
leaq 32(%rbx), %rsi
movq %rax, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.2, %edi
callq puts@PLT
xorl %edi, %edi
callq fflush
movq %r12, 32(%rbx)
movl 56(%rbx), %r15d
shlq $2, %r15
movq %r15, %rdi
callq malloc
movq %rax, %r12
leaq 48(%rbx), %rsi
movq %rax, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movq %r12, 48(%rbx)
movl $.Lstr.3, %edi
callq puts@PLT
xorl %edi, %edi
callq fflush
movl 72(%rbx), %r15d
shlq $2, %r15
movq %r15, %rdi
callq malloc
movq %rax, %r12
leaq 64(%rbx), %rsi
movq %rax, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movq %r12, 64(%rbx)
movl 8(%rbx), %edx
shlq $3, %rdx
movq %rbx, %rdi
movq %r14, %rsi
movl $2, %ecx
callq hipMemcpy
cmpl $0, 8(%rbx)
je .LBB0_3
# %bb.1: # %.lr.ph.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq 16(%rbx), %rax
movq 32(%rbx), %rcx
movl (%rax,%r15,4), %esi
movl (%rcx,%r15,4), %edx
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movq 16(%rbx), %rax
movq 32(%rbx), %rcx
movl (%rax,%r15,4), %eax
movl (%rcx,%r15,4), %edi
imulq %rax, %rdi
callq malloc
movq %rax, %r14
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
leaq (,%r15,8), %rsi
addq (%rbx), %rsi
movq 16(%rbx), %rax
movq 32(%rbx), %rcx
movl (%rax,%r15,4), %eax
movl (%rcx,%r15,4), %edx
imulq %rax, %rdx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movq (%rbx), %rax
movq %r14, (%rax,%r15,8)
movl $.Lstr.4, %edi
callq puts@PLT
xorl %edi, %edi
callq fflush
incq %r15
movl 8(%rbx), %eax
cmpq %rax, %r15
jb .LBB0_2
.LBB0_3: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z20GpuWaveMatchesToHostP14GpuWaveMatchesS0_, .Lfunc_end0-_Z20GpuWaveMatchesToHostP14GpuWaveMatchesS0_
.cfi_endproc
# -- End function
.globl _Z18freeGpuWaveMatchesP14GpuWaveMatches # -- Begin function _Z18freeGpuWaveMatchesP14GpuWaveMatches
.p2align 4, 0x90
.type _Z18freeGpuWaveMatchesP14GpuWaveMatches,@function
_Z18freeGpuWaveMatchesP14GpuWaveMatches: # @_Z18freeGpuWaveMatchesP14GpuWaveMatches
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl $80, %edi
callq malloc
movq %rax, %r14
movl $80, %edx
movq %rax, %rdi
movq %rbx, %rsi
movl $2, %ecx
callq hipMemcpy
cmpl $0, 8(%r14)
je .LBB1_3
# %bb.1: # %.lr.ph.preheader
xorl %r15d, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq (%r14), %rdi
addq %r15, %rdi
callq hipFree
incq %r12
movl 8(%r14), %eax
addq $8, %r15
cmpq %rax, %r12
jb .LBB1_2
.LBB1_3: # %._crit_edge
movl $.Lstr.5, %edi
callq puts@PLT
xorl %edi, %edi
callq fflush
leaq 16(%r14), %rdi
callq hipFree
leaq 32(%r14), %rdi
callq hipFree
leaq 48(%r14), %rdi
callq hipFree
movq %r14, %rdi
addq $64, %rdi
callq hipFree
movq %r14, %rdi
callq free
movq %rbx, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp hipFree # TAILCALL
.Lfunc_end1:
.size _Z18freeGpuWaveMatchesP14GpuWaveMatches, .Lfunc_end1-_Z18freeGpuWaveMatchesP14GpuWaveMatches
.cfi_endproc
# -- End function
.globl _Z16WaveMatchesToGpuRK11WaveMatchesP14GpuWaveMatches # -- Begin function _Z16WaveMatchesToGpuRK11WaveMatchesP14GpuWaveMatches
.p2align 4, 0x90
.type _Z16WaveMatchesToGpuRK11WaveMatchesP14GpuWaveMatches,@function
_Z16WaveMatchesToGpuRK11WaveMatchesP14GpuWaveMatches: # @_Z16WaveMatchesToGpuRK11WaveMatchesP14GpuWaveMatches
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $56, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
movq %rsi, 40(%rsp)
leaq 40(%rsp), %rdi
movl $80, %esi
callq hipMalloc
movl $80, %edi
callq malloc
movq %rax, 48(%rsp) # 8-byte Spill
movq 8(%rbx), %rsi
subq (%rbx), %rsi
leaq 32(%rsp), %rdi
callq hipMalloc
movq 8(%rbx), %r13
movq (%rbx), %r14
movq %r13, %rdi
subq %r14, %rdi
callq malloc
movq %rax, %r15
subq %r14, %r13
je .LBB2_3
# %bb.1: # %.lr.ph
movl $1, %ebp
xorl %r14d, %r14d
movq %rsp, %r12
.p2align 4, 0x90
.LBB2_2: # =>This Inner Loop Header: Depth=1
movq 24(%rbx), %rax
movq 48(%rbx), %rcx
movl (%rax,%r14,4), %eax
movl (%rcx,%r14,4), %esi
imulq %rax, %rsi
movq %r12, %rdi
callq hipMalloc
movq (%rsp), %rdi
movq (%rbx), %rax
movq 24(%rbx), %rcx
movq (%rax,%r14,8), %rsi
movl (%rcx,%r14,4), %eax
movq 48(%rbx), %rcx
movl (%rcx,%r14,4), %edx
imulq %rax, %rdx
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rax
movq %rax, (%r15,%r14,8)
movl %ebp, %r14d
movq 8(%rbx), %r13
subq (%rbx), %r13
movq %r13, %rax
sarq $3, %rax
incl %ebp
cmpq %r14, %rax
ja .LBB2_2
.LBB2_3: # %._crit_edge
movq 32(%rsp), %rdi
movq %r15, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rax
movq 48(%rsp), %r14 # 8-byte Reload
movq %rax, (%r14)
movq 8(%rbx), %rax
subq (%rbx), %rax
shrq $3, %rax
movl %eax, 8(%r14)
movq 32(%rbx), %rsi
subq 24(%rbx), %rsi
movq %rsp, %rdi
callq hipMalloc
movq (%rsp), %rdi
movq 24(%rbx), %rsi
movq 32(%rbx), %rdx
subq %rsi, %rdx
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rax
movq %rax, 16(%r14)
movq 32(%rbx), %rax
subq 24(%rbx), %rax
shrq $2, %rax
movl %eax, 24(%r14)
movq 56(%rbx), %rsi
subq 48(%rbx), %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
movq 24(%rsp), %rdi
movq 48(%rbx), %rsi
movq 56(%rbx), %rdx
subq %rsi, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rax
movq %rax, 32(%r14)
movq 56(%rbx), %rax
subq 48(%rbx), %rax
shrq $2, %rax
movl %eax, 40(%r14)
movq 80(%rbx), %rsi
subq 72(%rbx), %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
movq 16(%rsp), %rdi
movq 72(%rbx), %rsi
movq 80(%rbx), %rdx
subq %rsi, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rax
movq %rax, 48(%r14)
movq 80(%rbx), %rax
subq 72(%rbx), %rax
shrq $2, %rax
movl %eax, 56(%r14)
movq 104(%rbx), %rsi
subq 96(%rbx), %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
movq 8(%rsp), %rdi
movq 96(%rbx), %rsi
movq 104(%rbx), %rdx
subq %rsi, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rax
movq %rax, 64(%r14)
movq 104(%rbx), %rax
subq 96(%rbx), %rax
shrq $2, %rax
movl %eax, 72(%r14)
movq 40(%rsp), %rdi
movl $80, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z16WaveMatchesToGpuRK11WaveMatchesP14GpuWaveMatches, .Lfunc_end2-_Z16WaveMatchesToGpuRK11WaveMatchesP14GpuWaveMatches
.cfi_endproc
# -- End function
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "widths: %i , heights: %i\r\n"
.size .L.str.4, 27
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "brianIs"
.size .L.str.5, 8
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "notReal"
.size .L.str.6, 8
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "gwmth 1\r"
.size .Lstr, 9
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "gwmth 2\r"
.size .Lstr.1, 9
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "gwmth 3\r"
.size .Lstr.2, 9
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "gwmth 4\r"
.size .Lstr.3, 9
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "its a thing here\r"
.size .Lstr.4, 18
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "stuff n things\r"
.size .Lstr.5, 16
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007cd1d_00000000-6_constants.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2955:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2955:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "gwmth 1\r\n"
.LC1:
.string "gwmth 2\r\n"
.LC2:
.string "gwmth 3\r\n"
.LC3:
.string "gwmth 4\r\n"
.LC4:
.string "widths: %i , heights: %i\r\n"
.LC5:
.string "brianIs"
.LC6:
.string "notReal"
.LC7:
.string "its a thing here\r\n"
.text
.globl _Z20GpuWaveMatchesToHostP14GpuWaveMatchesS0_
.type _Z20GpuWaveMatchesToHostP14GpuWaveMatchesS0_, @function
_Z20GpuWaveMatchesToHostP14GpuWaveMatchesS0_:
.LFB2950:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rsi, %rbp
movl $80, %edi
call malloc@PLT
movq %rax, %rbx
movl $2, %ecx
movl $80, %edx
movq %rbp, %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call fflush@PLT
movl 24(%rbx), %r13d
salq $2, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %r12
leaq 16(%rbx), %rsi
movl $2, %ecx
movq %r13, %rdx
movq %rax, %rdi
call cudaMemcpy@PLT
movq %r12, 16(%rbx)
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call fflush@PLT
movl 40(%rbx), %r13d
salq $2, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %r12
leaq 32(%rbx), %rsi
movl $2, %ecx
movq %r13, %rdx
movq %rax, %rdi
call cudaMemcpy@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call fflush@PLT
movq %r12, 32(%rbx)
movl 56(%rbx), %r13d
salq $2, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %r12
leaq 48(%rbx), %rsi
movl $2, %ecx
movq %r13, %rdx
movq %rax, %rdi
call cudaMemcpy@PLT
movq %r12, 48(%rbx)
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call fflush@PLT
movl 72(%rbx), %r13d
salq $2, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %r12
leaq 64(%rbx), %rsi
movl $2, %ecx
movq %r13, %rdx
movq %rax, %rdi
call cudaMemcpy@PLT
movq %r12, 64(%rbx)
movl 8(%rbx), %edx
salq $3, %rdx
movl $2, %ecx
movq %rbp, %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
cmpl $0, 8(%rbx)
je .L3
movl $0, %ebp
leaq .LC4(%rip), %r15
leaq .LC5(%rip), %r14
leaq .LC6(%rip), %r13
.L5:
movq 32(%rbx), %rax
movl (%rax,%rbp,4), %ecx
movq 16(%rbx), %rax
movl (%rax,%rbp,4), %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 16(%rbx), %rax
movl (%rax,%rbp,4), %edi
movq 32(%rbx), %rax
movl (%rax,%rbp,4), %eax
imulq %rax, %rdi
call malloc@PLT
movq %rax, %r12
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 16(%rbx), %rax
movl (%rax,%rbp,4), %edx
movq 32(%rbx), %rax
movl (%rax,%rbp,4), %eax
imulq %rax, %rdx
movq (%rbx), %rax
leaq (%rax,%rbp,8), %rsi
movl $2, %ecx
movq %r12, %rdi
call cudaMemcpy@PLT
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rbx), %rax
movq %r12, (%rax,%rbp,8)
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call fflush@PLT
addq $1, %rbp
cmpl 8(%rbx), %ebp
jb .L5
.L3:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2950:
.size _Z20GpuWaveMatchesToHostP14GpuWaveMatchesS0_, .-_Z20GpuWaveMatchesToHostP14GpuWaveMatchesS0_
.section .rodata.str1.1
.LC8:
.string "stuff n things\r\n"
.text
.globl _Z18freeGpuWaveMatchesP14GpuWaveMatches
.type _Z18freeGpuWaveMatchesP14GpuWaveMatches, @function
_Z18freeGpuWaveMatchesP14GpuWaveMatches:
.LFB2951:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r12
movl $80, %edi
call malloc@PLT
movq %rax, %rbp
movl $2, %ecx
movl $80, %edx
movq %r12, %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
cmpl $0, 8(%rbp)
je .L9
movl $0, %ebx
.L10:
movq 0(%rbp), %rax
leaq (%rax,%rbx,8), %rdi
call cudaFree@PLT
addq $1, %rbx
cmpl 8(%rbp), %ebx
jb .L10
.L9:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call fflush@PLT
leaq 16(%rbp), %rdi
call cudaFree@PLT
leaq 32(%rbp), %rdi
call cudaFree@PLT
leaq 48(%rbp), %rdi
call cudaFree@PLT
leaq 64(%rbp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call cudaFree@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2951:
.size _Z18freeGpuWaveMatchesP14GpuWaveMatches, .-_Z18freeGpuWaveMatchesP14GpuWaveMatches
.globl _Z16WaveMatchesToGpuRK11WaveMatchesP14GpuWaveMatches
.type _Z16WaveMatchesToGpuRK11WaveMatchesP14GpuWaveMatches, @function
_Z16WaveMatchesToGpuRK11WaveMatchesP14GpuWaveMatches:
.LFB2952:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %rbx
movq %rsi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
movl $80, %edi
call malloc@PLT
movq %rax, %r14
movq 8(%rbx), %rsi
subq (%rbx), %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
movq 8(%rbx), %r12
subq (%rbx), %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %r15
testq %r12, %r12
je .L14
movl $0, %r13d
movl $0, %ebp
leaq 48(%rsp), %rax
movq %rax, (%rsp)
.L15:
movq 24(%rbx), %rax
movl (%rax,%rbp,4), %esi
movq 48(%rbx), %rax
movl (%rax,%rbp,4), %eax
imulq %rax, %rsi
movq (%rsp), %rdi
call cudaMalloc@PLT
movq 24(%rbx), %rax
movl (%rax,%rbp,4), %edx
movq 48(%rbx), %rax
movl (%rax,%rbp,4), %eax
imulq %rax, %rdx
movq (%rbx), %rax
movq (%rax,%rbp,8), %rsi
movl $1, %ecx
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movq 48(%rsp), %rax
movq %rax, (%r15,%rbp,8)
addl $1, %r13d
movl %r13d, %ebp
movq 8(%rbx), %r12
subq (%rbx), %r12
movq %r12, %rax
sarq $3, %rax
cmpq %rax, %rbp
jb .L15
.L14:
movl $1, %ecx
movq %r12, %rdx
movq %r15, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movq 16(%rsp), %rax
movq %rax, (%r14)
movq 8(%rbx), %rax
subq (%rbx), %rax
sarq $3, %rax
movl %eax, 8(%r14)
movq 32(%rbx), %rsi
subq 24(%rbx), %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
movq 24(%rbx), %rsi
movq 32(%rbx), %rdx
subq %rsi, %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rax
movq %rax, 16(%r14)
movq 32(%rbx), %rax
subq 24(%rbx), %rax
sarq $2, %rax
movl %eax, 24(%r14)
movq 56(%rbx), %rsi
subq 48(%rbx), %rsi
leaq 32(%rsp), %rdi
call cudaMalloc@PLT
movq 48(%rbx), %rsi
movq 56(%rbx), %rdx
subq %rsi, %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movq 32(%rsp), %rax
movq %rax, 32(%r14)
movq 56(%rbx), %rax
subq 48(%rbx), %rax
sarq $2, %rax
movl %eax, 40(%r14)
movq 80(%rbx), %rsi
subq 72(%rbx), %rsi
leaq 40(%rsp), %rdi
call cudaMalloc@PLT
movq 72(%rbx), %rsi
movq 80(%rbx), %rdx
subq %rsi, %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rax
movq %rax, 48(%r14)
movq 80(%rbx), %rax
subq 72(%rbx), %rax
sarq $2, %rax
movl %eax, 56(%r14)
movq 104(%rbx), %rsi
subq 96(%rbx), %rsi
leaq 48(%rsp), %rdi
call cudaMalloc@PLT
movq 96(%rbx), %rsi
movq 104(%rbx), %rdx
subq %rsi, %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movq 48(%rsp), %rax
movq %rax, 64(%r14)
movq 104(%rbx), %rax
subq 96(%rbx), %rax
sarq $2, %rax
movl %eax, 72(%r14)
movl $1, %ecx
movl $80, %edx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2952:
.size _Z16WaveMatchesToGpuRK11WaveMatchesP14GpuWaveMatches, .-_Z16WaveMatchesToGpuRK11WaveMatchesP14GpuWaveMatches
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2978:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2978:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "constants.hip"
.globl _Z20GpuWaveMatchesToHostP14GpuWaveMatchesS0_ # -- Begin function _Z20GpuWaveMatchesToHostP14GpuWaveMatchesS0_
.p2align 4, 0x90
.type _Z20GpuWaveMatchesToHostP14GpuWaveMatchesS0_,@function
_Z20GpuWaveMatchesToHostP14GpuWaveMatchesS0_: # @_Z20GpuWaveMatchesToHostP14GpuWaveMatchesS0_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %r14
movl $80, %edi
callq malloc
movq %rax, %rbx
movl $80, %edx
movq %rax, %rdi
movq %r14, %rsi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
xorl %edi, %edi
callq fflush
movl 24(%rbx), %r15d
shlq $2, %r15
movq %r15, %rdi
callq malloc
movq %rax, %r12
leaq 16(%rbx), %rsi
movq %rax, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movq %r12, 16(%rbx)
movl $.Lstr.1, %edi
callq puts@PLT
xorl %edi, %edi
callq fflush
movl 40(%rbx), %r15d
shlq $2, %r15
movq %r15, %rdi
callq malloc
movq %rax, %r12
leaq 32(%rbx), %rsi
movq %rax, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.2, %edi
callq puts@PLT
xorl %edi, %edi
callq fflush
movq %r12, 32(%rbx)
movl 56(%rbx), %r15d
shlq $2, %r15
movq %r15, %rdi
callq malloc
movq %rax, %r12
leaq 48(%rbx), %rsi
movq %rax, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movq %r12, 48(%rbx)
movl $.Lstr.3, %edi
callq puts@PLT
xorl %edi, %edi
callq fflush
movl 72(%rbx), %r15d
shlq $2, %r15
movq %r15, %rdi
callq malloc
movq %rax, %r12
leaq 64(%rbx), %rsi
movq %rax, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movq %r12, 64(%rbx)
movl 8(%rbx), %edx
shlq $3, %rdx
movq %rbx, %rdi
movq %r14, %rsi
movl $2, %ecx
callq hipMemcpy
cmpl $0, 8(%rbx)
je .LBB0_3
# %bb.1: # %.lr.ph.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq 16(%rbx), %rax
movq 32(%rbx), %rcx
movl (%rax,%r15,4), %esi
movl (%rcx,%r15,4), %edx
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movq 16(%rbx), %rax
movq 32(%rbx), %rcx
movl (%rax,%r15,4), %eax
movl (%rcx,%r15,4), %edi
imulq %rax, %rdi
callq malloc
movq %rax, %r14
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
leaq (,%r15,8), %rsi
addq (%rbx), %rsi
movq 16(%rbx), %rax
movq 32(%rbx), %rcx
movl (%rax,%r15,4), %eax
movl (%rcx,%r15,4), %edx
imulq %rax, %rdx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movq (%rbx), %rax
movq %r14, (%rax,%r15,8)
movl $.Lstr.4, %edi
callq puts@PLT
xorl %edi, %edi
callq fflush
incq %r15
movl 8(%rbx), %eax
cmpq %rax, %r15
jb .LBB0_2
.LBB0_3: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z20GpuWaveMatchesToHostP14GpuWaveMatchesS0_, .Lfunc_end0-_Z20GpuWaveMatchesToHostP14GpuWaveMatchesS0_
.cfi_endproc
# -- End function
.globl _Z18freeGpuWaveMatchesP14GpuWaveMatches # -- Begin function _Z18freeGpuWaveMatchesP14GpuWaveMatches
.p2align 4, 0x90
.type _Z18freeGpuWaveMatchesP14GpuWaveMatches,@function
_Z18freeGpuWaveMatchesP14GpuWaveMatches: # @_Z18freeGpuWaveMatchesP14GpuWaveMatches
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl $80, %edi
callq malloc
movq %rax, %r14
movl $80, %edx
movq %rax, %rdi
movq %rbx, %rsi
movl $2, %ecx
callq hipMemcpy
cmpl $0, 8(%r14)
je .LBB1_3
# %bb.1: # %.lr.ph.preheader
xorl %r15d, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq (%r14), %rdi
addq %r15, %rdi
callq hipFree
incq %r12
movl 8(%r14), %eax
addq $8, %r15
cmpq %rax, %r12
jb .LBB1_2
.LBB1_3: # %._crit_edge
movl $.Lstr.5, %edi
callq puts@PLT
xorl %edi, %edi
callq fflush
leaq 16(%r14), %rdi
callq hipFree
leaq 32(%r14), %rdi
callq hipFree
leaq 48(%r14), %rdi
callq hipFree
movq %r14, %rdi
addq $64, %rdi
callq hipFree
movq %r14, %rdi
callq free
movq %rbx, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp hipFree # TAILCALL
.Lfunc_end1:
.size _Z18freeGpuWaveMatchesP14GpuWaveMatches, .Lfunc_end1-_Z18freeGpuWaveMatchesP14GpuWaveMatches
.cfi_endproc
# -- End function
.globl _Z16WaveMatchesToGpuRK11WaveMatchesP14GpuWaveMatches # -- Begin function _Z16WaveMatchesToGpuRK11WaveMatchesP14GpuWaveMatches
.p2align 4, 0x90
.type _Z16WaveMatchesToGpuRK11WaveMatchesP14GpuWaveMatches,@function
_Z16WaveMatchesToGpuRK11WaveMatchesP14GpuWaveMatches: # @_Z16WaveMatchesToGpuRK11WaveMatchesP14GpuWaveMatches
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $56, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
movq %rsi, 40(%rsp)
leaq 40(%rsp), %rdi
movl $80, %esi
callq hipMalloc
movl $80, %edi
callq malloc
movq %rax, 48(%rsp) # 8-byte Spill
movq 8(%rbx), %rsi
subq (%rbx), %rsi
leaq 32(%rsp), %rdi
callq hipMalloc
movq 8(%rbx), %r13
movq (%rbx), %r14
movq %r13, %rdi
subq %r14, %rdi
callq malloc
movq %rax, %r15
subq %r14, %r13
je .LBB2_3
# %bb.1: # %.lr.ph
movl $1, %ebp
xorl %r14d, %r14d
movq %rsp, %r12
.p2align 4, 0x90
.LBB2_2: # =>This Inner Loop Header: Depth=1
movq 24(%rbx), %rax
movq 48(%rbx), %rcx
movl (%rax,%r14,4), %eax
movl (%rcx,%r14,4), %esi
imulq %rax, %rsi
movq %r12, %rdi
callq hipMalloc
movq (%rsp), %rdi
movq (%rbx), %rax
movq 24(%rbx), %rcx
movq (%rax,%r14,8), %rsi
movl (%rcx,%r14,4), %eax
movq 48(%rbx), %rcx
movl (%rcx,%r14,4), %edx
imulq %rax, %rdx
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rax
movq %rax, (%r15,%r14,8)
movl %ebp, %r14d
movq 8(%rbx), %r13
subq (%rbx), %r13
movq %r13, %rax
sarq $3, %rax
incl %ebp
cmpq %r14, %rax
ja .LBB2_2
.LBB2_3: # %._crit_edge
movq 32(%rsp), %rdi
movq %r15, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rax
movq 48(%rsp), %r14 # 8-byte Reload
movq %rax, (%r14)
movq 8(%rbx), %rax
subq (%rbx), %rax
shrq $3, %rax
movl %eax, 8(%r14)
movq 32(%rbx), %rsi
subq 24(%rbx), %rsi
movq %rsp, %rdi
callq hipMalloc
movq (%rsp), %rdi
movq 24(%rbx), %rsi
movq 32(%rbx), %rdx
subq %rsi, %rdx
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rax
movq %rax, 16(%r14)
movq 32(%rbx), %rax
subq 24(%rbx), %rax
shrq $2, %rax
movl %eax, 24(%r14)
movq 56(%rbx), %rsi
subq 48(%rbx), %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
movq 24(%rsp), %rdi
movq 48(%rbx), %rsi
movq 56(%rbx), %rdx
subq %rsi, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rax
movq %rax, 32(%r14)
movq 56(%rbx), %rax
subq 48(%rbx), %rax
shrq $2, %rax
movl %eax, 40(%r14)
movq 80(%rbx), %rsi
subq 72(%rbx), %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
movq 16(%rsp), %rdi
movq 72(%rbx), %rsi
movq 80(%rbx), %rdx
subq %rsi, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rax
movq %rax, 48(%r14)
movq 80(%rbx), %rax
subq 72(%rbx), %rax
shrq $2, %rax
movl %eax, 56(%r14)
movq 104(%rbx), %rsi
subq 96(%rbx), %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
movq 8(%rsp), %rdi
movq 96(%rbx), %rsi
movq 104(%rbx), %rdx
subq %rsi, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rax
movq %rax, 64(%r14)
movq 104(%rbx), %rax
subq 96(%rbx), %rax
shrq $2, %rax
movl %eax, 72(%r14)
movq 40(%rsp), %rdi
movl $80, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z16WaveMatchesToGpuRK11WaveMatchesP14GpuWaveMatches, .Lfunc_end2-_Z16WaveMatchesToGpuRK11WaveMatchesP14GpuWaveMatches
.cfi_endproc
# -- End function
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "widths: %i , heights: %i\r\n"
.size .L.str.4, 27
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "brianIs"
.size .L.str.5, 8
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "notReal"
.size .L.str.6, 8
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "gwmth 1\r"
.size .Lstr, 9
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "gwmth 2\r"
.size .Lstr.1, 9
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "gwmth 3\r"
.size .Lstr.2, 9
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "gwmth 4\r"
.size .Lstr.3, 9
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "its a thing here\r"
.size .Lstr.4, 18
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "stuff n things\r"
.size .Lstr.5, 16
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | template<typename T>
__device__ void abs(const T* data, T* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = (T)abs((float)data[index]);
}
}
extern "C"
__global__ void abs_Boolean(const unsigned char* data, unsigned char* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = data[index];
}
}
extern "C"
__global__ void abs_Char(const unsigned short* data, unsigned short* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = data[index];
}
}
extern "C"
__global__ void abs_Double(const double* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = abs(data[index]);
}
}
template<typename T>
__device__ void acosf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = acos((float)data[index]);
}
}
template<typename T>
__device__ void acosd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = acos((double)data[index]);
}
}
template<typename T>
__device__ void acoshf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = acosh((float)data[index]);
}
}
template<typename T>
__device__ void acoshd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = acosh((double)data[index]);
}
}
template<typename T>
__device__ void asinf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = asin((float)data[index]);
}
}
template<typename T>
__device__ void asind(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = asin((double)data[index]);
}
}
template<typename T>
__device__ void asinhf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = asinh((float)data[index]);
}
}
template<typename T>
__device__ void asinhd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = asinh((double)data[index]);
}
}
template<typename T>
__device__ void atanf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = atan((float)data[index]);
}
}
template<typename T>
__device__ void atand(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = atan((double)data[index]);
}
}
template<typename T>
__device__ void atanhf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = atanh((float)data[index]);
}
}
template<typename T>
__device__ void atanhd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = atanh((double)data[index]);
}
}
template<typename T>
__device__ void cbrtf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = cbrt((float)data[index]);
}
}
template<typename T>
__device__ void cbrtd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = cbrt((double)data[index]);
}
}
template<typename T>
__device__ void ceilf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = ceil((float)data[index]);
}
}
template<typename T>
__device__ void ceild(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = ceil((double)data[index]);
}
}
template<typename T>
__device__ void cosf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = cos((float)data[index]);
}
}
template<typename T>
__device__ void cosd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = cos((double)data[index]);
}
}
template<typename T>
__device__ void coshf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = cosh((float)data[index]);
}
}
template<typename T>
__device__ void coshd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = cosh((double)data[index]);
}
}
template<typename T>
__device__ void expf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = exp((float)data[index]);
}
}
template<typename T>
__device__ void expd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = exp((double)data[index]);
}
}
template<typename T>
__device__ void exp10f(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = exp10((float)data[index]);
}
}
template<typename T>
__device__ void exp10d(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = exp10((double)data[index]);
}
}
template<typename T>
__device__ void exp2f(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = exp2((float)data[index]);
}
}
template<typename T>
__device__ void exp2d(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = exp2((double)data[index]);
}
}
template<typename T>
__device__ void floorf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = floor((float)data[index]);
}
}
template<typename T>
__device__ void floord(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = floor((double)data[index]);
}
}
template<typename T>
__device__ void lnf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = log((float)data[index]);
}
}
template<typename T>
__device__ void lnd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = log((double)data[index]);
}
}
template<typename T>
__device__ void logf(const T* data, const float base, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = log((float)data[index]) / log(base);
}
}
template<typename T>
__device__ void logd(const T* data, const double base, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = log((float)data[index]) / log(base);
}
}
template<typename T>
__device__ void log10f(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = log10((float)data[index]);
}
}
template<typename T>
__device__ void log10d(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = log10((double)data[index]);
}
}
template<typename T>
__device__ void log2f(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = log2((float)data[index]);
}
}
template<typename T>
__device__ void log2d(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = log2((double)data[index]);
}
}
template<typename T>
__device__ void max1(const T* data, const T threshold, T* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
T value = data[index];
T diff = value - threshold;
result[index] = diff > 0 ? value : threshold;
}
}
extern "C"
__global__ void max1_Float(const float* data, const float threshold, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
float value = data[index];
float diff = value - threshold;
result[index] = max(value, threshold);
}
}
extern "C"
__global__ void max1_Double(const double* data, const double threshold, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
double value = data[index];
double diff = value - threshold;
result[index] = max(value, threshold);
}
}
template<typename T>
__device__ void max(const T* data1, const T* data2, T* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
T value1 = data1[index];
T value2 = data2[index];
T diff = value1 - value2;
result[index] = diff > 0 ? value1 : value2;
}
}
extern "C"
__global__ void max_Float(const float* data1, const float* data2, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = max(data1[index], data2[index]);
}
}
extern "C"
__global__ void max_Double(const double* data1, const double* data2, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = max(data1[index], data2[index]);
}
}
template<typename T>
__device__ void min1(const T* data, const T threshold, T* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
T value = data[index];
T diff = value - threshold;
result[index] = diff < 0 ? value : threshold;
}
}
extern "C"
__global__ void min1_Float(const float* data, const float threshold, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
float value = data[index];
float diff = value - threshold;
result[index] = min(value, threshold);
}
}
extern "C"
__global__ void min1_Double(const double* data, const double threshold, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
double value = data[index];
double diff = value - threshold;
result[index] = min(value, threshold);
}
}
template<typename T>
__device__ void min(const T* data1, const T* data2, T* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
T value1 = data1[index];
T value2 = data2[index];
T diff = value1 - value2;
result[index] = diff < 0 ? value1 : value2;
}
}
extern "C"
__global__ void min_Float(const float* data1, const float* data2, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = min(data1[index], data2[index]);
}
}
extern "C"
__global__ void min_Double(const double* data1, const double* data2, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = min(data1[index], data2[index]);
}
}
template<typename T>
__device__ void powf(const T* data, const float power, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = pow((float)data[index], power);
}
}
template<typename T>
__device__ void powd(T* data, const double power, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = pow((double)data[index], power);
}
}
template<typename T>
__device__ void pow2f(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
float value = data[index];
result[index] = value * value;
}
}
template<typename T>
__device__ void pow2d(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
double value = data[index];
result[index] = value * value;
}
}
template<typename T>
__device__ void relu(const T* data, T* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
T value = data[index];
result[index] = value >= 0 ? value : 0;
}
}
extern "C"
__global__ void round_f(const float* data, int* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = round(data[index]);
}
}
extern "C"
__global__ void round_d(const double* data, long long int* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = round(data[index]);
}
}
template<typename T>
__device__ void sigmoidf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = 1.0f / (1.0f + exp(-(float)data[index]));
}
}
template<typename T>
__device__ void sigmoidd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = 1.0f / (1.0f + exp(-(double)data[index]));
}
}
template<typename T>
__device__ void sign(const T* data, int* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
T value = data[index];
result[index] = value == 0 ? 0 : (value > 0 ? 1 : -1);
}
}
template<typename T>
__device__ void sinf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = sin((float)data[index]);
}
}
template<typename T>
__device__ void sind(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = sin((double)data[index]);
}
}
template<typename T>
__device__ void sinhf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = sinh((float)data[index]);
}
}
template<typename T>
__device__ void sinhd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = sinh((double)data[index]);
}
}
template<typename T>
__device__ void sqrtf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = sqrt((float)data[index]);
}
}
template<typename T>
__device__ void sqrtd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = sqrt((double)data[index]);
}
}
template<typename T>
__device__ void tanf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = tan((float)data[index]);
}
}
template<typename T>
__device__ void tand(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = tan((double)data[index]);
}
}
template<typename T>
__device__ void tanhf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = tanh((float)data[index]);
}
}
template<typename T>
__device__ void tanhd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = tanh((double)data[index]);
}
} | .file "tmpxft_00110488_00000000-6_Math.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z11abs_BooleanPKhPhiPKhPhi
.type _Z35__device_stub__Z11abs_BooleanPKhPhiPKhPhi, @function
_Z35__device_stub__Z11abs_BooleanPKhPhiPKhPhi:
.LFB2110:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq abs_Boolean(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2110:
.size _Z35__device_stub__Z11abs_BooleanPKhPhiPKhPhi, .-_Z35__device_stub__Z11abs_BooleanPKhPhiPKhPhi
.globl abs_Boolean
.type abs_Boolean, @function
abs_Boolean:
.LFB2111:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11abs_BooleanPKhPhiPKhPhi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2111:
.size abs_Boolean, .-abs_Boolean
.globl _Z31__device_stub__Z8abs_CharPKtPtiPKtPti
.type _Z31__device_stub__Z8abs_CharPKtPtiPKtPti, @function
_Z31__device_stub__Z8abs_CharPKtPtiPKtPti:
.LFB2112:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq abs_Char(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2112:
.size _Z31__device_stub__Z8abs_CharPKtPtiPKtPti, .-_Z31__device_stub__Z8abs_CharPKtPtiPKtPti
.globl abs_Char
.type abs_Char, @function
abs_Char:
.LFB2113:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8abs_CharPKtPtiPKtPti
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2113:
.size abs_Char, .-abs_Char
.globl _Z34__device_stub__Z10abs_DoublePKdPdiPKdPdi
.type _Z34__device_stub__Z10abs_DoublePKdPdiPKdPdi, @function
_Z34__device_stub__Z10abs_DoublePKdPdiPKdPdi:
.LFB2114:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq abs_Double(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2114:
.size _Z34__device_stub__Z10abs_DoublePKdPdiPKdPdi, .-_Z34__device_stub__Z10abs_DoublePKdPdiPKdPdi
.globl abs_Double
.type abs_Double, @function
abs_Double:
.LFB2115:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10abs_DoublePKdPdiPKdPdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2115:
.size abs_Double, .-abs_Double
.globl _Z35__device_stub__Z10max1_FloatPKffPfiPKffPfi
.type _Z35__device_stub__Z10max1_FloatPKffPfiPKffPfi, @function
_Z35__device_stub__Z10max1_FloatPKffPfiPKffPfi:
.LFB2116:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movss %xmm0, 20(%rsp)
movq %rsi, 8(%rsp)
movl %edx, 16(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq max1_Float(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2116:
.size _Z35__device_stub__Z10max1_FloatPKffPfiPKffPfi, .-_Z35__device_stub__Z10max1_FloatPKffPfiPKffPfi
.globl max1_Float
.type max1_Float, @function
max1_Float:
.LFB2117:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10max1_FloatPKffPfiPKffPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2117:
.size max1_Float, .-max1_Float
.globl _Z36__device_stub__Z11max1_DoublePKddPdiPKddPdi
.type _Z36__device_stub__Z11max1_DoublePKddPdiPKddPdi, @function
_Z36__device_stub__Z11max1_DoublePKddPdiPKddPdi:
.LFB2118:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movsd %xmm0, 16(%rsp)
movq %rsi, 8(%rsp)
movl %edx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq max1_Double(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2118:
.size _Z36__device_stub__Z11max1_DoublePKddPdiPKddPdi, .-_Z36__device_stub__Z11max1_DoublePKddPdiPKddPdi
.globl max1_Double
.type max1_Double, @function
max1_Double:
.LFB2119:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z11max1_DoublePKddPdiPKddPdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2119:
.size max1_Double, .-max1_Double
.globl _Z35__device_stub__Z9max_FloatPKfS0_PfiPKfS0_Pfi
.type _Z35__device_stub__Z9max_FloatPKfS0_PfiPKfS0_Pfi, @function
_Z35__device_stub__Z9max_FloatPKfS0_PfiPKfS0_Pfi:
.LFB2120:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq max_Float(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2120:
.size _Z35__device_stub__Z9max_FloatPKfS0_PfiPKfS0_Pfi, .-_Z35__device_stub__Z9max_FloatPKfS0_PfiPKfS0_Pfi
.globl max_Float
.type max_Float, @function
max_Float:
.LFB2121:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z9max_FloatPKfS0_PfiPKfS0_Pfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2121:
.size max_Float, .-max_Float
.globl _Z37__device_stub__Z10max_DoublePKdS0_PdiPKdS0_Pdi
.type _Z37__device_stub__Z10max_DoublePKdS0_PdiPKdS0_Pdi, @function
_Z37__device_stub__Z10max_DoublePKdS0_PdiPKdS0_Pdi:
.LFB2122:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L55
.L51:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L56
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq max_Double(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L51
.L56:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2122:
.size _Z37__device_stub__Z10max_DoublePKdS0_PdiPKdS0_Pdi, .-_Z37__device_stub__Z10max_DoublePKdS0_PdiPKdS0_Pdi
.globl max_Double
.type max_Double, @function
max_Double:
.LFB2123:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z10max_DoublePKdS0_PdiPKdS0_Pdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2123:
.size max_Double, .-max_Double
.globl _Z35__device_stub__Z10min1_FloatPKffPfiPKffPfi
.type _Z35__device_stub__Z10min1_FloatPKffPfiPKffPfi, @function
_Z35__device_stub__Z10min1_FloatPKffPfiPKffPfi:
.LFB2124:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movss %xmm0, 20(%rsp)
movq %rsi, 8(%rsp)
movl %edx, 16(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L63
.L59:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L64
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L63:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq min1_Float(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L59
.L64:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2124:
.size _Z35__device_stub__Z10min1_FloatPKffPfiPKffPfi, .-_Z35__device_stub__Z10min1_FloatPKffPfiPKffPfi
.globl min1_Float
.type min1_Float, @function
min1_Float:
.LFB2125:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10min1_FloatPKffPfiPKffPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2125:
.size min1_Float, .-min1_Float
.globl _Z36__device_stub__Z11min1_DoublePKddPdiPKddPdi
.type _Z36__device_stub__Z11min1_DoublePKddPdiPKddPdi, @function
_Z36__device_stub__Z11min1_DoublePKddPdiPKddPdi:
.LFB2126:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movsd %xmm0, 16(%rsp)
movq %rsi, 8(%rsp)
movl %edx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L71
.L67:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L72
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L71:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq min1_Double(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L67
.L72:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2126:
.size _Z36__device_stub__Z11min1_DoublePKddPdiPKddPdi, .-_Z36__device_stub__Z11min1_DoublePKddPdiPKddPdi
.globl min1_Double
.type min1_Double, @function
min1_Double:
.LFB2127:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z11min1_DoublePKddPdiPKddPdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2127:
.size min1_Double, .-min1_Double
.globl _Z35__device_stub__Z9min_FloatPKfS0_PfiPKfS0_Pfi
.type _Z35__device_stub__Z9min_FloatPKfS0_PfiPKfS0_Pfi, @function
_Z35__device_stub__Z9min_FloatPKfS0_PfiPKfS0_Pfi:
.LFB2128:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L79
.L75:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L80
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L79:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq min_Float(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L75
.L80:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2128:
.size _Z35__device_stub__Z9min_FloatPKfS0_PfiPKfS0_Pfi, .-_Z35__device_stub__Z9min_FloatPKfS0_PfiPKfS0_Pfi
.globl min_Float
.type min_Float, @function
min_Float:
.LFB2129:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z9min_FloatPKfS0_PfiPKfS0_Pfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2129:
.size min_Float, .-min_Float
.globl _Z37__device_stub__Z10min_DoublePKdS0_PdiPKdS0_Pdi
.type _Z37__device_stub__Z10min_DoublePKdS0_PdiPKdS0_Pdi, @function
_Z37__device_stub__Z10min_DoublePKdS0_PdiPKdS0_Pdi:
.LFB2130:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L87
.L83:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L88
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L87:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq min_Double(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L83
.L88:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2130:
.size _Z37__device_stub__Z10min_DoublePKdS0_PdiPKdS0_Pdi, .-_Z37__device_stub__Z10min_DoublePKdS0_PdiPKdS0_Pdi
.globl min_Double
.type min_Double, @function
min_Double:
.LFB2131:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z10min_DoublePKdS0_PdiPKdS0_Pdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2131:
.size min_Double, .-min_Double
.globl _Z30__device_stub__Z7round_fPKfPiiPKfPii
.type _Z30__device_stub__Z7round_fPKfPiiPKfPii, @function
_Z30__device_stub__Z7round_fPKfPiiPKfPii:
.LFB2132:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L95
.L91:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L96
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L95:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq round_f(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L91
.L96:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2132:
.size _Z30__device_stub__Z7round_fPKfPiiPKfPii, .-_Z30__device_stub__Z7round_fPKfPiiPKfPii
.globl round_f
.type round_f, @function
round_f:
.LFB2133:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7round_fPKfPiiPKfPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2133:
.size round_f, .-round_f
.globl _Z30__device_stub__Z7round_dPKdPxiPKdPxi
.type _Z30__device_stub__Z7round_dPKdPxiPKdPxi, @function
_Z30__device_stub__Z7round_dPKdPxiPKdPxi:
.LFB2134:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L103
.L99:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L104
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L103:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq round_d(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L99
.L104:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2134:
.size _Z30__device_stub__Z7round_dPKdPxiPKdPxi, .-_Z30__device_stub__Z7round_dPKdPxiPKdPxi
.globl round_d
.type round_d, @function
round_d:
.LFB2135:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7round_dPKdPxiPKdPxi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2135:
.size round_d, .-round_d
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "round_d"
.LC1:
.string "round_f"
.LC2:
.string "min_Double"
.LC3:
.string "min_Float"
.LC4:
.string "min1_Double"
.LC5:
.string "min1_Float"
.LC6:
.string "max_Double"
.LC7:
.string "max_Float"
.LC8:
.string "max1_Double"
.LC9:
.string "max1_Float"
.LC10:
.string "abs_Double"
.LC11:
.string "abs_Char"
.LC12:
.string "abs_Boolean"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2137:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq round_d(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq round_f(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq min_Double(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq min_Float(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq min1_Double(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq min1_Float(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq max_Double(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq max_Float(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq max1_Double(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq max1_Float(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq abs_Double(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq abs_Char(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq abs_Boolean(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2137:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | template<typename T>
__device__ void abs(const T* data, T* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = (T)abs((float)data[index]);
}
}
extern "C"
__global__ void abs_Boolean(const unsigned char* data, unsigned char* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = data[index];
}
}
extern "C"
__global__ void abs_Char(const unsigned short* data, unsigned short* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = data[index];
}
}
extern "C"
__global__ void abs_Double(const double* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = abs(data[index]);
}
}
template<typename T>
__device__ void acosf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = acos((float)data[index]);
}
}
template<typename T>
__device__ void acosd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = acos((double)data[index]);
}
}
template<typename T>
__device__ void acoshf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = acosh((float)data[index]);
}
}
template<typename T>
__device__ void acoshd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = acosh((double)data[index]);
}
}
template<typename T>
__device__ void asinf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = asin((float)data[index]);
}
}
template<typename T>
__device__ void asind(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = asin((double)data[index]);
}
}
template<typename T>
__device__ void asinhf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = asinh((float)data[index]);
}
}
template<typename T>
__device__ void asinhd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = asinh((double)data[index]);
}
}
template<typename T>
__device__ void atanf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = atan((float)data[index]);
}
}
template<typename T>
__device__ void atand(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = atan((double)data[index]);
}
}
template<typename T>
__device__ void atanhf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = atanh((float)data[index]);
}
}
template<typename T>
__device__ void atanhd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = atanh((double)data[index]);
}
}
template<typename T>
__device__ void cbrtf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = cbrt((float)data[index]);
}
}
template<typename T>
__device__ void cbrtd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = cbrt((double)data[index]);
}
}
template<typename T>
__device__ void ceilf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = ceil((float)data[index]);
}
}
template<typename T>
__device__ void ceild(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = ceil((double)data[index]);
}
}
template<typename T>
__device__ void cosf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = cos((float)data[index]);
}
}
template<typename T>
__device__ void cosd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = cos((double)data[index]);
}
}
template<typename T>
__device__ void coshf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = cosh((float)data[index]);
}
}
template<typename T>
__device__ void coshd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = cosh((double)data[index]);
}
}
template<typename T>
__device__ void expf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = exp((float)data[index]);
}
}
template<typename T>
__device__ void expd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = exp((double)data[index]);
}
}
template<typename T>
__device__ void exp10f(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = exp10((float)data[index]);
}
}
template<typename T>
__device__ void exp10d(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = exp10((double)data[index]);
}
}
template<typename T>
__device__ void exp2f(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = exp2((float)data[index]);
}
}
template<typename T>
__device__ void exp2d(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = exp2((double)data[index]);
}
}
template<typename T>
__device__ void floorf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = floor((float)data[index]);
}
}
template<typename T>
__device__ void floord(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = floor((double)data[index]);
}
}
template<typename T>
__device__ void lnf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = log((float)data[index]);
}
}
template<typename T>
__device__ void lnd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = log((double)data[index]);
}
}
template<typename T>
__device__ void logf(const T* data, const float base, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = log((float)data[index]) / log(base);
}
}
template<typename T>
__device__ void logd(const T* data, const double base, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = log((float)data[index]) / log(base);
}
}
template<typename T>
__device__ void log10f(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = log10((float)data[index]);
}
}
template<typename T>
__device__ void log10d(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = log10((double)data[index]);
}
}
template<typename T>
__device__ void log2f(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = log2((float)data[index]);
}
}
template<typename T>
__device__ void log2d(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = log2((double)data[index]);
}
}
template<typename T>
__device__ void max1(const T* data, const T threshold, T* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
T value = data[index];
T diff = value - threshold;
result[index] = diff > 0 ? value : threshold;
}
}
extern "C"
__global__ void max1_Float(const float* data, const float threshold, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
float value = data[index];
float diff = value - threshold;
result[index] = max(value, threshold);
}
}
extern "C"
__global__ void max1_Double(const double* data, const double threshold, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
double value = data[index];
double diff = value - threshold;
result[index] = max(value, threshold);
}
}
template<typename T>
__device__ void max(const T* data1, const T* data2, T* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
T value1 = data1[index];
T value2 = data2[index];
T diff = value1 - value2;
result[index] = diff > 0 ? value1 : value2;
}
}
extern "C"
__global__ void max_Float(const float* data1, const float* data2, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = max(data1[index], data2[index]);
}
}
extern "C"
__global__ void max_Double(const double* data1, const double* data2, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = max(data1[index], data2[index]);
}
}
template<typename T>
__device__ void min1(const T* data, const T threshold, T* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
T value = data[index];
T diff = value - threshold;
result[index] = diff < 0 ? value : threshold;
}
}
extern "C"
__global__ void min1_Float(const float* data, const float threshold, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
float value = data[index];
float diff = value - threshold;
result[index] = min(value, threshold);
}
}
extern "C"
__global__ void min1_Double(const double* data, const double threshold, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
double value = data[index];
double diff = value - threshold;
result[index] = min(value, threshold);
}
}
template<typename T>
__device__ void min(const T* data1, const T* data2, T* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
T value1 = data1[index];
T value2 = data2[index];
T diff = value1 - value2;
result[index] = diff < 0 ? value1 : value2;
}
}
extern "C"
__global__ void min_Float(const float* data1, const float* data2, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = min(data1[index], data2[index]);
}
}
extern "C"
__global__ void min_Double(const double* data1, const double* data2, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = min(data1[index], data2[index]);
}
}
template<typename T>
__device__ void powf(const T* data, const float power, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = pow((float)data[index], power);
}
}
template<typename T>
__device__ void powd(T* data, const double power, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = pow((double)data[index], power);
}
}
template<typename T>
__device__ void pow2f(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
float value = data[index];
result[index] = value * value;
}
}
template<typename T>
__device__ void pow2d(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
double value = data[index];
result[index] = value * value;
}
}
template<typename T>
__device__ void relu(const T* data, T* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
T value = data[index];
result[index] = value >= 0 ? value : 0;
}
}
extern "C"
__global__ void round_f(const float* data, int* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = round(data[index]);
}
}
extern "C"
__global__ void round_d(const double* data, long long int* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = round(data[index]);
}
}
template<typename T>
__device__ void sigmoidf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = 1.0f / (1.0f + exp(-(float)data[index]));
}
}
template<typename T>
__device__ void sigmoidd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = 1.0f / (1.0f + exp(-(double)data[index]));
}
}
template<typename T>
__device__ void sign(const T* data, int* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
T value = data[index];
result[index] = value == 0 ? 0 : (value > 0 ? 1 : -1);
}
}
template<typename T>
__device__ void sinf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = sin((float)data[index]);
}
}
template<typename T>
__device__ void sind(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = sin((double)data[index]);
}
}
template<typename T>
__device__ void sinhf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = sinh((float)data[index]);
}
}
template<typename T>
__device__ void sinhd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = sinh((double)data[index]);
}
}
template<typename T>
__device__ void sqrtf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = sqrt((float)data[index]);
}
}
template<typename T>
__device__ void sqrtd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = sqrt((double)data[index]);
}
}
template<typename T>
__device__ void tanf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = tan((float)data[index]);
}
}
template<typename T>
__device__ void tand(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = tan((double)data[index]);
}
}
template<typename T>
__device__ void tanhf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = tanh((float)data[index]);
}
}
template<typename T>
__device__ void tanhd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = tanh((double)data[index]);
}
} | #include <hip/hip_runtime.h>
template<typename T>
__device__ void abs(const T* data, T* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = (T)abs((float)data[index]);
}
}
extern "C"
__global__ void abs_Boolean(const unsigned char* data, unsigned char* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = data[index];
}
}
extern "C"
__global__ void abs_Char(const unsigned short* data, unsigned short* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = data[index];
}
}
extern "C"
__global__ void abs_Double(const double* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = abs(data[index]);
}
}
template<typename T>
__device__ void acosf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = acos((float)data[index]);
}
}
template<typename T>
__device__ void acosd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = acos((double)data[index]);
}
}
template<typename T>
__device__ void acoshf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = acosh((float)data[index]);
}
}
template<typename T>
__device__ void acoshd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = acosh((double)data[index]);
}
}
template<typename T>
__device__ void asinf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = asin((float)data[index]);
}
}
template<typename T>
__device__ void asind(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = asin((double)data[index]);
}
}
template<typename T>
__device__ void asinhf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = asinh((float)data[index]);
}
}
template<typename T>
__device__ void asinhd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = asinh((double)data[index]);
}
}
template<typename T>
__device__ void atanf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = atan((float)data[index]);
}
}
template<typename T>
__device__ void atand(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = atan((double)data[index]);
}
}
template<typename T>
__device__ void atanhf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = atanh((float)data[index]);
}
}
template<typename T>
__device__ void atanhd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = atanh((double)data[index]);
}
}
template<typename T>
__device__ void cbrtf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = cbrt((float)data[index]);
}
}
template<typename T>
__device__ void cbrtd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = cbrt((double)data[index]);
}
}
template<typename T>
__device__ void ceilf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = ceil((float)data[index]);
}
}
template<typename T>
__device__ void ceild(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = ceil((double)data[index]);
}
}
template<typename T>
__device__ void cosf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = cos((float)data[index]);
}
}
template<typename T>
__device__ void cosd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = cos((double)data[index]);
}
}
template<typename T>
__device__ void coshf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = cosh((float)data[index]);
}
}
template<typename T>
__device__ void coshd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = cosh((double)data[index]);
}
}
template<typename T>
__device__ void expf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = exp((float)data[index]);
}
}
template<typename T>
__device__ void expd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = exp((double)data[index]);
}
}
template<typename T>
__device__ void exp10f(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = exp10((float)data[index]);
}
}
template<typename T>
__device__ void exp10d(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = exp10((double)data[index]);
}
}
template<typename T>
__device__ void exp2f(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = exp2((float)data[index]);
}
}
template<typename T>
__device__ void exp2d(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = exp2((double)data[index]);
}
}
template<typename T>
__device__ void floorf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = floor((float)data[index]);
}
}
template<typename T>
__device__ void floord(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = floor((double)data[index]);
}
}
template<typename T>
__device__ void lnf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = log((float)data[index]);
}
}
template<typename T>
__device__ void lnd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = log((double)data[index]);
}
}
template<typename T>
__device__ void logf(const T* data, const float base, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = log((float)data[index]) / log(base);
}
}
template<typename T>
__device__ void logd(const T* data, const double base, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = log((float)data[index]) / log(base);
}
}
template<typename T>
__device__ void log10f(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = log10((float)data[index]);
}
}
template<typename T>
__device__ void log10d(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = log10((double)data[index]);
}
}
template<typename T>
__device__ void log2f(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = log2((float)data[index]);
}
}
template<typename T>
__device__ void log2d(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = log2((double)data[index]);
}
}
template<typename T>
__device__ void max1(const T* data, const T threshold, T* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
T value = data[index];
T diff = value - threshold;
result[index] = diff > 0 ? value : threshold;
}
}
extern "C"
__global__ void max1_Float(const float* data, const float threshold, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
float value = data[index];
float diff = value - threshold;
result[index] = max(value, threshold);
}
}
extern "C"
__global__ void max1_Double(const double* data, const double threshold, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
double value = data[index];
double diff = value - threshold;
result[index] = max(value, threshold);
}
}
template<typename T>
__device__ void max(const T* data1, const T* data2, T* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
T value1 = data1[index];
T value2 = data2[index];
T diff = value1 - value2;
result[index] = diff > 0 ? value1 : value2;
}
}
extern "C"
__global__ void max_Float(const float* data1, const float* data2, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = max(data1[index], data2[index]);
}
}
extern "C"
__global__ void max_Double(const double* data1, const double* data2, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = max(data1[index], data2[index]);
}
}
template<typename T>
__device__ void min1(const T* data, const T threshold, T* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
T value = data[index];
T diff = value - threshold;
result[index] = diff < 0 ? value : threshold;
}
}
extern "C"
__global__ void min1_Float(const float* data, const float threshold, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
float value = data[index];
float diff = value - threshold;
result[index] = min(value, threshold);
}
}
extern "C"
__global__ void min1_Double(const double* data, const double threshold, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
double value = data[index];
double diff = value - threshold;
result[index] = min(value, threshold);
}
}
template<typename T>
__device__ void min(const T* data1, const T* data2, T* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
T value1 = data1[index];
T value2 = data2[index];
T diff = value1 - value2;
result[index] = diff < 0 ? value1 : value2;
}
}
extern "C"
__global__ void min_Float(const float* data1, const float* data2, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = min(data1[index], data2[index]);
}
}
extern "C"
__global__ void min_Double(const double* data1, const double* data2, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = min(data1[index], data2[index]);
}
}
template<typename T>
__device__ void powf(const T* data, const float power, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = pow((float)data[index], power);
}
}
template<typename T>
__device__ void powd(T* data, const double power, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = pow((double)data[index], power);
}
}
template<typename T>
__device__ void pow2f(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
float value = data[index];
result[index] = value * value;
}
}
template<typename T>
__device__ void pow2d(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
double value = data[index];
result[index] = value * value;
}
}
template<typename T>
__device__ void relu(const T* data, T* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
T value = data[index];
result[index] = value >= 0 ? value : 0;
}
}
extern "C"
__global__ void round_f(const float* data, int* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = round(data[index]);
}
}
extern "C"
__global__ void round_d(const double* data, long long int* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = round(data[index]);
}
}
template<typename T>
__device__ void sigmoidf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = 1.0f / (1.0f + exp(-(float)data[index]));
}
}
template<typename T>
__device__ void sigmoidd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = 1.0f / (1.0f + exp(-(double)data[index]));
}
}
template<typename T>
__device__ void sign(const T* data, int* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
T value = data[index];
result[index] = value == 0 ? 0 : (value > 0 ? 1 : -1);
}
}
template<typename T>
__device__ void sinf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = sin((float)data[index]);
}
}
template<typename T>
__device__ void sind(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = sin((double)data[index]);
}
}
template<typename T>
__device__ void sinhf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = sinh((float)data[index]);
}
}
template<typename T>
__device__ void sinhd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = sinh((double)data[index]);
}
}
template<typename T>
__device__ void sqrtf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = sqrt((float)data[index]);
}
}
template<typename T>
__device__ void sqrtd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = sqrt((double)data[index]);
}
}
template<typename T>
__device__ void tanf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = tan((float)data[index]);
}
}
template<typename T>
__device__ void tand(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = tan((double)data[index]);
}
}
template<typename T>
__device__ void tanhf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = tanh((float)data[index]);
}
}
template<typename T>
__device__ void tanhd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = tanh((double)data[index]);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
template<typename T>
__device__ void abs(const T* data, T* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = (T)abs((float)data[index]);
}
}
extern "C"
__global__ void abs_Boolean(const unsigned char* data, unsigned char* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = data[index];
}
}
extern "C"
__global__ void abs_Char(const unsigned short* data, unsigned short* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = data[index];
}
}
extern "C"
__global__ void abs_Double(const double* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = abs(data[index]);
}
}
template<typename T>
__device__ void acosf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = acos((float)data[index]);
}
}
template<typename T>
__device__ void acosd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = acos((double)data[index]);
}
}
template<typename T>
__device__ void acoshf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = acosh((float)data[index]);
}
}
template<typename T>
__device__ void acoshd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = acosh((double)data[index]);
}
}
template<typename T>
__device__ void asinf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = asin((float)data[index]);
}
}
template<typename T>
__device__ void asind(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = asin((double)data[index]);
}
}
template<typename T>
__device__ void asinhf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = asinh((float)data[index]);
}
}
template<typename T>
__device__ void asinhd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = asinh((double)data[index]);
}
}
template<typename T>
__device__ void atanf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = atan((float)data[index]);
}
}
template<typename T>
__device__ void atand(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = atan((double)data[index]);
}
}
template<typename T>
__device__ void atanhf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = atanh((float)data[index]);
}
}
template<typename T>
__device__ void atanhd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = atanh((double)data[index]);
}
}
template<typename T>
__device__ void cbrtf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = cbrt((float)data[index]);
}
}
template<typename T>
__device__ void cbrtd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = cbrt((double)data[index]);
}
}
template<typename T>
__device__ void ceilf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = ceil((float)data[index]);
}
}
template<typename T>
__device__ void ceild(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = ceil((double)data[index]);
}
}
template<typename T>
__device__ void cosf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = cos((float)data[index]);
}
}
template<typename T>
__device__ void cosd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = cos((double)data[index]);
}
}
template<typename T>
__device__ void coshf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = cosh((float)data[index]);
}
}
template<typename T>
__device__ void coshd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = cosh((double)data[index]);
}
}
template<typename T>
__device__ void expf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = exp((float)data[index]);
}
}
template<typename T>
__device__ void expd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = exp((double)data[index]);
}
}
template<typename T>
__device__ void exp10f(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = exp10((float)data[index]);
}
}
template<typename T>
__device__ void exp10d(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = exp10((double)data[index]);
}
}
template<typename T>
__device__ void exp2f(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = exp2((float)data[index]);
}
}
template<typename T>
__device__ void exp2d(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = exp2((double)data[index]);
}
}
template<typename T>
__device__ void floorf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = floor((float)data[index]);
}
}
template<typename T>
__device__ void floord(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = floor((double)data[index]);
}
}
template<typename T>
__device__ void lnf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = log((float)data[index]);
}
}
template<typename T>
__device__ void lnd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = log((double)data[index]);
}
}
template<typename T>
__device__ void logf(const T* data, const float base, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = log((float)data[index]) / log(base);
}
}
template<typename T>
__device__ void logd(const T* data, const double base, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = log((float)data[index]) / log(base);
}
}
template<typename T>
__device__ void log10f(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = log10((float)data[index]);
}
}
template<typename T>
__device__ void log10d(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = log10((double)data[index]);
}
}
template<typename T>
__device__ void log2f(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = log2((float)data[index]);
}
}
template<typename T>
__device__ void log2d(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = log2((double)data[index]);
}
}
template<typename T>
__device__ void max1(const T* data, const T threshold, T* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
T value = data[index];
T diff = value - threshold;
result[index] = diff > 0 ? value : threshold;
}
}
extern "C"
__global__ void max1_Float(const float* data, const float threshold, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
float value = data[index];
float diff = value - threshold;
result[index] = max(value, threshold);
}
}
extern "C"
__global__ void max1_Double(const double* data, const double threshold, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
double value = data[index];
double diff = value - threshold;
result[index] = max(value, threshold);
}
}
template<typename T>
__device__ void max(const T* data1, const T* data2, T* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
T value1 = data1[index];
T value2 = data2[index];
T diff = value1 - value2;
result[index] = diff > 0 ? value1 : value2;
}
}
extern "C"
__global__ void max_Float(const float* data1, const float* data2, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = max(data1[index], data2[index]);
}
}
extern "C"
__global__ void max_Double(const double* data1, const double* data2, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = max(data1[index], data2[index]);
}
}
template<typename T>
__device__ void min1(const T* data, const T threshold, T* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
T value = data[index];
T diff = value - threshold;
result[index] = diff < 0 ? value : threshold;
}
}
extern "C"
__global__ void min1_Float(const float* data, const float threshold, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
float value = data[index];
float diff = value - threshold;
result[index] = min(value, threshold);
}
}
extern "C"
__global__ void min1_Double(const double* data, const double threshold, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
double value = data[index];
double diff = value - threshold;
result[index] = min(value, threshold);
}
}
template<typename T>
__device__ void min(const T* data1, const T* data2, T* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
T value1 = data1[index];
T value2 = data2[index];
T diff = value1 - value2;
result[index] = diff < 0 ? value1 : value2;
}
}
extern "C"
__global__ void min_Float(const float* data1, const float* data2, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = min(data1[index], data2[index]);
}
}
extern "C"
__global__ void min_Double(const double* data1, const double* data2, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = min(data1[index], data2[index]);
}
}
template<typename T>
__device__ void powf(const T* data, const float power, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = pow((float)data[index], power);
}
}
template<typename T>
__device__ void powd(T* data, const double power, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = pow((double)data[index], power);
}
}
template<typename T>
__device__ void pow2f(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
float value = data[index];
result[index] = value * value;
}
}
template<typename T>
__device__ void pow2d(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
double value = data[index];
result[index] = value * value;
}
}
template<typename T>
__device__ void relu(const T* data, T* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
T value = data[index];
result[index] = value >= 0 ? value : 0;
}
}
extern "C"
__global__ void round_f(const float* data, int* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = round(data[index]);
}
}
extern "C"
__global__ void round_d(const double* data, long long int* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = round(data[index]);
}
}
template<typename T>
__device__ void sigmoidf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = 1.0f / (1.0f + exp(-(float)data[index]));
}
}
template<typename T>
__device__ void sigmoidd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = 1.0f / (1.0f + exp(-(double)data[index]));
}
}
template<typename T>
__device__ void sign(const T* data, int* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
T value = data[index];
result[index] = value == 0 ? 0 : (value > 0 ? 1 : -1);
}
}
template<typename T>
__device__ void sinf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = sin((float)data[index]);
}
}
template<typename T>
__device__ void sind(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = sin((double)data[index]);
}
}
template<typename T>
__device__ void sinhf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = sinh((float)data[index]);
}
}
template<typename T>
__device__ void sinhd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = sinh((double)data[index]);
}
}
template<typename T>
__device__ void sqrtf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = sqrt((float)data[index]);
}
}
template<typename T>
__device__ void sqrtd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = sqrt((double)data[index]);
}
}
template<typename T>
__device__ void tanf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = tan((float)data[index]);
}
}
template<typename T>
__device__ void tand(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = tan((double)data[index]);
}
}
template<typename T>
__device__ void tanhf(const T* data, float* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = tanh((float)data[index]);
}
}
template<typename T>
__device__ void tanhd(const T* data, double* result, const int length) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
if (index < length) {
result[index] = tanh((double)data[index]);
}
} | .text
.file "Math.hip"
.globl __device_stub__abs_Boolean # -- Begin function __device_stub__abs_Boolean
.p2align 4, 0x90
.type __device_stub__abs_Boolean,@function
__device_stub__abs_Boolean: # @__device_stub__abs_Boolean
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $abs_Boolean, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size __device_stub__abs_Boolean, .Lfunc_end0-__device_stub__abs_Boolean
.cfi_endproc
# -- End function
.globl __device_stub__abs_Char # -- Begin function __device_stub__abs_Char
.p2align 4, 0x90
.type __device_stub__abs_Char,@function
__device_stub__abs_Char: # @__device_stub__abs_Char
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $abs_Char, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size __device_stub__abs_Char, .Lfunc_end1-__device_stub__abs_Char
.cfi_endproc
# -- End function
.globl __device_stub__abs_Double # -- Begin function __device_stub__abs_Double
.p2align 4, 0x90
.type __device_stub__abs_Double,@function
__device_stub__abs_Double: # @__device_stub__abs_Double
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $abs_Double, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size __device_stub__abs_Double, .Lfunc_end2-__device_stub__abs_Double
.cfi_endproc
# -- End function
.globl __device_stub__max1_Float # -- Begin function __device_stub__max1_Float
.p2align 4, 0x90
.type __device_stub__max1_Float,@function
__device_stub__max1_Float: # @__device_stub__max1_Float
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movss %xmm0, 12(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $max1_Float, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size __device_stub__max1_Float, .Lfunc_end3-__device_stub__max1_Float
.cfi_endproc
# -- End function
.globl __device_stub__max1_Double # -- Begin function __device_stub__max1_Double
.p2align 4, 0x90
.type __device_stub__max1_Double,@function
__device_stub__max1_Double: # @__device_stub__max1_Double
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movsd %xmm0, 64(%rsp)
movq %rsi, 56(%rsp)
movl %edx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $max1_Double, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size __device_stub__max1_Double, .Lfunc_end4-__device_stub__max1_Double
.cfi_endproc
# -- End function
.globl __device_stub__max_Float # -- Begin function __device_stub__max_Float
.p2align 4, 0x90
.type __device_stub__max_Float,@function
__device_stub__max_Float: # @__device_stub__max_Float
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $max_Float, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end5:
.size __device_stub__max_Float, .Lfunc_end5-__device_stub__max_Float
.cfi_endproc
# -- End function
.globl __device_stub__max_Double # -- Begin function __device_stub__max_Double
.p2align 4, 0x90
.type __device_stub__max_Double,@function
__device_stub__max_Double: # @__device_stub__max_Double
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $max_Double, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end6:
.size __device_stub__max_Double, .Lfunc_end6-__device_stub__max_Double
.cfi_endproc
# -- End function
.globl __device_stub__min1_Float # -- Begin function __device_stub__min1_Float
.p2align 4, 0x90
.type __device_stub__min1_Float,@function
__device_stub__min1_Float: # @__device_stub__min1_Float
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movss %xmm0, 12(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $min1_Float, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end7:
.size __device_stub__min1_Float, .Lfunc_end7-__device_stub__min1_Float
.cfi_endproc
# -- End function
.globl __device_stub__min1_Double # -- Begin function __device_stub__min1_Double
.p2align 4, 0x90
.type __device_stub__min1_Double,@function
__device_stub__min1_Double: # @__device_stub__min1_Double
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movsd %xmm0, 64(%rsp)
movq %rsi, 56(%rsp)
movl %edx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $min1_Double, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end8:
.size __device_stub__min1_Double, .Lfunc_end8-__device_stub__min1_Double
.cfi_endproc
# -- End function
.globl __device_stub__min_Float # -- Begin function __device_stub__min_Float
.p2align 4, 0x90
.type __device_stub__min_Float,@function
__device_stub__min_Float: # @__device_stub__min_Float
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $min_Float, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end9:
.size __device_stub__min_Float, .Lfunc_end9-__device_stub__min_Float
.cfi_endproc
# -- End function
.globl __device_stub__min_Double # -- Begin function __device_stub__min_Double
.p2align 4, 0x90
.type __device_stub__min_Double,@function
__device_stub__min_Double: # @__device_stub__min_Double
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $min_Double, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end10:
.size __device_stub__min_Double, .Lfunc_end10-__device_stub__min_Double
.cfi_endproc
# -- End function
.globl __device_stub__round_f # -- Begin function __device_stub__round_f
.p2align 4, 0x90
.type __device_stub__round_f,@function
__device_stub__round_f: # @__device_stub__round_f
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $round_f, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end11:
.size __device_stub__round_f, .Lfunc_end11-__device_stub__round_f
.cfi_endproc
# -- End function
.globl __device_stub__round_d # -- Begin function __device_stub__round_d
.p2align 4, 0x90
.type __device_stub__round_d,@function
__device_stub__round_d: # @__device_stub__round_d
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $round_d, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end12:
.size __device_stub__round_d, .Lfunc_end12-__device_stub__round_d
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB13_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB13_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $abs_Boolean, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $abs_Char, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $abs_Double, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $max1_Float, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $max1_Double, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $max_Float, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $max_Double, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $min1_Float, %esi
movl $.L__unnamed_8, %edx
movl $.L__unnamed_8, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $min1_Double, %esi
movl $.L__unnamed_9, %edx
movl $.L__unnamed_9, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $min_Float, %esi
movl $.L__unnamed_10, %edx
movl $.L__unnamed_10, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $min_Double, %esi
movl $.L__unnamed_11, %edx
movl $.L__unnamed_11, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $round_f, %esi
movl $.L__unnamed_12, %edx
movl $.L__unnamed_12, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $round_d, %esi
movl $.L__unnamed_13, %edx
movl $.L__unnamed_13, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end13:
.size __hip_module_ctor, .Lfunc_end13-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB14_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB14_2:
retq
.Lfunc_end14:
.size __hip_module_dtor, .Lfunc_end14-__hip_module_dtor
.cfi_endproc
# -- End function
.type abs_Boolean,@object # @abs_Boolean
.section .rodata,"a",@progbits
.globl abs_Boolean
.p2align 3, 0x0
abs_Boolean:
.quad __device_stub__abs_Boolean
.size abs_Boolean, 8
.type abs_Char,@object # @abs_Char
.globl abs_Char
.p2align 3, 0x0
abs_Char:
.quad __device_stub__abs_Char
.size abs_Char, 8
.type abs_Double,@object # @abs_Double
.globl abs_Double
.p2align 3, 0x0
abs_Double:
.quad __device_stub__abs_Double
.size abs_Double, 8
.type max1_Float,@object # @max1_Float
.globl max1_Float
.p2align 3, 0x0
max1_Float:
.quad __device_stub__max1_Float
.size max1_Float, 8
.type max1_Double,@object # @max1_Double
.globl max1_Double
.p2align 3, 0x0
max1_Double:
.quad __device_stub__max1_Double
.size max1_Double, 8
.type max_Float,@object # @max_Float
.globl max_Float
.p2align 3, 0x0
max_Float:
.quad __device_stub__max_Float
.size max_Float, 8
.type max_Double,@object # @max_Double
.globl max_Double
.p2align 3, 0x0
max_Double:
.quad __device_stub__max_Double
.size max_Double, 8
.type min1_Float,@object # @min1_Float
.globl min1_Float
.p2align 3, 0x0
min1_Float:
.quad __device_stub__min1_Float
.size min1_Float, 8
.type min1_Double,@object # @min1_Double
.globl min1_Double
.p2align 3, 0x0
min1_Double:
.quad __device_stub__min1_Double
.size min1_Double, 8
.type min_Float,@object # @min_Float
.globl min_Float
.p2align 3, 0x0
min_Float:
.quad __device_stub__min_Float
.size min_Float, 8
.type min_Double,@object # @min_Double
.globl min_Double
.p2align 3, 0x0
min_Double:
.quad __device_stub__min_Double
.size min_Double, 8
.type round_f,@object # @round_f
.globl round_f
.p2align 3, 0x0
round_f:
.quad __device_stub__round_f
.size round_f, 8
.type round_d,@object # @round_d
.globl round_d
.p2align 3, 0x0
round_d:
.quad __device_stub__round_d
.size round_d, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "abs_Boolean"
.size .L__unnamed_1, 12
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "abs_Char"
.size .L__unnamed_2, 9
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "abs_Double"
.size .L__unnamed_3, 11
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "max1_Float"
.size .L__unnamed_4, 11
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "max1_Double"
.size .L__unnamed_5, 12
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "max_Float"
.size .L__unnamed_6, 10
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "max_Double"
.size .L__unnamed_7, 11
.type .L__unnamed_8,@object # @7
.L__unnamed_8:
.asciz "min1_Float"
.size .L__unnamed_8, 11
.type .L__unnamed_9,@object # @8
.L__unnamed_9:
.asciz "min1_Double"
.size .L__unnamed_9, 12
.type .L__unnamed_10,@object # @9
.L__unnamed_10:
.asciz "min_Float"
.size .L__unnamed_10, 10
.type .L__unnamed_11,@object # @10
.L__unnamed_11:
.asciz "min_Double"
.size .L__unnamed_11, 11
.type .L__unnamed_12,@object # @11
.L__unnamed_12:
.asciz "round_f"
.size .L__unnamed_12, 8
.type .L__unnamed_13,@object # @12
.L__unnamed_13:
.asciz "round_d"
.size .L__unnamed_13, 8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__abs_Boolean
.addrsig_sym __device_stub__abs_Char
.addrsig_sym __device_stub__abs_Double
.addrsig_sym __device_stub__max1_Float
.addrsig_sym __device_stub__max1_Double
.addrsig_sym __device_stub__max_Float
.addrsig_sym __device_stub__max_Double
.addrsig_sym __device_stub__min1_Float
.addrsig_sym __device_stub__min1_Double
.addrsig_sym __device_stub__min_Float
.addrsig_sym __device_stub__min_Double
.addrsig_sym __device_stub__round_f
.addrsig_sym __device_stub__round_d
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym abs_Boolean
.addrsig_sym abs_Char
.addrsig_sym abs_Double
.addrsig_sym max1_Float
.addrsig_sym max1_Double
.addrsig_sym max_Float
.addrsig_sym max_Double
.addrsig_sym min1_Float
.addrsig_sym min1_Double
.addrsig_sym min_Float
.addrsig_sym min_Double
.addrsig_sym round_f
.addrsig_sym round_d
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ double2 make_complex(double in, int evolution_type){
double2 result;
switch(evolution_type){
// No change
case 0:
result.x = in;
result.y = 0;
break;
// Im. Time evolution
case 1:
result.x = exp(-in);
result.y = 0;
break;
// Real Time evolution
case 2:
result.x = cos(-in);
result.y = sin(-in);
break;
}
return result;
}
__global__ void make_complex_kernel(double *in, int *evolution_type, double2 *out){
//int id = threadIdx.x + blockIdx.x*blockDim.x;
//out[id] = make_complex(in[id], evolution_type[id]);
for (int i = 0; i < 3; ++i){
out[i] = make_complex(in[i], evolution_type[i]);
}
} | .file "tmpxft_0010b244_00000000-6_make_complex_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12make_complexdi
.type _Z12make_complexdi, @function
_Z12make_complexdi:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z12make_complexdi, .-_Z12make_complexdi
.globl _Z50__device_stub__Z19make_complex_kernelPdPiP7double2PdPiP7double2
.type _Z50__device_stub__Z19make_complex_kernelPdPiP7double2PdPiP7double2, @function
_Z50__device_stub__Z19make_complex_kernelPdPiP7double2PdPiP7double2:
.LFB2052:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19make_complex_kernelPdPiP7double2(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z50__device_stub__Z19make_complex_kernelPdPiP7double2PdPiP7double2, .-_Z50__device_stub__Z19make_complex_kernelPdPiP7double2PdPiP7double2
.globl _Z19make_complex_kernelPdPiP7double2
.type _Z19make_complex_kernelPdPiP7double2, @function
_Z19make_complex_kernelPdPiP7double2:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z19make_complex_kernelPdPiP7double2PdPiP7double2
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z19make_complex_kernelPdPiP7double2, .-_Z19make_complex_kernelPdPiP7double2
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19make_complex_kernelPdPiP7double2"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19make_complex_kernelPdPiP7double2(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ double2 make_complex(double in, int evolution_type){
double2 result;
switch(evolution_type){
// No change
case 0:
result.x = in;
result.y = 0;
break;
// Im. Time evolution
case 1:
result.x = exp(-in);
result.y = 0;
break;
// Real Time evolution
case 2:
result.x = cos(-in);
result.y = sin(-in);
break;
}
return result;
}
__global__ void make_complex_kernel(double *in, int *evolution_type, double2 *out){
//int id = threadIdx.x + blockIdx.x*blockDim.x;
//out[id] = make_complex(in[id], evolution_type[id]);
for (int i = 0; i < 3; ++i){
out[i] = make_complex(in[i], evolution_type[i]);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ double2 make_complex(double in, int evolution_type){
double2 result;
switch(evolution_type){
// No change
case 0:
result.x = in;
result.y = 0;
break;
// Im. Time evolution
case 1:
result.x = exp(-in);
result.y = 0;
break;
// Real Time evolution
case 2:
result.x = cos(-in);
result.y = sin(-in);
break;
}
return result;
}
__global__ void make_complex_kernel(double *in, int *evolution_type, double2 *out){
//int id = threadIdx.x + blockIdx.x*blockDim.x;
//out[id] = make_complex(in[id], evolution_type[id]);
for (int i = 0; i < 3; ++i){
out[i] = make_complex(in[i], evolution_type[i]);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ double2 make_complex(double in, int evolution_type){
double2 result;
switch(evolution_type){
// No change
case 0:
result.x = in;
result.y = 0;
break;
// Im. Time evolution
case 1:
result.x = exp(-in);
result.y = 0;
break;
// Real Time evolution
case 2:
result.x = cos(-in);
result.y = sin(-in);
break;
}
return result;
}
__global__ void make_complex_kernel(double *in, int *evolution_type, double2 *out){
//int id = threadIdx.x + blockIdx.x*blockDim.x;
//out[id] = make_complex(in[id], evolution_type[id]);
for (int i = 0; i < 3; ++i){
out[i] = make_complex(in[i], evolution_type[i]);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19make_complex_kernelPdPiP15HIP_vector_typeIdLj2EE
.globl _Z19make_complex_kernelPdPiP15HIP_vector_typeIdLj2EE
.p2align 8
.type _Z19make_complex_kernelPdPiP15HIP_vector_typeIdLj2EE,@function
_Z19make_complex_kernelPdPiP15HIP_vector_typeIdLj2EE:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
v_mov_b32_e32 v16, 0
s_mov_b64 s[10:11], 0
s_mov_b32 s12, 0
s_mov_b32 s3, 0x3ff921fb
s_mov_b32 s14, 0x54442d18
s_mov_b32 s17, 0x3c91a626
s_mov_b32 s18, 0x33145c07
s_mov_b32 s21, 0x3fe45f30
s_mov_b32 s20, 0x6dc9c883
s_mov_b32 s15, 0xbff921fb
s_mov_b32 s23, 0xbc91a626
s_mov_b32 s22, 0x33145c00
s_mov_b32 s25, 0xb97b839a
s_mov_b32 s24, 0x252049c0
s_mov_b32 s27, 0x3e21eeb6
s_mov_b32 s26, 0x9037ab78
s_mov_b32 s29, 0xbda907db
s_mov_b32 s28, 0x46cc5e42
s_mov_b32 s31, 0xbe927e4f
s_mov_b32 s30, 0xa17f65f6
s_mov_b32 s35, 0x3efa01a0
s_mov_b32 s34, 0x19f4ec90
s_mov_b32 s37, 0xbf56c16c
s_mov_b32 s36, 0x16c16967
s_mov_b32 s39, 0x3fa55555
s_mov_b32 s38, 0x55555555
s_mov_b32 s41, 0xbe5ae600
s_mov_b32 s40, 0xb42fdfa7
s_mov_b32 s43, 0x3de5e0b2
s_mov_b32 s42, 0xf9a43bb8
s_mov_b32 s45, 0x3ec71de3
s_mov_b32 s44, 0x796cde01
s_mov_b32 s47, 0xbf2a01a0
s_mov_b32 s46, 0x19e83e5c
s_mov_b32 s49, 0x3f811111
s_mov_b32 s48, 0x11110bb3
s_mov_b32 s51, 0xbfc55555
s_mov_b32 s53, 0xbff71547
s_mov_b32 s52, 0x652b82fe
s_mov_b32 s55, 0xbfe62e42
s_mov_b32 s54, 0xfefa39ef
s_mov_b32 s57, 0xbc7abc9e
s_mov_b32 s56, 0x3b39803f
s_mov_b32 s59, 0x3e928af3
s_mov_b32 s58, 0xfca7ab0c
s_mov_b32 s61, 0x3e5ade15
s_mov_b32 s60, 0x6a5dcb37
s_mov_b32 s63, 0x3ec71dee
s_mov_b32 s62, 0x623fde64
s_mov_b32 s65, 0x3efa0199
s_mov_b32 s64, 0x7c89e6b0
s_mov_b32 s67, 0x3f2a01a0
s_mov_b32 s66, 0x14761f6e
s_mov_b32 s69, 0x3f56c16c
s_mov_b32 s68, 0x1852b7b0
s_mov_b32 s70, 0x11122322
s_mov_b32 s72, 0x555502a1
s_mov_b32 s75, 0x3fc55555
s_mov_b32 s74, 0x55555511
s_mov_b32 s77, 0x3fe00000
s_mov_b32 s76, 11
s_branch .LBB0_3
.LBB0_1:
v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
s_waitcnt vmcnt(0)
v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
.LBB0_2:
s_add_u32 s10, s10, 4
s_addc_u32 s11, s11, 0
s_add_u32 s4, s4, 8
s_addc_u32 s5, s5, 0
global_store_b128 v16, v[0:3], s[8:9]
s_add_u32 s8, s8, 16
s_addc_u32 s9, s9, 0
s_cmp_eq_u32 s10, 12
s_cbranch_scc1 .LBB0_23
.LBB0_3:
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s6, s10
s_addc_u32 s1, s7, s11
s_clause 0x1
global_load_b32 v0, v16, s[0:1]
global_load_b64 v[4:5], v16, s[4:5]
s_waitcnt vmcnt(1)
v_cmp_gt_i32_e32 vcc_lo, 1, v0
v_readfirstlane_b32 s33, v0
s_cbranch_vccnz .LBB0_8
s_delay_alu instid0(VALU_DEP_1)
s_cmp_lt_i32 s33, 2
s_cbranch_scc1 .LBB0_9
s_cmp_eq_u32 s33, 2
s_cbranch_scc0 .LBB0_14
s_waitcnt vmcnt(0)
v_xor_b32_e32 v1, 0x80000000, v5
v_mov_b32_e32 v0, v4
v_cmp_ngt_f64_e64 s1, 0x41d00000, |v[4:5]|
s_delay_alu instid0(VALU_DEP_2)
v_trig_preop_f64 v[12:13], |v[0:1]|, 0
v_trig_preop_f64 v[10:11], |v[0:1]|, 1
v_cmp_le_f64_e64 s0, 0x7b000000, |v[0:1]|
v_ldexp_f64 v[14:15], |v[0:1]|, 0xffffff80
v_trig_preop_f64 v[8:9], |v[0:1]|, 2
s_and_b32 s1, exec_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 vcc_lo, s1
s_cbranch_vccz .LBB0_15
v_and_b32_e32 v3, 0x7fffffff, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v2, v0, v14, s0
s_mov_b32 s19, s17
v_cndmask_b32_e64 v3, v3, v15, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mul_f64 v[6:7], v[12:13], v[2:3]
v_mul_f64 v[17:18], v[10:11], v[2:3]
v_mul_f64 v[29:30], v[8:9], v[2:3]
v_fma_f64 v[19:20], v[12:13], v[2:3], -v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[31:32], v[10:11], v[2:3], -v[17:18]
v_fma_f64 v[2:3], v[8:9], v[2:3], -v[29:30]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[21:22], v[17:18], v[19:20]
v_add_f64 v[23:24], v[21:22], -v[17:18]
v_add_f64 v[27:28], v[6:7], v[21:22]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[25:26], v[21:22], -v[23:24]
v_add_f64 v[19:20], v[19:20], -v[23:24]
v_ldexp_f64 v[23:24], v[27:28], -2
v_add_f64 v[6:7], v[27:28], -v[6:7]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_f64 v[17:18], v[17:18], -v[25:26]
v_add_f64 v[25:26], v[29:30], v[31:32]
v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[23:24]|
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[6:7], v[21:22], -v[6:7]
v_add_f64 v[17:18], v[19:20], v[17:18]
v_fract_f64_e32 v[19:20], v[23:24]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[21:22], v[25:26], v[17:18]
v_dual_cndmask_b32 v20, 0, v20 :: v_dual_cndmask_b32 v19, 0, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ldexp_f64 v[19:20], v[19:20], 2
v_add_f64 v[23:24], v[6:7], v[21:22]
v_add_f64 v[33:34], v[21:22], -v[25:26]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[27:28], v[23:24], v[19:20]
v_add_f64 v[39:40], v[21:22], -v[33:34]
v_add_f64 v[17:18], v[17:18], -v[33:34]
v_add_f64 v[6:7], v[23:24], -v[6:7]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_gt_f64_e32 vcc_lo, 0, v[27:28]
v_add_f64 v[27:28], v[25:26], -v[29:30]
v_add_f64 v[6:7], v[21:22], -v[6:7]
s_and_b32 s2, vcc_lo, exec_lo
s_cselect_b32 s13, 0x40100000, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_add_f64 v[37:38], v[25:26], -v[27:28]
v_add_f64 v[19:20], v[19:20], s[12:13]
v_add_f64 v[27:28], v[31:32], -v[27:28]
v_add_f64 v[25:26], v[25:26], -v[39:40]
v_add_f64 v[31:32], v[29:30], -v[37:38]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[35:36], v[23:24], v[19:20]
v_add_f64 v[17:18], v[17:18], v[25:26]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[27:28], v[27:28], v[31:32]
v_cvt_i32_f64_e32 v35, v[35:36]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[17:18], v[27:28], v[17:18]
v_cvt_f64_i32_e32 v[33:34], v35
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[2:3], v[2:3], v[17:18]
v_add_f64 v[19:20], v[19:20], -v[33:34]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[2:3], v[6:7], v[2:3]
v_add_f64 v[25:26], v[23:24], v[19:20]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[17:18], v[25:26], -v[19:20]
v_cmp_le_f64_e32 vcc_lo, 0.5, v[25:26]
v_add_f64 v[6:7], v[23:24], -v[17:18]
s_and_b32 s2, vcc_lo, exec_lo
s_cselect_b32 s13, 0x3ff00000, 0
v_add_co_ci_u32_e64 v17, s2, 0, v35, vcc_lo
s_mov_b32 s2, s14
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], v[6:7]
v_add_f64 v[6:7], v[25:26], -s[12:13]
v_add_f64 v[18:19], v[6:7], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f64 v[20:21], v[18:19], s[2:3]
v_add_f64 v[6:7], v[18:19], -v[6:7]
v_fma_f64 v[22:23], v[18:19], s[2:3], -v[20:21]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[2:3], v[2:3], -v[6:7]
v_fma_f64 v[6:7], v[18:19], s[18:19], v[22:23]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[2:3], s[2:3], v[6:7]
v_add_f64 v[2:3], v[20:21], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[18:19], v[2:3], -v[20:21]
v_add_f64 v[6:7], v[6:7], -v[18:19]
s_cbranch_execz .LBB0_16
s_branch .LBB0_17
.LBB0_8:
s_branch .LBB0_12
.LBB0_9:
.LBB0_10:
s_waitcnt vmcnt(0)
v_mul_f64 v[0:1], v[4:5], s[52:53]
s_mov_b32 s71, s49
s_mov_b32 s73, s39
v_cmp_ngt_f64_e32 vcc_lo, 0xc0900000, v[4:5]
v_cmp_nlt_f64_e64 s0, 0x4090cc00, v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f64_e32 v[0:1], v[0:1]
v_fma_f64 v[2:3], v[0:1], s[54:55], -v[4:5]
v_cvt_i32_f64_e32 v8, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], v[0:1], s[56:57], v[2:3]
v_fma_f64 v[6:7], v[2:3], s[60:61], s[58:59]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[2:3], v[6:7], s[62:63]
v_fma_f64 v[6:7], v[2:3], v[6:7], s[64:65]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[2:3], v[6:7], s[66:67]
v_fma_f64 v[6:7], v[2:3], v[6:7], s[68:69]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[2:3], v[6:7], s[70:71]
v_fma_f64 v[6:7], v[2:3], v[6:7], s[72:73]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[2:3], v[6:7], s[74:75]
v_fma_f64 v[6:7], v[2:3], v[6:7], s[76:77]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[2:3], v[6:7], 1.0
v_fma_f64 v[0:1], v[2:3], v[6:7], 1.0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[0:1], v[0:1], v8
v_cndmask_b32_e32 v1, 0x7ff00000, v1, vcc_lo
s_and_b32 vcc_lo, s0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mov_b32 v3, 0 :: v_dual_cndmask_b32 v0, 0, v0
v_cndmask_b32_e64 v1, 0, v1, s0
.LBB0_11:
s_cbranch_execnz .LBB0_2
.LBB0_12:
s_delay_alu instid0(VALU_DEP_1)
s_cmp_lg_u32 s33, 0
s_cbranch_scc1 .LBB0_1
s_mov_b64 s[0:1], 0
s_branch .LBB0_1
.LBB0_14:
s_branch .LBB0_22
.LBB0_15:
.LBB0_16:
v_mul_f64 v[2:3], |v[0:1]|, s[20:21]
s_mov_b32 s16, s22
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f64_e32 v[17:18], v[2:3]
v_fma_f64 v[2:3], v[17:18], s[14:15], |v[0:1]|
v_mul_f64 v[6:7], v[17:18], s[22:23]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[21:22], v[17:18], s[22:23], v[2:3]
v_add_f64 v[19:20], v[2:3], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[2:3], v[2:3], -v[19:20]
v_add_f64 v[19:20], v[19:20], -v[21:22]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[2:3], v[2:3], v[6:7]
v_fma_f64 v[6:7], v[17:18], s[16:17], v[6:7]
v_add_f64 v[2:3], v[19:20], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], -v[6:7]
v_fma_f64 v[6:7], v[17:18], s[24:25], v[2:3]
v_cvt_i32_f64_e32 v17, v[17:18]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[21:22], v[6:7]
v_add_f64 v[19:20], v[2:3], -v[21:22]
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[6:7], v[6:7], -v[19:20]
.LBB0_17:
s_mov_b32 vcc_lo, s1
s_cbranch_vccz .LBB0_19
v_and_b32_e32 v18, 0x7fffffff, v1
v_cndmask_b32_e64 v14, v0, v14, s0
s_mov_b32 s2, s14
s_mov_b32 s19, s17
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v15, v18, v15, s0
v_mul_f64 v[18:19], v[12:13], v[14:15]
v_mul_f64 v[20:21], v[10:11], v[14:15]
v_mul_f64 v[30:31], v[8:9], v[14:15]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[12:13], v[12:13], v[14:15], -v[18:19]
v_fma_f64 v[10:11], v[10:11], v[14:15], -v[20:21]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[8:9], v[8:9], v[14:15], -v[30:31]
v_add_f64 v[22:23], v[20:21], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[24:25], v[22:23], -v[20:21]
v_add_f64 v[28:29], v[18:19], v[22:23]
v_add_f64 v[26:27], v[22:23], -v[24:25]
v_add_f64 v[12:13], v[12:13], -v[24:25]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_ldexp_f64 v[24:25], v[28:29], -2
v_add_f64 v[18:19], v[28:29], -v[18:19]
v_add_f64 v[20:21], v[20:21], -v[26:27]
v_add_f64 v[26:27], v[30:31], v[10:11]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[24:25]|
v_add_f64 v[18:19], v[22:23], -v[18:19]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[12:13], v[12:13], v[20:21]
v_fract_f64_e32 v[20:21], v[24:25]
v_add_f64 v[22:23], v[26:27], v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v21, 0, v21 :: v_dual_cndmask_b32 v20, 0, v20
v_ldexp_f64 v[20:21], v[20:21], 2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[24:25], v[18:19], v[22:23]
v_add_f64 v[32:33], v[22:23], -v[26:27]
v_add_f64 v[28:29], v[24:25], v[20:21]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_add_f64 v[38:39], v[22:23], -v[32:33]
v_add_f64 v[12:13], v[12:13], -v[32:33]
v_add_f64 v[14:15], v[24:25], -v[18:19]
v_cmp_gt_f64_e32 vcc_lo, 0, v[28:29]
v_add_f64 v[28:29], v[26:27], -v[30:31]
s_and_b32 s0, vcc_lo, exec_lo
s_cselect_b32 s13, 0x40100000, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_add_f64 v[36:37], v[26:27], -v[28:29]
v_add_f64 v[20:21], v[20:21], s[12:13]
v_add_f64 v[10:11], v[10:11], -v[28:29]
v_add_f64 v[26:27], v[26:27], -v[38:39]
v_add_f64 v[28:29], v[30:31], -v[36:37]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[34:35], v[24:25], v[20:21]
v_add_f64 v[12:13], v[12:13], v[26:27]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[10:11], v[10:11], v[28:29]
v_cvt_i32_f64_e32 v34, v[34:35]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[10:11], v[10:11], v[12:13]
v_cvt_f64_i32_e32 v[32:33], v34
v_add_f64 v[12:13], v[22:23], -v[14:15]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[8:9], v[8:9], v[10:11]
v_add_f64 v[20:21], v[20:21], -v[32:33]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[8:9], v[12:13], v[8:9]
v_add_f64 v[18:19], v[24:25], v[20:21]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[10:11], v[18:19], -v[20:21]
v_cmp_le_f64_e32 vcc_lo, 0.5, v[18:19]
v_add_f64 v[10:11], v[24:25], -v[10:11]
s_and_b32 s0, vcc_lo, exec_lo
s_cselect_b32 s13, 0x3ff00000, 0
v_add_co_ci_u32_e64 v12, s0, 0, v34, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[8:9], v[8:9], v[10:11]
v_add_f64 v[10:11], v[18:19], -s[12:13]
v_add_f64 v[13:14], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f64 v[18:19], v[13:14], s[2:3]
v_add_f64 v[10:11], v[13:14], -v[10:11]
v_fma_f64 v[20:21], v[13:14], s[2:3], -v[18:19]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[8:9], v[8:9], -v[10:11]
v_fma_f64 v[10:11], v[13:14], s[18:19], v[20:21]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], v[8:9], s[2:3], v[10:11]
v_add_f64 v[8:9], v[18:19], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[13:14], v[8:9], -v[18:19]
v_add_f64 v[10:11], v[10:11], -v[13:14]
s_cbranch_execz .LBB0_20
s_branch .LBB0_21
.LBB0_19:
.LBB0_20:
v_mul_f64 v[8:9], |v[0:1]|, s[20:21]
s_mov_b32 s16, s22
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f64_e32 v[12:13], v[8:9]
v_fma_f64 v[8:9], v[12:13], s[14:15], |v[0:1]|
v_mul_f64 v[10:11], v[12:13], s[22:23]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[18:19], v[12:13], s[22:23], v[8:9]
v_add_f64 v[14:15], v[8:9], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[8:9], v[8:9], -v[14:15]
v_add_f64 v[14:15], v[14:15], -v[18:19]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[8:9], v[8:9], v[10:11]
v_fma_f64 v[10:11], v[12:13], s[16:17], v[10:11]
v_add_f64 v[8:9], v[14:15], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[8:9], v[8:9], -v[10:11]
v_fma_f64 v[10:11], v[12:13], s[24:25], v[8:9]
v_cvt_i32_f64_e32 v12, v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[8:9], v[18:19], v[10:11]
v_add_f64 v[14:15], v[8:9], -v[18:19]
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[10:11], v[10:11], -v[14:15]
.LBB0_21:
v_mul_f64 v[13:14], v[2:3], v[2:3]
v_mul_f64 v[18:19], v[8:9], v[8:9]
v_mul_f64 v[36:37], v[6:7], 0.5
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mul_f64 v[42:43], v[10:11], 0.5
s_mov_b32 s50, s38
v_cmp_class_f64_e64 s0, v[0:1], 0x1f8
v_lshlrev_b32_e32 v0, 30, v12
v_xor_b32_e32 v0, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_and_b32_e32 v0, 0x80000000, v0
v_fma_f64 v[20:21], v[13:14], s[42:43], s[40:41]
v_fma_f64 v[22:23], v[18:19], s[42:43], s[40:41]
v_mul_f64 v[26:27], v[13:14], 0.5
v_fma_f64 v[24:25], v[13:14], s[28:29], s[26:27]
v_fma_f64 v[28:29], v[18:19], s[28:29], s[26:27]
v_mul_f64 v[30:31], v[18:19], 0.5
v_mul_f64 v[38:39], v[2:3], -v[13:14]
v_mul_f64 v[44:45], v[8:9], -v[18:19]
v_fma_f64 v[20:21], v[13:14], v[20:21], s[44:45]
v_fma_f64 v[22:23], v[18:19], v[22:23], s[44:45]
v_add_f64 v[32:33], -v[26:27], 1.0
v_fma_f64 v[24:25], v[13:14], v[24:25], s[30:31]
v_fma_f64 v[28:29], v[18:19], v[28:29], s[30:31]
v_add_f64 v[34:35], -v[30:31], 1.0
v_fma_f64 v[20:21], v[13:14], v[20:21], s[46:47]
v_fma_f64 v[22:23], v[18:19], v[22:23], s[46:47]
v_add_f64 v[40:41], -v[32:33], 1.0
v_fma_f64 v[24:25], v[13:14], v[24:25], s[34:35]
v_fma_f64 v[28:29], v[18:19], v[28:29], s[34:35]
v_add_f64 v[46:47], -v[34:35], 1.0
v_fma_f64 v[20:21], v[13:14], v[20:21], s[48:49]
v_fma_f64 v[22:23], v[18:19], v[22:23], s[48:49]
v_add_f64 v[26:27], v[40:41], -v[26:27]
v_fma_f64 v[24:25], v[13:14], v[24:25], s[36:37]
v_fma_f64 v[28:29], v[18:19], v[28:29], s[36:37]
v_add_f64 v[30:31], v[46:47], -v[30:31]
v_fma_f64 v[20:21], v[38:39], v[20:21], v[36:37]
v_fma_f64 v[22:23], v[44:45], v[22:23], v[42:43]
v_fma_f64 v[26:27], v[2:3], -v[6:7], v[26:27]
v_mul_f64 v[36:37], v[13:14], v[13:14]
v_fma_f64 v[24:25], v[13:14], v[24:25], s[38:39]
v_fma_f64 v[6:7], v[13:14], v[20:21], -v[6:7]
v_mul_f64 v[13:14], v[18:19], v[18:19]
v_fma_f64 v[20:21], v[18:19], v[28:29], s[38:39]
v_fma_f64 v[28:29], v[8:9], -v[10:11], v[30:31]
v_fma_f64 v[10:11], v[18:19], v[22:23], -v[10:11]
v_fma_f64 v[18:19], v[36:37], v[24:25], v[26:27]
v_fma_f64 v[6:7], v[38:39], s[50:51], v[6:7]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[13:14], v[13:14], v[20:21], v[28:29]
v_fma_f64 v[10:11], v[44:45], s[50:51], v[10:11]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[18:19], v[32:33], v[18:19]
v_add_f64 v[2:3], v[2:3], -v[6:7]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[6:7], v[34:35], v[13:14]
v_add_f64 v[8:9], v[8:9], -v[10:11]
v_lshlrev_b32_e32 v11, 30, v17
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_xor_b32_e32 v1, 0x80000000, v3
v_and_b32_e32 v10, 1, v17
v_and_b32_e32 v3, 0x80000000, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_eq_u32_e32 vcc_lo, 0, v10
v_dual_cndmask_b32 v1, v1, v19 :: v_dual_and_b32 v10, 1, v12
v_cndmask_b32_e32 v2, v2, v18, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_u32_e64 s1, 0, v10
v_xor_b32_e32 v1, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v7, v7, v9, s1
v_cndmask_b32_e64 v6, v6, v8, s1
v_cndmask_b32_e64 v1, 0x7ff80000, v1, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_xor_b32_e32 v3, v7, v0
v_cndmask_b32_e64 v0, 0, v2, s0
v_cndmask_b32_e64 v2, 0, v6, s0
s_delay_alu instid0(VALU_DEP_3)
v_cndmask_b32_e64 v3, 0x7ff80000, v3, s0
.LBB0_22:
s_cbranch_execnz .LBB0_11
s_branch .LBB0_10
.LBB0_23:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19make_complex_kernelPdPiP15HIP_vector_typeIdLj2EE
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 48
.amdhsa_next_free_sgpr 78
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19make_complex_kernelPdPiP15HIP_vector_typeIdLj2EE, .Lfunc_end0-_Z19make_complex_kernelPdPiP15HIP_vector_typeIdLj2EE
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19make_complex_kernelPdPiP15HIP_vector_typeIdLj2EE
.private_segment_fixed_size: 0
.sgpr_count: 80
.sgpr_spill_count: 0
.symbol: _Z19make_complex_kernelPdPiP15HIP_vector_typeIdLj2EE.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 48
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ double2 make_complex(double in, int evolution_type){
double2 result;
switch(evolution_type){
// No change
case 0:
result.x = in;
result.y = 0;
break;
// Im. Time evolution
case 1:
result.x = exp(-in);
result.y = 0;
break;
// Real Time evolution
case 2:
result.x = cos(-in);
result.y = sin(-in);
break;
}
return result;
}
__global__ void make_complex_kernel(double *in, int *evolution_type, double2 *out){
//int id = threadIdx.x + blockIdx.x*blockDim.x;
//out[id] = make_complex(in[id], evolution_type[id]);
for (int i = 0; i < 3; ++i){
out[i] = make_complex(in[i], evolution_type[i]);
}
} | .text
.file "make_complex_kernel.hip"
.globl _Z34__device_stub__make_complex_kernelPdPiP15HIP_vector_typeIdLj2EE # -- Begin function _Z34__device_stub__make_complex_kernelPdPiP15HIP_vector_typeIdLj2EE
.p2align 4, 0x90
.type _Z34__device_stub__make_complex_kernelPdPiP15HIP_vector_typeIdLj2EE,@function
_Z34__device_stub__make_complex_kernelPdPiP15HIP_vector_typeIdLj2EE: # @_Z34__device_stub__make_complex_kernelPdPiP15HIP_vector_typeIdLj2EE
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19make_complex_kernelPdPiP15HIP_vector_typeIdLj2EE, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z34__device_stub__make_complex_kernelPdPiP15HIP_vector_typeIdLj2EE, .Lfunc_end0-_Z34__device_stub__make_complex_kernelPdPiP15HIP_vector_typeIdLj2EE
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19make_complex_kernelPdPiP15HIP_vector_typeIdLj2EE, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19make_complex_kernelPdPiP15HIP_vector_typeIdLj2EE,@object # @_Z19make_complex_kernelPdPiP15HIP_vector_typeIdLj2EE
.section .rodata,"a",@progbits
.globl _Z19make_complex_kernelPdPiP15HIP_vector_typeIdLj2EE
.p2align 3, 0x0
_Z19make_complex_kernelPdPiP15HIP_vector_typeIdLj2EE:
.quad _Z34__device_stub__make_complex_kernelPdPiP15HIP_vector_typeIdLj2EE
.size _Z19make_complex_kernelPdPiP15HIP_vector_typeIdLj2EE, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19make_complex_kernelPdPiP15HIP_vector_typeIdLj2EE"
.size .L__unnamed_1, 53
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__make_complex_kernelPdPiP15HIP_vector_typeIdLj2EE
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19make_complex_kernelPdPiP15HIP_vector_typeIdLj2EE
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010b244_00000000-6_make_complex_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12make_complexdi
.type _Z12make_complexdi, @function
_Z12make_complexdi:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z12make_complexdi, .-_Z12make_complexdi
.globl _Z50__device_stub__Z19make_complex_kernelPdPiP7double2PdPiP7double2
.type _Z50__device_stub__Z19make_complex_kernelPdPiP7double2PdPiP7double2, @function
_Z50__device_stub__Z19make_complex_kernelPdPiP7double2PdPiP7double2:
.LFB2052:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19make_complex_kernelPdPiP7double2(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z50__device_stub__Z19make_complex_kernelPdPiP7double2PdPiP7double2, .-_Z50__device_stub__Z19make_complex_kernelPdPiP7double2PdPiP7double2
.globl _Z19make_complex_kernelPdPiP7double2
.type _Z19make_complex_kernelPdPiP7double2, @function
_Z19make_complex_kernelPdPiP7double2:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z19make_complex_kernelPdPiP7double2PdPiP7double2
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z19make_complex_kernelPdPiP7double2, .-_Z19make_complex_kernelPdPiP7double2
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19make_complex_kernelPdPiP7double2"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19make_complex_kernelPdPiP7double2(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "make_complex_kernel.hip"
.globl _Z34__device_stub__make_complex_kernelPdPiP15HIP_vector_typeIdLj2EE # -- Begin function _Z34__device_stub__make_complex_kernelPdPiP15HIP_vector_typeIdLj2EE
.p2align 4, 0x90
.type _Z34__device_stub__make_complex_kernelPdPiP15HIP_vector_typeIdLj2EE,@function
_Z34__device_stub__make_complex_kernelPdPiP15HIP_vector_typeIdLj2EE: # @_Z34__device_stub__make_complex_kernelPdPiP15HIP_vector_typeIdLj2EE
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19make_complex_kernelPdPiP15HIP_vector_typeIdLj2EE, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z34__device_stub__make_complex_kernelPdPiP15HIP_vector_typeIdLj2EE, .Lfunc_end0-_Z34__device_stub__make_complex_kernelPdPiP15HIP_vector_typeIdLj2EE
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19make_complex_kernelPdPiP15HIP_vector_typeIdLj2EE, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19make_complex_kernelPdPiP15HIP_vector_typeIdLj2EE,@object # @_Z19make_complex_kernelPdPiP15HIP_vector_typeIdLj2EE
.section .rodata,"a",@progbits
.globl _Z19make_complex_kernelPdPiP15HIP_vector_typeIdLj2EE
.p2align 3, 0x0
_Z19make_complex_kernelPdPiP15HIP_vector_typeIdLj2EE:
.quad _Z34__device_stub__make_complex_kernelPdPiP15HIP_vector_typeIdLj2EE
.size _Z19make_complex_kernelPdPiP15HIP_vector_typeIdLj2EE, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19make_complex_kernelPdPiP15HIP_vector_typeIdLj2EE"
.size .L__unnamed_1, 53
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__make_complex_kernelPdPiP15HIP_vector_typeIdLj2EE
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19make_complex_kernelPdPiP15HIP_vector_typeIdLj2EE
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_helpers.cuh"
// limited version of checkCudaErrors from helper_cuda.h in CUDA examples
#define checkCudaErrors(val) check_cuda( (val), #val, __FILE__, __LINE__ )
void check_cuda(cudaError_t result, char const *const func, const char *const file, int const line) {
if (result) {
std::cerr << "CUDA error = " << static_cast<unsigned int>(result) << " at " <<
file << ":" << line << " '" << func << "' \n";
// Make sure we call CUDA Device Reset before exiting
cudaDeviceReset();
exit(99);
}
}
__global__
void init_rand_state(curandState* d_rand_state, int width, int height) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if((x >= width) || (y >= height)) return;
int pixel_index = x*height + y;
//Each thread gets same seed, a different sequence number, no offset
curand_init(1984, pixel_index, 0, &d_rand_state[pixel_index]);
} | code for sm_80
Function : _Z15init_rand_stateP17curandStateXORWOWii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e620000002500 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x16c], PT ; /* 0x00005b0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R5, c[0x0][0x0], R0 ; /* 0x0000000005007a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x168], P0 ; /* 0x00005a0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD R0, R0, c[0x0][0x16c], R3 ; /* 0x00005b0000007a24 */
/* 0x000fe200078e0203 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x30 ; /* 0x00000030ff077424 */
/* 0x000fe200078e00ff */
/*00d0*/ BSSY B0, 0x11e0 ; /* 0x0000110000007945 */
/* 0x000fe20003800000 */
/*00e0*/ IMAD.MOV.U32 R2, RZ, RZ, 0xe2ad815 ; /* 0x0e2ad815ff027424 */
/* 0x000fe200078e00ff */
/*00f0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0100*/ IMAD.MOV.U32 R3, RZ, RZ, 0x3b8fc912 ; /* 0x3b8fc912ff037424 */
/* 0x000fe400078e00ff */
/*0110*/ IMAD.MOV.U32 R4, RZ, RZ, 0x21a9ae18 ; /* 0x21a9ae18ff047424 */
/* 0x000fe400078e00ff */
/*0120*/ IMAD.MOV.U32 R5, RZ, RZ, -0x75bd8fc ; /* 0xf8a42704ff057424 */
/* 0x000fc400078e00ff */
/*0130*/ IMAD.WIDE R6, R0, R7, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fc800078e0207 */
/*0140*/ IMAD.MOV.U32 R8, RZ, RZ, -0x23270784 ; /* 0xdcd8f87cff087424 */
/* 0x000fe200078e00ff */
/*0150*/ STG.E.64 [R6.64], R2 ; /* 0x0000000206007986 */
/* 0x0001e2000c101b04 */
/*0160*/ IMAD.MOV.U32 R9, RZ, RZ, 0x348c3b16 ; /* 0x348c3b16ff097424 */
/* 0x000fc600078e00ff */
/*0170*/ STG.E.64 [R6.64+0x8], R4 ; /* 0x0000080406007986 */
/* 0x0001e8000c101b04 */
/*0180*/ STG.E.64 [R6.64+0x10], R8 ; /* 0x0000100806007986 */
/* 0x0001e2000c101b04 */
/*0190*/ @!P0 BRA 0x11d0 ; /* 0x0000103000008947 */
/* 0x000fea0003800000 */
/*01a0*/ SHF.R.S32.HI R12, RZ, 0x1f, R0.reuse ; /* 0x0000001fff0c7819 */
/* 0x100fe20000011400 */
/*01b0*/ IMAD.MOV.U32 R13, RZ, RZ, RZ ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e00ff */
/*01c0*/ IMAD.MOV.U32 R14, RZ, RZ, R0 ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e0000 */
/*01d0*/ IMAD.MOV.U32 R15, RZ, RZ, R12 ; /* 0x000000ffff0f7224 */
/* 0x000fc600078e000c */
/*01e0*/ LOP3.LUT P0, RZ, R14, 0x3, RZ, 0xc0, !PT ; /* 0x000000030eff7812 */
/* 0x000fe2000780c0ff */
/*01f0*/ BSSY B1, 0x1160 ; /* 0x00000f6000017945 */
/* 0x000fd80003800000 */
/*0200*/ @!P0 BRA 0x1150 ; /* 0x00000f4000008947 */
/* 0x001fea0003800000 */
/*0210*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe400078e00ff */
/*0220*/ IMAD.MOV.U32 R17, RZ, RZ, RZ ; /* 0x000000ffff117224 */
/* 0x000fe200078e00ff */
/*0230*/ CS2R R4, SRZ ; /* 0x0000000000047805 */
/* 0x001fe2000001ff00 */
/*0240*/ IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff127224 */
/* 0x000fe200078e00ff */
/*0250*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fe4000001ff00 */
/*0260*/ IMAD.MOV.U32 R9, RZ, RZ, 0x30 ; /* 0x00000030ff097424 */
/* 0x000fe400078e00ff */
/*0270*/ IMAD R11, R12, 0x30, RZ ; /* 0x000000300c0b7824 */
/* 0x000fe400078e02ff */
/*0280*/ IMAD.WIDE.U32 R8, R0, R9, c[0x0][0x160] ; /* 0x0000580000087625 */
/* 0x000fc800078e0009 */
/*0290*/ IMAD.IADD R9, R9, 0x1, R11 ; /* 0x0000000109097824 */
/* 0x000fc800078e020b */
/*02a0*/ IMAD.WIDE R10, R18, 0x4, R8 ; /* 0x00000004120a7825 */
/* 0x000fca00078e0208 */
/*02b0*/ LDG.E R19, [R10.64+0x4] ; /* 0x000004040a137981 */
/* 0x000162000c1e1900 */
/*02c0*/ SHF.R.S32.HI R8, RZ, 0x1f, R13 ; /* 0x0000001fff087819 */
/* 0x000fe2000001140d */
/*02d0*/ IMAD.MOV.U32 R20, RZ, RZ, 0xc80 ; /* 0x00000c80ff147424 */
/* 0x000fe400078e00ff */
/*02e0*/ IMAD.MOV.U32 R23, RZ, RZ, RZ ; /* 0x000000ffff177224 */
/* 0x000fe400078e00ff */
/*02f0*/ IMAD R21, R8, 0xc80, RZ ; /* 0x00000c8008157824 */
/* 0x000fe400078e02ff */
/*0300*/ IMAD.WIDE.U32 R8, R13, R20, c[0x4][0x0] ; /* 0x010000000d087625 */
/* 0x000fc800078e0014 */
/*0310*/ IMAD.IADD R21, R9, 0x1, R21 ; /* 0x0000000109157824 */
/* 0x001fe400078e0215 */
/*0320*/ IMAD.MOV.U32 R10, RZ, RZ, 0x1 ; /* 0x00000001ff0a7424 */
/* 0x000fe400078e00ff */
/*0330*/ IMAD R11, R18, 0x20, R23 ; /* 0x00000020120b7824 */
/* 0x000fe400078e0217 */
/*0340*/ IMAD.MOV.U32 R20, RZ, RZ, 0x2 ; /* 0x00000002ff147424 */
/* 0x000fe200078e00ff */
/*0350*/ SHF.L.U32 R10, R10, R23.reuse, RZ ; /* 0x000000170a0a7219 */
/* 0x080fe200000006ff */
/*0360*/ IMAD R25, R11, 0x5, RZ ; /* 0x000000050b197824 */
/* 0x000fe400078e02ff */
/*0370*/ IMAD.MOV.U32 R11, RZ, RZ, R21 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0015 */
/*0380*/ LOP3.LUT P0, RZ, R19, R10, RZ, 0xc0, !PT ; /* 0x0000000a13ff7212 */
/* 0x020fe2000780c0ff */
/*0390*/ IMAD.MOV.U32 R10, RZ, RZ, R8 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0008 */
/*03a0*/ SHF.L.U32 R20, R20, R23, RZ ; /* 0x0000001714147219 */
/* 0x000fc600000006ff */
/*03b0*/ IMAD.WIDE R10, R25, 0x4, R10 ; /* 0x00000004190a7825 */
/* 0x000fe200078e020a */
/*03c0*/ LOP3.LUT P1, RZ, R19, R20, RZ, 0xc0, !PT ; /* 0x0000001413ff7212 */
/* 0x000fc6000782c0ff */
/*03d0*/ IMAD.MOV.U32 R20, RZ, RZ, 0x4 ; /* 0x00000004ff147424 */
/* 0x000fc800078e00ff */
/*03e0*/ @P0 LDG.E R25, [R10.64+0x4] ; /* 0x000004040a190981 */
/* 0x000ea2000c1e1900 */
/*03f0*/ SHF.L.U32 R20, R20, R23, RZ ; /* 0x0000001714147219 */
/* 0x000fc600000006ff */
/*0400*/ @P0 LDG.E R24, [R10.64] ; /* 0x000000040a180981 */
/* 0x000ee2000c1e1900 */
/*0410*/ LOP3.LUT P3, RZ, R19, R20, RZ, 0xc0, !PT ; /* 0x0000001413ff7212 */
/* 0x000fc6000786c0ff */
/*0420*/ @P0 LDG.E R22, [R10.64+0x8] ; /* 0x000008040a160981 */
/* 0x000f28000c1e1900 */
/*0430*/ @P1 LDG.E R26, [R10.64+0x14] ; /* 0x000014040a1a1981 */
/* 0x000f28000c1e1900 */
/*0440*/ @P1 LDG.E R27, [R10.64+0x18] ; /* 0x000018040a1b1981 */
/* 0x000f28000c1e1900 */
/*0450*/ @P3 LDG.E R20, [R10.64+0x28] ; /* 0x000028040a143981 */
/* 0x000f22000c1e1900 */
/*0460*/ @P0 LOP3.LUT R2, R2, R25, RZ, 0x3c, !PT ; /* 0x0000001902020212 */
/* 0x004fc600078e3cff */
/*0470*/ @P0 LDG.E R25, [R10.64+0xc] ; /* 0x00000c040a190981 */
/* 0x000ea2000c1e1900 */
/*0480*/ @P0 LOP3.LUT R17, R17, R24, RZ, 0x3c, !PT ; /* 0x0000001811110212 */
/* 0x008fc600078e3cff */
/*0490*/ @P0 LDG.E R24, [R10.64+0x10] ; /* 0x000010040a180981 */
/* 0x000ee2000c1e1900 */
/*04a0*/ @P0 LOP3.LUT R3, R3, R22, RZ, 0x3c, !PT ; /* 0x0000001603030212 */
/* 0x010fc600078e3cff */
/*04b0*/ @P1 LDG.E R22, [R10.64+0x1c] ; /* 0x00001c040a161981 */
/* 0x000f22000c1e1900 */
/*04c0*/ @P1 LOP3.LUT R17, R17, R26, RZ, 0x3c, !PT ; /* 0x0000001a11111212 */
/* 0x000fc800078e3cff */
/*04d0*/ @P3 LOP3.LUT R17, R17, R20, RZ, 0x3c, !PT ; /* 0x0000001411113212 */
/* 0x000fe200078e3cff */
/*04e0*/ IMAD.MOV.U32 R20, RZ, RZ, 0x8 ; /* 0x00000008ff147424 */
/* 0x000fca00078e00ff */
/*04f0*/ SHF.L.U32 R20, R20, R23, RZ ; /* 0x0000001714147219 */
/* 0x000fc800000006ff */
/*0500*/ LOP3.LUT P2, RZ, R19, R20, RZ, 0xc0, !PT ; /* 0x0000001413ff7212 */
/* 0x000fda000784c0ff */
/*0510*/ @P2 LDG.E R20, [R10.64+0x3c] ; /* 0x00003c040a142981 */
/* 0x000f22000c1e1900 */
/*0520*/ @P1 LOP3.LUT R2, R2, R27, RZ, 0x3c, !PT ; /* 0x0000001b02021212 */
/* 0x000fc600078e3cff */
/*0530*/ @P3 LDG.E R27, [R10.64+0x2c] ; /* 0x00002c040a1b3981 */
/* 0x000f22000c1e1900 */
/*0540*/ @P0 LOP3.LUT R4, R4, R25, RZ, 0x3c, !PT ; /* 0x0000001904040212 */
/* 0x004fc600078e3cff */
/*0550*/ @P1 LDG.E R25, [R10.64+0x20] ; /* 0x000020040a191981 */
/* 0x000ea2000c1e1900 */
/*0560*/ @P0 LOP3.LUT R5, R5, R24, RZ, 0x3c, !PT ; /* 0x0000001805050212 */
/* 0x008fc600078e3cff */
/*0570*/ @P1 LDG.E R24, [R10.64+0x24] ; /* 0x000024040a181981 */
/* 0x000ee2000c1e1900 */
/*0580*/ @P1 LOP3.LUT R3, R3, R22, RZ, 0x3c, !PT ; /* 0x0000001603031212 */
/* 0x010fc600078e3cff */
/*0590*/ @P3 LDG.E R22, [R10.64+0x30] ; /* 0x000030040a163981 */
/* 0x000f22000c1e1900 */
/*05a0*/ @P2 LOP3.LUT R17, R17, R20, RZ, 0x3c, !PT ; /* 0x0000001411112212 */
/* 0x000fe200078e3cff */
/*05b0*/ IMAD.MOV.U32 R20, RZ, RZ, 0x10 ; /* 0x00000010ff147424 */
/* 0x000fca00078e00ff */
/*05c0*/ SHF.L.U32 R20, R20, R23, RZ ; /* 0x0000001714147219 */
/* 0x000fc800000006ff */
/*05d0*/ LOP3.LUT P0, RZ, R19, R20, RZ, 0xc0, !PT ; /* 0x0000001413ff7212 */
/* 0x000fda000780c0ff */
/*05e0*/ @P0 LDG.E R20, [R10.64+0x50] ; /* 0x000050040a140981 */
/* 0x000f22000c1e1900 */
/*05f0*/ @P3 LOP3.LUT R2, R2, R27, RZ, 0x3c, !PT ; /* 0x0000001b02023212 */
/* 0x000fc600078e3cff */
/*0600*/ @P2 LDG.E R27, [R10.64+0x40] ; /* 0x000040040a1b2981 */
/* 0x000f22000c1e1900 */
/*0610*/ @P1 LOP3.LUT R4, R4, R25, RZ, 0x3c, !PT ; /* 0x0000001904041212 */
/* 0x004fc600078e3cff */
/*0620*/ @P3 LDG.E R25, [R10.64+0x34] ; /* 0x000034040a193981 */
/* 0x000ea2000c1e1900 */
/*0630*/ @P1 LOP3.LUT R5, R5, R24, RZ, 0x3c, !PT ; /* 0x0000001805051212 */
/* 0x008fc600078e3cff */
/*0640*/ @P3 LDG.E R24, [R10.64+0x38] ; /* 0x000038040a183981 */
/* 0x000ee2000c1e1900 */
/*0650*/ @P3 LOP3.LUT R3, R3, R22, RZ, 0x3c, !PT ; /* 0x0000001603033212 */
/* 0x010fc600078e3cff */
/*0660*/ @P2 LDG.E R22, [R10.64+0x44] ; /* 0x000044040a162981 */
/* 0x000f22000c1e1900 */
/*0670*/ @P0 LOP3.LUT R17, R17, R20, RZ, 0x3c, !PT ; /* 0x0000001411110212 */
/* 0x000fe200078e3cff */
/*0680*/ IMAD.MOV.U32 R20, RZ, RZ, 0x20 ; /* 0x00000020ff147424 */
/* 0x000fca00078e00ff */
/*0690*/ SHF.L.U32 R20, R20, R23, RZ ; /* 0x0000001714147219 */
/* 0x000fc800000006ff */
/*06a0*/ LOP3.LUT P1, RZ, R19, R20, RZ, 0xc0, !PT ; /* 0x0000001413ff7212 */
/* 0x000fda000782c0ff */
/*06b0*/ @P1 LDG.E R20, [R10.64+0x64] ; /* 0x000064040a141981 */
/* 0x000f22000c1e1900 */
/*06c0*/ @P2 LOP3.LUT R2, R2, R27, RZ, 0x3c, !PT ; /* 0x0000001b02022212 */
/* 0x000fc600078e3cff */
/*06d0*/ @P0 LDG.E R27, [R10.64+0x54] ; /* 0x000054040a1b0981 */
/* 0x000f22000c1e1900 */
/*06e0*/ @P3 LOP3.LUT R4, R4, R25, RZ, 0x3c, !PT ; /* 0x0000001904043212 */
/* 0x004fc600078e3cff */
/*06f0*/ @P2 LDG.E R25, [R10.64+0x48] ; /* 0x000048040a192981 */
/* 0x000ea2000c1e1900 */
/*0700*/ @P3 LOP3.LUT R5, R5, R24, RZ, 0x3c, !PT ; /* 0x0000001805053212 */
/* 0x008fc600078e3cff */
/*0710*/ @P2 LDG.E R24, [R10.64+0x4c] ; /* 0x00004c040a182981 */
/* 0x000ee2000c1e1900 */
/*0720*/ @P2 LOP3.LUT R3, R3, R22, RZ, 0x3c, !PT ; /* 0x0000001603032212 */
/* 0x010fc600078e3cff */
/*0730*/ @P0 LDG.E R22, [R10.64+0x58] ; /* 0x000058040a160981 */
/* 0x000f22000c1e1900 */
/*0740*/ @P1 LOP3.LUT R17, R17, R20, RZ, 0x3c, !PT ; /* 0x0000001411111212 */
/* 0x000fe200078e3cff */
/*0750*/ IMAD.MOV.U32 R20, RZ, RZ, 0x40 ; /* 0x00000040ff147424 */
/* 0x000fca00078e00ff */
/*0760*/ SHF.L.U32 R20, R20, R23, RZ ; /* 0x0000001714147219 */
/* 0x000fc800000006ff */
/*0770*/ LOP3.LUT P3, RZ, R19, R20, RZ, 0xc0, !PT ; /* 0x0000001413ff7212 */
/* 0x000fda000786c0ff */
/*0780*/ @P3 LDG.E R20, [R10.64+0x78] ; /* 0x000078040a143981 */
/* 0x000f22000c1e1900 */
/*0790*/ @P0 LOP3.LUT R2, R2, R27, RZ, 0x3c, !PT ; /* 0x0000001b02020212 */
/* 0x000fc600078e3cff */
/*07a0*/ @P1 LDG.E R27, [R10.64+0x68] ; /* 0x000068040a1b1981 */
/* 0x000f22000c1e1900 */
/*07b0*/ @P2 LOP3.LUT R4, R4, R25, RZ, 0x3c, !PT ; /* 0x0000001904042212 */
/* 0x004fc600078e3cff */
/*07c0*/ @P0 LDG.E R25, [R10.64+0x5c] ; /* 0x00005c040a190981 */
/* 0x000ea2000c1e1900 */
/*07d0*/ @P2 LOP3.LUT R5, R5, R24, RZ, 0x3c, !PT ; /* 0x0000001805052212 */
/* 0x008fc600078e3cff */
/*07e0*/ @P0 LDG.E R24, [R10.64+0x60] ; /* 0x000060040a180981 */
/* 0x000ee2000c1e1900 */
/*07f0*/ @P0 LOP3.LUT R3, R3, R22, RZ, 0x3c, !PT ; /* 0x0000001603030212 */
/* 0x010fc600078e3cff */
/*0800*/ @P1 LDG.E R22, [R10.64+0x6c] ; /* 0x00006c040a161981 */
/* 0x000ee2000c1e1900 */
/*0810*/ @P3 LOP3.LUT R17, R17, R20, RZ, 0x3c, !PT ; /* 0x0000001411113212 */
/* 0x000fe200078e3cff */
/*0820*/ IMAD.MOV.U32 R20, RZ, RZ, 0x80 ; /* 0x00000080ff147424 */
/* 0x000fca00078e00ff */
/*0830*/ SHF.L.U32 R20, R20, R23, RZ ; /* 0x0000001714147219 */
/* 0x000fc800000006ff */
/*0840*/ LOP3.LUT P2, RZ, R19, R20, RZ, 0xc0, !PT ; /* 0x0000001413ff7212 */
/* 0x000fda000784c0ff */
/*0850*/ @P2 LDG.E R20, [R10.64+0x8c] ; /* 0x00008c040a142981 */
/* 0x000f22000c1e1900 */
/*0860*/ @P1 LOP3.LUT R2, R2, R27, RZ, 0x3c, !PT ; /* 0x0000001b02021212 */
/* 0x000fc600078e3cff */
/*0870*/ @P3 LDG.E R27, [R10.64+0x7c] ; /* 0x00007c040a1b3981 */
/* 0x000f22000c1e1900 */
/*0880*/ @P0 LOP3.LUT R4, R4, R25, RZ, 0x3c, !PT ; /* 0x0000001904040212 */
/* 0x004fc600078e3cff */
/*0890*/ @P1 LDG.E R25, [R10.64+0x70] ; /* 0x000070040a191981 */
/* 0x000ea2000c1e1900 */
/*08a0*/ @P0 LOP3.LUT R5, R5, R24, RZ, 0x3c, !PT ; /* 0x0000001805050212 */
/* 0x008fc600078e3cff */
/*08b0*/ @P1 LDG.E R24, [R10.64+0x74] ; /* 0x000074040a181981 */
/* 0x000ee2000c1e1900 */
/*08c0*/ @P1 LOP3.LUT R3, R3, R22, RZ, 0x3c, !PT ; /* 0x0000001603031212 */
/* 0x000fc600078e3cff */
/*08d0*/ @P3 LDG.E R22, [R10.64+0x80] ; /* 0x000080040a163981 */
/* 0x000ee2000c1e1900 */
/*08e0*/ @P2 LOP3.LUT R17, R17, R20, RZ, 0x3c, !PT ; /* 0x0000001411112212 */
/* 0x010fe200078e3cff */
/*08f0*/ IMAD.MOV.U32 R20, RZ, RZ, 0x100 ; /* 0x00000100ff147424 */
/* 0x000fca00078e00ff */
/*0900*/ SHF.L.U32 R20, R20, R23, RZ ; /* 0x0000001714147219 */
/* 0x000fc800000006ff */
/*0910*/ LOP3.LUT P0, RZ, R19, R20, RZ, 0xc0, !PT ; /* 0x0000001413ff7212 */
/* 0x000fda000780c0ff */
/*0920*/ @P0 LDG.E R20, [R10.64+0xa0] ; /* 0x0000a0040a140981 */
/* 0x000f22000c1e1900 */
/*0930*/ @P3 LOP3.LUT R2, R2, R27, RZ, 0x3c, !PT ; /* 0x0000001b02023212 */
/* 0x000fc600078e3cff */
/*0940*/ @P2 LDG.E R27, [R10.64+0x90] ; /* 0x000090040a1b2981 */
/* 0x000f22000c1e1900 */
/*0950*/ @P1 LOP3.LUT R4, R4, R25, RZ, 0x3c, !PT ; /* 0x0000001904041212 */
/* 0x004fc600078e3cff */
/*0960*/ @P3 LDG.E R25, [R10.64+0x84] ; /* 0x000084040a193981 */
/* 0x000ea2000c1e1900 */
/*0970*/ @P1 LOP3.LUT R5, R5, R24, RZ, 0x3c, !PT ; /* 0x0000001805051212 */
/* 0x008fc600078e3cff */
/*0980*/ @P3 LDG.E R24, [R10.64+0x88] ; /* 0x000088040a183981 */
/* 0x000ee2000c1e1900 */
/*0990*/ @P3 LOP3.LUT R3, R3, R22, RZ, 0x3c, !PT ; /* 0x0000001603033212 */
/* 0x000fc600078e3cff */
/*09a0*/ @P2 LDG.E R22, [R10.64+0x94] ; /* 0x000094040a162981 */
/* 0x000ee2000c1e1900 */
/*09b0*/ @P0 LOP3.LUT R17, R17, R20, RZ, 0x3c, !PT ; /* 0x0000001411110212 */
/* 0x010fe200078e3cff */
/*09c0*/ IMAD.MOV.U32 R20, RZ, RZ, 0x200 ; /* 0x00000200ff147424 */
/* 0x000fca00078e00ff */
/*09d0*/ SHF.L.U32 R20, R20, R23, RZ ; /* 0x0000001714147219 */
/* 0x000fc800000006ff */
/*09e0*/ LOP3.LUT P1, RZ, R19, R20, RZ, 0xc0, !PT ; /* 0x0000001413ff7212 */
/* 0x000fda000782c0ff */
/*09f0*/ @P1 LDG.E R20, [R10.64+0xb4] ; /* 0x0000b4040a141981 */
/* 0x000f22000c1e1900 */
/*0a00*/ @P2 LOP3.LUT R2, R2, R27, RZ, 0x3c, !PT ; /* 0x0000001b02022212 */
/* 0x000fc600078e3cff */
/*0a10*/ @P0 LDG.E R27, [R10.64+0xa4] ; /* 0x0000a4040a1b0981 */
/* 0x000f22000c1e1900 */
/*0a20*/ @P3 LOP3.LUT R4, R4, R25, RZ, 0x3c, !PT ; /* 0x0000001904043212 */
/* 0x004fc600078e3cff */
/*0a30*/ @P2 LDG.E R25, [R10.64+0x98] ; /* 0x000098040a192981 */
/* 0x000ea2000c1e1900 */
/*0a40*/ @P3 LOP3.LUT R5, R5, R24, RZ, 0x3c, !PT ; /* 0x0000001805053212 */
/* 0x008fc600078e3cff */
/*0a50*/ @P2 LDG.E R24, [R10.64+0x9c] ; /* 0x00009c040a182981 */
/* 0x000ee2000c1e1900 */
/*0a60*/ @P2 LOP3.LUT R3, R3, R22, RZ, 0x3c, !PT ; /* 0x0000001603032212 */
/* 0x000fc600078e3cff */
/*0a70*/ @P0 LDG.E R22, [R10.64+0xa8] ; /* 0x0000a8040a160981 */
/* 0x000ee2000c1e1900 */
/*0a80*/ @P1 LOP3.LUT R17, R17, R20, RZ, 0x3c, !PT ; /* 0x0000001411111212 */
/* 0x010fe200078e3cff */
/*0a90*/ IMAD.MOV.U32 R20, RZ, RZ, 0x400 ; /* 0x00000400ff147424 */
/* 0x000fca00078e00ff */
/*0aa0*/ SHF.L.U32 R20, R20, R23, RZ ; /* 0x0000001714147219 */
/* 0x000fc800000006ff */
/*0ab0*/ LOP3.LUT P3, RZ, R19, R20, RZ, 0xc0, !PT ; /* 0x0000001413ff7212 */
/* 0x000fda000786c0ff */
/*0ac0*/ @P3 LDG.E R20, [R10.64+0xc8] ; /* 0x0000c8040a143981 */
/* 0x000f22000c1e1900 */
/*0ad0*/ @P0 LOP3.LUT R2, R2, R27, RZ, 0x3c, !PT ; /* 0x0000001b02020212 */
/* 0x000fc600078e3cff */
/*0ae0*/ @P1 LDG.E R27, [R10.64+0xb8] ; /* 0x0000b8040a1b1981 */
/* 0x000f22000c1e1900 */
/*0af0*/ @P2 LOP3.LUT R4, R4, R25, RZ, 0x3c, !PT ; /* 0x0000001904042212 */
/* 0x004fc600078e3cff */
/*0b00*/ @P0 LDG.E R25, [R10.64+0xac] ; /* 0x0000ac040a190981 */
/* 0x000ea2000c1e1900 */
/*0b10*/ @P2 LOP3.LUT R5, R5, R24, RZ, 0x3c, !PT ; /* 0x0000001805052212 */
/* 0x008fc600078e3cff */
/*0b20*/ @P0 LDG.E R24, [R10.64+0xb0] ; /* 0x0000b0040a180981 */
/* 0x000ee2000c1e1900 */
/*0b30*/ @P0 LOP3.LUT R3, R3, R22, RZ, 0x3c, !PT ; /* 0x0000001603030212 */
/* 0x000fc600078e3cff */
/*0b40*/ @P1 LDG.E R22, [R10.64+0xbc] ; /* 0x0000bc040a161981 */
/* 0x000ee2000c1e1900 */
/*0b50*/ @P3 LOP3.LUT R17, R17, R20, RZ, 0x3c, !PT ; /* 0x0000001411113212 */
/* 0x010fe200078e3cff */
/*0b60*/ IMAD.MOV.U32 R20, RZ, RZ, 0x800 ; /* 0x00000800ff147424 */
/* 0x000fca00078e00ff */
/*0b70*/ SHF.L.U32 R20, R20, R23, RZ ; /* 0x0000001714147219 */
/* 0x000fc800000006ff */
/*0b80*/ LOP3.LUT P2, RZ, R19, R20, RZ, 0xc0, !PT ; /* 0x0000001413ff7212 */
/* 0x000fda000784c0ff */
/*0b90*/ @P2 LDG.E R20, [R10.64+0xdc] ; /* 0x0000dc040a142981 */
/* 0x000f22000c1e1900 */
/*0ba0*/ @P1 LOP3.LUT R2, R2, R27, RZ, 0x3c, !PT ; /* 0x0000001b02021212 */
/* 0x000fc600078e3cff */
/*0bb0*/ @P3 LDG.E R27, [R10.64+0xcc] ; /* 0x0000cc040a1b3981 */
/* 0x000f22000c1e1900 */
/*0bc0*/ @P0 LOP3.LUT R4, R4, R25, RZ, 0x3c, !PT ; /* 0x0000001904040212 */
/* 0x004fc600078e3cff */
/*0bd0*/ @P1 LDG.E R25, [R10.64+0xc0] ; /* 0x0000c0040a191981 */
/* 0x000ea2000c1e1900 */
/*0be0*/ @P0 LOP3.LUT R5, R5, R24, RZ, 0x3c, !PT ; /* 0x0000001805050212 */
/* 0x008fc600078e3cff */
/*0bf0*/ @P1 LDG.E R24, [R10.64+0xc4] ; /* 0x0000c4040a181981 */
/* 0x000ee2000c1e1900 */
/*0c00*/ @P1 LOP3.LUT R3, R3, R22, RZ, 0x3c, !PT ; /* 0x0000001603031212 */
/* 0x000fc600078e3cff */
/*0c10*/ @P3 LDG.E R22, [R10.64+0xd0] ; /* 0x0000d0040a163981 */
/* 0x000ee2000c1e1900 */
/*0c20*/ @P2 LOP3.LUT R17, R17, R20, RZ, 0x3c, !PT ; /* 0x0000001411112212 */
/* 0x010fe200078e3cff */
/*0c30*/ IMAD.MOV.U32 R20, RZ, RZ, 0x1000 ; /* 0x00001000ff147424 */
/* 0x000fca00078e00ff */
/*0c40*/ SHF.L.U32 R20, R20, R23, RZ ; /* 0x0000001714147219 */
/* 0x000fc800000006ff */
/*0c50*/ LOP3.LUT P0, RZ, R19, R20, RZ, 0xc0, !PT ; /* 0x0000001413ff7212 */
/* 0x000fda000780c0ff */
/*0c60*/ @P0 LDG.E R20, [R10.64+0xf0] ; /* 0x0000f0040a140981 */
/* 0x000f22000c1e1900 */
/*0c70*/ @P3 LOP3.LUT R2, R2, R27, RZ, 0x3c, !PT ; /* 0x0000001b02023212 */
/* 0x000fc600078e3cff */
/*0c80*/ @P2 LDG.E R27, [R10.64+0xe0] ; /* 0x0000e0040a1b2981 */
/* 0x000f22000c1e1900 */
/*0c90*/ @P1 LOP3.LUT R4, R4, R25, RZ, 0x3c, !PT ; /* 0x0000001904041212 */
/* 0x004fc600078e3cff */
/*0ca0*/ @P3 LDG.E R25, [R10.64+0xd4] ; /* 0x0000d4040a193981 */
/* 0x000ea2000c1e1900 */
/*0cb0*/ @P1 LOP3.LUT R5, R5, R24, RZ, 0x3c, !PT ; /* 0x0000001805051212 */
/* 0x008fc600078e3cff */
/*0cc0*/ @P3 LDG.E R24, [R10.64+0xd8] ; /* 0x0000d8040a183981 */
/* 0x000ee2000c1e1900 */
/*0cd0*/ @P3 LOP3.LUT R3, R3, R22, RZ, 0x3c, !PT ; /* 0x0000001603033212 */
/* 0x000fc600078e3cff */
/*0ce0*/ @P2 LDG.E R22, [R10.64+0xe4] ; /* 0x0000e4040a162981 */
/* 0x000ee2000c1e1900 */
/*0cf0*/ @P0 LOP3.LUT R17, R17, R20, RZ, 0x3c, !PT ; /* 0x0000001411110212 */
/* 0x010fe200078e3cff */
/*0d00*/ IMAD.MOV.U32 R20, RZ, RZ, 0x2000 ; /* 0x00002000ff147424 */
/* 0x000fca00078e00ff */
/*0d10*/ SHF.L.U32 R20, R20, R23, RZ ; /* 0x0000001714147219 */
/* 0x000fc800000006ff */
/*0d20*/ LOP3.LUT P1, RZ, R19, R20, RZ, 0xc0, !PT ; /* 0x0000001413ff7212 */
/* 0x000fda000782c0ff */
/*0d30*/ @P1 LDG.E R20, [R10.64+0x104] ; /* 0x000104040a141981 */
/* 0x000f22000c1e1900 */
/*0d40*/ @P2 LOP3.LUT R2, R2, R27, RZ, 0x3c, !PT ; /* 0x0000001b02022212 */
/* 0x000fc600078e3cff */
/*0d50*/ @P0 LDG.E R27, [R10.64+0xf4] ; /* 0x0000f4040a1b0981 */
/* 0x000f22000c1e1900 */
/*0d60*/ @P3 LOP3.LUT R4, R4, R25, RZ, 0x3c, !PT ; /* 0x0000001904043212 */
/* 0x004fc600078e3cff */
/*0d70*/ @P2 LDG.E R25, [R10.64+0xe8] ; /* 0x0000e8040a192981 */
/* 0x000ea2000c1e1900 */
/*0d80*/ @P3 LOP3.LUT R5, R5, R24, RZ, 0x3c, !PT ; /* 0x0000001805053212 */
/* 0x008fc600078e3cff */
/*0d90*/ @P2 LDG.E R24, [R10.64+0xec] ; /* 0x0000ec040a182981 */
/* 0x000ee2000c1e1900 */
/*0da0*/ @P2 LOP3.LUT R3, R3, R22, RZ, 0x3c, !PT ; /* 0x0000001603032212 */
/* 0x000fc600078e3cff */
/*0db0*/ @P0 LDG.E R22, [R10.64+0xf8] ; /* 0x0000f8040a160981 */
/* 0x000ee2000c1e1900 */
/*0dc0*/ @P1 LOP3.LUT R17, R17, R20, RZ, 0x3c, !PT ; /* 0x0000001411111212 */
/* 0x010fe200078e3cff */
/*0dd0*/ IMAD.MOV.U32 R20, RZ, RZ, 0x4000 ; /* 0x00004000ff147424 */
/* 0x000fca00078e00ff */
/*0de0*/ SHF.L.U32 R20, R20, R23, RZ ; /* 0x0000001714147219 */
/* 0x000fc800000006ff */
/*0df0*/ LOP3.LUT P3, RZ, R19, R20, RZ, 0xc0, !PT ; /* 0x0000001413ff7212 */
/* 0x000fda000786c0ff */
/*0e00*/ @P3 LDG.E R20, [R10.64+0x118] ; /* 0x000118040a143981 */
/* 0x000f22000c1e1900 */
/*0e10*/ @P0 LOP3.LUT R2, R2, R27, RZ, 0x3c, !PT ; /* 0x0000001b02020212 */
/* 0x000fc600078e3cff */
/*0e20*/ @P1 LDG.E R27, [R10.64+0x108] ; /* 0x000108040a1b1981 */
/* 0x000f22000c1e1900 */
/*0e30*/ @P2 LOP3.LUT R4, R4, R25, RZ, 0x3c, !PT ; /* 0x0000001904042212 */
/* 0x004fc600078e3cff */
/*0e40*/ @P0 LDG.E R25, [R10.64+0xfc] ; /* 0x0000fc040a190981 */
/* 0x000ea2000c1e1900 */
/*0e50*/ @P2 LOP3.LUT R5, R5, R24, RZ, 0x3c, !PT ; /* 0x0000001805052212 */
/* 0x008fc600078e3cff */
/*0e60*/ @P0 LDG.E R24, [R10.64+0x100] ; /* 0x000100040a180981 */
/* 0x000ee2000c1e1900 */
/*0e70*/ @P0 LOP3.LUT R3, R3, R22, RZ, 0x3c, !PT ; /* 0x0000001603030212 */
/* 0x000fc600078e3cff */
/*0e80*/ @P1 LDG.E R22, [R10.64+0x10c] ; /* 0x00010c040a161981 */
/* 0x000ee2000c1e1900 */
/*0e90*/ @P3 LOP3.LUT R17, R17, R20, RZ, 0x3c, !PT ; /* 0x0000001411113212 */
/* 0x010fe200078e3cff */
/*0ea0*/ IMAD.MOV.U32 R20, RZ, RZ, 0x8000 ; /* 0x00008000ff147424 */
/* 0x000fca00078e00ff */
/*0eb0*/ SHF.L.U32 R20, R20, R23, RZ ; /* 0x0000001714147219 */
/* 0x000fc800000006ff */
/*0ec0*/ LOP3.LUT P2, RZ, R19, R20, RZ, 0xc0, !PT ; /* 0x0000001413ff7212 */
/* 0x000fe4000784c0ff */
/*0ed0*/ @P1 LDG.E R20, [R10.64+0x114] ; /* 0x000114040a141981 */
/* 0x000f22000c1e1900 */
/*0ee0*/ @P1 LOP3.LUT R2, R2, R27, RZ, 0x3c, !PT ; /* 0x0000001b02021212 */
/* 0x000fc600078e3cff */
/*0ef0*/ @P3 LDG.E R27, [R10.64+0x11c] ; /* 0x00011c040a1b3981 */
/* 0x000f2e000c1e1900 */
/*0f00*/ @P2 LDG.E R29, [R10.64+0x138] ; /* 0x000138040a1d2981 */
/* 0x000f22000c1e1900 */
/*0f10*/ @P0 LOP3.LUT R4, R4, R25, RZ, 0x3c, !PT ; /* 0x0000001904040212 */
/* 0x004fc600078e3cff */
/*0f20*/ @P1 LDG.E R25, [R10.64+0x110] ; /* 0x000110040a191981 */
/* 0x000ea2000c1e1900 */
/*0f30*/ @P0 LOP3.LUT R5, R5, R24, RZ, 0x3c, !PT ; /* 0x0000001805050212 */
/* 0x008fc600078e3cff */
/*0f40*/ @P2 LDG.E R24, [R10.64+0x12c] ; /* 0x00012c040a182981 */
/* 0x000ee2000c1e1900 */
/*0f50*/ @P1 LOP3.LUT R3, R3, R22, RZ, 0x3c, !PT ; /* 0x0000001603031212 */
/* 0x000fc600078e3cff */
/*0f60*/ @P3 LDG.E R22, [R10.64+0x120] ; /* 0x000120040a163981 */
/* 0x000ee2000c1e1900 */
/*0f70*/ @P1 LOP3.LUT R5, R5, R20, RZ, 0x3c, !PT ; /* 0x0000001405051212 */
/* 0x010fc600078e3cff */
/*0f80*/ @P3 LDG.E R20, [R10.64+0x128] ; /* 0x000128040a143981 */
/* 0x000f22000c1e1900 */
/*0f90*/ @P3 LOP3.LUT R2, R2, R27, RZ, 0x3c, !PT ; /* 0x0000001b02023212 */
/* 0x000fc600078e3cff */
/*0fa0*/ @P2 LDG.E R27, [R10.64+0x130] ; /* 0x000130040a1b2981 */
/* 0x000f22000c1e1900 */
/*0fb0*/ @P1 LOP3.LUT R4, R4, R25, RZ, 0x3c, !PT ; /* 0x0000001904041212 */
/* 0x004fc600078e3cff */
/*0fc0*/ @P3 LDG.E R25, [R10.64+0x124] ; /* 0x000124040a193981 */
/* 0x000ea2000c1e1900 */
/*0fd0*/ @P2 LOP3.LUT R17, R17, R24, RZ, 0x3c, !PT ; /* 0x0000001811112212 */
/* 0x008fc600078e3cff */
/*0fe0*/ @P2 LDG.E R24, [R10.64+0x13c] ; /* 0x00013c040a182981 */
/* 0x000ee2000c1e1900 */
/*0ff0*/ @P3 LOP3.LUT R3, R3, R22, RZ, 0x3c, !PT ; /* 0x0000001603033212 */
/* 0x000fc600078e3cff */
/*1000*/ @P2 LDG.E R22, [R10.64+0x134] ; /* 0x000134040a162981 */
/* 0x000ee2000c1e1900 */
/*1010*/ IADD3 R23, R23, 0x10, RZ ; /* 0x0000001017177810 */
/* 0x000fc80007ffe0ff */
/*1020*/ ISETP.NE.AND P0, PT, R23, 0x20, PT ; /* 0x000000201700780c */
/* 0x000fe40003f05270 */
/*1030*/ @P3 LOP3.LUT R5, R5, R20, RZ, 0x3c, !PT ; /* 0x0000001405053212 */
/* 0x010fe400078e3cff */
/*1040*/ @P2 LOP3.LUT R2, R2, R27, RZ, 0x3c, !PT ; /* 0x0000001b02022212 */
/* 0x000fe400078e3cff */
/*1050*/ @P3 LOP3.LUT R4, R4, R25, RZ, 0x3c, !PT ; /* 0x0000001904043212 */
/* 0x004fc800078e3cff */
/*1060*/ @P2 LOP3.LUT R4, R4, R29, RZ, 0x3c, !PT ; /* 0x0000001d04042212 */
/* 0x000fe400078e3cff */
/*1070*/ @P2 LOP3.LUT R5, R5, R24, RZ, 0x3c, !PT ; /* 0x0000001805052212 */
/* 0x008fe400078e3cff */
/*1080*/ @P2 LOP3.LUT R3, R3, R22, RZ, 0x3c, !PT ; /* 0x0000001603032212 */
/* 0x000fe200078e3cff */
/*1090*/ @P0 BRA 0x320 ; /* 0xfffff28000000947 */
/* 0x000fea000383ffff */
/*10a0*/ IADD3 R18, R18, 0x1, RZ ; /* 0x0000000112127810 */
/* 0x000fc80007ffe0ff */
/*10b0*/ ISETP.GE.U32.AND P0, PT, R18, 0x5, PT ; /* 0x000000051200780c */
/* 0x000fda0003f06070 */
/*10c0*/ @!P0 BRA 0x260 ; /* 0xfffff19000008947 */
/* 0x000fea000383ffff */
/*10d0*/ IADD3 R16, R16, 0x1, RZ ; /* 0x0000000110107810 */
/* 0x000fe20007ffe0ff */
/*10e0*/ STG.E.64 [R6.64+0x8], R2 ; /* 0x0000080206007986 */
/* 0x0001e2000c101b04 */
/*10f0*/ LOP3.LUT R9, R14, 0x3, RZ, 0xc0, !PT ; /* 0x000000030e097812 */
/* 0x000fc600078ec0ff */
/*1100*/ STG.E.64 [R6.64+0x10], R4 ; /* 0x0000100406007986 */
/* 0x0001e2000c101b04 */
/*1110*/ ISETP.GT.U32.AND P0, PT, R9, R16, PT ; /* 0x000000100900720c */
/* 0x000fc60003f04070 */
/*1120*/ STG.E [R6.64+0x4], R17 ; /* 0x0000041106007986 */
/* 0x0001e2000c101904 */
/*1130*/ ISETP.GT.U32.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fda0003f04100 */
/*1140*/ @P0 BRA 0x220 ; /* 0xfffff0d000000947 */
/* 0x001fea000383ffff */
/*1150*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*1160*/ SHF.R.U64 R14, R14, 0x2, R15.reuse ; /* 0x000000020e0e7819 */
/* 0x100fe4000000120f */
/*1170*/ SHF.R.U32.HI R15, RZ, 0x2, R15 ; /* 0x00000002ff0f7819 */
/* 0x000fe4000001160f */
/*1180*/ ISETP.NE.U32.AND P0, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe40003f05070 */
/*1190*/ IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d7810 */
/* 0x000fe40007ffe0ff */
/*11a0*/ ISETP.NE.AND.EX P0, PT, R15, RZ, PT, P0 ; /* 0x000000ff0f00720c */
/* 0x000fda0003f05300 */
/*11b0*/ @!P0 CALL.REL.NOINC 0x11d0 ; /* 0x0000001000008944 */
/* 0x000fe20003c00000 */
/*11c0*/ BRA 0x1e0 ; /* 0xfffff01000007947 */
/* 0x000fea000383ffff */
/*11d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*11e0*/ STG.E.64 [R6.64+0x18], RZ ; /* 0x000018ff06007986 */
/* 0x000fe8000c101b04 */
/*11f0*/ STG.E [R6.64+0x20], RZ ; /* 0x000020ff06007986 */
/* 0x000fe8000c101904 */
/*1200*/ STG.E.64 [R6.64+0x28], RZ ; /* 0x000028ff06007986 */
/* 0x000fe2000c101b04 */
/*1210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*1220*/ BRA 0x1220; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_helpers.cuh"
// limited version of checkCudaErrors from helper_cuda.h in CUDA examples
#define checkCudaErrors(val) check_cuda( (val), #val, __FILE__, __LINE__ )
void check_cuda(cudaError_t result, char const *const func, const char *const file, int const line) {
if (result) {
std::cerr << "CUDA error = " << static_cast<unsigned int>(result) << " at " <<
file << ":" << line << " '" << func << "' \n";
// Make sure we call CUDA Device Reset before exiting
cudaDeviceReset();
exit(99);
}
}
__global__
void init_rand_state(curandState* d_rand_state, int width, int height) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if((x >= width) || (y >= height)) return;
int pixel_index = x*height + y;
//Each thread gets same seed, a different sequence number, no offset
curand_init(1984, pixel_index, 0, &d_rand_state[pixel_index]);
} | .file "tmpxft_0008b20d_00000000-6_cuda_helpers.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3886:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3886:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA error = "
.LC1:
.string " at "
.LC2:
.string ":"
.LC3:
.string " '"
.LC4:
.string "' \n"
.text
.globl _Z10check_cuda9cudaErrorPKcS1_i
.type _Z10check_cuda9cudaErrorPKcS1_i, @function
_Z10check_cuda9cudaErrorPKcS1_i:
.LFB3883:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L8
ret
.L8:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %rbp
movq %rdx, %r13
movl %ecx, %r12d
leaq .LC0(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r13, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r12d, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
call cudaDeviceReset@PLT
movl $99, %edi
call exit@PLT
.cfi_endproc
.LFE3883:
.size _Z10check_cuda9cudaErrorPKcS1_i, .-_Z10check_cuda9cudaErrorPKcS1_i
.globl _Z55__device_stub__Z15init_rand_stateP17curandStateXORWOWiiP17curandStateXORWOWii
.type _Z55__device_stub__Z15init_rand_stateP17curandStateXORWOWiiP17curandStateXORWOWii, @function
_Z55__device_stub__Z15init_rand_stateP17curandStateXORWOWiiP17curandStateXORWOWii:
.LFB3908:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15init_rand_stateP17curandStateXORWOWii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3908:
.size _Z55__device_stub__Z15init_rand_stateP17curandStateXORWOWiiP17curandStateXORWOWii, .-_Z55__device_stub__Z15init_rand_stateP17curandStateXORWOWiiP17curandStateXORWOWii
.globl _Z15init_rand_stateP17curandStateXORWOWii
.type _Z15init_rand_stateP17curandStateXORWOWii, @function
_Z15init_rand_stateP17curandStateXORWOWii:
.LFB3909:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z55__device_stub__Z15init_rand_stateP17curandStateXORWOWiiP17curandStateXORWOWii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3909:
.size _Z15init_rand_stateP17curandStateXORWOWii, .-_Z15init_rand_stateP17curandStateXORWOWii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "_Z15init_rand_stateP17curandStateXORWOWii"
.section .rodata.str1.1
.LC6:
.string "precalc_xorwow_matrix"
.LC7:
.string "precalc_xorwow_offset_matrix"
.LC8:
.string "mrg32k3aM1"
.LC9:
.string "mrg32k3aM2"
.LC10:
.string "mrg32k3aM1SubSeq"
.LC11:
.string "mrg32k3aM2SubSeq"
.LC12:
.string "mrg32k3aM1Seq"
.LC13:
.string "mrg32k3aM2Seq"
.LC14:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3911:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z15init_rand_stateP17curandStateXORWOWii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3911:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_helpers.cuh"
// limited version of checkCudaErrors from helper_cuda.h in CUDA examples
#define checkCudaErrors(val) check_cuda( (val), #val, __FILE__, __LINE__ )
void check_cuda(cudaError_t result, char const *const func, const char *const file, int const line) {
if (result) {
std::cerr << "CUDA error = " << static_cast<unsigned int>(result) << " at " <<
file << ":" << line << " '" << func << "' \n";
// Make sure we call CUDA Device Reset before exiting
cudaDeviceReset();
exit(99);
}
}
__global__
void init_rand_state(curandState* d_rand_state, int width, int height) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if((x >= width) || (y >= height)) return;
int pixel_index = x*height + y;
//Each thread gets same seed, a different sequence number, no offset
curand_init(1984, pixel_index, 0, &d_rand_state[pixel_index]);
} | #ifndef CUDA_HELPERS_H
#define CUDA_HELPERS_H
#include <iostream>
//cuRand
#include <hiprand/hiprand_kernel.h>
#include <hiprand/hiprand.h>
#define checkCudaErrors(val) check_cuda( (val), #val, __FILE__, __LINE__ )
void check_cuda(hipError_t result, char const *const func, const char *const file, int const line);
__global__
void init_rand_state(hiprandState* d_rand_state, int width, int height);
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #ifndef CUDA_HELPERS_H
#define CUDA_HELPERS_H
#include <iostream>
//cuRand
#include <hiprand/hiprand_kernel.h>
#include <hiprand/hiprand.h>
#define checkCudaErrors(val) check_cuda( (val), #val, __FILE__, __LINE__ )
void check_cuda(hipError_t result, char const *const func, const char *const file, int const line);
__global__
void init_rand_state(hiprandState* d_rand_state, int width, int height);
#endif | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #ifndef CUDA_HELPERS_H
#define CUDA_HELPERS_H
#include <iostream>
//cuRand
#include <hiprand/hiprand_kernel.h>
#include <hiprand/hiprand.h>
#define checkCudaErrors(val) check_cuda( (val), #val, __FILE__, __LINE__ )
void check_cuda(hipError_t result, char const *const func, const char *const file, int const line);
__global__
void init_rand_state(hiprandState* d_rand_state, int width, int height);
#endif | .text
.file "cuda_helpers.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15init_rand_stateP17curandStateXORWOWii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e620000002500 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x16c], PT ; /* 0x00005b0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R5, c[0x0][0x0], R0 ; /* 0x0000000005007a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x168], P0 ; /* 0x00005a0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD R0, R0, c[0x0][0x16c], R3 ; /* 0x00005b0000007a24 */
/* 0x000fe200078e0203 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x30 ; /* 0x00000030ff077424 */
/* 0x000fe200078e00ff */
/*00d0*/ BSSY B0, 0x11e0 ; /* 0x0000110000007945 */
/* 0x000fe20003800000 */
/*00e0*/ IMAD.MOV.U32 R2, RZ, RZ, 0xe2ad815 ; /* 0x0e2ad815ff027424 */
/* 0x000fe200078e00ff */
/*00f0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0100*/ IMAD.MOV.U32 R3, RZ, RZ, 0x3b8fc912 ; /* 0x3b8fc912ff037424 */
/* 0x000fe400078e00ff */
/*0110*/ IMAD.MOV.U32 R4, RZ, RZ, 0x21a9ae18 ; /* 0x21a9ae18ff047424 */
/* 0x000fe400078e00ff */
/*0120*/ IMAD.MOV.U32 R5, RZ, RZ, -0x75bd8fc ; /* 0xf8a42704ff057424 */
/* 0x000fc400078e00ff */
/*0130*/ IMAD.WIDE R6, R0, R7, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fc800078e0207 */
/*0140*/ IMAD.MOV.U32 R8, RZ, RZ, -0x23270784 ; /* 0xdcd8f87cff087424 */
/* 0x000fe200078e00ff */
/*0150*/ STG.E.64 [R6.64], R2 ; /* 0x0000000206007986 */
/* 0x0001e2000c101b04 */
/*0160*/ IMAD.MOV.U32 R9, RZ, RZ, 0x348c3b16 ; /* 0x348c3b16ff097424 */
/* 0x000fc600078e00ff */
/*0170*/ STG.E.64 [R6.64+0x8], R4 ; /* 0x0000080406007986 */
/* 0x0001e8000c101b04 */
/*0180*/ STG.E.64 [R6.64+0x10], R8 ; /* 0x0000100806007986 */
/* 0x0001e2000c101b04 */
/*0190*/ @!P0 BRA 0x11d0 ; /* 0x0000103000008947 */
/* 0x000fea0003800000 */
/*01a0*/ SHF.R.S32.HI R12, RZ, 0x1f, R0.reuse ; /* 0x0000001fff0c7819 */
/* 0x100fe20000011400 */
/*01b0*/ IMAD.MOV.U32 R13, RZ, RZ, RZ ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e00ff */
/*01c0*/ IMAD.MOV.U32 R14, RZ, RZ, R0 ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e0000 */
/*01d0*/ IMAD.MOV.U32 R15, RZ, RZ, R12 ; /* 0x000000ffff0f7224 */
/* 0x000fc600078e000c */
/*01e0*/ LOP3.LUT P0, RZ, R14, 0x3, RZ, 0xc0, !PT ; /* 0x000000030eff7812 */
/* 0x000fe2000780c0ff */
/*01f0*/ BSSY B1, 0x1160 ; /* 0x00000f6000017945 */
/* 0x000fd80003800000 */
/*0200*/ @!P0 BRA 0x1150 ; /* 0x00000f4000008947 */
/* 0x001fea0003800000 */
/*0210*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe400078e00ff */
/*0220*/ IMAD.MOV.U32 R17, RZ, RZ, RZ ; /* 0x000000ffff117224 */
/* 0x000fe200078e00ff */
/*0230*/ CS2R R4, SRZ ; /* 0x0000000000047805 */
/* 0x001fe2000001ff00 */
/*0240*/ IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff127224 */
/* 0x000fe200078e00ff */
/*0250*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fe4000001ff00 */
/*0260*/ IMAD.MOV.U32 R9, RZ, RZ, 0x30 ; /* 0x00000030ff097424 */
/* 0x000fe400078e00ff */
/*0270*/ IMAD R11, R12, 0x30, RZ ; /* 0x000000300c0b7824 */
/* 0x000fe400078e02ff */
/*0280*/ IMAD.WIDE.U32 R8, R0, R9, c[0x0][0x160] ; /* 0x0000580000087625 */
/* 0x000fc800078e0009 */
/*0290*/ IMAD.IADD R9, R9, 0x1, R11 ; /* 0x0000000109097824 */
/* 0x000fc800078e020b */
/*02a0*/ IMAD.WIDE R10, R18, 0x4, R8 ; /* 0x00000004120a7825 */
/* 0x000fca00078e0208 */
/*02b0*/ LDG.E R19, [R10.64+0x4] ; /* 0x000004040a137981 */
/* 0x000162000c1e1900 */
/*02c0*/ SHF.R.S32.HI R8, RZ, 0x1f, R13 ; /* 0x0000001fff087819 */
/* 0x000fe2000001140d */
/*02d0*/ IMAD.MOV.U32 R20, RZ, RZ, 0xc80 ; /* 0x00000c80ff147424 */
/* 0x000fe400078e00ff */
/*02e0*/ IMAD.MOV.U32 R23, RZ, RZ, RZ ; /* 0x000000ffff177224 */
/* 0x000fe400078e00ff */
/*02f0*/ IMAD R21, R8, 0xc80, RZ ; /* 0x00000c8008157824 */
/* 0x000fe400078e02ff */
/*0300*/ IMAD.WIDE.U32 R8, R13, R20, c[0x4][0x0] ; /* 0x010000000d087625 */
/* 0x000fc800078e0014 */
/*0310*/ IMAD.IADD R21, R9, 0x1, R21 ; /* 0x0000000109157824 */
/* 0x001fe400078e0215 */
/*0320*/ IMAD.MOV.U32 R10, RZ, RZ, 0x1 ; /* 0x00000001ff0a7424 */
/* 0x000fe400078e00ff */
/*0330*/ IMAD R11, R18, 0x20, R23 ; /* 0x00000020120b7824 */
/* 0x000fe400078e0217 */
/*0340*/ IMAD.MOV.U32 R20, RZ, RZ, 0x2 ; /* 0x00000002ff147424 */
/* 0x000fe200078e00ff */
/*0350*/ SHF.L.U32 R10, R10, R23.reuse, RZ ; /* 0x000000170a0a7219 */
/* 0x080fe200000006ff */
/*0360*/ IMAD R25, R11, 0x5, RZ ; /* 0x000000050b197824 */
/* 0x000fe400078e02ff */
/*0370*/ IMAD.MOV.U32 R11, RZ, RZ, R21 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0015 */
/*0380*/ LOP3.LUT P0, RZ, R19, R10, RZ, 0xc0, !PT ; /* 0x0000000a13ff7212 */
/* 0x020fe2000780c0ff */
/*0390*/ IMAD.MOV.U32 R10, RZ, RZ, R8 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0008 */
/*03a0*/ SHF.L.U32 R20, R20, R23, RZ ; /* 0x0000001714147219 */
/* 0x000fc600000006ff */
/*03b0*/ IMAD.WIDE R10, R25, 0x4, R10 ; /* 0x00000004190a7825 */
/* 0x000fe200078e020a */
/*03c0*/ LOP3.LUT P1, RZ, R19, R20, RZ, 0xc0, !PT ; /* 0x0000001413ff7212 */
/* 0x000fc6000782c0ff */
/*03d0*/ IMAD.MOV.U32 R20, RZ, RZ, 0x4 ; /* 0x00000004ff147424 */
/* 0x000fc800078e00ff */
/*03e0*/ @P0 LDG.E R25, [R10.64+0x4] ; /* 0x000004040a190981 */
/* 0x000ea2000c1e1900 */
/*03f0*/ SHF.L.U32 R20, R20, R23, RZ ; /* 0x0000001714147219 */
/* 0x000fc600000006ff */
/*0400*/ @P0 LDG.E R24, [R10.64] ; /* 0x000000040a180981 */
/* 0x000ee2000c1e1900 */
/*0410*/ LOP3.LUT P3, RZ, R19, R20, RZ, 0xc0, !PT ; /* 0x0000001413ff7212 */
/* 0x000fc6000786c0ff */
/*0420*/ @P0 LDG.E R22, [R10.64+0x8] ; /* 0x000008040a160981 */
/* 0x000f28000c1e1900 */
/*0430*/ @P1 LDG.E R26, [R10.64+0x14] ; /* 0x000014040a1a1981 */
/* 0x000f28000c1e1900 */
/*0440*/ @P1 LDG.E R27, [R10.64+0x18] ; /* 0x000018040a1b1981 */
/* 0x000f28000c1e1900 */
/*0450*/ @P3 LDG.E R20, [R10.64+0x28] ; /* 0x000028040a143981 */
/* 0x000f22000c1e1900 */
/*0460*/ @P0 LOP3.LUT R2, R2, R25, RZ, 0x3c, !PT ; /* 0x0000001902020212 */
/* 0x004fc600078e3cff */
/*0470*/ @P0 LDG.E R25, [R10.64+0xc] ; /* 0x00000c040a190981 */
/* 0x000ea2000c1e1900 */
/*0480*/ @P0 LOP3.LUT R17, R17, R24, RZ, 0x3c, !PT ; /* 0x0000001811110212 */
/* 0x008fc600078e3cff */
/*0490*/ @P0 LDG.E R24, [R10.64+0x10] ; /* 0x000010040a180981 */
/* 0x000ee2000c1e1900 */
/*04a0*/ @P0 LOP3.LUT R3, R3, R22, RZ, 0x3c, !PT ; /* 0x0000001603030212 */
/* 0x010fc600078e3cff */
/*04b0*/ @P1 LDG.E R22, [R10.64+0x1c] ; /* 0x00001c040a161981 */
/* 0x000f22000c1e1900 */
/*04c0*/ @P1 LOP3.LUT R17, R17, R26, RZ, 0x3c, !PT ; /* 0x0000001a11111212 */
/* 0x000fc800078e3cff */
/*04d0*/ @P3 LOP3.LUT R17, R17, R20, RZ, 0x3c, !PT ; /* 0x0000001411113212 */
/* 0x000fe200078e3cff */
/*04e0*/ IMAD.MOV.U32 R20, RZ, RZ, 0x8 ; /* 0x00000008ff147424 */
/* 0x000fca00078e00ff */
/*04f0*/ SHF.L.U32 R20, R20, R23, RZ ; /* 0x0000001714147219 */
/* 0x000fc800000006ff */
/*0500*/ LOP3.LUT P2, RZ, R19, R20, RZ, 0xc0, !PT ; /* 0x0000001413ff7212 */
/* 0x000fda000784c0ff */
/*0510*/ @P2 LDG.E R20, [R10.64+0x3c] ; /* 0x00003c040a142981 */
/* 0x000f22000c1e1900 */
/*0520*/ @P1 LOP3.LUT R2, R2, R27, RZ, 0x3c, !PT ; /* 0x0000001b02021212 */
/* 0x000fc600078e3cff */
/*0530*/ @P3 LDG.E R27, [R10.64+0x2c] ; /* 0x00002c040a1b3981 */
/* 0x000f22000c1e1900 */
/*0540*/ @P0 LOP3.LUT R4, R4, R25, RZ, 0x3c, !PT ; /* 0x0000001904040212 */
/* 0x004fc600078e3cff */
/*0550*/ @P1 LDG.E R25, [R10.64+0x20] ; /* 0x000020040a191981 */
/* 0x000ea2000c1e1900 */
/*0560*/ @P0 LOP3.LUT R5, R5, R24, RZ, 0x3c, !PT ; /* 0x0000001805050212 */
/* 0x008fc600078e3cff */
/*0570*/ @P1 LDG.E R24, [R10.64+0x24] ; /* 0x000024040a181981 */
/* 0x000ee2000c1e1900 */
/*0580*/ @P1 LOP3.LUT R3, R3, R22, RZ, 0x3c, !PT ; /* 0x0000001603031212 */
/* 0x010fc600078e3cff */
/*0590*/ @P3 LDG.E R22, [R10.64+0x30] ; /* 0x000030040a163981 */
/* 0x000f22000c1e1900 */
/*05a0*/ @P2 LOP3.LUT R17, R17, R20, RZ, 0x3c, !PT ; /* 0x0000001411112212 */
/* 0x000fe200078e3cff */
/*05b0*/ IMAD.MOV.U32 R20, RZ, RZ, 0x10 ; /* 0x00000010ff147424 */
/* 0x000fca00078e00ff */
/*05c0*/ SHF.L.U32 R20, R20, R23, RZ ; /* 0x0000001714147219 */
/* 0x000fc800000006ff */
/*05d0*/ LOP3.LUT P0, RZ, R19, R20, RZ, 0xc0, !PT ; /* 0x0000001413ff7212 */
/* 0x000fda000780c0ff */
/*05e0*/ @P0 LDG.E R20, [R10.64+0x50] ; /* 0x000050040a140981 */
/* 0x000f22000c1e1900 */
/*05f0*/ @P3 LOP3.LUT R2, R2, R27, RZ, 0x3c, !PT ; /* 0x0000001b02023212 */
/* 0x000fc600078e3cff */
/*0600*/ @P2 LDG.E R27, [R10.64+0x40] ; /* 0x000040040a1b2981 */
/* 0x000f22000c1e1900 */
/*0610*/ @P1 LOP3.LUT R4, R4, R25, RZ, 0x3c, !PT ; /* 0x0000001904041212 */
/* 0x004fc600078e3cff */
/*0620*/ @P3 LDG.E R25, [R10.64+0x34] ; /* 0x000034040a193981 */
/* 0x000ea2000c1e1900 */
/*0630*/ @P1 LOP3.LUT R5, R5, R24, RZ, 0x3c, !PT ; /* 0x0000001805051212 */
/* 0x008fc600078e3cff */
/*0640*/ @P3 LDG.E R24, [R10.64+0x38] ; /* 0x000038040a183981 */
/* 0x000ee2000c1e1900 */
/*0650*/ @P3 LOP3.LUT R3, R3, R22, RZ, 0x3c, !PT ; /* 0x0000001603033212 */
/* 0x010fc600078e3cff */
/*0660*/ @P2 LDG.E R22, [R10.64+0x44] ; /* 0x000044040a162981 */
/* 0x000f22000c1e1900 */
/*0670*/ @P0 LOP3.LUT R17, R17, R20, RZ, 0x3c, !PT ; /* 0x0000001411110212 */
/* 0x000fe200078e3cff */
/*0680*/ IMAD.MOV.U32 R20, RZ, RZ, 0x20 ; /* 0x00000020ff147424 */
/* 0x000fca00078e00ff */
/*0690*/ SHF.L.U32 R20, R20, R23, RZ ; /* 0x0000001714147219 */
/* 0x000fc800000006ff */
/*06a0*/ LOP3.LUT P1, RZ, R19, R20, RZ, 0xc0, !PT ; /* 0x0000001413ff7212 */
/* 0x000fda000782c0ff */
/*06b0*/ @P1 LDG.E R20, [R10.64+0x64] ; /* 0x000064040a141981 */
/* 0x000f22000c1e1900 */
/*06c0*/ @P2 LOP3.LUT R2, R2, R27, RZ, 0x3c, !PT ; /* 0x0000001b02022212 */
/* 0x000fc600078e3cff */
/*06d0*/ @P0 LDG.E R27, [R10.64+0x54] ; /* 0x000054040a1b0981 */
/* 0x000f22000c1e1900 */
/*06e0*/ @P3 LOP3.LUT R4, R4, R25, RZ, 0x3c, !PT ; /* 0x0000001904043212 */
/* 0x004fc600078e3cff */
/*06f0*/ @P2 LDG.E R25, [R10.64+0x48] ; /* 0x000048040a192981 */
/* 0x000ea2000c1e1900 */
/*0700*/ @P3 LOP3.LUT R5, R5, R24, RZ, 0x3c, !PT ; /* 0x0000001805053212 */
/* 0x008fc600078e3cff */
/*0710*/ @P2 LDG.E R24, [R10.64+0x4c] ; /* 0x00004c040a182981 */
/* 0x000ee2000c1e1900 */
/*0720*/ @P2 LOP3.LUT R3, R3, R22, RZ, 0x3c, !PT ; /* 0x0000001603032212 */
/* 0x010fc600078e3cff */
/*0730*/ @P0 LDG.E R22, [R10.64+0x58] ; /* 0x000058040a160981 */
/* 0x000f22000c1e1900 */
/*0740*/ @P1 LOP3.LUT R17, R17, R20, RZ, 0x3c, !PT ; /* 0x0000001411111212 */
/* 0x000fe200078e3cff */
/*0750*/ IMAD.MOV.U32 R20, RZ, RZ, 0x40 ; /* 0x00000040ff147424 */
/* 0x000fca00078e00ff */
/*0760*/ SHF.L.U32 R20, R20, R23, RZ ; /* 0x0000001714147219 */
/* 0x000fc800000006ff */
/*0770*/ LOP3.LUT P3, RZ, R19, R20, RZ, 0xc0, !PT ; /* 0x0000001413ff7212 */
/* 0x000fda000786c0ff */
/*0780*/ @P3 LDG.E R20, [R10.64+0x78] ; /* 0x000078040a143981 */
/* 0x000f22000c1e1900 */
/*0790*/ @P0 LOP3.LUT R2, R2, R27, RZ, 0x3c, !PT ; /* 0x0000001b02020212 */
/* 0x000fc600078e3cff */
/*07a0*/ @P1 LDG.E R27, [R10.64+0x68] ; /* 0x000068040a1b1981 */
/* 0x000f22000c1e1900 */
/*07b0*/ @P2 LOP3.LUT R4, R4, R25, RZ, 0x3c, !PT ; /* 0x0000001904042212 */
/* 0x004fc600078e3cff */
/*07c0*/ @P0 LDG.E R25, [R10.64+0x5c] ; /* 0x00005c040a190981 */
/* 0x000ea2000c1e1900 */
/*07d0*/ @P2 LOP3.LUT R5, R5, R24, RZ, 0x3c, !PT ; /* 0x0000001805052212 */
/* 0x008fc600078e3cff */
/*07e0*/ @P0 LDG.E R24, [R10.64+0x60] ; /* 0x000060040a180981 */
/* 0x000ee2000c1e1900 */
/*07f0*/ @P0 LOP3.LUT R3, R3, R22, RZ, 0x3c, !PT ; /* 0x0000001603030212 */
/* 0x010fc600078e3cff */
/*0800*/ @P1 LDG.E R22, [R10.64+0x6c] ; /* 0x00006c040a161981 */
/* 0x000ee2000c1e1900 */
/*0810*/ @P3 LOP3.LUT R17, R17, R20, RZ, 0x3c, !PT ; /* 0x0000001411113212 */
/* 0x000fe200078e3cff */
/*0820*/ IMAD.MOV.U32 R20, RZ, RZ, 0x80 ; /* 0x00000080ff147424 */
/* 0x000fca00078e00ff */
/*0830*/ SHF.L.U32 R20, R20, R23, RZ ; /* 0x0000001714147219 */
/* 0x000fc800000006ff */
/*0840*/ LOP3.LUT P2, RZ, R19, R20, RZ, 0xc0, !PT ; /* 0x0000001413ff7212 */
/* 0x000fda000784c0ff */
/*0850*/ @P2 LDG.E R20, [R10.64+0x8c] ; /* 0x00008c040a142981 */
/* 0x000f22000c1e1900 */
/*0860*/ @P1 LOP3.LUT R2, R2, R27, RZ, 0x3c, !PT ; /* 0x0000001b02021212 */
/* 0x000fc600078e3cff */
/*0870*/ @P3 LDG.E R27, [R10.64+0x7c] ; /* 0x00007c040a1b3981 */
/* 0x000f22000c1e1900 */
/*0880*/ @P0 LOP3.LUT R4, R4, R25, RZ, 0x3c, !PT ; /* 0x0000001904040212 */
/* 0x004fc600078e3cff */
/*0890*/ @P1 LDG.E R25, [R10.64+0x70] ; /* 0x000070040a191981 */
/* 0x000ea2000c1e1900 */
/*08a0*/ @P0 LOP3.LUT R5, R5, R24, RZ, 0x3c, !PT ; /* 0x0000001805050212 */
/* 0x008fc600078e3cff */
/*08b0*/ @P1 LDG.E R24, [R10.64+0x74] ; /* 0x000074040a181981 */
/* 0x000ee2000c1e1900 */
/*08c0*/ @P1 LOP3.LUT R3, R3, R22, RZ, 0x3c, !PT ; /* 0x0000001603031212 */
/* 0x000fc600078e3cff */
/*08d0*/ @P3 LDG.E R22, [R10.64+0x80] ; /* 0x000080040a163981 */
/* 0x000ee2000c1e1900 */
/*08e0*/ @P2 LOP3.LUT R17, R17, R20, RZ, 0x3c, !PT ; /* 0x0000001411112212 */
/* 0x010fe200078e3cff */
/*08f0*/ IMAD.MOV.U32 R20, RZ, RZ, 0x100 ; /* 0x00000100ff147424 */
/* 0x000fca00078e00ff */
/*0900*/ SHF.L.U32 R20, R20, R23, RZ ; /* 0x0000001714147219 */
/* 0x000fc800000006ff */
/*0910*/ LOP3.LUT P0, RZ, R19, R20, RZ, 0xc0, !PT ; /* 0x0000001413ff7212 */
/* 0x000fda000780c0ff */
/*0920*/ @P0 LDG.E R20, [R10.64+0xa0] ; /* 0x0000a0040a140981 */
/* 0x000f22000c1e1900 */
/*0930*/ @P3 LOP3.LUT R2, R2, R27, RZ, 0x3c, !PT ; /* 0x0000001b02023212 */
/* 0x000fc600078e3cff */
/*0940*/ @P2 LDG.E R27, [R10.64+0x90] ; /* 0x000090040a1b2981 */
/* 0x000f22000c1e1900 */
/*0950*/ @P1 LOP3.LUT R4, R4, R25, RZ, 0x3c, !PT ; /* 0x0000001904041212 */
/* 0x004fc600078e3cff */
/*0960*/ @P3 LDG.E R25, [R10.64+0x84] ; /* 0x000084040a193981 */
/* 0x000ea2000c1e1900 */
/*0970*/ @P1 LOP3.LUT R5, R5, R24, RZ, 0x3c, !PT ; /* 0x0000001805051212 */
/* 0x008fc600078e3cff */
/*0980*/ @P3 LDG.E R24, [R10.64+0x88] ; /* 0x000088040a183981 */
/* 0x000ee2000c1e1900 */
/*0990*/ @P3 LOP3.LUT R3, R3, R22, RZ, 0x3c, !PT ; /* 0x0000001603033212 */
/* 0x000fc600078e3cff */
/*09a0*/ @P2 LDG.E R22, [R10.64+0x94] ; /* 0x000094040a162981 */
/* 0x000ee2000c1e1900 */
/*09b0*/ @P0 LOP3.LUT R17, R17, R20, RZ, 0x3c, !PT ; /* 0x0000001411110212 */
/* 0x010fe200078e3cff */
/*09c0*/ IMAD.MOV.U32 R20, RZ, RZ, 0x200 ; /* 0x00000200ff147424 */
/* 0x000fca00078e00ff */
/*09d0*/ SHF.L.U32 R20, R20, R23, RZ ; /* 0x0000001714147219 */
/* 0x000fc800000006ff */
/*09e0*/ LOP3.LUT P1, RZ, R19, R20, RZ, 0xc0, !PT ; /* 0x0000001413ff7212 */
/* 0x000fda000782c0ff */
/*09f0*/ @P1 LDG.E R20, [R10.64+0xb4] ; /* 0x0000b4040a141981 */
/* 0x000f22000c1e1900 */
/*0a00*/ @P2 LOP3.LUT R2, R2, R27, RZ, 0x3c, !PT ; /* 0x0000001b02022212 */
/* 0x000fc600078e3cff */
/*0a10*/ @P0 LDG.E R27, [R10.64+0xa4] ; /* 0x0000a4040a1b0981 */
/* 0x000f22000c1e1900 */
/*0a20*/ @P3 LOP3.LUT R4, R4, R25, RZ, 0x3c, !PT ; /* 0x0000001904043212 */
/* 0x004fc600078e3cff */
/*0a30*/ @P2 LDG.E R25, [R10.64+0x98] ; /* 0x000098040a192981 */
/* 0x000ea2000c1e1900 */
/*0a40*/ @P3 LOP3.LUT R5, R5, R24, RZ, 0x3c, !PT ; /* 0x0000001805053212 */
/* 0x008fc600078e3cff */
/*0a50*/ @P2 LDG.E R24, [R10.64+0x9c] ; /* 0x00009c040a182981 */
/* 0x000ee2000c1e1900 */
/*0a60*/ @P2 LOP3.LUT R3, R3, R22, RZ, 0x3c, !PT ; /* 0x0000001603032212 */
/* 0x000fc600078e3cff */
/*0a70*/ @P0 LDG.E R22, [R10.64+0xa8] ; /* 0x0000a8040a160981 */
/* 0x000ee2000c1e1900 */
/*0a80*/ @P1 LOP3.LUT R17, R17, R20, RZ, 0x3c, !PT ; /* 0x0000001411111212 */
/* 0x010fe200078e3cff */
/*0a90*/ IMAD.MOV.U32 R20, RZ, RZ, 0x400 ; /* 0x00000400ff147424 */
/* 0x000fca00078e00ff */
/*0aa0*/ SHF.L.U32 R20, R20, R23, RZ ; /* 0x0000001714147219 */
/* 0x000fc800000006ff */
/*0ab0*/ LOP3.LUT P3, RZ, R19, R20, RZ, 0xc0, !PT ; /* 0x0000001413ff7212 */
/* 0x000fda000786c0ff */
/*0ac0*/ @P3 LDG.E R20, [R10.64+0xc8] ; /* 0x0000c8040a143981 */
/* 0x000f22000c1e1900 */
/*0ad0*/ @P0 LOP3.LUT R2, R2, R27, RZ, 0x3c, !PT ; /* 0x0000001b02020212 */
/* 0x000fc600078e3cff */
/*0ae0*/ @P1 LDG.E R27, [R10.64+0xb8] ; /* 0x0000b8040a1b1981 */
/* 0x000f22000c1e1900 */
/*0af0*/ @P2 LOP3.LUT R4, R4, R25, RZ, 0x3c, !PT ; /* 0x0000001904042212 */
/* 0x004fc600078e3cff */
/*0b00*/ @P0 LDG.E R25, [R10.64+0xac] ; /* 0x0000ac040a190981 */
/* 0x000ea2000c1e1900 */
/*0b10*/ @P2 LOP3.LUT R5, R5, R24, RZ, 0x3c, !PT ; /* 0x0000001805052212 */
/* 0x008fc600078e3cff */
/*0b20*/ @P0 LDG.E R24, [R10.64+0xb0] ; /* 0x0000b0040a180981 */
/* 0x000ee2000c1e1900 */
/*0b30*/ @P0 LOP3.LUT R3, R3, R22, RZ, 0x3c, !PT ; /* 0x0000001603030212 */
/* 0x000fc600078e3cff */
/*0b40*/ @P1 LDG.E R22, [R10.64+0xbc] ; /* 0x0000bc040a161981 */
/* 0x000ee2000c1e1900 */
/*0b50*/ @P3 LOP3.LUT R17, R17, R20, RZ, 0x3c, !PT ; /* 0x0000001411113212 */
/* 0x010fe200078e3cff */
/*0b60*/ IMAD.MOV.U32 R20, RZ, RZ, 0x800 ; /* 0x00000800ff147424 */
/* 0x000fca00078e00ff */
/*0b70*/ SHF.L.U32 R20, R20, R23, RZ ; /* 0x0000001714147219 */
/* 0x000fc800000006ff */
/*0b80*/ LOP3.LUT P2, RZ, R19, R20, RZ, 0xc0, !PT ; /* 0x0000001413ff7212 */
/* 0x000fda000784c0ff */
/*0b90*/ @P2 LDG.E R20, [R10.64+0xdc] ; /* 0x0000dc040a142981 */
/* 0x000f22000c1e1900 */
/*0ba0*/ @P1 LOP3.LUT R2, R2, R27, RZ, 0x3c, !PT ; /* 0x0000001b02021212 */
/* 0x000fc600078e3cff */
/*0bb0*/ @P3 LDG.E R27, [R10.64+0xcc] ; /* 0x0000cc040a1b3981 */
/* 0x000f22000c1e1900 */
/*0bc0*/ @P0 LOP3.LUT R4, R4, R25, RZ, 0x3c, !PT ; /* 0x0000001904040212 */
/* 0x004fc600078e3cff */
/*0bd0*/ @P1 LDG.E R25, [R10.64+0xc0] ; /* 0x0000c0040a191981 */
/* 0x000ea2000c1e1900 */
/*0be0*/ @P0 LOP3.LUT R5, R5, R24, RZ, 0x3c, !PT ; /* 0x0000001805050212 */
/* 0x008fc600078e3cff */
/*0bf0*/ @P1 LDG.E R24, [R10.64+0xc4] ; /* 0x0000c4040a181981 */
/* 0x000ee2000c1e1900 */
/*0c00*/ @P1 LOP3.LUT R3, R3, R22, RZ, 0x3c, !PT ; /* 0x0000001603031212 */
/* 0x000fc600078e3cff */
/*0c10*/ @P3 LDG.E R22, [R10.64+0xd0] ; /* 0x0000d0040a163981 */
/* 0x000ee2000c1e1900 */
/*0c20*/ @P2 LOP3.LUT R17, R17, R20, RZ, 0x3c, !PT ; /* 0x0000001411112212 */
/* 0x010fe200078e3cff */
/*0c30*/ IMAD.MOV.U32 R20, RZ, RZ, 0x1000 ; /* 0x00001000ff147424 */
/* 0x000fca00078e00ff */
/*0c40*/ SHF.L.U32 R20, R20, R23, RZ ; /* 0x0000001714147219 */
/* 0x000fc800000006ff */
/*0c50*/ LOP3.LUT P0, RZ, R19, R20, RZ, 0xc0, !PT ; /* 0x0000001413ff7212 */
/* 0x000fda000780c0ff */
/*0c60*/ @P0 LDG.E R20, [R10.64+0xf0] ; /* 0x0000f0040a140981 */
/* 0x000f22000c1e1900 */
/*0c70*/ @P3 LOP3.LUT R2, R2, R27, RZ, 0x3c, !PT ; /* 0x0000001b02023212 */
/* 0x000fc600078e3cff */
/*0c80*/ @P2 LDG.E R27, [R10.64+0xe0] ; /* 0x0000e0040a1b2981 */
/* 0x000f22000c1e1900 */
/*0c90*/ @P1 LOP3.LUT R4, R4, R25, RZ, 0x3c, !PT ; /* 0x0000001904041212 */
/* 0x004fc600078e3cff */
/*0ca0*/ @P3 LDG.E R25, [R10.64+0xd4] ; /* 0x0000d4040a193981 */
/* 0x000ea2000c1e1900 */
/*0cb0*/ @P1 LOP3.LUT R5, R5, R24, RZ, 0x3c, !PT ; /* 0x0000001805051212 */
/* 0x008fc600078e3cff */
/*0cc0*/ @P3 LDG.E R24, [R10.64+0xd8] ; /* 0x0000d8040a183981 */
/* 0x000ee2000c1e1900 */
/*0cd0*/ @P3 LOP3.LUT R3, R3, R22, RZ, 0x3c, !PT ; /* 0x0000001603033212 */
/* 0x000fc600078e3cff */
/*0ce0*/ @P2 LDG.E R22, [R10.64+0xe4] ; /* 0x0000e4040a162981 */
/* 0x000ee2000c1e1900 */
/*0cf0*/ @P0 LOP3.LUT R17, R17, R20, RZ, 0x3c, !PT ; /* 0x0000001411110212 */
/* 0x010fe200078e3cff */
/*0d00*/ IMAD.MOV.U32 R20, RZ, RZ, 0x2000 ; /* 0x00002000ff147424 */
/* 0x000fca00078e00ff */
/*0d10*/ SHF.L.U32 R20, R20, R23, RZ ; /* 0x0000001714147219 */
/* 0x000fc800000006ff */
/*0d20*/ LOP3.LUT P1, RZ, R19, R20, RZ, 0xc0, !PT ; /* 0x0000001413ff7212 */
/* 0x000fda000782c0ff */
/*0d30*/ @P1 LDG.E R20, [R10.64+0x104] ; /* 0x000104040a141981 */
/* 0x000f22000c1e1900 */
/*0d40*/ @P2 LOP3.LUT R2, R2, R27, RZ, 0x3c, !PT ; /* 0x0000001b02022212 */
/* 0x000fc600078e3cff */
/*0d50*/ @P0 LDG.E R27, [R10.64+0xf4] ; /* 0x0000f4040a1b0981 */
/* 0x000f22000c1e1900 */
/*0d60*/ @P3 LOP3.LUT R4, R4, R25, RZ, 0x3c, !PT ; /* 0x0000001904043212 */
/* 0x004fc600078e3cff */
/*0d70*/ @P2 LDG.E R25, [R10.64+0xe8] ; /* 0x0000e8040a192981 */
/* 0x000ea2000c1e1900 */
/*0d80*/ @P3 LOP3.LUT R5, R5, R24, RZ, 0x3c, !PT ; /* 0x0000001805053212 */
/* 0x008fc600078e3cff */
/*0d90*/ @P2 LDG.E R24, [R10.64+0xec] ; /* 0x0000ec040a182981 */
/* 0x000ee2000c1e1900 */
/*0da0*/ @P2 LOP3.LUT R3, R3, R22, RZ, 0x3c, !PT ; /* 0x0000001603032212 */
/* 0x000fc600078e3cff */
/*0db0*/ @P0 LDG.E R22, [R10.64+0xf8] ; /* 0x0000f8040a160981 */
/* 0x000ee2000c1e1900 */
/*0dc0*/ @P1 LOP3.LUT R17, R17, R20, RZ, 0x3c, !PT ; /* 0x0000001411111212 */
/* 0x010fe200078e3cff */
/*0dd0*/ IMAD.MOV.U32 R20, RZ, RZ, 0x4000 ; /* 0x00004000ff147424 */
/* 0x000fca00078e00ff */
/*0de0*/ SHF.L.U32 R20, R20, R23, RZ ; /* 0x0000001714147219 */
/* 0x000fc800000006ff */
/*0df0*/ LOP3.LUT P3, RZ, R19, R20, RZ, 0xc0, !PT ; /* 0x0000001413ff7212 */
/* 0x000fda000786c0ff */
/*0e00*/ @P3 LDG.E R20, [R10.64+0x118] ; /* 0x000118040a143981 */
/* 0x000f22000c1e1900 */
/*0e10*/ @P0 LOP3.LUT R2, R2, R27, RZ, 0x3c, !PT ; /* 0x0000001b02020212 */
/* 0x000fc600078e3cff */
/*0e20*/ @P1 LDG.E R27, [R10.64+0x108] ; /* 0x000108040a1b1981 */
/* 0x000f22000c1e1900 */
/*0e30*/ @P2 LOP3.LUT R4, R4, R25, RZ, 0x3c, !PT ; /* 0x0000001904042212 */
/* 0x004fc600078e3cff */
/*0e40*/ @P0 LDG.E R25, [R10.64+0xfc] ; /* 0x0000fc040a190981 */
/* 0x000ea2000c1e1900 */
/*0e50*/ @P2 LOP3.LUT R5, R5, R24, RZ, 0x3c, !PT ; /* 0x0000001805052212 */
/* 0x008fc600078e3cff */
/*0e60*/ @P0 LDG.E R24, [R10.64+0x100] ; /* 0x000100040a180981 */
/* 0x000ee2000c1e1900 */
/*0e70*/ @P0 LOP3.LUT R3, R3, R22, RZ, 0x3c, !PT ; /* 0x0000001603030212 */
/* 0x000fc600078e3cff */
/*0e80*/ @P1 LDG.E R22, [R10.64+0x10c] ; /* 0x00010c040a161981 */
/* 0x000ee2000c1e1900 */
/*0e90*/ @P3 LOP3.LUT R17, R17, R20, RZ, 0x3c, !PT ; /* 0x0000001411113212 */
/* 0x010fe200078e3cff */
/*0ea0*/ IMAD.MOV.U32 R20, RZ, RZ, 0x8000 ; /* 0x00008000ff147424 */
/* 0x000fca00078e00ff */
/*0eb0*/ SHF.L.U32 R20, R20, R23, RZ ; /* 0x0000001714147219 */
/* 0x000fc800000006ff */
/*0ec0*/ LOP3.LUT P2, RZ, R19, R20, RZ, 0xc0, !PT ; /* 0x0000001413ff7212 */
/* 0x000fe4000784c0ff */
/*0ed0*/ @P1 LDG.E R20, [R10.64+0x114] ; /* 0x000114040a141981 */
/* 0x000f22000c1e1900 */
/*0ee0*/ @P1 LOP3.LUT R2, R2, R27, RZ, 0x3c, !PT ; /* 0x0000001b02021212 */
/* 0x000fc600078e3cff */
/*0ef0*/ @P3 LDG.E R27, [R10.64+0x11c] ; /* 0x00011c040a1b3981 */
/* 0x000f2e000c1e1900 */
/*0f00*/ @P2 LDG.E R29, [R10.64+0x138] ; /* 0x000138040a1d2981 */
/* 0x000f22000c1e1900 */
/*0f10*/ @P0 LOP3.LUT R4, R4, R25, RZ, 0x3c, !PT ; /* 0x0000001904040212 */
/* 0x004fc600078e3cff */
/*0f20*/ @P1 LDG.E R25, [R10.64+0x110] ; /* 0x000110040a191981 */
/* 0x000ea2000c1e1900 */
/*0f30*/ @P0 LOP3.LUT R5, R5, R24, RZ, 0x3c, !PT ; /* 0x0000001805050212 */
/* 0x008fc600078e3cff */
/*0f40*/ @P2 LDG.E R24, [R10.64+0x12c] ; /* 0x00012c040a182981 */
/* 0x000ee2000c1e1900 */
/*0f50*/ @P1 LOP3.LUT R3, R3, R22, RZ, 0x3c, !PT ; /* 0x0000001603031212 */
/* 0x000fc600078e3cff */
/*0f60*/ @P3 LDG.E R22, [R10.64+0x120] ; /* 0x000120040a163981 */
/* 0x000ee2000c1e1900 */
/*0f70*/ @P1 LOP3.LUT R5, R5, R20, RZ, 0x3c, !PT ; /* 0x0000001405051212 */
/* 0x010fc600078e3cff */
/*0f80*/ @P3 LDG.E R20, [R10.64+0x128] ; /* 0x000128040a143981 */
/* 0x000f22000c1e1900 */
/*0f90*/ @P3 LOP3.LUT R2, R2, R27, RZ, 0x3c, !PT ; /* 0x0000001b02023212 */
/* 0x000fc600078e3cff */
/*0fa0*/ @P2 LDG.E R27, [R10.64+0x130] ; /* 0x000130040a1b2981 */
/* 0x000f22000c1e1900 */
/*0fb0*/ @P1 LOP3.LUT R4, R4, R25, RZ, 0x3c, !PT ; /* 0x0000001904041212 */
/* 0x004fc600078e3cff */
/*0fc0*/ @P3 LDG.E R25, [R10.64+0x124] ; /* 0x000124040a193981 */
/* 0x000ea2000c1e1900 */
/*0fd0*/ @P2 LOP3.LUT R17, R17, R24, RZ, 0x3c, !PT ; /* 0x0000001811112212 */
/* 0x008fc600078e3cff */
/*0fe0*/ @P2 LDG.E R24, [R10.64+0x13c] ; /* 0x00013c040a182981 */
/* 0x000ee2000c1e1900 */
/*0ff0*/ @P3 LOP3.LUT R3, R3, R22, RZ, 0x3c, !PT ; /* 0x0000001603033212 */
/* 0x000fc600078e3cff */
/*1000*/ @P2 LDG.E R22, [R10.64+0x134] ; /* 0x000134040a162981 */
/* 0x000ee2000c1e1900 */
/*1010*/ IADD3 R23, R23, 0x10, RZ ; /* 0x0000001017177810 */
/* 0x000fc80007ffe0ff */
/*1020*/ ISETP.NE.AND P0, PT, R23, 0x20, PT ; /* 0x000000201700780c */
/* 0x000fe40003f05270 */
/*1030*/ @P3 LOP3.LUT R5, R5, R20, RZ, 0x3c, !PT ; /* 0x0000001405053212 */
/* 0x010fe400078e3cff */
/*1040*/ @P2 LOP3.LUT R2, R2, R27, RZ, 0x3c, !PT ; /* 0x0000001b02022212 */
/* 0x000fe400078e3cff */
/*1050*/ @P3 LOP3.LUT R4, R4, R25, RZ, 0x3c, !PT ; /* 0x0000001904043212 */
/* 0x004fc800078e3cff */
/*1060*/ @P2 LOP3.LUT R4, R4, R29, RZ, 0x3c, !PT ; /* 0x0000001d04042212 */
/* 0x000fe400078e3cff */
/*1070*/ @P2 LOP3.LUT R5, R5, R24, RZ, 0x3c, !PT ; /* 0x0000001805052212 */
/* 0x008fe400078e3cff */
/*1080*/ @P2 LOP3.LUT R3, R3, R22, RZ, 0x3c, !PT ; /* 0x0000001603032212 */
/* 0x000fe200078e3cff */
/*1090*/ @P0 BRA 0x320 ; /* 0xfffff28000000947 */
/* 0x000fea000383ffff */
/*10a0*/ IADD3 R18, R18, 0x1, RZ ; /* 0x0000000112127810 */
/* 0x000fc80007ffe0ff */
/*10b0*/ ISETP.GE.U32.AND P0, PT, R18, 0x5, PT ; /* 0x000000051200780c */
/* 0x000fda0003f06070 */
/*10c0*/ @!P0 BRA 0x260 ; /* 0xfffff19000008947 */
/* 0x000fea000383ffff */
/*10d0*/ IADD3 R16, R16, 0x1, RZ ; /* 0x0000000110107810 */
/* 0x000fe20007ffe0ff */
/*10e0*/ STG.E.64 [R6.64+0x8], R2 ; /* 0x0000080206007986 */
/* 0x0001e2000c101b04 */
/*10f0*/ LOP3.LUT R9, R14, 0x3, RZ, 0xc0, !PT ; /* 0x000000030e097812 */
/* 0x000fc600078ec0ff */
/*1100*/ STG.E.64 [R6.64+0x10], R4 ; /* 0x0000100406007986 */
/* 0x0001e2000c101b04 */
/*1110*/ ISETP.GT.U32.AND P0, PT, R9, R16, PT ; /* 0x000000100900720c */
/* 0x000fc60003f04070 */
/*1120*/ STG.E [R6.64+0x4], R17 ; /* 0x0000041106007986 */
/* 0x0001e2000c101904 */
/*1130*/ ISETP.GT.U32.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fda0003f04100 */
/*1140*/ @P0 BRA 0x220 ; /* 0xfffff0d000000947 */
/* 0x001fea000383ffff */
/*1150*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*1160*/ SHF.R.U64 R14, R14, 0x2, R15.reuse ; /* 0x000000020e0e7819 */
/* 0x100fe4000000120f */
/*1170*/ SHF.R.U32.HI R15, RZ, 0x2, R15 ; /* 0x00000002ff0f7819 */
/* 0x000fe4000001160f */
/*1180*/ ISETP.NE.U32.AND P0, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe40003f05070 */
/*1190*/ IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d7810 */
/* 0x000fe40007ffe0ff */
/*11a0*/ ISETP.NE.AND.EX P0, PT, R15, RZ, PT, P0 ; /* 0x000000ff0f00720c */
/* 0x000fda0003f05300 */
/*11b0*/ @!P0 CALL.REL.NOINC 0x11d0 ; /* 0x0000001000008944 */
/* 0x000fe20003c00000 */
/*11c0*/ BRA 0x1e0 ; /* 0xfffff01000007947 */
/* 0x000fea000383ffff */
/*11d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*11e0*/ STG.E.64 [R6.64+0x18], RZ ; /* 0x000018ff06007986 */
/* 0x000fe8000c101b04 */
/*11f0*/ STG.E [R6.64+0x20], RZ ; /* 0x000020ff06007986 */
/* 0x000fe8000c101904 */
/*1200*/ STG.E.64 [R6.64+0x28], RZ ; /* 0x000028ff06007986 */
/* 0x000fe2000c101b04 */
/*1210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*1220*/ BRA 0x1220; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0008b20d_00000000-6_cuda_helpers.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3886:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3886:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA error = "
.LC1:
.string " at "
.LC2:
.string ":"
.LC3:
.string " '"
.LC4:
.string "' \n"
.text
.globl _Z10check_cuda9cudaErrorPKcS1_i
.type _Z10check_cuda9cudaErrorPKcS1_i, @function
_Z10check_cuda9cudaErrorPKcS1_i:
.LFB3883:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L8
ret
.L8:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %rbp
movq %rdx, %r13
movl %ecx, %r12d
leaq .LC0(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r13, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r12d, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
call cudaDeviceReset@PLT
movl $99, %edi
call exit@PLT
.cfi_endproc
.LFE3883:
.size _Z10check_cuda9cudaErrorPKcS1_i, .-_Z10check_cuda9cudaErrorPKcS1_i
.globl _Z55__device_stub__Z15init_rand_stateP17curandStateXORWOWiiP17curandStateXORWOWii
.type _Z55__device_stub__Z15init_rand_stateP17curandStateXORWOWiiP17curandStateXORWOWii, @function
_Z55__device_stub__Z15init_rand_stateP17curandStateXORWOWiiP17curandStateXORWOWii:
.LFB3908:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15init_rand_stateP17curandStateXORWOWii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3908:
.size _Z55__device_stub__Z15init_rand_stateP17curandStateXORWOWiiP17curandStateXORWOWii, .-_Z55__device_stub__Z15init_rand_stateP17curandStateXORWOWiiP17curandStateXORWOWii
.globl _Z15init_rand_stateP17curandStateXORWOWii
.type _Z15init_rand_stateP17curandStateXORWOWii, @function
_Z15init_rand_stateP17curandStateXORWOWii:
.LFB3909:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z55__device_stub__Z15init_rand_stateP17curandStateXORWOWiiP17curandStateXORWOWii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3909:
.size _Z15init_rand_stateP17curandStateXORWOWii, .-_Z15init_rand_stateP17curandStateXORWOWii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "_Z15init_rand_stateP17curandStateXORWOWii"
.section .rodata.str1.1
.LC6:
.string "precalc_xorwow_matrix"
.LC7:
.string "precalc_xorwow_offset_matrix"
.LC8:
.string "mrg32k3aM1"
.LC9:
.string "mrg32k3aM2"
.LC10:
.string "mrg32k3aM1SubSeq"
.LC11:
.string "mrg32k3aM2SubSeq"
.LC12:
.string "mrg32k3aM1Seq"
.LC13:
.string "mrg32k3aM2Seq"
.LC14:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3911:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z15init_rand_stateP17curandStateXORWOWii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3911:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_helpers.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void gpu_sobel_kernel_naive(u_char *Source, u_char *Resultat, unsigned width, unsigned height) {
int j = blockIdx.x*blockDim.x + threadIdx.x;
int i = blockIdx.y*blockDim.y + threadIdx.y;
u_char val;
int globalIndex = i*width+j;
if ((i==0)||(i>=height-1)||(j==0)||(j>=width-1)) {Resultat[globalIndex]=0;}
else {
val = std::abs(Source[(i-1)*width+(j-1)] + Source[(i-1)*width+(j)] + Source[(i-1)*width+(j+1)] -\
(Source[(i+1)*width+(j-1)] + Source[(i+1)*width+(j)] + Source[(i+1)*width+(j+1)]));
Resultat[globalIndex] = val + std::abs(Source[(i-1)*width+(j-1)] + Source[(i)*width+(j-1)] + Source[(i+1)*width+(j-1)] -\
(Source[(i-1)*width+(j+1)] + Source[(i)*width+(j+1)] + Source[(i+1)*width+(j+1)]));
}
} | code for sm_80
Function : _Z22gpu_sobel_kernel_naivePhS_jj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002600 */
/*0020*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe20000000000 */
/*0030*/ BSSY B0, 0x460 ; /* 0x0000042000007945 */
/* 0x000fe20003800000 */
/*0040*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002200 */
/*0060*/ UIADD3 UR4, -UR5, UR7, URZ ; /* 0x0000000705047290 */
/* 0x000fe2000fffe13f */
/*0070*/ PRMT R4, RZ, 0x7610, R4 ; /* 0x00007610ff047816 */
/* 0x000fe40000000004 */
/*0080*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0090*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*00a0*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x001fca00078e0202 */
/*00b0*/ ISETP.GE.U32.AND P0, PT, R5.reuse, UR4, PT ; /* 0x0000000405007c0c */
/* 0x040fe2000bf06070 */
/*00c0*/ UIADD3 UR4, -UR5, UR6, URZ ; /* 0x0000000605047290 */
/* 0x000fe2000fffe13f */
/*00d0*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fe400078e0203 */
/*00e0*/ ISETP.EQ.OR P0, PT, R5.reuse, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x040fe40000702670 */
/*00f0*/ IMAD R3, R5, c[0x0][0x170], R0 ; /* 0x00005c0005037a24 */
/* 0x000fe400078e0200 */
/*0100*/ ISETP.EQ.OR P0, PT, R0, RZ, P0 ; /* 0x000000ff0000720c */
/* 0x000fc80000702670 */
/*0110*/ ISETP.GE.U32.OR P0, PT, R0, UR4, P0 ; /* 0x0000000400007c0c */
/* 0x000fe20008706470 */
/*0120*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0130*/ IADD3 R2, P1, R3, c[0x0][0x168], RZ ; /* 0x00005a0003027a10 */
/* 0x000fc80007f3e0ff */
/*0140*/ LEA.HI.X.SX32 R3, R3, c[0x0][0x16c], 0x1, P1 ; /* 0x00005b0003037a11 */
/* 0x000fce00008f0eff */
/*0150*/ @P0 BRA 0x450 ; /* 0x000002f000000947 */
/* 0x000fea0003800000 */
/*0160*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */
/* 0x000fe200078e00ff */
/*0170*/ IADD3 R8, R0.reuse, -0x1, RZ ; /* 0xffffffff00087810 */
/* 0x040fe40007ffe0ff */
/*0180*/ IADD3 R12, R0, 0x1, RZ ; /* 0x00000001000c7810 */
/* 0x000fe20007ffe0ff */
/*0190*/ IMAD R7, R5.reuse, R6, -c[0x0][0x170] ; /* 0x80005c0005077624 */
/* 0x040fe400078e0206 */
/*01a0*/ IMAD R4, R5, c[0x0][0x170], R8.reuse ; /* 0x00005c0005047a24 */
/* 0x100fe400078e0208 */
/*01b0*/ IMAD R11, R6, 0x2, R7.reuse ; /* 0x00000002060b7824 */
/* 0x100fe400078e0207 */
/*01c0*/ IMAD.IADD R6, R7.reuse, 0x1, R8 ; /* 0x0000000107067824 */
/* 0x040fe200078e0208 */
/*01d0*/ IADD3 R4, P1, R4, c[0x0][0x160], RZ ; /* 0x0000580004047a10 */
/* 0x000fe20007f3e0ff */
/*01e0*/ IMAD.IADD R10, R0.reuse, 0x1, R7 ; /* 0x00000001000a7824 */
/* 0x040fe200078e0207 */
/*01f0*/ IADD3 R0, R0, R11, RZ ; /* 0x0000000b00007210 */
/* 0x000fe20007ffe0ff */
/*0200*/ IMAD.IADD R9, R7, 0x1, R12.reuse ; /* 0x0000000107097824 */
/* 0x100fe200078e020c */
/*0210*/ IADD3 R6, P0, R6, c[0x0][0x160], RZ ; /* 0x0000580006067a10 */
/* 0x000fe20007f1e0ff */
/*0220*/ IMAD R18, R5, c[0x0][0x170], R12 ; /* 0x00005c0005127a24 */
/* 0x000fc400078e020c */
/*0230*/ IMAD.IADD R13, R8, 0x1, R11.reuse ; /* 0x00000001080d7824 */
/* 0x100fe400078e020b */
/*0240*/ IMAD.X R5, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff057624 */
/* 0x000fe200008e06ff */
/*0250*/ IADD3 R10, P1, R10, c[0x0][0x160], RZ ; /* 0x000058000a0a7a10 */
/* 0x000fe20007f3e0ff */
/*0260*/ IMAD.X R7, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff077624 */
/* 0x000fe200000e06ff */
/*0270*/ IADD3 R8, P0, R9, c[0x0][0x160], RZ ; /* 0x0000580009087a10 */
/* 0x000fe20007f1e0ff */
/*0280*/ IMAD.IADD R16, R12, 0x1, R11 ; /* 0x000000010c107824 */
/* 0x000fe200078e020b */
/*0290*/ IADD3 R12, P2, R13, c[0x0][0x160], RZ ; /* 0x000058000d0c7a10 */
/* 0x000fe20007f5e0ff */
/*02a0*/ IMAD.X R11, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff0b7624 */
/* 0x000fe200008e06ff */
/*02b0*/ IADD3.X R9, RZ, c[0x0][0x164], RZ, P0, !PT ; /* 0x00005900ff097a10 */
/* 0x000fe200007fe4ff */
/*02c0*/ LDG.E.U8 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1100 */
/*02d0*/ IADD3 R14, P1, R0, c[0x0][0x160], RZ ; /* 0x00005800000e7a10 */
/* 0x000fe20007f3e0ff */
/*02e0*/ IMAD.X R13, RZ, RZ, c[0x0][0x164], P2 ; /* 0x00005900ff0d7624 */
/* 0x000fe200010e06ff */
/*02f0*/ IADD3 R18, P0, R18, c[0x0][0x160], RZ ; /* 0x0000580012127a10 */
/* 0x000fe20007f1e0ff */
/*0300*/ LDG.E.U8 R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000ea2000c1e1100 */
/*0310*/ IADD3 R16, P2, R16, c[0x0][0x160], RZ ; /* 0x0000580010107a10 */
/* 0x000fe20007f5e0ff */
/*0320*/ IMAD.X R15, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff0f7624 */
/* 0x000fc400008e06ff */
/*0330*/ LDG.E.U8 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1100 */
/*0340*/ IMAD.X R19, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff137624 */
/* 0x000fe400000e06ff */
/*0350*/ IMAD.X R17, RZ, RZ, c[0x0][0x164], P2 ; /* 0x00005900ff117624 */
/* 0x000fe200010e06ff */
/*0360*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee8000c1e1100 */
/*0370*/ LDG.E.U8 R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000ee8000c1e1100 */
/*0380*/ LDG.E.U8 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f28000c1e1100 */
/*0390*/ LDG.E.U8 R19, [R18.64] ; /* 0x0000000412137981 */
/* 0x000f68000c1e1100 */
/*03a0*/ LDG.E.U8 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f62000c1e1100 */
/*03b0*/ IADD3 R11, R8, R11, R6 ; /* 0x0000000b080b7210 */
/* 0x004fc40007ffe006 */
/*03c0*/ IADD3 R4, R13, R4, R6 ; /* 0x000000040d047210 */
/* 0x008fe40007ffe006 */
/*03d0*/ IADD3 R11, -R14, R11, -R13 ; /* 0x0000000b0e0b7210 */
/* 0x010fe40007ffe90d */
/*03e0*/ IADD3 R5, -R19, R4, -R8 ; /* 0x0000000413057210 */
/* 0x020fe40007ffe908 */
/*03f0*/ IADD3 R11, -R16, R11, RZ ; /* 0x0000000b100b7210 */
/* 0x000fc60007ffe1ff */
/*0400*/ IMAD.IADD R5, R5, 0x1, -R16 ; /* 0x0000000105057824 */
/* 0x000fe200078e0a10 */
/*0410*/ IABS R11, R11 ; /* 0x0000000b000b7213 */
/* 0x000fc80000000000 */
/*0420*/ IABS R4, R5 ; /* 0x0000000500047213 */
/* 0x000fe20000000000 */
/*0430*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fc800078e000b */
/*0440*/ IMAD.IADD R4, R4, 0x1, R5 ; /* 0x0000000104047824 */
/* 0x000fe400078e0205 */
/*0450*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0460*/ STG.E.U8 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101104 */
/*0470*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0480*/ BRA 0x480; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void gpu_sobel_kernel_naive(u_char *Source, u_char *Resultat, unsigned width, unsigned height) {
int j = blockIdx.x*blockDim.x + threadIdx.x;
int i = blockIdx.y*blockDim.y + threadIdx.y;
u_char val;
int globalIndex = i*width+j;
if ((i==0)||(i>=height-1)||(j==0)||(j>=width-1)) {Resultat[globalIndex]=0;}
else {
val = std::abs(Source[(i-1)*width+(j-1)] + Source[(i-1)*width+(j)] + Source[(i-1)*width+(j+1)] -\
(Source[(i+1)*width+(j-1)] + Source[(i+1)*width+(j)] + Source[(i+1)*width+(j+1)]));
Resultat[globalIndex] = val + std::abs(Source[(i-1)*width+(j-1)] + Source[(i)*width+(j-1)] + Source[(i+1)*width+(j-1)] -\
(Source[(i-1)*width+(j+1)] + Source[(i)*width+(j+1)] + Source[(i+1)*width+(j+1)]));
}
} | .file "tmpxft_00073295_00000000-6_gpu_sobel_kernel_naive.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z22gpu_sobel_kernel_naivePhS_jjPhS_jj
.type _Z46__device_stub__Z22gpu_sobel_kernel_naivePhS_jjPhS_jj, @function
_Z46__device_stub__Z22gpu_sobel_kernel_naivePhS_jjPhS_jj:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22gpu_sobel_kernel_naivePhS_jj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z22gpu_sobel_kernel_naivePhS_jjPhS_jj, .-_Z46__device_stub__Z22gpu_sobel_kernel_naivePhS_jjPhS_jj
.globl _Z22gpu_sobel_kernel_naivePhS_jj
.type _Z22gpu_sobel_kernel_naivePhS_jj, @function
_Z22gpu_sobel_kernel_naivePhS_jj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z22gpu_sobel_kernel_naivePhS_jjPhS_jj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z22gpu_sobel_kernel_naivePhS_jj, .-_Z22gpu_sobel_kernel_naivePhS_jj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z22gpu_sobel_kernel_naivePhS_jj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z22gpu_sobel_kernel_naivePhS_jj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void gpu_sobel_kernel_naive(u_char *Source, u_char *Resultat, unsigned width, unsigned height) {
int j = blockIdx.x*blockDim.x + threadIdx.x;
int i = blockIdx.y*blockDim.y + threadIdx.y;
u_char val;
int globalIndex = i*width+j;
if ((i==0)||(i>=height-1)||(j==0)||(j>=width-1)) {Resultat[globalIndex]=0;}
else {
val = std::abs(Source[(i-1)*width+(j-1)] + Source[(i-1)*width+(j)] + Source[(i-1)*width+(j+1)] -\
(Source[(i+1)*width+(j-1)] + Source[(i+1)*width+(j)] + Source[(i+1)*width+(j+1)]));
Resultat[globalIndex] = val + std::abs(Source[(i-1)*width+(j-1)] + Source[(i)*width+(j-1)] + Source[(i+1)*width+(j-1)] -\
(Source[(i-1)*width+(j+1)] + Source[(i)*width+(j+1)] + Source[(i+1)*width+(j+1)]));
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gpu_sobel_kernel_naive(u_char *Source, u_char *Resultat, unsigned width, unsigned height) {
int j = blockIdx.x*blockDim.x + threadIdx.x;
int i = blockIdx.y*blockDim.y + threadIdx.y;
u_char val;
int globalIndex = i*width+j;
if ((i==0)||(i>=height-1)||(j==0)||(j>=width-1)) {Resultat[globalIndex]=0;}
else {
val = std::abs(Source[(i-1)*width+(j-1)] + Source[(i-1)*width+(j)] + Source[(i-1)*width+(j+1)] -\
(Source[(i+1)*width+(j-1)] + Source[(i+1)*width+(j)] + Source[(i+1)*width+(j+1)]));
Resultat[globalIndex] = val + std::abs(Source[(i-1)*width+(j-1)] + Source[(i)*width+(j-1)] + Source[(i+1)*width+(j-1)] -\
(Source[(i-1)*width+(j+1)] + Source[(i)*width+(j+1)] + Source[(i+1)*width+(j+1)]));
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gpu_sobel_kernel_naive(u_char *Source, u_char *Resultat, unsigned width, unsigned height) {
int j = blockIdx.x*blockDim.x + threadIdx.x;
int i = blockIdx.y*blockDim.y + threadIdx.y;
u_char val;
int globalIndex = i*width+j;
if ((i==0)||(i>=height-1)||(j==0)||(j>=width-1)) {Resultat[globalIndex]=0;}
else {
val = std::abs(Source[(i-1)*width+(j-1)] + Source[(i-1)*width+(j)] + Source[(i-1)*width+(j+1)] -\
(Source[(i+1)*width+(j-1)] + Source[(i+1)*width+(j)] + Source[(i+1)*width+(j+1)]));
Resultat[globalIndex] = val + std::abs(Source[(i-1)*width+(j-1)] + Source[(i)*width+(j-1)] + Source[(i+1)*width+(j-1)] -\
(Source[(i-1)*width+(j+1)] + Source[(i)*width+(j+1)] + Source[(i+1)*width+(j+1)]));
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22gpu_sobel_kernel_naivePhS_jj
.globl _Z22gpu_sobel_kernel_naivePhS_jj
.p2align 8
.type _Z22gpu_sobel_kernel_naivePhS_jj,@function
_Z22gpu_sobel_kernel_naivePhS_jj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
v_and_b32_e32 v3, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[0:1], null, s14, s2, v[3:4]
v_mul_lo_u32 v1, v2, s4
v_mov_b32_e32 v3, 0
v_cmpx_ne_u32_e32 0, v2
s_cbranch_execz .LBB0_4
s_load_b32 s2, s[0:1], 0x14
s_add_i32 s3, s4, -1
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_gt_u32_e32 vcc_lo, s2, v2
v_cmp_gt_u32_e64 s2, s3, v0
v_cmp_ne_u32_e64 s3, 0, v0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_3
s_load_b64 s[6:7], s[0:1], 0x0
v_add_nc_u32_e32 v5, -1, v2
v_mad_u64_u32 v[3:4], null, s4, v2, s[4:5]
v_add_nc_u32_e32 v6, -1, v0
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_lo_u32 v2, v5, s4
v_add_nc_u32_e32 v5, v1, v6
v_add_nc_u32_e32 v8, v3, v6
s_delay_alu instid0(VALU_DEP_4)
v_add_nc_u32_e32 v7, v1, v4
v_add_nc_u32_e32 v10, v3, v0
v_add_nc_u32_e32 v3, v3, v4
v_add_nc_u32_e32 v6, v2, v6
v_add_nc_u32_e32 v9, v2, v0
v_add_nc_u32_e32 v2, v2, v4
s_waitcnt lgkmcnt(0)
s_clause 0x7
global_load_u8 v4, v6, s[6:7]
global_load_u8 v6, v9, s[6:7]
global_load_u8 v2, v2, s[6:7]
global_load_u8 v8, v8, s[6:7]
global_load_u8 v9, v10, s[6:7]
global_load_u8 v3, v3, s[6:7]
global_load_u8 v5, v5, s[6:7]
global_load_u8 v7, v7, s[6:7]
s_waitcnt vmcnt(5)
v_add3_u32 v6, v6, v4, v2
s_waitcnt vmcnt(2)
v_add3_u32 v9, v8, v9, v3
s_waitcnt vmcnt(1)
v_add3_u32 v4, v4, v8, v5
s_waitcnt vmcnt(0)
v_add3_u32 v2, v2, v3, v7
v_sub_nc_u32_e32 v3, v6, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v4, v2
v_sub_nc_u32_e32 v4, 0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v5, 0, v2
v_max_i32_e32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v2, v2, v5
v_add_nc_u32_e32 v3, v2, v3
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
s_or_b32 exec_lo, exec_lo, s5
s_load_b64 s[0:1], s[0:1], 0x8
v_add_nc_u32_e32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b8 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22gpu_sobel_kernel_naivePhS_jj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22gpu_sobel_kernel_naivePhS_jj, .Lfunc_end0-_Z22gpu_sobel_kernel_naivePhS_jj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22gpu_sobel_kernel_naivePhS_jj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z22gpu_sobel_kernel_naivePhS_jj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gpu_sobel_kernel_naive(u_char *Source, u_char *Resultat, unsigned width, unsigned height) {
int j = blockIdx.x*blockDim.x + threadIdx.x;
int i = blockIdx.y*blockDim.y + threadIdx.y;
u_char val;
int globalIndex = i*width+j;
if ((i==0)||(i>=height-1)||(j==0)||(j>=width-1)) {Resultat[globalIndex]=0;}
else {
val = std::abs(Source[(i-1)*width+(j-1)] + Source[(i-1)*width+(j)] + Source[(i-1)*width+(j+1)] -\
(Source[(i+1)*width+(j-1)] + Source[(i+1)*width+(j)] + Source[(i+1)*width+(j+1)]));
Resultat[globalIndex] = val + std::abs(Source[(i-1)*width+(j-1)] + Source[(i)*width+(j-1)] + Source[(i+1)*width+(j-1)] -\
(Source[(i-1)*width+(j+1)] + Source[(i)*width+(j+1)] + Source[(i+1)*width+(j+1)]));
}
} | .text
.file "gpu_sobel_kernel_naive.hip"
.globl _Z37__device_stub__gpu_sobel_kernel_naivePhS_jj # -- Begin function _Z37__device_stub__gpu_sobel_kernel_naivePhS_jj
.p2align 4, 0x90
.type _Z37__device_stub__gpu_sobel_kernel_naivePhS_jj,@function
_Z37__device_stub__gpu_sobel_kernel_naivePhS_jj: # @_Z37__device_stub__gpu_sobel_kernel_naivePhS_jj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22gpu_sobel_kernel_naivePhS_jj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z37__device_stub__gpu_sobel_kernel_naivePhS_jj, .Lfunc_end0-_Z37__device_stub__gpu_sobel_kernel_naivePhS_jj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22gpu_sobel_kernel_naivePhS_jj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22gpu_sobel_kernel_naivePhS_jj,@object # @_Z22gpu_sobel_kernel_naivePhS_jj
.section .rodata,"a",@progbits
.globl _Z22gpu_sobel_kernel_naivePhS_jj
.p2align 3, 0x0
_Z22gpu_sobel_kernel_naivePhS_jj:
.quad _Z37__device_stub__gpu_sobel_kernel_naivePhS_jj
.size _Z22gpu_sobel_kernel_naivePhS_jj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z22gpu_sobel_kernel_naivePhS_jj"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__gpu_sobel_kernel_naivePhS_jj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22gpu_sobel_kernel_naivePhS_jj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z22gpu_sobel_kernel_naivePhS_jj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002600 */
/*0020*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe20000000000 */
/*0030*/ BSSY B0, 0x460 ; /* 0x0000042000007945 */
/* 0x000fe20003800000 */
/*0040*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002200 */
/*0060*/ UIADD3 UR4, -UR5, UR7, URZ ; /* 0x0000000705047290 */
/* 0x000fe2000fffe13f */
/*0070*/ PRMT R4, RZ, 0x7610, R4 ; /* 0x00007610ff047816 */
/* 0x000fe40000000004 */
/*0080*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0090*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*00a0*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x001fca00078e0202 */
/*00b0*/ ISETP.GE.U32.AND P0, PT, R5.reuse, UR4, PT ; /* 0x0000000405007c0c */
/* 0x040fe2000bf06070 */
/*00c0*/ UIADD3 UR4, -UR5, UR6, URZ ; /* 0x0000000605047290 */
/* 0x000fe2000fffe13f */
/*00d0*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fe400078e0203 */
/*00e0*/ ISETP.EQ.OR P0, PT, R5.reuse, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x040fe40000702670 */
/*00f0*/ IMAD R3, R5, c[0x0][0x170], R0 ; /* 0x00005c0005037a24 */
/* 0x000fe400078e0200 */
/*0100*/ ISETP.EQ.OR P0, PT, R0, RZ, P0 ; /* 0x000000ff0000720c */
/* 0x000fc80000702670 */
/*0110*/ ISETP.GE.U32.OR P0, PT, R0, UR4, P0 ; /* 0x0000000400007c0c */
/* 0x000fe20008706470 */
/*0120*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0130*/ IADD3 R2, P1, R3, c[0x0][0x168], RZ ; /* 0x00005a0003027a10 */
/* 0x000fc80007f3e0ff */
/*0140*/ LEA.HI.X.SX32 R3, R3, c[0x0][0x16c], 0x1, P1 ; /* 0x00005b0003037a11 */
/* 0x000fce00008f0eff */
/*0150*/ @P0 BRA 0x450 ; /* 0x000002f000000947 */
/* 0x000fea0003800000 */
/*0160*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */
/* 0x000fe200078e00ff */
/*0170*/ IADD3 R8, R0.reuse, -0x1, RZ ; /* 0xffffffff00087810 */
/* 0x040fe40007ffe0ff */
/*0180*/ IADD3 R12, R0, 0x1, RZ ; /* 0x00000001000c7810 */
/* 0x000fe20007ffe0ff */
/*0190*/ IMAD R7, R5.reuse, R6, -c[0x0][0x170] ; /* 0x80005c0005077624 */
/* 0x040fe400078e0206 */
/*01a0*/ IMAD R4, R5, c[0x0][0x170], R8.reuse ; /* 0x00005c0005047a24 */
/* 0x100fe400078e0208 */
/*01b0*/ IMAD R11, R6, 0x2, R7.reuse ; /* 0x00000002060b7824 */
/* 0x100fe400078e0207 */
/*01c0*/ IMAD.IADD R6, R7.reuse, 0x1, R8 ; /* 0x0000000107067824 */
/* 0x040fe200078e0208 */
/*01d0*/ IADD3 R4, P1, R4, c[0x0][0x160], RZ ; /* 0x0000580004047a10 */
/* 0x000fe20007f3e0ff */
/*01e0*/ IMAD.IADD R10, R0.reuse, 0x1, R7 ; /* 0x00000001000a7824 */
/* 0x040fe200078e0207 */
/*01f0*/ IADD3 R0, R0, R11, RZ ; /* 0x0000000b00007210 */
/* 0x000fe20007ffe0ff */
/*0200*/ IMAD.IADD R9, R7, 0x1, R12.reuse ; /* 0x0000000107097824 */
/* 0x100fe200078e020c */
/*0210*/ IADD3 R6, P0, R6, c[0x0][0x160], RZ ; /* 0x0000580006067a10 */
/* 0x000fe20007f1e0ff */
/*0220*/ IMAD R18, R5, c[0x0][0x170], R12 ; /* 0x00005c0005127a24 */
/* 0x000fc400078e020c */
/*0230*/ IMAD.IADD R13, R8, 0x1, R11.reuse ; /* 0x00000001080d7824 */
/* 0x100fe400078e020b */
/*0240*/ IMAD.X R5, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff057624 */
/* 0x000fe200008e06ff */
/*0250*/ IADD3 R10, P1, R10, c[0x0][0x160], RZ ; /* 0x000058000a0a7a10 */
/* 0x000fe20007f3e0ff */
/*0260*/ IMAD.X R7, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff077624 */
/* 0x000fe200000e06ff */
/*0270*/ IADD3 R8, P0, R9, c[0x0][0x160], RZ ; /* 0x0000580009087a10 */
/* 0x000fe20007f1e0ff */
/*0280*/ IMAD.IADD R16, R12, 0x1, R11 ; /* 0x000000010c107824 */
/* 0x000fe200078e020b */
/*0290*/ IADD3 R12, P2, R13, c[0x0][0x160], RZ ; /* 0x000058000d0c7a10 */
/* 0x000fe20007f5e0ff */
/*02a0*/ IMAD.X R11, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff0b7624 */
/* 0x000fe200008e06ff */
/*02b0*/ IADD3.X R9, RZ, c[0x0][0x164], RZ, P0, !PT ; /* 0x00005900ff097a10 */
/* 0x000fe200007fe4ff */
/*02c0*/ LDG.E.U8 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1100 */
/*02d0*/ IADD3 R14, P1, R0, c[0x0][0x160], RZ ; /* 0x00005800000e7a10 */
/* 0x000fe20007f3e0ff */
/*02e0*/ IMAD.X R13, RZ, RZ, c[0x0][0x164], P2 ; /* 0x00005900ff0d7624 */
/* 0x000fe200010e06ff */
/*02f0*/ IADD3 R18, P0, R18, c[0x0][0x160], RZ ; /* 0x0000580012127a10 */
/* 0x000fe20007f1e0ff */
/*0300*/ LDG.E.U8 R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000ea2000c1e1100 */
/*0310*/ IADD3 R16, P2, R16, c[0x0][0x160], RZ ; /* 0x0000580010107a10 */
/* 0x000fe20007f5e0ff */
/*0320*/ IMAD.X R15, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff0f7624 */
/* 0x000fc400008e06ff */
/*0330*/ LDG.E.U8 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1100 */
/*0340*/ IMAD.X R19, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff137624 */
/* 0x000fe400000e06ff */
/*0350*/ IMAD.X R17, RZ, RZ, c[0x0][0x164], P2 ; /* 0x00005900ff117624 */
/* 0x000fe200010e06ff */
/*0360*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee8000c1e1100 */
/*0370*/ LDG.E.U8 R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000ee8000c1e1100 */
/*0380*/ LDG.E.U8 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f28000c1e1100 */
/*0390*/ LDG.E.U8 R19, [R18.64] ; /* 0x0000000412137981 */
/* 0x000f68000c1e1100 */
/*03a0*/ LDG.E.U8 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f62000c1e1100 */
/*03b0*/ IADD3 R11, R8, R11, R6 ; /* 0x0000000b080b7210 */
/* 0x004fc40007ffe006 */
/*03c0*/ IADD3 R4, R13, R4, R6 ; /* 0x000000040d047210 */
/* 0x008fe40007ffe006 */
/*03d0*/ IADD3 R11, -R14, R11, -R13 ; /* 0x0000000b0e0b7210 */
/* 0x010fe40007ffe90d */
/*03e0*/ IADD3 R5, -R19, R4, -R8 ; /* 0x0000000413057210 */
/* 0x020fe40007ffe908 */
/*03f0*/ IADD3 R11, -R16, R11, RZ ; /* 0x0000000b100b7210 */
/* 0x000fc60007ffe1ff */
/*0400*/ IMAD.IADD R5, R5, 0x1, -R16 ; /* 0x0000000105057824 */
/* 0x000fe200078e0a10 */
/*0410*/ IABS R11, R11 ; /* 0x0000000b000b7213 */
/* 0x000fc80000000000 */
/*0420*/ IABS R4, R5 ; /* 0x0000000500047213 */
/* 0x000fe20000000000 */
/*0430*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fc800078e000b */
/*0440*/ IMAD.IADD R4, R4, 0x1, R5 ; /* 0x0000000104047824 */
/* 0x000fe400078e0205 */
/*0450*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0460*/ STG.E.U8 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101104 */
/*0470*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0480*/ BRA 0x480; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22gpu_sobel_kernel_naivePhS_jj
.globl _Z22gpu_sobel_kernel_naivePhS_jj
.p2align 8
.type _Z22gpu_sobel_kernel_naivePhS_jj,@function
_Z22gpu_sobel_kernel_naivePhS_jj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
v_and_b32_e32 v3, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[0:1], null, s14, s2, v[3:4]
v_mul_lo_u32 v1, v2, s4
v_mov_b32_e32 v3, 0
v_cmpx_ne_u32_e32 0, v2
s_cbranch_execz .LBB0_4
s_load_b32 s2, s[0:1], 0x14
s_add_i32 s3, s4, -1
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_gt_u32_e32 vcc_lo, s2, v2
v_cmp_gt_u32_e64 s2, s3, v0
v_cmp_ne_u32_e64 s3, 0, v0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_3
s_load_b64 s[6:7], s[0:1], 0x0
v_add_nc_u32_e32 v5, -1, v2
v_mad_u64_u32 v[3:4], null, s4, v2, s[4:5]
v_add_nc_u32_e32 v6, -1, v0
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_lo_u32 v2, v5, s4
v_add_nc_u32_e32 v5, v1, v6
v_add_nc_u32_e32 v8, v3, v6
s_delay_alu instid0(VALU_DEP_4)
v_add_nc_u32_e32 v7, v1, v4
v_add_nc_u32_e32 v10, v3, v0
v_add_nc_u32_e32 v3, v3, v4
v_add_nc_u32_e32 v6, v2, v6
v_add_nc_u32_e32 v9, v2, v0
v_add_nc_u32_e32 v2, v2, v4
s_waitcnt lgkmcnt(0)
s_clause 0x7
global_load_u8 v4, v6, s[6:7]
global_load_u8 v6, v9, s[6:7]
global_load_u8 v2, v2, s[6:7]
global_load_u8 v8, v8, s[6:7]
global_load_u8 v9, v10, s[6:7]
global_load_u8 v3, v3, s[6:7]
global_load_u8 v5, v5, s[6:7]
global_load_u8 v7, v7, s[6:7]
s_waitcnt vmcnt(5)
v_add3_u32 v6, v6, v4, v2
s_waitcnt vmcnt(2)
v_add3_u32 v9, v8, v9, v3
s_waitcnt vmcnt(1)
v_add3_u32 v4, v4, v8, v5
s_waitcnt vmcnt(0)
v_add3_u32 v2, v2, v3, v7
v_sub_nc_u32_e32 v3, v6, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v4, v2
v_sub_nc_u32_e32 v4, 0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v5, 0, v2
v_max_i32_e32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v2, v2, v5
v_add_nc_u32_e32 v3, v2, v3
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
s_or_b32 exec_lo, exec_lo, s5
s_load_b64 s[0:1], s[0:1], 0x8
v_add_nc_u32_e32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b8 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22gpu_sobel_kernel_naivePhS_jj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22gpu_sobel_kernel_naivePhS_jj, .Lfunc_end0-_Z22gpu_sobel_kernel_naivePhS_jj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22gpu_sobel_kernel_naivePhS_jj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z22gpu_sobel_kernel_naivePhS_jj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00073295_00000000-6_gpu_sobel_kernel_naive.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z22gpu_sobel_kernel_naivePhS_jjPhS_jj
.type _Z46__device_stub__Z22gpu_sobel_kernel_naivePhS_jjPhS_jj, @function
_Z46__device_stub__Z22gpu_sobel_kernel_naivePhS_jjPhS_jj:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22gpu_sobel_kernel_naivePhS_jj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z22gpu_sobel_kernel_naivePhS_jjPhS_jj, .-_Z46__device_stub__Z22gpu_sobel_kernel_naivePhS_jjPhS_jj
.globl _Z22gpu_sobel_kernel_naivePhS_jj
.type _Z22gpu_sobel_kernel_naivePhS_jj, @function
_Z22gpu_sobel_kernel_naivePhS_jj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z22gpu_sobel_kernel_naivePhS_jjPhS_jj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z22gpu_sobel_kernel_naivePhS_jj, .-_Z22gpu_sobel_kernel_naivePhS_jj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z22gpu_sobel_kernel_naivePhS_jj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z22gpu_sobel_kernel_naivePhS_jj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gpu_sobel_kernel_naive.hip"
.globl _Z37__device_stub__gpu_sobel_kernel_naivePhS_jj # -- Begin function _Z37__device_stub__gpu_sobel_kernel_naivePhS_jj
.p2align 4, 0x90
.type _Z37__device_stub__gpu_sobel_kernel_naivePhS_jj,@function
_Z37__device_stub__gpu_sobel_kernel_naivePhS_jj: # @_Z37__device_stub__gpu_sobel_kernel_naivePhS_jj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22gpu_sobel_kernel_naivePhS_jj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z37__device_stub__gpu_sobel_kernel_naivePhS_jj, .Lfunc_end0-_Z37__device_stub__gpu_sobel_kernel_naivePhS_jj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22gpu_sobel_kernel_naivePhS_jj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22gpu_sobel_kernel_naivePhS_jj,@object # @_Z22gpu_sobel_kernel_naivePhS_jj
.section .rodata,"a",@progbits
.globl _Z22gpu_sobel_kernel_naivePhS_jj
.p2align 3, 0x0
_Z22gpu_sobel_kernel_naivePhS_jj:
.quad _Z37__device_stub__gpu_sobel_kernel_naivePhS_jj
.size _Z22gpu_sobel_kernel_naivePhS_jj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z22gpu_sobel_kernel_naivePhS_jj"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__gpu_sobel_kernel_naivePhS_jj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22gpu_sobel_kernel_naivePhS_jj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* JCuda - Java bindings for NVIDIA CUDA driver and runtime API
* http://www.jcuda.org
*
*
* This code is based on the NVIDIA 'reduction' CUDA sample,
* Copyright 1993-2010 NVIDIA Corporation.
*/
extern "C"
__global__ void reduce(float *g_idata, float *g_odata, unsigned int n)
{
extern __shared__ float sdata[];
// perform first level of reduction,
// reading from global memory, writing to shared memory
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*blockDim.x*2 + threadIdx.x;
unsigned int gridSize = blockDim.x*2*gridDim.x;
float mySum = 0;
// we reduce multiple elements per thread. The number is determined by the
// number of active thread blocks (via gridDim). More blocks will result
// in a larger gridSize and therefore fewer elements per thread
while (i < n)
{
mySum += g_idata[i];
// ensure we don't read out of bounds
if (i + blockDim.x < n)
mySum += g_idata[i+blockDim.x];
i += gridSize;
}
// each thread puts its local sum into shared memory
sdata[tid] = mySum;
__syncthreads();
// do reduction in shared mem
if (blockDim.x >= 512) { if (tid < 256) { sdata[tid] = mySum = mySum + sdata[tid + 256]; } __syncthreads(); }
if (blockDim.x >= 256) { if (tid < 128) { sdata[tid] = mySum = mySum + sdata[tid + 128]; } __syncthreads(); }
if (blockDim.x >= 128) { if (tid < 64) { sdata[tid] = mySum = mySum + sdata[tid + 64]; } __syncthreads(); }
if (tid < 32)
{
// now that we are using warp-synchronous programming (below)
// we need to declare our shared memory volatile so that the compiler
// doesn't reorder stores to it and induce incorrect behavior.
volatile float* smem = sdata;
if (blockDim.x >= 64) { smem[tid] = mySum = mySum + smem[tid + 32]; }
if (blockDim.x >= 32) { smem[tid] = mySum = mySum + smem[tid + 16]; }
if (blockDim.x >= 16) { smem[tid] = mySum = mySum + smem[tid + 8]; }
if (blockDim.x >= 8) { smem[tid] = mySum = mySum + smem[tid + 4]; }
if (blockDim.x >= 4) { smem[tid] = mySum = mySum + smem[tid + 2]; }
if (blockDim.x >= 2) { smem[tid] = mySum = mySum + smem[tid + 1]; }
}
// write result for this block to global mem
if (tid == 0)
g_odata[blockIdx.x] = sdata[0];
} | code for sm_80
Function : reduce
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff087624 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002100 */
/*0060*/ BSSY B0, 0x200 ; /* 0x0000019000007945 */
/* 0x000fe20003800000 */
/*0070*/ SHF.L.U32 R0, R0, 0x1, RZ ; /* 0x0000000100007819 */
/* 0x000fe200000006ff */
/*0080*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x000fe200000001ff */
/*0090*/ ISETP.GE.U32.AND P4, PT, R8.reuse, 0x200, PT ; /* 0x000002000800780c */
/* 0x040fe40003f86070 */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R8, 0x100, PT ; /* 0x000001000800780c */
/* 0x000fc40003f06070 */
/*00b0*/ ISETP.GE.U32.AND P1, PT, R8, 0x80, PT ; /* 0x000000800800780c */
/* 0x000fe20003f26070 */
/*00c0*/ IMAD R2, R0, R9, R11 ; /* 0x0000000900027224 */
/* 0x001fe200078e020b */
/*00d0*/ ISETP.GT.U32.AND P2, PT, R11.reuse, 0x1f, PT ; /* 0x0000001f0b00780c */
/* 0x040fe40003f44070 */
/*00e0*/ ISETP.NE.AND P3, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f65270 */
/*00f0*/ ISETP.GE.U32.AND P5, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003fa6070 */
/*0100*/ @P5 BRA 0x1f0 ; /* 0x000000e000005947 */
/* 0x000fea0003800000 */
/*0110*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*0120*/ MOV R6, RZ ; /* 0x000000ff00067202 */
/* 0x000fc80000000f00 */
/*0130*/ IADD3 R5, R7, c[0x0][0x0], RZ ; /* 0x0000000007057a10 */
/* 0x000fe20007ffe0ff */
/*0140*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc600078e00ff */
/*0150*/ ISETP.GE.U32.AND P5, PT, R5, c[0x0][0x170], PT ; /* 0x00005c0005007a0c */
/* 0x000fe20003fa6070 */
/*0160*/ IMAD.WIDE.U32 R2, R7, R4, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x000fcc00078e0004 */
/*0170*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000eac000c1e1900 */
/*0180*/ @!P5 IMAD.WIDE.U32 R4, R5, R4, c[0x0][0x160] ; /* 0x000058000504d625 */
/* 0x000fcc00078e0004 */
/*0190*/ @!P5 LDG.E R5, [R4.64] ; /* 0x000000040405d981 */
/* 0x000ee2000c1e1900 */
/*01a0*/ IMAD R7, R0, c[0x0][0xc], R7 ; /* 0x0000030000077a24 */
/* 0x000fca00078e0207 */
/*01b0*/ ISETP.GE.U32.AND P6, PT, R7, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x000fe20003fc6070 */
/*01c0*/ FADD R6, R3, R6 ; /* 0x0000000603067221 */
/* 0x004fc80000000000 */
/*01d0*/ @!P5 FADD R6, R6, R5 ; /* 0x000000050606d221 */
/* 0x008fd00000000000 */
/*01e0*/ @!P6 BRA 0x130 ; /* 0xffffff400000e947 */
/* 0x000fea000383ffff */
/*01f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0200*/ STS [R11.X4], R6 ; /* 0x000000060b007388 */
/* 0x0001e20000004800 */
/*0210*/ MOV R3, R6 ; /* 0x0000000600037202 */
/* 0x000fc60000000f00 */
/*0220*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0230*/ @!P4 BRA 0x290 ; /* 0x000000500000c947 */
/* 0x000fea0003800000 */
/*0240*/ ISETP.GT.U32.AND P4, PT, R11, 0xff, PT ; /* 0x000000ff0b00780c */
/* 0x001fda0003f84070 */
/*0250*/ @!P4 LDS R0, [R11.X4+0x400] ; /* 0x000400000b00c984 */
/* 0x000e240000004800 */
/*0260*/ @!P4 FADD R3, R0, R3 ; /* 0x000000030003c221 */
/* 0x001fca0000000000 */
/*0270*/ @!P4 STS [R11.X4], R3 ; /* 0x000000030b00c388 */
/* 0x0001e80000004800 */
/*0280*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0290*/ @!P0 BRA 0x2f0 ; /* 0x0000005000008947 */
/* 0x001fea0003800000 */
/*02a0*/ ISETP.GT.U32.AND P0, PT, R11, 0x7f, PT ; /* 0x0000007f0b00780c */
/* 0x000fda0003f04070 */
/*02b0*/ @!P0 LDS R0, [R11.X4+0x200] ; /* 0x000200000b008984 */
/* 0x000e240000004800 */
/*02c0*/ @!P0 FADD R3, R0, R3 ; /* 0x0000000300038221 */
/* 0x001fca0000000000 */
/*02d0*/ @!P0 STS [R11.X4], R3 ; /* 0x000000030b008388 */
/* 0x0001e80000004800 */
/*02e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02f0*/ @!P1 BRA 0x350 ; /* 0x0000005000009947 */
/* 0x000fea0003800000 */
/*0300*/ ISETP.GT.U32.AND P0, PT, R11, 0x3f, PT ; /* 0x0000003f0b00780c */
/* 0x000fda0003f04070 */
/*0310*/ @!P0 LDS R0, [R11.X4+0x100] ; /* 0x000100000b008984 */
/* 0x000e640000004800 */
/*0320*/ @!P0 FADD R3, R0, R3 ; /* 0x0000000300038221 */
/* 0x003fca0000000000 */
/*0330*/ @!P0 STS [R11.X4], R3 ; /* 0x000000030b008388 */
/* 0x0001e80000004800 */
/*0340*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0350*/ BSSY B0, 0x500 ; /* 0x000001a000007945 */
/* 0x000fe20003800000 */
/*0360*/ @P2 BRA 0x4f0 ; /* 0x0000018000002947 */
/* 0x000fea0003800000 */
/*0370*/ ISETP.GE.U32.AND P0, PT, R8.reuse, 0x40, PT ; /* 0x000000400800780c */
/* 0x040fe40003f06070 */
/*0380*/ ISETP.GE.U32.AND P1, PT, R8, 0x20, PT ; /* 0x000000200800780c */
/* 0x000fd60003f26070 */
/*0390*/ @P0 LDS R0, [R11.X4+0x80] ; /* 0x000080000b000984 */
/* 0x000e640000004800 */
/*03a0*/ @P0 FADD R3, R0, R3 ; /* 0x0000000300030221 */
/* 0x003fca0000000000 */
/*03b0*/ @P0 STS [R11.X4], R3 ; /* 0x000000030b000388 */
/* 0x000fe20000004800 */
/*03c0*/ ISETP.GE.U32.AND P0, PT, R8, 0x10, PT ; /* 0x000000100800780c */
/* 0x000fc60003f06070 */
/*03d0*/ @P1 LDS R0, [R11.X4+0x40] ; /* 0x000040000b001984 */
/* 0x000e240000004800 */
/*03e0*/ @P1 FADD R3, R0, R3 ; /* 0x0000000300031221 */
/* 0x001fca0000000000 */
/*03f0*/ @P1 STS [R11.X4], R3 ; /* 0x000000030b001388 */
/* 0x000fe20000004800 */
/*0400*/ ISETP.GE.U32.AND P1, PT, R8, 0x8, PT ; /* 0x000000080800780c */
/* 0x000fc60003f26070 */
/*0410*/ @P0 LDS R0, [R11.X4+0x20] ; /* 0x000020000b000984 */
/* 0x000e240000004800 */
/*0420*/ @P0 FADD R3, R0, R3 ; /* 0x0000000300030221 */
/* 0x001fca0000000000 */
/*0430*/ @P0 STS [R11.X4], R3 ; /* 0x000000030b000388 */
/* 0x000fe20000004800 */
/*0440*/ ISETP.GE.U32.AND P0, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fc60003f06070 */
/*0450*/ @P1 LDS R0, [R11.X4+0x10] ; /* 0x000010000b001984 */
/* 0x000e240000004800 */
/*0460*/ @P1 FADD R3, R0, R3 ; /* 0x0000000300031221 */
/* 0x001fca0000000000 */
/*0470*/ @P1 STS [R11.X4], R3 ; /* 0x000000030b001388 */
/* 0x000fe20000004800 */
/*0480*/ ISETP.GE.U32.AND P1, PT, R8, 0x2, PT ; /* 0x000000020800780c */
/* 0x000fc60003f26070 */
/*0490*/ @P0 LDS R0, [R11.X4+0x8] ; /* 0x000008000b000984 */
/* 0x000e240000004800 */
/*04a0*/ @P0 FADD R3, R0, R3 ; /* 0x0000000300030221 */
/* 0x001fca0000000000 */
/*04b0*/ @P0 STS [R11.X4], R3 ; /* 0x000000030b000388 */
/* 0x000fe80000004800 */
/*04c0*/ @P1 LDS R0, [R11.X4+0x4] ; /* 0x000004000b001984 */
/* 0x000e240000004800 */
/*04d0*/ @P1 FADD R0, R0, R3 ; /* 0x0000000300001221 */
/* 0x001fca0000000000 */
/*04e0*/ @P1 STS [R11.X4], R0 ; /* 0x000000000b001388 */
/* 0x0001e40000004800 */
/*04f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0500*/ @P3 EXIT ; /* 0x000000000000394d */
/* 0x000fea0003800000 */
/*0510*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e620000000800 */
/*0520*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc800078e00ff */
/*0530*/ IMAD.WIDE.U32 R2, R9, R2, c[0x0][0x168] ; /* 0x00005a0009027625 */
/* 0x001fca00078e0002 */
/*0540*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe2000c101904 */
/*0550*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0560*/ BRA 0x560; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* JCuda - Java bindings for NVIDIA CUDA driver and runtime API
* http://www.jcuda.org
*
*
* This code is based on the NVIDIA 'reduction' CUDA sample,
* Copyright 1993-2010 NVIDIA Corporation.
*/
extern "C"
__global__ void reduce(float *g_idata, float *g_odata, unsigned int n)
{
extern __shared__ float sdata[];
// perform first level of reduction,
// reading from global memory, writing to shared memory
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*blockDim.x*2 + threadIdx.x;
unsigned int gridSize = blockDim.x*2*gridDim.x;
float mySum = 0;
// we reduce multiple elements per thread. The number is determined by the
// number of active thread blocks (via gridDim). More blocks will result
// in a larger gridSize and therefore fewer elements per thread
while (i < n)
{
mySum += g_idata[i];
// ensure we don't read out of bounds
if (i + blockDim.x < n)
mySum += g_idata[i+blockDim.x];
i += gridSize;
}
// each thread puts its local sum into shared memory
sdata[tid] = mySum;
__syncthreads();
// do reduction in shared mem
if (blockDim.x >= 512) { if (tid < 256) { sdata[tid] = mySum = mySum + sdata[tid + 256]; } __syncthreads(); }
if (blockDim.x >= 256) { if (tid < 128) { sdata[tid] = mySum = mySum + sdata[tid + 128]; } __syncthreads(); }
if (blockDim.x >= 128) { if (tid < 64) { sdata[tid] = mySum = mySum + sdata[tid + 64]; } __syncthreads(); }
if (tid < 32)
{
// now that we are using warp-synchronous programming (below)
// we need to declare our shared memory volatile so that the compiler
// doesn't reorder stores to it and induce incorrect behavior.
volatile float* smem = sdata;
if (blockDim.x >= 64) { smem[tid] = mySum = mySum + smem[tid + 32]; }
if (blockDim.x >= 32) { smem[tid] = mySum = mySum + smem[tid + 16]; }
if (blockDim.x >= 16) { smem[tid] = mySum = mySum + smem[tid + 8]; }
if (blockDim.x >= 8) { smem[tid] = mySum = mySum + smem[tid + 4]; }
if (blockDim.x >= 4) { smem[tid] = mySum = mySum + smem[tid + 2]; }
if (blockDim.x >= 2) { smem[tid] = mySum = mySum + smem[tid + 1]; }
}
// write result for this block to global mem
if (tid == 0)
g_odata[blockIdx.x] = sdata[0];
} | .file "tmpxft_00161766_00000000-6_JCudaReductionKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z6reducePfS_jPfS_j
.type _Z28__device_stub__Z6reducePfS_jPfS_j, @function
_Z28__device_stub__Z6reducePfS_jPfS_j:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq reduce(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z6reducePfS_jPfS_j, .-_Z28__device_stub__Z6reducePfS_jPfS_j
.globl reduce
.type reduce, @function
reduce:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z6reducePfS_jPfS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size reduce, .-reduce
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "reduce"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq reduce(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* JCuda - Java bindings for NVIDIA CUDA driver and runtime API
* http://www.jcuda.org
*
*
* This code is based on the NVIDIA 'reduction' CUDA sample,
* Copyright 1993-2010 NVIDIA Corporation.
*/
extern "C"
__global__ void reduce(float *g_idata, float *g_odata, unsigned int n)
{
extern __shared__ float sdata[];
// perform first level of reduction,
// reading from global memory, writing to shared memory
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*blockDim.x*2 + threadIdx.x;
unsigned int gridSize = blockDim.x*2*gridDim.x;
float mySum = 0;
// we reduce multiple elements per thread. The number is determined by the
// number of active thread blocks (via gridDim). More blocks will result
// in a larger gridSize and therefore fewer elements per thread
while (i < n)
{
mySum += g_idata[i];
// ensure we don't read out of bounds
if (i + blockDim.x < n)
mySum += g_idata[i+blockDim.x];
i += gridSize;
}
// each thread puts its local sum into shared memory
sdata[tid] = mySum;
__syncthreads();
// do reduction in shared mem
if (blockDim.x >= 512) { if (tid < 256) { sdata[tid] = mySum = mySum + sdata[tid + 256]; } __syncthreads(); }
if (blockDim.x >= 256) { if (tid < 128) { sdata[tid] = mySum = mySum + sdata[tid + 128]; } __syncthreads(); }
if (blockDim.x >= 128) { if (tid < 64) { sdata[tid] = mySum = mySum + sdata[tid + 64]; } __syncthreads(); }
if (tid < 32)
{
// now that we are using warp-synchronous programming (below)
// we need to declare our shared memory volatile so that the compiler
// doesn't reorder stores to it and induce incorrect behavior.
volatile float* smem = sdata;
if (blockDim.x >= 64) { smem[tid] = mySum = mySum + smem[tid + 32]; }
if (blockDim.x >= 32) { smem[tid] = mySum = mySum + smem[tid + 16]; }
if (blockDim.x >= 16) { smem[tid] = mySum = mySum + smem[tid + 8]; }
if (blockDim.x >= 8) { smem[tid] = mySum = mySum + smem[tid + 4]; }
if (blockDim.x >= 4) { smem[tid] = mySum = mySum + smem[tid + 2]; }
if (blockDim.x >= 2) { smem[tid] = mySum = mySum + smem[tid + 1]; }
}
// write result for this block to global mem
if (tid == 0)
g_odata[blockIdx.x] = sdata[0];
} | #include <hip/hip_runtime.h>
/*
* JCuda - Java bindings for NVIDIA CUDA driver and runtime API
* http://www.jcuda.org
*
*
* This code is based on the NVIDIA 'reduction' CUDA sample,
* Copyright 1993-2010 NVIDIA Corporation.
*/
extern "C"
__global__ void reduce(float *g_idata, float *g_odata, unsigned int n)
{
extern __shared__ float sdata[];
// perform first level of reduction,
// reading from global memory, writing to shared memory
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*blockDim.x*2 + threadIdx.x;
unsigned int gridSize = blockDim.x*2*gridDim.x;
float mySum = 0;
// we reduce multiple elements per thread. The number is determined by the
// number of active thread blocks (via gridDim). More blocks will result
// in a larger gridSize and therefore fewer elements per thread
while (i < n)
{
mySum += g_idata[i];
// ensure we don't read out of bounds
if (i + blockDim.x < n)
mySum += g_idata[i+blockDim.x];
i += gridSize;
}
// each thread puts its local sum into shared memory
sdata[tid] = mySum;
__syncthreads();
// do reduction in shared mem
if (blockDim.x >= 512) { if (tid < 256) { sdata[tid] = mySum = mySum + sdata[tid + 256]; } __syncthreads(); }
if (blockDim.x >= 256) { if (tid < 128) { sdata[tid] = mySum = mySum + sdata[tid + 128]; } __syncthreads(); }
if (blockDim.x >= 128) { if (tid < 64) { sdata[tid] = mySum = mySum + sdata[tid + 64]; } __syncthreads(); }
if (tid < 32)
{
// now that we are using warp-synchronous programming (below)
// we need to declare our shared memory volatile so that the compiler
// doesn't reorder stores to it and induce incorrect behavior.
volatile float* smem = sdata;
if (blockDim.x >= 64) { smem[tid] = mySum = mySum + smem[tid + 32]; }
if (blockDim.x >= 32) { smem[tid] = mySum = mySum + smem[tid + 16]; }
if (blockDim.x >= 16) { smem[tid] = mySum = mySum + smem[tid + 8]; }
if (blockDim.x >= 8) { smem[tid] = mySum = mySum + smem[tid + 4]; }
if (blockDim.x >= 4) { smem[tid] = mySum = mySum + smem[tid + 2]; }
if (blockDim.x >= 2) { smem[tid] = mySum = mySum + smem[tid + 1]; }
}
// write result for this block to global mem
if (tid == 0)
g_odata[blockIdx.x] = sdata[0];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/*
* JCuda - Java bindings for NVIDIA CUDA driver and runtime API
* http://www.jcuda.org
*
*
* This code is based on the NVIDIA 'reduction' CUDA sample,
* Copyright 1993-2010 NVIDIA Corporation.
*/
extern "C"
__global__ void reduce(float *g_idata, float *g_odata, unsigned int n)
{
extern __shared__ float sdata[];
// perform first level of reduction,
// reading from global memory, writing to shared memory
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*blockDim.x*2 + threadIdx.x;
unsigned int gridSize = blockDim.x*2*gridDim.x;
float mySum = 0;
// we reduce multiple elements per thread. The number is determined by the
// number of active thread blocks (via gridDim). More blocks will result
// in a larger gridSize and therefore fewer elements per thread
while (i < n)
{
mySum += g_idata[i];
// ensure we don't read out of bounds
if (i + blockDim.x < n)
mySum += g_idata[i+blockDim.x];
i += gridSize;
}
// each thread puts its local sum into shared memory
sdata[tid] = mySum;
__syncthreads();
// do reduction in shared mem
if (blockDim.x >= 512) { if (tid < 256) { sdata[tid] = mySum = mySum + sdata[tid + 256]; } __syncthreads(); }
if (blockDim.x >= 256) { if (tid < 128) { sdata[tid] = mySum = mySum + sdata[tid + 128]; } __syncthreads(); }
if (blockDim.x >= 128) { if (tid < 64) { sdata[tid] = mySum = mySum + sdata[tid + 64]; } __syncthreads(); }
if (tid < 32)
{
// now that we are using warp-synchronous programming (below)
// we need to declare our shared memory volatile so that the compiler
// doesn't reorder stores to it and induce incorrect behavior.
volatile float* smem = sdata;
if (blockDim.x >= 64) { smem[tid] = mySum = mySum + smem[tid + 32]; }
if (blockDim.x >= 32) { smem[tid] = mySum = mySum + smem[tid + 16]; }
if (blockDim.x >= 16) { smem[tid] = mySum = mySum + smem[tid + 8]; }
if (blockDim.x >= 8) { smem[tid] = mySum = mySum + smem[tid + 4]; }
if (blockDim.x >= 4) { smem[tid] = mySum = mySum + smem[tid + 2]; }
if (blockDim.x >= 2) { smem[tid] = mySum = mySum + smem[tid + 1]; }
}
// write result for this block to global mem
if (tid == 0)
g_odata[blockIdx.x] = sdata[0];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected reduce
.globl reduce
.p2align 8
.type reduce,@function
reduce:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b32 s7, s[0:1], 0x10
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
s_lshl_b32 s10, s15, 1
v_mov_b32_e32 v3, 0
s_mov_b32 s2, s15
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s9, s10, s3
v_add_nc_u32_e32 v1, s9, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s7, v1
s_cbranch_execz .LBB0_6
s_load_b32 s11, s[4:5], 0x0
s_load_b64 s[4:5], s[0:1], 0x0
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0
v_mov_b32_e32 v4, v0
s_add_i32 s10, s10, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mul_i32 s10, s10, s3
s_waitcnt lgkmcnt(0)
s_mul_i32 s11, s11, s3
s_lshl_b32 s12, s11, 1
s_mov_b32 s11, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s13
v_add_nc_u32_e32 v4, s12, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, s9, v4
v_cmp_le_u32_e32 vcc_lo, s7, v1
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execz .LBB0_5
.LBB0_3:
v_add_nc_u32_e32 v1, s9, v4
s_mov_b32 s13, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_add_nc_u32_e32 v1, s10, v4
v_add_co_u32 v5, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, v3, v5
v_cmpx_gt_u32_e64 s7, v1
s_cbranch_execz .LBB0_2
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_load_b32 v1, v[5:6], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, v3, v1
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s11
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
s_or_b32 exec_lo, exec_lo, s8
v_cmp_gt_u16_e64 s4, 0x200, s6
v_lshl_add_u32 v1, v0, 2, 0
s_and_b32 vcc_lo, exec_lo, s4
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB0_10
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e32 0x100, v0
s_cbranch_execz .LBB0_9
v_lshl_add_u32 v2, v0, 2, 0
ds_load_b32 v2, v2 offset:1024
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v3, v3, v2
ds_store_b32 v1, v3
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_10:
v_cmp_gt_u16_e64 s5, 0x100, s6
s_and_b32 s4, 0xffff, s6
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB0_14
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e32 0x80, v0
s_cbranch_execz .LBB0_13
v_lshl_add_u32 v2, v0, 2, 0
ds_load_b32 v2, v2 offset:512
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v3, v3, v2
ds_store_b32 v1, v3
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_14:
v_cmp_gt_u16_e64 s5, 0x80, s6
s_and_b32 s7, 0xffff, s6
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB0_18
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e32 64, v0
s_cbranch_execz .LBB0_17
v_lshl_add_u32 v2, v0, 2, 0
ds_load_b32 v2, v2 offset:256
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v3, v3, v2
ds_store_b32 v1, v3
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_18:
s_and_b32 s8, 0xffff, s6
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB0_26
v_cmp_lt_u16_e64 s9, s6, 64
s_and_b32 s6, 0xffff, s6
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s9
s_cbranch_vccz .LBB0_29
s_cmp_lt_u32 s6, 32
s_cbranch_scc0 .LBB0_30
.LBB0_21:
s_cmp_lt_u32 s8, 16
s_cbranch_scc0 .LBB0_31
.LBB0_22:
s_cmp_lt_u32 s7, 8
s_cbranch_scc0 .LBB0_32
.LBB0_23:
s_cmp_lt_u32 s4, 4
s_cbranch_scc0 .LBB0_33
.LBB0_24:
s_cmp_lt_u32 s3, 2
s_cbranch_scc1 .LBB0_26
.LBB0_25:
v_lshl_add_u32 v4, v0, 2, 0
s_mov_b64 s[6:7], src_shared_base
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, 4, v4
v_cmp_ne_u32_e32 vcc_lo, -1, v1
v_cndmask_b32_e32 v1, 0, v1, vcc_lo
v_cndmask_b32_e64 v2, 0, s7, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v4
flat_load_b32 v2, v[1:2] glc dlc
s_waitcnt vmcnt(0)
v_cndmask_b32_e32 v1, 0, v4, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v3, v3, v2
v_cndmask_b32_e64 v2, 0, s7, vcc_lo
flat_store_b32 v[1:2], v3 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_28
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB0_28:
s_endpgm
.LBB0_29:
v_lshl_add_u32 v4, v0, 2, 0
s_mov_b64 s[10:11], src_shared_base
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, 0x80, v4
v_cmp_ne_u32_e32 vcc_lo, -1, v1
v_cndmask_b32_e32 v1, 0, v1, vcc_lo
v_cndmask_b32_e64 v2, 0, s11, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v4
flat_load_b32 v2, v[1:2] glc dlc
s_waitcnt vmcnt(0)
v_cndmask_b32_e32 v1, 0, v4, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v3, v3, v2
v_cndmask_b32_e64 v2, 0, s11, vcc_lo
flat_store_b32 v[1:2], v3 dlc
s_waitcnt_vscnt null, 0x0
s_cmp_lt_u32 s6, 32
s_cbranch_scc1 .LBB0_21
.LBB0_30:
v_lshl_add_u32 v4, v0, 2, 0
s_mov_b64 s[10:11], src_shared_base
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, 64, v4
v_cmp_ne_u32_e32 vcc_lo, -1, v1
v_cndmask_b32_e32 v1, 0, v1, vcc_lo
v_cndmask_b32_e64 v2, 0, s11, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v4
flat_load_b32 v2, v[1:2] glc dlc
s_waitcnt vmcnt(0)
v_cndmask_b32_e32 v1, 0, v4, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v3, v3, v2
v_cndmask_b32_e64 v2, 0, s11, vcc_lo
flat_store_b32 v[1:2], v3 dlc
s_waitcnt_vscnt null, 0x0
s_cmp_lt_u32 s8, 16
s_cbranch_scc1 .LBB0_22
.LBB0_31:
v_lshl_add_u32 v4, v0, 2, 0
s_mov_b64 s[8:9], src_shared_base
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, 32, v4
v_cmp_ne_u32_e32 vcc_lo, -1, v1
v_cndmask_b32_e32 v1, 0, v1, vcc_lo
v_cndmask_b32_e64 v2, 0, s9, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v4
flat_load_b32 v2, v[1:2] glc dlc
s_waitcnt vmcnt(0)
v_cndmask_b32_e32 v1, 0, v4, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v3, v3, v2
v_cndmask_b32_e64 v2, 0, s9, vcc_lo
flat_store_b32 v[1:2], v3 dlc
s_waitcnt_vscnt null, 0x0
s_cmp_lt_u32 s7, 8
s_cbranch_scc1 .LBB0_23
.LBB0_32:
v_lshl_add_u32 v4, v0, 2, 0
s_mov_b64 s[6:7], src_shared_base
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, 16, v4
v_cmp_ne_u32_e32 vcc_lo, -1, v1
v_cndmask_b32_e32 v1, 0, v1, vcc_lo
v_cndmask_b32_e64 v2, 0, s7, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v4
flat_load_b32 v2, v[1:2] glc dlc
s_waitcnt vmcnt(0)
v_cndmask_b32_e32 v1, 0, v4, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v3, v3, v2
v_cndmask_b32_e64 v2, 0, s7, vcc_lo
flat_store_b32 v[1:2], v3 dlc
s_waitcnt_vscnt null, 0x0
s_cmp_lt_u32 s4, 4
s_cbranch_scc1 .LBB0_24
.LBB0_33:
v_lshl_add_u32 v4, v0, 2, 0
s_mov_b64 s[6:7], src_shared_base
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, 8, v4
v_cmp_ne_u32_e32 vcc_lo, -1, v1
v_cndmask_b32_e32 v1, 0, v1, vcc_lo
v_cndmask_b32_e64 v2, 0, s7, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v4
flat_load_b32 v2, v[1:2] glc dlc
s_waitcnt vmcnt(0)
v_cndmask_b32_e32 v1, 0, v4, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v3, v3, v2
v_cndmask_b32_e64 v2, 0, s7, vcc_lo
flat_store_b32 v[1:2], v3 dlc
s_waitcnt_vscnt null, 0x0
s_cmp_lt_u32 s3, 2
s_cbranch_scc0 .LBB0_25
s_branch .LBB0_26
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel reduce
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size reduce, .Lfunc_end0-reduce
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym sdata
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: reduce
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: reduce.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*
* JCuda - Java bindings for NVIDIA CUDA driver and runtime API
* http://www.jcuda.org
*
*
* This code is based on the NVIDIA 'reduction' CUDA sample,
* Copyright 1993-2010 NVIDIA Corporation.
*/
extern "C"
__global__ void reduce(float *g_idata, float *g_odata, unsigned int n)
{
extern __shared__ float sdata[];
// perform first level of reduction,
// reading from global memory, writing to shared memory
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*blockDim.x*2 + threadIdx.x;
unsigned int gridSize = blockDim.x*2*gridDim.x;
float mySum = 0;
// we reduce multiple elements per thread. The number is determined by the
// number of active thread blocks (via gridDim). More blocks will result
// in a larger gridSize and therefore fewer elements per thread
while (i < n)
{
mySum += g_idata[i];
// ensure we don't read out of bounds
if (i + blockDim.x < n)
mySum += g_idata[i+blockDim.x];
i += gridSize;
}
// each thread puts its local sum into shared memory
sdata[tid] = mySum;
__syncthreads();
// do reduction in shared mem
if (blockDim.x >= 512) { if (tid < 256) { sdata[tid] = mySum = mySum + sdata[tid + 256]; } __syncthreads(); }
if (blockDim.x >= 256) { if (tid < 128) { sdata[tid] = mySum = mySum + sdata[tid + 128]; } __syncthreads(); }
if (blockDim.x >= 128) { if (tid < 64) { sdata[tid] = mySum = mySum + sdata[tid + 64]; } __syncthreads(); }
if (tid < 32)
{
// now that we are using warp-synchronous programming (below)
// we need to declare our shared memory volatile so that the compiler
// doesn't reorder stores to it and induce incorrect behavior.
volatile float* smem = sdata;
if (blockDim.x >= 64) { smem[tid] = mySum = mySum + smem[tid + 32]; }
if (blockDim.x >= 32) { smem[tid] = mySum = mySum + smem[tid + 16]; }
if (blockDim.x >= 16) { smem[tid] = mySum = mySum + smem[tid + 8]; }
if (blockDim.x >= 8) { smem[tid] = mySum = mySum + smem[tid + 4]; }
if (blockDim.x >= 4) { smem[tid] = mySum = mySum + smem[tid + 2]; }
if (blockDim.x >= 2) { smem[tid] = mySum = mySum + smem[tid + 1]; }
}
// write result for this block to global mem
if (tid == 0)
g_odata[blockIdx.x] = sdata[0];
} | .text
.file "JCudaReductionKernel.hip"
.globl __device_stub__reduce # -- Begin function __device_stub__reduce
.p2align 4, 0x90
.type __device_stub__reduce,@function
__device_stub__reduce: # @__device_stub__reduce
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $reduce, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size __device_stub__reduce, .Lfunc_end0-__device_stub__reduce
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $reduce, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type reduce,@object # @reduce
.section .rodata,"a",@progbits
.globl reduce
.p2align 3, 0x0
reduce:
.quad __device_stub__reduce
.size reduce, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "reduce"
.size .L__unnamed_1, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__reduce
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym reduce
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : reduce
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff087624 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002100 */
/*0060*/ BSSY B0, 0x200 ; /* 0x0000019000007945 */
/* 0x000fe20003800000 */
/*0070*/ SHF.L.U32 R0, R0, 0x1, RZ ; /* 0x0000000100007819 */
/* 0x000fe200000006ff */
/*0080*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x000fe200000001ff */
/*0090*/ ISETP.GE.U32.AND P4, PT, R8.reuse, 0x200, PT ; /* 0x000002000800780c */
/* 0x040fe40003f86070 */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R8, 0x100, PT ; /* 0x000001000800780c */
/* 0x000fc40003f06070 */
/*00b0*/ ISETP.GE.U32.AND P1, PT, R8, 0x80, PT ; /* 0x000000800800780c */
/* 0x000fe20003f26070 */
/*00c0*/ IMAD R2, R0, R9, R11 ; /* 0x0000000900027224 */
/* 0x001fe200078e020b */
/*00d0*/ ISETP.GT.U32.AND P2, PT, R11.reuse, 0x1f, PT ; /* 0x0000001f0b00780c */
/* 0x040fe40003f44070 */
/*00e0*/ ISETP.NE.AND P3, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f65270 */
/*00f0*/ ISETP.GE.U32.AND P5, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003fa6070 */
/*0100*/ @P5 BRA 0x1f0 ; /* 0x000000e000005947 */
/* 0x000fea0003800000 */
/*0110*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*0120*/ MOV R6, RZ ; /* 0x000000ff00067202 */
/* 0x000fc80000000f00 */
/*0130*/ IADD3 R5, R7, c[0x0][0x0], RZ ; /* 0x0000000007057a10 */
/* 0x000fe20007ffe0ff */
/*0140*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc600078e00ff */
/*0150*/ ISETP.GE.U32.AND P5, PT, R5, c[0x0][0x170], PT ; /* 0x00005c0005007a0c */
/* 0x000fe20003fa6070 */
/*0160*/ IMAD.WIDE.U32 R2, R7, R4, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x000fcc00078e0004 */
/*0170*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000eac000c1e1900 */
/*0180*/ @!P5 IMAD.WIDE.U32 R4, R5, R4, c[0x0][0x160] ; /* 0x000058000504d625 */
/* 0x000fcc00078e0004 */
/*0190*/ @!P5 LDG.E R5, [R4.64] ; /* 0x000000040405d981 */
/* 0x000ee2000c1e1900 */
/*01a0*/ IMAD R7, R0, c[0x0][0xc], R7 ; /* 0x0000030000077a24 */
/* 0x000fca00078e0207 */
/*01b0*/ ISETP.GE.U32.AND P6, PT, R7, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x000fe20003fc6070 */
/*01c0*/ FADD R6, R3, R6 ; /* 0x0000000603067221 */
/* 0x004fc80000000000 */
/*01d0*/ @!P5 FADD R6, R6, R5 ; /* 0x000000050606d221 */
/* 0x008fd00000000000 */
/*01e0*/ @!P6 BRA 0x130 ; /* 0xffffff400000e947 */
/* 0x000fea000383ffff */
/*01f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0200*/ STS [R11.X4], R6 ; /* 0x000000060b007388 */
/* 0x0001e20000004800 */
/*0210*/ MOV R3, R6 ; /* 0x0000000600037202 */
/* 0x000fc60000000f00 */
/*0220*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0230*/ @!P4 BRA 0x290 ; /* 0x000000500000c947 */
/* 0x000fea0003800000 */
/*0240*/ ISETP.GT.U32.AND P4, PT, R11, 0xff, PT ; /* 0x000000ff0b00780c */
/* 0x001fda0003f84070 */
/*0250*/ @!P4 LDS R0, [R11.X4+0x400] ; /* 0x000400000b00c984 */
/* 0x000e240000004800 */
/*0260*/ @!P4 FADD R3, R0, R3 ; /* 0x000000030003c221 */
/* 0x001fca0000000000 */
/*0270*/ @!P4 STS [R11.X4], R3 ; /* 0x000000030b00c388 */
/* 0x0001e80000004800 */
/*0280*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0290*/ @!P0 BRA 0x2f0 ; /* 0x0000005000008947 */
/* 0x001fea0003800000 */
/*02a0*/ ISETP.GT.U32.AND P0, PT, R11, 0x7f, PT ; /* 0x0000007f0b00780c */
/* 0x000fda0003f04070 */
/*02b0*/ @!P0 LDS R0, [R11.X4+0x200] ; /* 0x000200000b008984 */
/* 0x000e240000004800 */
/*02c0*/ @!P0 FADD R3, R0, R3 ; /* 0x0000000300038221 */
/* 0x001fca0000000000 */
/*02d0*/ @!P0 STS [R11.X4], R3 ; /* 0x000000030b008388 */
/* 0x0001e80000004800 */
/*02e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02f0*/ @!P1 BRA 0x350 ; /* 0x0000005000009947 */
/* 0x000fea0003800000 */
/*0300*/ ISETP.GT.U32.AND P0, PT, R11, 0x3f, PT ; /* 0x0000003f0b00780c */
/* 0x000fda0003f04070 */
/*0310*/ @!P0 LDS R0, [R11.X4+0x100] ; /* 0x000100000b008984 */
/* 0x000e640000004800 */
/*0320*/ @!P0 FADD R3, R0, R3 ; /* 0x0000000300038221 */
/* 0x003fca0000000000 */
/*0330*/ @!P0 STS [R11.X4], R3 ; /* 0x000000030b008388 */
/* 0x0001e80000004800 */
/*0340*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0350*/ BSSY B0, 0x500 ; /* 0x000001a000007945 */
/* 0x000fe20003800000 */
/*0360*/ @P2 BRA 0x4f0 ; /* 0x0000018000002947 */
/* 0x000fea0003800000 */
/*0370*/ ISETP.GE.U32.AND P0, PT, R8.reuse, 0x40, PT ; /* 0x000000400800780c */
/* 0x040fe40003f06070 */
/*0380*/ ISETP.GE.U32.AND P1, PT, R8, 0x20, PT ; /* 0x000000200800780c */
/* 0x000fd60003f26070 */
/*0390*/ @P0 LDS R0, [R11.X4+0x80] ; /* 0x000080000b000984 */
/* 0x000e640000004800 */
/*03a0*/ @P0 FADD R3, R0, R3 ; /* 0x0000000300030221 */
/* 0x003fca0000000000 */
/*03b0*/ @P0 STS [R11.X4], R3 ; /* 0x000000030b000388 */
/* 0x000fe20000004800 */
/*03c0*/ ISETP.GE.U32.AND P0, PT, R8, 0x10, PT ; /* 0x000000100800780c */
/* 0x000fc60003f06070 */
/*03d0*/ @P1 LDS R0, [R11.X4+0x40] ; /* 0x000040000b001984 */
/* 0x000e240000004800 */
/*03e0*/ @P1 FADD R3, R0, R3 ; /* 0x0000000300031221 */
/* 0x001fca0000000000 */
/*03f0*/ @P1 STS [R11.X4], R3 ; /* 0x000000030b001388 */
/* 0x000fe20000004800 */
/*0400*/ ISETP.GE.U32.AND P1, PT, R8, 0x8, PT ; /* 0x000000080800780c */
/* 0x000fc60003f26070 */
/*0410*/ @P0 LDS R0, [R11.X4+0x20] ; /* 0x000020000b000984 */
/* 0x000e240000004800 */
/*0420*/ @P0 FADD R3, R0, R3 ; /* 0x0000000300030221 */
/* 0x001fca0000000000 */
/*0430*/ @P0 STS [R11.X4], R3 ; /* 0x000000030b000388 */
/* 0x000fe20000004800 */
/*0440*/ ISETP.GE.U32.AND P0, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fc60003f06070 */
/*0450*/ @P1 LDS R0, [R11.X4+0x10] ; /* 0x000010000b001984 */
/* 0x000e240000004800 */
/*0460*/ @P1 FADD R3, R0, R3 ; /* 0x0000000300031221 */
/* 0x001fca0000000000 */
/*0470*/ @P1 STS [R11.X4], R3 ; /* 0x000000030b001388 */
/* 0x000fe20000004800 */
/*0480*/ ISETP.GE.U32.AND P1, PT, R8, 0x2, PT ; /* 0x000000020800780c */
/* 0x000fc60003f26070 */
/*0490*/ @P0 LDS R0, [R11.X4+0x8] ; /* 0x000008000b000984 */
/* 0x000e240000004800 */
/*04a0*/ @P0 FADD R3, R0, R3 ; /* 0x0000000300030221 */
/* 0x001fca0000000000 */
/*04b0*/ @P0 STS [R11.X4], R3 ; /* 0x000000030b000388 */
/* 0x000fe80000004800 */
/*04c0*/ @P1 LDS R0, [R11.X4+0x4] ; /* 0x000004000b001984 */
/* 0x000e240000004800 */
/*04d0*/ @P1 FADD R0, R0, R3 ; /* 0x0000000300001221 */
/* 0x001fca0000000000 */
/*04e0*/ @P1 STS [R11.X4], R0 ; /* 0x000000000b001388 */
/* 0x0001e40000004800 */
/*04f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0500*/ @P3 EXIT ; /* 0x000000000000394d */
/* 0x000fea0003800000 */
/*0510*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e620000000800 */
/*0520*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc800078e00ff */
/*0530*/ IMAD.WIDE.U32 R2, R9, R2, c[0x0][0x168] ; /* 0x00005a0009027625 */
/* 0x001fca00078e0002 */
/*0540*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe2000c101904 */
/*0550*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0560*/ BRA 0x560; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected reduce
.globl reduce
.p2align 8
.type reduce,@function
reduce:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b32 s7, s[0:1], 0x10
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
s_lshl_b32 s10, s15, 1
v_mov_b32_e32 v3, 0
s_mov_b32 s2, s15
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s9, s10, s3
v_add_nc_u32_e32 v1, s9, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s7, v1
s_cbranch_execz .LBB0_6
s_load_b32 s11, s[4:5], 0x0
s_load_b64 s[4:5], s[0:1], 0x0
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0
v_mov_b32_e32 v4, v0
s_add_i32 s10, s10, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mul_i32 s10, s10, s3
s_waitcnt lgkmcnt(0)
s_mul_i32 s11, s11, s3
s_lshl_b32 s12, s11, 1
s_mov_b32 s11, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s13
v_add_nc_u32_e32 v4, s12, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, s9, v4
v_cmp_le_u32_e32 vcc_lo, s7, v1
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execz .LBB0_5
.LBB0_3:
v_add_nc_u32_e32 v1, s9, v4
s_mov_b32 s13, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_add_nc_u32_e32 v1, s10, v4
v_add_co_u32 v5, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, v3, v5
v_cmpx_gt_u32_e64 s7, v1
s_cbranch_execz .LBB0_2
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_load_b32 v1, v[5:6], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, v3, v1
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s11
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
s_or_b32 exec_lo, exec_lo, s8
v_cmp_gt_u16_e64 s4, 0x200, s6
v_lshl_add_u32 v1, v0, 2, 0
s_and_b32 vcc_lo, exec_lo, s4
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB0_10
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e32 0x100, v0
s_cbranch_execz .LBB0_9
v_lshl_add_u32 v2, v0, 2, 0
ds_load_b32 v2, v2 offset:1024
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v3, v3, v2
ds_store_b32 v1, v3
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_10:
v_cmp_gt_u16_e64 s5, 0x100, s6
s_and_b32 s4, 0xffff, s6
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB0_14
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e32 0x80, v0
s_cbranch_execz .LBB0_13
v_lshl_add_u32 v2, v0, 2, 0
ds_load_b32 v2, v2 offset:512
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v3, v3, v2
ds_store_b32 v1, v3
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_14:
v_cmp_gt_u16_e64 s5, 0x80, s6
s_and_b32 s7, 0xffff, s6
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB0_18
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e32 64, v0
s_cbranch_execz .LBB0_17
v_lshl_add_u32 v2, v0, 2, 0
ds_load_b32 v2, v2 offset:256
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v3, v3, v2
ds_store_b32 v1, v3
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_18:
s_and_b32 s8, 0xffff, s6
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB0_26
v_cmp_lt_u16_e64 s9, s6, 64
s_and_b32 s6, 0xffff, s6
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s9
s_cbranch_vccz .LBB0_29
s_cmp_lt_u32 s6, 32
s_cbranch_scc0 .LBB0_30
.LBB0_21:
s_cmp_lt_u32 s8, 16
s_cbranch_scc0 .LBB0_31
.LBB0_22:
s_cmp_lt_u32 s7, 8
s_cbranch_scc0 .LBB0_32
.LBB0_23:
s_cmp_lt_u32 s4, 4
s_cbranch_scc0 .LBB0_33
.LBB0_24:
s_cmp_lt_u32 s3, 2
s_cbranch_scc1 .LBB0_26
.LBB0_25:
v_lshl_add_u32 v4, v0, 2, 0
s_mov_b64 s[6:7], src_shared_base
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, 4, v4
v_cmp_ne_u32_e32 vcc_lo, -1, v1
v_cndmask_b32_e32 v1, 0, v1, vcc_lo
v_cndmask_b32_e64 v2, 0, s7, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v4
flat_load_b32 v2, v[1:2] glc dlc
s_waitcnt vmcnt(0)
v_cndmask_b32_e32 v1, 0, v4, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v3, v3, v2
v_cndmask_b32_e64 v2, 0, s7, vcc_lo
flat_store_b32 v[1:2], v3 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_28
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB0_28:
s_endpgm
.LBB0_29:
v_lshl_add_u32 v4, v0, 2, 0
s_mov_b64 s[10:11], src_shared_base
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, 0x80, v4
v_cmp_ne_u32_e32 vcc_lo, -1, v1
v_cndmask_b32_e32 v1, 0, v1, vcc_lo
v_cndmask_b32_e64 v2, 0, s11, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v4
flat_load_b32 v2, v[1:2] glc dlc
s_waitcnt vmcnt(0)
v_cndmask_b32_e32 v1, 0, v4, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v3, v3, v2
v_cndmask_b32_e64 v2, 0, s11, vcc_lo
flat_store_b32 v[1:2], v3 dlc
s_waitcnt_vscnt null, 0x0
s_cmp_lt_u32 s6, 32
s_cbranch_scc1 .LBB0_21
.LBB0_30:
v_lshl_add_u32 v4, v0, 2, 0
s_mov_b64 s[10:11], src_shared_base
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, 64, v4
v_cmp_ne_u32_e32 vcc_lo, -1, v1
v_cndmask_b32_e32 v1, 0, v1, vcc_lo
v_cndmask_b32_e64 v2, 0, s11, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v4
flat_load_b32 v2, v[1:2] glc dlc
s_waitcnt vmcnt(0)
v_cndmask_b32_e32 v1, 0, v4, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v3, v3, v2
v_cndmask_b32_e64 v2, 0, s11, vcc_lo
flat_store_b32 v[1:2], v3 dlc
s_waitcnt_vscnt null, 0x0
s_cmp_lt_u32 s8, 16
s_cbranch_scc1 .LBB0_22
.LBB0_31:
v_lshl_add_u32 v4, v0, 2, 0
s_mov_b64 s[8:9], src_shared_base
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, 32, v4
v_cmp_ne_u32_e32 vcc_lo, -1, v1
v_cndmask_b32_e32 v1, 0, v1, vcc_lo
v_cndmask_b32_e64 v2, 0, s9, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v4
flat_load_b32 v2, v[1:2] glc dlc
s_waitcnt vmcnt(0)
v_cndmask_b32_e32 v1, 0, v4, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v3, v3, v2
v_cndmask_b32_e64 v2, 0, s9, vcc_lo
flat_store_b32 v[1:2], v3 dlc
s_waitcnt_vscnt null, 0x0
s_cmp_lt_u32 s7, 8
s_cbranch_scc1 .LBB0_23
.LBB0_32:
v_lshl_add_u32 v4, v0, 2, 0
s_mov_b64 s[6:7], src_shared_base
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, 16, v4
v_cmp_ne_u32_e32 vcc_lo, -1, v1
v_cndmask_b32_e32 v1, 0, v1, vcc_lo
v_cndmask_b32_e64 v2, 0, s7, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v4
flat_load_b32 v2, v[1:2] glc dlc
s_waitcnt vmcnt(0)
v_cndmask_b32_e32 v1, 0, v4, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v3, v3, v2
v_cndmask_b32_e64 v2, 0, s7, vcc_lo
flat_store_b32 v[1:2], v3 dlc
s_waitcnt_vscnt null, 0x0
s_cmp_lt_u32 s4, 4
s_cbranch_scc1 .LBB0_24
.LBB0_33:
v_lshl_add_u32 v4, v0, 2, 0
s_mov_b64 s[6:7], src_shared_base
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, 8, v4
v_cmp_ne_u32_e32 vcc_lo, -1, v1
v_cndmask_b32_e32 v1, 0, v1, vcc_lo
v_cndmask_b32_e64 v2, 0, s7, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v4
flat_load_b32 v2, v[1:2] glc dlc
s_waitcnt vmcnt(0)
v_cndmask_b32_e32 v1, 0, v4, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v3, v3, v2
v_cndmask_b32_e64 v2, 0, s7, vcc_lo
flat_store_b32 v[1:2], v3 dlc
s_waitcnt_vscnt null, 0x0
s_cmp_lt_u32 s3, 2
s_cbranch_scc0 .LBB0_25
s_branch .LBB0_26
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel reduce
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size reduce, .Lfunc_end0-reduce
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym sdata
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: reduce
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: reduce.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00161766_00000000-6_JCudaReductionKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z6reducePfS_jPfS_j
.type _Z28__device_stub__Z6reducePfS_jPfS_j, @function
_Z28__device_stub__Z6reducePfS_jPfS_j:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq reduce(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z6reducePfS_jPfS_j, .-_Z28__device_stub__Z6reducePfS_jPfS_j
.globl reduce
.type reduce, @function
reduce:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z6reducePfS_jPfS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size reduce, .-reduce
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "reduce"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq reduce(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "JCudaReductionKernel.hip"
.globl __device_stub__reduce # -- Begin function __device_stub__reduce
.p2align 4, 0x90
.type __device_stub__reduce,@function
__device_stub__reduce: # @__device_stub__reduce
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $reduce, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size __device_stub__reduce, .Lfunc_end0-__device_stub__reduce
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $reduce, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type reduce,@object # @reduce
.section .rodata,"a",@progbits
.globl reduce
.p2align 3, 0x0
reduce:
.quad __device_stub__reduce
.size reduce, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "reduce"
.size .L__unnamed_1, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__reduce
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym reduce
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void kernel(int* d_vec, int n) {
int tid = threadIdx.x;
if(threadIdx.x < n) {
int i = d_vec[tid];
d_vec[tid] = i > 5 ? -i : i;
}
} | code for sm_80
Function : _Z6kernelPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x001fda0003f06070 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0070*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea4000c1e1900 */
/*0080*/ ISETP.GT.AND P0, PT, R5, 0x5, PT ; /* 0x000000050500780c */
/* 0x004fda0003f04270 */
/*0090*/ @P0 IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff050224 */
/* 0x000fca00078e0a05 */
/*00a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kernel(int* d_vec, int n) {
int tid = threadIdx.x;
if(threadIdx.x < n) {
int i = d_vec[tid];
d_vec[tid] = i > 5 ? -i : i;
}
} | .file "tmpxft_00055aa2_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z6kernelPiiPii
.type _Z26__device_stub__Z6kernelPiiPii, @function
_Z26__device_stub__Z6kernelPiiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z6kernelPiiPii, .-_Z26__device_stub__Z6kernelPiiPii
.globl _Z6kernelPii
.type _Z6kernelPii, @function
_Z6kernelPii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6kernelPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6kernelPii, .-_Z6kernelPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kernelPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kernel(int* d_vec, int n) {
int tid = threadIdx.x;
if(threadIdx.x < n) {
int i = d_vec[tid];
d_vec[tid] = i > 5 ? -i : i;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel(int* d_vec, int n) {
int tid = threadIdx.x;
if(threadIdx.x < n) {
int i = d_vec[tid];
d_vec[tid] = i > 5 ? -i : i;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel(int* d_vec, int n) {
int tid = threadIdx.x;
if(threadIdx.x < n) {
int i = d_vec[tid];
d_vec[tid] = i > 5 ? -i : i;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPii
.globl _Z6kernelPii
.p2align 8
.type _Z6kernelPii,@function
_Z6kernelPii:
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_cmp_gt_u32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v2, 0, v1
v_cmp_lt_i32_e32 vcc_lo, 5, v1
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v1, v1, v2, vcc_lo
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 3
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPii, .Lfunc_end0-_Z6kernelPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPii
.private_segment_fixed_size: 0
.sgpr_count: 5
.sgpr_spill_count: 0
.symbol: _Z6kernelPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel(int* d_vec, int n) {
int tid = threadIdx.x;
if(threadIdx.x < n) {
int i = d_vec[tid];
d_vec[tid] = i > 5 ? -i : i;
}
} | .text
.file "kernel.hip"
.globl _Z21__device_stub__kernelPii # -- Begin function _Z21__device_stub__kernelPii
.p2align 4, 0x90
.type _Z21__device_stub__kernelPii,@function
_Z21__device_stub__kernelPii: # @_Z21__device_stub__kernelPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPii, .Lfunc_end0-_Z21__device_stub__kernelPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPii,@object # @_Z6kernelPii
.section .rodata,"a",@progbits
.globl _Z6kernelPii
.p2align 3, 0x0
_Z6kernelPii:
.quad _Z21__device_stub__kernelPii
.size _Z6kernelPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelPii"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kernelPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x001fda0003f06070 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0070*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea4000c1e1900 */
/*0080*/ ISETP.GT.AND P0, PT, R5, 0x5, PT ; /* 0x000000050500780c */
/* 0x004fda0003f04270 */
/*0090*/ @P0 IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff050224 */
/* 0x000fca00078e0a05 */
/*00a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPii
.globl _Z6kernelPii
.p2align 8
.type _Z6kernelPii,@function
_Z6kernelPii:
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_cmp_gt_u32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v2, 0, v1
v_cmp_lt_i32_e32 vcc_lo, 5, v1
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v1, v1, v2, vcc_lo
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 3
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPii, .Lfunc_end0-_Z6kernelPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPii
.private_segment_fixed_size: 0
.sgpr_count: 5
.sgpr_spill_count: 0
.symbol: _Z6kernelPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00055aa2_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z6kernelPiiPii
.type _Z26__device_stub__Z6kernelPiiPii, @function
_Z26__device_stub__Z6kernelPiiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z6kernelPiiPii, .-_Z26__device_stub__Z6kernelPiiPii
.globl _Z6kernelPii
.type _Z6kernelPii, @function
_Z6kernelPii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6kernelPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6kernelPii, .-_Z6kernelPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kernelPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z21__device_stub__kernelPii # -- Begin function _Z21__device_stub__kernelPii
.p2align 4, 0x90
.type _Z21__device_stub__kernelPii,@function
_Z21__device_stub__kernelPii: # @_Z21__device_stub__kernelPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPii, .Lfunc_end0-_Z21__device_stub__kernelPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPii,@object # @_Z6kernelPii
.section .rodata,"a",@progbits
.globl _Z6kernelPii
.p2align 3, 0x0
_Z6kernelPii:
.quad _Z21__device_stub__kernelPii
.size _Z6kernelPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelPii"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
__global__ void gpu_scan_sharemem_phaseI(int *in, int *out, int *aux, int size_tmp, int block_d){
__shared__ int tmp[2][128];
unsigned int myblock = blockIdx.x;
unsigned int tid = threadIdx.x;
while(myblock < size_tmp){
tmp[0][tid] = in[myblock*blockDim.x+threadIdx.x];
__syncthreads();
int iout = 0;
for (int d = 0; d < block_d; ++d){ //depth d
iout ^= 1;
int *tmp_out = tmp[iout];
int *tmp_in = tmp[iout ^ 1];
int t1 = tid - (1 << d); //tid - 2^d
if (t1 >= 0) { //tid > 2^d
tmp_out[tid] = tmp_in[tid] + tmp_in[t1];
}
else {
tmp_out[tid] = tmp_in[tid];
}
__syncthreads();
}
out[myblock*blockDim.x+threadIdx.x] = tmp[iout][tid];
aux[myblock] = tmp[iout][127]; //last element of each block for next scan
myblock+=128;
}
}
__global__ void gpu_scan_sharemem_phaseIII(int *d_out, int *d_out2, int *d_aux2, int size_tmp){
__shared__ int tmp[128];
unsigned int myblock = blockIdx.x;
unsigned int tid = threadIdx.x;
while(myblock < size_tmp){
tmp[tid] = d_out[myblock*blockDim.x+threadIdx.x];
__syncthreads();
if(myblock > 0){
tmp[tid] += d_aux2[myblock-1];
__syncthreads();
}
d_out2[myblock*blockDim.x+threadIdx.x] = tmp[tid];
myblock+=128;
}
}
int main()
{
int *in;
int *out;
int *out_2;
int *h_out;
int *aux;
int *aux_2;
int num_size = 32000000;
int size_tmp = (num_size + 127) / 128;
int block_d = 7; //depth of block, log2(128) = 7
cudaMallocHost((void **) &in, sizeof(int)*num_size);
cudaMallocHost((void **) &out, sizeof(int)*num_size);
cudaMallocHost((void **) &h_out, sizeof(int)*num_size);
cudaMallocHost((void **) &out_2, sizeof(int)*num_size);
cudaMallocHost((void **) &aux, sizeof(int)*size_tmp); //for checking itermediate values
cudaMallocHost((void **) &aux_2, sizeof(int)*size_tmp); //for checking the update itermediate values
for (int i = 0; i < num_size; i++) {
in[i] = i;
out[i] = 0;
}
for (int i = 0; i < size_tmp; i++) {
aux[i] = 0;
}
int *d_in;
int *d_out;
int *d_aux;
// int dszp = (num_size)*sizeof(int);
int dszp_aux = (size_tmp)*sizeof(int);
cudaMalloc((void **) &d_in, sizeof(int)*num_size);
cudaMalloc((void **) &d_out, sizeof(int)*num_size);
cudaMalloc((void **) &d_aux, sizeof(int)*size_tmp);
// cudaMemset(d_out, 0, dszp);
cudaMemset(d_aux, 0, dszp_aux);
// Phase1: scan original data per block and store last element of each block for later scan
cudaMemcpy(d_in, in, sizeof(int)*num_size, cudaMemcpyHostToDevice);
gpu_scan_sharemem_phaseI<<<128, 128>>>(d_in, d_out, d_aux, size_tmp, block_d);
cudaMemcpy(out, d_out, sizeof(int)*num_size, cudaMemcpyDeviceToHost);
cudaMemcpy(aux, d_aux, sizeof(int)*size_tmp, cudaMemcpyDeviceToHost);
cudaThreadSynchronize();
// Phase2: scan the last element of each block to accumulate the sum of each block
aux_2[0] = aux[0];
for(int i = 1; i < size_tmp; i++){
aux_2[i] = aux[i] + aux_2[i-1];
}
int *d_aux2;
cudaMalloc((void **) &d_aux2, sizeof(int)*size_tmp);
cudaMemcpy(d_aux2, aux_2, sizeof(int)*size_tmp, cudaMemcpyHostToDevice);
// Phase3: scan the last element of each block to accumulate the sum of each block
int *d_out2;
cudaMalloc((void **) &d_out2, sizeof(int)*num_size);
gpu_scan_sharemem_phaseIII<<<128, 128>>>(d_out, d_out2, d_aux2, size_tmp);
cudaMemcpy(out_2, d_out2, sizeof(int)*num_size, cudaMemcpyDeviceToHost);
// check the GPU results
printf("First 200 elements of the scan results:\n");
for (int i = 0; i < 200; i++){
printf("%d\t", out_2[i]);
if (i % 10 == 0) printf("\n");
}
printf("\n");
// printf("last 100 elements of the scan results:\n");
// for (int i = num_size-101; i < num_size-1; i++){
// printf("%d\t", out_2[i]);
// if (i % 10 == 0) printf("\n");
// }
// printf("\n");
// verify via comparasion with cpu version
int psum = 0;
for (int i = 0; i < num_size; i++){
psum += in[i];
if (psum != out_2[i]) {printf("mismatch at %d, was: %d, should be: %d\n", i, out_2[i], psum); return 1;}
}
printf("successfully scan!\n");
cudaFree(d_in);
cudaFree(d_out);
cudaFree(d_out2);
cudaFree(d_aux);
cudaFree(d_aux2);
cudaFreeHost(in);
cudaFreeHost(out);
cudaFreeHost(out_2);
cudaFreeHost(h_out);
cudaFreeHost(aux);
cudaFreeHost(aux_2);
return 0;
} | code for sm_80
Function : _Z26gpu_scan_sharemem_phaseIIIPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x001fda0003f06070 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002100 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0060*/ IMAD R6, R0, c[0x0][0x0], R11 ; /* 0x0000000000067a24 */
/* 0x001fe400078e020b */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*0080*/ IMAD.WIDE.U32 R2, R6, R5, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fca00078e0005 */
/*0090*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IADD3 R4, R0, -0x1, RZ ; /* 0xffffffff00047810 */
/* 0x000fc80007ffe0ff */
/*00b0*/ ISETP.NE.AND P0, PT, R4, -0x1, PT ; /* 0xffffffff0400780c */
/* 0x000fda0003f05270 */
/*00c0*/ @P0 IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004040625 */
/* 0x000fe200078e0005 */
/*00d0*/ STS [R11.X4], R7 ; /* 0x000000070b007388 */
/* 0x004fe80000004800 */
/*00e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00f0*/ @P0 LDG.E R5, [R4.64] ; /* 0x0000000404050981 */
/* 0x000ea2000c1e1900 */
/*0100*/ IADD3 R0, R0, 0x80, RZ ; /* 0x0000008000007810 */
/* 0x000fc60007ffe0ff */
/*0110*/ @P0 LDS R8, [R11.X4] ; /* 0x000000000b080984 */
/* 0x000ea40000004800 */
/*0120*/ @P0 IADD3 R8, R8, R5, RZ ; /* 0x0000000508080210 */
/* 0x004fe20007ffe0ff */
/*0130*/ IMAD.MOV.U32 R5, RZ, RZ, 0x80 ; /* 0x00000080ff057424 */
/* 0x000fc800078e00ff */
/*0140*/ @P0 STS [R11.X4], R8 ; /* 0x000000080b000388 */
/* 0x000fe80000004800 */
/*0150*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fe20000010000 */
/*0160*/ LEA R2, P0, R6, c[0x0][0x168], 0x2 ; /* 0x00005a0006027a11 */
/* 0x000fc800078010ff */
/*0170*/ LEA.HI.X R3, R6, c[0x0][0x16c], RZ, 0x2, P0 ; /* 0x00005b0006037a11 */
/* 0x000fe200000f14ff */
/*0180*/ IMAD R6, R5, c[0x0][0x0], R6 ; /* 0x0000000005067a24 */
/* 0x000fe200078e0206 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06070 */
/*01a0*/ LDS R9, [R11.X4] ; /* 0x000000000b097984 */
/* 0x000e280000004800 */
/*01b0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0011f0000c101904 */
/*01c0*/ @!P0 BRA 0x70 ; /* 0xfffffea000008947 */
/* 0x000fea000383ffff */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z24gpu_scan_sharemem_phaseIPiS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x178], PT ; /* 0x00005e0005007a0c */
/* 0x001fda0003f06070 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0050*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff027624 */
/* 0x000fe200078e00ff */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*0070*/ LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fc800078ec0ff */
/*0080*/ IADD3 R4, -R2, c[0x0][0x17c], RZ ; /* 0x00005f0002047a10 */
/* 0x000fe20007ffe1ff */
/*0090*/ IMAD.SHL.U32 R3, R0, 0x4, RZ ; /* 0x0000000400037824 */
/* 0x001fca00078e00ff */
/*00a0*/ IADD3 R6, R3, 0x200, RZ ; /* 0x0000020003067810 */
/* 0x000fe40007ffe0ff */
/*00b0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x001fe400078e00ff */
/*00c0*/ IMAD R7, R5, c[0x0][0x0], R0 ; /* 0x0000000005077a24 */
/* 0x000fc800078e0200 */
/*00d0*/ IMAD.WIDE.U32 R10, R7, R8, c[0x0][0x160] ; /* 0x00005800070a7625 */
/* 0x000fcc00078e0008 */
/*00e0*/ LDG.E R11, [R10.64] ; /* 0x000000060a0b7981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff097624 */
/* 0x000fe200078e00ff */
/*0100*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0110*/ IMAD.MOV.U32 R12, RZ, RZ, R3 ; /* 0x000000ffff0c7224 */
/* 0x000fc600078e0003 */
/*0120*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fe20003f06270 */
/*0130*/ STS [R0.X4], R11 ; /* 0x0000000b00007388 */
/* 0x0041e80000004800 */
/*0140*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*0150*/ @!P0 BRA 0x6d0 ; /* 0x0000057000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R9, R9, -0x1, RZ ; /* 0xffffffff09097810 */
/* 0x001fe40007ffe0ff */
/*0170*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fc40003f05270 */
/*0180*/ ISETP.GE.U32.AND P1, PT, R9, 0x3, PT ; /* 0x000000030900780c */
/* 0x000fe20003f26070 */
/*0190*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fd800078e00ff */
/*01a0*/ @!P1 BRA 0x450 ; /* 0x000002a000009947 */
/* 0x000fea0003800000 */
/*01b0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe400078e00ff */
/*01c0*/ IMAD.MOV.U32 R10, RZ, RZ, R4 ; /* 0x000000ffff0a7224 */
/* 0x000fc800078e0004 */
/*01d0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x000fe200078e00ff */
/*01e0*/ IADD3 R10, R10, -0x4, RZ ; /* 0xfffffffc0a0a7810 */
/* 0x000fe20007ffe0ff */
/*01f0*/ IMAD.MOV.U32 R12, RZ, RZ, 0x2 ; /* 0x00000002ff0c7424 */
/* 0x000fc600078e00ff */
/*0200*/ SHF.L.U32 R11, R8, R9.reuse, RZ ; /* 0x00000009080b7219 */
/* 0x080fe400000006ff */
/*0210*/ SHF.L.U32 R13, R12, R9, RZ ; /* 0x000000090c0d7219 */
/* 0x000fc600000006ff */
/*0220*/ IMAD.IADD R14, R0.reuse, 0x1, -R11 ; /* 0x00000001000e7824 */
/* 0x040fe400078e0a0b */
/*0230*/ LDS R11, [R0.X4] ; /* 0x00000000000b7984 */
/* 0x000fe20000004800 */
/*0240*/ IMAD.IADD R16, R0, 0x1, -R13 ; /* 0x0000000100107824 */
/* 0x000fe400078e0a0d */
/*0250*/ ISETP.GE.AND P2, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fc60003f46270 */
/*0260*/ ISETP.GE.AND P1, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fd40003f26270 */
/*0270*/ @P2 LDS R8, [R14.X4] ; /* 0x000000000e082984 */
/* 0x0000640000004800 */
/*0280*/ IMAD.MOV.U32 R14, RZ, RZ, 0x8 ; /* 0x00000008ff0e7424 */
/* 0x001fe400078e00ff */
/*0290*/ @P2 IMAD.IADD R11, R11, 0x1, R8 ; /* 0x000000010b0b2824 */
/* 0x002fe400078e0208 */
/*02a0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fc600078e00ff */
/*02b0*/ STS [R0.X4+0x200], R11 ; /* 0x0002000b00007388 */
/* 0x000fe40000004800 */
/*02c0*/ SHF.L.U32 R15, R8, R9.reuse, RZ ; /* 0x00000009080f7219 */
/* 0x080fe400000006ff */
/*02d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*02e0*/ IMAD.IADD R17, R0, 0x1, -R15 ; /* 0x0000000100117824 */
/* 0x000fe200078e0a0f */
/*02f0*/ SHF.L.U32 R15, R14, R9, RZ ; /* 0x000000090e0f7219 */
/* 0x000fe400000006ff */
/*0300*/ IADD3 R9, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fc40007ffe0ff */
/*0310*/ ISETP.GE.AND P2, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fe20003f46270 */
/*0320*/ IMAD.IADD R15, R0, 0x1, -R15 ; /* 0x00000001000f7824 */
/* 0x000fe200078e0a0f */
/*0330*/ @P1 LDS R12, [R16.X4+0x200] ; /* 0x00020000100c1984 */
/* 0x000fe80000004800 */
/*0340*/ LDS R13, [R0.X4+0x200] ; /* 0x00020000000d7984 */
/* 0x000e240000004800 */
/*0350*/ @P1 IADD3 R13, R13, R12, RZ ; /* 0x0000000c0d0d1210 */
/* 0x001fe40007ffe0ff */
/*0360*/ ISETP.GE.AND P1, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fc60003f26270 */
/*0370*/ STS [R0.X4], R13 ; /* 0x0000000d00007388 */
/* 0x000fe80000004800 */
/*0380*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0390*/ @P2 LDS R12, [R17.X4] ; /* 0x00000000110c2984 */
/* 0x000fe80000004800 */
/*03a0*/ LDS R11, [R0.X4] ; /* 0x00000000000b7984 */
/* 0x000e240000004800 */
/*03b0*/ @P2 IMAD.IADD R11, R11, 0x1, R12 ; /* 0x000000010b0b2824 */
/* 0x001fca00078e020c */
/*03c0*/ STS [R0.X4+0x200], R11 ; /* 0x0002000b00007388 */
/* 0x000fe80000004800 */
/*03d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03e0*/ @P1 LDS R12, [R15.X4+0x200] ; /* 0x000200000f0c1984 */
/* 0x000fe80000004800 */
/*03f0*/ LDS R13, [R0.X4+0x200] ; /* 0x00020000000d7984 */
/* 0x000e240000004800 */
/*0400*/ @P1 IMAD.IADD R13, R13, 0x1, R12 ; /* 0x000000010d0d1824 */
/* 0x001fe200078e020c */
/*0410*/ ISETP.NE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fc80003f25270 */
/*0420*/ STS [R0.X4], R13 ; /* 0x0000000d00007388 */
/* 0x0001e80000004800 */
/*0430*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0440*/ @P1 BRA 0x1d0 ; /* 0xfffffd8000001947 */
/* 0x001fea000383ffff */
/*0450*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0460*/ IMAD.MOV.U32 R12, RZ, RZ, R3 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0003 */
/*0470*/ @!P0 BRA 0x6d0 ; /* 0x0000025000008947 */
/* 0x000fea0003800000 */
/*0480*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1 ; /* 0x00000001ff0e7424 */
/* 0x000fe200078e00ff */
/*0490*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe20000000000 */
/*04a0*/ MOV R12, R6 ; /* 0x00000006000c7202 */
/* 0x000fc60000000f00 */
/*04b0*/ SHF.L.U32 R11, R14, R9, RZ ; /* 0x000000090e0b7219 */
/* 0x000fca00000006ff */
/*04c0*/ IMAD.IADD R10, R0, 0x1, -R11 ; /* 0x00000001000a7824 */
/* 0x000fe400078e0a0b */
/*04d0*/ LDS R11, [R0.X4] ; /* 0x00000000000b7984 */
/* 0x000fe60000004800 */
/*04e0*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f06270 */
/*04f0*/ @P0 LDS R10, [R10.X4] ; /* 0x000000000a0a0984 */
/* 0x000e240000004800 */
/*0500*/ @P0 IMAD.IADD R11, R11, 0x1, R10 ; /* 0x000000010b0b0824 */
/* 0x001fe200078e020a */
/*0510*/ ISETP.NE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fc80003f05270 */
/*0520*/ STS [R0.X4+0x200], R11 ; /* 0x0002000b00007388 */
/* 0x0001e80000004800 */
/*0530*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0540*/ @!P0 BRA 0x6d0 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0550*/ IADD3 R10, R9, 0x1, RZ ; /* 0x00000001090a7810 */
/* 0x001fe20007ffe0ff */
/*0560*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0570*/ IMAD.MOV.U32 R12, RZ, RZ, R3 ; /* 0x000000ffff0c7224 */
/* 0x000fc400078e0003 */
/*0580*/ SHF.L.U32 R11, R14, R10, RZ ; /* 0x0000000a0e0b7219 */
/* 0x000fca00000006ff */
/*0590*/ IMAD.IADD R10, R0, 0x1, -R11 ; /* 0x00000001000a7824 */
/* 0x000fe400078e0a0b */
/*05a0*/ LDS R11, [R0.X4+0x200] ; /* 0x00020000000b7984 */
/* 0x000fe60000004800 */
/*05b0*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f06270 */
/*05c0*/ @P0 LDS R10, [R10.X4+0x200] ; /* 0x000200000a0a0984 */
/* 0x000e240000004800 */
/*05d0*/ @P0 IMAD.IADD R11, R11, 0x1, R10 ; /* 0x000000010b0b0824 */
/* 0x001fe200078e020a */
/*05e0*/ ISETP.NE.AND P0, PT, R2, 0x2, PT ; /* 0x000000020200780c */
/* 0x000fc80003f05270 */
/*05f0*/ STS [R0.X4], R11 ; /* 0x0000000b00007388 */
/* 0x0001e80000004800 */
/*0600*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0610*/ @!P0 BRA 0x6d0 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0620*/ IADD3 R9, R9, 0x2, RZ ; /* 0x0000000209097810 */
/* 0x001fe20007ffe0ff */
/*0630*/ IMAD.MOV.U32 R12, RZ, RZ, R6 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0006 */
/*0640*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fc40000000000 */
/*0650*/ SHF.L.U32 R9, R14, R9, RZ ; /* 0x000000090e097219 */
/* 0x000fca00000006ff */
/*0660*/ IMAD.IADD R10, R0, 0x1, -R9 ; /* 0x00000001000a7824 */
/* 0x000fe400078e0a09 */
/*0670*/ LDS R9, [R0.X4] ; /* 0x0000000000097984 */
/* 0x000fe60000004800 */
/*0680*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f06270 */
/*0690*/ @P0 LDS R10, [R10.X4] ; /* 0x000000000a0a0984 */
/* 0x000e240000004800 */
/*06a0*/ @P0 IMAD.IADD R9, R9, 0x1, R10 ; /* 0x0000000109090824 */
/* 0x001fca00078e020a */
/*06b0*/ STS [R0.X4+0x200], R9 ; /* 0x0002000900007388 */
/* 0x0001e80000004800 */
/*06c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*06d0*/ USHF.L.U32 UR4, UR4, 0x9, URZ ; /* 0x0000000904047899 */
/* 0x001fe2000800063f */
/*06e0*/ LDS R13, [R12] ; /* 0x000000000c0d7984 */
/* 0x000e220000000800 */
/*06f0*/ LEA R10, P0, R7, c[0x0][0x168], 0x2 ; /* 0x00005a00070a7a11 */
/* 0x000fe200078010ff */
/*0700*/ IMAD.WIDE.U32 R8, R5.reuse, R8, c[0x0][0x170] ; /* 0x00005c0005087625 */
/* 0x040fe200078e0008 */
/*0710*/ IADD3 R5, R5, 0x80, RZ ; /* 0x0000008005057810 */
/* 0x000fe40007ffe0ff */
/*0720*/ LEA.HI.X R11, R7, c[0x0][0x16c], RZ, 0x2, P0 ; /* 0x00005b00070b7a11 */
/* 0x000fc400000f14ff */
/*0730*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x178], PT ; /* 0x00005e0005007a0c */
/* 0x000fe20003f06070 */
/*0740*/ LDS R15, [UR4+0x1fc] ; /* 0x0001fc04ff0f7984 */
/* 0x000e680008000800 */
/*0750*/ STG.E [R10.64], R13 ; /* 0x0000000d0a007986 */
/* 0x0011e8000c101906 */
/*0760*/ STG.E [R8.64], R15 ; /* 0x0000000f08007986 */
/* 0x0021e8000c101906 */
/*0770*/ @!P0 BRA 0xb0 ; /* 0xfffff93000008947 */
/* 0x000fea000383ffff */
/*0780*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0790*/ BRA 0x790; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
__global__ void gpu_scan_sharemem_phaseI(int *in, int *out, int *aux, int size_tmp, int block_d){
__shared__ int tmp[2][128];
unsigned int myblock = blockIdx.x;
unsigned int tid = threadIdx.x;
while(myblock < size_tmp){
tmp[0][tid] = in[myblock*blockDim.x+threadIdx.x];
__syncthreads();
int iout = 0;
for (int d = 0; d < block_d; ++d){ //depth d
iout ^= 1;
int *tmp_out = tmp[iout];
int *tmp_in = tmp[iout ^ 1];
int t1 = tid - (1 << d); //tid - 2^d
if (t1 >= 0) { //tid > 2^d
tmp_out[tid] = tmp_in[tid] + tmp_in[t1];
}
else {
tmp_out[tid] = tmp_in[tid];
}
__syncthreads();
}
out[myblock*blockDim.x+threadIdx.x] = tmp[iout][tid];
aux[myblock] = tmp[iout][127]; //last element of each block for next scan
myblock+=128;
}
}
__global__ void gpu_scan_sharemem_phaseIII(int *d_out, int *d_out2, int *d_aux2, int size_tmp){
__shared__ int tmp[128];
unsigned int myblock = blockIdx.x;
unsigned int tid = threadIdx.x;
while(myblock < size_tmp){
tmp[tid] = d_out[myblock*blockDim.x+threadIdx.x];
__syncthreads();
if(myblock > 0){
tmp[tid] += d_aux2[myblock-1];
__syncthreads();
}
d_out2[myblock*blockDim.x+threadIdx.x] = tmp[tid];
myblock+=128;
}
}
int main()
{
int *in;
int *out;
int *out_2;
int *h_out;
int *aux;
int *aux_2;
int num_size = 32000000;
int size_tmp = (num_size + 127) / 128;
int block_d = 7; //depth of block, log2(128) = 7
cudaMallocHost((void **) &in, sizeof(int)*num_size);
cudaMallocHost((void **) &out, sizeof(int)*num_size);
cudaMallocHost((void **) &h_out, sizeof(int)*num_size);
cudaMallocHost((void **) &out_2, sizeof(int)*num_size);
cudaMallocHost((void **) &aux, sizeof(int)*size_tmp); //for checking itermediate values
cudaMallocHost((void **) &aux_2, sizeof(int)*size_tmp); //for checking the update itermediate values
for (int i = 0; i < num_size; i++) {
in[i] = i;
out[i] = 0;
}
for (int i = 0; i < size_tmp; i++) {
aux[i] = 0;
}
int *d_in;
int *d_out;
int *d_aux;
// int dszp = (num_size)*sizeof(int);
int dszp_aux = (size_tmp)*sizeof(int);
cudaMalloc((void **) &d_in, sizeof(int)*num_size);
cudaMalloc((void **) &d_out, sizeof(int)*num_size);
cudaMalloc((void **) &d_aux, sizeof(int)*size_tmp);
// cudaMemset(d_out, 0, dszp);
cudaMemset(d_aux, 0, dszp_aux);
// Phase1: scan original data per block and store last element of each block for later scan
cudaMemcpy(d_in, in, sizeof(int)*num_size, cudaMemcpyHostToDevice);
gpu_scan_sharemem_phaseI<<<128, 128>>>(d_in, d_out, d_aux, size_tmp, block_d);
cudaMemcpy(out, d_out, sizeof(int)*num_size, cudaMemcpyDeviceToHost);
cudaMemcpy(aux, d_aux, sizeof(int)*size_tmp, cudaMemcpyDeviceToHost);
cudaThreadSynchronize();
// Phase2: scan the last element of each block to accumulate the sum of each block
aux_2[0] = aux[0];
for(int i = 1; i < size_tmp; i++){
aux_2[i] = aux[i] + aux_2[i-1];
}
int *d_aux2;
cudaMalloc((void **) &d_aux2, sizeof(int)*size_tmp);
cudaMemcpy(d_aux2, aux_2, sizeof(int)*size_tmp, cudaMemcpyHostToDevice);
// Phase3: scan the last element of each block to accumulate the sum of each block
int *d_out2;
cudaMalloc((void **) &d_out2, sizeof(int)*num_size);
gpu_scan_sharemem_phaseIII<<<128, 128>>>(d_out, d_out2, d_aux2, size_tmp);
cudaMemcpy(out_2, d_out2, sizeof(int)*num_size, cudaMemcpyDeviceToHost);
// check the GPU results
printf("First 200 elements of the scan results:\n");
for (int i = 0; i < 200; i++){
printf("%d\t", out_2[i]);
if (i % 10 == 0) printf("\n");
}
printf("\n");
// printf("last 100 elements of the scan results:\n");
// for (int i = num_size-101; i < num_size-1; i++){
// printf("%d\t", out_2[i]);
// if (i % 10 == 0) printf("\n");
// }
// printf("\n");
// verify via comparasion with cpu version
int psum = 0;
for (int i = 0; i < num_size; i++){
psum += in[i];
if (psum != out_2[i]) {printf("mismatch at %d, was: %d, should be: %d\n", i, out_2[i], psum); return 1;}
}
printf("successfully scan!\n");
cudaFree(d_in);
cudaFree(d_out);
cudaFree(d_out2);
cudaFree(d_aux);
cudaFree(d_aux2);
cudaFreeHost(in);
cudaFreeHost(out);
cudaFreeHost(out_2);
cudaFreeHost(h_out);
cudaFreeHost(aux);
cudaFreeHost(aux_2);
return 0;
} | .file "tmpxft_00123a33_00000000-6_scan.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z24gpu_scan_sharemem_phaseIPiS_S_iiPiS_S_ii
.type _Z50__device_stub__Z24gpu_scan_sharemem_phaseIPiS_S_iiPiS_S_ii, @function
_Z50__device_stub__Z24gpu_scan_sharemem_phaseIPiS_S_iiPiS_S_ii:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z24gpu_scan_sharemem_phaseIPiS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z50__device_stub__Z24gpu_scan_sharemem_phaseIPiS_S_iiPiS_S_ii, .-_Z50__device_stub__Z24gpu_scan_sharemem_phaseIPiS_S_iiPiS_S_ii
.globl _Z24gpu_scan_sharemem_phaseIPiS_S_ii
.type _Z24gpu_scan_sharemem_phaseIPiS_S_ii, @function
_Z24gpu_scan_sharemem_phaseIPiS_S_ii:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z24gpu_scan_sharemem_phaseIPiS_S_iiPiS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z24gpu_scan_sharemem_phaseIPiS_S_ii, .-_Z24gpu_scan_sharemem_phaseIPiS_S_ii
.globl _Z51__device_stub__Z26gpu_scan_sharemem_phaseIIIPiS_S_iPiS_S_i
.type _Z51__device_stub__Z26gpu_scan_sharemem_phaseIIIPiS_S_iPiS_S_i, @function
_Z51__device_stub__Z26gpu_scan_sharemem_phaseIIIPiS_S_iPiS_S_i:
.LFB3696:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z26gpu_scan_sharemem_phaseIIIPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z51__device_stub__Z26gpu_scan_sharemem_phaseIIIPiS_S_iPiS_S_i, .-_Z51__device_stub__Z26gpu_scan_sharemem_phaseIIIPiS_S_iPiS_S_i
.globl _Z26gpu_scan_sharemem_phaseIIIPiS_S_i
.type _Z26gpu_scan_sharemem_phaseIIIPiS_S_i, @function
_Z26gpu_scan_sharemem_phaseIIIPiS_S_i:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z26gpu_scan_sharemem_phaseIIIPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z26gpu_scan_sharemem_phaseIIIPiS_S_i, .-_Z26gpu_scan_sharemem_phaseIIIPiS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "First 200 elements of the scan results:\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%d\t"
.LC2:
.string "\n"
.section .rodata.str1.8
.align 8
.LC3:
.string "mismatch at %d, was: %d, should be: %d\n"
.section .rodata.str1.1
.LC4:
.string "successfully scan!\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
addq $-128, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $128000000, %esi
call cudaMallocHost@PLT
leaq 16(%rsp), %rdi
movl $128000000, %esi
call cudaMallocHost@PLT
leaq 32(%rsp), %rdi
movl $128000000, %esi
call cudaMallocHost@PLT
leaq 24(%rsp), %rdi
movl $128000000, %esi
call cudaMallocHost@PLT
leaq 40(%rsp), %rdi
movl $1000000, %esi
call cudaMallocHost@PLT
leaq 48(%rsp), %rdi
movl $1000000, %esi
call cudaMallocHost@PLT
movl $0, %eax
.L20:
movq 8(%rsp), %rdx
movl %eax, (%rdx,%rax,4)
movq 16(%rsp), %rdx
movl $0, (%rdx,%rax,4)
addq $1, %rax
cmpq $32000000, %rax
jne .L20
movl $0, %eax
.L21:
movq 40(%rsp), %rdx
movl $0, (%rdx,%rax)
addq $4, %rax
cmpq $1000000, %rax
jne .L21
leaq 56(%rsp), %rdi
movl $128000000, %esi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movl $128000000, %esi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movl $1000000, %esi
call cudaMalloc@PLT
movl $1000000, %edx
movl $0, %esi
movq 72(%rsp), %rdi
call cudaMemset@PLT
movl $1, %ecx
movl $128000000, %edx
movq 8(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $128, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L22:
movl $2, %ecx
movl $128000000, %edx
movq 64(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $1000000, %edx
movq 72(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
call cudaThreadSynchronize@PLT
movq 40(%rsp), %rax
movl (%rax), %edx
movq 48(%rsp), %rax
movl %edx, (%rax)
movl $4, %eax
.L23:
movq 48(%rsp), %rcx
movl -4(%rcx,%rax), %edx
movq 40(%rsp), %rsi
addl (%rsi,%rax), %edx
movl %edx, (%rcx,%rax)
addq $4, %rax
cmpq $1000000, %rax
jne .L23
leaq 80(%rsp), %rdi
movl $1000000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $1000000, %edx
movq 48(%rsp), %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
leaq 88(%rsp), %rdi
movl $128000000, %esi
call cudaMalloc@PLT
movl $128, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $128, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L24:
movl $2, %ecx
movl $128000000, %edx
movq 88(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC1(%rip), %rbp
leaq .LC2(%rip), %r12
jmp .L26
.L37:
movl $7, %r8d
movl $250000, %ecx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z50__device_stub__Z24gpu_scan_sharemem_phaseIPiS_S_iiPiS_S_ii
jmp .L22
.L38:
movl $250000, %ecx
movq 80(%rsp), %rdx
movq 88(%rsp), %rsi
movq 64(%rsp), %rdi
call _Z51__device_stub__Z26gpu_scan_sharemem_phaseIIIPiS_S_iPiS_S_i
jmp .L24
.L25:
addq $1, %rbx
cmpq $200, %rbx
je .L39
.L26:
movq 24(%rsp), %rax
movl (%rax,%rbx,4), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %ebx, %rax
imulq $1717986919, %rax, %rax
sarq $34, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,4), %eax
addl %eax, %eax
cmpl %ebx, %eax
jne .L25
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L25
.L39:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
movq 24(%rsp), %rsi
movl $0, %edx
movl $0, %eax
.L29:
addl (%rdi,%rdx,4), %eax
movl %eax, %r8d
movl (%rsi,%rdx,4), %ecx
cmpl %eax, %ecx
jne .L40
addq $1, %rdx
cmpq $32000000, %rdx
jne .L29
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFreeHost@PLT
movq 16(%rsp), %rdi
call cudaFreeHost@PLT
movq 24(%rsp), %rdi
call cudaFreeHost@PLT
movq 32(%rsp), %rdi
call cudaFreeHost@PLT
movq 40(%rsp), %rdi
call cudaFreeHost@PLT
movq 48(%rsp), %rdi
call cudaFreeHost@PLT
movl $0, %eax
jmp .L19
.L40:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
.L19:
movq 120(%rsp), %rdx
subq %fs:40, %rdx
jne .L41
subq $-128, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC5:
.string "_Z26gpu_scan_sharemem_phaseIIIPiS_S_i"
.align 8
.LC6:
.string "_Z24gpu_scan_sharemem_phaseIPiS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z26gpu_scan_sharemem_phaseIIIPiS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z24gpu_scan_sharemem_phaseIPiS_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
__global__ void gpu_scan_sharemem_phaseI(int *in, int *out, int *aux, int size_tmp, int block_d){
__shared__ int tmp[2][128];
unsigned int myblock = blockIdx.x;
unsigned int tid = threadIdx.x;
while(myblock < size_tmp){
tmp[0][tid] = in[myblock*blockDim.x+threadIdx.x];
__syncthreads();
int iout = 0;
for (int d = 0; d < block_d; ++d){ //depth d
iout ^= 1;
int *tmp_out = tmp[iout];
int *tmp_in = tmp[iout ^ 1];
int t1 = tid - (1 << d); //tid - 2^d
if (t1 >= 0) { //tid > 2^d
tmp_out[tid] = tmp_in[tid] + tmp_in[t1];
}
else {
tmp_out[tid] = tmp_in[tid];
}
__syncthreads();
}
out[myblock*blockDim.x+threadIdx.x] = tmp[iout][tid];
aux[myblock] = tmp[iout][127]; //last element of each block for next scan
myblock+=128;
}
}
__global__ void gpu_scan_sharemem_phaseIII(int *d_out, int *d_out2, int *d_aux2, int size_tmp){
__shared__ int tmp[128];
unsigned int myblock = blockIdx.x;
unsigned int tid = threadIdx.x;
while(myblock < size_tmp){
tmp[tid] = d_out[myblock*blockDim.x+threadIdx.x];
__syncthreads();
if(myblock > 0){
tmp[tid] += d_aux2[myblock-1];
__syncthreads();
}
d_out2[myblock*blockDim.x+threadIdx.x] = tmp[tid];
myblock+=128;
}
}
int main()
{
int *in;
int *out;
int *out_2;
int *h_out;
int *aux;
int *aux_2;
int num_size = 32000000;
int size_tmp = (num_size + 127) / 128;
int block_d = 7; //depth of block, log2(128) = 7
cudaMallocHost((void **) &in, sizeof(int)*num_size);
cudaMallocHost((void **) &out, sizeof(int)*num_size);
cudaMallocHost((void **) &h_out, sizeof(int)*num_size);
cudaMallocHost((void **) &out_2, sizeof(int)*num_size);
cudaMallocHost((void **) &aux, sizeof(int)*size_tmp); //for checking itermediate values
cudaMallocHost((void **) &aux_2, sizeof(int)*size_tmp); //for checking the update itermediate values
for (int i = 0; i < num_size; i++) {
in[i] = i;
out[i] = 0;
}
for (int i = 0; i < size_tmp; i++) {
aux[i] = 0;
}
int *d_in;
int *d_out;
int *d_aux;
// int dszp = (num_size)*sizeof(int);
int dszp_aux = (size_tmp)*sizeof(int);
cudaMalloc((void **) &d_in, sizeof(int)*num_size);
cudaMalloc((void **) &d_out, sizeof(int)*num_size);
cudaMalloc((void **) &d_aux, sizeof(int)*size_tmp);
// cudaMemset(d_out, 0, dszp);
cudaMemset(d_aux, 0, dszp_aux);
// Phase1: scan original data per block and store last element of each block for later scan
cudaMemcpy(d_in, in, sizeof(int)*num_size, cudaMemcpyHostToDevice);
gpu_scan_sharemem_phaseI<<<128, 128>>>(d_in, d_out, d_aux, size_tmp, block_d);
cudaMemcpy(out, d_out, sizeof(int)*num_size, cudaMemcpyDeviceToHost);
cudaMemcpy(aux, d_aux, sizeof(int)*size_tmp, cudaMemcpyDeviceToHost);
cudaThreadSynchronize();
// Phase2: scan the last element of each block to accumulate the sum of each block
aux_2[0] = aux[0];
for(int i = 1; i < size_tmp; i++){
aux_2[i] = aux[i] + aux_2[i-1];
}
int *d_aux2;
cudaMalloc((void **) &d_aux2, sizeof(int)*size_tmp);
cudaMemcpy(d_aux2, aux_2, sizeof(int)*size_tmp, cudaMemcpyHostToDevice);
// Phase3: scan the last element of each block to accumulate the sum of each block
int *d_out2;
cudaMalloc((void **) &d_out2, sizeof(int)*num_size);
gpu_scan_sharemem_phaseIII<<<128, 128>>>(d_out, d_out2, d_aux2, size_tmp);
cudaMemcpy(out_2, d_out2, sizeof(int)*num_size, cudaMemcpyDeviceToHost);
// check the GPU results
printf("First 200 elements of the scan results:\n");
for (int i = 0; i < 200; i++){
printf("%d\t", out_2[i]);
if (i % 10 == 0) printf("\n");
}
printf("\n");
// printf("last 100 elements of the scan results:\n");
// for (int i = num_size-101; i < num_size-1; i++){
// printf("%d\t", out_2[i]);
// if (i % 10 == 0) printf("\n");
// }
// printf("\n");
// verify via comparasion with cpu version
int psum = 0;
for (int i = 0; i < num_size; i++){
psum += in[i];
if (psum != out_2[i]) {printf("mismatch at %d, was: %d, should be: %d\n", i, out_2[i], psum); return 1;}
}
printf("successfully scan!\n");
cudaFree(d_in);
cudaFree(d_out);
cudaFree(d_out2);
cudaFree(d_aux);
cudaFree(d_aux2);
cudaFreeHost(in);
cudaFreeHost(out);
cudaFreeHost(out_2);
cudaFreeHost(h_out);
cudaFreeHost(aux);
cudaFreeHost(aux_2);
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
__global__ void gpu_scan_sharemem_phaseI(int *in, int *out, int *aux, int size_tmp, int block_d){
__shared__ int tmp[2][128];
unsigned int myblock = blockIdx.x;
unsigned int tid = threadIdx.x;
while(myblock < size_tmp){
tmp[0][tid] = in[myblock*blockDim.x+threadIdx.x];
__syncthreads();
int iout = 0;
for (int d = 0; d < block_d; ++d){ //depth d
iout ^= 1;
int *tmp_out = tmp[iout];
int *tmp_in = tmp[iout ^ 1];
int t1 = tid - (1 << d); //tid - 2^d
if (t1 >= 0) { //tid > 2^d
tmp_out[tid] = tmp_in[tid] + tmp_in[t1];
}
else {
tmp_out[tid] = tmp_in[tid];
}
__syncthreads();
}
out[myblock*blockDim.x+threadIdx.x] = tmp[iout][tid];
aux[myblock] = tmp[iout][127]; //last element of each block for next scan
myblock+=128;
}
}
__global__ void gpu_scan_sharemem_phaseIII(int *d_out, int *d_out2, int *d_aux2, int size_tmp){
__shared__ int tmp[128];
unsigned int myblock = blockIdx.x;
unsigned int tid = threadIdx.x;
while(myblock < size_tmp){
tmp[tid] = d_out[myblock*blockDim.x+threadIdx.x];
__syncthreads();
if(myblock > 0){
tmp[tid] += d_aux2[myblock-1];
__syncthreads();
}
d_out2[myblock*blockDim.x+threadIdx.x] = tmp[tid];
myblock+=128;
}
}
int main()
{
int *in;
int *out;
int *out_2;
int *h_out;
int *aux;
int *aux_2;
int num_size = 32000000;
int size_tmp = (num_size + 127) / 128;
int block_d = 7; //depth of block, log2(128) = 7
hipHostMalloc((void **) &in, sizeof(int)*num_size, hipHostMallocDefault);
hipHostMalloc((void **) &out, sizeof(int)*num_size, hipHostMallocDefault);
hipHostMalloc((void **) &h_out, sizeof(int)*num_size, hipHostMallocDefault);
hipHostMalloc((void **) &out_2, sizeof(int)*num_size, hipHostMallocDefault);
hipHostMalloc((void **) &aux, sizeof(int)*size_tmp, hipHostMallocDefault); //for checking itermediate values
hipHostMalloc((void **) &aux_2, sizeof(int)*size_tmp, hipHostMallocDefault); //for checking the update itermediate values
for (int i = 0; i < num_size; i++) {
in[i] = i;
out[i] = 0;
}
for (int i = 0; i < size_tmp; i++) {
aux[i] = 0;
}
int *d_in;
int *d_out;
int *d_aux;
// int dszp = (num_size)*sizeof(int);
int dszp_aux = (size_tmp)*sizeof(int);
hipMalloc((void **) &d_in, sizeof(int)*num_size);
hipMalloc((void **) &d_out, sizeof(int)*num_size);
hipMalloc((void **) &d_aux, sizeof(int)*size_tmp);
// cudaMemset(d_out, 0, dszp);
hipMemset(d_aux, 0, dszp_aux);
// Phase1: scan original data per block and store last element of each block for later scan
hipMemcpy(d_in, in, sizeof(int)*num_size, hipMemcpyHostToDevice);
gpu_scan_sharemem_phaseI<<<128, 128>>>(d_in, d_out, d_aux, size_tmp, block_d);
hipMemcpy(out, d_out, sizeof(int)*num_size, hipMemcpyDeviceToHost);
hipMemcpy(aux, d_aux, sizeof(int)*size_tmp, hipMemcpyDeviceToHost);
hipDeviceSynchronize();
// Phase2: scan the last element of each block to accumulate the sum of each block
aux_2[0] = aux[0];
for(int i = 1; i < size_tmp; i++){
aux_2[i] = aux[i] + aux_2[i-1];
}
int *d_aux2;
hipMalloc((void **) &d_aux2, sizeof(int)*size_tmp);
hipMemcpy(d_aux2, aux_2, sizeof(int)*size_tmp, hipMemcpyHostToDevice);
// Phase3: scan the last element of each block to accumulate the sum of each block
int *d_out2;
hipMalloc((void **) &d_out2, sizeof(int)*num_size);
gpu_scan_sharemem_phaseIII<<<128, 128>>>(d_out, d_out2, d_aux2, size_tmp);
hipMemcpy(out_2, d_out2, sizeof(int)*num_size, hipMemcpyDeviceToHost);
// check the GPU results
printf("First 200 elements of the scan results:\n");
for (int i = 0; i < 200; i++){
printf("%d\t", out_2[i]);
if (i % 10 == 0) printf("\n");
}
printf("\n");
// printf("last 100 elements of the scan results:\n");
// for (int i = num_size-101; i < num_size-1; i++){
// printf("%d\t", out_2[i]);
// if (i % 10 == 0) printf("\n");
// }
// printf("\n");
// verify via comparasion with cpu version
int psum = 0;
for (int i = 0; i < num_size; i++){
psum += in[i];
if (psum != out_2[i]) {printf("mismatch at %d, was: %d, should be: %d\n", i, out_2[i], psum); return 1;}
}
printf("successfully scan!\n");
hipFree(d_in);
hipFree(d_out);
hipFree(d_out2);
hipFree(d_aux);
hipFree(d_aux2);
hipHostFree(in);
hipHostFree(out);
hipHostFree(out_2);
hipHostFree(h_out);
hipHostFree(aux);
hipHostFree(aux_2);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
__global__ void gpu_scan_sharemem_phaseI(int *in, int *out, int *aux, int size_tmp, int block_d){
__shared__ int tmp[2][128];
unsigned int myblock = blockIdx.x;
unsigned int tid = threadIdx.x;
while(myblock < size_tmp){
tmp[0][tid] = in[myblock*blockDim.x+threadIdx.x];
__syncthreads();
int iout = 0;
for (int d = 0; d < block_d; ++d){ //depth d
iout ^= 1;
int *tmp_out = tmp[iout];
int *tmp_in = tmp[iout ^ 1];
int t1 = tid - (1 << d); //tid - 2^d
if (t1 >= 0) { //tid > 2^d
tmp_out[tid] = tmp_in[tid] + tmp_in[t1];
}
else {
tmp_out[tid] = tmp_in[tid];
}
__syncthreads();
}
out[myblock*blockDim.x+threadIdx.x] = tmp[iout][tid];
aux[myblock] = tmp[iout][127]; //last element of each block for next scan
myblock+=128;
}
}
__global__ void gpu_scan_sharemem_phaseIII(int *d_out, int *d_out2, int *d_aux2, int size_tmp){
__shared__ int tmp[128];
unsigned int myblock = blockIdx.x;
unsigned int tid = threadIdx.x;
while(myblock < size_tmp){
tmp[tid] = d_out[myblock*blockDim.x+threadIdx.x];
__syncthreads();
if(myblock > 0){
tmp[tid] += d_aux2[myblock-1];
__syncthreads();
}
d_out2[myblock*blockDim.x+threadIdx.x] = tmp[tid];
myblock+=128;
}
}
int main()
{
int *in;
int *out;
int *out_2;
int *h_out;
int *aux;
int *aux_2;
int num_size = 32000000;
int size_tmp = (num_size + 127) / 128;
int block_d = 7; //depth of block, log2(128) = 7
hipHostMalloc((void **) &in, sizeof(int)*num_size, hipHostMallocDefault);
hipHostMalloc((void **) &out, sizeof(int)*num_size, hipHostMallocDefault);
hipHostMalloc((void **) &h_out, sizeof(int)*num_size, hipHostMallocDefault);
hipHostMalloc((void **) &out_2, sizeof(int)*num_size, hipHostMallocDefault);
hipHostMalloc((void **) &aux, sizeof(int)*size_tmp, hipHostMallocDefault); //for checking itermediate values
hipHostMalloc((void **) &aux_2, sizeof(int)*size_tmp, hipHostMallocDefault); //for checking the update itermediate values
for (int i = 0; i < num_size; i++) {
in[i] = i;
out[i] = 0;
}
for (int i = 0; i < size_tmp; i++) {
aux[i] = 0;
}
int *d_in;
int *d_out;
int *d_aux;
// int dszp = (num_size)*sizeof(int);
int dszp_aux = (size_tmp)*sizeof(int);
hipMalloc((void **) &d_in, sizeof(int)*num_size);
hipMalloc((void **) &d_out, sizeof(int)*num_size);
hipMalloc((void **) &d_aux, sizeof(int)*size_tmp);
// cudaMemset(d_out, 0, dszp);
hipMemset(d_aux, 0, dszp_aux);
// Phase1: scan original data per block and store last element of each block for later scan
hipMemcpy(d_in, in, sizeof(int)*num_size, hipMemcpyHostToDevice);
gpu_scan_sharemem_phaseI<<<128, 128>>>(d_in, d_out, d_aux, size_tmp, block_d);
hipMemcpy(out, d_out, sizeof(int)*num_size, hipMemcpyDeviceToHost);
hipMemcpy(aux, d_aux, sizeof(int)*size_tmp, hipMemcpyDeviceToHost);
hipDeviceSynchronize();
// Phase2: scan the last element of each block to accumulate the sum of each block
aux_2[0] = aux[0];
for(int i = 1; i < size_tmp; i++){
aux_2[i] = aux[i] + aux_2[i-1];
}
int *d_aux2;
hipMalloc((void **) &d_aux2, sizeof(int)*size_tmp);
hipMemcpy(d_aux2, aux_2, sizeof(int)*size_tmp, hipMemcpyHostToDevice);
// Phase3: scan the last element of each block to accumulate the sum of each block
int *d_out2;
hipMalloc((void **) &d_out2, sizeof(int)*num_size);
gpu_scan_sharemem_phaseIII<<<128, 128>>>(d_out, d_out2, d_aux2, size_tmp);
hipMemcpy(out_2, d_out2, sizeof(int)*num_size, hipMemcpyDeviceToHost);
// check the GPU results
printf("First 200 elements of the scan results:\n");
for (int i = 0; i < 200; i++){
printf("%d\t", out_2[i]);
if (i % 10 == 0) printf("\n");
}
printf("\n");
// printf("last 100 elements of the scan results:\n");
// for (int i = num_size-101; i < num_size-1; i++){
// printf("%d\t", out_2[i]);
// if (i % 10 == 0) printf("\n");
// }
// printf("\n");
// verify via comparasion with cpu version
int psum = 0;
for (int i = 0; i < num_size; i++){
psum += in[i];
if (psum != out_2[i]) {printf("mismatch at %d, was: %d, should be: %d\n", i, out_2[i], psum); return 1;}
}
printf("successfully scan!\n");
hipFree(d_in);
hipFree(d_out);
hipFree(d_out2);
hipFree(d_aux);
hipFree(d_aux2);
hipHostFree(in);
hipHostFree(out);
hipHostFree(out_2);
hipHostFree(h_out);
hipHostFree(aux);
hipHostFree(aux_2);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24gpu_scan_sharemem_phaseIPiS_S_ii
.globl _Z24gpu_scan_sharemem_phaseIPiS_S_ii
.p2align 8
.type _Z24gpu_scan_sharemem_phaseIPiS_S_ii,@function
_Z24gpu_scan_sharemem_phaseIPiS_S_ii:
s_load_b32 s8, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_ge_u32 s15, s8
s_cbranch_scc1 .LBB0_8
s_clause 0x3
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s9, s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_dual_mov_b32 v4, 0 :: v_dual_lshlrev_b32 v3, 2, v0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s10, s3, 0xffff
s_cmp_gt_i32 s9, 0
s_mov_b32 s3, 0
s_cselect_b32 s11, -1, 0
s_branch .LBB0_3
.LBB0_2:
s_set_inst_prefetch_distance 0x2
s_lshl_b32 s12, s12, 9
v_add_co_u32 v1, vcc_lo, s6, v1
v_lshl_add_u32 v5, v0, 2, s12
v_mov_b32_e32 v6, s12
s_lshl_b64 s[12:13], s[2:3], 2
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
ds_load_b32 v5, v5
ds_load_b32 v6, v6 offset:508
s_add_u32 s12, s0, s12
s_addc_u32 s13, s1, s13
s_addk_i32 s2, 0x80
s_waitcnt lgkmcnt(1)
global_store_b32 v[1:2], v5, off
s_waitcnt lgkmcnt(0)
global_store_b32 v4, v6, s[12:13]
s_cmp_ge_u32 s2, s8
s_cbranch_scc1 .LBB0_8
.LBB0_3:
v_mad_u64_u32 v[1:2], null, s2, s10, v[0:1]
v_mov_b32_e32 v2, v4
s_mov_b32 s12, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v5, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v2, vcc_lo
s_and_not1_b32 vcc_lo, exec_lo, s11
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0)
ds_store_b32 v3, v5
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB0_2
s_mov_b32 s13, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s15
s_xor_b32 s12, s12, 1
s_add_i32 s13, s13, 1
v_lshl_add_u32 v6, s12, 9, v3
s_cmp_eq_u32 s9, s13
s_waitcnt lgkmcnt(0)
ds_store_b32 v6, v5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_2
.LBB0_6:
s_lshl_b32 s14, s12, 9
v_lshl_add_u32 v6, -1, s13, v0
v_lshl_add_u32 v5, v0, 2, s14
s_mov_b32 s15, exec_lo
ds_load_b32 v5, v5
v_cmpx_lt_i32_e32 -1, v6
s_cbranch_execz .LBB0_5
v_lshl_add_u32 v6, v6, 2, s14
ds_load_b32 v6, v6
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v5, v6, v5
s_branch .LBB0_5
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24gpu_scan_sharemem_phaseIPiS_S_ii
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24gpu_scan_sharemem_phaseIPiS_S_ii, .Lfunc_end0-_Z24gpu_scan_sharemem_phaseIPiS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z26gpu_scan_sharemem_phaseIIIPiS_S_i
.globl _Z26gpu_scan_sharemem_phaseIIIPiS_S_i
.p2align 8
.type _Z26gpu_scan_sharemem_phaseIIIPiS_S_i,@function
_Z26gpu_scan_sharemem_phaseIIIPiS_S_i:
s_load_b32 s8, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_ge_u32 s15, s8
s_cbranch_scc1 .LBB1_5
s_clause 0x2
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_lshlrev_b32_e32 v0, 2, v0
v_mov_b32_e32 v2, 0
s_lshl_b32 s9, s2, 7
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_3
.p2align 6
.LBB1_2:
ds_load_b32 v5, v0
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
v_add_nc_u32_e32 v1, s9, v1
s_addk_i32 s15, 0x80
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_u32 s15, s8
s_waitcnt lgkmcnt(0)
global_store_b32 v[3:4], v5, off
s_cbranch_scc0 .LBB1_5
.LBB1_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_cmp_eq_u32 s15, 0
v_add_co_u32 v5, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0)
ds_store_b32 v0, v5
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_2
s_add_i32 s2, s15, -1
ds_load_b32 v6, v0
s_lshl_b64 s[10:11], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s10, s0, s10
s_addc_u32 s11, s1, s11
global_load_b32 v5, v2, s[10:11]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v5, v6, v5
ds_store_b32 v0, v5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_branch .LBB1_2
.LBB1_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26gpu_scan_sharemem_phaseIIIPiS_S_i
.amdhsa_group_segment_fixed_size 512
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z26gpu_scan_sharemem_phaseIIIPiS_S_i, .Lfunc_end1-_Z26gpu_scan_sharemem_phaseIIIPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24gpu_scan_sharemem_phaseIPiS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z24gpu_scan_sharemem_phaseIPiS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 512
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26gpu_scan_sharemem_phaseIIIPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z26gpu_scan_sharemem_phaseIIIPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
__global__ void gpu_scan_sharemem_phaseI(int *in, int *out, int *aux, int size_tmp, int block_d){
__shared__ int tmp[2][128];
unsigned int myblock = blockIdx.x;
unsigned int tid = threadIdx.x;
while(myblock < size_tmp){
tmp[0][tid] = in[myblock*blockDim.x+threadIdx.x];
__syncthreads();
int iout = 0;
for (int d = 0; d < block_d; ++d){ //depth d
iout ^= 1;
int *tmp_out = tmp[iout];
int *tmp_in = tmp[iout ^ 1];
int t1 = tid - (1 << d); //tid - 2^d
if (t1 >= 0) { //tid > 2^d
tmp_out[tid] = tmp_in[tid] + tmp_in[t1];
}
else {
tmp_out[tid] = tmp_in[tid];
}
__syncthreads();
}
out[myblock*blockDim.x+threadIdx.x] = tmp[iout][tid];
aux[myblock] = tmp[iout][127]; //last element of each block for next scan
myblock+=128;
}
}
__global__ void gpu_scan_sharemem_phaseIII(int *d_out, int *d_out2, int *d_aux2, int size_tmp){
__shared__ int tmp[128];
unsigned int myblock = blockIdx.x;
unsigned int tid = threadIdx.x;
while(myblock < size_tmp){
tmp[tid] = d_out[myblock*blockDim.x+threadIdx.x];
__syncthreads();
if(myblock > 0){
tmp[tid] += d_aux2[myblock-1];
__syncthreads();
}
d_out2[myblock*blockDim.x+threadIdx.x] = tmp[tid];
myblock+=128;
}
}
int main()
{
int *in;
int *out;
int *out_2;
int *h_out;
int *aux;
int *aux_2;
int num_size = 32000000;
int size_tmp = (num_size + 127) / 128;
int block_d = 7; //depth of block, log2(128) = 7
hipHostMalloc((void **) &in, sizeof(int)*num_size, hipHostMallocDefault);
hipHostMalloc((void **) &out, sizeof(int)*num_size, hipHostMallocDefault);
hipHostMalloc((void **) &h_out, sizeof(int)*num_size, hipHostMallocDefault);
hipHostMalloc((void **) &out_2, sizeof(int)*num_size, hipHostMallocDefault);
hipHostMalloc((void **) &aux, sizeof(int)*size_tmp, hipHostMallocDefault); //for checking itermediate values
hipHostMalloc((void **) &aux_2, sizeof(int)*size_tmp, hipHostMallocDefault); //for checking the update itermediate values
for (int i = 0; i < num_size; i++) {
in[i] = i;
out[i] = 0;
}
for (int i = 0; i < size_tmp; i++) {
aux[i] = 0;
}
int *d_in;
int *d_out;
int *d_aux;
// int dszp = (num_size)*sizeof(int);
int dszp_aux = (size_tmp)*sizeof(int);
hipMalloc((void **) &d_in, sizeof(int)*num_size);
hipMalloc((void **) &d_out, sizeof(int)*num_size);
hipMalloc((void **) &d_aux, sizeof(int)*size_tmp);
// cudaMemset(d_out, 0, dszp);
hipMemset(d_aux, 0, dszp_aux);
// Phase1: scan original data per block and store last element of each block for later scan
hipMemcpy(d_in, in, sizeof(int)*num_size, hipMemcpyHostToDevice);
gpu_scan_sharemem_phaseI<<<128, 128>>>(d_in, d_out, d_aux, size_tmp, block_d);
hipMemcpy(out, d_out, sizeof(int)*num_size, hipMemcpyDeviceToHost);
hipMemcpy(aux, d_aux, sizeof(int)*size_tmp, hipMemcpyDeviceToHost);
hipDeviceSynchronize();
// Phase2: scan the last element of each block to accumulate the sum of each block
aux_2[0] = aux[0];
for(int i = 1; i < size_tmp; i++){
aux_2[i] = aux[i] + aux_2[i-1];
}
int *d_aux2;
hipMalloc((void **) &d_aux2, sizeof(int)*size_tmp);
hipMemcpy(d_aux2, aux_2, sizeof(int)*size_tmp, hipMemcpyHostToDevice);
// Phase3: scan the last element of each block to accumulate the sum of each block
int *d_out2;
hipMalloc((void **) &d_out2, sizeof(int)*num_size);
gpu_scan_sharemem_phaseIII<<<128, 128>>>(d_out, d_out2, d_aux2, size_tmp);
hipMemcpy(out_2, d_out2, sizeof(int)*num_size, hipMemcpyDeviceToHost);
// check the GPU results
printf("First 200 elements of the scan results:\n");
for (int i = 0; i < 200; i++){
printf("%d\t", out_2[i]);
if (i % 10 == 0) printf("\n");
}
printf("\n");
// printf("last 100 elements of the scan results:\n");
// for (int i = num_size-101; i < num_size-1; i++){
// printf("%d\t", out_2[i]);
// if (i % 10 == 0) printf("\n");
// }
// printf("\n");
// verify via comparasion with cpu version
int psum = 0;
for (int i = 0; i < num_size; i++){
psum += in[i];
if (psum != out_2[i]) {printf("mismatch at %d, was: %d, should be: %d\n", i, out_2[i], psum); return 1;}
}
printf("successfully scan!\n");
hipFree(d_in);
hipFree(d_out);
hipFree(d_out2);
hipFree(d_aux);
hipFree(d_aux2);
hipHostFree(in);
hipHostFree(out);
hipHostFree(out_2);
hipHostFree(h_out);
hipHostFree(aux);
hipHostFree(aux_2);
return 0;
} | .text
.file "scan.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z39__device_stub__gpu_scan_sharemem_phaseIPiS_S_ii # -- Begin function _Z39__device_stub__gpu_scan_sharemem_phaseIPiS_S_ii
.p2align 4, 0x90
.type _Z39__device_stub__gpu_scan_sharemem_phaseIPiS_S_ii,@function
_Z39__device_stub__gpu_scan_sharemem_phaseIPiS_S_ii: # @_Z39__device_stub__gpu_scan_sharemem_phaseIPiS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z24gpu_scan_sharemem_phaseIPiS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z39__device_stub__gpu_scan_sharemem_phaseIPiS_S_ii, .Lfunc_end0-_Z39__device_stub__gpu_scan_sharemem_phaseIPiS_S_ii
.cfi_endproc
# -- End function
.globl _Z41__device_stub__gpu_scan_sharemem_phaseIIIPiS_S_i # -- Begin function _Z41__device_stub__gpu_scan_sharemem_phaseIIIPiS_S_i
.p2align 4, 0x90
.type _Z41__device_stub__gpu_scan_sharemem_phaseIIIPiS_S_i,@function
_Z41__device_stub__gpu_scan_sharemem_phaseIIIPiS_S_i: # @_Z41__device_stub__gpu_scan_sharemem_phaseIIIPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26gpu_scan_sharemem_phaseIIIPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z41__device_stub__gpu_scan_sharemem_phaseIIIPiS_S_i, .Lfunc_end1-_Z41__device_stub__gpu_scan_sharemem_phaseIIIPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $208, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 48(%rsp), %rdi
xorl %ebx, %ebx
movl $128000000, %esi # imm = 0x7A12000
xorl %edx, %edx
callq hipHostMalloc
leaq 72(%rsp), %rdi
movl $128000000, %esi # imm = 0x7A12000
xorl %edx, %edx
callq hipHostMalloc
leaq 200(%rsp), %rdi
movl $128000000, %esi # imm = 0x7A12000
xorl %edx, %edx
callq hipHostMalloc
leaq 40(%rsp), %rdi
movl $128000000, %esi # imm = 0x7A12000
xorl %edx, %edx
callq hipHostMalloc
leaq 32(%rsp), %rdi
movl $1000000, %esi # imm = 0xF4240
xorl %edx, %edx
callq hipHostMalloc
leaq 64(%rsp), %rdi
movl $1000000, %esi # imm = 0xF4240
xorl %edx, %edx
callq hipHostMalloc
movq 48(%rsp), %rax
movq 72(%rsp), %rcx
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl %ebx, (%rax,%rbx,4)
movl $0, (%rcx,%rbx,4)
incq %rbx
cmpq $32000000, %rbx # imm = 0x1E84800
jne .LBB2_1
# %bb.2: # %.preheader
movabsq $4294967424, %rbx # imm = 0x100000080
movq 32(%rsp), %rdi
movl $1000000, %edx # imm = 0xF4240
xorl %esi, %esi
callq memset@PLT
leaq 56(%rsp), %rdi
movl $128000000, %esi # imm = 0x7A12000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $128000000, %esi # imm = 0x7A12000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $1000000, %esi # imm = 0xF4240
callq hipMalloc
movq 16(%rsp), %rdi
movl $1000000, %edx # imm = 0xF4240
xorl %esi, %esi
callq hipMemset
movq 56(%rsp), %rdi
movq 48(%rsp), %rsi
movl $128000000, %edx # imm = 0x7A12000
movl $1, %ecx
callq hipMemcpy
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 56(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movq %rdx, 128(%rsp)
movl $250000, 8(%rsp) # imm = 0x3D090
movl $7, (%rsp)
leaq 144(%rsp), %rax
movq %rax, 160(%rsp)
leaq 136(%rsp), %rax
movq %rax, 168(%rsp)
leaq 128(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
movq %rsp, %rax
movq %rax, 192(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z24gpu_scan_sharemem_phaseIPiS_S_ii, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq 72(%rsp), %rdi
movq 24(%rsp), %rsi
movl $128000000, %edx # imm = 0x7A12000
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movq 16(%rsp), %rsi
movl $1000000, %edx # imm = 0xF4240
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
movq 32(%rsp), %rax
movl (%rax), %ecx
movq 64(%rsp), %rdx
movl %ecx, (%rdx)
movl $1, %esi
.p2align 4, 0x90
.LBB2_5: # =>This Inner Loop Header: Depth=1
addl (%rax,%rsi,4), %ecx
movl %ecx, (%rdx,%rsi,4)
incq %rsi
cmpq $250000, %rsi # imm = 0x3D090
jne .LBB2_5
# %bb.6:
leaq 8(%rsp), %rdi
movl $1000000, %esi # imm = 0xF4240
callq hipMalloc
movq 8(%rsp), %rdi
movq 64(%rsp), %rsi
movl $1000000, %edx # imm = 0xF4240
movl $1, %ecx
callq hipMemcpy
movq %rsp, %rdi
movl $128000000, %esi # imm = 0x7A12000
callq hipMalloc
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movq 24(%rsp), %rax
movq (%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movq %rdx, 128(%rsp)
movl $250000, 156(%rsp) # imm = 0x3D090
leaq 144(%rsp), %rax
movq %rax, 160(%rsp)
leaq 136(%rsp), %rax
movq %rax, 168(%rsp)
leaq 128(%rsp), %rax
movq %rax, 176(%rsp)
leaq 156(%rsp), %rax
movq %rax, 184(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z26gpu_scan_sharemem_phaseIIIPiS_S_i, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8:
movq 40(%rsp), %rdi
movq (%rsp), %rsi
movl $128000000, %edx # imm = 0x7A12000
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
movq $-800, %rbx # imm = 0xFCE0
movl $3435973837, %r14d # imm = 0xCCCCCCCD
xorl %ebp, %ebp
xorl %r15d, %r15d
jmp .LBB2_9
.p2align 4, 0x90
.LBB2_11: # in Loop: Header=BB2_9 Depth=1
decl %r15d
incl %ebp
addq $4, %rbx
je .LBB2_12
.LBB2_9: # =>This Inner Loop Header: Depth=1
movl %ebp, %eax
imulq %r14, %rax
shrq $35, %rax
leal (%rax,%rax,4), %r12d
addl %r12d, %r12d
movq 40(%rsp), %rax
movl 800(%rax,%rbx), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
addl %r15d, %r12d
jne .LBB2_11
# %bb.10: # in Loop: Header=BB2_9 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB2_11
.LBB2_12:
movl $10, %edi
callq putchar@PLT
movq 48(%rsp), %rax
movq 40(%rsp), %rdi
movl (%rax), %ecx
movl (%rdi), %edx
xorl %esi, %esi
cmpl %edx, %ecx
jne .LBB2_13
# %bb.17: # %.lr.ph.preheader
xorl %esi, %esi
.p2align 4, 0x90
.LBB2_18: # %.lr.ph
# =>This Inner Loop Header: Depth=1
cmpq $31999999, %rsi # imm = 0x1E847FF
je .LBB2_19
# %bb.14: # in Loop: Header=BB2_18 Depth=1
addl 4(%rax,%rsi,4), %ecx
movl 4(%rdi,%rsi,4), %edx
incq %rsi
cmpl %edx, %ecx
je .LBB2_18
# %bb.15: # %._crit_edge
leaq -1(%rsi), %rax
cmpq $31999999, %rax # imm = 0x1E847FF
setae %bl
jmp .LBB2_16
.LBB2_13:
xorl %ebx, %ebx
.LBB2_16:
movl $.L.str.3, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
movl $1, %eax
testb %bl, %bl
je .LBB2_22
.LBB2_21:
movl $.Lstr.1, %edi
callq puts@PLT
movq 56(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipHostFree
movq 72(%rsp), %rdi
callq hipHostFree
movq 40(%rsp), %rdi
callq hipHostFree
movq 200(%rsp), %rdi
callq hipHostFree
movq 32(%rsp), %rdi
callq hipHostFree
movq 64(%rsp), %rdi
callq hipHostFree
xorl %eax, %eax
.LBB2_22:
addq $208, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_19: # %.loopexit.loopexit
.cfi_def_cfa_offset 256
setae %bl
xorl %eax, %eax
testb %bl, %bl
jne .LBB2_21
jmp .LBB2_22
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24gpu_scan_sharemem_phaseIPiS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26gpu_scan_sharemem_phaseIIIPiS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24gpu_scan_sharemem_phaseIPiS_S_ii,@object # @_Z24gpu_scan_sharemem_phaseIPiS_S_ii
.section .rodata,"a",@progbits
.globl _Z24gpu_scan_sharemem_phaseIPiS_S_ii
.p2align 3, 0x0
_Z24gpu_scan_sharemem_phaseIPiS_S_ii:
.quad _Z39__device_stub__gpu_scan_sharemem_phaseIPiS_S_ii
.size _Z24gpu_scan_sharemem_phaseIPiS_S_ii, 8
.type _Z26gpu_scan_sharemem_phaseIIIPiS_S_i,@object # @_Z26gpu_scan_sharemem_phaseIIIPiS_S_i
.globl _Z26gpu_scan_sharemem_phaseIIIPiS_S_i
.p2align 3, 0x0
_Z26gpu_scan_sharemem_phaseIIIPiS_S_i:
.quad _Z41__device_stub__gpu_scan_sharemem_phaseIIIPiS_S_i
.size _Z26gpu_scan_sharemem_phaseIIIPiS_S_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d\t"
.size .L.str.1, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "mismatch at %d, was: %d, should be: %d\n"
.size .L.str.3, 40
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z24gpu_scan_sharemem_phaseIPiS_S_ii"
.size .L__unnamed_1, 37
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z26gpu_scan_sharemem_phaseIIIPiS_S_i"
.size .L__unnamed_2, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "First 200 elements of the scan results:"
.size .Lstr, 40
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "successfully scan!"
.size .Lstr.1, 19
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__gpu_scan_sharemem_phaseIPiS_S_ii
.addrsig_sym _Z41__device_stub__gpu_scan_sharemem_phaseIIIPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24gpu_scan_sharemem_phaseIPiS_S_ii
.addrsig_sym _Z26gpu_scan_sharemem_phaseIIIPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z26gpu_scan_sharemem_phaseIIIPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x001fda0003f06070 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002100 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0060*/ IMAD R6, R0, c[0x0][0x0], R11 ; /* 0x0000000000067a24 */
/* 0x001fe400078e020b */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*0080*/ IMAD.WIDE.U32 R2, R6, R5, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fca00078e0005 */
/*0090*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IADD3 R4, R0, -0x1, RZ ; /* 0xffffffff00047810 */
/* 0x000fc80007ffe0ff */
/*00b0*/ ISETP.NE.AND P0, PT, R4, -0x1, PT ; /* 0xffffffff0400780c */
/* 0x000fda0003f05270 */
/*00c0*/ @P0 IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004040625 */
/* 0x000fe200078e0005 */
/*00d0*/ STS [R11.X4], R7 ; /* 0x000000070b007388 */
/* 0x004fe80000004800 */
/*00e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00f0*/ @P0 LDG.E R5, [R4.64] ; /* 0x0000000404050981 */
/* 0x000ea2000c1e1900 */
/*0100*/ IADD3 R0, R0, 0x80, RZ ; /* 0x0000008000007810 */
/* 0x000fc60007ffe0ff */
/*0110*/ @P0 LDS R8, [R11.X4] ; /* 0x000000000b080984 */
/* 0x000ea40000004800 */
/*0120*/ @P0 IADD3 R8, R8, R5, RZ ; /* 0x0000000508080210 */
/* 0x004fe20007ffe0ff */
/*0130*/ IMAD.MOV.U32 R5, RZ, RZ, 0x80 ; /* 0x00000080ff057424 */
/* 0x000fc800078e00ff */
/*0140*/ @P0 STS [R11.X4], R8 ; /* 0x000000080b000388 */
/* 0x000fe80000004800 */
/*0150*/ @P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000000b1d */
/* 0x000fe20000010000 */
/*0160*/ LEA R2, P0, R6, c[0x0][0x168], 0x2 ; /* 0x00005a0006027a11 */
/* 0x000fc800078010ff */
/*0170*/ LEA.HI.X R3, R6, c[0x0][0x16c], RZ, 0x2, P0 ; /* 0x00005b0006037a11 */
/* 0x000fe200000f14ff */
/*0180*/ IMAD R6, R5, c[0x0][0x0], R6 ; /* 0x0000000005067a24 */
/* 0x000fe200078e0206 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06070 */
/*01a0*/ LDS R9, [R11.X4] ; /* 0x000000000b097984 */
/* 0x000e280000004800 */
/*01b0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0011f0000c101904 */
/*01c0*/ @!P0 BRA 0x70 ; /* 0xfffffea000008947 */
/* 0x000fea000383ffff */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z24gpu_scan_sharemem_phaseIPiS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x178], PT ; /* 0x00005e0005007a0c */
/* 0x001fda0003f06070 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0050*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff027624 */
/* 0x000fe200078e00ff */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*0070*/ LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fc800078ec0ff */
/*0080*/ IADD3 R4, -R2, c[0x0][0x17c], RZ ; /* 0x00005f0002047a10 */
/* 0x000fe20007ffe1ff */
/*0090*/ IMAD.SHL.U32 R3, R0, 0x4, RZ ; /* 0x0000000400037824 */
/* 0x001fca00078e00ff */
/*00a0*/ IADD3 R6, R3, 0x200, RZ ; /* 0x0000020003067810 */
/* 0x000fe40007ffe0ff */
/*00b0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x001fe400078e00ff */
/*00c0*/ IMAD R7, R5, c[0x0][0x0], R0 ; /* 0x0000000005077a24 */
/* 0x000fc800078e0200 */
/*00d0*/ IMAD.WIDE.U32 R10, R7, R8, c[0x0][0x160] ; /* 0x00005800070a7625 */
/* 0x000fcc00078e0008 */
/*00e0*/ LDG.E R11, [R10.64] ; /* 0x000000060a0b7981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff097624 */
/* 0x000fe200078e00ff */
/*0100*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0110*/ IMAD.MOV.U32 R12, RZ, RZ, R3 ; /* 0x000000ffff0c7224 */
/* 0x000fc600078e0003 */
/*0120*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fe20003f06270 */
/*0130*/ STS [R0.X4], R11 ; /* 0x0000000b00007388 */
/* 0x0041e80000004800 */
/*0140*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*0150*/ @!P0 BRA 0x6d0 ; /* 0x0000057000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R9, R9, -0x1, RZ ; /* 0xffffffff09097810 */
/* 0x001fe40007ffe0ff */
/*0170*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fc40003f05270 */
/*0180*/ ISETP.GE.U32.AND P1, PT, R9, 0x3, PT ; /* 0x000000030900780c */
/* 0x000fe20003f26070 */
/*0190*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fd800078e00ff */
/*01a0*/ @!P1 BRA 0x450 ; /* 0x000002a000009947 */
/* 0x000fea0003800000 */
/*01b0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe400078e00ff */
/*01c0*/ IMAD.MOV.U32 R10, RZ, RZ, R4 ; /* 0x000000ffff0a7224 */
/* 0x000fc800078e0004 */
/*01d0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x000fe200078e00ff */
/*01e0*/ IADD3 R10, R10, -0x4, RZ ; /* 0xfffffffc0a0a7810 */
/* 0x000fe20007ffe0ff */
/*01f0*/ IMAD.MOV.U32 R12, RZ, RZ, 0x2 ; /* 0x00000002ff0c7424 */
/* 0x000fc600078e00ff */
/*0200*/ SHF.L.U32 R11, R8, R9.reuse, RZ ; /* 0x00000009080b7219 */
/* 0x080fe400000006ff */
/*0210*/ SHF.L.U32 R13, R12, R9, RZ ; /* 0x000000090c0d7219 */
/* 0x000fc600000006ff */
/*0220*/ IMAD.IADD R14, R0.reuse, 0x1, -R11 ; /* 0x00000001000e7824 */
/* 0x040fe400078e0a0b */
/*0230*/ LDS R11, [R0.X4] ; /* 0x00000000000b7984 */
/* 0x000fe20000004800 */
/*0240*/ IMAD.IADD R16, R0, 0x1, -R13 ; /* 0x0000000100107824 */
/* 0x000fe400078e0a0d */
/*0250*/ ISETP.GE.AND P2, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fc60003f46270 */
/*0260*/ ISETP.GE.AND P1, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fd40003f26270 */
/*0270*/ @P2 LDS R8, [R14.X4] ; /* 0x000000000e082984 */
/* 0x0000640000004800 */
/*0280*/ IMAD.MOV.U32 R14, RZ, RZ, 0x8 ; /* 0x00000008ff0e7424 */
/* 0x001fe400078e00ff */
/*0290*/ @P2 IMAD.IADD R11, R11, 0x1, R8 ; /* 0x000000010b0b2824 */
/* 0x002fe400078e0208 */
/*02a0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fc600078e00ff */
/*02b0*/ STS [R0.X4+0x200], R11 ; /* 0x0002000b00007388 */
/* 0x000fe40000004800 */
/*02c0*/ SHF.L.U32 R15, R8, R9.reuse, RZ ; /* 0x00000009080f7219 */
/* 0x080fe400000006ff */
/*02d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*02e0*/ IMAD.IADD R17, R0, 0x1, -R15 ; /* 0x0000000100117824 */
/* 0x000fe200078e0a0f */
/*02f0*/ SHF.L.U32 R15, R14, R9, RZ ; /* 0x000000090e0f7219 */
/* 0x000fe400000006ff */
/*0300*/ IADD3 R9, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fc40007ffe0ff */
/*0310*/ ISETP.GE.AND P2, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fe20003f46270 */
/*0320*/ IMAD.IADD R15, R0, 0x1, -R15 ; /* 0x00000001000f7824 */
/* 0x000fe200078e0a0f */
/*0330*/ @P1 LDS R12, [R16.X4+0x200] ; /* 0x00020000100c1984 */
/* 0x000fe80000004800 */
/*0340*/ LDS R13, [R0.X4+0x200] ; /* 0x00020000000d7984 */
/* 0x000e240000004800 */
/*0350*/ @P1 IADD3 R13, R13, R12, RZ ; /* 0x0000000c0d0d1210 */
/* 0x001fe40007ffe0ff */
/*0360*/ ISETP.GE.AND P1, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fc60003f26270 */
/*0370*/ STS [R0.X4], R13 ; /* 0x0000000d00007388 */
/* 0x000fe80000004800 */
/*0380*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0390*/ @P2 LDS R12, [R17.X4] ; /* 0x00000000110c2984 */
/* 0x000fe80000004800 */
/*03a0*/ LDS R11, [R0.X4] ; /* 0x00000000000b7984 */
/* 0x000e240000004800 */
/*03b0*/ @P2 IMAD.IADD R11, R11, 0x1, R12 ; /* 0x000000010b0b2824 */
/* 0x001fca00078e020c */
/*03c0*/ STS [R0.X4+0x200], R11 ; /* 0x0002000b00007388 */
/* 0x000fe80000004800 */
/*03d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03e0*/ @P1 LDS R12, [R15.X4+0x200] ; /* 0x000200000f0c1984 */
/* 0x000fe80000004800 */
/*03f0*/ LDS R13, [R0.X4+0x200] ; /* 0x00020000000d7984 */
/* 0x000e240000004800 */
/*0400*/ @P1 IMAD.IADD R13, R13, 0x1, R12 ; /* 0x000000010d0d1824 */
/* 0x001fe200078e020c */
/*0410*/ ISETP.NE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fc80003f25270 */
/*0420*/ STS [R0.X4], R13 ; /* 0x0000000d00007388 */
/* 0x0001e80000004800 */
/*0430*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0440*/ @P1 BRA 0x1d0 ; /* 0xfffffd8000001947 */
/* 0x001fea000383ffff */
/*0450*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0460*/ IMAD.MOV.U32 R12, RZ, RZ, R3 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0003 */
/*0470*/ @!P0 BRA 0x6d0 ; /* 0x0000025000008947 */
/* 0x000fea0003800000 */
/*0480*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1 ; /* 0x00000001ff0e7424 */
/* 0x000fe200078e00ff */
/*0490*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe20000000000 */
/*04a0*/ MOV R12, R6 ; /* 0x00000006000c7202 */
/* 0x000fc60000000f00 */
/*04b0*/ SHF.L.U32 R11, R14, R9, RZ ; /* 0x000000090e0b7219 */
/* 0x000fca00000006ff */
/*04c0*/ IMAD.IADD R10, R0, 0x1, -R11 ; /* 0x00000001000a7824 */
/* 0x000fe400078e0a0b */
/*04d0*/ LDS R11, [R0.X4] ; /* 0x00000000000b7984 */
/* 0x000fe60000004800 */
/*04e0*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f06270 */
/*04f0*/ @P0 LDS R10, [R10.X4] ; /* 0x000000000a0a0984 */
/* 0x000e240000004800 */
/*0500*/ @P0 IMAD.IADD R11, R11, 0x1, R10 ; /* 0x000000010b0b0824 */
/* 0x001fe200078e020a */
/*0510*/ ISETP.NE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fc80003f05270 */
/*0520*/ STS [R0.X4+0x200], R11 ; /* 0x0002000b00007388 */
/* 0x0001e80000004800 */
/*0530*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0540*/ @!P0 BRA 0x6d0 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0550*/ IADD3 R10, R9, 0x1, RZ ; /* 0x00000001090a7810 */
/* 0x001fe20007ffe0ff */
/*0560*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0570*/ IMAD.MOV.U32 R12, RZ, RZ, R3 ; /* 0x000000ffff0c7224 */
/* 0x000fc400078e0003 */
/*0580*/ SHF.L.U32 R11, R14, R10, RZ ; /* 0x0000000a0e0b7219 */
/* 0x000fca00000006ff */
/*0590*/ IMAD.IADD R10, R0, 0x1, -R11 ; /* 0x00000001000a7824 */
/* 0x000fe400078e0a0b */
/*05a0*/ LDS R11, [R0.X4+0x200] ; /* 0x00020000000b7984 */
/* 0x000fe60000004800 */
/*05b0*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f06270 */
/*05c0*/ @P0 LDS R10, [R10.X4+0x200] ; /* 0x000200000a0a0984 */
/* 0x000e240000004800 */
/*05d0*/ @P0 IMAD.IADD R11, R11, 0x1, R10 ; /* 0x000000010b0b0824 */
/* 0x001fe200078e020a */
/*05e0*/ ISETP.NE.AND P0, PT, R2, 0x2, PT ; /* 0x000000020200780c */
/* 0x000fc80003f05270 */
/*05f0*/ STS [R0.X4], R11 ; /* 0x0000000b00007388 */
/* 0x0001e80000004800 */
/*0600*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0610*/ @!P0 BRA 0x6d0 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0620*/ IADD3 R9, R9, 0x2, RZ ; /* 0x0000000209097810 */
/* 0x001fe20007ffe0ff */
/*0630*/ IMAD.MOV.U32 R12, RZ, RZ, R6 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0006 */
/*0640*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fc40000000000 */
/*0650*/ SHF.L.U32 R9, R14, R9, RZ ; /* 0x000000090e097219 */
/* 0x000fca00000006ff */
/*0660*/ IMAD.IADD R10, R0, 0x1, -R9 ; /* 0x00000001000a7824 */
/* 0x000fe400078e0a09 */
/*0670*/ LDS R9, [R0.X4] ; /* 0x0000000000097984 */
/* 0x000fe60000004800 */
/*0680*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f06270 */
/*0690*/ @P0 LDS R10, [R10.X4] ; /* 0x000000000a0a0984 */
/* 0x000e240000004800 */
/*06a0*/ @P0 IMAD.IADD R9, R9, 0x1, R10 ; /* 0x0000000109090824 */
/* 0x001fca00078e020a */
/*06b0*/ STS [R0.X4+0x200], R9 ; /* 0x0002000900007388 */
/* 0x0001e80000004800 */
/*06c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*06d0*/ USHF.L.U32 UR4, UR4, 0x9, URZ ; /* 0x0000000904047899 */
/* 0x001fe2000800063f */
/*06e0*/ LDS R13, [R12] ; /* 0x000000000c0d7984 */
/* 0x000e220000000800 */
/*06f0*/ LEA R10, P0, R7, c[0x0][0x168], 0x2 ; /* 0x00005a00070a7a11 */
/* 0x000fe200078010ff */
/*0700*/ IMAD.WIDE.U32 R8, R5.reuse, R8, c[0x0][0x170] ; /* 0x00005c0005087625 */
/* 0x040fe200078e0008 */
/*0710*/ IADD3 R5, R5, 0x80, RZ ; /* 0x0000008005057810 */
/* 0x000fe40007ffe0ff */
/*0720*/ LEA.HI.X R11, R7, c[0x0][0x16c], RZ, 0x2, P0 ; /* 0x00005b00070b7a11 */
/* 0x000fc400000f14ff */
/*0730*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x178], PT ; /* 0x00005e0005007a0c */
/* 0x000fe20003f06070 */
/*0740*/ LDS R15, [UR4+0x1fc] ; /* 0x0001fc04ff0f7984 */
/* 0x000e680008000800 */
/*0750*/ STG.E [R10.64], R13 ; /* 0x0000000d0a007986 */
/* 0x0011e8000c101906 */
/*0760*/ STG.E [R8.64], R15 ; /* 0x0000000f08007986 */
/* 0x0021e8000c101906 */
/*0770*/ @!P0 BRA 0xb0 ; /* 0xfffff93000008947 */
/* 0x000fea000383ffff */
/*0780*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0790*/ BRA 0x790; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24gpu_scan_sharemem_phaseIPiS_S_ii
.globl _Z24gpu_scan_sharemem_phaseIPiS_S_ii
.p2align 8
.type _Z24gpu_scan_sharemem_phaseIPiS_S_ii,@function
_Z24gpu_scan_sharemem_phaseIPiS_S_ii:
s_load_b32 s8, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_ge_u32 s15, s8
s_cbranch_scc1 .LBB0_8
s_clause 0x3
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s9, s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_dual_mov_b32 v4, 0 :: v_dual_lshlrev_b32 v3, 2, v0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s10, s3, 0xffff
s_cmp_gt_i32 s9, 0
s_mov_b32 s3, 0
s_cselect_b32 s11, -1, 0
s_branch .LBB0_3
.LBB0_2:
s_set_inst_prefetch_distance 0x2
s_lshl_b32 s12, s12, 9
v_add_co_u32 v1, vcc_lo, s6, v1
v_lshl_add_u32 v5, v0, 2, s12
v_mov_b32_e32 v6, s12
s_lshl_b64 s[12:13], s[2:3], 2
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
ds_load_b32 v5, v5
ds_load_b32 v6, v6 offset:508
s_add_u32 s12, s0, s12
s_addc_u32 s13, s1, s13
s_addk_i32 s2, 0x80
s_waitcnt lgkmcnt(1)
global_store_b32 v[1:2], v5, off
s_waitcnt lgkmcnt(0)
global_store_b32 v4, v6, s[12:13]
s_cmp_ge_u32 s2, s8
s_cbranch_scc1 .LBB0_8
.LBB0_3:
v_mad_u64_u32 v[1:2], null, s2, s10, v[0:1]
v_mov_b32_e32 v2, v4
s_mov_b32 s12, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v5, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v2, vcc_lo
s_and_not1_b32 vcc_lo, exec_lo, s11
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0)
ds_store_b32 v3, v5
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB0_2
s_mov_b32 s13, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s15
s_xor_b32 s12, s12, 1
s_add_i32 s13, s13, 1
v_lshl_add_u32 v6, s12, 9, v3
s_cmp_eq_u32 s9, s13
s_waitcnt lgkmcnt(0)
ds_store_b32 v6, v5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_2
.LBB0_6:
s_lshl_b32 s14, s12, 9
v_lshl_add_u32 v6, -1, s13, v0
v_lshl_add_u32 v5, v0, 2, s14
s_mov_b32 s15, exec_lo
ds_load_b32 v5, v5
v_cmpx_lt_i32_e32 -1, v6
s_cbranch_execz .LBB0_5
v_lshl_add_u32 v6, v6, 2, s14
ds_load_b32 v6, v6
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v5, v6, v5
s_branch .LBB0_5
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24gpu_scan_sharemem_phaseIPiS_S_ii
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24gpu_scan_sharemem_phaseIPiS_S_ii, .Lfunc_end0-_Z24gpu_scan_sharemem_phaseIPiS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z26gpu_scan_sharemem_phaseIIIPiS_S_i
.globl _Z26gpu_scan_sharemem_phaseIIIPiS_S_i
.p2align 8
.type _Z26gpu_scan_sharemem_phaseIIIPiS_S_i,@function
_Z26gpu_scan_sharemem_phaseIIIPiS_S_i:
s_load_b32 s8, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_ge_u32 s15, s8
s_cbranch_scc1 .LBB1_5
s_clause 0x2
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_lshlrev_b32_e32 v0, 2, v0
v_mov_b32_e32 v2, 0
s_lshl_b32 s9, s2, 7
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_3
.p2align 6
.LBB1_2:
ds_load_b32 v5, v0
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
v_add_nc_u32_e32 v1, s9, v1
s_addk_i32 s15, 0x80
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_u32 s15, s8
s_waitcnt lgkmcnt(0)
global_store_b32 v[3:4], v5, off
s_cbranch_scc0 .LBB1_5
.LBB1_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_cmp_eq_u32 s15, 0
v_add_co_u32 v5, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0)
ds_store_b32 v0, v5
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_2
s_add_i32 s2, s15, -1
ds_load_b32 v6, v0
s_lshl_b64 s[10:11], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s10, s0, s10
s_addc_u32 s11, s1, s11
global_load_b32 v5, v2, s[10:11]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v5, v6, v5
ds_store_b32 v0, v5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_branch .LBB1_2
.LBB1_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26gpu_scan_sharemem_phaseIIIPiS_S_i
.amdhsa_group_segment_fixed_size 512
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z26gpu_scan_sharemem_phaseIIIPiS_S_i, .Lfunc_end1-_Z26gpu_scan_sharemem_phaseIIIPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24gpu_scan_sharemem_phaseIPiS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z24gpu_scan_sharemem_phaseIPiS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 512
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26gpu_scan_sharemem_phaseIIIPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z26gpu_scan_sharemem_phaseIIIPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00123a33_00000000-6_scan.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z24gpu_scan_sharemem_phaseIPiS_S_iiPiS_S_ii
.type _Z50__device_stub__Z24gpu_scan_sharemem_phaseIPiS_S_iiPiS_S_ii, @function
_Z50__device_stub__Z24gpu_scan_sharemem_phaseIPiS_S_iiPiS_S_ii:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z24gpu_scan_sharemem_phaseIPiS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z50__device_stub__Z24gpu_scan_sharemem_phaseIPiS_S_iiPiS_S_ii, .-_Z50__device_stub__Z24gpu_scan_sharemem_phaseIPiS_S_iiPiS_S_ii
.globl _Z24gpu_scan_sharemem_phaseIPiS_S_ii
.type _Z24gpu_scan_sharemem_phaseIPiS_S_ii, @function
_Z24gpu_scan_sharemem_phaseIPiS_S_ii:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z24gpu_scan_sharemem_phaseIPiS_S_iiPiS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z24gpu_scan_sharemem_phaseIPiS_S_ii, .-_Z24gpu_scan_sharemem_phaseIPiS_S_ii
.globl _Z51__device_stub__Z26gpu_scan_sharemem_phaseIIIPiS_S_iPiS_S_i
.type _Z51__device_stub__Z26gpu_scan_sharemem_phaseIIIPiS_S_iPiS_S_i, @function
_Z51__device_stub__Z26gpu_scan_sharemem_phaseIIIPiS_S_iPiS_S_i:
.LFB3696:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z26gpu_scan_sharemem_phaseIIIPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z51__device_stub__Z26gpu_scan_sharemem_phaseIIIPiS_S_iPiS_S_i, .-_Z51__device_stub__Z26gpu_scan_sharemem_phaseIIIPiS_S_iPiS_S_i
.globl _Z26gpu_scan_sharemem_phaseIIIPiS_S_i
.type _Z26gpu_scan_sharemem_phaseIIIPiS_S_i, @function
_Z26gpu_scan_sharemem_phaseIIIPiS_S_i:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z26gpu_scan_sharemem_phaseIIIPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z26gpu_scan_sharemem_phaseIIIPiS_S_i, .-_Z26gpu_scan_sharemem_phaseIIIPiS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "First 200 elements of the scan results:\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%d\t"
.LC2:
.string "\n"
.section .rodata.str1.8
.align 8
.LC3:
.string "mismatch at %d, was: %d, should be: %d\n"
.section .rodata.str1.1
.LC4:
.string "successfully scan!\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
addq $-128, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $128000000, %esi
call cudaMallocHost@PLT
leaq 16(%rsp), %rdi
movl $128000000, %esi
call cudaMallocHost@PLT
leaq 32(%rsp), %rdi
movl $128000000, %esi
call cudaMallocHost@PLT
leaq 24(%rsp), %rdi
movl $128000000, %esi
call cudaMallocHost@PLT
leaq 40(%rsp), %rdi
movl $1000000, %esi
call cudaMallocHost@PLT
leaq 48(%rsp), %rdi
movl $1000000, %esi
call cudaMallocHost@PLT
movl $0, %eax
.L20:
movq 8(%rsp), %rdx
movl %eax, (%rdx,%rax,4)
movq 16(%rsp), %rdx
movl $0, (%rdx,%rax,4)
addq $1, %rax
cmpq $32000000, %rax
jne .L20
movl $0, %eax
.L21:
movq 40(%rsp), %rdx
movl $0, (%rdx,%rax)
addq $4, %rax
cmpq $1000000, %rax
jne .L21
leaq 56(%rsp), %rdi
movl $128000000, %esi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movl $128000000, %esi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movl $1000000, %esi
call cudaMalloc@PLT
movl $1000000, %edx
movl $0, %esi
movq 72(%rsp), %rdi
call cudaMemset@PLT
movl $1, %ecx
movl $128000000, %edx
movq 8(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $128, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L22:
movl $2, %ecx
movl $128000000, %edx
movq 64(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $1000000, %edx
movq 72(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
call cudaThreadSynchronize@PLT
movq 40(%rsp), %rax
movl (%rax), %edx
movq 48(%rsp), %rax
movl %edx, (%rax)
movl $4, %eax
.L23:
movq 48(%rsp), %rcx
movl -4(%rcx,%rax), %edx
movq 40(%rsp), %rsi
addl (%rsi,%rax), %edx
movl %edx, (%rcx,%rax)
addq $4, %rax
cmpq $1000000, %rax
jne .L23
leaq 80(%rsp), %rdi
movl $1000000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $1000000, %edx
movq 48(%rsp), %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
leaq 88(%rsp), %rdi
movl $128000000, %esi
call cudaMalloc@PLT
movl $128, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $128, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L24:
movl $2, %ecx
movl $128000000, %edx
movq 88(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC1(%rip), %rbp
leaq .LC2(%rip), %r12
jmp .L26
.L37:
movl $7, %r8d
movl $250000, %ecx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z50__device_stub__Z24gpu_scan_sharemem_phaseIPiS_S_iiPiS_S_ii
jmp .L22
.L38:
movl $250000, %ecx
movq 80(%rsp), %rdx
movq 88(%rsp), %rsi
movq 64(%rsp), %rdi
call _Z51__device_stub__Z26gpu_scan_sharemem_phaseIIIPiS_S_iPiS_S_i
jmp .L24
.L25:
addq $1, %rbx
cmpq $200, %rbx
je .L39
.L26:
movq 24(%rsp), %rax
movl (%rax,%rbx,4), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %ebx, %rax
imulq $1717986919, %rax, %rax
sarq $34, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,4), %eax
addl %eax, %eax
cmpl %ebx, %eax
jne .L25
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L25
.L39:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
movq 24(%rsp), %rsi
movl $0, %edx
movl $0, %eax
.L29:
addl (%rdi,%rdx,4), %eax
movl %eax, %r8d
movl (%rsi,%rdx,4), %ecx
cmpl %eax, %ecx
jne .L40
addq $1, %rdx
cmpq $32000000, %rdx
jne .L29
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFreeHost@PLT
movq 16(%rsp), %rdi
call cudaFreeHost@PLT
movq 24(%rsp), %rdi
call cudaFreeHost@PLT
movq 32(%rsp), %rdi
call cudaFreeHost@PLT
movq 40(%rsp), %rdi
call cudaFreeHost@PLT
movq 48(%rsp), %rdi
call cudaFreeHost@PLT
movl $0, %eax
jmp .L19
.L40:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
.L19:
movq 120(%rsp), %rdx
subq %fs:40, %rdx
jne .L41
subq $-128, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC5:
.string "_Z26gpu_scan_sharemem_phaseIIIPiS_S_i"
.align 8
.LC6:
.string "_Z24gpu_scan_sharemem_phaseIPiS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z26gpu_scan_sharemem_phaseIIIPiS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z24gpu_scan_sharemem_phaseIPiS_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "scan.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z39__device_stub__gpu_scan_sharemem_phaseIPiS_S_ii # -- Begin function _Z39__device_stub__gpu_scan_sharemem_phaseIPiS_S_ii
.p2align 4, 0x90
.type _Z39__device_stub__gpu_scan_sharemem_phaseIPiS_S_ii,@function
_Z39__device_stub__gpu_scan_sharemem_phaseIPiS_S_ii: # @_Z39__device_stub__gpu_scan_sharemem_phaseIPiS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z24gpu_scan_sharemem_phaseIPiS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z39__device_stub__gpu_scan_sharemem_phaseIPiS_S_ii, .Lfunc_end0-_Z39__device_stub__gpu_scan_sharemem_phaseIPiS_S_ii
.cfi_endproc
# -- End function
.globl _Z41__device_stub__gpu_scan_sharemem_phaseIIIPiS_S_i # -- Begin function _Z41__device_stub__gpu_scan_sharemem_phaseIIIPiS_S_i
.p2align 4, 0x90
.type _Z41__device_stub__gpu_scan_sharemem_phaseIIIPiS_S_i,@function
_Z41__device_stub__gpu_scan_sharemem_phaseIIIPiS_S_i: # @_Z41__device_stub__gpu_scan_sharemem_phaseIIIPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26gpu_scan_sharemem_phaseIIIPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z41__device_stub__gpu_scan_sharemem_phaseIIIPiS_S_i, .Lfunc_end1-_Z41__device_stub__gpu_scan_sharemem_phaseIIIPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $208, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 48(%rsp), %rdi
xorl %ebx, %ebx
movl $128000000, %esi # imm = 0x7A12000
xorl %edx, %edx
callq hipHostMalloc
leaq 72(%rsp), %rdi
movl $128000000, %esi # imm = 0x7A12000
xorl %edx, %edx
callq hipHostMalloc
leaq 200(%rsp), %rdi
movl $128000000, %esi # imm = 0x7A12000
xorl %edx, %edx
callq hipHostMalloc
leaq 40(%rsp), %rdi
movl $128000000, %esi # imm = 0x7A12000
xorl %edx, %edx
callq hipHostMalloc
leaq 32(%rsp), %rdi
movl $1000000, %esi # imm = 0xF4240
xorl %edx, %edx
callq hipHostMalloc
leaq 64(%rsp), %rdi
movl $1000000, %esi # imm = 0xF4240
xorl %edx, %edx
callq hipHostMalloc
movq 48(%rsp), %rax
movq 72(%rsp), %rcx
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl %ebx, (%rax,%rbx,4)
movl $0, (%rcx,%rbx,4)
incq %rbx
cmpq $32000000, %rbx # imm = 0x1E84800
jne .LBB2_1
# %bb.2: # %.preheader
movabsq $4294967424, %rbx # imm = 0x100000080
movq 32(%rsp), %rdi
movl $1000000, %edx # imm = 0xF4240
xorl %esi, %esi
callq memset@PLT
leaq 56(%rsp), %rdi
movl $128000000, %esi # imm = 0x7A12000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $128000000, %esi # imm = 0x7A12000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $1000000, %esi # imm = 0xF4240
callq hipMalloc
movq 16(%rsp), %rdi
movl $1000000, %edx # imm = 0xF4240
xorl %esi, %esi
callq hipMemset
movq 56(%rsp), %rdi
movq 48(%rsp), %rsi
movl $128000000, %edx # imm = 0x7A12000
movl $1, %ecx
callq hipMemcpy
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 56(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movq %rdx, 128(%rsp)
movl $250000, 8(%rsp) # imm = 0x3D090
movl $7, (%rsp)
leaq 144(%rsp), %rax
movq %rax, 160(%rsp)
leaq 136(%rsp), %rax
movq %rax, 168(%rsp)
leaq 128(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
movq %rsp, %rax
movq %rax, 192(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z24gpu_scan_sharemem_phaseIPiS_S_ii, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq 72(%rsp), %rdi
movq 24(%rsp), %rsi
movl $128000000, %edx # imm = 0x7A12000
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movq 16(%rsp), %rsi
movl $1000000, %edx # imm = 0xF4240
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
movq 32(%rsp), %rax
movl (%rax), %ecx
movq 64(%rsp), %rdx
movl %ecx, (%rdx)
movl $1, %esi
.p2align 4, 0x90
.LBB2_5: # =>This Inner Loop Header: Depth=1
addl (%rax,%rsi,4), %ecx
movl %ecx, (%rdx,%rsi,4)
incq %rsi
cmpq $250000, %rsi # imm = 0x3D090
jne .LBB2_5
# %bb.6:
leaq 8(%rsp), %rdi
movl $1000000, %esi # imm = 0xF4240
callq hipMalloc
movq 8(%rsp), %rdi
movq 64(%rsp), %rsi
movl $1000000, %edx # imm = 0xF4240
movl $1, %ecx
callq hipMemcpy
movq %rsp, %rdi
movl $128000000, %esi # imm = 0x7A12000
callq hipMalloc
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movq 24(%rsp), %rax
movq (%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movq %rdx, 128(%rsp)
movl $250000, 156(%rsp) # imm = 0x3D090
leaq 144(%rsp), %rax
movq %rax, 160(%rsp)
leaq 136(%rsp), %rax
movq %rax, 168(%rsp)
leaq 128(%rsp), %rax
movq %rax, 176(%rsp)
leaq 156(%rsp), %rax
movq %rax, 184(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z26gpu_scan_sharemem_phaseIIIPiS_S_i, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8:
movq 40(%rsp), %rdi
movq (%rsp), %rsi
movl $128000000, %edx # imm = 0x7A12000
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
movq $-800, %rbx # imm = 0xFCE0
movl $3435973837, %r14d # imm = 0xCCCCCCCD
xorl %ebp, %ebp
xorl %r15d, %r15d
jmp .LBB2_9
.p2align 4, 0x90
.LBB2_11: # in Loop: Header=BB2_9 Depth=1
decl %r15d
incl %ebp
addq $4, %rbx
je .LBB2_12
.LBB2_9: # =>This Inner Loop Header: Depth=1
movl %ebp, %eax
imulq %r14, %rax
shrq $35, %rax
leal (%rax,%rax,4), %r12d
addl %r12d, %r12d
movq 40(%rsp), %rax
movl 800(%rax,%rbx), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
addl %r15d, %r12d
jne .LBB2_11
# %bb.10: # in Loop: Header=BB2_9 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB2_11
.LBB2_12:
movl $10, %edi
callq putchar@PLT
movq 48(%rsp), %rax
movq 40(%rsp), %rdi
movl (%rax), %ecx
movl (%rdi), %edx
xorl %esi, %esi
cmpl %edx, %ecx
jne .LBB2_13
# %bb.17: # %.lr.ph.preheader
xorl %esi, %esi
.p2align 4, 0x90
.LBB2_18: # %.lr.ph
# =>This Inner Loop Header: Depth=1
cmpq $31999999, %rsi # imm = 0x1E847FF
je .LBB2_19
# %bb.14: # in Loop: Header=BB2_18 Depth=1
addl 4(%rax,%rsi,4), %ecx
movl 4(%rdi,%rsi,4), %edx
incq %rsi
cmpl %edx, %ecx
je .LBB2_18
# %bb.15: # %._crit_edge
leaq -1(%rsi), %rax
cmpq $31999999, %rax # imm = 0x1E847FF
setae %bl
jmp .LBB2_16
.LBB2_13:
xorl %ebx, %ebx
.LBB2_16:
movl $.L.str.3, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
movl $1, %eax
testb %bl, %bl
je .LBB2_22
.LBB2_21:
movl $.Lstr.1, %edi
callq puts@PLT
movq 56(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipHostFree
movq 72(%rsp), %rdi
callq hipHostFree
movq 40(%rsp), %rdi
callq hipHostFree
movq 200(%rsp), %rdi
callq hipHostFree
movq 32(%rsp), %rdi
callq hipHostFree
movq 64(%rsp), %rdi
callq hipHostFree
xorl %eax, %eax
.LBB2_22:
addq $208, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_19: # %.loopexit.loopexit
.cfi_def_cfa_offset 256
setae %bl
xorl %eax, %eax
testb %bl, %bl
jne .LBB2_21
jmp .LBB2_22
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24gpu_scan_sharemem_phaseIPiS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26gpu_scan_sharemem_phaseIIIPiS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24gpu_scan_sharemem_phaseIPiS_S_ii,@object # @_Z24gpu_scan_sharemem_phaseIPiS_S_ii
.section .rodata,"a",@progbits
.globl _Z24gpu_scan_sharemem_phaseIPiS_S_ii
.p2align 3, 0x0
_Z24gpu_scan_sharemem_phaseIPiS_S_ii:
.quad _Z39__device_stub__gpu_scan_sharemem_phaseIPiS_S_ii
.size _Z24gpu_scan_sharemem_phaseIPiS_S_ii, 8
.type _Z26gpu_scan_sharemem_phaseIIIPiS_S_i,@object # @_Z26gpu_scan_sharemem_phaseIIIPiS_S_i
.globl _Z26gpu_scan_sharemem_phaseIIIPiS_S_i
.p2align 3, 0x0
_Z26gpu_scan_sharemem_phaseIIIPiS_S_i:
.quad _Z41__device_stub__gpu_scan_sharemem_phaseIIIPiS_S_i
.size _Z26gpu_scan_sharemem_phaseIIIPiS_S_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d\t"
.size .L.str.1, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "mismatch at %d, was: %d, should be: %d\n"
.size .L.str.3, 40
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z24gpu_scan_sharemem_phaseIPiS_S_ii"
.size .L__unnamed_1, 37
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z26gpu_scan_sharemem_phaseIIIPiS_S_i"
.size .L__unnamed_2, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "First 200 elements of the scan results:"
.size .Lstr, 40
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "successfully scan!"
.size .Lstr.1, 19
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__gpu_scan_sharemem_phaseIPiS_S_ii
.addrsig_sym _Z41__device_stub__gpu_scan_sharemem_phaseIIIPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24gpu_scan_sharemem_phaseIPiS_S_ii
.addrsig_sym _Z26gpu_scan_sharemem_phaseIIIPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
int main(){
printf("Hello World!!!");
return 0;
} | code for sm_80 |
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