system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void add( double *a, double *b, double *c, int n )
{
int tid = threadIdx.x + blockIdx.x * blockDim.x;
// handle the data at this index
while (tid < n) {
c[tid] = a[tid] + b[tid];
tid += blockDim.x * gridDim.x;
}
//printf("Value of *ip variable: %f\n", a[tid] );
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPdS_S_i
.globl _Z3addPdS_S_i
.p2align 8
.type _Z3addPdS_S_i,@function
_Z3addPdS_S_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s8, s[0:1], 0x18
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_3
s_load_b32 s10, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s10, s9
s_mov_b32 s9, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 3, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s8, v1
global_load_b64 v[4:5], v[4:5], off
global_load_b64 v[6:7], v[6:7], off
v_add_co_u32 v2, s0, s2, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_or_b32 s9, vcc_lo, s9
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], v[6:7]
global_store_b64 v[2:3], v[4:5], off
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPdS_S_i, .Lfunc_end0-_Z3addPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void add( double *a, double *b, double *c, int n )
{
int tid = threadIdx.x + blockIdx.x * blockDim.x;
// handle the data at this index
while (tid < n) {
c[tid] = a[tid] + b[tid];
tid += blockDim.x * gridDim.x;
}
//printf("Value of *ip variable: %f\n", a[tid] );
} | .text
.file "add.hip"
.globl _Z18__device_stub__addPdS_S_i # -- Begin function _Z18__device_stub__addPdS_S_i
.p2align 4, 0x90
.type _Z18__device_stub__addPdS_S_i,@function
_Z18__device_stub__addPdS_S_i: # @_Z18__device_stub__addPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__addPdS_S_i, .Lfunc_end0-_Z18__device_stub__addPdS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPdS_S_i,@object # @_Z3addPdS_S_i
.section .rodata,"a",@progbits
.globl _Z3addPdS_S_i
.p2align 3, 0x0
_Z3addPdS_S_i:
.quad _Z18__device_stub__addPdS_S_i
.size _Z3addPdS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addPdS_S_i"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R9, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0209 */
/*0090*/ IMAD.WIDE R4, R0.reuse, R9.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0209 */
/*00a0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD.WIDE R8, R0, R9, c[0x0][0x170] ; /* 0x00005c0000087625 */
/* 0x000fe200078e0209 */
/*00d0*/ MOV R11, c[0x0][0x0] ; /* 0x00000000000b7a02 */
/* 0x000fca0000000f00 */
/*00e0*/ IMAD R0, R11, c[0x0][0xc], R0 ; /* 0x000003000b007a24 */
/* 0x000fca00078e0200 */
/*00f0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06270 */
/*0100*/ DADD R6, R4, R2 ; /* 0x0000000004067229 */
/* 0x004e0e0000000002 */
/*0110*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x0011ea000c101b04 */
/*0120*/ @!P0 BRA 0x70 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPdS_S_i
.globl _Z3addPdS_S_i
.p2align 8
.type _Z3addPdS_S_i,@function
_Z3addPdS_S_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s8, s[0:1], 0x18
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_3
s_load_b32 s10, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s10, s9
s_mov_b32 s9, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 3, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s8, v1
global_load_b64 v[4:5], v[4:5], off
global_load_b64 v[6:7], v[6:7], off
v_add_co_u32 v2, s0, s2, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_or_b32 s9, vcc_lo, s9
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], v[6:7]
global_store_b64 v[2:3], v[4:5], off
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPdS_S_i, .Lfunc_end0-_Z3addPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007b200_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z3addPdS_S_iPdS_S_i
.type _Z27__device_stub__Z3addPdS_S_iPdS_S_i, @function
_Z27__device_stub__Z3addPdS_S_iPdS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z3addPdS_S_iPdS_S_i, .-_Z27__device_stub__Z3addPdS_S_iPdS_S_i
.globl _Z3addPdS_S_i
.type _Z3addPdS_S_i, @function
_Z3addPdS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3addPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3addPdS_S_i, .-_Z3addPdS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add.hip"
.globl _Z18__device_stub__addPdS_S_i # -- Begin function _Z18__device_stub__addPdS_S_i
.p2align 4, 0x90
.type _Z18__device_stub__addPdS_S_i,@function
_Z18__device_stub__addPdS_S_i: # @_Z18__device_stub__addPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__addPdS_S_i, .Lfunc_end0-_Z18__device_stub__addPdS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPdS_S_i,@object # @_Z3addPdS_S_i
.section .rodata,"a",@progbits
.globl _Z3addPdS_S_i
.p2align 3, 0x0
_Z3addPdS_S_i:
.quad _Z18__device_stub__addPdS_S_i
.size _Z3addPdS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addPdS_S_i"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <iostream>
using namespace std;
#define BLOCK_SIZE 16
#define BASE_TYPE double
__global__ void matrixMult(const BASE_TYPE *A, BASE_TYPE *C, int Acols, int Arows)
{
int i0 = Acols *(blockDim.y*blockIdx.y + threadIdx.y);
//int iAT = Arows*(blockDim.x*blockIdx.x + threadIdx.x) + blockDim.y*blockIdx.y + threadIdx.y;
BASE_TYPE sum = 0;
for (int k = 0; k < Acols; k++)
{
sum = +A[i0 + k] * A[i0+k];
}
int ind = Acols* (blockDim.y*blockIdx.y + threadIdx.y) + blockDim.x*blockIdx.x + threadIdx.x;
C[ind] = sum;
}
int main()
{
int Arows = 100;
int Acols = 200;
size_t Asize = Arows*Acols * sizeof(BASE_TYPE);
BASE_TYPE *h_A = (BASE_TYPE *)malloc(Asize);
BASE_TYPE *h_C = (BASE_TYPE *)malloc(Asize);
for (int i = 0; i < Arows*Acols; i++)
{
h_A[i] = rand() / (BASE_TYPE)RAND_MAX;
}
for (int i = 0; i < Arows*Acols; i++)
{
printf("h_A[%d]=%d ", i, h_A[i]);
}
BASE_TYPE *d_A = NULL;
cudaMalloc((void **)&d_A, Asize);
BASE_TYPE *d_C = NULL;
cudaMalloc((void **)&d_C, Asize);
cudaMemcpy(d_A, h_A, Asize, cudaMemcpyHostToDevice);
dim3 threadsPerBlock = dim3(BLOCK_SIZE, BLOCK_SIZE);
dim3 blocksPerGrid = dim3(Acols / BLOCK_SIZE, Arows / BLOCK_SIZE);
matrixMult <<<blocksPerGrid, threadsPerBlock >>> (d_A, d_C, Acols, Arows);
cudaMemcpy(h_C, d_C, Asize, cudaMemcpyDeviceToHost);
printf("Test Started\n");
bool t = false;
for (int i = 0; i < Arows; i++)
{
for (int j = 0; j < Arows; j++)
{
if (h_C[i*Arows + j] !=1)
{
t = true;
//fprintf(stderr, "Result verification failed at element [%d,%d]!\n", i, j);
//printf("sum=%f,h_C[i*Arows + j]=%f\n", 1, h_C[i*Arows + j]);
//exit(EXIT_FAILURE);
printf("Matrix A is not orthogonal\n");
}
if (t) break;
}
if (t) break;
}
printf("Test Passed\n");
cudaFree(d_A);
cudaFree(d_C);
free(h_A);
free(h_C);
getchar();
system("pause");
} | code for sm_80
Function : _Z10matrixMultPKdPdii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fe2000001ff00 */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e240000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x001fd800078e0205 */
/*0080*/ @!P0 BRA 0x310 ; /* 0x0000028000008947 */
/* 0x000fea0003800000 */
/*0090*/ IADD3 R2, R4, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x000fe20007ffe0ff */
/*00a0*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fc600078e00ff */
/*00b0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*00c0*/ LOP3.LUT R2, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304027812 */
/* 0x000fd600078ec0ff */
/*00d0*/ @!P0 BRA 0x250 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*00e0*/ IADD3 R3, -R2, c[0x0][0x170], RZ ; /* 0x00005c0002037a10 */
/* 0x000fe20007ffe1ff */
/*00f0*/ IMAD.MOV.U32 R5, RZ, RZ, -0x1 ; /* 0xffffffffff057424 */
/* 0x000fc600078e00ff */
/*0100*/ ISETP.GT.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f04270 */
/*0110*/ @!P0 BRA 0x200 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0120*/ ISETP.GT.AND P1, PT, R3, 0xc, PT ; /* 0x0000000c0300780c */
/* 0x000fe40003f24270 */
/*0130*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0140*/ @!P1 BRA 0x1a0 ; /* 0x0000005000009947 */
/* 0x000fea0003800000 */
/*0150*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0160*/ IADD3 R3, R3, -0x10, RZ ; /* 0xfffffff003037810 */
/* 0x000fe40007ffe0ff */
/*0170*/ IADD3 R5, R5, 0x10, RZ ; /* 0x0000001005057810 */
/* 0x000fe40007ffe0ff */
/*0180*/ ISETP.GT.AND P1, PT, R3, 0xc, PT ; /* 0x0000000c0300780c */
/* 0x000fda0003f24270 */
/*0190*/ @P1 BRA 0x160 ; /* 0xffffffc000001947 */
/* 0x000fea000383ffff */
/*01a0*/ ISETP.GT.AND P1, PT, R3, 0x4, PT ; /* 0x000000040300780c */
/* 0x000fda0003f24270 */
/*01b0*/ @P1 PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000181c */
/* 0x000fe40003f0e170 */
/*01c0*/ @P1 IADD3 R3, R3, -0x8, RZ ; /* 0xfffffff803031810 */
/* 0x000fe40007ffe0ff */
/*01d0*/ @P1 IADD3 R5, R5, 0x8, RZ ; /* 0x0000000805051810 */
/* 0x000fd20007ffe0ff */
/*01e0*/ ISETP.NE.OR P0, PT, R3, RZ, P0 ; /* 0x000000ff0300720c */
/* 0x000fda0000705670 */
/*01f0*/ @!P0 BRA 0x240 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0200*/ IADD3 R3, R3, -0x4, RZ ; /* 0xfffffffc03037810 */
/* 0x000fe40007ffe0ff */
/*0210*/ IADD3 R5, R5, 0x4, RZ ; /* 0x0000000405057810 */
/* 0x000fe40007ffe0ff */
/*0220*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*0230*/ @P0 BRA 0x200 ; /* 0xffffffc000000947 */
/* 0x000fea000383ffff */
/*0240*/ IADD3 R3, R5, 0x1, RZ ; /* 0x0000000105037810 */
/* 0x000fe40007ffe0ff */
/*0250*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*0260*/ IMAD.MOV.U32 R4, RZ, RZ, 0x8 ; /* 0x00000008ff047424 */
/* 0x000fd800078e00ff */
/*0270*/ @!P0 BRA 0x2d0 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0280*/ IADD3 R5, R3, -0x1, RZ ; /* 0xffffffff03057810 */
/* 0x000fe40007ffe0ff */
/*0290*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*02a0*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fe40007ffe0ff */
/*02b0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*02c0*/ @P0 BRA 0x290 ; /* 0xffffffc000000947 */
/* 0x000fea000383ffff */
/*02d0*/ IMAD R5, R0, c[0x0][0x170], R5 ; /* 0x00005c0000057a24 */
/* 0x000fc800078e0205 */
/*02e0*/ IMAD.WIDE R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fcc00078e0204 */
/*02f0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1b00 */
/*0300*/ DMUL R2, R4, R4 ; /* 0x0000000404027228 */
/* 0x0040480000000000 */
/*0310*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x001e280000002500 */
/*0320*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e240000002100 */
/*0330*/ IMAD R5, R5, c[0x0][0x0], R4 ; /* 0x0000000005057a24 */
/* 0x001fe400078e0204 */
/*0340*/ IMAD.MOV.U32 R4, RZ, RZ, 0x8 ; /* 0x00000008ff047424 */
/* 0x000fc400078e00ff */
/*0350*/ IMAD R5, R0, c[0x0][0x170], R5 ; /* 0x00005c0000057a24 */
/* 0x000fc800078e0205 */
/*0360*/ IMAD.WIDE R4, R5, R4, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e0204 */
/*0370*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x002fe2000c101b04 */
/*0380*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0390*/ BRA 0x390; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <iostream>
using namespace std;
#define BLOCK_SIZE 16
#define BASE_TYPE double
__global__ void matrixMult(const BASE_TYPE *A, BASE_TYPE *C, int Acols, int Arows)
{
int i0 = Acols *(blockDim.y*blockIdx.y + threadIdx.y);
//int iAT = Arows*(blockDim.x*blockIdx.x + threadIdx.x) + blockDim.y*blockIdx.y + threadIdx.y;
BASE_TYPE sum = 0;
for (int k = 0; k < Acols; k++)
{
sum = +A[i0 + k] * A[i0+k];
}
int ind = Acols* (blockDim.y*blockIdx.y + threadIdx.y) + blockDim.x*blockIdx.x + threadIdx.x;
C[ind] = sum;
}
int main()
{
int Arows = 100;
int Acols = 200;
size_t Asize = Arows*Acols * sizeof(BASE_TYPE);
BASE_TYPE *h_A = (BASE_TYPE *)malloc(Asize);
BASE_TYPE *h_C = (BASE_TYPE *)malloc(Asize);
for (int i = 0; i < Arows*Acols; i++)
{
h_A[i] = rand() / (BASE_TYPE)RAND_MAX;
}
for (int i = 0; i < Arows*Acols; i++)
{
printf("h_A[%d]=%d ", i, h_A[i]);
}
BASE_TYPE *d_A = NULL;
cudaMalloc((void **)&d_A, Asize);
BASE_TYPE *d_C = NULL;
cudaMalloc((void **)&d_C, Asize);
cudaMemcpy(d_A, h_A, Asize, cudaMemcpyHostToDevice);
dim3 threadsPerBlock = dim3(BLOCK_SIZE, BLOCK_SIZE);
dim3 blocksPerGrid = dim3(Acols / BLOCK_SIZE, Arows / BLOCK_SIZE);
matrixMult <<<blocksPerGrid, threadsPerBlock >>> (d_A, d_C, Acols, Arows);
cudaMemcpy(h_C, d_C, Asize, cudaMemcpyDeviceToHost);
printf("Test Started\n");
bool t = false;
for (int i = 0; i < Arows; i++)
{
for (int j = 0; j < Arows; j++)
{
if (h_C[i*Arows + j] !=1)
{
t = true;
//fprintf(stderr, "Result verification failed at element [%d,%d]!\n", i, j);
//printf("sum=%f,h_C[i*Arows + j]=%f\n", 1, h_C[i*Arows + j]);
//exit(EXIT_FAILURE);
printf("Matrix A is not orthogonal\n");
}
if (t) break;
}
if (t) break;
}
printf("Test Passed\n");
cudaFree(d_A);
cudaFree(d_C);
free(h_A);
free(h_C);
getchar();
system("pause");
} | .file "tmpxft_000e4aa7_00000000-6_kernel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10matrixMultPKdPdiiPKdPdii
.type _Z35__device_stub__Z10matrixMultPKdPdiiPKdPdii, @function
_Z35__device_stub__Z10matrixMultPKdPdiiPKdPdii:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10matrixMultPKdPdii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z35__device_stub__Z10matrixMultPKdPdiiPKdPdii, .-_Z35__device_stub__Z10matrixMultPKdPdiiPKdPdii
.globl _Z10matrixMultPKdPdii
.type _Z10matrixMultPKdPdii, @function
_Z10matrixMultPKdPdii:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10matrixMultPKdPdiiPKdPdii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z10matrixMultPKdPdii, .-_Z10matrixMultPKdPdii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "h_A[%d]=%d "
.LC2:
.string "Test Started\n"
.LC4:
.string "Matrix A is not orthogonal\n"
.LC5:
.string "Test Passed\n"
.LC6:
.string "pause"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $160000, %edi
call malloc@PLT
movq %rax, %rbp
movl $160000, %edi
call malloc@PLT
movq %rax, %r12
movq %rbp, %rbx
leaq 160000(%rbp), %r13
.L12:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC0(%rip), %xmm0
movsd %xmm0, (%rbx)
addq $8, %rbx
cmpq %r13, %rbx
jne .L12
movl $0, %ebx
leaq .LC1(%rip), %r13
.L13:
movsd 0(%rbp,%rbx,8), %xmm0
movl %ebx, %edx
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $20000, %rbx
jne .L13
movq $0, (%rsp)
movq %rsp, %rdi
movl $160000, %esi
call cudaMalloc@PLT
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $160000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $160000, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 16(%rsp)
movl $16, 20(%rsp)
movl $12, 28(%rsp)
movl $6, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L14:
movl $2, %ecx
movl $160000, %edx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 800(%r12), %rdx
leaq 80800(%r12), %rcx
movsd .LC3(%rip), %xmm0
movapd %xmm0, %xmm1
jmp .L15
.L26:
movl $100, %ecx
movl $200, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z35__device_stub__Z10matrixMultPKdPdiiPKdPdii
jmp .L14
.L21:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L18:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq stdin(%rip), %rdi
call getc@PLT
leaq .LC6(%rip), %rdi
call system@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L27
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
addq $800, %rdx
cmpq %rcx, %rdx
je .L18
.L15:
leaq -800(%rdx), %rax
.L19:
ucomisd (%rax), %xmm0
jp .L21
ucomisd (%rax), %xmm1
jne .L21
addq $8, %rax
cmpq %rdx, %rax
jne .L19
jmp .L28
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z10matrixMultPKdPdii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z10matrixMultPKdPdii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -4194304
.long 1105199103
.align 8
.LC3:
.long 0
.long 1072693248
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <iostream>
using namespace std;
#define BLOCK_SIZE 16
#define BASE_TYPE double
__global__ void matrixMult(const BASE_TYPE *A, BASE_TYPE *C, int Acols, int Arows)
{
int i0 = Acols *(blockDim.y*blockIdx.y + threadIdx.y);
//int iAT = Arows*(blockDim.x*blockIdx.x + threadIdx.x) + blockDim.y*blockIdx.y + threadIdx.y;
BASE_TYPE sum = 0;
for (int k = 0; k < Acols; k++)
{
sum = +A[i0 + k] * A[i0+k];
}
int ind = Acols* (blockDim.y*blockIdx.y + threadIdx.y) + blockDim.x*blockIdx.x + threadIdx.x;
C[ind] = sum;
}
int main()
{
int Arows = 100;
int Acols = 200;
size_t Asize = Arows*Acols * sizeof(BASE_TYPE);
BASE_TYPE *h_A = (BASE_TYPE *)malloc(Asize);
BASE_TYPE *h_C = (BASE_TYPE *)malloc(Asize);
for (int i = 0; i < Arows*Acols; i++)
{
h_A[i] = rand() / (BASE_TYPE)RAND_MAX;
}
for (int i = 0; i < Arows*Acols; i++)
{
printf("h_A[%d]=%d ", i, h_A[i]);
}
BASE_TYPE *d_A = NULL;
cudaMalloc((void **)&d_A, Asize);
BASE_TYPE *d_C = NULL;
cudaMalloc((void **)&d_C, Asize);
cudaMemcpy(d_A, h_A, Asize, cudaMemcpyHostToDevice);
dim3 threadsPerBlock = dim3(BLOCK_SIZE, BLOCK_SIZE);
dim3 blocksPerGrid = dim3(Acols / BLOCK_SIZE, Arows / BLOCK_SIZE);
matrixMult <<<blocksPerGrid, threadsPerBlock >>> (d_A, d_C, Acols, Arows);
cudaMemcpy(h_C, d_C, Asize, cudaMemcpyDeviceToHost);
printf("Test Started\n");
bool t = false;
for (int i = 0; i < Arows; i++)
{
for (int j = 0; j < Arows; j++)
{
if (h_C[i*Arows + j] !=1)
{
t = true;
//fprintf(stderr, "Result verification failed at element [%d,%d]!\n", i, j);
//printf("sum=%f,h_C[i*Arows + j]=%f\n", 1, h_C[i*Arows + j]);
//exit(EXIT_FAILURE);
printf("Matrix A is not orthogonal\n");
}
if (t) break;
}
if (t) break;
}
printf("Test Passed\n");
cudaFree(d_A);
cudaFree(d_C);
free(h_A);
free(h_C);
getchar();
system("pause");
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <iostream>
using namespace std;
#define BLOCK_SIZE 16
#define BASE_TYPE double
__global__ void matrixMult(const BASE_TYPE *A, BASE_TYPE *C, int Acols, int Arows)
{
int i0 = Acols *(blockDim.y*blockIdx.y + threadIdx.y);
//int iAT = Arows*(blockDim.x*blockIdx.x + threadIdx.x) + blockDim.y*blockIdx.y + threadIdx.y;
BASE_TYPE sum = 0;
for (int k = 0; k < Acols; k++)
{
sum = +A[i0 + k] * A[i0+k];
}
int ind = Acols* (blockDim.y*blockIdx.y + threadIdx.y) + blockDim.x*blockIdx.x + threadIdx.x;
C[ind] = sum;
}
int main()
{
int Arows = 100;
int Acols = 200;
size_t Asize = Arows*Acols * sizeof(BASE_TYPE);
BASE_TYPE *h_A = (BASE_TYPE *)malloc(Asize);
BASE_TYPE *h_C = (BASE_TYPE *)malloc(Asize);
for (int i = 0; i < Arows*Acols; i++)
{
h_A[i] = rand() / (BASE_TYPE)RAND_MAX;
}
for (int i = 0; i < Arows*Acols; i++)
{
printf("h_A[%d]=%d ", i, h_A[i]);
}
BASE_TYPE *d_A = NULL;
hipMalloc((void **)&d_A, Asize);
BASE_TYPE *d_C = NULL;
hipMalloc((void **)&d_C, Asize);
hipMemcpy(d_A, h_A, Asize, hipMemcpyHostToDevice);
dim3 threadsPerBlock = dim3(BLOCK_SIZE, BLOCK_SIZE);
dim3 blocksPerGrid = dim3(Acols / BLOCK_SIZE, Arows / BLOCK_SIZE);
matrixMult <<<blocksPerGrid, threadsPerBlock >>> (d_A, d_C, Acols, Arows);
hipMemcpy(h_C, d_C, Asize, hipMemcpyDeviceToHost);
printf("Test Started\n");
bool t = false;
for (int i = 0; i < Arows; i++)
{
for (int j = 0; j < Arows; j++)
{
if (h_C[i*Arows + j] !=1)
{
t = true;
//fprintf(stderr, "Result verification failed at element [%d,%d]!\n", i, j);
//printf("sum=%f,h_C[i*Arows + j]=%f\n", 1, h_C[i*Arows + j]);
//exit(EXIT_FAILURE);
printf("Matrix A is not orthogonal\n");
}
if (t) break;
}
if (t) break;
}
printf("Test Passed\n");
hipFree(d_A);
hipFree(d_C);
free(h_A);
free(h_C);
getchar();
system("pause");
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <iostream>
using namespace std;
#define BLOCK_SIZE 16
#define BASE_TYPE double
__global__ void matrixMult(const BASE_TYPE *A, BASE_TYPE *C, int Acols, int Arows)
{
int i0 = Acols *(blockDim.y*blockIdx.y + threadIdx.y);
//int iAT = Arows*(blockDim.x*blockIdx.x + threadIdx.x) + blockDim.y*blockIdx.y + threadIdx.y;
BASE_TYPE sum = 0;
for (int k = 0; k < Acols; k++)
{
sum = +A[i0 + k] * A[i0+k];
}
int ind = Acols* (blockDim.y*blockIdx.y + threadIdx.y) + blockDim.x*blockIdx.x + threadIdx.x;
C[ind] = sum;
}
int main()
{
int Arows = 100;
int Acols = 200;
size_t Asize = Arows*Acols * sizeof(BASE_TYPE);
BASE_TYPE *h_A = (BASE_TYPE *)malloc(Asize);
BASE_TYPE *h_C = (BASE_TYPE *)malloc(Asize);
for (int i = 0; i < Arows*Acols; i++)
{
h_A[i] = rand() / (BASE_TYPE)RAND_MAX;
}
for (int i = 0; i < Arows*Acols; i++)
{
printf("h_A[%d]=%d ", i, h_A[i]);
}
BASE_TYPE *d_A = NULL;
hipMalloc((void **)&d_A, Asize);
BASE_TYPE *d_C = NULL;
hipMalloc((void **)&d_C, Asize);
hipMemcpy(d_A, h_A, Asize, hipMemcpyHostToDevice);
dim3 threadsPerBlock = dim3(BLOCK_SIZE, BLOCK_SIZE);
dim3 blocksPerGrid = dim3(Acols / BLOCK_SIZE, Arows / BLOCK_SIZE);
matrixMult <<<blocksPerGrid, threadsPerBlock >>> (d_A, d_C, Acols, Arows);
hipMemcpy(h_C, d_C, Asize, hipMemcpyDeviceToHost);
printf("Test Started\n");
bool t = false;
for (int i = 0; i < Arows; i++)
{
for (int j = 0; j < Arows; j++)
{
if (h_C[i*Arows + j] !=1)
{
t = true;
//fprintf(stderr, "Result verification failed at element [%d,%d]!\n", i, j);
//printf("sum=%f,h_C[i*Arows + j]=%f\n", 1, h_C[i*Arows + j]);
//exit(EXIT_FAILURE);
printf("Matrix A is not orthogonal\n");
}
if (t) break;
}
if (t) break;
}
printf("Test Passed\n");
hipFree(d_A);
hipFree(d_C);
free(h_A);
free(h_C);
getchar();
system("pause");
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10matrixMultPKdPdii
.globl _Z10matrixMultPKdPdii
.p2align 8
.type _Z10matrixMultPKdPdii,@function
_Z10matrixMultPKdPdii:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s5, 16
s_cmp_lt_i32 s4, 1
v_mad_u64_u32 v[2:3], null, s15, s5, v[1:2]
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v3, v2, s4
s_cbranch_scc1 .LBB0_2
s_load_b64 s[6:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v1, s4, -1, v3
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b64 v[1:2], v[1:2], off
s_waitcnt vmcnt(0)
v_mul_f64 v[1:2], v[1:2], v[1:2]
s_branch .LBB0_3
.LBB0_2:
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
.LBB0_3:
s_load_b32 s2, s[2:3], 0xc
s_load_b64 s[0:1], s[0:1], 0x8
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s14, s14, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add3_u32 v3, v3, v0, s14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 3, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_store_b64 v[3:4], v[1:2], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10matrixMultPKdPdii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10matrixMultPKdPdii, .Lfunc_end0-_Z10matrixMultPKdPdii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10matrixMultPKdPdii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10matrixMultPKdPdii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <iostream>
using namespace std;
#define BLOCK_SIZE 16
#define BASE_TYPE double
__global__ void matrixMult(const BASE_TYPE *A, BASE_TYPE *C, int Acols, int Arows)
{
int i0 = Acols *(blockDim.y*blockIdx.y + threadIdx.y);
//int iAT = Arows*(blockDim.x*blockIdx.x + threadIdx.x) + blockDim.y*blockIdx.y + threadIdx.y;
BASE_TYPE sum = 0;
for (int k = 0; k < Acols; k++)
{
sum = +A[i0 + k] * A[i0+k];
}
int ind = Acols* (blockDim.y*blockIdx.y + threadIdx.y) + blockDim.x*blockIdx.x + threadIdx.x;
C[ind] = sum;
}
int main()
{
int Arows = 100;
int Acols = 200;
size_t Asize = Arows*Acols * sizeof(BASE_TYPE);
BASE_TYPE *h_A = (BASE_TYPE *)malloc(Asize);
BASE_TYPE *h_C = (BASE_TYPE *)malloc(Asize);
for (int i = 0; i < Arows*Acols; i++)
{
h_A[i] = rand() / (BASE_TYPE)RAND_MAX;
}
for (int i = 0; i < Arows*Acols; i++)
{
printf("h_A[%d]=%d ", i, h_A[i]);
}
BASE_TYPE *d_A = NULL;
hipMalloc((void **)&d_A, Asize);
BASE_TYPE *d_C = NULL;
hipMalloc((void **)&d_C, Asize);
hipMemcpy(d_A, h_A, Asize, hipMemcpyHostToDevice);
dim3 threadsPerBlock = dim3(BLOCK_SIZE, BLOCK_SIZE);
dim3 blocksPerGrid = dim3(Acols / BLOCK_SIZE, Arows / BLOCK_SIZE);
matrixMult <<<blocksPerGrid, threadsPerBlock >>> (d_A, d_C, Acols, Arows);
hipMemcpy(h_C, d_C, Asize, hipMemcpyDeviceToHost);
printf("Test Started\n");
bool t = false;
for (int i = 0; i < Arows; i++)
{
for (int j = 0; j < Arows; j++)
{
if (h_C[i*Arows + j] !=1)
{
t = true;
//fprintf(stderr, "Result verification failed at element [%d,%d]!\n", i, j);
//printf("sum=%f,h_C[i*Arows + j]=%f\n", 1, h_C[i*Arows + j]);
//exit(EXIT_FAILURE);
printf("Matrix A is not orthogonal\n");
}
if (t) break;
}
if (t) break;
}
printf("Test Passed\n");
hipFree(d_A);
hipFree(d_C);
free(h_A);
free(h_C);
getchar();
system("pause");
} | .text
.file "kernel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z25__device_stub__matrixMultPKdPdii # -- Begin function _Z25__device_stub__matrixMultPKdPdii
.p2align 4, 0x90
.type _Z25__device_stub__matrixMultPKdPdii,@function
_Z25__device_stub__matrixMultPKdPdii: # @_Z25__device_stub__matrixMultPKdPdii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10matrixMultPKdPdii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__matrixMultPKdPdii, .Lfunc_end0-_Z25__device_stub__matrixMultPKdPdii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x41dfffffffc00000 # double 2147483647
.LCPI1_1:
.quad 0x3ff0000000000000 # double 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $160000, %edi # imm = 0x27100
callq malloc
movq %rax, %rbx
movl $160000, %edi # imm = 0x27100
callq malloc
movq %rax, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
movsd %xmm0, (%rbx,%r15,8)
incq %r15
cmpq $20000, %r15 # imm = 0x4E20
jne .LBB1_1
# %bb.2: # %.preheader57.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_3: # %.preheader57
# =>This Inner Loop Header: Depth=1
movsd (%rbx,%r15,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str, %edi
movl %r15d, %esi
movb $1, %al
callq printf
incq %r15
cmpq $20000, %r15 # imm = 0x4E20
jne .LBB1_3
# %bb.4:
movq $0, 16(%rsp)
leaq 16(%rsp), %rdi
movl $160000, %esi # imm = 0x27100
callq hipMalloc
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $160000, %esi # imm = 0x27100
callq hipMalloc
movq 16(%rsp), %rdi
movl $160000, %edx # imm = 0x27100
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $25769803788, %rdi # imm = 0x60000000C
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $200, 28(%rsp)
movl $100, 24(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10matrixMultPKdPdii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 8(%rsp), %rsi
movl $160000, %edx # imm = 0x27100
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
xorl %r15d, %r15d
movq %r14, %r12
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_8: # Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r12,%r13,8), %xmm0 # xmm0 = mem[0],zero
ucomisd .LCPI1_1(%rip), %xmm0
jne .LBB1_9
jnp .LBB1_10
.LBB1_9: # in Loop: Header=BB1_8 Depth=2
movl $.Lstr.1, %edi
callq puts@PLT
movb $1, %al
.LBB1_10: # in Loop: Header=BB1_8 Depth=2
testb $1, %al
jne .LBB1_12
# %bb.11: # in Loop: Header=BB1_8 Depth=2
leaq 1(%r13), %rcx
cmpq $99, %r13
movq %rcx, %r13
jb .LBB1_8
.LBB1_12: # in Loop: Header=BB1_7 Depth=1
testb $1, %al
jne .LBB1_14
# %bb.13: # in Loop: Header=BB1_7 Depth=1
incq %r15
addq $800, %r12 # imm = 0x320
cmpq $100, %r15
jne .LBB1_7
.LBB1_14:
movl $.Lstr.2, %edi
callq puts@PLT
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq stdin(%rip), %rdi
callq getc
movl $.L.str.4, %edi
callq system
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10matrixMultPKdPdii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10matrixMultPKdPdii,@object # @_Z10matrixMultPKdPdii
.section .rodata,"a",@progbits
.globl _Z10matrixMultPKdPdii
.p2align 3, 0x0
_Z10matrixMultPKdPdii:
.quad _Z25__device_stub__matrixMultPKdPdii
.size _Z10matrixMultPKdPdii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "h_A[%d]=%d "
.size .L.str, 12
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "pause"
.size .L.str.4, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10matrixMultPKdPdii"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Test Started"
.size .Lstr, 13
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Matrix A is not orthogonal"
.size .Lstr.1, 27
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Test Passed"
.size .Lstr.2, 12
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__matrixMultPKdPdii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10matrixMultPKdPdii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10matrixMultPKdPdii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fe2000001ff00 */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e240000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x001fd800078e0205 */
/*0080*/ @!P0 BRA 0x310 ; /* 0x0000028000008947 */
/* 0x000fea0003800000 */
/*0090*/ IADD3 R2, R4, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x000fe20007ffe0ff */
/*00a0*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fc600078e00ff */
/*00b0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*00c0*/ LOP3.LUT R2, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304027812 */
/* 0x000fd600078ec0ff */
/*00d0*/ @!P0 BRA 0x250 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*00e0*/ IADD3 R3, -R2, c[0x0][0x170], RZ ; /* 0x00005c0002037a10 */
/* 0x000fe20007ffe1ff */
/*00f0*/ IMAD.MOV.U32 R5, RZ, RZ, -0x1 ; /* 0xffffffffff057424 */
/* 0x000fc600078e00ff */
/*0100*/ ISETP.GT.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f04270 */
/*0110*/ @!P0 BRA 0x200 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0120*/ ISETP.GT.AND P1, PT, R3, 0xc, PT ; /* 0x0000000c0300780c */
/* 0x000fe40003f24270 */
/*0130*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0140*/ @!P1 BRA 0x1a0 ; /* 0x0000005000009947 */
/* 0x000fea0003800000 */
/*0150*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0160*/ IADD3 R3, R3, -0x10, RZ ; /* 0xfffffff003037810 */
/* 0x000fe40007ffe0ff */
/*0170*/ IADD3 R5, R5, 0x10, RZ ; /* 0x0000001005057810 */
/* 0x000fe40007ffe0ff */
/*0180*/ ISETP.GT.AND P1, PT, R3, 0xc, PT ; /* 0x0000000c0300780c */
/* 0x000fda0003f24270 */
/*0190*/ @P1 BRA 0x160 ; /* 0xffffffc000001947 */
/* 0x000fea000383ffff */
/*01a0*/ ISETP.GT.AND P1, PT, R3, 0x4, PT ; /* 0x000000040300780c */
/* 0x000fda0003f24270 */
/*01b0*/ @P1 PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000181c */
/* 0x000fe40003f0e170 */
/*01c0*/ @P1 IADD3 R3, R3, -0x8, RZ ; /* 0xfffffff803031810 */
/* 0x000fe40007ffe0ff */
/*01d0*/ @P1 IADD3 R5, R5, 0x8, RZ ; /* 0x0000000805051810 */
/* 0x000fd20007ffe0ff */
/*01e0*/ ISETP.NE.OR P0, PT, R3, RZ, P0 ; /* 0x000000ff0300720c */
/* 0x000fda0000705670 */
/*01f0*/ @!P0 BRA 0x240 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0200*/ IADD3 R3, R3, -0x4, RZ ; /* 0xfffffffc03037810 */
/* 0x000fe40007ffe0ff */
/*0210*/ IADD3 R5, R5, 0x4, RZ ; /* 0x0000000405057810 */
/* 0x000fe40007ffe0ff */
/*0220*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*0230*/ @P0 BRA 0x200 ; /* 0xffffffc000000947 */
/* 0x000fea000383ffff */
/*0240*/ IADD3 R3, R5, 0x1, RZ ; /* 0x0000000105037810 */
/* 0x000fe40007ffe0ff */
/*0250*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*0260*/ IMAD.MOV.U32 R4, RZ, RZ, 0x8 ; /* 0x00000008ff047424 */
/* 0x000fd800078e00ff */
/*0270*/ @!P0 BRA 0x2d0 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0280*/ IADD3 R5, R3, -0x1, RZ ; /* 0xffffffff03057810 */
/* 0x000fe40007ffe0ff */
/*0290*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*02a0*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fe40007ffe0ff */
/*02b0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*02c0*/ @P0 BRA 0x290 ; /* 0xffffffc000000947 */
/* 0x000fea000383ffff */
/*02d0*/ IMAD R5, R0, c[0x0][0x170], R5 ; /* 0x00005c0000057a24 */
/* 0x000fc800078e0205 */
/*02e0*/ IMAD.WIDE R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fcc00078e0204 */
/*02f0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1b00 */
/*0300*/ DMUL R2, R4, R4 ; /* 0x0000000404027228 */
/* 0x0040480000000000 */
/*0310*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x001e280000002500 */
/*0320*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e240000002100 */
/*0330*/ IMAD R5, R5, c[0x0][0x0], R4 ; /* 0x0000000005057a24 */
/* 0x001fe400078e0204 */
/*0340*/ IMAD.MOV.U32 R4, RZ, RZ, 0x8 ; /* 0x00000008ff047424 */
/* 0x000fc400078e00ff */
/*0350*/ IMAD R5, R0, c[0x0][0x170], R5 ; /* 0x00005c0000057a24 */
/* 0x000fc800078e0205 */
/*0360*/ IMAD.WIDE R4, R5, R4, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e0204 */
/*0370*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x002fe2000c101b04 */
/*0380*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0390*/ BRA 0x390; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10matrixMultPKdPdii
.globl _Z10matrixMultPKdPdii
.p2align 8
.type _Z10matrixMultPKdPdii,@function
_Z10matrixMultPKdPdii:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s5, 16
s_cmp_lt_i32 s4, 1
v_mad_u64_u32 v[2:3], null, s15, s5, v[1:2]
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v3, v2, s4
s_cbranch_scc1 .LBB0_2
s_load_b64 s[6:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v1, s4, -1, v3
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b64 v[1:2], v[1:2], off
s_waitcnt vmcnt(0)
v_mul_f64 v[1:2], v[1:2], v[1:2]
s_branch .LBB0_3
.LBB0_2:
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
.LBB0_3:
s_load_b32 s2, s[2:3], 0xc
s_load_b64 s[0:1], s[0:1], 0x8
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s14, s14, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add3_u32 v3, v3, v0, s14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 3, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_store_b64 v[3:4], v[1:2], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10matrixMultPKdPdii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10matrixMultPKdPdii, .Lfunc_end0-_Z10matrixMultPKdPdii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10matrixMultPKdPdii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10matrixMultPKdPdii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e4aa7_00000000-6_kernel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10matrixMultPKdPdiiPKdPdii
.type _Z35__device_stub__Z10matrixMultPKdPdiiPKdPdii, @function
_Z35__device_stub__Z10matrixMultPKdPdiiPKdPdii:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10matrixMultPKdPdii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z35__device_stub__Z10matrixMultPKdPdiiPKdPdii, .-_Z35__device_stub__Z10matrixMultPKdPdiiPKdPdii
.globl _Z10matrixMultPKdPdii
.type _Z10matrixMultPKdPdii, @function
_Z10matrixMultPKdPdii:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10matrixMultPKdPdiiPKdPdii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z10matrixMultPKdPdii, .-_Z10matrixMultPKdPdii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "h_A[%d]=%d "
.LC2:
.string "Test Started\n"
.LC4:
.string "Matrix A is not orthogonal\n"
.LC5:
.string "Test Passed\n"
.LC6:
.string "pause"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $160000, %edi
call malloc@PLT
movq %rax, %rbp
movl $160000, %edi
call malloc@PLT
movq %rax, %r12
movq %rbp, %rbx
leaq 160000(%rbp), %r13
.L12:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC0(%rip), %xmm0
movsd %xmm0, (%rbx)
addq $8, %rbx
cmpq %r13, %rbx
jne .L12
movl $0, %ebx
leaq .LC1(%rip), %r13
.L13:
movsd 0(%rbp,%rbx,8), %xmm0
movl %ebx, %edx
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $20000, %rbx
jne .L13
movq $0, (%rsp)
movq %rsp, %rdi
movl $160000, %esi
call cudaMalloc@PLT
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $160000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $160000, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 16(%rsp)
movl $16, 20(%rsp)
movl $12, 28(%rsp)
movl $6, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L14:
movl $2, %ecx
movl $160000, %edx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 800(%r12), %rdx
leaq 80800(%r12), %rcx
movsd .LC3(%rip), %xmm0
movapd %xmm0, %xmm1
jmp .L15
.L26:
movl $100, %ecx
movl $200, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z35__device_stub__Z10matrixMultPKdPdiiPKdPdii
jmp .L14
.L21:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L18:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq stdin(%rip), %rdi
call getc@PLT
leaq .LC6(%rip), %rdi
call system@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L27
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
addq $800, %rdx
cmpq %rcx, %rdx
je .L18
.L15:
leaq -800(%rdx), %rax
.L19:
ucomisd (%rax), %xmm0
jp .L21
ucomisd (%rax), %xmm1
jne .L21
addq $8, %rax
cmpq %rdx, %rax
jne .L19
jmp .L28
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z10matrixMultPKdPdii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z10matrixMultPKdPdii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -4194304
.long 1105199103
.align 8
.LC3:
.long 0
.long 1072693248
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z25__device_stub__matrixMultPKdPdii # -- Begin function _Z25__device_stub__matrixMultPKdPdii
.p2align 4, 0x90
.type _Z25__device_stub__matrixMultPKdPdii,@function
_Z25__device_stub__matrixMultPKdPdii: # @_Z25__device_stub__matrixMultPKdPdii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10matrixMultPKdPdii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__matrixMultPKdPdii, .Lfunc_end0-_Z25__device_stub__matrixMultPKdPdii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x41dfffffffc00000 # double 2147483647
.LCPI1_1:
.quad 0x3ff0000000000000 # double 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $160000, %edi # imm = 0x27100
callq malloc
movq %rax, %rbx
movl $160000, %edi # imm = 0x27100
callq malloc
movq %rax, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
movsd %xmm0, (%rbx,%r15,8)
incq %r15
cmpq $20000, %r15 # imm = 0x4E20
jne .LBB1_1
# %bb.2: # %.preheader57.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_3: # %.preheader57
# =>This Inner Loop Header: Depth=1
movsd (%rbx,%r15,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str, %edi
movl %r15d, %esi
movb $1, %al
callq printf
incq %r15
cmpq $20000, %r15 # imm = 0x4E20
jne .LBB1_3
# %bb.4:
movq $0, 16(%rsp)
leaq 16(%rsp), %rdi
movl $160000, %esi # imm = 0x27100
callq hipMalloc
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $160000, %esi # imm = 0x27100
callq hipMalloc
movq 16(%rsp), %rdi
movl $160000, %edx # imm = 0x27100
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $25769803788, %rdi # imm = 0x60000000C
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $200, 28(%rsp)
movl $100, 24(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10matrixMultPKdPdii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 8(%rsp), %rsi
movl $160000, %edx # imm = 0x27100
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
xorl %r15d, %r15d
movq %r14, %r12
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_8: # Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r12,%r13,8), %xmm0 # xmm0 = mem[0],zero
ucomisd .LCPI1_1(%rip), %xmm0
jne .LBB1_9
jnp .LBB1_10
.LBB1_9: # in Loop: Header=BB1_8 Depth=2
movl $.Lstr.1, %edi
callq puts@PLT
movb $1, %al
.LBB1_10: # in Loop: Header=BB1_8 Depth=2
testb $1, %al
jne .LBB1_12
# %bb.11: # in Loop: Header=BB1_8 Depth=2
leaq 1(%r13), %rcx
cmpq $99, %r13
movq %rcx, %r13
jb .LBB1_8
.LBB1_12: # in Loop: Header=BB1_7 Depth=1
testb $1, %al
jne .LBB1_14
# %bb.13: # in Loop: Header=BB1_7 Depth=1
incq %r15
addq $800, %r12 # imm = 0x320
cmpq $100, %r15
jne .LBB1_7
.LBB1_14:
movl $.Lstr.2, %edi
callq puts@PLT
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq stdin(%rip), %rdi
callq getc
movl $.L.str.4, %edi
callq system
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10matrixMultPKdPdii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10matrixMultPKdPdii,@object # @_Z10matrixMultPKdPdii
.section .rodata,"a",@progbits
.globl _Z10matrixMultPKdPdii
.p2align 3, 0x0
_Z10matrixMultPKdPdii:
.quad _Z25__device_stub__matrixMultPKdPdii
.size _Z10matrixMultPKdPdii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "h_A[%d]=%d "
.size .L.str, 12
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "pause"
.size .L.str.4, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10matrixMultPKdPdii"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Test Started"
.size .Lstr, 13
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Matrix A is not orthogonal"
.size .Lstr.1, 27
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Test Passed"
.size .Lstr.2, 12
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__matrixMultPKdPdii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10matrixMultPKdPdii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<cuda_runtime.h>
// Kernel definition
__global__ void MatAdd(float A, float B, float C)
{
int i = threadIdx.x;
int j = threadIdx.y;
C= A + B;
} | code for sm_80
Function : _Z6MatAddfff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<cuda_runtime.h>
// Kernel definition
__global__ void MatAdd(float A, float B, float C)
{
int i = threadIdx.x;
int j = threadIdx.y;
C= A + B;
} | .file "tmpxft_0015c7fb_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z6MatAddffffff
.type _Z26__device_stub__Z6MatAddffffff, @function
_Z26__device_stub__Z6MatAddffffff:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm2, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6MatAddfff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z6MatAddffffff, .-_Z26__device_stub__Z6MatAddffffff
.globl _Z6MatAddfff
.type _Z6MatAddfff, @function
_Z6MatAddfff:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6MatAddffffff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6MatAddfff, .-_Z6MatAddfff
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6MatAddfff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6MatAddfff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<cuda_runtime.h>
// Kernel definition
__global__ void MatAdd(float A, float B, float C)
{
int i = threadIdx.x;
int j = threadIdx.y;
C= A + B;
} | #include<hip/hip_runtime.h>
// Kernel definition
__global__ void MatAdd(float A, float B, float C)
{
int i = threadIdx.x;
int j = threadIdx.y;
C= A + B;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include<hip/hip_runtime.h>
// Kernel definition
__global__ void MatAdd(float A, float B, float C)
{
int i = threadIdx.x;
int j = threadIdx.y;
C= A + B;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6MatAddfff
.globl _Z6MatAddfff
.p2align 8
.type _Z6MatAddfff,@function
_Z6MatAddfff:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6MatAddfff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6MatAddfff, .Lfunc_end0-_Z6MatAddfff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6MatAddfff
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z6MatAddfff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<hip/hip_runtime.h>
// Kernel definition
__global__ void MatAdd(float A, float B, float C)
{
int i = threadIdx.x;
int j = threadIdx.y;
C= A + B;
} | .text
.file "test.hip"
.globl _Z21__device_stub__MatAddfff # -- Begin function _Z21__device_stub__MatAddfff
.p2align 4, 0x90
.type _Z21__device_stub__MatAddfff,@function
_Z21__device_stub__MatAddfff: # @_Z21__device_stub__MatAddfff
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm2, 4(%rsp)
leaq 12(%rsp), %rax
movq %rax, 64(%rsp)
leaq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6MatAddfff, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__MatAddfff, .Lfunc_end0-_Z21__device_stub__MatAddfff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6MatAddfff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6MatAddfff,@object # @_Z6MatAddfff
.section .rodata,"a",@progbits
.globl _Z6MatAddfff
.p2align 3, 0x0
_Z6MatAddfff:
.quad _Z21__device_stub__MatAddfff
.size _Z6MatAddfff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6MatAddfff"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__MatAddfff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6MatAddfff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6MatAddfff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6MatAddfff
.globl _Z6MatAddfff
.p2align 8
.type _Z6MatAddfff,@function
_Z6MatAddfff:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6MatAddfff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6MatAddfff, .Lfunc_end0-_Z6MatAddfff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6MatAddfff
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z6MatAddfff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0015c7fb_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z6MatAddffffff
.type _Z26__device_stub__Z6MatAddffffff, @function
_Z26__device_stub__Z6MatAddffffff:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm2, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6MatAddfff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z6MatAddffffff, .-_Z26__device_stub__Z6MatAddffffff
.globl _Z6MatAddfff
.type _Z6MatAddfff, @function
_Z6MatAddfff:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6MatAddffffff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6MatAddfff, .-_Z6MatAddfff
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6MatAddfff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6MatAddfff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
.globl _Z21__device_stub__MatAddfff # -- Begin function _Z21__device_stub__MatAddfff
.p2align 4, 0x90
.type _Z21__device_stub__MatAddfff,@function
_Z21__device_stub__MatAddfff: # @_Z21__device_stub__MatAddfff
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm2, 4(%rsp)
leaq 12(%rsp), %rax
movq %rax, 64(%rsp)
leaq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6MatAddfff, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__MatAddfff, .Lfunc_end0-_Z21__device_stub__MatAddfff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6MatAddfff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6MatAddfff,@object # @_Z6MatAddfff
.section .rodata,"a",@progbits
.globl _Z6MatAddfff
.p2align 3, 0x0
_Z6MatAddfff:
.quad _Z21__device_stub__MatAddfff
.size _Z6MatAddfff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6MatAddfff"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__MatAddfff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6MatAddfff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void decrement_dynamic_kernel(int* pInts, size_t numInts)
{
size_t idx = blockDim.x * blockIdx.x + threadIdx.x;
if (idx > numInts)
return;
pInts[idx] -= 1;
} | code for sm_80
Function : _Z24decrement_dynamic_kernelPim
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fc80003f04070 */
/*0050*/ ISETP.GT.U32.AND.EX P0, PT, RZ, c[0x0][0x16c], PT, P0 ; /* 0x00005b00ff007a0c */
/* 0x000fda0003f04100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ LEA R2, P0, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000027a11 */
/* 0x000fe200078010ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0090*/ LEA.HI.X R3, R0, c[0x0][0x164], RZ, 0x2, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f14ff */
/*00a0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00b0*/ IADD3 R5, R0, -0x1, RZ ; /* 0xffffffff00057810 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void decrement_dynamic_kernel(int* pInts, size_t numInts)
{
size_t idx = blockDim.x * blockIdx.x + threadIdx.x;
if (idx > numInts)
return;
pInts[idx] -= 1;
} | .file "tmpxft_000d5e96_00000000-6_decrement_dynamic_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z24decrement_dynamic_kernelPimPim
.type _Z45__device_stub__Z24decrement_dynamic_kernelPimPim, @function
_Z45__device_stub__Z24decrement_dynamic_kernelPimPim:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z24decrement_dynamic_kernelPim(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z24decrement_dynamic_kernelPimPim, .-_Z45__device_stub__Z24decrement_dynamic_kernelPimPim
.globl _Z24decrement_dynamic_kernelPim
.type _Z24decrement_dynamic_kernelPim, @function
_Z24decrement_dynamic_kernelPim:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z24decrement_dynamic_kernelPimPim
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z24decrement_dynamic_kernelPim, .-_Z24decrement_dynamic_kernelPim
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24decrement_dynamic_kernelPim"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24decrement_dynamic_kernelPim(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void decrement_dynamic_kernel(int* pInts, size_t numInts)
{
size_t idx = blockDim.x * blockIdx.x + threadIdx.x;
if (idx > numInts)
return;
pInts[idx] -= 1;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void decrement_dynamic_kernel(int* pInts, size_t numInts)
{
size_t idx = blockDim.x * blockIdx.x + threadIdx.x;
if (idx > numInts)
return;
pInts[idx] -= 1;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void decrement_dynamic_kernel(int* pInts, size_t numInts)
{
size_t idx = blockDim.x * blockIdx.x + threadIdx.x;
if (idx > numInts)
return;
pInts[idx] -= 1;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24decrement_dynamic_kernelPim
.globl _Z24decrement_dynamic_kernelPim
.p2align 8
.type _Z24decrement_dynamic_kernelPim,@function
_Z24decrement_dynamic_kernelPim:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
v_cmp_ge_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, -1, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24decrement_dynamic_kernelPim
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24decrement_dynamic_kernelPim, .Lfunc_end0-_Z24decrement_dynamic_kernelPim
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24decrement_dynamic_kernelPim
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z24decrement_dynamic_kernelPim.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void decrement_dynamic_kernel(int* pInts, size_t numInts)
{
size_t idx = blockDim.x * blockIdx.x + threadIdx.x;
if (idx > numInts)
return;
pInts[idx] -= 1;
} | .text
.file "decrement_dynamic_kernel.hip"
.globl _Z39__device_stub__decrement_dynamic_kernelPim # -- Begin function _Z39__device_stub__decrement_dynamic_kernelPim
.p2align 4, 0x90
.type _Z39__device_stub__decrement_dynamic_kernelPim,@function
_Z39__device_stub__decrement_dynamic_kernelPim: # @_Z39__device_stub__decrement_dynamic_kernelPim
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z24decrement_dynamic_kernelPim, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z39__device_stub__decrement_dynamic_kernelPim, .Lfunc_end0-_Z39__device_stub__decrement_dynamic_kernelPim
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24decrement_dynamic_kernelPim, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24decrement_dynamic_kernelPim,@object # @_Z24decrement_dynamic_kernelPim
.section .rodata,"a",@progbits
.globl _Z24decrement_dynamic_kernelPim
.p2align 3, 0x0
_Z24decrement_dynamic_kernelPim:
.quad _Z39__device_stub__decrement_dynamic_kernelPim
.size _Z24decrement_dynamic_kernelPim, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24decrement_dynamic_kernelPim"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__decrement_dynamic_kernelPim
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24decrement_dynamic_kernelPim
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z24decrement_dynamic_kernelPim
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fc80003f04070 */
/*0050*/ ISETP.GT.U32.AND.EX P0, PT, RZ, c[0x0][0x16c], PT, P0 ; /* 0x00005b00ff007a0c */
/* 0x000fda0003f04100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ LEA R2, P0, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000027a11 */
/* 0x000fe200078010ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0090*/ LEA.HI.X R3, R0, c[0x0][0x164], RZ, 0x2, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f14ff */
/*00a0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00b0*/ IADD3 R5, R0, -0x1, RZ ; /* 0xffffffff00057810 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24decrement_dynamic_kernelPim
.globl _Z24decrement_dynamic_kernelPim
.p2align 8
.type _Z24decrement_dynamic_kernelPim,@function
_Z24decrement_dynamic_kernelPim:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
v_cmp_ge_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, -1, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24decrement_dynamic_kernelPim
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24decrement_dynamic_kernelPim, .Lfunc_end0-_Z24decrement_dynamic_kernelPim
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24decrement_dynamic_kernelPim
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z24decrement_dynamic_kernelPim.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d5e96_00000000-6_decrement_dynamic_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z24decrement_dynamic_kernelPimPim
.type _Z45__device_stub__Z24decrement_dynamic_kernelPimPim, @function
_Z45__device_stub__Z24decrement_dynamic_kernelPimPim:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z24decrement_dynamic_kernelPim(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z24decrement_dynamic_kernelPimPim, .-_Z45__device_stub__Z24decrement_dynamic_kernelPimPim
.globl _Z24decrement_dynamic_kernelPim
.type _Z24decrement_dynamic_kernelPim, @function
_Z24decrement_dynamic_kernelPim:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z24decrement_dynamic_kernelPimPim
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z24decrement_dynamic_kernelPim, .-_Z24decrement_dynamic_kernelPim
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24decrement_dynamic_kernelPim"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24decrement_dynamic_kernelPim(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "decrement_dynamic_kernel.hip"
.globl _Z39__device_stub__decrement_dynamic_kernelPim # -- Begin function _Z39__device_stub__decrement_dynamic_kernelPim
.p2align 4, 0x90
.type _Z39__device_stub__decrement_dynamic_kernelPim,@function
_Z39__device_stub__decrement_dynamic_kernelPim: # @_Z39__device_stub__decrement_dynamic_kernelPim
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z24decrement_dynamic_kernelPim, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z39__device_stub__decrement_dynamic_kernelPim, .Lfunc_end0-_Z39__device_stub__decrement_dynamic_kernelPim
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24decrement_dynamic_kernelPim, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24decrement_dynamic_kernelPim,@object # @_Z24decrement_dynamic_kernelPim
.section .rodata,"a",@progbits
.globl _Z24decrement_dynamic_kernelPim
.p2align 3, 0x0
_Z24decrement_dynamic_kernelPim:
.quad _Z39__device_stub__decrement_dynamic_kernelPim
.size _Z24decrement_dynamic_kernelPim, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24decrement_dynamic_kernelPim"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__decrement_dynamic_kernelPim
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24decrement_dynamic_kernelPim
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void Saxy_device(float* x, float* y, float* d, float xb, float yb, int n)
{
int i = threadIdx.x;
if (i < n)
d[i] = (x[i] - xb) * (y[i] - yb);
} | code for sm_80
Function : _Z11Saxy_devicePfS_S_ffi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x180], PT ; /* 0x0000600006007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00b0*/ FADD R0, R2, -c[0x0][0x178] ; /* 0x80005e0002007621 */
/* 0x004fe40000000000 */
/*00c0*/ FADD R9, R4, -c[0x0][0x17c] ; /* 0x80005f0004097621 */
/* 0x008fc80000000000 */
/*00d0*/ FMUL R9, R0, R9 ; /* 0x0000000900097220 */
/* 0x000fca0000400000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void Saxy_device(float* x, float* y, float* d, float xb, float yb, int n)
{
int i = threadIdx.x;
if (i < n)
d[i] = (x[i] - xb) * (y[i] - yb);
} | .file "tmpxft_000ff4e5_00000000-6_Saxy_device.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z11Saxy_devicePfS_S_ffiPfS_S_ffi
.type _Z38__device_stub__Z11Saxy_devicePfS_S_ffiPfS_S_ffi, @function
_Z38__device_stub__Z11Saxy_devicePfS_S_ffiPfS_S_ffi:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11Saxy_devicePfS_S_ffi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z11Saxy_devicePfS_S_ffiPfS_S_ffi, .-_Z38__device_stub__Z11Saxy_devicePfS_S_ffiPfS_S_ffi
.globl _Z11Saxy_devicePfS_S_ffi
.type _Z11Saxy_devicePfS_S_ffi, @function
_Z11Saxy_devicePfS_S_ffi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z11Saxy_devicePfS_S_ffiPfS_S_ffi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11Saxy_devicePfS_S_ffi, .-_Z11Saxy_devicePfS_S_ffi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11Saxy_devicePfS_S_ffi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11Saxy_devicePfS_S_ffi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void Saxy_device(float* x, float* y, float* d, float xb, float yb, int n)
{
int i = threadIdx.x;
if (i < n)
d[i] = (x[i] - xb) * (y[i] - yb);
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Saxy_device(float* x, float* y, float* d, float xb, float yb, int n)
{
int i = threadIdx.x;
if (i < n)
d[i] = (x[i] - xb) * (y[i] - yb);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Saxy_device(float* x, float* y, float* d, float xb, float yb, int n)
{
int i = threadIdx.x;
if (i < n)
d[i] = (x[i] - xb) * (y[i] - yb);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11Saxy_devicePfS_S_ffi
.globl _Z11Saxy_devicePfS_S_ffi
.p2align 8
.type _Z11Saxy_devicePfS_S_ffi,@function
_Z11Saxy_devicePfS_S_ffi:
s_load_b32 s2, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b256 s[0:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[0:1]
global_load_b32 v2, v0, s[2:3]
s_waitcnt vmcnt(0)
v_dual_subrev_f32 v1, s6, v1 :: v_dual_subrev_f32 v2, s7, v2
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[4:5]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11Saxy_devicePfS_S_ffi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11Saxy_devicePfS_S_ffi, .Lfunc_end0-_Z11Saxy_devicePfS_S_ffi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11Saxy_devicePfS_S_ffi
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z11Saxy_devicePfS_S_ffi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Saxy_device(float* x, float* y, float* d, float xb, float yb, int n)
{
int i = threadIdx.x;
if (i < n)
d[i] = (x[i] - xb) * (y[i] - yb);
} | .text
.file "Saxy_device.hip"
.globl _Z26__device_stub__Saxy_devicePfS_S_ffi # -- Begin function _Z26__device_stub__Saxy_devicePfS_S_ffi
.p2align 4, 0x90
.type _Z26__device_stub__Saxy_devicePfS_S_ffi,@function
_Z26__device_stub__Saxy_devicePfS_S_ffi: # @_Z26__device_stub__Saxy_devicePfS_S_ffi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11Saxy_devicePfS_S_ffi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z26__device_stub__Saxy_devicePfS_S_ffi, .Lfunc_end0-_Z26__device_stub__Saxy_devicePfS_S_ffi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11Saxy_devicePfS_S_ffi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11Saxy_devicePfS_S_ffi,@object # @_Z11Saxy_devicePfS_S_ffi
.section .rodata,"a",@progbits
.globl _Z11Saxy_devicePfS_S_ffi
.p2align 3, 0x0
_Z11Saxy_devicePfS_S_ffi:
.quad _Z26__device_stub__Saxy_devicePfS_S_ffi
.size _Z11Saxy_devicePfS_S_ffi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11Saxy_devicePfS_S_ffi"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__Saxy_devicePfS_S_ffi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11Saxy_devicePfS_S_ffi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11Saxy_devicePfS_S_ffi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x180], PT ; /* 0x0000600006007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00b0*/ FADD R0, R2, -c[0x0][0x178] ; /* 0x80005e0002007621 */
/* 0x004fe40000000000 */
/*00c0*/ FADD R9, R4, -c[0x0][0x17c] ; /* 0x80005f0004097621 */
/* 0x008fc80000000000 */
/*00d0*/ FMUL R9, R0, R9 ; /* 0x0000000900097220 */
/* 0x000fca0000400000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11Saxy_devicePfS_S_ffi
.globl _Z11Saxy_devicePfS_S_ffi
.p2align 8
.type _Z11Saxy_devicePfS_S_ffi,@function
_Z11Saxy_devicePfS_S_ffi:
s_load_b32 s2, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b256 s[0:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[0:1]
global_load_b32 v2, v0, s[2:3]
s_waitcnt vmcnt(0)
v_dual_subrev_f32 v1, s6, v1 :: v_dual_subrev_f32 v2, s7, v2
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[4:5]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11Saxy_devicePfS_S_ffi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11Saxy_devicePfS_S_ffi, .Lfunc_end0-_Z11Saxy_devicePfS_S_ffi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11Saxy_devicePfS_S_ffi
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z11Saxy_devicePfS_S_ffi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ff4e5_00000000-6_Saxy_device.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z11Saxy_devicePfS_S_ffiPfS_S_ffi
.type _Z38__device_stub__Z11Saxy_devicePfS_S_ffiPfS_S_ffi, @function
_Z38__device_stub__Z11Saxy_devicePfS_S_ffiPfS_S_ffi:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11Saxy_devicePfS_S_ffi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z11Saxy_devicePfS_S_ffiPfS_S_ffi, .-_Z38__device_stub__Z11Saxy_devicePfS_S_ffiPfS_S_ffi
.globl _Z11Saxy_devicePfS_S_ffi
.type _Z11Saxy_devicePfS_S_ffi, @function
_Z11Saxy_devicePfS_S_ffi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z11Saxy_devicePfS_S_ffiPfS_S_ffi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11Saxy_devicePfS_S_ffi, .-_Z11Saxy_devicePfS_S_ffi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11Saxy_devicePfS_S_ffi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11Saxy_devicePfS_S_ffi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Saxy_device.hip"
.globl _Z26__device_stub__Saxy_devicePfS_S_ffi # -- Begin function _Z26__device_stub__Saxy_devicePfS_S_ffi
.p2align 4, 0x90
.type _Z26__device_stub__Saxy_devicePfS_S_ffi,@function
_Z26__device_stub__Saxy_devicePfS_S_ffi: # @_Z26__device_stub__Saxy_devicePfS_S_ffi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11Saxy_devicePfS_S_ffi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z26__device_stub__Saxy_devicePfS_S_ffi, .Lfunc_end0-_Z26__device_stub__Saxy_devicePfS_S_ffi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11Saxy_devicePfS_S_ffi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11Saxy_devicePfS_S_ffi,@object # @_Z11Saxy_devicePfS_S_ffi
.section .rodata,"a",@progbits
.globl _Z11Saxy_devicePfS_S_ffi
.p2align 3, 0x0
_Z11Saxy_devicePfS_S_ffi:
.quad _Z26__device_stub__Saxy_devicePfS_S_ffi
.size _Z11Saxy_devicePfS_S_ffi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11Saxy_devicePfS_S_ffi"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__Saxy_devicePfS_S_ffi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11Saxy_devicePfS_S_ffi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Matrix Multiplication
#include <stdio.h>
#include <stdlib.h>
__global__ void matrixMul(int* m, int* n,int* p,int size)
{
//Calculate ow and Column
int row = blockIdx.y * blockDim.y + threadIdx.y;
int column = blockIdx.x * blockDim.x + threadIdx.x;
int p_sum = 0;
for(int i=0;i<size;i++)
{
p_sum += m[row * size + i] * n[i * size + column];
}
p[row * size + column] = p_sum;
}
int main()
{
int n = 1<<10; //1024 or 2^10
//Host matrix m,n,p
int* h_m;
int* h_n;
int* h_p;
//Device matrix m,n,p
int* d_m;
int* d_n;
int* d_p;
size_t bytes = n * n * sizeof(int);
//Allocating memory on Host side
h_m = (int*)malloc(bytes);
h_n = (int*)malloc(bytes);
h_p = (int*)malloc(bytes);
//Initialize matrix m,n,p
for(int i=0;i<n;i++)
{
for(int j=0;j<n;j++)
{
h_m[i*n+j]=rand()%1024;
h_n[i*n+j]=rand()%1024;
}
}
//Allocating memory on Device side
cudaMalloc(&d_m, bytes);
cudaMalloc(&d_n, bytes);
cudaMalloc(&d_p, bytes);
//Copy data from Host to the Device
cudaMemcpy(d_m, h_m, bytes, cudaMemcpyHostToDevice);
cudaMemcpy(d_n, h_n, bytes, cudaMemcpyHostToDevice);
int threads_per_block = 16;
dim3 block_size(threads_per_block, threads_per_block);
dim3 grid_size(n / block_size.x, n / block_size.y);
matrixMul <<< grid_size, block_size >>>(d_m,d_n,d_p,n);
cudaMemcpy(h_p, d_p, bytes, cudaMemcpyDeviceToHost);
printf("Completed Successfully!\n");
//Clean-Up
free(h_m);
free(h_n);
free(h_p);
cudaFree(d_m);
cudaFree(d_n);
cudaFree(d_p);
return 0;
} | code for sm_80
Function : _Z9matrixMulPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e220000002600 */
/*0020*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0080*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R4, R4, c[0x0][0x4], R3 ; /* 0x0000010004047a24 */
/* 0x001fc800078e0203 */
/*00a0*/ IMAD R4, R4, c[0x0][0x178], RZ ; /* 0x00005e0004047a24 */
/* 0x000fe400078e02ff */
/*00b0*/ IMAD R2, R2, c[0x0][0x0], R5 ; /* 0x0000000002027a24 */
/* 0x002fe200078e0205 */
/*00c0*/ @!P0 BRA 0xbe0 ; /* 0x00000b1000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R3, R0.reuse, -0x1, RZ ; /* 0xffffffff00037810 */
/* 0x040fe40007ffe0ff */
/*00e0*/ LOP3.LUT R5, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300057812 */
/* 0x000fe400078ec0ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*0100*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fd20000000f00 */
/*0120*/ @!P0 BRA 0xac0 ; /* 0x0000099000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0140*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0150*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0160*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fe40000000f00 */
/*0170*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fcc0003f04270 */
/*0180*/ IMAD.WIDE R24, R2, R25, c[0x0][0x168] ; /* 0x00005a0002187625 */
/* 0x000fce00078e0219 */
/*0190*/ @!P0 BRA 0x930 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01a0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01c0*/ @!P1 BRA 0x670 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01e0*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*01f0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0200*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0210*/ IMAD.WIDE R12, R4, 0x4, R12 ; /* 0x00000004040c7825 */
/* 0x000fca00078e020c */
/*0220*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0230*/ IMAD.WIDE R10, R0, 0x4, R24 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0218 */
/*0240*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0250*/ IMAD.WIDE R18, R0.reuse, 0x4, R10 ; /* 0x0000000400127825 */
/* 0x040fe200078e020a */
/*0260*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*0270*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*0280*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0212 */
/*0290*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02a0*/ IMAD.WIDE R20, R0.reuse, 0x4, R14 ; /* 0x0000000400147825 */
/* 0x040fe200078e020e */
/*02b0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*02c0*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*02d0*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*02e0*/ IMAD.WIDE R14, R0, 0x4, R20 ; /* 0x00000004000e7825 */
/* 0x001fc600078e0214 */
/*02f0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0300*/ IMAD.WIDE R22, R0.reuse, 0x4, R14 ; /* 0x0000000400167825 */
/* 0x040fe200078e020e */
/*0310*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0320*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0330*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x000fc600078e0216 */
/*0340*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0350*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*0360*/ IMAD R29, R29, R27, R28 ; /* 0x0000001b1d1d7224 */
/* 0x004fc600078e021c */
/*0370*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*0380*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*0390*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0218 */
/*03a0*/ IMAD R29, R16, R17, R29 ; /* 0x00000011101d7224 */
/* 0x008fe400078e021d */
/*03b0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fe400078e020e */
/*03c0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*03d0*/ IMAD R29, R18, R19, R29 ; /* 0x00000013121d7224 */
/* 0x010fe400078e021d */
/*03e0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fe400078e0210 */
/*03f0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0400*/ IMAD R26, R26, R7, R29 ; /* 0x000000071a1a7224 */
/* 0x000fc400078e021d */
/*0410*/ IMAD.WIDE R22, R0.reuse, 0x4, R18 ; /* 0x0000000400167825 */
/* 0x042fe200078e0212 */
/*0420*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0430*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0440*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x001fc600078e0216 */
/*0450*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*0460*/ IMAD R9, R20, R9, R26 ; /* 0x0000000914097224 */
/* 0x020fc600078e021a */
/*0470*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*0480*/ IMAD R11, R8, R11, R9 ; /* 0x0000000b080b7224 */
/* 0x000fe400078e0209 */
/*0490*/ IMAD.WIDE R8, R0, 0x4, R24 ; /* 0x0000000400087825 */
/* 0x000fe200078e0218 */
/*04a0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04b0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*04c0*/ IMAD R21, R10, R21, R11 ; /* 0x000000150a157224 */
/* 0x000fc600078e020b */
/*04d0*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*04e0*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0208 */
/*04f0*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0500*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0510*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0520*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0530*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0540*/ IMAD R9, R28, R27, R21 ; /* 0x0000001b1c097224 */
/* 0x004fc600078e0215 */
/*0550*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0560*/ IMAD.WIDE R20, R0, 0x4, R10 ; /* 0x0000000400147825 */
/* 0x000fca00078e020a */
/*0570*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*0580*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*0590*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05a0*/ IMAD R7, R14, R7, R9 ; /* 0x000000070e077224 */
/* 0x000fc800078e0209 */
/*05b0*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x000fc800078e0207 */
/*05c0*/ IMAD R7, R18, R26, R7 ; /* 0x0000001a12077224 */
/* 0x020fc800078e0207 */
/*05d0*/ IMAD R7, R22, R17, R7 ; /* 0x0000001116077224 */
/* 0x010fe200078e0207 */
/*05e0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*05f0*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fc60007ffe0ff */
/*0600*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0610*/ IMAD R7, R15, R24, R7 ; /* 0x000000180f077224 */
/* 0x008fc800078e0207 */
/*0620*/ IMAD R28, R19, R28, R7 ; /* 0x0000001c131c7224 */
/* 0x004fc800078e0207 */
/*0630*/ IMAD R28, R23, R25, R28 ; /* 0x00000019171c7224 */
/* 0x000fe400078e021c */
/*0640*/ IMAD.WIDE R24, R0, 0x4, R20 ; /* 0x0000000400187825 */
/* 0x000fc800078e0214 */
/*0650*/ IMAD R28, R27, R8, R28 ; /* 0x000000081b1c7224 */
/* 0x000fe200078e021c */
/*0660*/ @P1 BRA 0x1e0 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*0670*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0680*/ @!P1 BRA 0x910 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*0690*/ IMAD.WIDE R16, R0, 0x4, R24 ; /* 0x0000000400107825 */
/* 0x000fe200078e0218 */
/*06a0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06b0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*06c0*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*06d0*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fe200078e0210 */
/*06e0*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*06f0*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fe200078e0208 */
/*0700*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0710*/ IMAD.WIDE R14, R0.reuse, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x040fe200078e020c */
/*0720*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0730*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0740*/ IMAD.WIDE R10, R0, 0x4, R14 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020e */
/*0750*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*0760*/ IMAD.WIDE R16, R0.reuse, 0x4, R10 ; /* 0x0000000400107825 */
/* 0x042fe200078e020a */
/*0770*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*0780*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*0790*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*07a0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07b0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*07c0*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x010fc600078e0212 */
/*07d0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*07e0*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*07f0*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0800*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0810*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0830*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0840*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0850*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe40007ffe0ff */
/*0860*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0870*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0880*/ IMAD R7, R7, R20, R28 ; /* 0x0000001407077224 */
/* 0x004fc800078e021c */
/*0890*/ IMAD R7, R21, R22, R7 ; /* 0x0000001615077224 */
/* 0x008fc800078e0207 */
/*08a0*/ IMAD R7, R23, R26, R7 ; /* 0x0000001a17077224 */
/* 0x020fc800078e0207 */
/*08b0*/ IMAD R7, R14, R27, R7 ; /* 0x0000001b0e077224 */
/* 0x000fc800078e0207 */
/*08c0*/ IMAD R7, R10, R25, R7 ; /* 0x000000190a077224 */
/* 0x000fc800078e0207 */
/*08d0*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x010fc800078e0207 */
/*08e0*/ IMAD R7, R24, R11, R7 ; /* 0x0000000b18077224 */
/* 0x000fe400078e0207 */
/*08f0*/ IMAD.WIDE R24, R0, 0x4, R12 ; /* 0x0000000400187825 */
/* 0x000fc800078e020c */
/*0900*/ IMAD R28, R15, R18, R7 ; /* 0x000000120f1c7224 */
/* 0x000fe400078e0207 */
/*0910*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0920*/ @!P0 BRA 0xac0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0930*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0940*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */
/* 0x000fe200078e0218 */
/*0950*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0960*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*0970*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fc800078e0208 */
/*0980*/ IMAD.WIDE R12, R0.reuse, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x040fe200078e020e */
/*0990*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09b0*/ IMAD.WIDE R10, R0, 0x4, R12 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020c */
/*09c0*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*09d0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*09e0*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*09f0*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a00*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a10*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a20*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a30*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a40*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fc60007ffe0ff */
/*0a50*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a60*/ IMAD R7, R25, R7, R28 ; /* 0x0000000719077224 */
/* 0x004fc800078e021c */
/*0a70*/ IMAD R7, R14, R16, R7 ; /* 0x000000100e077224 */
/* 0x008fe400078e0207 */
/*0a80*/ IMAD.WIDE R24, R0, 0x4, R10 ; /* 0x0000000400187825 */
/* 0x000fc800078e020a */
/*0a90*/ IMAD R7, R18, R17, R7 ; /* 0x0000001112077224 */
/* 0x010fc800078e0207 */
/*0aa0*/ IMAD R28, R20, R19, R7 ; /* 0x00000013141c7224 */
/* 0x020fe200078e0207 */
/*0ab0*/ @P0 BRA 0x930 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0ac0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0ad0*/ @!P0 BRA 0xbe0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0ae0*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0af0*/ IADD3 R6, R4, R3, RZ ; /* 0x0000000304067210 */
/* 0x000fe20007ffe0ff */
/*0b00*/ IMAD R3, R3, c[0x0][0x178], R2 ; /* 0x00005e0003037a24 */
/* 0x000fd000078e0202 */
/*0b10*/ IMAD.WIDE R6, R6, R8, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0208 */
/*0b20*/ IMAD.WIDE R8, R3, R8, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fe200078e0208 */
/*0b30*/ MOV R10, R6 ; /* 0x00000006000a7202 */
/* 0x000fc80000000f00 */
/*0b40*/ MOV R6, R10 ; /* 0x0000000a00067202 */
/* 0x000fe20000000f00 */
/*0b50*/ LDG.E R3, [R8.64] ; /* 0x0000000408037981 */
/* 0x0000aa000c1e1900 */
/*0b60*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x0002a2000c1e1900 */
/*0b70*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*0b80*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fc40007f3e0ff */
/*0b90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0ba0*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fe200078e0208 */
/*0bb0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x002fc60000ffe4ff */
/*0bc0*/ IMAD R28, R3, R6, R28 ; /* 0x00000006031c7224 */
/* 0x004fd000078e021c */
/*0bd0*/ @P0 BRA 0xb40 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0be0*/ IADD3 R2, R2, R4, RZ ; /* 0x0000000402027210 */
/* 0x000fe40007ffe0ff */
/*0bf0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0c00*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0c10*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c20*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c30*/ BRA 0xc30; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Matrix Multiplication
#include <stdio.h>
#include <stdlib.h>
__global__ void matrixMul(int* m, int* n,int* p,int size)
{
//Calculate ow and Column
int row = blockIdx.y * blockDim.y + threadIdx.y;
int column = blockIdx.x * blockDim.x + threadIdx.x;
int p_sum = 0;
for(int i=0;i<size;i++)
{
p_sum += m[row * size + i] * n[i * size + column];
}
p[row * size + column] = p_sum;
}
int main()
{
int n = 1<<10; //1024 or 2^10
//Host matrix m,n,p
int* h_m;
int* h_n;
int* h_p;
//Device matrix m,n,p
int* d_m;
int* d_n;
int* d_p;
size_t bytes = n * n * sizeof(int);
//Allocating memory on Host side
h_m = (int*)malloc(bytes);
h_n = (int*)malloc(bytes);
h_p = (int*)malloc(bytes);
//Initialize matrix m,n,p
for(int i=0;i<n;i++)
{
for(int j=0;j<n;j++)
{
h_m[i*n+j]=rand()%1024;
h_n[i*n+j]=rand()%1024;
}
}
//Allocating memory on Device side
cudaMalloc(&d_m, bytes);
cudaMalloc(&d_n, bytes);
cudaMalloc(&d_p, bytes);
//Copy data from Host to the Device
cudaMemcpy(d_m, h_m, bytes, cudaMemcpyHostToDevice);
cudaMemcpy(d_n, h_n, bytes, cudaMemcpyHostToDevice);
int threads_per_block = 16;
dim3 block_size(threads_per_block, threads_per_block);
dim3 grid_size(n / block_size.x, n / block_size.y);
matrixMul <<< grid_size, block_size >>>(d_m,d_n,d_p,n);
cudaMemcpy(h_p, d_p, bytes, cudaMemcpyDeviceToHost);
printf("Completed Successfully!\n");
//Clean-Up
free(h_m);
free(h_n);
free(h_p);
cudaFree(d_m);
cudaFree(d_n);
cudaFree(d_p);
return 0;
} | .file "tmpxft_000eb8f7_00000000-6_vector_multiplication.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9matrixMulPiS_S_iPiS_S_i
.type _Z33__device_stub__Z9matrixMulPiS_S_iPiS_S_i, @function
_Z33__device_stub__Z9matrixMulPiS_S_iPiS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9matrixMulPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z33__device_stub__Z9matrixMulPiS_S_iPiS_S_i, .-_Z33__device_stub__Z9matrixMulPiS_S_iPiS_S_i
.globl _Z9matrixMulPiS_S_i
.type _Z9matrixMulPiS_S_i, @function
_Z9matrixMulPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9matrixMulPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9matrixMulPiS_S_i, .-_Z9matrixMulPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Completed Successfully!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %r14
movl $4194304, %edi
call malloc@PLT
movq %rax, %r15
movl $4194304, %edi
call malloc@PLT
movq %rax, 8(%rsp)
movq %r14, %rbp
movq %r15, %r12
leaq 4194304(%r14), %r13
.L12:
movl $0, %ebx
.L13:
call rand@PLT
cltd
shrl $22, %edx
addl %edx, %eax
andl $1023, %eax
subl %edx, %eax
movl %eax, 0(%rbp,%rbx)
call rand@PLT
cltd
shrl $22, %edx
addl %edx, %eax
andl $1023, %eax
subl %edx, %eax
movl %eax, (%r12,%rbx)
addq $4, %rbx
cmpq $4096, %rbx
jne .L13
addq $4096, %rbp
addq $4096, %r12
cmpq %r13, %rbp
jne .L12
leaq 24(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4194304, %edx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movq %r15, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $64, 60(%rsp)
movl $64, 64(%rsp)
movl $16, 48(%rsp)
movl $16, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movl $2, %ecx
movl $4194304, %edx
movq 40(%rsp), %rsi
movq 8(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r14, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $1024, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z33__device_stub__Z9matrixMulPiS_S_iPiS_S_i
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z9matrixMulPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9matrixMulPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Matrix Multiplication
#include <stdio.h>
#include <stdlib.h>
__global__ void matrixMul(int* m, int* n,int* p,int size)
{
//Calculate ow and Column
int row = blockIdx.y * blockDim.y + threadIdx.y;
int column = blockIdx.x * blockDim.x + threadIdx.x;
int p_sum = 0;
for(int i=0;i<size;i++)
{
p_sum += m[row * size + i] * n[i * size + column];
}
p[row * size + column] = p_sum;
}
int main()
{
int n = 1<<10; //1024 or 2^10
//Host matrix m,n,p
int* h_m;
int* h_n;
int* h_p;
//Device matrix m,n,p
int* d_m;
int* d_n;
int* d_p;
size_t bytes = n * n * sizeof(int);
//Allocating memory on Host side
h_m = (int*)malloc(bytes);
h_n = (int*)malloc(bytes);
h_p = (int*)malloc(bytes);
//Initialize matrix m,n,p
for(int i=0;i<n;i++)
{
for(int j=0;j<n;j++)
{
h_m[i*n+j]=rand()%1024;
h_n[i*n+j]=rand()%1024;
}
}
//Allocating memory on Device side
cudaMalloc(&d_m, bytes);
cudaMalloc(&d_n, bytes);
cudaMalloc(&d_p, bytes);
//Copy data from Host to the Device
cudaMemcpy(d_m, h_m, bytes, cudaMemcpyHostToDevice);
cudaMemcpy(d_n, h_n, bytes, cudaMemcpyHostToDevice);
int threads_per_block = 16;
dim3 block_size(threads_per_block, threads_per_block);
dim3 grid_size(n / block_size.x, n / block_size.y);
matrixMul <<< grid_size, block_size >>>(d_m,d_n,d_p,n);
cudaMemcpy(h_p, d_p, bytes, cudaMemcpyDeviceToHost);
printf("Completed Successfully!\n");
//Clean-Up
free(h_m);
free(h_n);
free(h_p);
cudaFree(d_m);
cudaFree(d_n);
cudaFree(d_p);
return 0;
} | // Matrix Multiplication
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void matrixMul(int* m, int* n,int* p,int size)
{
//Calculate ow and Column
int row = blockIdx.y * blockDim.y + threadIdx.y;
int column = blockIdx.x * blockDim.x + threadIdx.x;
int p_sum = 0;
for(int i=0;i<size;i++)
{
p_sum += m[row * size + i] * n[i * size + column];
}
p[row * size + column] = p_sum;
}
int main()
{
int n = 1<<10; //1024 or 2^10
//Host matrix m,n,p
int* h_m;
int* h_n;
int* h_p;
//Device matrix m,n,p
int* d_m;
int* d_n;
int* d_p;
size_t bytes = n * n * sizeof(int);
//Allocating memory on Host side
h_m = (int*)malloc(bytes);
h_n = (int*)malloc(bytes);
h_p = (int*)malloc(bytes);
//Initialize matrix m,n,p
for(int i=0;i<n;i++)
{
for(int j=0;j<n;j++)
{
h_m[i*n+j]=rand()%1024;
h_n[i*n+j]=rand()%1024;
}
}
//Allocating memory on Device side
hipMalloc(&d_m, bytes);
hipMalloc(&d_n, bytes);
hipMalloc(&d_p, bytes);
//Copy data from Host to the Device
hipMemcpy(d_m, h_m, bytes, hipMemcpyHostToDevice);
hipMemcpy(d_n, h_n, bytes, hipMemcpyHostToDevice);
int threads_per_block = 16;
dim3 block_size(threads_per_block, threads_per_block);
dim3 grid_size(n / block_size.x, n / block_size.y);
matrixMul <<< grid_size, block_size >>>(d_m,d_n,d_p,n);
hipMemcpy(h_p, d_p, bytes, hipMemcpyDeviceToHost);
printf("Completed Successfully!\n");
//Clean-Up
free(h_m);
free(h_n);
free(h_p);
hipFree(d_m);
hipFree(d_n);
hipFree(d_p);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Matrix Multiplication
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void matrixMul(int* m, int* n,int* p,int size)
{
//Calculate ow and Column
int row = blockIdx.y * blockDim.y + threadIdx.y;
int column = blockIdx.x * blockDim.x + threadIdx.x;
int p_sum = 0;
for(int i=0;i<size;i++)
{
p_sum += m[row * size + i] * n[i * size + column];
}
p[row * size + column] = p_sum;
}
int main()
{
int n = 1<<10; //1024 or 2^10
//Host matrix m,n,p
int* h_m;
int* h_n;
int* h_p;
//Device matrix m,n,p
int* d_m;
int* d_n;
int* d_p;
size_t bytes = n * n * sizeof(int);
//Allocating memory on Host side
h_m = (int*)malloc(bytes);
h_n = (int*)malloc(bytes);
h_p = (int*)malloc(bytes);
//Initialize matrix m,n,p
for(int i=0;i<n;i++)
{
for(int j=0;j<n;j++)
{
h_m[i*n+j]=rand()%1024;
h_n[i*n+j]=rand()%1024;
}
}
//Allocating memory on Device side
hipMalloc(&d_m, bytes);
hipMalloc(&d_n, bytes);
hipMalloc(&d_p, bytes);
//Copy data from Host to the Device
hipMemcpy(d_m, h_m, bytes, hipMemcpyHostToDevice);
hipMemcpy(d_n, h_n, bytes, hipMemcpyHostToDevice);
int threads_per_block = 16;
dim3 block_size(threads_per_block, threads_per_block);
dim3 grid_size(n / block_size.x, n / block_size.y);
matrixMul <<< grid_size, block_size >>>(d_m,d_n,d_p,n);
hipMemcpy(h_p, d_p, bytes, hipMemcpyDeviceToHost);
printf("Completed Successfully!\n");
//Clean-Up
free(h_m);
free(h_n);
free(h_p);
hipFree(d_m);
hipFree(d_n);
hipFree(d_p);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9matrixMulPiS_S_i
.globl _Z9matrixMulPiS_S_i
.p2align 8
.type _Z9matrixMulPiS_S_i,@function
_Z9matrixMulPiS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v0, s2
s_mov_b32 s3, s2
v_mov_b32_e32 v5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v6, 31, v5
s_add_i32 s3, s3, -1
s_cmp_eq_u32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_load_b32 v8, v[3:4], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[6:7], null, v9, v8, v[2:3]
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v2, v6 :: v_dual_add_nc_u32 v5, s2, v5
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v2, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9matrixMulPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9matrixMulPiS_S_i, .Lfunc_end0-_Z9matrixMulPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9matrixMulPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9matrixMulPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Matrix Multiplication
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void matrixMul(int* m, int* n,int* p,int size)
{
//Calculate ow and Column
int row = blockIdx.y * blockDim.y + threadIdx.y;
int column = blockIdx.x * blockDim.x + threadIdx.x;
int p_sum = 0;
for(int i=0;i<size;i++)
{
p_sum += m[row * size + i] * n[i * size + column];
}
p[row * size + column] = p_sum;
}
int main()
{
int n = 1<<10; //1024 or 2^10
//Host matrix m,n,p
int* h_m;
int* h_n;
int* h_p;
//Device matrix m,n,p
int* d_m;
int* d_n;
int* d_p;
size_t bytes = n * n * sizeof(int);
//Allocating memory on Host side
h_m = (int*)malloc(bytes);
h_n = (int*)malloc(bytes);
h_p = (int*)malloc(bytes);
//Initialize matrix m,n,p
for(int i=0;i<n;i++)
{
for(int j=0;j<n;j++)
{
h_m[i*n+j]=rand()%1024;
h_n[i*n+j]=rand()%1024;
}
}
//Allocating memory on Device side
hipMalloc(&d_m, bytes);
hipMalloc(&d_n, bytes);
hipMalloc(&d_p, bytes);
//Copy data from Host to the Device
hipMemcpy(d_m, h_m, bytes, hipMemcpyHostToDevice);
hipMemcpy(d_n, h_n, bytes, hipMemcpyHostToDevice);
int threads_per_block = 16;
dim3 block_size(threads_per_block, threads_per_block);
dim3 grid_size(n / block_size.x, n / block_size.y);
matrixMul <<< grid_size, block_size >>>(d_m,d_n,d_p,n);
hipMemcpy(h_p, d_p, bytes, hipMemcpyDeviceToHost);
printf("Completed Successfully!\n");
//Clean-Up
free(h_m);
free(h_n);
free(h_p);
hipFree(d_m);
hipFree(d_n);
hipFree(d_p);
return 0;
} | .text
.file "vector_multiplication.hip"
.globl _Z24__device_stub__matrixMulPiS_S_i # -- Begin function _Z24__device_stub__matrixMulPiS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__matrixMulPiS_S_i,@function
_Z24__device_stub__matrixMulPiS_S_i: # @_Z24__device_stub__matrixMulPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9matrixMulPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__matrixMulPiS_S_i, .Lfunc_end0-_Z24__device_stub__matrixMulPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, 32(%rsp) # 8-byte Spill
xorl %r12d, %r12d
movq %rbx, %r13
movq %r14, %rbp
.p2align 4, 0x90
.LBB1_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
# kill: def $eax killed $eax def $rax
leal 1023(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
andl $-1024, %ecx # imm = 0xFC00
subl %ecx, %eax
movl %eax, (%r13,%r15,4)
callq rand
# kill: def $eax killed $eax def $rax
leal 1023(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
andl $-1024, %ecx # imm = 0xFC00
subl %ecx, %eax
movl %eax, (%rbp,%r15,4)
incq %r15
cmpq $1024, %r15 # imm = 0x400
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %r12
addq $4096, %rbp # imm = 0x1000
addq $4096, %r13 # imm = 0x1000
cmpq $1024, %r12 # imm = 0x400
jne .LBB1_1
# %bb.4:
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movq %rsp, %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movq 16(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $274877907008, %rdi # imm = 0x4000000040
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $1024, 28(%rsp) # imm = 0x400
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9matrixMulPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq (%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq 32(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9matrixMulPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9matrixMulPiS_S_i,@object # @_Z9matrixMulPiS_S_i
.section .rodata,"a",@progbits
.globl _Z9matrixMulPiS_S_i
.p2align 3, 0x0
_Z9matrixMulPiS_S_i:
.quad _Z24__device_stub__matrixMulPiS_S_i
.size _Z9matrixMulPiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9matrixMulPiS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Completed Successfully!"
.size .Lstr, 24
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__matrixMulPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9matrixMulPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9matrixMulPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e220000002600 */
/*0020*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0080*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R4, R4, c[0x0][0x4], R3 ; /* 0x0000010004047a24 */
/* 0x001fc800078e0203 */
/*00a0*/ IMAD R4, R4, c[0x0][0x178], RZ ; /* 0x00005e0004047a24 */
/* 0x000fe400078e02ff */
/*00b0*/ IMAD R2, R2, c[0x0][0x0], R5 ; /* 0x0000000002027a24 */
/* 0x002fe200078e0205 */
/*00c0*/ @!P0 BRA 0xbe0 ; /* 0x00000b1000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R3, R0.reuse, -0x1, RZ ; /* 0xffffffff00037810 */
/* 0x040fe40007ffe0ff */
/*00e0*/ LOP3.LUT R5, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300057812 */
/* 0x000fe400078ec0ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*0100*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fd20000000f00 */
/*0120*/ @!P0 BRA 0xac0 ; /* 0x0000099000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0140*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0150*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0160*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fe40000000f00 */
/*0170*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fcc0003f04270 */
/*0180*/ IMAD.WIDE R24, R2, R25, c[0x0][0x168] ; /* 0x00005a0002187625 */
/* 0x000fce00078e0219 */
/*0190*/ @!P0 BRA 0x930 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01a0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01c0*/ @!P1 BRA 0x670 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01e0*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*01f0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0200*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0210*/ IMAD.WIDE R12, R4, 0x4, R12 ; /* 0x00000004040c7825 */
/* 0x000fca00078e020c */
/*0220*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0230*/ IMAD.WIDE R10, R0, 0x4, R24 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0218 */
/*0240*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0250*/ IMAD.WIDE R18, R0.reuse, 0x4, R10 ; /* 0x0000000400127825 */
/* 0x040fe200078e020a */
/*0260*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*0270*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*0280*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0212 */
/*0290*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02a0*/ IMAD.WIDE R20, R0.reuse, 0x4, R14 ; /* 0x0000000400147825 */
/* 0x040fe200078e020e */
/*02b0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*02c0*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*02d0*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*02e0*/ IMAD.WIDE R14, R0, 0x4, R20 ; /* 0x00000004000e7825 */
/* 0x001fc600078e0214 */
/*02f0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0300*/ IMAD.WIDE R22, R0.reuse, 0x4, R14 ; /* 0x0000000400167825 */
/* 0x040fe200078e020e */
/*0310*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0320*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0330*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x000fc600078e0216 */
/*0340*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0350*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*0360*/ IMAD R29, R29, R27, R28 ; /* 0x0000001b1d1d7224 */
/* 0x004fc600078e021c */
/*0370*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*0380*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*0390*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0218 */
/*03a0*/ IMAD R29, R16, R17, R29 ; /* 0x00000011101d7224 */
/* 0x008fe400078e021d */
/*03b0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fe400078e020e */
/*03c0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*03d0*/ IMAD R29, R18, R19, R29 ; /* 0x00000013121d7224 */
/* 0x010fe400078e021d */
/*03e0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fe400078e0210 */
/*03f0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0400*/ IMAD R26, R26, R7, R29 ; /* 0x000000071a1a7224 */
/* 0x000fc400078e021d */
/*0410*/ IMAD.WIDE R22, R0.reuse, 0x4, R18 ; /* 0x0000000400167825 */
/* 0x042fe200078e0212 */
/*0420*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0430*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0440*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x001fc600078e0216 */
/*0450*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*0460*/ IMAD R9, R20, R9, R26 ; /* 0x0000000914097224 */
/* 0x020fc600078e021a */
/*0470*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*0480*/ IMAD R11, R8, R11, R9 ; /* 0x0000000b080b7224 */
/* 0x000fe400078e0209 */
/*0490*/ IMAD.WIDE R8, R0, 0x4, R24 ; /* 0x0000000400087825 */
/* 0x000fe200078e0218 */
/*04a0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04b0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*04c0*/ IMAD R21, R10, R21, R11 ; /* 0x000000150a157224 */
/* 0x000fc600078e020b */
/*04d0*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*04e0*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0208 */
/*04f0*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0500*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0510*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0520*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0530*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0540*/ IMAD R9, R28, R27, R21 ; /* 0x0000001b1c097224 */
/* 0x004fc600078e0215 */
/*0550*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0560*/ IMAD.WIDE R20, R0, 0x4, R10 ; /* 0x0000000400147825 */
/* 0x000fca00078e020a */
/*0570*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*0580*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*0590*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05a0*/ IMAD R7, R14, R7, R9 ; /* 0x000000070e077224 */
/* 0x000fc800078e0209 */
/*05b0*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x000fc800078e0207 */
/*05c0*/ IMAD R7, R18, R26, R7 ; /* 0x0000001a12077224 */
/* 0x020fc800078e0207 */
/*05d0*/ IMAD R7, R22, R17, R7 ; /* 0x0000001116077224 */
/* 0x010fe200078e0207 */
/*05e0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*05f0*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fc60007ffe0ff */
/*0600*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0610*/ IMAD R7, R15, R24, R7 ; /* 0x000000180f077224 */
/* 0x008fc800078e0207 */
/*0620*/ IMAD R28, R19, R28, R7 ; /* 0x0000001c131c7224 */
/* 0x004fc800078e0207 */
/*0630*/ IMAD R28, R23, R25, R28 ; /* 0x00000019171c7224 */
/* 0x000fe400078e021c */
/*0640*/ IMAD.WIDE R24, R0, 0x4, R20 ; /* 0x0000000400187825 */
/* 0x000fc800078e0214 */
/*0650*/ IMAD R28, R27, R8, R28 ; /* 0x000000081b1c7224 */
/* 0x000fe200078e021c */
/*0660*/ @P1 BRA 0x1e0 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*0670*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0680*/ @!P1 BRA 0x910 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*0690*/ IMAD.WIDE R16, R0, 0x4, R24 ; /* 0x0000000400107825 */
/* 0x000fe200078e0218 */
/*06a0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06b0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*06c0*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*06d0*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fe200078e0210 */
/*06e0*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*06f0*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fe200078e0208 */
/*0700*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0710*/ IMAD.WIDE R14, R0.reuse, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x040fe200078e020c */
/*0720*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0730*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0740*/ IMAD.WIDE R10, R0, 0x4, R14 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020e */
/*0750*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*0760*/ IMAD.WIDE R16, R0.reuse, 0x4, R10 ; /* 0x0000000400107825 */
/* 0x042fe200078e020a */
/*0770*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*0780*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*0790*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*07a0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07b0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*07c0*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x010fc600078e0212 */
/*07d0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*07e0*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*07f0*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0800*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0810*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0830*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0840*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0850*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe40007ffe0ff */
/*0860*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0870*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0880*/ IMAD R7, R7, R20, R28 ; /* 0x0000001407077224 */
/* 0x004fc800078e021c */
/*0890*/ IMAD R7, R21, R22, R7 ; /* 0x0000001615077224 */
/* 0x008fc800078e0207 */
/*08a0*/ IMAD R7, R23, R26, R7 ; /* 0x0000001a17077224 */
/* 0x020fc800078e0207 */
/*08b0*/ IMAD R7, R14, R27, R7 ; /* 0x0000001b0e077224 */
/* 0x000fc800078e0207 */
/*08c0*/ IMAD R7, R10, R25, R7 ; /* 0x000000190a077224 */
/* 0x000fc800078e0207 */
/*08d0*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x010fc800078e0207 */
/*08e0*/ IMAD R7, R24, R11, R7 ; /* 0x0000000b18077224 */
/* 0x000fe400078e0207 */
/*08f0*/ IMAD.WIDE R24, R0, 0x4, R12 ; /* 0x0000000400187825 */
/* 0x000fc800078e020c */
/*0900*/ IMAD R28, R15, R18, R7 ; /* 0x000000120f1c7224 */
/* 0x000fe400078e0207 */
/*0910*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0920*/ @!P0 BRA 0xac0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0930*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0940*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */
/* 0x000fe200078e0218 */
/*0950*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0960*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*0970*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fc800078e0208 */
/*0980*/ IMAD.WIDE R12, R0.reuse, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x040fe200078e020e */
/*0990*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09b0*/ IMAD.WIDE R10, R0, 0x4, R12 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020c */
/*09c0*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*09d0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*09e0*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*09f0*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a00*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a10*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a20*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a30*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a40*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fc60007ffe0ff */
/*0a50*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a60*/ IMAD R7, R25, R7, R28 ; /* 0x0000000719077224 */
/* 0x004fc800078e021c */
/*0a70*/ IMAD R7, R14, R16, R7 ; /* 0x000000100e077224 */
/* 0x008fe400078e0207 */
/*0a80*/ IMAD.WIDE R24, R0, 0x4, R10 ; /* 0x0000000400187825 */
/* 0x000fc800078e020a */
/*0a90*/ IMAD R7, R18, R17, R7 ; /* 0x0000001112077224 */
/* 0x010fc800078e0207 */
/*0aa0*/ IMAD R28, R20, R19, R7 ; /* 0x00000013141c7224 */
/* 0x020fe200078e0207 */
/*0ab0*/ @P0 BRA 0x930 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0ac0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0ad0*/ @!P0 BRA 0xbe0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0ae0*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0af0*/ IADD3 R6, R4, R3, RZ ; /* 0x0000000304067210 */
/* 0x000fe20007ffe0ff */
/*0b00*/ IMAD R3, R3, c[0x0][0x178], R2 ; /* 0x00005e0003037a24 */
/* 0x000fd000078e0202 */
/*0b10*/ IMAD.WIDE R6, R6, R8, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0208 */
/*0b20*/ IMAD.WIDE R8, R3, R8, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fe200078e0208 */
/*0b30*/ MOV R10, R6 ; /* 0x00000006000a7202 */
/* 0x000fc80000000f00 */
/*0b40*/ MOV R6, R10 ; /* 0x0000000a00067202 */
/* 0x000fe20000000f00 */
/*0b50*/ LDG.E R3, [R8.64] ; /* 0x0000000408037981 */
/* 0x0000aa000c1e1900 */
/*0b60*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x0002a2000c1e1900 */
/*0b70*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*0b80*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fc40007f3e0ff */
/*0b90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0ba0*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fe200078e0208 */
/*0bb0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x002fc60000ffe4ff */
/*0bc0*/ IMAD R28, R3, R6, R28 ; /* 0x00000006031c7224 */
/* 0x004fd000078e021c */
/*0bd0*/ @P0 BRA 0xb40 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0be0*/ IADD3 R2, R2, R4, RZ ; /* 0x0000000402027210 */
/* 0x000fe40007ffe0ff */
/*0bf0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0c00*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0c10*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c20*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c30*/ BRA 0xc30; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9matrixMulPiS_S_i
.globl _Z9matrixMulPiS_S_i
.p2align 8
.type _Z9matrixMulPiS_S_i,@function
_Z9matrixMulPiS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v0, s2
s_mov_b32 s3, s2
v_mov_b32_e32 v5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v6, 31, v5
s_add_i32 s3, s3, -1
s_cmp_eq_u32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_load_b32 v8, v[3:4], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[6:7], null, v9, v8, v[2:3]
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v2, v6 :: v_dual_add_nc_u32 v5, s2, v5
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v2, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9matrixMulPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9matrixMulPiS_S_i, .Lfunc_end0-_Z9matrixMulPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9matrixMulPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9matrixMulPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000eb8f7_00000000-6_vector_multiplication.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9matrixMulPiS_S_iPiS_S_i
.type _Z33__device_stub__Z9matrixMulPiS_S_iPiS_S_i, @function
_Z33__device_stub__Z9matrixMulPiS_S_iPiS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9matrixMulPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z33__device_stub__Z9matrixMulPiS_S_iPiS_S_i, .-_Z33__device_stub__Z9matrixMulPiS_S_iPiS_S_i
.globl _Z9matrixMulPiS_S_i
.type _Z9matrixMulPiS_S_i, @function
_Z9matrixMulPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9matrixMulPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9matrixMulPiS_S_i, .-_Z9matrixMulPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Completed Successfully!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %r14
movl $4194304, %edi
call malloc@PLT
movq %rax, %r15
movl $4194304, %edi
call malloc@PLT
movq %rax, 8(%rsp)
movq %r14, %rbp
movq %r15, %r12
leaq 4194304(%r14), %r13
.L12:
movl $0, %ebx
.L13:
call rand@PLT
cltd
shrl $22, %edx
addl %edx, %eax
andl $1023, %eax
subl %edx, %eax
movl %eax, 0(%rbp,%rbx)
call rand@PLT
cltd
shrl $22, %edx
addl %edx, %eax
andl $1023, %eax
subl %edx, %eax
movl %eax, (%r12,%rbx)
addq $4, %rbx
cmpq $4096, %rbx
jne .L13
addq $4096, %rbp
addq $4096, %r12
cmpq %r13, %rbp
jne .L12
leaq 24(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4194304, %edx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movq %r15, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $64, 60(%rsp)
movl $64, 64(%rsp)
movl $16, 48(%rsp)
movl $16, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movl $2, %ecx
movl $4194304, %edx
movq 40(%rsp), %rsi
movq 8(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r14, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $1024, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z33__device_stub__Z9matrixMulPiS_S_iPiS_S_i
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z9matrixMulPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9matrixMulPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vector_multiplication.hip"
.globl _Z24__device_stub__matrixMulPiS_S_i # -- Begin function _Z24__device_stub__matrixMulPiS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__matrixMulPiS_S_i,@function
_Z24__device_stub__matrixMulPiS_S_i: # @_Z24__device_stub__matrixMulPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9matrixMulPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__matrixMulPiS_S_i, .Lfunc_end0-_Z24__device_stub__matrixMulPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, 32(%rsp) # 8-byte Spill
xorl %r12d, %r12d
movq %rbx, %r13
movq %r14, %rbp
.p2align 4, 0x90
.LBB1_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
# kill: def $eax killed $eax def $rax
leal 1023(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
andl $-1024, %ecx # imm = 0xFC00
subl %ecx, %eax
movl %eax, (%r13,%r15,4)
callq rand
# kill: def $eax killed $eax def $rax
leal 1023(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
andl $-1024, %ecx # imm = 0xFC00
subl %ecx, %eax
movl %eax, (%rbp,%r15,4)
incq %r15
cmpq $1024, %r15 # imm = 0x400
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %r12
addq $4096, %rbp # imm = 0x1000
addq $4096, %r13 # imm = 0x1000
cmpq $1024, %r12 # imm = 0x400
jne .LBB1_1
# %bb.4:
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movq %rsp, %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movq 16(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $274877907008, %rdi # imm = 0x4000000040
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $1024, 28(%rsp) # imm = 0x400
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9matrixMulPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq (%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq 32(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9matrixMulPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9matrixMulPiS_S_i,@object # @_Z9matrixMulPiS_S_i
.section .rodata,"a",@progbits
.globl _Z9matrixMulPiS_S_i
.p2align 3, 0x0
_Z9matrixMulPiS_S_i:
.quad _Z24__device_stub__matrixMulPiS_S_i
.size _Z9matrixMulPiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9matrixMulPiS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Completed Successfully!"
.size .Lstr, 24
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__matrixMulPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9matrixMulPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void kernel(unsigned char *ptr, int ticks) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int offset = x + y*blockDim.x*gridDim.x;
float fx = x - DIM / 2;
float fy = y - DIM / 2;
float d = sqrtf(fx*fx + fy*fy);
unsigned char grey = (unsigned char)(128.0f + 127.0f * cos(d / 10.0f - ticks / 7.0f) / (d / 10.0f + 1.0f));
ptr[offset * 4 + 0] = grey;
ptr[offset * 4 + 1] = grey;
ptr[offset * 4 + 2] = grey;
ptr[offset * 4 + 3] = 255;
} | code for sm_80
Function : _Z6kernelPhi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R8, SR_CTAID.Y ; /* 0x0000000000087919 */
/* 0x000e220000002600 */
/*0020*/ IADD3 R1, R1, -0x20, RZ ; /* 0xffffffe001017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ BSSY B0, 0x1d0 ; /* 0x0000019000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0050*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e680000002500 */
/*0060*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0070*/ IMAD R8, R8, c[0x0][0x4], R3 ; /* 0x0000010008087a24 */
/* 0x001fca00078e0203 */
/*0080*/ IADD3 R3, R8, -0x200, RZ ; /* 0xfffffe0008037810 */
/* 0x000fe20007ffe0ff */
/*0090*/ IMAD R9, R9, c[0x0][0x0], R0 ; /* 0x0000000009097a24 */
/* 0x002fca00078e0200 */
/*00a0*/ I2F R3, R3 ; /* 0x0000000300037306 */
/* 0x000e220000201400 */
/*00b0*/ IADD3 R2, R9, -0x200, RZ ; /* 0xfffffe0009027810 */
/* 0x000fce0007ffe0ff */
/*00c0*/ I2F R2, R2 ; /* 0x0000000200027306 */
/* 0x000e620000201400 */
/*00d0*/ FMUL R5, R3, R3 ; /* 0x0000000303057220 */
/* 0x001fc80000400000 */
/*00e0*/ FFMA R5, R2, R2, R5 ; /* 0x0000000202057223 */
/* 0x002fc80000000005 */
/*00f0*/ MUFU.RSQ R4, R5 ; /* 0x0000000500047308 */
/* 0x0000620000001400 */
/*0100*/ IADD3 R0, R5, -0xd000000, RZ ; /* 0xf300000005007810 */
/* 0x000fc80007ffe0ff */
/*0110*/ ISETP.GT.U32.AND P0, PT, R0, 0x727fffff, PT ; /* 0x727fffff0000780c */
/* 0x000fe20003f04070 */
/*0120*/ IMAD.MOV.U32 R0, RZ, RZ, R1 ; /* 0x000000ffff007224 */
/* 0x000fd800078e0001 */
/*0130*/ @!P0 BRA 0x180 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0140*/ MOV R11, 0x160 ; /* 0x00000160000b7802 */
/* 0x003fe40000000f00 */
/*0150*/ CALL.REL.NOINC 0xb20 ; /* 0x000009c000007944 */
/* 0x000fea0003c00000 */
/*0160*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0004 */
/*0170*/ BRA 0x1c0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0180*/ FMUL.FTZ R2, R5, R4 ; /* 0x0000000405027220 */
/* 0x003fe40000410000 */
/*0190*/ FMUL.FTZ R4, R4, 0.5 ; /* 0x3f00000004047820 */
/* 0x000fe40000410000 */
/*01a0*/ FFMA R5, -R2, R2, R5 ; /* 0x0000000202057223 */
/* 0x000fc80000000105 */
/*01b0*/ FFMA R2, R5, R4, R2 ; /* 0x0000000405027223 */
/* 0x000fe40000000002 */
/*01c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01d0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x3dcccccd ; /* 0x3dcccccdff047424 */
/* 0x000fe200078e00ff */
/*01e0*/ FCHK P0, R2, 10 ; /* 0x4120000002007902 */
/* 0x000e220000000000 */
/*01f0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x41200000 ; /* 0x41200000ff037424 */
/* 0x000fe200078e00ff */
/*0200*/ BSSY B0, 0x2d0 ; /* 0x000000c000007945 */
/* 0x000fe60003800000 */
/*0210*/ FFMA R3, R4, -R3, 1 ; /* 0x3f80000004037423 */
/* 0x000fc80000000803 */
/*0220*/ FFMA R3, R3, R4, 0.10000000149011611938 ; /* 0x3dcccccd03037423 */
/* 0x000fc80000000004 */
/*0230*/ FFMA R10, R3, R2, RZ ; /* 0x00000002030a7223 */
/* 0x000fc800000000ff */
/*0240*/ FFMA R4, R10, -10, R2 ; /* 0xc12000000a047823 */
/* 0x000fc80000000002 */
/*0250*/ FFMA R10, R3, R4, R10 ; /* 0x00000004030a7223 */
/* 0x000fe2000000000a */
/*0260*/ @!P0 BRA 0x2c0 ; /* 0x0000005000008947 */
/* 0x001fea0003800000 */
/*0270*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0002 */
/*0280*/ MOV R2, 0x2b0 ; /* 0x000002b000027802 */
/* 0x000fe20000000f00 */
/*0290*/ IMAD.MOV.U32 R7, RZ, RZ, 0x41200000 ; /* 0x41200000ff077424 */
/* 0x000fe400078e00ff */
/*02a0*/ CALL.REL.NOINC 0xc90 ; /* 0x000009e000007944 */
/* 0x000fea0003c00000 */
/*02b0*/ IMAD.MOV.U32 R10, RZ, RZ, R11 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e000b */
/*02c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02d0*/ I2F R2, c[0x0][0x168] ; /* 0x00005a0000027b06 */
/* 0x000e220000201400 */
/*02e0*/ HFMA2.MMA R4, -RZ, RZ, 1.517578125, 10.2890625 ; /* 0x3e124925ff047435 */
/* 0x000fe200000001ff */
/*02f0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x40e00000 ; /* 0x40e00000ff037424 */
/* 0x000fd200078e00ff */
/*0300*/ FFMA R3, -R4, R3, 1 ; /* 0x3f80000004037423 */
/* 0x000fc80000000103 */
/*0310*/ FFMA R3, R3, -R4, -0.14285714924335479736 ; /* 0xbe12492503037423 */
/* 0x000fe20000000804 */
/*0320*/ FCHK P0, R2, -7 ; /* 0xc0e0000002007902 */
/* 0x001e260000000000 */
/*0330*/ FFMA R4, R2, R3, RZ ; /* 0x0000000302047223 */
/* 0x000fc800000000ff */
/*0340*/ FFMA R5, R4, 7, R2 ; /* 0x40e0000004057823 */
/* 0x000fc80000000002 */
/*0350*/ FFMA R11, R3, R5, R4 ; /* 0x00000005030b7223 */
/* 0x000fe20000000004 */
/*0360*/ @!P0 BRA 0x3b0 ; /* 0x0000004000008947 */
/* 0x001fea0003800000 */
/*0370*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0002 */
/*0380*/ MOV R2, 0x3b0 ; /* 0x000003b000027802 */
/* 0x000fe20000000f00 */
/*0390*/ IMAD.MOV.U32 R7, RZ, RZ, -0x3f200000 ; /* 0xc0e00000ff077424 */
/* 0x000fe400078e00ff */
/*03a0*/ CALL.REL.NOINC 0xc90 ; /* 0x000008e000007944 */
/* 0x000fea0003c00000 */
/*03b0*/ FADD R11, R11, R10 ; /* 0x0000000a0b0b7221 */
/* 0x000fe20000000000 */
/*03c0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*03d0*/ BSSY B0, 0x820 ; /* 0x0000044000007945 */
/* 0x000fe40003800000 */
/*03e0*/ FMUL R2, R11.reuse, 0.63661974668502807617 ; /* 0x3f22f9830b027820 */
/* 0x040fe20000400000 */
/*03f0*/ FSETP.GE.AND P0, PT, |R11|, 105615, PT ; /* 0x47ce47800b00780b */
/* 0x000fc60003f06200 */
/*0400*/ F2I.NTZ R6, R2 ; /* 0x0000000200067305 */
/* 0x000e300000203100 */
/*0410*/ I2F R4, R6 ; /* 0x0000000600047306 */
/* 0x001e240000201400 */
/*0420*/ FFMA R3, R4, -1.5707962512969970703, R11 ; /* 0xbfc90fda04037823 */
/* 0x001fc8000000000b */
/*0430*/ FFMA R3, R4, -7.5497894158615963534e-08, R3 ; /* 0xb3a2216804037823 */
/* 0x000fc80000000003 */
/*0440*/ FFMA R7, R4, -5.3903029534742383927e-15, R3 ; /* 0xa7c234c504077823 */
/* 0x000fe20000000003 */
/*0450*/ @!P0 BRA 0x810 ; /* 0x000003b000008947 */
/* 0x000fea0003800000 */
/*0460*/ FSETP.NEU.AND P0, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x000fda0003f0d200 */
/*0470*/ @!P0 BRA 0x7f0 ; /* 0x0000037000008947 */
/* 0x000fea0003800000 */
/*0480*/ IMAD.SHL.U32 R2, R11, 0x100, RZ ; /* 0x000001000b027824 */
/* 0x000fe200078e00ff */
/*0490*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*04a0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*04b0*/ ULDC.64 UR8, c[0x4][0x0] ; /* 0x0100000000087ab9 */
/* 0x000fe20000000a00 */
/*04c0*/ LOP3.LUT R15, R2, 0x80000000, RZ, 0xfc, !PT ; /* 0x80000000020f7812 */
/* 0x000fe400078efcff */
/*04d0*/ IMAD.U32 R4, RZ, RZ, UR8 ; /* 0x00000008ff047e24 */
/* 0x000fe4000f8e00ff */
/*04e0*/ IMAD.U32 R5, RZ, RZ, UR9 ; /* 0x00000009ff057e24 */
/* 0x000fca000f8e00ff */
/*04f0*/ LDG.E.CONSTANT R2, [R4.64] ; /* 0x0000000604027981 */
/* 0x000ea2000c1e9900 */
/*0500*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe20007ffe0ff */
/*0510*/ UIADD3 UR8, UP0, UR8, 0x4, URZ ; /* 0x0000000408087890 */
/* 0x000fc6000ff1e03f */
/*0520*/ ISETP.NE.AND P0, PT, R7, 0x6, PT ; /* 0x000000060700780c */
/* 0x000fe20003f05270 */
/*0530*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe200087fe43f */
/*0540*/ IMAD.WIDE.U32 R2, R2, R15, RZ ; /* 0x0000000f02027225 */
/* 0x004fca00078e00ff */
/*0550*/ IADD3 R13, P1, R2, R6, RZ ; /* 0x00000006020d7210 */
/* 0x000fc80007f3e0ff */
/*0560*/ IADD3.X R6, R3, UR4, RZ, P1, !PT ; /* 0x0000000403067c10 */
/* 0x000fe20008ffe4ff */
/*0570*/ STL [R0], R13 ; /* 0x0000000d00007387 */
/* 0x0001e40000100800 */
/*0580*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x001fe20007ffe0ff */
/*0590*/ @P0 BRA 0x4d0 ; /* 0xffffff3000000947 */
/* 0x000fea000383ffff */
/*05a0*/ SHF.R.U32.HI R0, RZ, 0x17, R11 ; /* 0x00000017ff007819 */
/* 0x000fe2000001160b */
/*05b0*/ STL [R1+0x18], R6 ; /* 0x0000180601007387 */
/* 0x0001e60000100800 */
/*05c0*/ LOP3.LUT R0, R0, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff00007812 */
/* 0x000fc800078ec0ff */
/*05d0*/ IADD3 R0, R0, -0x80, RZ ; /* 0xffffff8000007810 */
/* 0x000fc80007ffe0ff */
/*05e0*/ LOP3.LUT P0, R7, R0, 0x1f, RZ, 0xc0, !PT ; /* 0x0000001f00077812 */
/* 0x000fe4000780c0ff */
/*05f0*/ SHF.R.U32.HI R0, RZ, 0x5, R0 ; /* 0x00000005ff007819 */
/* 0x000fc80000011600 */
/*0600*/ IADD3 R2, -R0.reuse, 0x4, RZ ; /* 0x0000000400027810 */
/* 0x040fe40007ffe1ff */
/*0610*/ IADD3 R0, -R0, 0x6, RZ ; /* 0x0000000600007810 */
/* 0x000fc80007ffe1ff */
/*0620*/ LEA R12, R0, R1, 0x2 ; /* 0x00000001000c7211 */
/* 0x000fe200078e10ff */
/*0630*/ @P0 IMAD R13, R2, 0x4, R1 ; /* 0x00000004020d0824 */
/* 0x000fc800078e0201 */
/*0640*/ LDL R0, [R12] ; /* 0x000000000c007983 */
/* 0x000ea80000100800 */
/*0650*/ @P0 LDL R5, [R13] ; /* 0x000000000d050983 */
/* 0x000ee80000100800 */
/*0660*/ LDL R3, [R12+-0x4] ; /* 0xfffffc000c037983 */
/* 0x000f220000100800 */
/*0670*/ @P0 IADD3 R2, -R7, 0x20, RZ ; /* 0x0000002007020810 */
/* 0x000fe40007ffe1ff */
/*0680*/ LOP3.LUT P1, R11, R11, 0x80000000, RZ, 0xc0, !PT ; /* 0x800000000b0b7812 */
/* 0x000fc4000782c0ff */
/*0690*/ @P0 SHF.R.U32.HI R4, RZ, R2.reuse, R5 ; /* 0x00000002ff040219 */
/* 0x088fe40000011605 */
/*06a0*/ @P0 SHF.L.U32 R5, R0, R7.reuse, RZ ; /* 0x0000000700050219 */
/* 0x084fe400000006ff */
/*06b0*/ @P0 SHF.R.U32.HI R2, RZ, R2, R3 ; /* 0x00000002ff020219 */
/* 0x010fe40000011603 */
/*06c0*/ @P0 SHF.L.U32 R7, R3, R7, RZ ; /* 0x0000000703070219 */
/* 0x000fc600000006ff */
/*06d0*/ @P0 IMAD.IADD R0, R2, 0x1, R5 ; /* 0x0000000102000824 */
/* 0x000fe400078e0205 */
/*06e0*/ @P0 IMAD.IADD R3, R4, 0x1, R7 ; /* 0x0000000104030824 */
/* 0x000fca00078e0207 */
/*06f0*/ SHF.L.U32.HI R5, R3, 0x2, R0 ; /* 0x0000000203057819 */
/* 0x000fc80000010600 */
/*0700*/ SHF.R.U32.HI R7, RZ, 0x1f, R5 ; /* 0x0000001fff077819 */
/* 0x000fc80000011605 */
/*0710*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*0720*/ IMAD.SHL.U32 R4, R3, 0x4, RZ ; /* 0x0000000403047824 */
/* 0x000fd800078e00ff */
/*0730*/ @P0 LOP3.LUT R5, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff050212 */
/* 0x000fe400078e33ff */
/*0740*/ @P0 LOP3.LUT R4, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff040212 */
/* 0x000fc800078e33ff */
/*0750*/ I2F.F64.S64 R2, R4 ; /* 0x0000000400027312 */
/* 0x000e640000301c00 */
/*0760*/ DMUL R2, R2, c[0x2][0x0] ; /* 0x0080000002027a28 */
/* 0x002e620000000000 */
/*0770*/ LEA.HI R6, R0, R7, RZ, 0x2 ; /* 0x0000000700067211 */
/* 0x001fd200078f10ff */
/*0780*/ F2F.F32.F64 R2, R2 ; /* 0x0000000200027310 */
/* 0x002e220000301000 */
/*0790*/ @P0 LOP3.LUT R11, R11, 0x80000000, RZ, 0x3c, !PT ; /* 0x800000000b0b0812 */
/* 0x000fe200078e3cff */
/*07a0*/ IMAD.MOV R0, RZ, RZ, -R6 ; /* 0x000000ffff007224 */
/* 0x000fc600078e0a06 */
/*07b0*/ ISETP.NE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f05270 */
/*07c0*/ @P1 IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff061224 */
/* 0x000fc600078e0000 */
/*07d0*/ FSEL R7, R2, -R2, !P0 ; /* 0x8000000202077208 */
/* 0x001fe20004000000 */
/*07e0*/ BRA 0x810 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*07f0*/ FMUL R7, RZ, R11 ; /* 0x0000000bff077220 */
/* 0x000fe40000400000 */
/*0800*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*0810*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0820*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fe20007ffe0ff */
/*0830*/ IMAD.MOV.U32 R3, RZ, RZ, 0x3c0885e4 ; /* 0x3c0885e4ff037424 */
/* 0x000fe200078e00ff */
/*0840*/ MOV R0, 0xb94d4153 ; /* 0xb94d415300007802 */
/* 0x000fe20000000f00 */
/*0850*/ FMUL R5, R7, R7 ; /* 0x0000000707057220 */
/* 0x000fe20000400000 */
/*0860*/ LOP3.LUT P1, RZ, R6.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000106ff7812 */
/* 0x040fe2000782c0ff */
/*0870*/ IMAD.MOV.U32 R4, RZ, RZ, 0x3e2aaaa8 ; /* 0x3e2aaaa8ff047424 */
/* 0x000fe200078e00ff */
/*0880*/ LOP3.LUT P0, RZ, R6, 0x2, RZ, 0xc0, !PT ; /* 0x0000000206ff7812 */
/* 0x000fe2000780c0ff */
/*0890*/ FADD R11, R10, 1 ; /* 0x3f8000000a0b7421 */
/* 0x000fe20000000000 */
/*08a0*/ FSEL R3, R3, 0.041666727513074874878, !P1 ; /* 0x3d2aaabb03037808 */
/* 0x000fe20004800000 */
/*08b0*/ BSSY B0, 0xa30 ; /* 0x0000017000007945 */
/* 0x000fe20003800000 */
/*08c0*/ FSEL R7, R7, 1, !P1 ; /* 0x3f80000007077808 */
/* 0x000fce0004800000 */
/*08d0*/ @P1 IMAD.MOV.U32 R2, RZ, RZ, 0x37cbac00 ; /* 0x37cbac00ff021424 */
/* 0x000fc800078e00ff */
/*08e0*/ @P1 FFMA R0, R5.reuse, R2, -0.0013887860113754868507 ; /* 0xbab607ed05001423 */
/* 0x040fe40000000002 */
/*08f0*/ MUFU.RCP R2, R11 ; /* 0x0000000b00027308 */
/* 0x000e240000001000 */
/*0900*/ FFMA R0, R5, R0, R3 ; /* 0x0000000005007223 */
/* 0x000fe20000000003 */
/*0910*/ FSEL R3, -R4, -0.4999999701976776123, !P1 ; /* 0xbeffffff04037808 */
/* 0x000fca0004800100 */
/*0920*/ FFMA R0, R5, R0, R3 ; /* 0x0000000005007223 */
/* 0x000fe40000000003 */
/*0930*/ FFMA R3, R7, R5, RZ ; /* 0x0000000507037223 */
/* 0x000fc800000000ff */
/*0940*/ FFMA R0, R0, R3, R7 ; /* 0x0000000300007223 */
/* 0x000fe40000000007 */
/*0950*/ FFMA R3, -R11, R2, 1 ; /* 0x3f8000000b037423 */
/* 0x001fe40000000102 */
/*0960*/ @P0 FFMA R0, R0, -1, RZ ; /* 0xbf80000000000823 */
/* 0x000fe400000000ff */
/*0970*/ FFMA R3, R2, R3, R2 ; /* 0x0000000302037223 */
/* 0x000fe40000000002 */
/*0980*/ FMUL R6, R0, 127 ; /* 0x42fe000000067820 */
/* 0x000fc80000400000 */
/*0990*/ FCHK P0, R6, R11 ; /* 0x0000000b06007302 */
/* 0x000e220000000000 */
/*09a0*/ FFMA R0, R6, R3, RZ ; /* 0x0000000306007223 */
/* 0x000fc800000000ff */
/*09b0*/ FFMA R2, -R11, R0, R6 ; /* 0x000000000b027223 */
/* 0x000fc80000000106 */
/*09c0*/ FFMA R0, R3, R2, R0 ; /* 0x0000000203007223 */
/* 0x000fe20000000000 */
/*09d0*/ @!P0 BRA 0xa20 ; /* 0x0000004000008947 */
/* 0x001fea0003800000 */
/*09e0*/ IMAD.MOV.U32 R7, RZ, RZ, R11 ; /* 0x000000ffff077224 */
/* 0x000fe200078e000b */
/*09f0*/ MOV R2, 0xa10 ; /* 0x00000a1000027802 */
/* 0x000fe40000000f00 */
/*0a00*/ CALL.REL.NOINC 0xc90 ; /* 0x0000028000007944 */
/* 0x000fea0003c00000 */
/*0a10*/ IMAD.MOV.U32 R0, RZ, RZ, R11 ; /* 0x000000ffff007224 */
/* 0x000fe400078e000b */
/*0a20*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0a30*/ ULDC UR4, c[0x0][0xc] ; /* 0x0000030000047ab9 */
/* 0x000fe20000000800 */
/*0a40*/ FADD R0, R0, 128 ; /* 0x4300000000007421 */
/* 0x000fe20000000000 */
/*0a50*/ ULDC UR5, c[0x0][0x0] ; /* 0x0000000000057ab9 */
/* 0x000fe20000000800 */
/*0a60*/ HFMA2.MMA R4, -RZ, RZ, 0, 1.5199184417724609375e-05 ; /* 0x000000ffff047435 */
/* 0x000fe200000001ff */
/*0a70*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fe2000f8e023f */
/*0a80*/ F2I.U32.TRUNC.NTZ R5, R0 ; /* 0x0000000000057305 */
/* 0x000e2a000020f000 */
/*0a90*/ IMAD R8, R8, UR4, R9 ; /* 0x0000000408087c24 */
/* 0x000fc8000f8e0209 */
/*0aa0*/ IMAD.SHL.U32 R8, R8, 0x4, RZ ; /* 0x0000000408087824 */
/* 0x000fca00078e00ff */
/*0ab0*/ IADD3 R2, P0, R8, c[0x0][0x160], RZ ; /* 0x0000580008027a10 */
/* 0x000fc80007f1e0ff */
/*0ac0*/ LEA.HI.X.SX32 R3, R8, c[0x0][0x164], 0x1, P0 ; /* 0x0000590008037a11 */
/* 0x000fca00000f0eff */
/*0ad0*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe8000c101106 */
/*0ae0*/ STG.E.U8 [R2.64+0x1], R5 ; /* 0x0000010502007986 */
/* 0x000fe8000c101106 */
/*0af0*/ STG.E.U8 [R2.64+0x2], R5 ; /* 0x0000020502007986 */
/* 0x000fe8000c101106 */
/*0b00*/ STG.E.U8 [R2.64+0x3], R4 ; /* 0x0000030402007986 */
/* 0x000fe2000c101106 */
/*0b10*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b20*/ LOP3.LUT P0, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05ff7812 */
/* 0x000fda000780c0ff */
/*0b30*/ @!P0 IMAD.MOV.U32 R2, RZ, RZ, R5 ; /* 0x000000ffff028224 */
/* 0x000fe200078e0005 */
/*0b40*/ @!P0 BRA 0xc50 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0b50*/ FSETP.GEU.FTZ.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720b */
/* 0x000fda0003f1e000 */
/*0b60*/ @!P0 IMAD.MOV.U32 R2, RZ, RZ, 0x7fffffff ; /* 0x7fffffffff028424 */
/* 0x000fe200078e00ff */
/*0b70*/ @!P0 BRA 0xc50 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0b80*/ FSETP.GTU.FTZ.AND P0, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fda0003f1c200 */
/*0b90*/ @P0 FADD.FTZ R2, R5, 1 ; /* 0x3f80000005020421 */
/* 0x000fe20000010000 */
/*0ba0*/ @P0 BRA 0xc50 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0bb0*/ FSETP.NEU.FTZ.AND P0, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fda0003f1d200 */
/*0bc0*/ @P0 FFMA R3, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f80000005030823 */
/* 0x000fc800000000ff */
/*0bd0*/ @P0 MUFU.RSQ R2, R3 ; /* 0x0000000300020308 */
/* 0x000e240000001400 */
/*0be0*/ @P0 FMUL.FTZ R4, R3, R2 ; /* 0x0000000203040220 */
/* 0x001fe40000410000 */
/*0bf0*/ @P0 FMUL.FTZ R10, R2, 0.5 ; /* 0x3f000000020a0820 */
/* 0x000fe40000410000 */
/*0c00*/ @P0 FADD.FTZ R6, -R4.reuse, -RZ ; /* 0x800000ff04060221 */
/* 0x040fe40000010100 */
/*0c10*/ @!P0 IMAD.MOV.U32 R2, RZ, RZ, R5 ; /* 0x000000ffff028224 */
/* 0x000fe400078e0005 */
/*0c20*/ @P0 FFMA R7, R4, R6, R3 ; /* 0x0000000604070223 */
/* 0x000fc80000000003 */
/*0c30*/ @P0 FFMA R7, R7, R10, R4 ; /* 0x0000000a07070223 */
/* 0x000fc80000000004 */
/*0c40*/ @P0 FMUL.FTZ R2, R7, 2.3283064365386962891e-10 ; /* 0x2f80000007020820 */
/* 0x000fc80000410000 */
/*0c50*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0002 */
/*0c60*/ IMAD.MOV.U32 R2, RZ, RZ, R11 ; /* 0x000000ffff027224 */
/* 0x000fe400078e000b */
/*0c70*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0c80*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff37002007950 */
/* 0x000fea0003c3ffff */
/*0c90*/ SHF.R.U32.HI R4, RZ, 0x17, R7.reuse ; /* 0x00000017ff047819 */
/* 0x100fe20000011607 */
/*0ca0*/ BSSY B1, 0x12f0 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0cb0*/ SHF.R.U32.HI R3, RZ, 0x17, R6 ; /* 0x00000017ff037819 */
/* 0x000fe40000011606 */
/*0cc0*/ LOP3.LUT R13, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff040d7812 */
/* 0x000fe200078ec0ff */
/*0cd0*/ IMAD.MOV.U32 R4, RZ, RZ, R7 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0007 */
/*0ce0*/ LOP3.LUT R11, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff030b7812 */
/* 0x000fe400078ec0ff */
/*0cf0*/ IADD3 R14, R13, -0x1, RZ ; /* 0xffffffff0d0e7810 */
/* 0x000fe40007ffe0ff */
/*0d00*/ IADD3 R12, R11, -0x1, RZ ; /* 0xffffffff0b0c7810 */
/* 0x000fc40007ffe0ff */
/*0d10*/ ISETP.GT.U32.AND P0, PT, R14, 0xfd, PT ; /* 0x000000fd0e00780c */
/* 0x000fe40003f04070 */
/*0d20*/ MOV R3, R6 ; /* 0x0000000600037202 */
/* 0x000fe40000000f00 */
/*0d30*/ ISETP.GT.U32.OR P0, PT, R12, 0xfd, P0 ; /* 0x000000fd0c00780c */
/* 0x000fda0000704470 */
/*0d40*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff058224 */
/* 0x000fe200078e00ff */
/*0d50*/ @!P0 BRA 0xed0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0d60*/ FSETP.GTU.FTZ.AND P0, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fe40003f1c200 */
/*0d70*/ FSETP.GTU.FTZ.AND P1, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fc80003f3c200 */
/*0d80*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0d90*/ @P0 BRA 0x12d0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0da0*/ LOP3.LUT P0, RZ, R4, 0x7fffffff, R3, 0xc8, !PT ; /* 0x7fffffff04ff7812 */
/* 0x000fda000780c803 */
/*0db0*/ @!P0 BRA 0x12b0 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0dc0*/ FSETP.NEU.FTZ.AND P2, PT, |R6|.reuse, +INF , PT ; /* 0x7f8000000600780b */
/* 0x040fe40003f5d200 */
/*0dd0*/ FSETP.NEU.FTZ.AND P1, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fe40003f3d200 */
/*0de0*/ FSETP.NEU.FTZ.AND P0, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fd60003f1d200 */
/*0df0*/ @!P1 BRA !P2, 0x12b0 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0e00*/ LOP3.LUT P2, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff03ff7812 */
/* 0x000fc8000784c0ff */
/*0e10*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0e20*/ @P1 BRA 0x1290 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0e30*/ LOP3.LUT P1, RZ, R4, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff04ff7812 */
/* 0x000fc8000782c0ff */
/*0e40*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0e50*/ @P0 BRA 0x1260 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0e60*/ ISETP.GE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f06270 */
/*0e70*/ ISETP.GE.AND P1, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fd60003f26270 */
/*0e80*/ @P0 IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff050224 */
/* 0x000fe400078e00ff */
/*0e90*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, -0x40 ; /* 0xffffffc0ff058424 */
/* 0x000fe400078e00ff */
/*0ea0*/ @!P0 FFMA R3, R6, 1.84467440737095516160e+19, RZ ; /* 0x5f80000006038823 */
/* 0x000fe400000000ff */
/*0eb0*/ @!P1 FFMA R4, R7, 1.84467440737095516160e+19, RZ ; /* 0x5f80000007049823 */
/* 0x000fe200000000ff */
/*0ec0*/ @!P1 IADD3 R5, R5, 0x40, RZ ; /* 0x0000004005059810 */
/* 0x000fe40007ffe0ff */
/*0ed0*/ LEA R7, R13, 0xc0800000, 0x17 ; /* 0xc08000000d077811 */
/* 0x000fe200078eb8ff */
/*0ee0*/ BSSY B2, 0x1250 ; /* 0x0000036000027945 */
/* 0x000fe80003800000 */
/*0ef0*/ IMAD.IADD R7, R4, 0x1, -R7 ; /* 0x0000000104077824 */
/* 0x000fe200078e0a07 */
/*0f00*/ IADD3 R4, R11, -0x7f, RZ ; /* 0xffffff810b047810 */
/* 0x000fc60007ffe0ff */
/*0f10*/ MUFU.RCP R6, R7 ; /* 0x0000000700067308 */
/* 0x000e220000001000 */
/*0f20*/ FADD.FTZ R12, -R7, -RZ ; /* 0x800000ff070c7221 */
/* 0x000fe40000010100 */
/*0f30*/ IMAD R3, R4, -0x800000, R3 ; /* 0xff80000004037824 */
/* 0x000fe400078e0203 */
/*0f40*/ FFMA R11, R6, R12, 1 ; /* 0x3f800000060b7423 */
/* 0x001fc8000000000c */
/*0f50*/ FFMA R14, R6, R11, R6 ; /* 0x0000000b060e7223 */
/* 0x000fc80000000006 */
/*0f60*/ FFMA R6, R3, R14, RZ ; /* 0x0000000e03067223 */
/* 0x000fc800000000ff */
/*0f70*/ FFMA R11, R12, R6, R3 ; /* 0x000000060c0b7223 */
/* 0x000fc80000000003 */
/*0f80*/ FFMA R11, R14, R11, R6 ; /* 0x0000000b0e0b7223 */
/* 0x000fe20000000006 */
/*0f90*/ IADD3 R6, R4, 0x7f, -R13 ; /* 0x0000007f04067810 */
/* 0x000fc60007ffe80d */
/*0fa0*/ FFMA R12, R12, R11, R3 ; /* 0x0000000b0c0c7223 */
/* 0x000fe40000000003 */
/*0fb0*/ IMAD.IADD R6, R6, 0x1, R5 ; /* 0x0000000106067824 */
/* 0x000fe400078e0205 */
/*0fc0*/ FFMA R3, R14, R12, R11 ; /* 0x0000000c0e037223 */
/* 0x000fca000000000b */
/*0fd0*/ SHF.R.U32.HI R4, RZ, 0x17, R3 ; /* 0x00000017ff047819 */
/* 0x000fc80000011603 */
/*0fe0*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fc800078ec0ff */
/*0ff0*/ IADD3 R13, R4, R6, RZ ; /* 0x00000006040d7210 */
/* 0x000fc80007ffe0ff */
/*1000*/ IADD3 R4, R13, -0x1, RZ ; /* 0xffffffff0d047810 */
/* 0x000fc80007ffe0ff */
/*1010*/ ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ; /* 0x000000fe0400780c */
/* 0x000fda0003f06070 */
/*1020*/ @!P0 BRA 0x1230 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*1030*/ ISETP.GT.AND P0, PT, R13, 0xfe, PT ; /* 0x000000fe0d00780c */
/* 0x000fda0003f04270 */
/*1040*/ @P0 BRA 0x1200 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*1050*/ ISETP.GE.AND P0, PT, R13, 0x1, PT ; /* 0x000000010d00780c */
/* 0x000fda0003f06270 */
/*1060*/ @P0 BRA 0x1240 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*1070*/ ISETP.GE.AND P0, PT, R13, -0x18, PT ; /* 0xffffffe80d00780c */
/* 0x000fe40003f06270 */
/*1080*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*1090*/ @!P0 BRA 0x1240 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*10a0*/ FFMA.RZ R4, R14.reuse, R12.reuse, R11.reuse ; /* 0x0000000c0e047223 */
/* 0x1c0fe2000000c00b */
/*10b0*/ IADD3 R7, R13.reuse, 0x20, RZ ; /* 0x000000200d077810 */
/* 0x040fe20007ffe0ff */
/*10c0*/ FFMA.RM R5, R14, R12.reuse, R11.reuse ; /* 0x0000000c0e057223 */
/* 0x180fe2000000400b */
/*10d0*/ ISETP.NE.AND P2, PT, R13.reuse, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x040fe40003f45270 */
/*10e0*/ LOP3.LUT R6, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04067812 */
/* 0x000fe200078ec0ff */
/*10f0*/ FFMA.RP R4, R14, R12, R11 ; /* 0x0000000c0e047223 */
/* 0x000fe2000000800b */
/*1100*/ ISETP.NE.AND P1, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe20003f25270 */
/*1110*/ IMAD.MOV R11, RZ, RZ, -R13 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0a0d */
/*1120*/ LOP3.LUT R6, R6, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000006067812 */
/* 0x000fe400078efcff */
/*1130*/ FSETP.NEU.FTZ.AND P0, PT, R4, R5, PT ; /* 0x000000050400720b */
/* 0x000fc40003f1d000 */
/*1140*/ SHF.L.U32 R7, R6, R7, RZ ; /* 0x0000000706077219 */
/* 0x000fe400000006ff */
/*1150*/ SEL R5, R11, RZ, P2 ; /* 0x000000ff0b057207 */
/* 0x000fe40001000000 */
/*1160*/ ISETP.NE.AND P1, PT, R7, RZ, P1 ; /* 0x000000ff0700720c */
/* 0x000fe40000f25270 */
/*1170*/ SHF.R.U32.HI R5, RZ, R5, R6 ; /* 0x00000005ff057219 */
/* 0x000fe40000011606 */
/*1180*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*1190*/ SHF.R.U32.HI R7, RZ, 0x1, R5 ; /* 0x00000001ff077819 */
/* 0x000fc40000011605 */
/*11a0*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*11b0*/ LOP3.LUT R4, R4, 0x1, R7, 0xf8, !PT ; /* 0x0000000104047812 */
/* 0x000fc800078ef807 */
/*11c0*/ LOP3.LUT R4, R4, R5, RZ, 0xc0, !PT ; /* 0x0000000504047212 */
/* 0x000fca00078ec0ff */
/*11d0*/ IMAD.IADD R4, R7, 0x1, R4 ; /* 0x0000000107047824 */
/* 0x000fca00078e0204 */
/*11e0*/ LOP3.LUT R3, R4, R3, RZ, 0xfc, !PT ; /* 0x0000000304037212 */
/* 0x000fe200078efcff */
/*11f0*/ BRA 0x1240 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*1200*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*1210*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*1220*/ BRA 0x1240 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*1230*/ IMAD R3, R6, 0x800000, R3 ; /* 0x0080000006037824 */
/* 0x000fe400078e0203 */
/*1240*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*1250*/ BRA 0x12e0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*1260*/ LOP3.LUT R3, R4, 0x80000000, R3, 0x48, !PT ; /* 0x8000000004037812 */
/* 0x000fc800078e4803 */
/*1270*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*1280*/ BRA 0x12e0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*1290*/ LOP3.LUT R3, R4, 0x80000000, R3, 0x48, !PT ; /* 0x8000000004037812 */
/* 0x000fe200078e4803 */
/*12a0*/ BRA 0x12e0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*12b0*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*12c0*/ BRA 0x12e0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*12d0*/ FADD.FTZ R3, R6, R7 ; /* 0x0000000706037221 */
/* 0x000fe40000010000 */
/*12e0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*12f0*/ IMAD.MOV.U32 R11, RZ, RZ, R3 ; /* 0x000000ffff0b7224 */
/* 0x001fe400078e0003 */
/*1300*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*1310*/ RET.REL.NODEC R2 0x0 ; /* 0xffffece002007950 */
/* 0x000fea0003c3ffff */
/*1320*/ BRA 0x1320; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kernel(unsigned char *ptr, int ticks) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int offset = x + y*blockDim.x*gridDim.x;
float fx = x - DIM / 2;
float fy = y - DIM / 2;
float d = sqrtf(fx*fx + fy*fy);
unsigned char grey = (unsigned char)(128.0f + 127.0f * cos(d / 10.0f - ticks / 7.0f) / (d / 10.0f + 1.0f));
ptr[offset * 4 + 0] = grey;
ptr[offset * 4 + 1] = grey;
ptr[offset * 4 + 2] = grey;
ptr[offset * 4 + 3] = 255;
} | .file "tmpxft_00148390_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z6kernelPhiPhi
.type _Z26__device_stub__Z6kernelPhiPhi, @function
_Z26__device_stub__Z6kernelPhiPhi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPhi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z6kernelPhiPhi, .-_Z26__device_stub__Z6kernelPhiPhi
.globl _Z6kernelPhi
.type _Z6kernelPhi, @function
_Z6kernelPhi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6kernelPhiPhi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6kernelPhi, .-_Z6kernelPhi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kernelPhi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPhi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kernel(unsigned char *ptr, int ticks) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int offset = x + y*blockDim.x*gridDim.x;
float fx = x - DIM / 2;
float fy = y - DIM / 2;
float d = sqrtf(fx*fx + fy*fy);
unsigned char grey = (unsigned char)(128.0f + 127.0f * cos(d / 10.0f - ticks / 7.0f) / (d / 10.0f + 1.0f));
ptr[offset * 4 + 0] = grey;
ptr[offset * 4 + 1] = grey;
ptr[offset * 4 + 2] = grey;
ptr[offset * 4 + 3] = 255;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel(unsigned char *ptr, int ticks) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int offset = x + y*blockDim.x*gridDim.x;
float fx = x - DIM / 2;
float fy = y - DIM / 2;
float d = sqrtf(fx*fx + fy*fy);
unsigned char grey = (unsigned char)(128.0f + 127.0f * cos(d / 10.0f - ticks / 7.0f) / (d / 10.0f + 1.0f));
ptr[offset * 4 + 0] = grey;
ptr[offset * 4 + 1] = grey;
ptr[offset * 4 + 2] = grey;
ptr[offset * 4 + 3] = 255;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel(unsigned char *ptr, int ticks) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int offset = x + y*blockDim.x*gridDim.x;
float fx = x - DIM / 2;
float fy = y - DIM / 2;
float d = sqrtf(fx*fx + fy*fy);
unsigned char grey = (unsigned char)(128.0f + 127.0f * cos(d / 10.0f - ticks / 7.0f) / (d / 10.0f + 1.0f));
ptr[offset * 4 + 0] = grey;
ptr[offset * 4 + 1] = grey;
ptr[offset * 4 + 2] = grey;
ptr[offset * 4 + 3] = 255;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPhi
.globl _Z6kernelPhi
.p2align 8
.type _Z6kernelPhi,@function
_Z6kernelPhi:
s_load_b32 s2, s[0:1], 0x1c
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s4, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
v_mad_u64_u32 v[0:1], null, s14, s4, v[4:5]
s_load_b32 s3, s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v1, 0xfffffe00, v2
v_add_nc_u32_e32 v3, 0xfffffe00, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v1, v1
v_cvt_f32_i32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v1, v1, v1
v_fmac_f32_e32 v1, v3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v3, 0x4f800000, v1
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v1
v_cndmask_b32_e32 v1, v1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v3, v1
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v4, -1, v3
v_add_nc_u32_e32 v5, 1, v3
v_fma_f32 v6, -v4, v3, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v7, -v5, v3, v1
v_cmp_ge_f32_e64 s2, 0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v3, v3, v4, s2
v_cmp_lt_f32_e64 s2, 0, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v3, v3, v5, s2
v_mul_f32_e32 v4, 0x37800000, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v1, 0x260
v_cndmask_b32_e32 v1, v3, v1, vcc_lo
s_waitcnt lgkmcnt(0)
v_cvt_f32_i32_e32 v3, s3
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_scale_f32 v4, null, 0x41200000, 0x41200000, v1
v_div_scale_f32 v5, null, 0xc0e00000, 0xc0e00000, v3
v_div_scale_f32 v10, vcc_lo, v1, 0x41200000, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v6, v4
v_rcp_f32_e32 v7, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v4, v6, 1.0
v_fma_f32 v9, -v5, v7, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v6, v8, v6
v_div_scale_f32 v8, s2, v3, 0xc0e00000, v3
v_fmac_f32_e32 v7, v9, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v9, v10, v6
v_mul_f32_e32 v11, v8, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v12, -v4, v9, v10
v_fma_f32 v13, -v5, v11, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v9, v12, v6
v_fmac_f32_e32 v11, v13, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v4, -v4, v9, v10
v_fma_f32 v5, -v5, v11, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f32 v4, v4, v6, v9
s_mov_b32 vcc_lo, s2
v_div_fmas_f32 v5, v5, v7, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f32 v1, v4, 0x41200000, v1
v_div_fixup_f32 v3, v5, 0xc0e00000, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v1, v3
v_cmpx_ngt_f32_e64 0x48000000, |v3|
s_xor_b32 s5, exec_lo, s3
s_cbranch_execz .LBB0_2
v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v11, 0x7fffffff, v3
s_mov_b32 s2, 0x7fffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_and_or_b32 v14, v11, s2, 0x800000
v_lshrrev_b32_e32 v11, 23, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[4:5], null, v14, 0xfe5163ab, 0
v_add_nc_u32_e32 v12, 0xffffff88, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_lt_u32_e32 vcc_lo, 63, v12
v_mad_u64_u32 v[7:8], null, v14, 0x3c439041, v[5:6]
v_cndmask_b32_e64 v13, 0, 0xffffffc0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v5, v8
v_add_nc_u32_e32 v13, v13, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[8:9], null, v14, 0xdb629599, v[5:6]
v_cmp_lt_u32_e64 s2, 31, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v15, 0, 0xffffffe0, s2
v_dual_mov_b32 v5, v9 :: v_dual_cndmask_b32 v4, v8, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v15, v15, v13
v_mad_u64_u32 v[9:10], null, v14, 0xf534ddc0, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_u32_e64 s3, 31, v15
v_mov_b32_e32 v5, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v7, v9, v7, vcc_lo
v_mad_u64_u32 v[10:11], null, v14, 0xfc2757d1, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v4, v7, v4, s2
v_mov_b32_e32 v5, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[11:12], null, v14, 0x4e441529, v[5:6]
v_mov_b32_e32 v5, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[12:13], null, v14, 0xa2f9836e, v[5:6]
v_cndmask_b32_e64 v5, 0, 0xffffffe0, s3
v_dual_cndmask_b32 v6, v11, v9 :: v_dual_add_nc_u32 v5, v5, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v12, v12, v10 :: v_dual_cndmask_b32 v11, v13, v11
v_cndmask_b32_e32 v10, v10, v8, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v9, v12, v6, s2
v_cndmask_b32_e64 v11, v11, v12, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v6, v6, v10, s2
v_sub_nc_u32_e32 v12, 32, v5
v_cndmask_b32_e64 v10, v10, v7, s2
v_cndmask_b32_e64 v11, v11, v9, s3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v9, v9, v6, s3
v_cndmask_b32_e64 v6, v6, v10, s3
v_cndmask_b32_e64 v4, v10, v4, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v13, v11, v9, v12
v_alignbit_b32 v8, v9, v6, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v5, v13, v11, vcc_lo
v_alignbit_b32 v11, v6, v4, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v7, v8, v9, vcc_lo
v_bfe_u32 v8, v5, 29, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v6, v11, v6, vcc_lo
v_alignbit_b32 v9, v5, v7, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v10, 0, v8
v_alignbit_b32 v7, v7, v6, 30
v_alignbit_b32 v4, v6, v4, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v9, v9, v10
v_xor_b32_e32 v6, v7, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v4, v4, v10
v_clz_i32_u32_e32 v11, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_u32_e32 v11, 32, v11
v_sub_nc_u32_e32 v7, 31, v11
v_lshlrev_b32_e32 v13, 23, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_alignbit_b32 v9, v9, v6, v7
v_alignbit_b32 v4, v6, v4, v7
v_lshrrev_b32_e32 v7, 29, v5
v_alignbit_b32 v6, v9, v4, 9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b32_e32 v7, 31, v7
v_lshrrev_b32_e32 v9, 9, v9
v_clz_i32_u32_e32 v10, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v12, 0.5, v7
v_min_u32_e32 v10, 32, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v12, v12, v13
v_sub_nc_u32_e32 v14, 31, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v4, v6, v4, v14
v_or_b32_e32 v6, v9, v12
v_add_lshl_u32 v9, v10, v11, 23
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshrrev_b32_e32 v4, 9, v4
v_mul_f32_e32 v10, 0x3fc90fda, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v4, v4, v9
v_fma_f32 v9, v6, 0x3fc90fda, -v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, 0x33000000, v4
v_fmamk_f32 v6, v6, 0x33a22168, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v4, v4, v7
v_fmac_f32_e32 v6, 0x3fc90fda, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v4, v10, v6
v_lshrrev_b32_e32 v5, 30, v5
v_add_nc_u32_e32 v5, v8, v5
.LBB0_2:
s_or_saveexec_b32 s3, s5
s_load_b32 s2, s[0:1], 0x10
s_xor_b32 exec_lo, exec_lo, s3
v_mul_f32_e64 v4, 0x3f22f983, |v3|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v5, v4
v_fma_f32 v4, v5, 0xbfc90fda, |v3|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v4, v5, 0xb3a22168, v4
v_fmamk_f32 v4, v5, 0xa7c234c4, v4
v_cvt_i32_f32_e32 v5, v5
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(VALU_DEP_1)
v_dual_mul_f32 v6, v4, v4 :: v_dual_and_b32 v9, 1, v5
s_mov_b32 s3, 0xb94c1982
s_mov_b32 s5, 0x37d75334
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s4
v_fmaak_f32 v7, s3, v6, 0x3c0881c4
v_cmp_eq_u32_e32 vcc_lo, 0, v9
s_load_b64 s[0:1], s[0:1], 0x0
v_mul_lo_u32 v2, s2, v2
v_lshlrev_b32_e32 v5, 30, v5
v_fmaak_f32 v7, v6, v7, 0xbe2aaa9d
v_fmaak_f32 v8, s5, v6, 0xbab64f3b
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_and_b32_e32 v5, 0x80000000, v5
v_mul_f32_e32 v7, v6, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fmaak_f32 v8, v6, v8, 0x3d2aabf7
v_add_lshl_u32 v0, v2, v0, 2
v_fmac_f32_e32 v4, v4, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmaak_f32 v8, v6, v8, 0xbf000004
v_or_b32_e32 v9, 1, v0
v_ashrrev_i32_e32 v2, 31, v0
v_or_b32_e32 v10, 3, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v6, v6, v8, 1.0
v_ashrrev_i32_e32 v12, 31, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v4, -v4, v6, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v3, 0x1f8
v_xor_b32_e32 v4, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v5, 1.0, v1 :: v_dual_mul_f32 v4, 0x42fe0000, v4
v_cndmask_b32_e32 v3, 0x7fc00000, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v1, null, v5, v5, v3
v_div_scale_f32 v7, vcc_lo, v3, v5, v3
v_rcp_f32_e32 v4, v1
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v1, v4, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v6, v4
v_mul_f32_e32 v6, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v1, v6, v7
v_fmac_f32_e32 v6, v8, v4
v_mov_b32_e32 v8, 0xff
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v1, -v1, v6, v7
v_or_b32_e32 v7, 2, v0
v_div_fmas_f32 v4, v1, v4, v6
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_ashrrev_i32_e32 v6, 31, v9
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
v_div_fixup_f32 v4, v4, v5, v3
v_add_co_u32 v2, vcc_lo, s0, v9
v_ashrrev_i32_e32 v11, 31, v7
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_f32_e32 v6, 0x43000000, v4
v_add_co_u32 v4, vcc_lo, s0, v7
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_cvt_i32_f32_e32 v9, v6
v_add_co_u32 v6, vcc_lo, s0, v10
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v12, vcc_lo
s_clause 0x3
global_store_b8 v[0:1], v9, off
global_store_b8 v[2:3], v9, off
global_store_b8 v[4:5], v9, off
global_store_b8 v[6:7], v8, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPhi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPhi, .Lfunc_end0-_Z6kernelPhi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPhi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPhi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel(unsigned char *ptr, int ticks) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int offset = x + y*blockDim.x*gridDim.x;
float fx = x - DIM / 2;
float fy = y - DIM / 2;
float d = sqrtf(fx*fx + fy*fy);
unsigned char grey = (unsigned char)(128.0f + 127.0f * cos(d / 10.0f - ticks / 7.0f) / (d / 10.0f + 1.0f));
ptr[offset * 4 + 0] = grey;
ptr[offset * 4 + 1] = grey;
ptr[offset * 4 + 2] = grey;
ptr[offset * 4 + 3] = 255;
} | .text
.file "kernel.hip"
.globl _Z21__device_stub__kernelPhi # -- Begin function _Z21__device_stub__kernelPhi
.p2align 4, 0x90
.type _Z21__device_stub__kernelPhi,@function
_Z21__device_stub__kernelPhi: # @_Z21__device_stub__kernelPhi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelPhi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPhi, .Lfunc_end0-_Z21__device_stub__kernelPhi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPhi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPhi,@object # @_Z6kernelPhi
.section .rodata,"a",@progbits
.globl _Z6kernelPhi
.p2align 3, 0x0
_Z6kernelPhi:
.quad _Z21__device_stub__kernelPhi
.size _Z6kernelPhi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelPhi"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPhi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPhi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00148390_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z6kernelPhiPhi
.type _Z26__device_stub__Z6kernelPhiPhi, @function
_Z26__device_stub__Z6kernelPhiPhi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPhi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z6kernelPhiPhi, .-_Z26__device_stub__Z6kernelPhiPhi
.globl _Z6kernelPhi
.type _Z6kernelPhi, @function
_Z6kernelPhi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6kernelPhiPhi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6kernelPhi, .-_Z6kernelPhi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kernelPhi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPhi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z21__device_stub__kernelPhi # -- Begin function _Z21__device_stub__kernelPhi
.p2align 4, 0x90
.type _Z21__device_stub__kernelPhi,@function
_Z21__device_stub__kernelPhi: # @_Z21__device_stub__kernelPhi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelPhi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPhi, .Lfunc_end0-_Z21__device_stub__kernelPhi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPhi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPhi,@object # @_Z6kernelPhi
.section .rodata,"a",@progbits
.globl _Z6kernelPhi
.p2align 3, 0x0
_Z6kernelPhi:
.quad _Z21__device_stub__kernelPhi
.size _Z6kernelPhi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelPhi"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPhi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPhi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
This is a basic code to compare between Host Code(CPU) and Device Code(GPU)
*/
#include<stdio.h>
__global__ void mykernel(void){}
int main(void)
{
mykernel<<<1,1>>>(); // Kernel Launch
printf("Hello World \n");
return 0;
} | code for sm_80
Function : _Z8mykernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
This is a basic code to compare between Host Code(CPU) and Device Code(GPU)
*/
#include<stdio.h>
__global__ void mykernel(void){}
int main(void)
{
mykernel<<<1,1>>>(); // Kernel Launch
printf("Hello World \n");
return 0;
} | .file "tmpxft_00036d2d_00000000-6_Basic_Cuda_Device.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z8mykernelvv
.type _Z26__device_stub__Z8mykernelvv, @function
_Z26__device_stub__Z8mykernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z8mykernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z8mykernelvv, .-_Z26__device_stub__Z8mykernelvv
.globl _Z8mykernelv
.type _Z8mykernelv, @function
_Z8mykernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z8mykernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8mykernelv, .-_Z8mykernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello World \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z26__device_stub__Z8mykernelvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z8mykernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z8mykernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
This is a basic code to compare between Host Code(CPU) and Device Code(GPU)
*/
#include<stdio.h>
__global__ void mykernel(void){}
int main(void)
{
mykernel<<<1,1>>>(); // Kernel Launch
printf("Hello World \n");
return 0;
} | /*
This is a basic code to compare between Host Code(CPU) and Device Code(GPU)
*/
#include <hip/hip_runtime.h>
#include<stdio.h>
__global__ void mykernel(void){}
int main(void)
{
mykernel<<<1,1>>>(); // Kernel Launch
printf("Hello World \n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
This is a basic code to compare between Host Code(CPU) and Device Code(GPU)
*/
#include <hip/hip_runtime.h>
#include<stdio.h>
__global__ void mykernel(void){}
int main(void)
{
mykernel<<<1,1>>>(); // Kernel Launch
printf("Hello World \n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8mykernelv
.globl _Z8mykernelv
.p2align 8
.type _Z8mykernelv,@function
_Z8mykernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8mykernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8mykernelv, .Lfunc_end0-_Z8mykernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8mykernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z8mykernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
This is a basic code to compare between Host Code(CPU) and Device Code(GPU)
*/
#include <hip/hip_runtime.h>
#include<stdio.h>
__global__ void mykernel(void){}
int main(void)
{
mykernel<<<1,1>>>(); // Kernel Launch
printf("Hello World \n");
return 0;
} | .text
.file "Basic_Cuda_Device.hip"
.globl _Z23__device_stub__mykernelv # -- Begin function _Z23__device_stub__mykernelv
.p2align 4, 0x90
.type _Z23__device_stub__mykernelv,@function
_Z23__device_stub__mykernelv: # @_Z23__device_stub__mykernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8mykernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z23__device_stub__mykernelv, .Lfunc_end0-_Z23__device_stub__mykernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8mykernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8mykernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8mykernelv,@object # @_Z8mykernelv
.section .rodata,"a",@progbits
.globl _Z8mykernelv
.p2align 3, 0x0
_Z8mykernelv:
.quad _Z23__device_stub__mykernelv
.size _Z8mykernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8mykernelv"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello World "
.size .Lstr, 13
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__mykernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8mykernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8mykernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8mykernelv
.globl _Z8mykernelv
.p2align 8
.type _Z8mykernelv,@function
_Z8mykernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8mykernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8mykernelv, .Lfunc_end0-_Z8mykernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8mykernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z8mykernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00036d2d_00000000-6_Basic_Cuda_Device.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z8mykernelvv
.type _Z26__device_stub__Z8mykernelvv, @function
_Z26__device_stub__Z8mykernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z8mykernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z8mykernelvv, .-_Z26__device_stub__Z8mykernelvv
.globl _Z8mykernelv
.type _Z8mykernelv, @function
_Z8mykernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z8mykernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8mykernelv, .-_Z8mykernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello World \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z26__device_stub__Z8mykernelvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z8mykernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z8mykernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Basic_Cuda_Device.hip"
.globl _Z23__device_stub__mykernelv # -- Begin function _Z23__device_stub__mykernelv
.p2align 4, 0x90
.type _Z23__device_stub__mykernelv,@function
_Z23__device_stub__mykernelv: # @_Z23__device_stub__mykernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8mykernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z23__device_stub__mykernelv, .Lfunc_end0-_Z23__device_stub__mykernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8mykernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8mykernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8mykernelv,@object # @_Z8mykernelv
.section .rodata,"a",@progbits
.globl _Z8mykernelv
.p2align 3, 0x0
_Z8mykernelv:
.quad _Z23__device_stub__mykernelv
.size _Z8mykernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8mykernelv"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello World "
.size .Lstr, 13
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__mykernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8mykernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cstdlib>
#include <sys/time.h>
#include <math.h>
#include <stdio.h>
#include <assert.h>
void writeBMP(const int x, const int y, const unsigned char* const bmp, const char* const name) {
const unsigned char bmphdr[54] = {66, 77, 255, 255, 255, 255, 0, 0, 0, 0, 54, 4, 0, 0, 40, 0, 0, 0, 255, 255, 255, 255, 255, 255, 255, 255, 1, 0, 8, 0, 0, 0, 0, 0, 255, 255, 255, 255, 196, 14, 0, 0, 196, 14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
unsigned char hdr[1078];
int i, j, c, xcorr, diff;
FILE* f;
xcorr = (x + 3) >> 2 << 2; // BMPs have to be a multiple of 4 pixels wide
diff = xcorr - x;
for (i = 0; i < 54; i++) hdr[i] = bmphdr[i];
*((int*)(&hdr[18])) = xcorr;
*((int*)(&hdr[22])) = y;
*((int*)(&hdr[34])) = xcorr * y;
*((int*)(&hdr[2])) = xcorr * y + 1078;
for (i = 0; i < 256; i++) {
j = i * 4 + 54;
hdr[j+0] = i; // blue ColorTable
hdr[j+1] = 0; // green
hdr[j+2] = 0; // red
hdr[j+3] = 0; // dummy
}
f = fopen(name, "wb"); assert(f != NULL);
c = fwrite(hdr, 1, 1078, f); assert(c == 1078);
if (diff == 0) {
c = fwrite(bmp, 1, x * y, f); assert(c == x * y);
} else {
*((int*)(&hdr[0])) = 0; // need up to three zero bytes
for (j = 0; j < y; j++) {
c = fwrite(&bmp[j * x], 1, x, f); assert(c == x);
c = fwrite(hdr, 1, diff, f); assert(c == diff);
}
}
fclose(f);
}
__global__ void buildPicture(int frames, unsigned char *pic) {
int row = blockIdx.x;
int col = threadIdx.x;
int width = blockDim.x;
for (int frame = 0; frame < frames; frame++) {
float fx = col - 1024 / 2;
float fy = row - 1024 / 2;
float d = sqrtf(fx * fx + fy * fy);
unsigned char color = (unsigned char)(160.0f + 127.0f *
cos(d / 10.0f - frame / 7.0f) /
(d / 50.0f + 1.0f));
pic[frame * width * width + row * width + col] = (unsigned char)color;
}
}
int main(int argc, char *argv[]) {
// check command line
if (argc != 3) {
fprintf(stderr, "usage: %s frame_width num_frames\n", argv[0]);
exit(-1);
}
int width = atoi(argv[1]);
if (width < 100) {
fprintf(stderr, "error: frame_width must be at least 100\n");
exit(-1);
}
int frames = atoi(argv[2]);
if (frames < 1) {
fprintf(stderr, "error: num_frames must be at least 1\n");
exit(-1);
}
printf("computing %d frames of %d by %d picture\n", frames, width, width);
// allocate picture array
int N = frames * width * width;
unsigned char *pic = new unsigned char[N];
cudaMallocManaged(&pic, N*sizeof(unsigned char));
// static value for blockSize, so we avoid problems if the width gets high
int blockSize = 128;
/**
* each line has (width / blockSize) blocks. We have 'width' lines. So,
* the total number of blocks is given by: width * (width / blockSize)
*/
int numBlocks = width * (width / blockSize);
buildPicture<<<numBlocks, blockSize>>>(frames, pic);
// Wait for GPU to finish before accessing on host
cudaDeviceSynchronize();
// verify result by writing frames to BMP files
if ((width <= 256) & (frames <= 100)) {
for (int frame = 0; frame < frames; frame++) {
char name[32];
sprintf(name, "wave%d.bmp", frame + 1000);
writeBMP(width, width, &pic[frame * width * width], name);
}
}
cudaFree(pic);
return 0;
} | .file "tmpxft_001872e6_00000000-6_wavecuda1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "wb"
.text
.globl _Z8writeBMPiiPKhPKc
.type _Z8writeBMPiiPKhPKc, @function
_Z8writeBMPiiPKhPKc:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1160, %rsp
.cfi_def_cfa_offset 1216
movl %edi, %r15d
movl %esi, %r12d
movq %rdx, %rbx
movq %rcx, %rdi
movq %fs:40, %rax
movq %rax, 1144(%rsp)
xorl %eax, %eax
movabsq $281474976664898, %rax
movabsq $11258999139074048, %rdx
movq %rax, (%rsp)
movq %rdx, 8(%rsp)
movq $-65536, %rax
movabsq $34359869439, %rdx
movq %rax, 16(%rsp)
movq %rdx, 24(%rsp)
movabsq $1064256886942924800, %rax
movl $247726080, %edx
movq %rax, 32(%rsp)
movq %rdx, 40(%rsp)
movq $0, 46(%rsp)
leal 3(%r15), %ecx
andl $-4, %ecx
movl %ecx, %r13d
subl %r15d, %r13d
movl $0, %eax
.L4:
movzbl (%rsp,%rax), %edx
movb %dl, 64(%rsp,%rax)
addq $1, %rax
cmpq $54, %rax
jne .L4
movl %ecx, 82(%rsp)
movl %r12d, 86(%rsp)
imull %r12d, %ecx
movl %ecx, 98(%rsp)
addl $1078, %ecx
movl %ecx, 66(%rsp)
leaq 118(%rsp), %rax
movl $0, %edx
.L5:
movb %dl, (%rax)
movb $0, 1(%rax)
movb $0, 2(%rax)
movb $0, 3(%rax)
addl $1, %edx
addq $4, %rax
cmpl $256, %edx
jne .L5
leaq .LC0(%rip), %rsi
call fopen@PLT
movq %rax, %r14
leaq 64(%rsp), %rdi
movq %rax, %rcx
movl $1078, %edx
movl $1, %esi
call fwrite@PLT
testl %r13d, %r13d
je .L14
movl $0, 64(%rsp)
testl %r12d, %r12d
jle .L7
movslq %r15d, %r15
movl $0, %ebp
movslq %r13d, %r13
.L8:
movq %r14, %rcx
movq %r15, %rdx
movl $1, %esi
movq %rbx, %rdi
call fwrite@PLT
leaq 64(%rsp), %rdi
movq %r14, %rcx
movq %r13, %rdx
movl $1, %esi
call fwrite@PLT
addl $1, %ebp
addq %r15, %rbx
cmpl %ebp, %r12d
jne .L8
.L7:
movq %r14, %rdi
call fclose@PLT
movq 1144(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $1160, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
imull %r15d, %r12d
movslq %r12d, %rdx
movq %r14, %rcx
movl $1, %esi
movq %rbx, %rdi
call fwrite@PLT
jmp .L7
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z8writeBMPiiPKhPKc, .-_Z8writeBMPiiPKhPKc
.globl _Z33__device_stub__Z12buildPictureiPhiPh
.type _Z33__device_stub__Z12buildPictureiPhiPh, @function
_Z33__device_stub__Z12buildPictureiPhiPh:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12buildPictureiPh(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z33__device_stub__Z12buildPictureiPhiPh, .-_Z33__device_stub__Z12buildPictureiPhiPh
.globl _Z12buildPictureiPh
.type _Z12buildPictureiPh, @function
_Z12buildPictureiPh:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z12buildPictureiPhiPh
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z12buildPictureiPh, .-_Z12buildPictureiPh
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "usage: %s frame_width num_frames\n"
.align 8
.LC2:
.string "error: frame_width must be at least 100\n"
.align 8
.LC3:
.string "error: num_frames must be at least 1\n"
.align 8
.LC4:
.string "computing %d frames of %d by %d picture\n"
.section .rodata.str1.1
.LC5:
.string "wave%d.bmp"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
cmpl $3, %edi
jne .L34
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, %r15d
cmpl $99, %eax
jle .L35
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
testl %eax, %eax
jle .L36
movl %ebx, %r8d
movl %ebx, %ecx
movl %eax, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r14d, %r12d
imull %ebx, %r12d
imull %ebx, %r12d
movslq %r12d, %r12
movq %r12, %rdi
call _Znam@PLT
movq %rax, (%rsp)
movq %rsp, %rdi
movl $1, %edx
movq %r12, %rsi
call cudaMallocManaged@PLT
movl $128, 20(%rsp)
movl $1, 24(%rsp)
leal 127(%rbx), %eax
testl %ebx, %ebx
cmovns %ebx, %eax
sarl $7, %eax
imull %ebx, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L28:
call cudaDeviceSynchronize@PLT
cmpl $256, %ebx
jg .L29
cmpl $100, %r14d
jg .L29
imull %ebx, %ebx
movslq %ebx, %rbx
addl $1000, %r14d
movl $0, %r12d
movl $1000, %ebp
.L30:
leaq 32(%rsp), %r13
movl %ebp, %r8d
leaq .LC5(%rip), %rcx
movl $32, %edx
movl $2, %esi
movq %r13, %rdi
movl $0, %eax
call __sprintf_chk@PLT
movq %r12, %rdx
addq (%rsp), %rdx
movq %r13, %rcx
movl %r15d, %esi
movl %r15d, %edi
call _Z8writeBMPiiPKhPKc
addl $1, %ebp
addq %rbx, %r12
cmpl %r14d, %ebp
jne .L30
.L29:
movq (%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L38
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movq (%rsi), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L35:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L36:
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L37:
movq (%rsp), %rsi
movl %r14d, %edi
call _Z33__device_stub__Z12buildPictureiPhiPh
jmp .L28
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z12buildPictureiPh"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z12buildPictureiPh(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cstdlib>
#include <sys/time.h>
#include <math.h>
#include <stdio.h>
#include <assert.h>
void writeBMP(const int x, const int y, const unsigned char* const bmp, const char* const name) {
const unsigned char bmphdr[54] = {66, 77, 255, 255, 255, 255, 0, 0, 0, 0, 54, 4, 0, 0, 40, 0, 0, 0, 255, 255, 255, 255, 255, 255, 255, 255, 1, 0, 8, 0, 0, 0, 0, 0, 255, 255, 255, 255, 196, 14, 0, 0, 196, 14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
unsigned char hdr[1078];
int i, j, c, xcorr, diff;
FILE* f;
xcorr = (x + 3) >> 2 << 2; // BMPs have to be a multiple of 4 pixels wide
diff = xcorr - x;
for (i = 0; i < 54; i++) hdr[i] = bmphdr[i];
*((int*)(&hdr[18])) = xcorr;
*((int*)(&hdr[22])) = y;
*((int*)(&hdr[34])) = xcorr * y;
*((int*)(&hdr[2])) = xcorr * y + 1078;
for (i = 0; i < 256; i++) {
j = i * 4 + 54;
hdr[j+0] = i; // blue ColorTable
hdr[j+1] = 0; // green
hdr[j+2] = 0; // red
hdr[j+3] = 0; // dummy
}
f = fopen(name, "wb"); assert(f != NULL);
c = fwrite(hdr, 1, 1078, f); assert(c == 1078);
if (diff == 0) {
c = fwrite(bmp, 1, x * y, f); assert(c == x * y);
} else {
*((int*)(&hdr[0])) = 0; // need up to three zero bytes
for (j = 0; j < y; j++) {
c = fwrite(&bmp[j * x], 1, x, f); assert(c == x);
c = fwrite(hdr, 1, diff, f); assert(c == diff);
}
}
fclose(f);
}
__global__ void buildPicture(int frames, unsigned char *pic) {
int row = blockIdx.x;
int col = threadIdx.x;
int width = blockDim.x;
for (int frame = 0; frame < frames; frame++) {
float fx = col - 1024 / 2;
float fy = row - 1024 / 2;
float d = sqrtf(fx * fx + fy * fy);
unsigned char color = (unsigned char)(160.0f + 127.0f *
cos(d / 10.0f - frame / 7.0f) /
(d / 50.0f + 1.0f));
pic[frame * width * width + row * width + col] = (unsigned char)color;
}
}
int main(int argc, char *argv[]) {
// check command line
if (argc != 3) {
fprintf(stderr, "usage: %s frame_width num_frames\n", argv[0]);
exit(-1);
}
int width = atoi(argv[1]);
if (width < 100) {
fprintf(stderr, "error: frame_width must be at least 100\n");
exit(-1);
}
int frames = atoi(argv[2]);
if (frames < 1) {
fprintf(stderr, "error: num_frames must be at least 1\n");
exit(-1);
}
printf("computing %d frames of %d by %d picture\n", frames, width, width);
// allocate picture array
int N = frames * width * width;
unsigned char *pic = new unsigned char[N];
cudaMallocManaged(&pic, N*sizeof(unsigned char));
// static value for blockSize, so we avoid problems if the width gets high
int blockSize = 128;
/**
* each line has (width / blockSize) blocks. We have 'width' lines. So,
* the total number of blocks is given by: width * (width / blockSize)
*/
int numBlocks = width * (width / blockSize);
buildPicture<<<numBlocks, blockSize>>>(frames, pic);
// Wait for GPU to finish before accessing on host
cudaDeviceSynchronize();
// verify result by writing frames to BMP files
if ((width <= 256) & (frames <= 100)) {
for (int frame = 0; frame < frames; frame++) {
char name[32];
sprintf(name, "wave%d.bmp", frame + 1000);
writeBMP(width, width, &pic[frame * width * width], name);
}
}
cudaFree(pic);
return 0;
} | #include <hip/hip_runtime.h>
#include <cstdlib>
#include <sys/time.h>
#include <math.h>
#include <stdio.h>
#include <assert.h>
void writeBMP(const int x, const int y, const unsigned char* const bmp, const char* const name) {
const unsigned char bmphdr[54] = {66, 77, 255, 255, 255, 255, 0, 0, 0, 0, 54, 4, 0, 0, 40, 0, 0, 0, 255, 255, 255, 255, 255, 255, 255, 255, 1, 0, 8, 0, 0, 0, 0, 0, 255, 255, 255, 255, 196, 14, 0, 0, 196, 14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
unsigned char hdr[1078];
int i, j, c, xcorr, diff;
FILE* f;
xcorr = (x + 3) >> 2 << 2; // BMPs have to be a multiple of 4 pixels wide
diff = xcorr - x;
for (i = 0; i < 54; i++) hdr[i] = bmphdr[i];
*((int*)(&hdr[18])) = xcorr;
*((int*)(&hdr[22])) = y;
*((int*)(&hdr[34])) = xcorr * y;
*((int*)(&hdr[2])) = xcorr * y + 1078;
for (i = 0; i < 256; i++) {
j = i * 4 + 54;
hdr[j+0] = i; // blue ColorTable
hdr[j+1] = 0; // green
hdr[j+2] = 0; // red
hdr[j+3] = 0; // dummy
}
f = fopen(name, "wb"); assert(f != NULL);
c = fwrite(hdr, 1, 1078, f); assert(c == 1078);
if (diff == 0) {
c = fwrite(bmp, 1, x * y, f); assert(c == x * y);
} else {
*((int*)(&hdr[0])) = 0; // need up to three zero bytes
for (j = 0; j < y; j++) {
c = fwrite(&bmp[j * x], 1, x, f); assert(c == x);
c = fwrite(hdr, 1, diff, f); assert(c == diff);
}
}
fclose(f);
}
__global__ void buildPicture(int frames, unsigned char *pic) {
int row = blockIdx.x;
int col = threadIdx.x;
int width = blockDim.x;
for (int frame = 0; frame < frames; frame++) {
float fx = col - 1024 / 2;
float fy = row - 1024 / 2;
float d = sqrtf(fx * fx + fy * fy);
unsigned char color = (unsigned char)(160.0f + 127.0f *
cos(d / 10.0f - frame / 7.0f) /
(d / 50.0f + 1.0f));
pic[frame * width * width + row * width + col] = (unsigned char)color;
}
}
int main(int argc, char *argv[]) {
// check command line
if (argc != 3) {
fprintf(stderr, "usage: %s frame_width num_frames\n", argv[0]);
exit(-1);
}
int width = atoi(argv[1]);
if (width < 100) {
fprintf(stderr, "error: frame_width must be at least 100\n");
exit(-1);
}
int frames = atoi(argv[2]);
if (frames < 1) {
fprintf(stderr, "error: num_frames must be at least 1\n");
exit(-1);
}
printf("computing %d frames of %d by %d picture\n", frames, width, width);
// allocate picture array
int N = frames * width * width;
unsigned char *pic = new unsigned char[N];
hipMallocManaged(&pic, N*sizeof(unsigned char));
// static value for blockSize, so we avoid problems if the width gets high
int blockSize = 128;
/**
* each line has (width / blockSize) blocks. We have 'width' lines. So,
* the total number of blocks is given by: width * (width / blockSize)
*/
int numBlocks = width * (width / blockSize);
buildPicture<<<numBlocks, blockSize>>>(frames, pic);
// Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
// verify result by writing frames to BMP files
if ((width <= 256) & (frames <= 100)) {
for (int frame = 0; frame < frames; frame++) {
char name[32];
sprintf(name, "wave%d.bmp", frame + 1000);
writeBMP(width, width, &pic[frame * width * width], name);
}
}
hipFree(pic);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cstdlib>
#include <sys/time.h>
#include <math.h>
#include <stdio.h>
#include <assert.h>
void writeBMP(const int x, const int y, const unsigned char* const bmp, const char* const name) {
const unsigned char bmphdr[54] = {66, 77, 255, 255, 255, 255, 0, 0, 0, 0, 54, 4, 0, 0, 40, 0, 0, 0, 255, 255, 255, 255, 255, 255, 255, 255, 1, 0, 8, 0, 0, 0, 0, 0, 255, 255, 255, 255, 196, 14, 0, 0, 196, 14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
unsigned char hdr[1078];
int i, j, c, xcorr, diff;
FILE* f;
xcorr = (x + 3) >> 2 << 2; // BMPs have to be a multiple of 4 pixels wide
diff = xcorr - x;
for (i = 0; i < 54; i++) hdr[i] = bmphdr[i];
*((int*)(&hdr[18])) = xcorr;
*((int*)(&hdr[22])) = y;
*((int*)(&hdr[34])) = xcorr * y;
*((int*)(&hdr[2])) = xcorr * y + 1078;
for (i = 0; i < 256; i++) {
j = i * 4 + 54;
hdr[j+0] = i; // blue ColorTable
hdr[j+1] = 0; // green
hdr[j+2] = 0; // red
hdr[j+3] = 0; // dummy
}
f = fopen(name, "wb"); assert(f != NULL);
c = fwrite(hdr, 1, 1078, f); assert(c == 1078);
if (diff == 0) {
c = fwrite(bmp, 1, x * y, f); assert(c == x * y);
} else {
*((int*)(&hdr[0])) = 0; // need up to three zero bytes
for (j = 0; j < y; j++) {
c = fwrite(&bmp[j * x], 1, x, f); assert(c == x);
c = fwrite(hdr, 1, diff, f); assert(c == diff);
}
}
fclose(f);
}
__global__ void buildPicture(int frames, unsigned char *pic) {
int row = blockIdx.x;
int col = threadIdx.x;
int width = blockDim.x;
for (int frame = 0; frame < frames; frame++) {
float fx = col - 1024 / 2;
float fy = row - 1024 / 2;
float d = sqrtf(fx * fx + fy * fy);
unsigned char color = (unsigned char)(160.0f + 127.0f *
cos(d / 10.0f - frame / 7.0f) /
(d / 50.0f + 1.0f));
pic[frame * width * width + row * width + col] = (unsigned char)color;
}
}
int main(int argc, char *argv[]) {
// check command line
if (argc != 3) {
fprintf(stderr, "usage: %s frame_width num_frames\n", argv[0]);
exit(-1);
}
int width = atoi(argv[1]);
if (width < 100) {
fprintf(stderr, "error: frame_width must be at least 100\n");
exit(-1);
}
int frames = atoi(argv[2]);
if (frames < 1) {
fprintf(stderr, "error: num_frames must be at least 1\n");
exit(-1);
}
printf("computing %d frames of %d by %d picture\n", frames, width, width);
// allocate picture array
int N = frames * width * width;
unsigned char *pic = new unsigned char[N];
hipMallocManaged(&pic, N*sizeof(unsigned char));
// static value for blockSize, so we avoid problems if the width gets high
int blockSize = 128;
/**
* each line has (width / blockSize) blocks. We have 'width' lines. So,
* the total number of blocks is given by: width * (width / blockSize)
*/
int numBlocks = width * (width / blockSize);
buildPicture<<<numBlocks, blockSize>>>(frames, pic);
// Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
// verify result by writing frames to BMP files
if ((width <= 256) & (frames <= 100)) {
for (int frame = 0; frame < frames; frame++) {
char name[32];
sprintf(name, "wave%d.bmp", frame + 1000);
writeBMP(width, width, &pic[frame * width * width], name);
}
}
hipFree(pic);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12buildPictureiPh
.globl _Z12buildPictureiPh
.p2align 8
.type _Z12buildPictureiPh,@function
_Z12buildPictureiPh:
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_7
s_add_i32 s2, s15, 0xfffffe00
s_clause 0x1
s_load_b32 s6, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x8
v_cvt_f32_i32_e32 v2, s2
v_add_nc_u32_e32 v1, 0xfffffe00, v0
s_mov_b32 s7, 0x7fffff
s_mov_b32 s8, 0xb94c1982
s_mov_b32 s9, 0x37d75334
v_mul_f32_e32 v2, v2, v2
v_cvt_f32_i32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v2, v1, v1
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2
v_mul_f32_e32 v1, 0x4f800000, v2
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, v2, v1, vcc_lo
v_sqrt_f32_e32 v2, v1
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v4, 1, v2
v_add_nc_u32_e32 v3, -1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v6, -v4, v2, v1
v_fma_f32 v5, -v3, v2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s2, 0, v5
v_cndmask_b32_e64 v2, v2, v3, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s2, 0, v6
v_cndmask_b32_e64 v2, v2, v4, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v3, 0x37800000, v2
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v1, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v2, v1, vcc_lo
v_div_scale_f32 v1, null, 0x41200000, 0x41200000, v3
v_div_scale_f32 v2, null, 0x42480000, 0x42480000, v3
v_div_scale_f32 v8, vcc_lo, v3, 0x41200000, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v4, v1
v_rcp_f32_e32 v5, v2
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v1, v4, 1.0
v_fma_f32 v7, -v2, v5, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v4, v6, v4
v_div_scale_f32 v6, s2, v3, 0x42480000, v3
v_fmac_f32_e32 v5, v7, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v7, v8, v4
v_mul_f32_e32 v9, v6, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v10, -v1, v7, v8
v_fma_f32 v11, -v2, v9, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v7, v10, v4
v_fmac_f32_e32 v9, v11, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v1, -v1, v7, v8
v_fma_f32 v2, -v2, v9, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_fmas_f32 v4, v1, v4, v7
s_mov_b32 vcc_lo, s2
s_mov_b32 s2, 0
v_div_fmas_f32 v1, v2, v5, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_div_fixup_f32 v5, v1, 0x42480000, v3
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
v_div_fixup_f32 v0, v4, 0x41200000, v3
s_mul_i32 s6, s6, s6
v_add_f32_e32 v2, 1.0, v5
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_dual_mul_f32 v6, v4, v4 :: v_dual_and_b32 v9, 1, v5
s_add_i32 s2, s2, 1
v_lshlrev_b32_e32 v5, 30, v5
s_cmp_eq_u32 s3, s2
v_fmaak_f32 v7, s8, v6, 0x3c0881c4
v_cmp_eq_u32_e32 vcc_lo, 0, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_and_b32_e32 v5, 0x80000000, v5
v_fmaak_f32 v7, v6, v7, 0xbe2aaa9d
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmaak_f32 v8, s9, v6, 0xbab64f3b :: v_dual_mul_f32 v7, v6, v7
v_fmaak_f32 v8, v6, v8, 0x3d2aabf7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v4, v4, v7
v_fmaak_f32 v8, v6, v8, 0xbf000004
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, v6, v8, 1.0
v_cndmask_b32_e64 v4, -v4, v6, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v3, 0x1f8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v4, v5, v4
v_mul_f32_e32 v4, 0x42fe0000, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, 0x7fc00000, v4, vcc_lo
v_div_scale_f32 v4, null, v2, v2, v3
v_div_scale_f32 v7, vcc_lo, v3, v2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
v_fmac_f32_e32 v5, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v7, v5
v_fma_f32 v8, -v4, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v8, v5
v_fma_f32 v4, -v4, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v4, v4, v5, v6
v_div_fixup_f32 v3, v4, v2, v3
v_ashrrev_i32_e32 v4, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f32_e32 v5, 0x43200000, v3
v_add_co_u32 v3, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_cvt_i32_f32_e32 v5, v5
v_add_nc_u32_e32 v1, s6, v1
global_store_b8 v[3:4], v5, off
s_cbranch_scc1 .LBB0_7
.LBB0_3:
v_cvt_f32_i32_e32 v3, s2
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v4, null, 0xc0e00000, 0xc0e00000, v3
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, v3, 0xc0e00000, v3
v_mul_f32_e32 v7, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v4, v7, v6
v_fmac_f32_e32 v7, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v7, v6
v_div_fmas_f32 v4, v4, v5, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v3, v4, 0xc0e00000, v3
v_add_f32_e32 v3, v0, v3
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ngt_f32_e64 0x48000000, |v3|
s_xor_b32 s10, exec_lo, s1
s_cbranch_execz .LBB0_5
v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v11, 0x7fffffff, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_and_or_b32 v14, v11, s7, 0x800000
v_lshrrev_b32_e32 v11, 23, v11
v_mad_u64_u32 v[4:5], null, v14, 0xfe5163ab, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v12, 0xffffff88, v11
v_cmp_lt_u32_e32 vcc_lo, 63, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[7:8], null, v14, 0x3c439041, v[5:6]
v_cndmask_b32_e64 v13, 0, 0xffffffc0, vcc_lo
v_mov_b32_e32 v5, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v13, v13, v12
v_mad_u64_u32 v[8:9], null, v14, 0xdb629599, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_u32_e64 s0, 31, v13
v_cndmask_b32_e64 v15, 0, 0xffffffe0, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mov_b32 v5, v9 :: v_dual_cndmask_b32 v4, v8, v4
v_add_nc_u32_e32 v15, v15, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[9:10], null, v14, 0xf534ddc0, v[5:6]
v_cmp_lt_u32_e64 s1, 31, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mov_b32_e32 v5, v10
v_cndmask_b32_e32 v7, v9, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[10:11], null, v14, 0xfc2757d1, v[5:6]
v_cndmask_b32_e64 v4, v7, v4, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v5, v11
v_mad_u64_u32 v[11:12], null, v14, 0x4e441529, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v5, v12
v_mad_u64_u32 v[12:13], null, v14, 0xa2f9836e, v[5:6]
v_cndmask_b32_e64 v5, 0, 0xffffffe0, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v6, v11, v9 :: v_dual_add_nc_u32 v5, v5, v15
v_dual_cndmask_b32 v12, v12, v10 :: v_dual_cndmask_b32 v11, v13, v11
v_cndmask_b32_e32 v10, v10, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_u32_e32 vcc_lo, 0, v5
v_cndmask_b32_e64 v9, v12, v6, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v11, v11, v12, s0
v_cndmask_b32_e64 v6, v6, v10, s0
v_sub_nc_u32_e32 v12, 32, v5
v_cndmask_b32_e64 v10, v10, v7, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v11, v11, v9, s1
v_cndmask_b32_e64 v9, v9, v6, s1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v6, v6, v10, s1
v_cndmask_b32_e64 v4, v10, v4, s1
v_alignbit_b32 v13, v11, v9, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_alignbit_b32 v8, v9, v6, v12
v_cndmask_b32_e32 v5, v13, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v11, v6, v4, v12
v_cndmask_b32_e32 v7, v8, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_bfe_u32 v8, v5, 29, 1
v_cndmask_b32_e32 v6, v11, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v9, v5, v7, 30
v_sub_nc_u32_e32 v10, 0, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_alignbit_b32 v7, v7, v6, 30
v_alignbit_b32 v4, v6, v4, 30
v_xor_b32_e32 v9, v9, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v6, v7, v10
v_xor_b32_e32 v4, v4, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_clz_i32_u32_e32 v11, v9
v_min_u32_e32 v11, 32, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v7, 31, v11
v_lshlrev_b32_e32 v13, 23, v11
v_alignbit_b32 v9, v9, v6, v7
v_alignbit_b32 v4, v6, v4, v7
v_lshrrev_b32_e32 v7, 29, v5
v_lshrrev_b32_e32 v5, 30, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v6, v9, v4, 9
v_lshlrev_b32_e32 v7, 31, v7
v_lshrrev_b32_e32 v9, 9, v9
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v5, v8, v5
v_clz_i32_u32_e32 v10, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v12, 0.5, v7
v_min_u32_e32 v10, 32, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v12, v12, v13
v_sub_nc_u32_e32 v14, 31, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v4, v6, v4, v14
v_or_b32_e32 v6, v9, v12
v_add_lshl_u32 v9, v10, v11, 23
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshrrev_b32_e32 v4, 9, v4
v_mul_f32_e32 v10, 0x3fc90fda, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v4, v4, v9
v_fma_f32 v9, v6, 0x3fc90fda, -v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, 0x33000000, v4
v_fmac_f32_e32 v9, 0x33a22168, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v4, v4, v7
v_fmac_f32_e32 v9, 0x3fc90fda, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v4, v10, v9
.LBB0_5:
s_and_not1_saveexec_b32 s0, s10
s_cbranch_execz .LBB0_2
v_mul_f32_e64 v4, 0x3f22f983, |v3|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v5, v4
v_fma_f32 v4, v5, 0xbfc90fda, |v3|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, 0xb3a22168, v5
v_fmac_f32_e32 v4, 0xa7c234c4, v5
v_cvt_i32_f32_e32 v5, v5
s_branch .LBB0_2
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12buildPictureiPh
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12buildPictureiPh, .Lfunc_end0-_Z12buildPictureiPh
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12buildPictureiPh
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12buildPictureiPh.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cstdlib>
#include <sys/time.h>
#include <math.h>
#include <stdio.h>
#include <assert.h>
void writeBMP(const int x, const int y, const unsigned char* const bmp, const char* const name) {
const unsigned char bmphdr[54] = {66, 77, 255, 255, 255, 255, 0, 0, 0, 0, 54, 4, 0, 0, 40, 0, 0, 0, 255, 255, 255, 255, 255, 255, 255, 255, 1, 0, 8, 0, 0, 0, 0, 0, 255, 255, 255, 255, 196, 14, 0, 0, 196, 14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
unsigned char hdr[1078];
int i, j, c, xcorr, diff;
FILE* f;
xcorr = (x + 3) >> 2 << 2; // BMPs have to be a multiple of 4 pixels wide
diff = xcorr - x;
for (i = 0; i < 54; i++) hdr[i] = bmphdr[i];
*((int*)(&hdr[18])) = xcorr;
*((int*)(&hdr[22])) = y;
*((int*)(&hdr[34])) = xcorr * y;
*((int*)(&hdr[2])) = xcorr * y + 1078;
for (i = 0; i < 256; i++) {
j = i * 4 + 54;
hdr[j+0] = i; // blue ColorTable
hdr[j+1] = 0; // green
hdr[j+2] = 0; // red
hdr[j+3] = 0; // dummy
}
f = fopen(name, "wb"); assert(f != NULL);
c = fwrite(hdr, 1, 1078, f); assert(c == 1078);
if (diff == 0) {
c = fwrite(bmp, 1, x * y, f); assert(c == x * y);
} else {
*((int*)(&hdr[0])) = 0; // need up to three zero bytes
for (j = 0; j < y; j++) {
c = fwrite(&bmp[j * x], 1, x, f); assert(c == x);
c = fwrite(hdr, 1, diff, f); assert(c == diff);
}
}
fclose(f);
}
__global__ void buildPicture(int frames, unsigned char *pic) {
int row = blockIdx.x;
int col = threadIdx.x;
int width = blockDim.x;
for (int frame = 0; frame < frames; frame++) {
float fx = col - 1024 / 2;
float fy = row - 1024 / 2;
float d = sqrtf(fx * fx + fy * fy);
unsigned char color = (unsigned char)(160.0f + 127.0f *
cos(d / 10.0f - frame / 7.0f) /
(d / 50.0f + 1.0f));
pic[frame * width * width + row * width + col] = (unsigned char)color;
}
}
int main(int argc, char *argv[]) {
// check command line
if (argc != 3) {
fprintf(stderr, "usage: %s frame_width num_frames\n", argv[0]);
exit(-1);
}
int width = atoi(argv[1]);
if (width < 100) {
fprintf(stderr, "error: frame_width must be at least 100\n");
exit(-1);
}
int frames = atoi(argv[2]);
if (frames < 1) {
fprintf(stderr, "error: num_frames must be at least 1\n");
exit(-1);
}
printf("computing %d frames of %d by %d picture\n", frames, width, width);
// allocate picture array
int N = frames * width * width;
unsigned char *pic = new unsigned char[N];
hipMallocManaged(&pic, N*sizeof(unsigned char));
// static value for blockSize, so we avoid problems if the width gets high
int blockSize = 128;
/**
* each line has (width / blockSize) blocks. We have 'width' lines. So,
* the total number of blocks is given by: width * (width / blockSize)
*/
int numBlocks = width * (width / blockSize);
buildPicture<<<numBlocks, blockSize>>>(frames, pic);
// Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
// verify result by writing frames to BMP files
if ((width <= 256) & (frames <= 100)) {
for (int frame = 0; frame < frames; frame++) {
char name[32];
sprintf(name, "wave%d.bmp", frame + 1000);
writeBMP(width, width, &pic[frame * width * width], name);
}
}
hipFree(pic);
return 0;
} | .text
.file "wavecuda1.hip"
.globl _Z8writeBMPiiPKhPKc # -- Begin function _Z8writeBMPiiPKhPKc
.p2align 4, 0x90
.type _Z8writeBMPiiPKhPKc,@function
_Z8writeBMPiiPKhPKc: # @_Z8writeBMPiiPKhPKc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1080, %rsp # imm = 0x438
.cfi_def_cfa_offset 1136
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %rbx
movl %esi, %ebp
movl %edi, %r14d
leal 3(%r14), %r12d
andl $-4, %r12d
movw $19778, (%rsp) # imm = 0x4D42
movl $4294967295, %eax # imm = 0xFFFFFFFF
movq %rax, 2(%rsp)
movabsq $171798692918, %rax # imm = 0x2800000436
movq %rax, 10(%rsp)
movq $-1, 18(%rsp)
movw $1, 26(%rsp)
movb $8, 28(%rsp)
movl $0, 29(%rsp)
movb $0, 33(%rsp)
movabsq $16239271346175, %rax # imm = 0xEC4FFFFFFFF
movq %rax, 34(%rsp)
movw $3780, 42(%rsp) # imm = 0xEC4
movw $0, 52(%rsp)
movq $0, 44(%rsp)
movl %r12d, 18(%rsp)
movl %esi, 22(%rsp)
movl %r12d, %eax
imull %esi, %eax
movl %eax, 34(%rsp)
addl $1078, %eax # imm = 0x436
movl %eax, 2(%rsp)
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movb %al, 54(%rsp,%rax,4)
movw $0, 55(%rsp,%rax,4)
movb $0, 57(%rsp,%rax,4)
incq %rax
cmpq $256, %rax # imm = 0x100
jne .LBB0_1
# %bb.2:
movl $.L.str, %esi
movq %rcx, %rdi
callq fopen
movq %rax, %r15
movq %rsp, %rdi
movl $1, %esi
movl $1078, %edx # imm = 0x436
movq %rax, %rcx
callq fwrite
subl %r14d, %r12d
jne .LBB0_4
# %bb.3:
imull %r14d, %ebp
movslq %ebp, %rdx
movl $1, %esi
movq %rbx, %rdi
movq %r15, %rcx
callq fwrite
jmp .LBB0_7
.LBB0_4:
movl $0, (%rsp)
testl %ebp, %ebp
jle .LBB0_7
# %bb.5: # %.lr.ph
movslq %r14d, %r14
movslq %r12d, %r12
movl %ebp, %ebp
movq %rsp, %r13
.p2align 4, 0x90
.LBB0_6: # =>This Inner Loop Header: Depth=1
movl $1, %esi
movq %rbx, %rdi
movq %r14, %rdx
movq %r15, %rcx
callq fwrite
movl $1, %esi
movq %r13, %rdi
movq %r12, %rdx
movq %r15, %rcx
callq fwrite
addq %r14, %rbx
decq %rbp
jne .LBB0_6
.LBB0_7: # %.loopexit
movq %r15, %rdi
addq $1080, %rsp # imm = 0x438
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end0:
.size _Z8writeBMPiiPKhPKc, .Lfunc_end0-_Z8writeBMPiiPKhPKc
.cfi_endproc
# -- End function
.globl _Z27__device_stub__buildPictureiPh # -- Begin function _Z27__device_stub__buildPictureiPh
.p2align 4, 0x90
.type _Z27__device_stub__buildPictureiPh,@function
_Z27__device_stub__buildPictureiPh: # @_Z27__device_stub__buildPictureiPh
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12buildPictureiPh, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z27__device_stub__buildPictureiPh, .Lfunc_end1-_Z27__device_stub__buildPictureiPh
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
cmpl $3, %edi
jne .LBB2_13
# %bb.1:
movq 8(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
cmpl $99, %ebx
jle .LBB2_2
# %bb.4:
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
testl %r14d, %r14d
jle .LBB2_5
# %bb.6:
movl $.L.str.4, %edi
movl %r14d, %esi
movl %ebx, %edx
movl %ebx, %ecx
xorl %eax, %eax
callq printf
movl %ebx, %eax
imull %ebx, %eax
movl %r14d, %r15d
imull %eax, %r15d
movq %r15, %rdi
callq _Znam
movq %rax, 8(%rsp)
leaq 8(%rsp), %rdi
movq %r15, %rsi
movl $1, %edx
callq hipMallocManaged
movl %ebx, %edi
shrl $7, %edi
imull %ebx, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $128, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movq 8(%rsp), %rax
movl %r14d, 20(%rsp)
movq %rax, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12buildPictureiPh, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8:
callq hipDeviceSynchronize
cmpl $256, %ebx # imm = 0x100
jg .LBB2_12
# %bb.9:
cmpl $100, %r14d
jg .LBB2_12
# %bb.10: # %.lr.ph
movq %rbx, %r15
imulq %rbx, %r15
cmpl $2, %r14d
movl $1, %r12d
cmovgel %r14d, %r12d
leaq 80(%rsp), %r14
xorl %r13d, %r13d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_11: # =>This Inner Loop Header: Depth=1
leal 1000(%rbp), %edx
movl $.L.str.5, %esi
movq %r14, %rdi
xorl %eax, %eax
callq sprintf
movl %r13d, %edx
addq 8(%rsp), %rdx
movl %ebx, %edi
movl %ebx, %esi
movq %r14, %rcx
callq _Z8writeBMPiiPKhPKc
incq %rbp
addq %r15, %r13
cmpq %rbp, %r12
jne .LBB2_11
.LBB2_12: # %.loopexit
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_13:
.cfi_def_cfa_offset 176
movq stderr(%rip), %rdi
movq (%r14), %rdx
movl $.L.str.1, %esi
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.LBB2_2:
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $40, %esi
jmp .LBB2_3
.LBB2_5:
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $37, %esi
.LBB2_3:
movl $1, %edx
callq fwrite
movl $-1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12buildPictureiPh, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "wb"
.size .L.str, 3
.type _Z12buildPictureiPh,@object # @_Z12buildPictureiPh
.section .rodata,"a",@progbits
.globl _Z12buildPictureiPh
.p2align 3, 0x0
_Z12buildPictureiPh:
.quad _Z27__device_stub__buildPictureiPh
.size _Z12buildPictureiPh, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "usage: %s frame_width num_frames\n"
.size .L.str.1, 34
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "error: frame_width must be at least 100\n"
.size .L.str.2, 41
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "error: num_frames must be at least 1\n"
.size .L.str.3, 38
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "computing %d frames of %d by %d picture\n"
.size .L.str.4, 41
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "wave%d.bmp"
.size .L.str.5, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12buildPictureiPh"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__buildPictureiPh
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12buildPictureiPh
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001872e6_00000000-6_wavecuda1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "wb"
.text
.globl _Z8writeBMPiiPKhPKc
.type _Z8writeBMPiiPKhPKc, @function
_Z8writeBMPiiPKhPKc:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1160, %rsp
.cfi_def_cfa_offset 1216
movl %edi, %r15d
movl %esi, %r12d
movq %rdx, %rbx
movq %rcx, %rdi
movq %fs:40, %rax
movq %rax, 1144(%rsp)
xorl %eax, %eax
movabsq $281474976664898, %rax
movabsq $11258999139074048, %rdx
movq %rax, (%rsp)
movq %rdx, 8(%rsp)
movq $-65536, %rax
movabsq $34359869439, %rdx
movq %rax, 16(%rsp)
movq %rdx, 24(%rsp)
movabsq $1064256886942924800, %rax
movl $247726080, %edx
movq %rax, 32(%rsp)
movq %rdx, 40(%rsp)
movq $0, 46(%rsp)
leal 3(%r15), %ecx
andl $-4, %ecx
movl %ecx, %r13d
subl %r15d, %r13d
movl $0, %eax
.L4:
movzbl (%rsp,%rax), %edx
movb %dl, 64(%rsp,%rax)
addq $1, %rax
cmpq $54, %rax
jne .L4
movl %ecx, 82(%rsp)
movl %r12d, 86(%rsp)
imull %r12d, %ecx
movl %ecx, 98(%rsp)
addl $1078, %ecx
movl %ecx, 66(%rsp)
leaq 118(%rsp), %rax
movl $0, %edx
.L5:
movb %dl, (%rax)
movb $0, 1(%rax)
movb $0, 2(%rax)
movb $0, 3(%rax)
addl $1, %edx
addq $4, %rax
cmpl $256, %edx
jne .L5
leaq .LC0(%rip), %rsi
call fopen@PLT
movq %rax, %r14
leaq 64(%rsp), %rdi
movq %rax, %rcx
movl $1078, %edx
movl $1, %esi
call fwrite@PLT
testl %r13d, %r13d
je .L14
movl $0, 64(%rsp)
testl %r12d, %r12d
jle .L7
movslq %r15d, %r15
movl $0, %ebp
movslq %r13d, %r13
.L8:
movq %r14, %rcx
movq %r15, %rdx
movl $1, %esi
movq %rbx, %rdi
call fwrite@PLT
leaq 64(%rsp), %rdi
movq %r14, %rcx
movq %r13, %rdx
movl $1, %esi
call fwrite@PLT
addl $1, %ebp
addq %r15, %rbx
cmpl %ebp, %r12d
jne .L8
.L7:
movq %r14, %rdi
call fclose@PLT
movq 1144(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $1160, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
imull %r15d, %r12d
movslq %r12d, %rdx
movq %r14, %rcx
movl $1, %esi
movq %rbx, %rdi
call fwrite@PLT
jmp .L7
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z8writeBMPiiPKhPKc, .-_Z8writeBMPiiPKhPKc
.globl _Z33__device_stub__Z12buildPictureiPhiPh
.type _Z33__device_stub__Z12buildPictureiPhiPh, @function
_Z33__device_stub__Z12buildPictureiPhiPh:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12buildPictureiPh(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z33__device_stub__Z12buildPictureiPhiPh, .-_Z33__device_stub__Z12buildPictureiPhiPh
.globl _Z12buildPictureiPh
.type _Z12buildPictureiPh, @function
_Z12buildPictureiPh:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z12buildPictureiPhiPh
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z12buildPictureiPh, .-_Z12buildPictureiPh
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "usage: %s frame_width num_frames\n"
.align 8
.LC2:
.string "error: frame_width must be at least 100\n"
.align 8
.LC3:
.string "error: num_frames must be at least 1\n"
.align 8
.LC4:
.string "computing %d frames of %d by %d picture\n"
.section .rodata.str1.1
.LC5:
.string "wave%d.bmp"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
cmpl $3, %edi
jne .L34
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, %r15d
cmpl $99, %eax
jle .L35
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
testl %eax, %eax
jle .L36
movl %ebx, %r8d
movl %ebx, %ecx
movl %eax, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r14d, %r12d
imull %ebx, %r12d
imull %ebx, %r12d
movslq %r12d, %r12
movq %r12, %rdi
call _Znam@PLT
movq %rax, (%rsp)
movq %rsp, %rdi
movl $1, %edx
movq %r12, %rsi
call cudaMallocManaged@PLT
movl $128, 20(%rsp)
movl $1, 24(%rsp)
leal 127(%rbx), %eax
testl %ebx, %ebx
cmovns %ebx, %eax
sarl $7, %eax
imull %ebx, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L28:
call cudaDeviceSynchronize@PLT
cmpl $256, %ebx
jg .L29
cmpl $100, %r14d
jg .L29
imull %ebx, %ebx
movslq %ebx, %rbx
addl $1000, %r14d
movl $0, %r12d
movl $1000, %ebp
.L30:
leaq 32(%rsp), %r13
movl %ebp, %r8d
leaq .LC5(%rip), %rcx
movl $32, %edx
movl $2, %esi
movq %r13, %rdi
movl $0, %eax
call __sprintf_chk@PLT
movq %r12, %rdx
addq (%rsp), %rdx
movq %r13, %rcx
movl %r15d, %esi
movl %r15d, %edi
call _Z8writeBMPiiPKhPKc
addl $1, %ebp
addq %rbx, %r12
cmpl %r14d, %ebp
jne .L30
.L29:
movq (%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L38
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movq (%rsi), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L35:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L36:
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L37:
movq (%rsp), %rsi
movl %r14d, %edi
call _Z33__device_stub__Z12buildPictureiPhiPh
jmp .L28
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z12buildPictureiPh"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z12buildPictureiPh(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "wavecuda1.hip"
.globl _Z8writeBMPiiPKhPKc # -- Begin function _Z8writeBMPiiPKhPKc
.p2align 4, 0x90
.type _Z8writeBMPiiPKhPKc,@function
_Z8writeBMPiiPKhPKc: # @_Z8writeBMPiiPKhPKc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1080, %rsp # imm = 0x438
.cfi_def_cfa_offset 1136
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %rbx
movl %esi, %ebp
movl %edi, %r14d
leal 3(%r14), %r12d
andl $-4, %r12d
movw $19778, (%rsp) # imm = 0x4D42
movl $4294967295, %eax # imm = 0xFFFFFFFF
movq %rax, 2(%rsp)
movabsq $171798692918, %rax # imm = 0x2800000436
movq %rax, 10(%rsp)
movq $-1, 18(%rsp)
movw $1, 26(%rsp)
movb $8, 28(%rsp)
movl $0, 29(%rsp)
movb $0, 33(%rsp)
movabsq $16239271346175, %rax # imm = 0xEC4FFFFFFFF
movq %rax, 34(%rsp)
movw $3780, 42(%rsp) # imm = 0xEC4
movw $0, 52(%rsp)
movq $0, 44(%rsp)
movl %r12d, 18(%rsp)
movl %esi, 22(%rsp)
movl %r12d, %eax
imull %esi, %eax
movl %eax, 34(%rsp)
addl $1078, %eax # imm = 0x436
movl %eax, 2(%rsp)
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movb %al, 54(%rsp,%rax,4)
movw $0, 55(%rsp,%rax,4)
movb $0, 57(%rsp,%rax,4)
incq %rax
cmpq $256, %rax # imm = 0x100
jne .LBB0_1
# %bb.2:
movl $.L.str, %esi
movq %rcx, %rdi
callq fopen
movq %rax, %r15
movq %rsp, %rdi
movl $1, %esi
movl $1078, %edx # imm = 0x436
movq %rax, %rcx
callq fwrite
subl %r14d, %r12d
jne .LBB0_4
# %bb.3:
imull %r14d, %ebp
movslq %ebp, %rdx
movl $1, %esi
movq %rbx, %rdi
movq %r15, %rcx
callq fwrite
jmp .LBB0_7
.LBB0_4:
movl $0, (%rsp)
testl %ebp, %ebp
jle .LBB0_7
# %bb.5: # %.lr.ph
movslq %r14d, %r14
movslq %r12d, %r12
movl %ebp, %ebp
movq %rsp, %r13
.p2align 4, 0x90
.LBB0_6: # =>This Inner Loop Header: Depth=1
movl $1, %esi
movq %rbx, %rdi
movq %r14, %rdx
movq %r15, %rcx
callq fwrite
movl $1, %esi
movq %r13, %rdi
movq %r12, %rdx
movq %r15, %rcx
callq fwrite
addq %r14, %rbx
decq %rbp
jne .LBB0_6
.LBB0_7: # %.loopexit
movq %r15, %rdi
addq $1080, %rsp # imm = 0x438
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end0:
.size _Z8writeBMPiiPKhPKc, .Lfunc_end0-_Z8writeBMPiiPKhPKc
.cfi_endproc
# -- End function
.globl _Z27__device_stub__buildPictureiPh # -- Begin function _Z27__device_stub__buildPictureiPh
.p2align 4, 0x90
.type _Z27__device_stub__buildPictureiPh,@function
_Z27__device_stub__buildPictureiPh: # @_Z27__device_stub__buildPictureiPh
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12buildPictureiPh, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z27__device_stub__buildPictureiPh, .Lfunc_end1-_Z27__device_stub__buildPictureiPh
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
cmpl $3, %edi
jne .LBB2_13
# %bb.1:
movq 8(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
cmpl $99, %ebx
jle .LBB2_2
# %bb.4:
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
testl %r14d, %r14d
jle .LBB2_5
# %bb.6:
movl $.L.str.4, %edi
movl %r14d, %esi
movl %ebx, %edx
movl %ebx, %ecx
xorl %eax, %eax
callq printf
movl %ebx, %eax
imull %ebx, %eax
movl %r14d, %r15d
imull %eax, %r15d
movq %r15, %rdi
callq _Znam
movq %rax, 8(%rsp)
leaq 8(%rsp), %rdi
movq %r15, %rsi
movl $1, %edx
callq hipMallocManaged
movl %ebx, %edi
shrl $7, %edi
imull %ebx, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $128, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movq 8(%rsp), %rax
movl %r14d, 20(%rsp)
movq %rax, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12buildPictureiPh, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8:
callq hipDeviceSynchronize
cmpl $256, %ebx # imm = 0x100
jg .LBB2_12
# %bb.9:
cmpl $100, %r14d
jg .LBB2_12
# %bb.10: # %.lr.ph
movq %rbx, %r15
imulq %rbx, %r15
cmpl $2, %r14d
movl $1, %r12d
cmovgel %r14d, %r12d
leaq 80(%rsp), %r14
xorl %r13d, %r13d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_11: # =>This Inner Loop Header: Depth=1
leal 1000(%rbp), %edx
movl $.L.str.5, %esi
movq %r14, %rdi
xorl %eax, %eax
callq sprintf
movl %r13d, %edx
addq 8(%rsp), %rdx
movl %ebx, %edi
movl %ebx, %esi
movq %r14, %rcx
callq _Z8writeBMPiiPKhPKc
incq %rbp
addq %r15, %r13
cmpq %rbp, %r12
jne .LBB2_11
.LBB2_12: # %.loopexit
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_13:
.cfi_def_cfa_offset 176
movq stderr(%rip), %rdi
movq (%r14), %rdx
movl $.L.str.1, %esi
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.LBB2_2:
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $40, %esi
jmp .LBB2_3
.LBB2_5:
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $37, %esi
.LBB2_3:
movl $1, %edx
callq fwrite
movl $-1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12buildPictureiPh, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "wb"
.size .L.str, 3
.type _Z12buildPictureiPh,@object # @_Z12buildPictureiPh
.section .rodata,"a",@progbits
.globl _Z12buildPictureiPh
.p2align 3, 0x0
_Z12buildPictureiPh:
.quad _Z27__device_stub__buildPictureiPh
.size _Z12buildPictureiPh, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "usage: %s frame_width num_frames\n"
.size .L.str.1, 34
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "error: frame_width must be at least 100\n"
.size .L.str.2, 41
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "error: num_frames must be at least 1\n"
.size .L.str.3, 38
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "computing %d frames of %d by %d picture\n"
.size .L.str.4, 41
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "wave%d.bmp"
.size .L.str.5, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12buildPictureiPh"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__buildPictureiPh
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12buildPictureiPh
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // We assume row_indices, col_indices, and values are of length count
struct SparseMatrixCOO {
float* values;
int* col_indices;
int* row_indices;
int M;
int N;
int count;
};
// Compared to the sequential SpMV/CSR, the sequential SpMN/COO doesn't waste
// time with fully-zero rows
void SpMV_COO(const SparseMatrixCOO A, const float* x, float* y){
for(int element = 0; element < A.count; ++element){
const int column = A.col_indices[element];
const int row = A.row_indices[element];
y[row] += A.values[element] * x[column];
}
}
__global__ void SpMV_COO_kernel_v1(const SparseMatrixCOO A, const float* x, float* y)
{
for(int element = threadIdx.x + blockIdx.x * blockDim.x;
element < A.count;
element += blockDim.x * gridDim.x){
const int column = A.col_indices[element];
const int row = A.row_indices[element];
// Output interference
y[row] += A.values[element] * x[column];
}
}
// Swithcing to an atomic addition will make the output of this kernel coorect
// It will also serializat a potential large number of writes
// We could solve this using techniques from the histogram pattern(i.e.
// privitization)
// We'll note that this representation is better suited to sequential hardware
// and take a different approach.
__global__ void SpMV_COO_kernel_v2(const SparseMatrixCOO A, const float* x, float* y)
{
for(int element = threadIdx.x + blockIdx.x * blockDim.x;
element < A.count;
element += blockDim.x * gridDim.x){
const int column = A.col_indices[element];
const int row = A.row_indices[element];
atomicAdd(&y[row], A.values[element] * x[column]);
}
} | code for sm_80
Function : _Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R7, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0207 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fc800078e0207 */
/*00b0*/ IMAD.WIDE R8, R0, R7.reuse, c[0x0][0x160] ; /* 0x0000580000087625 */
/* 0x080fe400078e0207 */
/*00c0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee8000c1e1900 */
/*00d0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000f22000c1e1900 */
/*00e0*/ IMAD.WIDE R10, R2, R7, c[0x0][0x188] ; /* 0x00006200020a7625 */
/* 0x004fcc00078e0207 */
/*00f0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f22000c1e1900 */
/*0100*/ MOV R3, c[0x0][0x0] ; /* 0x0000000000037a02 */
/* 0x000fca0000000f00 */
/*0110*/ IMAD R0, R3, c[0x0][0xc], R0 ; /* 0x0000030003007a24 */
/* 0x000fca00078e0200 */
/*0120*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe20003f06270 */
/*0130*/ IMAD.WIDE R6, R4, R7, c[0x0][0x190] ; /* 0x0000640004067625 */
/* 0x008fe200078e0207 */
/*0140*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe60003800000 */
/*0150*/ FMUL R13, R10, R9 ; /* 0x000000090a0d7220 */
/* 0x010fca0000400000 */
/*0160*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R6.64], R13 ; /* 0x0000000d0600798e */
/* 0x0001e6000c10e784 */
/*0170*/ @!P0 BRA 0x70 ; /* 0xfffffef000008947 */
/* 0x000fea000383ffff */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R11, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e020b */
/*0090*/ IMAD.WIDE R4, R0.reuse, R11.reuse, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x0c0fe400078e020b */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R0, R11, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fcc00078e020b */
/*00d0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000f22000c1e1900 */
/*00e0*/ IMAD.WIDE R8, R2, R11, c[0x0][0x188] ; /* 0x0000620002087625 */
/* 0x004fc800078e020b */
/*00f0*/ IMAD.WIDE R10, R4, R11, c[0x0][0x190] ; /* 0x00006400040a7625 */
/* 0x008fe400078e020b */
/*0100*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000f28000c1e1900 */
/*0110*/ LDG.E R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x000f22000c1e1900 */
/*0120*/ MOV R15, c[0x0][0x0] ; /* 0x00000000000f7a02 */
/* 0x000fca0000000f00 */
/*0130*/ IMAD R0, R15, c[0x0][0xc], R0 ; /* 0x000003000f007a24 */
/* 0x000fca00078e0200 */
/*0140*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe20003f06270 */
/*0150*/ FFMA R13, R8, R7, R12 ; /* 0x00000007080d7223 */
/* 0x010fca000000000c */
/*0160*/ STG.E [R10.64], R13 ; /* 0x0000000d0a007986 */
/* 0x0001ee000c101904 */
/*0170*/ @!P0 BRA 0x70 ; /* 0xfffffef000008947 */
/* 0x000fea000383ffff */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // We assume row_indices, col_indices, and values are of length count
struct SparseMatrixCOO {
float* values;
int* col_indices;
int* row_indices;
int M;
int N;
int count;
};
// Compared to the sequential SpMV/CSR, the sequential SpMN/COO doesn't waste
// time with fully-zero rows
void SpMV_COO(const SparseMatrixCOO A, const float* x, float* y){
for(int element = 0; element < A.count; ++element){
const int column = A.col_indices[element];
const int row = A.row_indices[element];
y[row] += A.values[element] * x[column];
}
}
__global__ void SpMV_COO_kernel_v1(const SparseMatrixCOO A, const float* x, float* y)
{
for(int element = threadIdx.x + blockIdx.x * blockDim.x;
element < A.count;
element += blockDim.x * gridDim.x){
const int column = A.col_indices[element];
const int row = A.row_indices[element];
// Output interference
y[row] += A.values[element] * x[column];
}
}
// Swithcing to an atomic addition will make the output of this kernel coorect
// It will also serializat a potential large number of writes
// We could solve this using techniques from the histogram pattern(i.e.
// privitization)
// We'll note that this representation is better suited to sequential hardware
// and take a different approach.
__global__ void SpMV_COO_kernel_v2(const SparseMatrixCOO A, const float* x, float* y)
{
for(int element = threadIdx.x + blockIdx.x * blockDim.x;
element < A.count;
element += blockDim.x * gridDim.x){
const int column = A.col_indices[element];
const int row = A.row_indices[element];
atomicAdd(&y[row], A.values[element] * x[column]);
}
} | .file "tmpxft_000051c0_00000000-6_SpMV_COO.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8SpMV_COO15SparseMatrixCOOPKfPf
.type _Z8SpMV_COO15SparseMatrixCOOPKfPf, @function
_Z8SpMV_COO15SparseMatrixCOOPKfPf:
.LFB2027:
.cfi_startproc
endbr64
movq %rdi, %r8
movl 40(%rsp), %edi
testl %edi, %edi
jle .L3
movq 16(%rsp), %r11
movq 24(%rsp), %r10
movq 8(%rsp), %r9
movslq %edi, %rdi
salq $2, %rdi
movl $0, %eax
.L5:
movslq (%r10,%rax), %rdx
leaq (%rsi,%rdx,4), %rdx
movslq (%r11,%rax), %rcx
movss (%r8,%rcx,4), %xmm0
mulss (%r9,%rax), %xmm0
addss (%rdx), %xmm0
movss %xmm0, (%rdx)
addq $4, %rax
cmpq %rdi, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2027:
.size _Z8SpMV_COO15SparseMatrixCOOPKfPf, .-_Z8SpMV_COO15SparseMatrixCOOPKfPf
.globl _Z58__device_stub__Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPfRK15SparseMatrixCOOPKfPf
.type _Z58__device_stub__Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPfRK15SparseMatrixCOOPKfPf, @function
_Z58__device_stub__Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPfRK15SparseMatrixCOOPKfPf:
.LFB2052:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rsi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq %rdi, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z58__device_stub__Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPfRK15SparseMatrixCOOPKfPf, .-_Z58__device_stub__Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPfRK15SparseMatrixCOOPKfPf
.globl _Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf
.type _Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf, @function
_Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq %rsi, %rdx
movq %rdi, %rsi
leaq 16(%rsp), %rdi
call _Z58__device_stub__Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPfRK15SparseMatrixCOOPKfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf, .-_Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf
.globl _Z58__device_stub__Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPfRK15SparseMatrixCOOPKfPf
.type _Z58__device_stub__Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPfRK15SparseMatrixCOOPKfPf, @function
_Z58__device_stub__Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPfRK15SparseMatrixCOOPKfPf:
.LFB2054:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rsi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq %rdi, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z58__device_stub__Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPfRK15SparseMatrixCOOPKfPf, .-_Z58__device_stub__Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPfRK15SparseMatrixCOOPKfPf
.globl _Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf
.type _Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf, @function
_Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq %rsi, %rdx
movq %rdi, %rsi
leaq 16(%rsp), %rdi
call _Z58__device_stub__Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPfRK15SparseMatrixCOOPKfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf, .-_Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf"
.align 8
.LC1:
.string "_Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // We assume row_indices, col_indices, and values are of length count
struct SparseMatrixCOO {
float* values;
int* col_indices;
int* row_indices;
int M;
int N;
int count;
};
// Compared to the sequential SpMV/CSR, the sequential SpMN/COO doesn't waste
// time with fully-zero rows
void SpMV_COO(const SparseMatrixCOO A, const float* x, float* y){
for(int element = 0; element < A.count; ++element){
const int column = A.col_indices[element];
const int row = A.row_indices[element];
y[row] += A.values[element] * x[column];
}
}
__global__ void SpMV_COO_kernel_v1(const SparseMatrixCOO A, const float* x, float* y)
{
for(int element = threadIdx.x + blockIdx.x * blockDim.x;
element < A.count;
element += blockDim.x * gridDim.x){
const int column = A.col_indices[element];
const int row = A.row_indices[element];
// Output interference
y[row] += A.values[element] * x[column];
}
}
// Swithcing to an atomic addition will make the output of this kernel coorect
// It will also serializat a potential large number of writes
// We could solve this using techniques from the histogram pattern(i.e.
// privitization)
// We'll note that this representation is better suited to sequential hardware
// and take a different approach.
__global__ void SpMV_COO_kernel_v2(const SparseMatrixCOO A, const float* x, float* y)
{
for(int element = threadIdx.x + blockIdx.x * blockDim.x;
element < A.count;
element += blockDim.x * gridDim.x){
const int column = A.col_indices[element];
const int row = A.row_indices[element];
atomicAdd(&y[row], A.values[element] * x[column]);
}
} | #include <hip/hip_runtime.h>
// We assume row_indices, col_indices, and values are of length count
struct SparseMatrixCOO {
float* values;
int* col_indices;
int* row_indices;
int M;
int N;
int count;
};
// Compared to the sequential SpMV/CSR, the sequential SpMN/COO doesn't waste
// time with fully-zero rows
void SpMV_COO(const SparseMatrixCOO A, const float* x, float* y){
for(int element = 0; element < A.count; ++element){
const int column = A.col_indices[element];
const int row = A.row_indices[element];
y[row] += A.values[element] * x[column];
}
}
__global__ void SpMV_COO_kernel_v1(const SparseMatrixCOO A, const float* x, float* y)
{
for(int element = threadIdx.x + blockIdx.x * blockDim.x;
element < A.count;
element += blockDim.x * gridDim.x){
const int column = A.col_indices[element];
const int row = A.row_indices[element];
// Output interference
y[row] += A.values[element] * x[column];
}
}
// Swithcing to an atomic addition will make the output of this kernel coorect
// It will also serializat a potential large number of writes
// We could solve this using techniques from the histogram pattern(i.e.
// privitization)
// We'll note that this representation is better suited to sequential hardware
// and take a different approach.
__global__ void SpMV_COO_kernel_v2(const SparseMatrixCOO A, const float* x, float* y)
{
for(int element = threadIdx.x + blockIdx.x * blockDim.x;
element < A.count;
element += blockDim.x * gridDim.x){
const int column = A.col_indices[element];
const int row = A.row_indices[element];
atomicAdd(&y[row], A.values[element] * x[column]);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
// We assume row_indices, col_indices, and values are of length count
struct SparseMatrixCOO {
float* values;
int* col_indices;
int* row_indices;
int M;
int N;
int count;
};
// Compared to the sequential SpMV/CSR, the sequential SpMN/COO doesn't waste
// time with fully-zero rows
void SpMV_COO(const SparseMatrixCOO A, const float* x, float* y){
for(int element = 0; element < A.count; ++element){
const int column = A.col_indices[element];
const int row = A.row_indices[element];
y[row] += A.values[element] * x[column];
}
}
__global__ void SpMV_COO_kernel_v1(const SparseMatrixCOO A, const float* x, float* y)
{
for(int element = threadIdx.x + blockIdx.x * blockDim.x;
element < A.count;
element += blockDim.x * gridDim.x){
const int column = A.col_indices[element];
const int row = A.row_indices[element];
// Output interference
y[row] += A.values[element] * x[column];
}
}
// Swithcing to an atomic addition will make the output of this kernel coorect
// It will also serializat a potential large number of writes
// We could solve this using techniques from the histogram pattern(i.e.
// privitization)
// We'll note that this representation is better suited to sequential hardware
// and take a different approach.
__global__ void SpMV_COO_kernel_v2(const SparseMatrixCOO A, const float* x, float* y)
{
for(int element = threadIdx.x + blockIdx.x * blockDim.x;
element < A.count;
element += blockDim.x * gridDim.x){
const int column = A.col_indices[element];
const int row = A.row_indices[element];
atomicAdd(&y[row], A.values[element] * x[column]);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf
.globl _Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf
.p2align 8
.type _Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf,@function
_Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x44
s_load_b32 s12, s[0:1], 0x20
s_add_u32 s2, s0, 56
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s13, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s13, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x28
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s13
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v1, s2, v1
v_add_co_u32 v4, vcc_lo, s10, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s8, v2
global_load_b32 v4, v[4:5], off
global_load_b32 v6, v[6:7], off
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_waitcnt vmcnt(1)
v_ashrrev_i32_e32 v5, 31, v4
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v6, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_load_b32 v0, v[2:3], off
global_load_b32 v2, v[4:5], off
global_load_b32 v3, v[6:7], off
v_cmp_le_i32_e32 vcc_lo, s12, v1
s_or_b32 s3, vcc_lo, s3
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, v0, v2
global_store_b32 v[6:7], v3, off
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf, .Lfunc_end0-_Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf
.globl _Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf
.p2align 8
.type _Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf,@function
_Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x44
s_load_b32 s12, s[0:1], 0x20
s_add_u32 s2, s0, 56
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s13, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s13, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB1_5
s_load_b32 s2, s[2:3], 0x0
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x28
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s13
.LBB1_2:
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s13, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s10, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v8, vcc_lo, s8, v2
global_load_b32 v4, v[4:5], off
global_load_b32 v6, v[6:7], off
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v3, vcc_lo
s_waitcnt vmcnt(1)
v_ashrrev_i32_e32 v5, 31, v4
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_lshlrev_b64 v[2:3], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v0, v[8:9], off
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(1)
v_mul_f32_e32 v0, v0, v4
.LBB1_3:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v4, v5, v0
global_atomic_cmpswap_b32 v4, v[2:3], v[4:5], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v4, v5
v_mov_b32_e32 v5, v4
s_or_b32 s13, vcc_lo, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execnz .LBB1_3
s_or_b32 exec_lo, exec_lo, s13
v_add_nc_u32_e32 v1, s2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s12, v1
s_or_b32 s3, vcc_lo, s3
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB1_2
.LBB1_5:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf, .Lfunc_end1-_Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 40
.value_kind: by_value
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 40
.value_kind: by_value
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
// We assume row_indices, col_indices, and values are of length count
struct SparseMatrixCOO {
float* values;
int* col_indices;
int* row_indices;
int M;
int N;
int count;
};
// Compared to the sequential SpMV/CSR, the sequential SpMN/COO doesn't waste
// time with fully-zero rows
void SpMV_COO(const SparseMatrixCOO A, const float* x, float* y){
for(int element = 0; element < A.count; ++element){
const int column = A.col_indices[element];
const int row = A.row_indices[element];
y[row] += A.values[element] * x[column];
}
}
__global__ void SpMV_COO_kernel_v1(const SparseMatrixCOO A, const float* x, float* y)
{
for(int element = threadIdx.x + blockIdx.x * blockDim.x;
element < A.count;
element += blockDim.x * gridDim.x){
const int column = A.col_indices[element];
const int row = A.row_indices[element];
// Output interference
y[row] += A.values[element] * x[column];
}
}
// Swithcing to an atomic addition will make the output of this kernel coorect
// It will also serializat a potential large number of writes
// We could solve this using techniques from the histogram pattern(i.e.
// privitization)
// We'll note that this representation is better suited to sequential hardware
// and take a different approach.
__global__ void SpMV_COO_kernel_v2(const SparseMatrixCOO A, const float* x, float* y)
{
for(int element = threadIdx.x + blockIdx.x * blockDim.x;
element < A.count;
element += blockDim.x * gridDim.x){
const int column = A.col_indices[element];
const int row = A.row_indices[element];
atomicAdd(&y[row], A.values[element] * x[column]);
}
} | .text
.file "SpMV_COO.hip"
.globl _Z8SpMV_COO15SparseMatrixCOOPKfPf # -- Begin function _Z8SpMV_COO15SparseMatrixCOOPKfPf
.p2align 4, 0x90
.type _Z8SpMV_COO15SparseMatrixCOOPKfPf,@function
_Z8SpMV_COO15SparseMatrixCOOPKfPf: # @_Z8SpMV_COO15SparseMatrixCOOPKfPf
.cfi_startproc
# %bb.0:
movl 40(%rsp), %eax
testl %eax, %eax
jle .LBB0_3
# %bb.1: # %.lr.ph
leaq 8(%rsp), %r8
movq (%r8), %rcx
movq 8(%r8), %rdx
movq 16(%r8), %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB0_2: # =>This Inner Loop Header: Depth=1
movslq (%rdx,%r9,4), %r10
movslq (%r8,%r9,4), %r11
movss (%rcx,%r9,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss (%rdi,%r10,4), %xmm0
addss (%rsi,%r11,4), %xmm0
movss %xmm0, (%rsi,%r11,4)
incq %r9
cmpq %r9, %rax
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z8SpMV_COO15SparseMatrixCOOPKfPf, .Lfunc_end0-_Z8SpMV_COO15SparseMatrixCOOPKfPf
.cfi_endproc
# -- End function
.globl _Z33__device_stub__SpMV_COO_kernel_v115SparseMatrixCOOPKfPf # -- Begin function _Z33__device_stub__SpMV_COO_kernel_v115SparseMatrixCOOPKfPf
.p2align 4, 0x90
.type _Z33__device_stub__SpMV_COO_kernel_v115SparseMatrixCOOPKfPf,@function
_Z33__device_stub__SpMV_COO_kernel_v115SparseMatrixCOOPKfPf: # @_Z33__device_stub__SpMV_COO_kernel_v115SparseMatrixCOOPKfPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 96(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 48(%rsp), %rax
movq %rax, 80(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z33__device_stub__SpMV_COO_kernel_v115SparseMatrixCOOPKfPf, .Lfunc_end1-_Z33__device_stub__SpMV_COO_kernel_v115SparseMatrixCOOPKfPf
.cfi_endproc
# -- End function
.globl _Z33__device_stub__SpMV_COO_kernel_v215SparseMatrixCOOPKfPf # -- Begin function _Z33__device_stub__SpMV_COO_kernel_v215SparseMatrixCOOPKfPf
.p2align 4, 0x90
.type _Z33__device_stub__SpMV_COO_kernel_v215SparseMatrixCOOPKfPf,@function
_Z33__device_stub__SpMV_COO_kernel_v215SparseMatrixCOOPKfPf: # @_Z33__device_stub__SpMV_COO_kernel_v215SparseMatrixCOOPKfPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 96(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 48(%rsp), %rax
movq %rax, 80(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z33__device_stub__SpMV_COO_kernel_v215SparseMatrixCOOPKfPf, .Lfunc_end2-_Z33__device_stub__SpMV_COO_kernel_v215SparseMatrixCOOPKfPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf,@object # @_Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf
.section .rodata,"a",@progbits
.globl _Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf
.p2align 3, 0x0
_Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf:
.quad _Z33__device_stub__SpMV_COO_kernel_v115SparseMatrixCOOPKfPf
.size _Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf, 8
.type _Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf,@object # @_Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf
.globl _Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf
.p2align 3, 0x0
_Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf:
.quad _Z33__device_stub__SpMV_COO_kernel_v215SparseMatrixCOOPKfPf
.size _Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf"
.size .L__unnamed_1, 45
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf"
.size .L__unnamed_2, 45
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__SpMV_COO_kernel_v115SparseMatrixCOOPKfPf
.addrsig_sym _Z33__device_stub__SpMV_COO_kernel_v215SparseMatrixCOOPKfPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf
.addrsig_sym _Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R7, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0207 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fc800078e0207 */
/*00b0*/ IMAD.WIDE R8, R0, R7.reuse, c[0x0][0x160] ; /* 0x0000580000087625 */
/* 0x080fe400078e0207 */
/*00c0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee8000c1e1900 */
/*00d0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000f22000c1e1900 */
/*00e0*/ IMAD.WIDE R10, R2, R7, c[0x0][0x188] ; /* 0x00006200020a7625 */
/* 0x004fcc00078e0207 */
/*00f0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f22000c1e1900 */
/*0100*/ MOV R3, c[0x0][0x0] ; /* 0x0000000000037a02 */
/* 0x000fca0000000f00 */
/*0110*/ IMAD R0, R3, c[0x0][0xc], R0 ; /* 0x0000030003007a24 */
/* 0x000fca00078e0200 */
/*0120*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe20003f06270 */
/*0130*/ IMAD.WIDE R6, R4, R7, c[0x0][0x190] ; /* 0x0000640004067625 */
/* 0x008fe200078e0207 */
/*0140*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe60003800000 */
/*0150*/ FMUL R13, R10, R9 ; /* 0x000000090a0d7220 */
/* 0x010fca0000400000 */
/*0160*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R6.64], R13 ; /* 0x0000000d0600798e */
/* 0x0001e6000c10e784 */
/*0170*/ @!P0 BRA 0x70 ; /* 0xfffffef000008947 */
/* 0x000fea000383ffff */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R11, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e020b */
/*0090*/ IMAD.WIDE R4, R0.reuse, R11.reuse, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x0c0fe400078e020b */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R0, R11, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fcc00078e020b */
/*00d0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000f22000c1e1900 */
/*00e0*/ IMAD.WIDE R8, R2, R11, c[0x0][0x188] ; /* 0x0000620002087625 */
/* 0x004fc800078e020b */
/*00f0*/ IMAD.WIDE R10, R4, R11, c[0x0][0x190] ; /* 0x00006400040a7625 */
/* 0x008fe400078e020b */
/*0100*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000f28000c1e1900 */
/*0110*/ LDG.E R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x000f22000c1e1900 */
/*0120*/ MOV R15, c[0x0][0x0] ; /* 0x00000000000f7a02 */
/* 0x000fca0000000f00 */
/*0130*/ IMAD R0, R15, c[0x0][0xc], R0 ; /* 0x000003000f007a24 */
/* 0x000fca00078e0200 */
/*0140*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe20003f06270 */
/*0150*/ FFMA R13, R8, R7, R12 ; /* 0x00000007080d7223 */
/* 0x010fca000000000c */
/*0160*/ STG.E [R10.64], R13 ; /* 0x0000000d0a007986 */
/* 0x0001ee000c101904 */
/*0170*/ @!P0 BRA 0x70 ; /* 0xfffffef000008947 */
/* 0x000fea000383ffff */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf
.globl _Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf
.p2align 8
.type _Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf,@function
_Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x44
s_load_b32 s12, s[0:1], 0x20
s_add_u32 s2, s0, 56
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s13, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s13, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x28
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s13
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v1, s2, v1
v_add_co_u32 v4, vcc_lo, s10, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s8, v2
global_load_b32 v4, v[4:5], off
global_load_b32 v6, v[6:7], off
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_waitcnt vmcnt(1)
v_ashrrev_i32_e32 v5, 31, v4
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v6, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_load_b32 v0, v[2:3], off
global_load_b32 v2, v[4:5], off
global_load_b32 v3, v[6:7], off
v_cmp_le_i32_e32 vcc_lo, s12, v1
s_or_b32 s3, vcc_lo, s3
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, v0, v2
global_store_b32 v[6:7], v3, off
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf, .Lfunc_end0-_Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf
.globl _Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf
.p2align 8
.type _Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf,@function
_Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x44
s_load_b32 s12, s[0:1], 0x20
s_add_u32 s2, s0, 56
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s13, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s13, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB1_5
s_load_b32 s2, s[2:3], 0x0
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x28
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s13
.LBB1_2:
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s13, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s10, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v8, vcc_lo, s8, v2
global_load_b32 v4, v[4:5], off
global_load_b32 v6, v[6:7], off
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v3, vcc_lo
s_waitcnt vmcnt(1)
v_ashrrev_i32_e32 v5, 31, v4
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_lshlrev_b64 v[2:3], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v0, v[8:9], off
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(1)
v_mul_f32_e32 v0, v0, v4
.LBB1_3:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v4, v5, v0
global_atomic_cmpswap_b32 v4, v[2:3], v[4:5], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v4, v5
v_mov_b32_e32 v5, v4
s_or_b32 s13, vcc_lo, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execnz .LBB1_3
s_or_b32 exec_lo, exec_lo, s13
v_add_nc_u32_e32 v1, s2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s12, v1
s_or_b32 s3, vcc_lo, s3
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB1_2
.LBB1_5:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf, .Lfunc_end1-_Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 40
.value_kind: by_value
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 40
.value_kind: by_value
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000051c0_00000000-6_SpMV_COO.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8SpMV_COO15SparseMatrixCOOPKfPf
.type _Z8SpMV_COO15SparseMatrixCOOPKfPf, @function
_Z8SpMV_COO15SparseMatrixCOOPKfPf:
.LFB2027:
.cfi_startproc
endbr64
movq %rdi, %r8
movl 40(%rsp), %edi
testl %edi, %edi
jle .L3
movq 16(%rsp), %r11
movq 24(%rsp), %r10
movq 8(%rsp), %r9
movslq %edi, %rdi
salq $2, %rdi
movl $0, %eax
.L5:
movslq (%r10,%rax), %rdx
leaq (%rsi,%rdx,4), %rdx
movslq (%r11,%rax), %rcx
movss (%r8,%rcx,4), %xmm0
mulss (%r9,%rax), %xmm0
addss (%rdx), %xmm0
movss %xmm0, (%rdx)
addq $4, %rax
cmpq %rdi, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2027:
.size _Z8SpMV_COO15SparseMatrixCOOPKfPf, .-_Z8SpMV_COO15SparseMatrixCOOPKfPf
.globl _Z58__device_stub__Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPfRK15SparseMatrixCOOPKfPf
.type _Z58__device_stub__Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPfRK15SparseMatrixCOOPKfPf, @function
_Z58__device_stub__Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPfRK15SparseMatrixCOOPKfPf:
.LFB2052:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rsi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq %rdi, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z58__device_stub__Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPfRK15SparseMatrixCOOPKfPf, .-_Z58__device_stub__Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPfRK15SparseMatrixCOOPKfPf
.globl _Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf
.type _Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf, @function
_Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq %rsi, %rdx
movq %rdi, %rsi
leaq 16(%rsp), %rdi
call _Z58__device_stub__Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPfRK15SparseMatrixCOOPKfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf, .-_Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf
.globl _Z58__device_stub__Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPfRK15SparseMatrixCOOPKfPf
.type _Z58__device_stub__Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPfRK15SparseMatrixCOOPKfPf, @function
_Z58__device_stub__Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPfRK15SparseMatrixCOOPKfPf:
.LFB2054:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rsi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq %rdi, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z58__device_stub__Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPfRK15SparseMatrixCOOPKfPf, .-_Z58__device_stub__Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPfRK15SparseMatrixCOOPKfPf
.globl _Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf
.type _Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf, @function
_Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq %rsi, %rdx
movq %rdi, %rsi
leaq 16(%rsp), %rdi
call _Z58__device_stub__Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPfRK15SparseMatrixCOOPKfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf, .-_Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf"
.align 8
.LC1:
.string "_Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "SpMV_COO.hip"
.globl _Z8SpMV_COO15SparseMatrixCOOPKfPf # -- Begin function _Z8SpMV_COO15SparseMatrixCOOPKfPf
.p2align 4, 0x90
.type _Z8SpMV_COO15SparseMatrixCOOPKfPf,@function
_Z8SpMV_COO15SparseMatrixCOOPKfPf: # @_Z8SpMV_COO15SparseMatrixCOOPKfPf
.cfi_startproc
# %bb.0:
movl 40(%rsp), %eax
testl %eax, %eax
jle .LBB0_3
# %bb.1: # %.lr.ph
leaq 8(%rsp), %r8
movq (%r8), %rcx
movq 8(%r8), %rdx
movq 16(%r8), %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB0_2: # =>This Inner Loop Header: Depth=1
movslq (%rdx,%r9,4), %r10
movslq (%r8,%r9,4), %r11
movss (%rcx,%r9,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss (%rdi,%r10,4), %xmm0
addss (%rsi,%r11,4), %xmm0
movss %xmm0, (%rsi,%r11,4)
incq %r9
cmpq %r9, %rax
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z8SpMV_COO15SparseMatrixCOOPKfPf, .Lfunc_end0-_Z8SpMV_COO15SparseMatrixCOOPKfPf
.cfi_endproc
# -- End function
.globl _Z33__device_stub__SpMV_COO_kernel_v115SparseMatrixCOOPKfPf # -- Begin function _Z33__device_stub__SpMV_COO_kernel_v115SparseMatrixCOOPKfPf
.p2align 4, 0x90
.type _Z33__device_stub__SpMV_COO_kernel_v115SparseMatrixCOOPKfPf,@function
_Z33__device_stub__SpMV_COO_kernel_v115SparseMatrixCOOPKfPf: # @_Z33__device_stub__SpMV_COO_kernel_v115SparseMatrixCOOPKfPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 96(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 48(%rsp), %rax
movq %rax, 80(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z33__device_stub__SpMV_COO_kernel_v115SparseMatrixCOOPKfPf, .Lfunc_end1-_Z33__device_stub__SpMV_COO_kernel_v115SparseMatrixCOOPKfPf
.cfi_endproc
# -- End function
.globl _Z33__device_stub__SpMV_COO_kernel_v215SparseMatrixCOOPKfPf # -- Begin function _Z33__device_stub__SpMV_COO_kernel_v215SparseMatrixCOOPKfPf
.p2align 4, 0x90
.type _Z33__device_stub__SpMV_COO_kernel_v215SparseMatrixCOOPKfPf,@function
_Z33__device_stub__SpMV_COO_kernel_v215SparseMatrixCOOPKfPf: # @_Z33__device_stub__SpMV_COO_kernel_v215SparseMatrixCOOPKfPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 96(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 48(%rsp), %rax
movq %rax, 80(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z33__device_stub__SpMV_COO_kernel_v215SparseMatrixCOOPKfPf, .Lfunc_end2-_Z33__device_stub__SpMV_COO_kernel_v215SparseMatrixCOOPKfPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf,@object # @_Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf
.section .rodata,"a",@progbits
.globl _Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf
.p2align 3, 0x0
_Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf:
.quad _Z33__device_stub__SpMV_COO_kernel_v115SparseMatrixCOOPKfPf
.size _Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf, 8
.type _Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf,@object # @_Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf
.globl _Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf
.p2align 3, 0x0
_Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf:
.quad _Z33__device_stub__SpMV_COO_kernel_v215SparseMatrixCOOPKfPf
.size _Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf"
.size .L__unnamed_1, 45
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf"
.size .L__unnamed_2, 45
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__SpMV_COO_kernel_v115SparseMatrixCOOPKfPf
.addrsig_sym _Z33__device_stub__SpMV_COO_kernel_v215SparseMatrixCOOPKfPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf
.addrsig_sym _Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // C++ Libraries.
#include <iostream>
// CUDA libraries.
#include <cuda.h>
#include <cuda_runtime.h>
#include "cuComplex.h"
// Define max number of concurrent threads
#define MAX_BLOCKSIZE 512
////////////////////////////////////////////////////////////////////////////////
/// 1. Strided Offset N Search ///
////////////////////////////////////////////////////////////////////////////////
/**
* Searches dev_Array for the given unique value by having each thread search 'offset' number of elements from
* the previous thread's search (strided offset).
* @param dev_Array Array to be searched.
* @param uniqueValue Unique value to be searched for.
* @param offset Number of elements each thread will search, and the separation between each thread's starting index.
* @param arraySize Number of elements in the given array to search.
* @param dev_foundIndex Output index of the found unique value.
*/
__global__ void dev_Strided_Offset_N_Search(int *dev_Array, int uniqueValue, int offset, int arraySize, int *dev_foundIndex){
// Calculate thread id.
int tid = blockDim.x * blockIdx.x + threadIdx.x;
// Initialize currentValue and actualIndex to register memory.
int currentValue, actualIndex;
// Iterate through offset N number of adjacent elements.
for (int N = 0; N < offset; N++){
// Calculate actual array index.
actualIndex = tid * offset + N;
// Ensure thread is not out of bounds.
if ( actualIndex < arraySize ) {
// Retrieve current value from global memory to be checked.
currentValue = dev_Array[actualIndex];
// Check if current value is the unique value.
if ( currentValue == uniqueValue ) {
// Unique value found, store its index in the foundIndex global memory variable.
*dev_foundIndex = actualIndex;
}
}
}
}
/**
* Wrapper function to call the CUDA kernel device function dev_Strided_Offset_N_Search.
* @param dev_Array Array in device memory to be searched.
* @param uniqueValue Unique value to be searched for.
* @param offset Number of elements each thread will search, and the separation between each thread's starting index.
* @param arraySize Number of elements in the given array to search.
* @return Return the index of the unique value.
*/
int Strided_Offset_N_Search(int *dev_Array, int uniqueValue, int offset, int arraySize){
// Initialize foundIndex integer.
int foundIndex = -1;
// Initialize foundIndex device pointer.
int *dev_foundIndex;
// Allocate memory on device for foundIndex.
cudaMalloc((void**)&dev_foundIndex, sizeof(int));
// Copy foundIndex initialized value to device.
cudaMemcpy(dev_foundIndex, &foundIndex, sizeof(int), cudaMemcpyHostToDevice);
// Calculate the number of threads expected.
int numOfThreads = arraySize / offset + 1;
// Initiaize CUDA event timers.
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// Initialize blocksize as the number of threads.
dim3 blockSize(MAX_BLOCKSIZE, 1, 1);
dim3 gridSize(numOfThreads / MAX_BLOCKSIZE + 1, 1);
// Launch device Strided_Offset_N_Search kernel routine and start and stop event timers.
cudaEventRecord(start);
dev_Strided_Offset_N_Search<<<gridSize, blockSize>>>(dev_Array, uniqueValue, offset, arraySize, dev_foundIndex);
cudaEventRecord(stop);
// Retrieve kernel timing.
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
// Print event timing.
std::cout << offset << " " << milliseconds << std::endl;
// Copy d_foundIndex device value back to host memory.
cudaMemcpy(&foundIndex, dev_foundIndex, sizeof(int), cudaMemcpyDeviceToHost);
// Return found index.
return foundIndex;
}
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
/// 2. Coalesced N Element Search ///
////////////////////////////////////////////////////////////////////////////////
/**
* Searches dev_Array for the given unique value by having each thread search adjacent to each other in
* a coalesced fashion, followed by searching adjacent to the other threads again but offset by the total
* number of threads.
* @param dev_Array Array in device memory to be searched.
* @param uniqueValue Unique value to be searched for.
* @param numToCheck Number of elements each thread will check.
* @param numOfThreads Total number of threads searching the array.
* @param arraySize Number of elements in the given array to search.
* @param dev_foundIndex Output index of the found unique value.
*/
__global__ void dev_Coalesced_N_Search(int *dev_Array, int uniqueValue, int numToCheck, int numOfThreads, int arraySize, int *dev_foundIndex){
// Calculate thread id.
int tid = blockDim.x * blockIdx.x + threadIdx.x;
// Initialize currentValue and actualIndex to register memory.
int currentValue, actualIndex;
// Iterate through offset N number of adjacent elements.
for (int N = 0; N < numToCheck; N++){
// Calculate actual array index.
actualIndex = numOfThreads * N + tid;
// Ensure thread is not out of bounds.
if ( actualIndex < arraySize ) {
// Retrieve current value from global memory to be checked.
currentValue = dev_Array[actualIndex];
// Check if current value is the unique value.
if ( currentValue == uniqueValue ) {
// Unique value found, store its index in the foundIndex global memory variable.
*dev_foundIndex = actualIndex;
}
}
}
}
/**
* Wrapper function to call the CUDA kernel device function dev_Coalesced_N_Search.
* @param dev_Array Array in device memory to be searched.
* @param uniqueValue Unique value to be searched for.
* @param numToCheck Number of elements each thread will check.
* @param arraySize Number of elements in the given array to search.
* @return Return the index of the unique value.
*/
int Coalesced_N_Search(int *dev_Array, int uniqueValue, int numToCheck, int arraySize) {
// Initialize foundIndex integer.
int foundIndex = -1;
// Initialize foundIndex device pointer.
int *dev_foundIndex;
// Allocate memory on device for foundIndex.
cudaMalloc((void**)&dev_foundIndex, sizeof(int));
// Copy foundIndex initialized value to device.
cudaMemcpy(dev_foundIndex, &foundIndex, sizeof(int), cudaMemcpyHostToDevice);
// Calculate the number of threads expected.
int numOfThreads = arraySize / numToCheck + 1;
// Initiaize CUDA event timers.
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// Initialize blocksize as the number of threads.
dim3 blockSize(MAX_BLOCKSIZE, 1, 1);
dim3 gridSize(numOfThreads / MAX_BLOCKSIZE + 1, 1);
// Launch device Strided_Offset_N_Search kernel routine and start and stop event timers.
cudaEventRecord(start);
dev_Coalesced_N_Search<<<gridSize, blockSize>>>(dev_Array, uniqueValue, numToCheck, numOfThreads, arraySize, dev_foundIndex);
cudaEventRecord(stop);
// Retrieve kernel timing.
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
// Print event timing.
std::cout << numToCheck << " " << milliseconds << std::endl;
// Copy d_foundIndex device value back to host memory.
cudaMemcpy(&foundIndex, dev_foundIndex, sizeof(int), cudaMemcpyDeviceToHost);
// Return found index.
return foundIndex;
}
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
/// 3. Unrolled Coalesced N Element Search ///
////////////////////////////////////////////////////////////////////////////////
/**
* Searches dev_Array for the given unique value by having each thread search adjacent to each other in
* a coalesced fashion, followed by searching adjacent to the other threads again but offset by the total
* number of threads. All for loops are unrolled with #pragma.
* @param dev_Array Array in device memory to be searched.
* @param uniqueValue Unique value to be searched for.
* @param numToCheck Number of elements each thread will check.
* @param numOfThreads Total number of threads searching the array.
* @param arraySize Number of elements in the given array to search.
* @param dev_foundIndex Output index of the found unique value.
*/
__global__ void dev_Unrolled_Coalesced_N_Search(int *dev_Array, int uniqueValue, int numToCheck, int numOfThreads, int arraySize, int *dev_foundIndex){
// Calculate thread id.
int tid = blockDim.x * blockIdx.x + threadIdx.x;
// Initialize currentValue and actualIndex to register memory.
int currentValue, actualIndex;
// Iterate through offset N number of adjacent elements.
#pragma unroll
for (int N = 0; N < numToCheck; N++){
// Calculate actual array index.
actualIndex = numOfThreads * N + tid;
// Ensure thread is not out of bounds.
if ( actualIndex < arraySize ) {
// Retrieve current value from global memory to be checked.
currentValue = dev_Array[actualIndex];
// Check if current value is the unique value.
if ( currentValue == uniqueValue ) {
// Unique value found, store its index in the foundIndex global memory variable.
*dev_foundIndex = actualIndex;
}
}
}
}
/**
* Wrapper function to call the CUDA kernel device function dev_Coalesced_N_Search.
* @param dev_Array Array in device memory to be searched.
* @param uniqueValue Unique value to be searched for.
* @param numToCheck Number of elements each thread will check.
* @param arraySize Number of elements in the given array to search.
* @return Return the index of the unique value.
*/
int Unrolled_Coalesced_N_Search(int *dev_Array, int uniqueValue, int numToCheck, int arraySize) {
// Initialize foundIndex integer.
int foundIndex = -1;
// Initialize foundIndex device pointer.
int *dev_foundIndex;
// Allocate memory on device for foundIndex.
cudaMalloc((void**)&dev_foundIndex, sizeof(int));
// Copy foundIndex initialized value to device.
cudaMemcpy(dev_foundIndex, &foundIndex, sizeof(int), cudaMemcpyHostToDevice);
// Calculate the number of threads expected.
int numOfThreads = arraySize / numToCheck + 1;
// Initiaize CUDA event timers.
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// Initialize blocksize as the number of threads.
dim3 blockSize(MAX_BLOCKSIZE, 1, 1);
dim3 gridSize(numOfThreads / MAX_BLOCKSIZE + 1, 1);
// Launch device Strided_Offset_N_Search kernel routine and start and stop event timers.
cudaEventRecord(start);
dev_Unrolled_Coalesced_N_Search<<<gridSize, blockSize>>>(dev_Array, uniqueValue, numToCheck, numOfThreads, arraySize, dev_foundIndex);
cudaEventRecord(stop);
// Retrieve kernel timing.
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
// Print event timing.
std::cout << numToCheck << " " << milliseconds << std::endl;
// Copy d_foundIndex device value back to host memory.
cudaMemcpy(&foundIndex, dev_foundIndex, sizeof(int), cudaMemcpyDeviceToHost);
// Return found index.
return foundIndex;
}
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
/// 4. Full Coalesced Element Search ///
////////////////////////////////////////////////////////////////////////////////
/**
* Searches dev_Array for the given unique value by having each thread search adjacent to each other in
* a coalesced fashion.
* @param dev_Array Array in device memory to be searched.
* @param uniqueValue Unique value to be searched for.
* @param arraySize Number of elements in the given array to search.
* @param dev_foundIndex Output index of the found unique value.
*/
__global__ void dev_Full_Coalesced_Search(int *dev_Array, int uniqueValue, int arraySize, int *dev_foundIndex){
// Calculate thread id.
int tid = blockDim.x * blockIdx.x + threadIdx.x;
// Retrieve current value from global memory to be checked.
int currentValue = dev_Array[tid];
// Check if current value is the unique value.
if ( currentValue == uniqueValue ) {
// Unique value found, store its index in the foundIndex global memory variable.
*dev_foundIndex = tid;
}
}
/**
* Wrapper function to call the CUDA kernel device function dev_Coalesced_N_Search.
* @param dev_Array Array in device memory to be searched.
* @param uniqueValue Unique value to be searched for.
* @param arraySize Number of elements in the given array to search.
* @return Return the index of the unique value.
*/
int Full_Coalesced_Search(int *dev_Array, int uniqueValue, int arraySize) {
// Initialize foundIndex integer.
int foundIndex = -1;
// Initialize foundIndex device pointer.
int *dev_foundIndex;
// Allocate memory on device for foundIndex.
cudaMalloc((void**)&dev_foundIndex, sizeof(int));
// Copy foundIndex initialized value to device.
cudaMemcpy(dev_foundIndex, &foundIndex, sizeof(int), cudaMemcpyHostToDevice);
// Calculate the number of threads expected.
int numOfThreads = arraySize;
// Initiaize CUDA event timers.
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// Initialize blocksize as the number of threads.
dim3 blockSize(MAX_BLOCKSIZE, 1, 1);
dim3 gridSize(numOfThreads / MAX_BLOCKSIZE + 1, 1);
// Launch device Strided_Offset_N_Search kernel routine and start and stop event timers.
cudaEventRecord(start);
dev_Full_Coalesced_Search<<<gridSize, blockSize>>>(dev_Array, uniqueValue, arraySize, dev_foundIndex);
cudaEventRecord(stop);
// Retrieve kernel timing.
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
// Print event timing.
std::cout << "1" << " " << milliseconds << std::endl;
// Copy d_foundIndex device value back to host memory.
cudaMemcpy(&foundIndex, dev_foundIndex, sizeof(int), cudaMemcpyDeviceToHost);
// Return found index.
return foundIndex;
}
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
int main(){
// Define unique value to search for.
const int uniqueValue = 5;
// Define random index the unique value will be for constructing the searchable array.
const int randomIndex = 68;
// Define the size of our array.
const int arraySize = 500000;
// Initialize test array that we will search.
int testArray[arraySize];
// Set array to all zeros.
for (int i = 0; i < arraySize; i++){
testArray[i] = 0;
}
// Set random index to value to search for.
testArray[randomIndex] = uniqueValue;
// CUDA ALLOCATIONS //
// Initialize device pointers.
int *d_testArray, d_foundIndex;
// Allocate memory for local variables on the GPU device.
cudaMalloc((void**)&d_testArray, arraySize * sizeof(int));
cudaMalloc((void**)&d_foundIndex, sizeof(int));
// Transfer test array from local host memory to device.
cudaMemcpy(d_testArray, testArray, arraySize * sizeof(int), cudaMemcpyHostToDevice);
// Find unique values //
int foundIndex = -1;
//////////////////////////////////////////////////////////////////////////////////////////////////////
// 1. Each thread searches through N adjacent elements where each thread begins its search N elements
// from the previous thread's starting position. If a thread successfully locates the unique value, it
// write the index of the element to memory.
//////////////////////////////////////////////////////////////////////////////////////////////////////
// Test multiple offset sizes.
std::cout << "-- Strided Offset N Search --" << std::endl;
int offset = 1;
for (int offset = 1; offset < 65; offset+=1) {
foundIndex = Strided_Offset_N_Search(d_testArray, uniqueValue, offset, arraySize);
}
// Print out index of found unique value.
std::cout << "Located unique value at index = " << foundIndex << std::endl;
/////////////////////////////////////////////////////////////////////////////////////////////////////
// 2. Each thread searches through N elements in a coalesced fashion where each thread begins its search
// adjacent to the previous and following threads starting positions. From there, the threads search the
// value which is the total number of threads offset from the current position, so that all threads are
// still making coalesced memory calls.
/////////////////////////////////////////////////////////////////////////////////////////////////////
// Test multiple values of N, where N is the number of elements each thread will check.
std::cout << "-- Coalesced N Search --" << std::endl;
int numToCheck = 1;
for (int numToCheck = 1; numToCheck < 65; numToCheck+=1) {
foundIndex = Coalesced_N_Search(d_testArray, uniqueValue, numToCheck, arraySize);
}
// Print out index of found unique value.
std::cout << "Located unique value at index = " << foundIndex << std::endl;
/////////////////////////////////////////////////////////////////////////////////////////////////////
// 3. Each thread searches through N elements in a coalesced fashion where each thread begins its search
// adjacent to the previous and following threads starting positions. From there, the threads search the
// value which is the total number of threads offset from the current position, so that all threads are
// still making coalesced memory calls. For loop is unroll with #pragma.
/////////////////////////////////////////////////////////////////////////////////////////////////////
// Test multiple values of N, where N is the number of elements each thread will check.
std::cout << "-- Unrolled Coalesced N Search --" << std::endl;
for (int numToCheck = 1; numToCheck < 65; numToCheck+=1) {
foundIndex = Unrolled_Coalesced_N_Search(d_testArray, uniqueValue, 12, arraySize);
}
// Print out index of found unique value.
std::cout << "Located unique value at index = " << foundIndex << std::endl;
///////////////////////////////////////////////////////////////////////////////////////////////////
// 4. Each thread searches a single elements in a coalesced fashion where each thread begins its search
// adjacent to the previous and following threads starting positions.
///////////////////////////////////////////////////////////////////////////////////////////////////
// Test multiple values of N, where N is the number of elements each thread will check.
std::cout << "-- Full Coalesced Search --" << std::endl;
for (int offset = 1; offset < 65; offset+=1) {
foundIndex = Full_Coalesced_Search(d_testArray, uniqueValue, arraySize);
}
// Print out index of found unique value.
std::cout << "Located unique value at index = " << foundIndex << std::endl;
} | .file "tmpxft_0009f198_00000000-6_Test_Search_Unique_Value_CUDA.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z52__device_stub__Z27dev_Strided_Offset_N_SearchPiiiiS_PiiiiS_
.type _Z52__device_stub__Z27dev_Strided_Offset_N_SearchPiiiiS_PiiiiS_, @function
_Z52__device_stub__Z27dev_Strided_Offset_N_SearchPiiiiS_PiiiiS_:
.LFB3721:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z27dev_Strided_Offset_N_SearchPiiiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3721:
.size _Z52__device_stub__Z27dev_Strided_Offset_N_SearchPiiiiS_PiiiiS_, .-_Z52__device_stub__Z27dev_Strided_Offset_N_SearchPiiiiS_PiiiiS_
.globl _Z27dev_Strided_Offset_N_SearchPiiiiS_
.type _Z27dev_Strided_Offset_N_SearchPiiiiS_, @function
_Z27dev_Strided_Offset_N_SearchPiiiiS_:
.LFB3722:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z27dev_Strided_Offset_N_SearchPiiiiS_PiiiiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3722:
.size _Z27dev_Strided_Offset_N_SearchPiiiiS_, .-_Z27dev_Strided_Offset_N_SearchPiiiiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string " "
.text
.globl _Z23Strided_Offset_N_SearchPiiii
.type _Z23Strided_Offset_N_SearchPiiii, @function
_Z23Strided_Offset_N_SearchPiiii:
.LFB3692:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r12
movl %esi, %r13d
movl %edx, %ebx
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $-1, (%rsp)
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movq %rsp, %rsi
movl $1, %ecx
movl $4, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $512, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl %ebp, %eax
cltd
idivl %ebx
leal 512(%rax), %edx
addl $1, %eax
cmovns %eax, %edx
sarl $9, %edx
addl $1, %edx
movl %edx, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L12:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 4(%rsp)
leaq 4(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl %ebx, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $1, %edx
leaq .LC1(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L20
cmpb $0, 56(%rbp)
je .L15
movzbl 67(%rbp), %esi
.L16:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq %rsp, %rdi
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
movl (%rsp), %eax
movq 56(%rsp), %rdx
subq %fs:40, %rdx
jne .L21
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 8(%rsp), %r8
movl %ebp, %ecx
movl %ebx, %edx
movl %r13d, %esi
movq %r12, %rdi
call _Z52__device_stub__Z27dev_Strided_Offset_N_SearchPiiiiS_PiiiiS_
jmp .L12
.L20:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L22
call _ZSt16__throw_bad_castv@PLT
.L22:
call __stack_chk_fail@PLT
.L15:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3692:
.size _Z23Strided_Offset_N_SearchPiiii, .-_Z23Strided_Offset_N_SearchPiiii
.globl _Z48__device_stub__Z22dev_Coalesced_N_SearchPiiiiiS_PiiiiiS_
.type _Z48__device_stub__Z22dev_Coalesced_N_SearchPiiiiiS_PiiiiiS_, @function
_Z48__device_stub__Z22dev_Coalesced_N_SearchPiiiiiS_PiiiiiS_:
.LFB3723:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22dev_Coalesced_N_SearchPiiiiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3723:
.size _Z48__device_stub__Z22dev_Coalesced_N_SearchPiiiiiS_PiiiiiS_, .-_Z48__device_stub__Z22dev_Coalesced_N_SearchPiiiiiS_PiiiiiS_
.globl _Z22dev_Coalesced_N_SearchPiiiiiS_
.type _Z22dev_Coalesced_N_SearchPiiiiiS_, @function
_Z22dev_Coalesced_N_SearchPiiiiiS_:
.LFB3724:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z22dev_Coalesced_N_SearchPiiiiiS_PiiiiiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3724:
.size _Z22dev_Coalesced_N_SearchPiiiiiS_, .-_Z22dev_Coalesced_N_SearchPiiiiiS_
.globl _Z18Coalesced_N_SearchPiiii
.type _Z18Coalesced_N_SearchPiiii, @function
_Z18Coalesced_N_SearchPiiii:
.LFB3693:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r13
movl %esi, %r14d
movl %edx, %ebp
movl %ecx, %r12d
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $-1, (%rsp)
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movq %rsp, %rsi
movl $1, %ecx
movl $4, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %r12d, %eax
cltd
idivl %ebp
movl %eax, %ebx
leal 1(%rax), %r15d
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $512, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
addl $512, %ebx
testl %r15d, %r15d
cmovns %r15d, %ebx
sarl $9, %ebx
addl $1, %ebx
movl %ebx, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L32:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 4(%rsp)
leaq 4(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl %ebp, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $1, %edx
leaq .LC1(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L40
cmpb $0, 56(%rbp)
je .L35
movzbl 67(%rbp), %esi
.L36:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq %rsp, %rdi
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
movl (%rsp), %eax
movq 56(%rsp), %rdx
subq %fs:40, %rdx
jne .L41
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
movq 8(%rsp), %r9
movl %r12d, %r8d
movl %r15d, %ecx
movl %ebp, %edx
movl %r14d, %esi
movq %r13, %rdi
call _Z48__device_stub__Z22dev_Coalesced_N_SearchPiiiiiS_PiiiiiS_
jmp .L32
.L40:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L42
call _ZSt16__throw_bad_castv@PLT
.L42:
call __stack_chk_fail@PLT
.L35:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L36
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3693:
.size _Z18Coalesced_N_SearchPiiii, .-_Z18Coalesced_N_SearchPiiii
.globl _Z57__device_stub__Z31dev_Unrolled_Coalesced_N_SearchPiiiiiS_PiiiiiS_
.type _Z57__device_stub__Z31dev_Unrolled_Coalesced_N_SearchPiiiiiS_PiiiiiS_, @function
_Z57__device_stub__Z31dev_Unrolled_Coalesced_N_SearchPiiiiiS_PiiiiiS_:
.LFB3725:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z31dev_Unrolled_Coalesced_N_SearchPiiiiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3725:
.size _Z57__device_stub__Z31dev_Unrolled_Coalesced_N_SearchPiiiiiS_PiiiiiS_, .-_Z57__device_stub__Z31dev_Unrolled_Coalesced_N_SearchPiiiiiS_PiiiiiS_
.globl _Z31dev_Unrolled_Coalesced_N_SearchPiiiiiS_
.type _Z31dev_Unrolled_Coalesced_N_SearchPiiiiiS_, @function
_Z31dev_Unrolled_Coalesced_N_SearchPiiiiiS_:
.LFB3726:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z57__device_stub__Z31dev_Unrolled_Coalesced_N_SearchPiiiiiS_PiiiiiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3726:
.size _Z31dev_Unrolled_Coalesced_N_SearchPiiiiiS_, .-_Z31dev_Unrolled_Coalesced_N_SearchPiiiiiS_
.globl _Z27Unrolled_Coalesced_N_SearchPiiii
.type _Z27Unrolled_Coalesced_N_SearchPiiii, @function
_Z27Unrolled_Coalesced_N_SearchPiiii:
.LFB3694:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r13
movl %esi, %r14d
movl %edx, %ebp
movl %ecx, %r12d
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $-1, (%rsp)
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movq %rsp, %rsi
movl $1, %ecx
movl $4, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %r12d, %eax
cltd
idivl %ebp
movl %eax, %ebx
leal 1(%rax), %r15d
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $512, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
addl $512, %ebx
testl %r15d, %r15d
cmovns %r15d, %ebx
sarl $9, %ebx
addl $1, %ebx
movl %ebx, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L59
.L52:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 4(%rsp)
leaq 4(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl %ebp, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $1, %edx
leaq .LC1(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L60
cmpb $0, 56(%rbp)
je .L55
movzbl 67(%rbp), %esi
.L56:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq %rsp, %rdi
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
movl (%rsp), %eax
movq 56(%rsp), %rdx
subq %fs:40, %rdx
jne .L61
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L59:
.cfi_restore_state
movq 8(%rsp), %r9
movl %r12d, %r8d
movl %r15d, %ecx
movl %ebp, %edx
movl %r14d, %esi
movq %r13, %rdi
call _Z57__device_stub__Z31dev_Unrolled_Coalesced_N_SearchPiiiiiS_PiiiiiS_
jmp .L52
.L60:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L62
call _ZSt16__throw_bad_castv@PLT
.L62:
call __stack_chk_fail@PLT
.L55:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L56
.L61:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z27Unrolled_Coalesced_N_SearchPiiii, .-_Z27Unrolled_Coalesced_N_SearchPiiii
.globl _Z49__device_stub__Z25dev_Full_Coalesced_SearchPiiiS_PiiiS_
.type _Z49__device_stub__Z25dev_Full_Coalesced_SearchPiiiS_PiiiS_, @function
_Z49__device_stub__Z25dev_Full_Coalesced_SearchPiiiS_PiiiS_:
.LFB3727:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L67
.L63:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L68
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L67:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z25dev_Full_Coalesced_SearchPiiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L63
.L68:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3727:
.size _Z49__device_stub__Z25dev_Full_Coalesced_SearchPiiiS_PiiiS_, .-_Z49__device_stub__Z25dev_Full_Coalesced_SearchPiiiS_PiiiS_
.globl _Z25dev_Full_Coalesced_SearchPiiiS_
.type _Z25dev_Full_Coalesced_SearchPiiiS_, @function
_Z25dev_Full_Coalesced_SearchPiiiS_:
.LFB3728:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z25dev_Full_Coalesced_SearchPiiiS_PiiiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3728:
.size _Z25dev_Full_Coalesced_SearchPiiiS_, .-_Z25dev_Full_Coalesced_SearchPiiiS_
.section .rodata.str1.1
.LC2:
.string "1"
.text
.globl _Z21Full_Coalesced_SearchPiii
.type _Z21Full_Coalesced_SearchPiii, @function
_Z21Full_Coalesced_SearchPiii:
.LFB3695:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbp
movl %esi, %r12d
movl %edx, %ebx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $-1, (%rsp)
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movq %rsp, %rsi
movl $1, %ecx
movl $4, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $512, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
leal 511(%rbx), %eax
testl %ebx, %ebx
cmovns %ebx, %eax
sarl $9, %eax
addl $1, %eax
movl %eax, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L79
.L72:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 4(%rsp)
leaq 4(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $1, %edx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $1, %edx
leaq .LC1(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L80
cmpb $0, 56(%rbp)
je .L75
movzbl 67(%rbp), %esi
.L76:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq %rsp, %rdi
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
movl (%rsp), %eax
movq 56(%rsp), %rdx
subq %fs:40, %rdx
jne .L81
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L79:
.cfi_restore_state
movq 8(%rsp), %rcx
movl %ebx, %edx
movl %r12d, %esi
movq %rbp, %rdi
call _Z49__device_stub__Z25dev_Full_Coalesced_SearchPiiiS_PiiiS_
jmp .L72
.L80:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L82
call _ZSt16__throw_bad_castv@PLT
.L82:
call __stack_chk_fail@PLT
.L75:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L76
.L81:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z21Full_Coalesced_SearchPiii, .-_Z21Full_Coalesced_SearchPiii
.section .rodata.str1.1
.LC3:
.string "-- Strided Offset N Search --"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Located unique value at index = "
.section .rodata.str1.1
.LC5:
.string "-- Coalesced N Search --"
.section .rodata.str1.8
.align 8
.LC6:
.string "-- Unrolled Coalesced N Search --"
.section .rodata.str1.1
.LC7:
.string "-- Full Coalesced Search --"
.text
.globl main
.type main, @function
main:
.LFB3696:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
leaq -1998848(%rsp), %r11
.cfi_def_cfa 11, 1998872
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $1192, %rsp
.cfi_def_cfa_offset 2000064
movq %fs:40, %rax
movq %rax, 2000024(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rax
leaq 2000016(%rsp), %rdx
.L84:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L84
movl $5, 288(%rsp)
leaq 8(%rsp), %rdi
movl $2000000, %esi
call cudaMalloc@PLT
leaq 4(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rsi
movl $1, %ecx
movl $2000000, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %ebx
.L85:
movl $500000, %ecx
movl %ebx, %edx
movl $5, %esi
movq 8(%rsp), %rdi
call _Z23Strided_Offset_N_SearchPiiii
movl %eax, %ebp
addl $1, %ebx
cmpl $65, %ebx
jne .L85
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebp, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC5(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %ebx
.L86:
movl $500000, %ecx
movl %ebx, %edx
movl $5, %esi
movq 8(%rsp), %rdi
call _Z18Coalesced_N_SearchPiiii
movl %eax, %ebp
addl $1, %ebx
cmpl $65, %ebx
jne .L86
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebp, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $64, %ebp
.L87:
movl $500000, %ecx
movl $12, %edx
movl $5, %esi
movq 8(%rsp), %rdi
call _Z27Unrolled_Coalesced_N_SearchPiiii
movl %eax, %ebx
subl $1, %ebp
jne .L87
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC7(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $64, %ebp
.L88:
movl $500000, %edx
movl $5, %esi
movq 8(%rsp), %rdi
call _Z21Full_Coalesced_SearchPiii
movl %eax, %ebx
subl $1, %ebp
jne .L88
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 2000024(%rsp), %rax
subq %fs:40, %rax
jne .L96
movl $0, %eax
addq $2000040, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L96:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC8:
.string "_Z25dev_Full_Coalesced_SearchPiiiS_"
.align 8
.LC9:
.string "_Z31dev_Unrolled_Coalesced_N_SearchPiiiiiS_"
.align 8
.LC10:
.string "_Z22dev_Coalesced_N_SearchPiiiiiS_"
.align 8
.LC11:
.string "_Z27dev_Strided_Offset_N_SearchPiiiiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3730:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z25dev_Full_Coalesced_SearchPiiiS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z31dev_Unrolled_Coalesced_N_SearchPiiiiiS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z22dev_Coalesced_N_SearchPiiiiiS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z27dev_Strided_Offset_N_SearchPiiiiS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3730:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // C++ Libraries.
#include <iostream>
// CUDA libraries.
#include <cuda.h>
#include <cuda_runtime.h>
#include "cuComplex.h"
// Define max number of concurrent threads
#define MAX_BLOCKSIZE 512
////////////////////////////////////////////////////////////////////////////////
/// 1. Strided Offset N Search ///
////////////////////////////////////////////////////////////////////////////////
/**
* Searches dev_Array for the given unique value by having each thread search 'offset' number of elements from
* the previous thread's search (strided offset).
* @param dev_Array Array to be searched.
* @param uniqueValue Unique value to be searched for.
* @param offset Number of elements each thread will search, and the separation between each thread's starting index.
* @param arraySize Number of elements in the given array to search.
* @param dev_foundIndex Output index of the found unique value.
*/
__global__ void dev_Strided_Offset_N_Search(int *dev_Array, int uniqueValue, int offset, int arraySize, int *dev_foundIndex){
// Calculate thread id.
int tid = blockDim.x * blockIdx.x + threadIdx.x;
// Initialize currentValue and actualIndex to register memory.
int currentValue, actualIndex;
// Iterate through offset N number of adjacent elements.
for (int N = 0; N < offset; N++){
// Calculate actual array index.
actualIndex = tid * offset + N;
// Ensure thread is not out of bounds.
if ( actualIndex < arraySize ) {
// Retrieve current value from global memory to be checked.
currentValue = dev_Array[actualIndex];
// Check if current value is the unique value.
if ( currentValue == uniqueValue ) {
// Unique value found, store its index in the foundIndex global memory variable.
*dev_foundIndex = actualIndex;
}
}
}
}
/**
* Wrapper function to call the CUDA kernel device function dev_Strided_Offset_N_Search.
* @param dev_Array Array in device memory to be searched.
* @param uniqueValue Unique value to be searched for.
* @param offset Number of elements each thread will search, and the separation between each thread's starting index.
* @param arraySize Number of elements in the given array to search.
* @return Return the index of the unique value.
*/
int Strided_Offset_N_Search(int *dev_Array, int uniqueValue, int offset, int arraySize){
// Initialize foundIndex integer.
int foundIndex = -1;
// Initialize foundIndex device pointer.
int *dev_foundIndex;
// Allocate memory on device for foundIndex.
cudaMalloc((void**)&dev_foundIndex, sizeof(int));
// Copy foundIndex initialized value to device.
cudaMemcpy(dev_foundIndex, &foundIndex, sizeof(int), cudaMemcpyHostToDevice);
// Calculate the number of threads expected.
int numOfThreads = arraySize / offset + 1;
// Initiaize CUDA event timers.
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// Initialize blocksize as the number of threads.
dim3 blockSize(MAX_BLOCKSIZE, 1, 1);
dim3 gridSize(numOfThreads / MAX_BLOCKSIZE + 1, 1);
// Launch device Strided_Offset_N_Search kernel routine and start and stop event timers.
cudaEventRecord(start);
dev_Strided_Offset_N_Search<<<gridSize, blockSize>>>(dev_Array, uniqueValue, offset, arraySize, dev_foundIndex);
cudaEventRecord(stop);
// Retrieve kernel timing.
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
// Print event timing.
std::cout << offset << " " << milliseconds << std::endl;
// Copy d_foundIndex device value back to host memory.
cudaMemcpy(&foundIndex, dev_foundIndex, sizeof(int), cudaMemcpyDeviceToHost);
// Return found index.
return foundIndex;
}
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
/// 2. Coalesced N Element Search ///
////////////////////////////////////////////////////////////////////////////////
/**
* Searches dev_Array for the given unique value by having each thread search adjacent to each other in
* a coalesced fashion, followed by searching adjacent to the other threads again but offset by the total
* number of threads.
* @param dev_Array Array in device memory to be searched.
* @param uniqueValue Unique value to be searched for.
* @param numToCheck Number of elements each thread will check.
* @param numOfThreads Total number of threads searching the array.
* @param arraySize Number of elements in the given array to search.
* @param dev_foundIndex Output index of the found unique value.
*/
__global__ void dev_Coalesced_N_Search(int *dev_Array, int uniqueValue, int numToCheck, int numOfThreads, int arraySize, int *dev_foundIndex){
// Calculate thread id.
int tid = blockDim.x * blockIdx.x + threadIdx.x;
// Initialize currentValue and actualIndex to register memory.
int currentValue, actualIndex;
// Iterate through offset N number of adjacent elements.
for (int N = 0; N < numToCheck; N++){
// Calculate actual array index.
actualIndex = numOfThreads * N + tid;
// Ensure thread is not out of bounds.
if ( actualIndex < arraySize ) {
// Retrieve current value from global memory to be checked.
currentValue = dev_Array[actualIndex];
// Check if current value is the unique value.
if ( currentValue == uniqueValue ) {
// Unique value found, store its index in the foundIndex global memory variable.
*dev_foundIndex = actualIndex;
}
}
}
}
/**
* Wrapper function to call the CUDA kernel device function dev_Coalesced_N_Search.
* @param dev_Array Array in device memory to be searched.
* @param uniqueValue Unique value to be searched for.
* @param numToCheck Number of elements each thread will check.
* @param arraySize Number of elements in the given array to search.
* @return Return the index of the unique value.
*/
int Coalesced_N_Search(int *dev_Array, int uniqueValue, int numToCheck, int arraySize) {
// Initialize foundIndex integer.
int foundIndex = -1;
// Initialize foundIndex device pointer.
int *dev_foundIndex;
// Allocate memory on device for foundIndex.
cudaMalloc((void**)&dev_foundIndex, sizeof(int));
// Copy foundIndex initialized value to device.
cudaMemcpy(dev_foundIndex, &foundIndex, sizeof(int), cudaMemcpyHostToDevice);
// Calculate the number of threads expected.
int numOfThreads = arraySize / numToCheck + 1;
// Initiaize CUDA event timers.
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// Initialize blocksize as the number of threads.
dim3 blockSize(MAX_BLOCKSIZE, 1, 1);
dim3 gridSize(numOfThreads / MAX_BLOCKSIZE + 1, 1);
// Launch device Strided_Offset_N_Search kernel routine and start and stop event timers.
cudaEventRecord(start);
dev_Coalesced_N_Search<<<gridSize, blockSize>>>(dev_Array, uniqueValue, numToCheck, numOfThreads, arraySize, dev_foundIndex);
cudaEventRecord(stop);
// Retrieve kernel timing.
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
// Print event timing.
std::cout << numToCheck << " " << milliseconds << std::endl;
// Copy d_foundIndex device value back to host memory.
cudaMemcpy(&foundIndex, dev_foundIndex, sizeof(int), cudaMemcpyDeviceToHost);
// Return found index.
return foundIndex;
}
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
/// 3. Unrolled Coalesced N Element Search ///
////////////////////////////////////////////////////////////////////////////////
/**
* Searches dev_Array for the given unique value by having each thread search adjacent to each other in
* a coalesced fashion, followed by searching adjacent to the other threads again but offset by the total
* number of threads. All for loops are unrolled with #pragma.
* @param dev_Array Array in device memory to be searched.
* @param uniqueValue Unique value to be searched for.
* @param numToCheck Number of elements each thread will check.
* @param numOfThreads Total number of threads searching the array.
* @param arraySize Number of elements in the given array to search.
* @param dev_foundIndex Output index of the found unique value.
*/
__global__ void dev_Unrolled_Coalesced_N_Search(int *dev_Array, int uniqueValue, int numToCheck, int numOfThreads, int arraySize, int *dev_foundIndex){
// Calculate thread id.
int tid = blockDim.x * blockIdx.x + threadIdx.x;
// Initialize currentValue and actualIndex to register memory.
int currentValue, actualIndex;
// Iterate through offset N number of adjacent elements.
#pragma unroll
for (int N = 0; N < numToCheck; N++){
// Calculate actual array index.
actualIndex = numOfThreads * N + tid;
// Ensure thread is not out of bounds.
if ( actualIndex < arraySize ) {
// Retrieve current value from global memory to be checked.
currentValue = dev_Array[actualIndex];
// Check if current value is the unique value.
if ( currentValue == uniqueValue ) {
// Unique value found, store its index in the foundIndex global memory variable.
*dev_foundIndex = actualIndex;
}
}
}
}
/**
* Wrapper function to call the CUDA kernel device function dev_Coalesced_N_Search.
* @param dev_Array Array in device memory to be searched.
* @param uniqueValue Unique value to be searched for.
* @param numToCheck Number of elements each thread will check.
* @param arraySize Number of elements in the given array to search.
* @return Return the index of the unique value.
*/
int Unrolled_Coalesced_N_Search(int *dev_Array, int uniqueValue, int numToCheck, int arraySize) {
// Initialize foundIndex integer.
int foundIndex = -1;
// Initialize foundIndex device pointer.
int *dev_foundIndex;
// Allocate memory on device for foundIndex.
cudaMalloc((void**)&dev_foundIndex, sizeof(int));
// Copy foundIndex initialized value to device.
cudaMemcpy(dev_foundIndex, &foundIndex, sizeof(int), cudaMemcpyHostToDevice);
// Calculate the number of threads expected.
int numOfThreads = arraySize / numToCheck + 1;
// Initiaize CUDA event timers.
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// Initialize blocksize as the number of threads.
dim3 blockSize(MAX_BLOCKSIZE, 1, 1);
dim3 gridSize(numOfThreads / MAX_BLOCKSIZE + 1, 1);
// Launch device Strided_Offset_N_Search kernel routine and start and stop event timers.
cudaEventRecord(start);
dev_Unrolled_Coalesced_N_Search<<<gridSize, blockSize>>>(dev_Array, uniqueValue, numToCheck, numOfThreads, arraySize, dev_foundIndex);
cudaEventRecord(stop);
// Retrieve kernel timing.
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
// Print event timing.
std::cout << numToCheck << " " << milliseconds << std::endl;
// Copy d_foundIndex device value back to host memory.
cudaMemcpy(&foundIndex, dev_foundIndex, sizeof(int), cudaMemcpyDeviceToHost);
// Return found index.
return foundIndex;
}
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
/// 4. Full Coalesced Element Search ///
////////////////////////////////////////////////////////////////////////////////
/**
* Searches dev_Array for the given unique value by having each thread search adjacent to each other in
* a coalesced fashion.
* @param dev_Array Array in device memory to be searched.
* @param uniqueValue Unique value to be searched for.
* @param arraySize Number of elements in the given array to search.
* @param dev_foundIndex Output index of the found unique value.
*/
__global__ void dev_Full_Coalesced_Search(int *dev_Array, int uniqueValue, int arraySize, int *dev_foundIndex){
// Calculate thread id.
int tid = blockDim.x * blockIdx.x + threadIdx.x;
// Retrieve current value from global memory to be checked.
int currentValue = dev_Array[tid];
// Check if current value is the unique value.
if ( currentValue == uniqueValue ) {
// Unique value found, store its index in the foundIndex global memory variable.
*dev_foundIndex = tid;
}
}
/**
* Wrapper function to call the CUDA kernel device function dev_Coalesced_N_Search.
* @param dev_Array Array in device memory to be searched.
* @param uniqueValue Unique value to be searched for.
* @param arraySize Number of elements in the given array to search.
* @return Return the index of the unique value.
*/
int Full_Coalesced_Search(int *dev_Array, int uniqueValue, int arraySize) {
// Initialize foundIndex integer.
int foundIndex = -1;
// Initialize foundIndex device pointer.
int *dev_foundIndex;
// Allocate memory on device for foundIndex.
cudaMalloc((void**)&dev_foundIndex, sizeof(int));
// Copy foundIndex initialized value to device.
cudaMemcpy(dev_foundIndex, &foundIndex, sizeof(int), cudaMemcpyHostToDevice);
// Calculate the number of threads expected.
int numOfThreads = arraySize;
// Initiaize CUDA event timers.
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// Initialize blocksize as the number of threads.
dim3 blockSize(MAX_BLOCKSIZE, 1, 1);
dim3 gridSize(numOfThreads / MAX_BLOCKSIZE + 1, 1);
// Launch device Strided_Offset_N_Search kernel routine and start and stop event timers.
cudaEventRecord(start);
dev_Full_Coalesced_Search<<<gridSize, blockSize>>>(dev_Array, uniqueValue, arraySize, dev_foundIndex);
cudaEventRecord(stop);
// Retrieve kernel timing.
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
// Print event timing.
std::cout << "1" << " " << milliseconds << std::endl;
// Copy d_foundIndex device value back to host memory.
cudaMemcpy(&foundIndex, dev_foundIndex, sizeof(int), cudaMemcpyDeviceToHost);
// Return found index.
return foundIndex;
}
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
int main(){
// Define unique value to search for.
const int uniqueValue = 5;
// Define random index the unique value will be for constructing the searchable array.
const int randomIndex = 68;
// Define the size of our array.
const int arraySize = 500000;
// Initialize test array that we will search.
int testArray[arraySize];
// Set array to all zeros.
for (int i = 0; i < arraySize; i++){
testArray[i] = 0;
}
// Set random index to value to search for.
testArray[randomIndex] = uniqueValue;
// CUDA ALLOCATIONS //
// Initialize device pointers.
int *d_testArray, d_foundIndex;
// Allocate memory for local variables on the GPU device.
cudaMalloc((void**)&d_testArray, arraySize * sizeof(int));
cudaMalloc((void**)&d_foundIndex, sizeof(int));
// Transfer test array from local host memory to device.
cudaMemcpy(d_testArray, testArray, arraySize * sizeof(int), cudaMemcpyHostToDevice);
// Find unique values //
int foundIndex = -1;
//////////////////////////////////////////////////////////////////////////////////////////////////////
// 1. Each thread searches through N adjacent elements where each thread begins its search N elements
// from the previous thread's starting position. If a thread successfully locates the unique value, it
// write the index of the element to memory.
//////////////////////////////////////////////////////////////////////////////////////////////////////
// Test multiple offset sizes.
std::cout << "-- Strided Offset N Search --" << std::endl;
int offset = 1;
for (int offset = 1; offset < 65; offset+=1) {
foundIndex = Strided_Offset_N_Search(d_testArray, uniqueValue, offset, arraySize);
}
// Print out index of found unique value.
std::cout << "Located unique value at index = " << foundIndex << std::endl;
/////////////////////////////////////////////////////////////////////////////////////////////////////
// 2. Each thread searches through N elements in a coalesced fashion where each thread begins its search
// adjacent to the previous and following threads starting positions. From there, the threads search the
// value which is the total number of threads offset from the current position, so that all threads are
// still making coalesced memory calls.
/////////////////////////////////////////////////////////////////////////////////////////////////////
// Test multiple values of N, where N is the number of elements each thread will check.
std::cout << "-- Coalesced N Search --" << std::endl;
int numToCheck = 1;
for (int numToCheck = 1; numToCheck < 65; numToCheck+=1) {
foundIndex = Coalesced_N_Search(d_testArray, uniqueValue, numToCheck, arraySize);
}
// Print out index of found unique value.
std::cout << "Located unique value at index = " << foundIndex << std::endl;
/////////////////////////////////////////////////////////////////////////////////////////////////////
// 3. Each thread searches through N elements in a coalesced fashion where each thread begins its search
// adjacent to the previous and following threads starting positions. From there, the threads search the
// value which is the total number of threads offset from the current position, so that all threads are
// still making coalesced memory calls. For loop is unroll with #pragma.
/////////////////////////////////////////////////////////////////////////////////////////////////////
// Test multiple values of N, where N is the number of elements each thread will check.
std::cout << "-- Unrolled Coalesced N Search --" << std::endl;
for (int numToCheck = 1; numToCheck < 65; numToCheck+=1) {
foundIndex = Unrolled_Coalesced_N_Search(d_testArray, uniqueValue, 12, arraySize);
}
// Print out index of found unique value.
std::cout << "Located unique value at index = " << foundIndex << std::endl;
///////////////////////////////////////////////////////////////////////////////////////////////////
// 4. Each thread searches a single elements in a coalesced fashion where each thread begins its search
// adjacent to the previous and following threads starting positions.
///////////////////////////////////////////////////////////////////////////////////////////////////
// Test multiple values of N, where N is the number of elements each thread will check.
std::cout << "-- Full Coalesced Search --" << std::endl;
for (int offset = 1; offset < 65; offset+=1) {
foundIndex = Full_Coalesced_Search(d_testArray, uniqueValue, arraySize);
}
// Print out index of found unique value.
std::cout << "Located unique value at index = " << foundIndex << std::endl;
} | // C++ Libraries.
#include <iostream>
// CUDA libraries.
#include <hip/hip_runtime.h>
#include "hip/hip_complex.h"
// Define max number of concurrent threads
#define MAX_BLOCKSIZE 512
////////////////////////////////////////////////////////////////////////////////
/// 1. Strided Offset N Search ///
////////////////////////////////////////////////////////////////////////////////
/**
* Searches dev_Array for the given unique value by having each thread search 'offset' number of elements from
* the previous thread's search (strided offset).
* @param dev_Array Array to be searched.
* @param uniqueValue Unique value to be searched for.
* @param offset Number of elements each thread will search, and the separation between each thread's starting index.
* @param arraySize Number of elements in the given array to search.
* @param dev_foundIndex Output index of the found unique value.
*/
__global__ void dev_Strided_Offset_N_Search(int *dev_Array, int uniqueValue, int offset, int arraySize, int *dev_foundIndex){
// Calculate thread id.
int tid = blockDim.x * blockIdx.x + threadIdx.x;
// Initialize currentValue and actualIndex to register memory.
int currentValue, actualIndex;
// Iterate through offset N number of adjacent elements.
for (int N = 0; N < offset; N++){
// Calculate actual array index.
actualIndex = tid * offset + N;
// Ensure thread is not out of bounds.
if ( actualIndex < arraySize ) {
// Retrieve current value from global memory to be checked.
currentValue = dev_Array[actualIndex];
// Check if current value is the unique value.
if ( currentValue == uniqueValue ) {
// Unique value found, store its index in the foundIndex global memory variable.
*dev_foundIndex = actualIndex;
}
}
}
}
/**
* Wrapper function to call the CUDA kernel device function dev_Strided_Offset_N_Search.
* @param dev_Array Array in device memory to be searched.
* @param uniqueValue Unique value to be searched for.
* @param offset Number of elements each thread will search, and the separation between each thread's starting index.
* @param arraySize Number of elements in the given array to search.
* @return Return the index of the unique value.
*/
int Strided_Offset_N_Search(int *dev_Array, int uniqueValue, int offset, int arraySize){
// Initialize foundIndex integer.
int foundIndex = -1;
// Initialize foundIndex device pointer.
int *dev_foundIndex;
// Allocate memory on device for foundIndex.
hipMalloc((void**)&dev_foundIndex, sizeof(int));
// Copy foundIndex initialized value to device.
hipMemcpy(dev_foundIndex, &foundIndex, sizeof(int), hipMemcpyHostToDevice);
// Calculate the number of threads expected.
int numOfThreads = arraySize / offset + 1;
// Initiaize CUDA event timers.
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// Initialize blocksize as the number of threads.
dim3 blockSize(MAX_BLOCKSIZE, 1, 1);
dim3 gridSize(numOfThreads / MAX_BLOCKSIZE + 1, 1);
// Launch device Strided_Offset_N_Search kernel routine and start and stop event timers.
hipEventRecord(start);
dev_Strided_Offset_N_Search<<<gridSize, blockSize>>>(dev_Array, uniqueValue, offset, arraySize, dev_foundIndex);
hipEventRecord(stop);
// Retrieve kernel timing.
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
// Print event timing.
std::cout << offset << " " << milliseconds << std::endl;
// Copy d_foundIndex device value back to host memory.
hipMemcpy(&foundIndex, dev_foundIndex, sizeof(int), hipMemcpyDeviceToHost);
// Return found index.
return foundIndex;
}
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
/// 2. Coalesced N Element Search ///
////////////////////////////////////////////////////////////////////////////////
/**
* Searches dev_Array for the given unique value by having each thread search adjacent to each other in
* a coalesced fashion, followed by searching adjacent to the other threads again but offset by the total
* number of threads.
* @param dev_Array Array in device memory to be searched.
* @param uniqueValue Unique value to be searched for.
* @param numToCheck Number of elements each thread will check.
* @param numOfThreads Total number of threads searching the array.
* @param arraySize Number of elements in the given array to search.
* @param dev_foundIndex Output index of the found unique value.
*/
__global__ void dev_Coalesced_N_Search(int *dev_Array, int uniqueValue, int numToCheck, int numOfThreads, int arraySize, int *dev_foundIndex){
// Calculate thread id.
int tid = blockDim.x * blockIdx.x + threadIdx.x;
// Initialize currentValue and actualIndex to register memory.
int currentValue, actualIndex;
// Iterate through offset N number of adjacent elements.
for (int N = 0; N < numToCheck; N++){
// Calculate actual array index.
actualIndex = numOfThreads * N + tid;
// Ensure thread is not out of bounds.
if ( actualIndex < arraySize ) {
// Retrieve current value from global memory to be checked.
currentValue = dev_Array[actualIndex];
// Check if current value is the unique value.
if ( currentValue == uniqueValue ) {
// Unique value found, store its index in the foundIndex global memory variable.
*dev_foundIndex = actualIndex;
}
}
}
}
/**
* Wrapper function to call the CUDA kernel device function dev_Coalesced_N_Search.
* @param dev_Array Array in device memory to be searched.
* @param uniqueValue Unique value to be searched for.
* @param numToCheck Number of elements each thread will check.
* @param arraySize Number of elements in the given array to search.
* @return Return the index of the unique value.
*/
int Coalesced_N_Search(int *dev_Array, int uniqueValue, int numToCheck, int arraySize) {
// Initialize foundIndex integer.
int foundIndex = -1;
// Initialize foundIndex device pointer.
int *dev_foundIndex;
// Allocate memory on device for foundIndex.
hipMalloc((void**)&dev_foundIndex, sizeof(int));
// Copy foundIndex initialized value to device.
hipMemcpy(dev_foundIndex, &foundIndex, sizeof(int), hipMemcpyHostToDevice);
// Calculate the number of threads expected.
int numOfThreads = arraySize / numToCheck + 1;
// Initiaize CUDA event timers.
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// Initialize blocksize as the number of threads.
dim3 blockSize(MAX_BLOCKSIZE, 1, 1);
dim3 gridSize(numOfThreads / MAX_BLOCKSIZE + 1, 1);
// Launch device Strided_Offset_N_Search kernel routine and start and stop event timers.
hipEventRecord(start);
dev_Coalesced_N_Search<<<gridSize, blockSize>>>(dev_Array, uniqueValue, numToCheck, numOfThreads, arraySize, dev_foundIndex);
hipEventRecord(stop);
// Retrieve kernel timing.
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
// Print event timing.
std::cout << numToCheck << " " << milliseconds << std::endl;
// Copy d_foundIndex device value back to host memory.
hipMemcpy(&foundIndex, dev_foundIndex, sizeof(int), hipMemcpyDeviceToHost);
// Return found index.
return foundIndex;
}
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
/// 3. Unrolled Coalesced N Element Search ///
////////////////////////////////////////////////////////////////////////////////
/**
* Searches dev_Array for the given unique value by having each thread search adjacent to each other in
* a coalesced fashion, followed by searching adjacent to the other threads again but offset by the total
* number of threads. All for loops are unrolled with #pragma.
* @param dev_Array Array in device memory to be searched.
* @param uniqueValue Unique value to be searched for.
* @param numToCheck Number of elements each thread will check.
* @param numOfThreads Total number of threads searching the array.
* @param arraySize Number of elements in the given array to search.
* @param dev_foundIndex Output index of the found unique value.
*/
__global__ void dev_Unrolled_Coalesced_N_Search(int *dev_Array, int uniqueValue, int numToCheck, int numOfThreads, int arraySize, int *dev_foundIndex){
// Calculate thread id.
int tid = blockDim.x * blockIdx.x + threadIdx.x;
// Initialize currentValue and actualIndex to register memory.
int currentValue, actualIndex;
// Iterate through offset N number of adjacent elements.
#pragma unroll
for (int N = 0; N < numToCheck; N++){
// Calculate actual array index.
actualIndex = numOfThreads * N + tid;
// Ensure thread is not out of bounds.
if ( actualIndex < arraySize ) {
// Retrieve current value from global memory to be checked.
currentValue = dev_Array[actualIndex];
// Check if current value is the unique value.
if ( currentValue == uniqueValue ) {
// Unique value found, store its index in the foundIndex global memory variable.
*dev_foundIndex = actualIndex;
}
}
}
}
/**
* Wrapper function to call the CUDA kernel device function dev_Coalesced_N_Search.
* @param dev_Array Array in device memory to be searched.
* @param uniqueValue Unique value to be searched for.
* @param numToCheck Number of elements each thread will check.
* @param arraySize Number of elements in the given array to search.
* @return Return the index of the unique value.
*/
int Unrolled_Coalesced_N_Search(int *dev_Array, int uniqueValue, int numToCheck, int arraySize) {
// Initialize foundIndex integer.
int foundIndex = -1;
// Initialize foundIndex device pointer.
int *dev_foundIndex;
// Allocate memory on device for foundIndex.
hipMalloc((void**)&dev_foundIndex, sizeof(int));
// Copy foundIndex initialized value to device.
hipMemcpy(dev_foundIndex, &foundIndex, sizeof(int), hipMemcpyHostToDevice);
// Calculate the number of threads expected.
int numOfThreads = arraySize / numToCheck + 1;
// Initiaize CUDA event timers.
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// Initialize blocksize as the number of threads.
dim3 blockSize(MAX_BLOCKSIZE, 1, 1);
dim3 gridSize(numOfThreads / MAX_BLOCKSIZE + 1, 1);
// Launch device Strided_Offset_N_Search kernel routine and start and stop event timers.
hipEventRecord(start);
dev_Unrolled_Coalesced_N_Search<<<gridSize, blockSize>>>(dev_Array, uniqueValue, numToCheck, numOfThreads, arraySize, dev_foundIndex);
hipEventRecord(stop);
// Retrieve kernel timing.
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
// Print event timing.
std::cout << numToCheck << " " << milliseconds << std::endl;
// Copy d_foundIndex device value back to host memory.
hipMemcpy(&foundIndex, dev_foundIndex, sizeof(int), hipMemcpyDeviceToHost);
// Return found index.
return foundIndex;
}
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
/// 4. Full Coalesced Element Search ///
////////////////////////////////////////////////////////////////////////////////
/**
* Searches dev_Array for the given unique value by having each thread search adjacent to each other in
* a coalesced fashion.
* @param dev_Array Array in device memory to be searched.
* @param uniqueValue Unique value to be searched for.
* @param arraySize Number of elements in the given array to search.
* @param dev_foundIndex Output index of the found unique value.
*/
__global__ void dev_Full_Coalesced_Search(int *dev_Array, int uniqueValue, int arraySize, int *dev_foundIndex){
// Calculate thread id.
int tid = blockDim.x * blockIdx.x + threadIdx.x;
// Retrieve current value from global memory to be checked.
int currentValue = dev_Array[tid];
// Check if current value is the unique value.
if ( currentValue == uniqueValue ) {
// Unique value found, store its index in the foundIndex global memory variable.
*dev_foundIndex = tid;
}
}
/**
* Wrapper function to call the CUDA kernel device function dev_Coalesced_N_Search.
* @param dev_Array Array in device memory to be searched.
* @param uniqueValue Unique value to be searched for.
* @param arraySize Number of elements in the given array to search.
* @return Return the index of the unique value.
*/
int Full_Coalesced_Search(int *dev_Array, int uniqueValue, int arraySize) {
// Initialize foundIndex integer.
int foundIndex = -1;
// Initialize foundIndex device pointer.
int *dev_foundIndex;
// Allocate memory on device for foundIndex.
hipMalloc((void**)&dev_foundIndex, sizeof(int));
// Copy foundIndex initialized value to device.
hipMemcpy(dev_foundIndex, &foundIndex, sizeof(int), hipMemcpyHostToDevice);
// Calculate the number of threads expected.
int numOfThreads = arraySize;
// Initiaize CUDA event timers.
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// Initialize blocksize as the number of threads.
dim3 blockSize(MAX_BLOCKSIZE, 1, 1);
dim3 gridSize(numOfThreads / MAX_BLOCKSIZE + 1, 1);
// Launch device Strided_Offset_N_Search kernel routine and start and stop event timers.
hipEventRecord(start);
dev_Full_Coalesced_Search<<<gridSize, blockSize>>>(dev_Array, uniqueValue, arraySize, dev_foundIndex);
hipEventRecord(stop);
// Retrieve kernel timing.
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
// Print event timing.
std::cout << "1" << " " << milliseconds << std::endl;
// Copy d_foundIndex device value back to host memory.
hipMemcpy(&foundIndex, dev_foundIndex, sizeof(int), hipMemcpyDeviceToHost);
// Return found index.
return foundIndex;
}
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
int main(){
// Define unique value to search for.
const int uniqueValue = 5;
// Define random index the unique value will be for constructing the searchable array.
const int randomIndex = 68;
// Define the size of our array.
const int arraySize = 500000;
// Initialize test array that we will search.
int testArray[arraySize];
// Set array to all zeros.
for (int i = 0; i < arraySize; i++){
testArray[i] = 0;
}
// Set random index to value to search for.
testArray[randomIndex] = uniqueValue;
// CUDA ALLOCATIONS //
// Initialize device pointers.
int *d_testArray, d_foundIndex;
// Allocate memory for local variables on the GPU device.
hipMalloc((void**)&d_testArray, arraySize * sizeof(int));
hipMalloc((void**)&d_foundIndex, sizeof(int));
// Transfer test array from local host memory to device.
hipMemcpy(d_testArray, testArray, arraySize * sizeof(int), hipMemcpyHostToDevice);
// Find unique values //
int foundIndex = -1;
//////////////////////////////////////////////////////////////////////////////////////////////////////
// 1. Each thread searches through N adjacent elements where each thread begins its search N elements
// from the previous thread's starting position. If a thread successfully locates the unique value, it
// write the index of the element to memory.
//////////////////////////////////////////////////////////////////////////////////////////////////////
// Test multiple offset sizes.
std::cout << "-- Strided Offset N Search --" << std::endl;
int offset = 1;
for (int offset = 1; offset < 65; offset+=1) {
foundIndex = Strided_Offset_N_Search(d_testArray, uniqueValue, offset, arraySize);
}
// Print out index of found unique value.
std::cout << "Located unique value at index = " << foundIndex << std::endl;
/////////////////////////////////////////////////////////////////////////////////////////////////////
// 2. Each thread searches through N elements in a coalesced fashion where each thread begins its search
// adjacent to the previous and following threads starting positions. From there, the threads search the
// value which is the total number of threads offset from the current position, so that all threads are
// still making coalesced memory calls.
/////////////////////////////////////////////////////////////////////////////////////////////////////
// Test multiple values of N, where N is the number of elements each thread will check.
std::cout << "-- Coalesced N Search --" << std::endl;
int numToCheck = 1;
for (int numToCheck = 1; numToCheck < 65; numToCheck+=1) {
foundIndex = Coalesced_N_Search(d_testArray, uniqueValue, numToCheck, arraySize);
}
// Print out index of found unique value.
std::cout << "Located unique value at index = " << foundIndex << std::endl;
/////////////////////////////////////////////////////////////////////////////////////////////////////
// 3. Each thread searches through N elements in a coalesced fashion where each thread begins its search
// adjacent to the previous and following threads starting positions. From there, the threads search the
// value which is the total number of threads offset from the current position, so that all threads are
// still making coalesced memory calls. For loop is unroll with #pragma.
/////////////////////////////////////////////////////////////////////////////////////////////////////
// Test multiple values of N, where N is the number of elements each thread will check.
std::cout << "-- Unrolled Coalesced N Search --" << std::endl;
for (int numToCheck = 1; numToCheck < 65; numToCheck+=1) {
foundIndex = Unrolled_Coalesced_N_Search(d_testArray, uniqueValue, 12, arraySize);
}
// Print out index of found unique value.
std::cout << "Located unique value at index = " << foundIndex << std::endl;
///////////////////////////////////////////////////////////////////////////////////////////////////
// 4. Each thread searches a single elements in a coalesced fashion where each thread begins its search
// adjacent to the previous and following threads starting positions.
///////////////////////////////////////////////////////////////////////////////////////////////////
// Test multiple values of N, where N is the number of elements each thread will check.
std::cout << "-- Full Coalesced Search --" << std::endl;
for (int offset = 1; offset < 65; offset+=1) {
foundIndex = Full_Coalesced_Search(d_testArray, uniqueValue, arraySize);
}
// Print out index of found unique value.
std::cout << "Located unique value at index = " << foundIndex << std::endl;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // C++ Libraries.
#include <iostream>
// CUDA libraries.
#include <hip/hip_runtime.h>
#include "hip/hip_complex.h"
// Define max number of concurrent threads
#define MAX_BLOCKSIZE 512
////////////////////////////////////////////////////////////////////////////////
/// 1. Strided Offset N Search ///
////////////////////////////////////////////////////////////////////////////////
/**
* Searches dev_Array for the given unique value by having each thread search 'offset' number of elements from
* the previous thread's search (strided offset).
* @param dev_Array Array to be searched.
* @param uniqueValue Unique value to be searched for.
* @param offset Number of elements each thread will search, and the separation between each thread's starting index.
* @param arraySize Number of elements in the given array to search.
* @param dev_foundIndex Output index of the found unique value.
*/
__global__ void dev_Strided_Offset_N_Search(int *dev_Array, int uniqueValue, int offset, int arraySize, int *dev_foundIndex){
// Calculate thread id.
int tid = blockDim.x * blockIdx.x + threadIdx.x;
// Initialize currentValue and actualIndex to register memory.
int currentValue, actualIndex;
// Iterate through offset N number of adjacent elements.
for (int N = 0; N < offset; N++){
// Calculate actual array index.
actualIndex = tid * offset + N;
// Ensure thread is not out of bounds.
if ( actualIndex < arraySize ) {
// Retrieve current value from global memory to be checked.
currentValue = dev_Array[actualIndex];
// Check if current value is the unique value.
if ( currentValue == uniqueValue ) {
// Unique value found, store its index in the foundIndex global memory variable.
*dev_foundIndex = actualIndex;
}
}
}
}
/**
* Wrapper function to call the CUDA kernel device function dev_Strided_Offset_N_Search.
* @param dev_Array Array in device memory to be searched.
* @param uniqueValue Unique value to be searched for.
* @param offset Number of elements each thread will search, and the separation between each thread's starting index.
* @param arraySize Number of elements in the given array to search.
* @return Return the index of the unique value.
*/
int Strided_Offset_N_Search(int *dev_Array, int uniqueValue, int offset, int arraySize){
// Initialize foundIndex integer.
int foundIndex = -1;
// Initialize foundIndex device pointer.
int *dev_foundIndex;
// Allocate memory on device for foundIndex.
hipMalloc((void**)&dev_foundIndex, sizeof(int));
// Copy foundIndex initialized value to device.
hipMemcpy(dev_foundIndex, &foundIndex, sizeof(int), hipMemcpyHostToDevice);
// Calculate the number of threads expected.
int numOfThreads = arraySize / offset + 1;
// Initiaize CUDA event timers.
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// Initialize blocksize as the number of threads.
dim3 blockSize(MAX_BLOCKSIZE, 1, 1);
dim3 gridSize(numOfThreads / MAX_BLOCKSIZE + 1, 1);
// Launch device Strided_Offset_N_Search kernel routine and start and stop event timers.
hipEventRecord(start);
dev_Strided_Offset_N_Search<<<gridSize, blockSize>>>(dev_Array, uniqueValue, offset, arraySize, dev_foundIndex);
hipEventRecord(stop);
// Retrieve kernel timing.
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
// Print event timing.
std::cout << offset << " " << milliseconds << std::endl;
// Copy d_foundIndex device value back to host memory.
hipMemcpy(&foundIndex, dev_foundIndex, sizeof(int), hipMemcpyDeviceToHost);
// Return found index.
return foundIndex;
}
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
/// 2. Coalesced N Element Search ///
////////////////////////////////////////////////////////////////////////////////
/**
* Searches dev_Array for the given unique value by having each thread search adjacent to each other in
* a coalesced fashion, followed by searching adjacent to the other threads again but offset by the total
* number of threads.
* @param dev_Array Array in device memory to be searched.
* @param uniqueValue Unique value to be searched for.
* @param numToCheck Number of elements each thread will check.
* @param numOfThreads Total number of threads searching the array.
* @param arraySize Number of elements in the given array to search.
* @param dev_foundIndex Output index of the found unique value.
*/
__global__ void dev_Coalesced_N_Search(int *dev_Array, int uniqueValue, int numToCheck, int numOfThreads, int arraySize, int *dev_foundIndex){
// Calculate thread id.
int tid = blockDim.x * blockIdx.x + threadIdx.x;
// Initialize currentValue and actualIndex to register memory.
int currentValue, actualIndex;
// Iterate through offset N number of adjacent elements.
for (int N = 0; N < numToCheck; N++){
// Calculate actual array index.
actualIndex = numOfThreads * N + tid;
// Ensure thread is not out of bounds.
if ( actualIndex < arraySize ) {
// Retrieve current value from global memory to be checked.
currentValue = dev_Array[actualIndex];
// Check if current value is the unique value.
if ( currentValue == uniqueValue ) {
// Unique value found, store its index in the foundIndex global memory variable.
*dev_foundIndex = actualIndex;
}
}
}
}
/**
* Wrapper function to call the CUDA kernel device function dev_Coalesced_N_Search.
* @param dev_Array Array in device memory to be searched.
* @param uniqueValue Unique value to be searched for.
* @param numToCheck Number of elements each thread will check.
* @param arraySize Number of elements in the given array to search.
* @return Return the index of the unique value.
*/
int Coalesced_N_Search(int *dev_Array, int uniqueValue, int numToCheck, int arraySize) {
// Initialize foundIndex integer.
int foundIndex = -1;
// Initialize foundIndex device pointer.
int *dev_foundIndex;
// Allocate memory on device for foundIndex.
hipMalloc((void**)&dev_foundIndex, sizeof(int));
// Copy foundIndex initialized value to device.
hipMemcpy(dev_foundIndex, &foundIndex, sizeof(int), hipMemcpyHostToDevice);
// Calculate the number of threads expected.
int numOfThreads = arraySize / numToCheck + 1;
// Initiaize CUDA event timers.
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// Initialize blocksize as the number of threads.
dim3 blockSize(MAX_BLOCKSIZE, 1, 1);
dim3 gridSize(numOfThreads / MAX_BLOCKSIZE + 1, 1);
// Launch device Strided_Offset_N_Search kernel routine and start and stop event timers.
hipEventRecord(start);
dev_Coalesced_N_Search<<<gridSize, blockSize>>>(dev_Array, uniqueValue, numToCheck, numOfThreads, arraySize, dev_foundIndex);
hipEventRecord(stop);
// Retrieve kernel timing.
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
// Print event timing.
std::cout << numToCheck << " " << milliseconds << std::endl;
// Copy d_foundIndex device value back to host memory.
hipMemcpy(&foundIndex, dev_foundIndex, sizeof(int), hipMemcpyDeviceToHost);
// Return found index.
return foundIndex;
}
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
/// 3. Unrolled Coalesced N Element Search ///
////////////////////////////////////////////////////////////////////////////////
/**
* Searches dev_Array for the given unique value by having each thread search adjacent to each other in
* a coalesced fashion, followed by searching adjacent to the other threads again but offset by the total
* number of threads. All for loops are unrolled with #pragma.
* @param dev_Array Array in device memory to be searched.
* @param uniqueValue Unique value to be searched for.
* @param numToCheck Number of elements each thread will check.
* @param numOfThreads Total number of threads searching the array.
* @param arraySize Number of elements in the given array to search.
* @param dev_foundIndex Output index of the found unique value.
*/
__global__ void dev_Unrolled_Coalesced_N_Search(int *dev_Array, int uniqueValue, int numToCheck, int numOfThreads, int arraySize, int *dev_foundIndex){
// Calculate thread id.
int tid = blockDim.x * blockIdx.x + threadIdx.x;
// Initialize currentValue and actualIndex to register memory.
int currentValue, actualIndex;
// Iterate through offset N number of adjacent elements.
#pragma unroll
for (int N = 0; N < numToCheck; N++){
// Calculate actual array index.
actualIndex = numOfThreads * N + tid;
// Ensure thread is not out of bounds.
if ( actualIndex < arraySize ) {
// Retrieve current value from global memory to be checked.
currentValue = dev_Array[actualIndex];
// Check if current value is the unique value.
if ( currentValue == uniqueValue ) {
// Unique value found, store its index in the foundIndex global memory variable.
*dev_foundIndex = actualIndex;
}
}
}
}
/**
* Wrapper function to call the CUDA kernel device function dev_Coalesced_N_Search.
* @param dev_Array Array in device memory to be searched.
* @param uniqueValue Unique value to be searched for.
* @param numToCheck Number of elements each thread will check.
* @param arraySize Number of elements in the given array to search.
* @return Return the index of the unique value.
*/
int Unrolled_Coalesced_N_Search(int *dev_Array, int uniqueValue, int numToCheck, int arraySize) {
// Initialize foundIndex integer.
int foundIndex = -1;
// Initialize foundIndex device pointer.
int *dev_foundIndex;
// Allocate memory on device for foundIndex.
hipMalloc((void**)&dev_foundIndex, sizeof(int));
// Copy foundIndex initialized value to device.
hipMemcpy(dev_foundIndex, &foundIndex, sizeof(int), hipMemcpyHostToDevice);
// Calculate the number of threads expected.
int numOfThreads = arraySize / numToCheck + 1;
// Initiaize CUDA event timers.
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// Initialize blocksize as the number of threads.
dim3 blockSize(MAX_BLOCKSIZE, 1, 1);
dim3 gridSize(numOfThreads / MAX_BLOCKSIZE + 1, 1);
// Launch device Strided_Offset_N_Search kernel routine and start and stop event timers.
hipEventRecord(start);
dev_Unrolled_Coalesced_N_Search<<<gridSize, blockSize>>>(dev_Array, uniqueValue, numToCheck, numOfThreads, arraySize, dev_foundIndex);
hipEventRecord(stop);
// Retrieve kernel timing.
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
// Print event timing.
std::cout << numToCheck << " " << milliseconds << std::endl;
// Copy d_foundIndex device value back to host memory.
hipMemcpy(&foundIndex, dev_foundIndex, sizeof(int), hipMemcpyDeviceToHost);
// Return found index.
return foundIndex;
}
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
/// 4. Full Coalesced Element Search ///
////////////////////////////////////////////////////////////////////////////////
/**
* Searches dev_Array for the given unique value by having each thread search adjacent to each other in
* a coalesced fashion.
* @param dev_Array Array in device memory to be searched.
* @param uniqueValue Unique value to be searched for.
* @param arraySize Number of elements in the given array to search.
* @param dev_foundIndex Output index of the found unique value.
*/
__global__ void dev_Full_Coalesced_Search(int *dev_Array, int uniqueValue, int arraySize, int *dev_foundIndex){
// Calculate thread id.
int tid = blockDim.x * blockIdx.x + threadIdx.x;
// Retrieve current value from global memory to be checked.
int currentValue = dev_Array[tid];
// Check if current value is the unique value.
if ( currentValue == uniqueValue ) {
// Unique value found, store its index in the foundIndex global memory variable.
*dev_foundIndex = tid;
}
}
/**
* Wrapper function to call the CUDA kernel device function dev_Coalesced_N_Search.
* @param dev_Array Array in device memory to be searched.
* @param uniqueValue Unique value to be searched for.
* @param arraySize Number of elements in the given array to search.
* @return Return the index of the unique value.
*/
int Full_Coalesced_Search(int *dev_Array, int uniqueValue, int arraySize) {
// Initialize foundIndex integer.
int foundIndex = -1;
// Initialize foundIndex device pointer.
int *dev_foundIndex;
// Allocate memory on device for foundIndex.
hipMalloc((void**)&dev_foundIndex, sizeof(int));
// Copy foundIndex initialized value to device.
hipMemcpy(dev_foundIndex, &foundIndex, sizeof(int), hipMemcpyHostToDevice);
// Calculate the number of threads expected.
int numOfThreads = arraySize;
// Initiaize CUDA event timers.
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// Initialize blocksize as the number of threads.
dim3 blockSize(MAX_BLOCKSIZE, 1, 1);
dim3 gridSize(numOfThreads / MAX_BLOCKSIZE + 1, 1);
// Launch device Strided_Offset_N_Search kernel routine and start and stop event timers.
hipEventRecord(start);
dev_Full_Coalesced_Search<<<gridSize, blockSize>>>(dev_Array, uniqueValue, arraySize, dev_foundIndex);
hipEventRecord(stop);
// Retrieve kernel timing.
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
// Print event timing.
std::cout << "1" << " " << milliseconds << std::endl;
// Copy d_foundIndex device value back to host memory.
hipMemcpy(&foundIndex, dev_foundIndex, sizeof(int), hipMemcpyDeviceToHost);
// Return found index.
return foundIndex;
}
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
int main(){
// Define unique value to search for.
const int uniqueValue = 5;
// Define random index the unique value will be for constructing the searchable array.
const int randomIndex = 68;
// Define the size of our array.
const int arraySize = 500000;
// Initialize test array that we will search.
int testArray[arraySize];
// Set array to all zeros.
for (int i = 0; i < arraySize; i++){
testArray[i] = 0;
}
// Set random index to value to search for.
testArray[randomIndex] = uniqueValue;
// CUDA ALLOCATIONS //
// Initialize device pointers.
int *d_testArray, d_foundIndex;
// Allocate memory for local variables on the GPU device.
hipMalloc((void**)&d_testArray, arraySize * sizeof(int));
hipMalloc((void**)&d_foundIndex, sizeof(int));
// Transfer test array from local host memory to device.
hipMemcpy(d_testArray, testArray, arraySize * sizeof(int), hipMemcpyHostToDevice);
// Find unique values //
int foundIndex = -1;
//////////////////////////////////////////////////////////////////////////////////////////////////////
// 1. Each thread searches through N adjacent elements where each thread begins its search N elements
// from the previous thread's starting position. If a thread successfully locates the unique value, it
// write the index of the element to memory.
//////////////////////////////////////////////////////////////////////////////////////////////////////
// Test multiple offset sizes.
std::cout << "-- Strided Offset N Search --" << std::endl;
int offset = 1;
for (int offset = 1; offset < 65; offset+=1) {
foundIndex = Strided_Offset_N_Search(d_testArray, uniqueValue, offset, arraySize);
}
// Print out index of found unique value.
std::cout << "Located unique value at index = " << foundIndex << std::endl;
/////////////////////////////////////////////////////////////////////////////////////////////////////
// 2. Each thread searches through N elements in a coalesced fashion where each thread begins its search
// adjacent to the previous and following threads starting positions. From there, the threads search the
// value which is the total number of threads offset from the current position, so that all threads are
// still making coalesced memory calls.
/////////////////////////////////////////////////////////////////////////////////////////////////////
// Test multiple values of N, where N is the number of elements each thread will check.
std::cout << "-- Coalesced N Search --" << std::endl;
int numToCheck = 1;
for (int numToCheck = 1; numToCheck < 65; numToCheck+=1) {
foundIndex = Coalesced_N_Search(d_testArray, uniqueValue, numToCheck, arraySize);
}
// Print out index of found unique value.
std::cout << "Located unique value at index = " << foundIndex << std::endl;
/////////////////////////////////////////////////////////////////////////////////////////////////////
// 3. Each thread searches through N elements in a coalesced fashion where each thread begins its search
// adjacent to the previous and following threads starting positions. From there, the threads search the
// value which is the total number of threads offset from the current position, so that all threads are
// still making coalesced memory calls. For loop is unroll with #pragma.
/////////////////////////////////////////////////////////////////////////////////////////////////////
// Test multiple values of N, where N is the number of elements each thread will check.
std::cout << "-- Unrolled Coalesced N Search --" << std::endl;
for (int numToCheck = 1; numToCheck < 65; numToCheck+=1) {
foundIndex = Unrolled_Coalesced_N_Search(d_testArray, uniqueValue, 12, arraySize);
}
// Print out index of found unique value.
std::cout << "Located unique value at index = " << foundIndex << std::endl;
///////////////////////////////////////////////////////////////////////////////////////////////////
// 4. Each thread searches a single elements in a coalesced fashion where each thread begins its search
// adjacent to the previous and following threads starting positions.
///////////////////////////////////////////////////////////////////////////////////////////////////
// Test multiple values of N, where N is the number of elements each thread will check.
std::cout << "-- Full Coalesced Search --" << std::endl;
for (int offset = 1; offset < 65; offset+=1) {
foundIndex = Full_Coalesced_Search(d_testArray, uniqueValue, arraySize);
}
// Print out index of found unique value.
std::cout << "Located unique value at index = " << foundIndex << std::endl;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z27dev_Strided_Offset_N_SearchPiiiiS_
.globl _Z27dev_Strided_Offset_N_SearchPiiiiS_
.p2align 8
.type _Z27dev_Strided_Offset_N_SearchPiiiiS_,@function
_Z27dev_Strided_Offset_N_SearchPiiiiS_:
s_load_b32 s2, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_6
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b64 s[6:7], s[0:1], 0x0
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_clause 0x2
s_load_b32 s3, s[0:1], 0x8
s_load_b32 s4, s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x18
v_mul_lo_u32 v0, v1, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[1:2], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s5
v_add_co_u32 v1, vcc_lo, v1, 4
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
v_add_nc_u32_e32 v0, 1, v0
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 0
s_cbranch_scc1 .LBB0_6
.LBB0_3:
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s4, v0
s_cbranch_execz .LBB0_2
global_load_b32 v4, v[1:2], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, s3, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_2
global_store_b32 v3, v0, s[0:1]
s_branch .LBB0_2
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z27dev_Strided_Offset_N_SearchPiiiiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z27dev_Strided_Offset_N_SearchPiiiiS_, .Lfunc_end0-_Z27dev_Strided_Offset_N_SearchPiiiiS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z22dev_Coalesced_N_SearchPiiiiiS_
.globl _Z22dev_Coalesced_N_SearchPiiiiiS_
.p2align 8
.type _Z22dev_Coalesced_N_SearchPiiiiiS_,@function
_Z22dev_Coalesced_N_SearchPiiiiiS_:
s_load_b32 s8, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s8, 1
s_cbranch_scc1 .LBB1_6
s_clause 0x3
s_load_b32 s9, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s9, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s1, v[0:1]
v_mov_b32_e32 v0, 0
s_branch .LBB1_3
.p2align 6
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u32_e32 v1, s4, v1
s_add_i32 s8, s8, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB1_6
.LBB1_3:
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s5, v1
s_cbranch_execz .LBB1_2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, s0, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB1_2
global_store_b32 v0, v1, s[6:7]
s_branch .LBB1_2
.LBB1_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22dev_Coalesced_N_SearchPiiiiiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z22dev_Coalesced_N_SearchPiiiiiS_, .Lfunc_end1-_Z22dev_Coalesced_N_SearchPiiiiiS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z31dev_Unrolled_Coalesced_N_SearchPiiiiiS_
.globl _Z31dev_Unrolled_Coalesced_N_SearchPiiiiiS_
.p2align 8
.type _Z31dev_Unrolled_Coalesced_N_SearchPiiiiiS_,@function
_Z31dev_Unrolled_Coalesced_N_SearchPiiiiiS_:
s_load_b32 s8, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s8, 1
s_cbranch_scc1 .LBB2_22
s_clause 0x3
s_load_b32 s9, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s9, 0xffff
s_cmp_lt_u32 s8, 4
s_mul_i32 s15, s15, s1
s_mov_b32 s1, 0
s_cbranch_scc1 .LBB2_16
v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v1, s15, v0
s_and_b32 s9, s8, 0x7ffffffc
s_mul_i32 s10, s4, 3
s_lshl_b32 s11, s4, 2
s_lshl_b32 s12, s4, 1
s_branch .LBB2_4
.LBB2_3:
s_or_b32 exec_lo, exec_lo, s13
v_add_nc_u32_e32 v1, s11, v1
s_add_i32 s1, s1, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s9, s1
s_cbranch_scc1 .LBB2_16
.LBB2_4:
s_mov_b32 s13, exec_lo
v_cmpx_gt_i32_e64 s5, v1
s_cbranch_execz .LBB2_7
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, s0, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB2_7
global_store_b32 v4, v1, s[6:7]
.LBB2_7:
s_or_b32 exec_lo, exec_lo, s13
v_add_nc_u32_e32 v2, s4, v1
s_mov_b32 s13, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s5, v2
s_cbranch_execz .LBB2_10
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[2:3]
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
global_load_b32 v3, v[5:6], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, s0, v3
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB2_10
global_store_b32 v4, v2, s[6:7]
.LBB2_10:
s_or_b32 exec_lo, exec_lo, s13
v_add_nc_u32_e32 v2, s12, v1
s_mov_b32 s13, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s5, v2
s_cbranch_execz .LBB2_13
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[2:3]
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
global_load_b32 v3, v[5:6], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, s0, v3
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB2_13
global_store_b32 v4, v2, s[6:7]
.LBB2_13:
s_or_b32 exec_lo, exec_lo, s13
v_add_nc_u32_e32 v2, s10, v1
s_mov_b32 s13, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s5, v2
s_cbranch_execz .LBB2_3
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[2:3]
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
global_load_b32 v3, v[5:6], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, s0, v3
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB2_3
global_store_b32 v4, v2, s[6:7]
s_branch .LBB2_3
.LBB2_16:
s_and_b32 s8, s8, 3
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB2_22
s_mul_i32 s1, s1, s4
v_mov_b32_e32 v2, 0
v_add3_u32 v0, s15, s1, v0
s_branch .LBB2_19
.p2align 6
.LBB2_18:
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u32_e32 v0, s4, v0
s_add_i32 s8, s8, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s8, 0
s_cbranch_scc0 .LBB2_22
.LBB2_19:
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s5, v0
s_cbranch_execz .LBB2_18
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[0:1]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v1, v[3:4], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, s0, v1
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB2_18
global_store_b32 v2, v0, s[6:7]
s_branch .LBB2_18
.LBB2_22:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z31dev_Unrolled_Coalesced_N_SearchPiiiiiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z31dev_Unrolled_Coalesced_N_SearchPiiiiiS_, .Lfunc_end2-_Z31dev_Unrolled_Coalesced_N_SearchPiiiiiS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z25dev_Full_Coalesced_SearchPiiiS_
.globl _Z25dev_Full_Coalesced_SearchPiiiS_
.p2align 8
.type _Z25dev_Full_Coalesced_SearchPiiiS_,@function
_Z25dev_Full_Coalesced_SearchPiiiS_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_load_b64 s[2:3], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_load_b32 s4, s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_mov_b32 s2, exec_lo
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e64 s4, v0
s_cbranch_execz .LBB3_2
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB3_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25dev_Full_Coalesced_SearchPiiiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z25dev_Full_Coalesced_SearchPiiiS_, .Lfunc_end3-_Z25dev_Full_Coalesced_SearchPiiiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z27dev_Strided_Offset_N_SearchPiiiiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z27dev_Strided_Offset_N_SearchPiiiiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22dev_Coalesced_N_SearchPiiiiiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z22dev_Coalesced_N_SearchPiiiiiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z31dev_Unrolled_Coalesced_N_SearchPiiiiiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z31dev_Unrolled_Coalesced_N_SearchPiiiiiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25dev_Full_Coalesced_SearchPiiiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z25dev_Full_Coalesced_SearchPiiiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // C++ Libraries.
#include <iostream>
// CUDA libraries.
#include <hip/hip_runtime.h>
#include "hip/hip_complex.h"
// Define max number of concurrent threads
#define MAX_BLOCKSIZE 512
////////////////////////////////////////////////////////////////////////////////
/// 1. Strided Offset N Search ///
////////////////////////////////////////////////////////////////////////////////
/**
* Searches dev_Array for the given unique value by having each thread search 'offset' number of elements from
* the previous thread's search (strided offset).
* @param dev_Array Array to be searched.
* @param uniqueValue Unique value to be searched for.
* @param offset Number of elements each thread will search, and the separation between each thread's starting index.
* @param arraySize Number of elements in the given array to search.
* @param dev_foundIndex Output index of the found unique value.
*/
__global__ void dev_Strided_Offset_N_Search(int *dev_Array, int uniqueValue, int offset, int arraySize, int *dev_foundIndex){
// Calculate thread id.
int tid = blockDim.x * blockIdx.x + threadIdx.x;
// Initialize currentValue and actualIndex to register memory.
int currentValue, actualIndex;
// Iterate through offset N number of adjacent elements.
for (int N = 0; N < offset; N++){
// Calculate actual array index.
actualIndex = tid * offset + N;
// Ensure thread is not out of bounds.
if ( actualIndex < arraySize ) {
// Retrieve current value from global memory to be checked.
currentValue = dev_Array[actualIndex];
// Check if current value is the unique value.
if ( currentValue == uniqueValue ) {
// Unique value found, store its index in the foundIndex global memory variable.
*dev_foundIndex = actualIndex;
}
}
}
}
/**
* Wrapper function to call the CUDA kernel device function dev_Strided_Offset_N_Search.
* @param dev_Array Array in device memory to be searched.
* @param uniqueValue Unique value to be searched for.
* @param offset Number of elements each thread will search, and the separation between each thread's starting index.
* @param arraySize Number of elements in the given array to search.
* @return Return the index of the unique value.
*/
int Strided_Offset_N_Search(int *dev_Array, int uniqueValue, int offset, int arraySize){
// Initialize foundIndex integer.
int foundIndex = -1;
// Initialize foundIndex device pointer.
int *dev_foundIndex;
// Allocate memory on device for foundIndex.
hipMalloc((void**)&dev_foundIndex, sizeof(int));
// Copy foundIndex initialized value to device.
hipMemcpy(dev_foundIndex, &foundIndex, sizeof(int), hipMemcpyHostToDevice);
// Calculate the number of threads expected.
int numOfThreads = arraySize / offset + 1;
// Initiaize CUDA event timers.
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// Initialize blocksize as the number of threads.
dim3 blockSize(MAX_BLOCKSIZE, 1, 1);
dim3 gridSize(numOfThreads / MAX_BLOCKSIZE + 1, 1);
// Launch device Strided_Offset_N_Search kernel routine and start and stop event timers.
hipEventRecord(start);
dev_Strided_Offset_N_Search<<<gridSize, blockSize>>>(dev_Array, uniqueValue, offset, arraySize, dev_foundIndex);
hipEventRecord(stop);
// Retrieve kernel timing.
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
// Print event timing.
std::cout << offset << " " << milliseconds << std::endl;
// Copy d_foundIndex device value back to host memory.
hipMemcpy(&foundIndex, dev_foundIndex, sizeof(int), hipMemcpyDeviceToHost);
// Return found index.
return foundIndex;
}
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
/// 2. Coalesced N Element Search ///
////////////////////////////////////////////////////////////////////////////////
/**
* Searches dev_Array for the given unique value by having each thread search adjacent to each other in
* a coalesced fashion, followed by searching adjacent to the other threads again but offset by the total
* number of threads.
* @param dev_Array Array in device memory to be searched.
* @param uniqueValue Unique value to be searched for.
* @param numToCheck Number of elements each thread will check.
* @param numOfThreads Total number of threads searching the array.
* @param arraySize Number of elements in the given array to search.
* @param dev_foundIndex Output index of the found unique value.
*/
__global__ void dev_Coalesced_N_Search(int *dev_Array, int uniqueValue, int numToCheck, int numOfThreads, int arraySize, int *dev_foundIndex){
// Calculate thread id.
int tid = blockDim.x * blockIdx.x + threadIdx.x;
// Initialize currentValue and actualIndex to register memory.
int currentValue, actualIndex;
// Iterate through offset N number of adjacent elements.
for (int N = 0; N < numToCheck; N++){
// Calculate actual array index.
actualIndex = numOfThreads * N + tid;
// Ensure thread is not out of bounds.
if ( actualIndex < arraySize ) {
// Retrieve current value from global memory to be checked.
currentValue = dev_Array[actualIndex];
// Check if current value is the unique value.
if ( currentValue == uniqueValue ) {
// Unique value found, store its index in the foundIndex global memory variable.
*dev_foundIndex = actualIndex;
}
}
}
}
/**
* Wrapper function to call the CUDA kernel device function dev_Coalesced_N_Search.
* @param dev_Array Array in device memory to be searched.
* @param uniqueValue Unique value to be searched for.
* @param numToCheck Number of elements each thread will check.
* @param arraySize Number of elements in the given array to search.
* @return Return the index of the unique value.
*/
int Coalesced_N_Search(int *dev_Array, int uniqueValue, int numToCheck, int arraySize) {
// Initialize foundIndex integer.
int foundIndex = -1;
// Initialize foundIndex device pointer.
int *dev_foundIndex;
// Allocate memory on device for foundIndex.
hipMalloc((void**)&dev_foundIndex, sizeof(int));
// Copy foundIndex initialized value to device.
hipMemcpy(dev_foundIndex, &foundIndex, sizeof(int), hipMemcpyHostToDevice);
// Calculate the number of threads expected.
int numOfThreads = arraySize / numToCheck + 1;
// Initiaize CUDA event timers.
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// Initialize blocksize as the number of threads.
dim3 blockSize(MAX_BLOCKSIZE, 1, 1);
dim3 gridSize(numOfThreads / MAX_BLOCKSIZE + 1, 1);
// Launch device Strided_Offset_N_Search kernel routine and start and stop event timers.
hipEventRecord(start);
dev_Coalesced_N_Search<<<gridSize, blockSize>>>(dev_Array, uniqueValue, numToCheck, numOfThreads, arraySize, dev_foundIndex);
hipEventRecord(stop);
// Retrieve kernel timing.
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
// Print event timing.
std::cout << numToCheck << " " << milliseconds << std::endl;
// Copy d_foundIndex device value back to host memory.
hipMemcpy(&foundIndex, dev_foundIndex, sizeof(int), hipMemcpyDeviceToHost);
// Return found index.
return foundIndex;
}
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
/// 3. Unrolled Coalesced N Element Search ///
////////////////////////////////////////////////////////////////////////////////
/**
* Searches dev_Array for the given unique value by having each thread search adjacent to each other in
* a coalesced fashion, followed by searching adjacent to the other threads again but offset by the total
* number of threads. All for loops are unrolled with #pragma.
* @param dev_Array Array in device memory to be searched.
* @param uniqueValue Unique value to be searched for.
* @param numToCheck Number of elements each thread will check.
* @param numOfThreads Total number of threads searching the array.
* @param arraySize Number of elements in the given array to search.
* @param dev_foundIndex Output index of the found unique value.
*/
__global__ void dev_Unrolled_Coalesced_N_Search(int *dev_Array, int uniqueValue, int numToCheck, int numOfThreads, int arraySize, int *dev_foundIndex){
// Calculate thread id.
int tid = blockDim.x * blockIdx.x + threadIdx.x;
// Initialize currentValue and actualIndex to register memory.
int currentValue, actualIndex;
// Iterate through offset N number of adjacent elements.
#pragma unroll
for (int N = 0; N < numToCheck; N++){
// Calculate actual array index.
actualIndex = numOfThreads * N + tid;
// Ensure thread is not out of bounds.
if ( actualIndex < arraySize ) {
// Retrieve current value from global memory to be checked.
currentValue = dev_Array[actualIndex];
// Check if current value is the unique value.
if ( currentValue == uniqueValue ) {
// Unique value found, store its index in the foundIndex global memory variable.
*dev_foundIndex = actualIndex;
}
}
}
}
/**
* Wrapper function to call the CUDA kernel device function dev_Coalesced_N_Search.
* @param dev_Array Array in device memory to be searched.
* @param uniqueValue Unique value to be searched for.
* @param numToCheck Number of elements each thread will check.
* @param arraySize Number of elements in the given array to search.
* @return Return the index of the unique value.
*/
int Unrolled_Coalesced_N_Search(int *dev_Array, int uniqueValue, int numToCheck, int arraySize) {
// Initialize foundIndex integer.
int foundIndex = -1;
// Initialize foundIndex device pointer.
int *dev_foundIndex;
// Allocate memory on device for foundIndex.
hipMalloc((void**)&dev_foundIndex, sizeof(int));
// Copy foundIndex initialized value to device.
hipMemcpy(dev_foundIndex, &foundIndex, sizeof(int), hipMemcpyHostToDevice);
// Calculate the number of threads expected.
int numOfThreads = arraySize / numToCheck + 1;
// Initiaize CUDA event timers.
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// Initialize blocksize as the number of threads.
dim3 blockSize(MAX_BLOCKSIZE, 1, 1);
dim3 gridSize(numOfThreads / MAX_BLOCKSIZE + 1, 1);
// Launch device Strided_Offset_N_Search kernel routine and start and stop event timers.
hipEventRecord(start);
dev_Unrolled_Coalesced_N_Search<<<gridSize, blockSize>>>(dev_Array, uniqueValue, numToCheck, numOfThreads, arraySize, dev_foundIndex);
hipEventRecord(stop);
// Retrieve kernel timing.
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
// Print event timing.
std::cout << numToCheck << " " << milliseconds << std::endl;
// Copy d_foundIndex device value back to host memory.
hipMemcpy(&foundIndex, dev_foundIndex, sizeof(int), hipMemcpyDeviceToHost);
// Return found index.
return foundIndex;
}
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
/// 4. Full Coalesced Element Search ///
////////////////////////////////////////////////////////////////////////////////
/**
* Searches dev_Array for the given unique value by having each thread search adjacent to each other in
* a coalesced fashion.
* @param dev_Array Array in device memory to be searched.
* @param uniqueValue Unique value to be searched for.
* @param arraySize Number of elements in the given array to search.
* @param dev_foundIndex Output index of the found unique value.
*/
__global__ void dev_Full_Coalesced_Search(int *dev_Array, int uniqueValue, int arraySize, int *dev_foundIndex){
// Calculate thread id.
int tid = blockDim.x * blockIdx.x + threadIdx.x;
// Retrieve current value from global memory to be checked.
int currentValue = dev_Array[tid];
// Check if current value is the unique value.
if ( currentValue == uniqueValue ) {
// Unique value found, store its index in the foundIndex global memory variable.
*dev_foundIndex = tid;
}
}
/**
* Wrapper function to call the CUDA kernel device function dev_Coalesced_N_Search.
* @param dev_Array Array in device memory to be searched.
* @param uniqueValue Unique value to be searched for.
* @param arraySize Number of elements in the given array to search.
* @return Return the index of the unique value.
*/
int Full_Coalesced_Search(int *dev_Array, int uniqueValue, int arraySize) {
// Initialize foundIndex integer.
int foundIndex = -1;
// Initialize foundIndex device pointer.
int *dev_foundIndex;
// Allocate memory on device for foundIndex.
hipMalloc((void**)&dev_foundIndex, sizeof(int));
// Copy foundIndex initialized value to device.
hipMemcpy(dev_foundIndex, &foundIndex, sizeof(int), hipMemcpyHostToDevice);
// Calculate the number of threads expected.
int numOfThreads = arraySize;
// Initiaize CUDA event timers.
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// Initialize blocksize as the number of threads.
dim3 blockSize(MAX_BLOCKSIZE, 1, 1);
dim3 gridSize(numOfThreads / MAX_BLOCKSIZE + 1, 1);
// Launch device Strided_Offset_N_Search kernel routine and start and stop event timers.
hipEventRecord(start);
dev_Full_Coalesced_Search<<<gridSize, blockSize>>>(dev_Array, uniqueValue, arraySize, dev_foundIndex);
hipEventRecord(stop);
// Retrieve kernel timing.
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
// Print event timing.
std::cout << "1" << " " << milliseconds << std::endl;
// Copy d_foundIndex device value back to host memory.
hipMemcpy(&foundIndex, dev_foundIndex, sizeof(int), hipMemcpyDeviceToHost);
// Return found index.
return foundIndex;
}
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
int main(){
// Define unique value to search for.
const int uniqueValue = 5;
// Define random index the unique value will be for constructing the searchable array.
const int randomIndex = 68;
// Define the size of our array.
const int arraySize = 500000;
// Initialize test array that we will search.
int testArray[arraySize];
// Set array to all zeros.
for (int i = 0; i < arraySize; i++){
testArray[i] = 0;
}
// Set random index to value to search for.
testArray[randomIndex] = uniqueValue;
// CUDA ALLOCATIONS //
// Initialize device pointers.
int *d_testArray, d_foundIndex;
// Allocate memory for local variables on the GPU device.
hipMalloc((void**)&d_testArray, arraySize * sizeof(int));
hipMalloc((void**)&d_foundIndex, sizeof(int));
// Transfer test array from local host memory to device.
hipMemcpy(d_testArray, testArray, arraySize * sizeof(int), hipMemcpyHostToDevice);
// Find unique values //
int foundIndex = -1;
//////////////////////////////////////////////////////////////////////////////////////////////////////
// 1. Each thread searches through N adjacent elements where each thread begins its search N elements
// from the previous thread's starting position. If a thread successfully locates the unique value, it
// write the index of the element to memory.
//////////////////////////////////////////////////////////////////////////////////////////////////////
// Test multiple offset sizes.
std::cout << "-- Strided Offset N Search --" << std::endl;
int offset = 1;
for (int offset = 1; offset < 65; offset+=1) {
foundIndex = Strided_Offset_N_Search(d_testArray, uniqueValue, offset, arraySize);
}
// Print out index of found unique value.
std::cout << "Located unique value at index = " << foundIndex << std::endl;
/////////////////////////////////////////////////////////////////////////////////////////////////////
// 2. Each thread searches through N elements in a coalesced fashion where each thread begins its search
// adjacent to the previous and following threads starting positions. From there, the threads search the
// value which is the total number of threads offset from the current position, so that all threads are
// still making coalesced memory calls.
/////////////////////////////////////////////////////////////////////////////////////////////////////
// Test multiple values of N, where N is the number of elements each thread will check.
std::cout << "-- Coalesced N Search --" << std::endl;
int numToCheck = 1;
for (int numToCheck = 1; numToCheck < 65; numToCheck+=1) {
foundIndex = Coalesced_N_Search(d_testArray, uniqueValue, numToCheck, arraySize);
}
// Print out index of found unique value.
std::cout << "Located unique value at index = " << foundIndex << std::endl;
/////////////////////////////////////////////////////////////////////////////////////////////////////
// 3. Each thread searches through N elements in a coalesced fashion where each thread begins its search
// adjacent to the previous and following threads starting positions. From there, the threads search the
// value which is the total number of threads offset from the current position, so that all threads are
// still making coalesced memory calls. For loop is unroll with #pragma.
/////////////////////////////////////////////////////////////////////////////////////////////////////
// Test multiple values of N, where N is the number of elements each thread will check.
std::cout << "-- Unrolled Coalesced N Search --" << std::endl;
for (int numToCheck = 1; numToCheck < 65; numToCheck+=1) {
foundIndex = Unrolled_Coalesced_N_Search(d_testArray, uniqueValue, 12, arraySize);
}
// Print out index of found unique value.
std::cout << "Located unique value at index = " << foundIndex << std::endl;
///////////////////////////////////////////////////////////////////////////////////////////////////
// 4. Each thread searches a single elements in a coalesced fashion where each thread begins its search
// adjacent to the previous and following threads starting positions.
///////////////////////////////////////////////////////////////////////////////////////////////////
// Test multiple values of N, where N is the number of elements each thread will check.
std::cout << "-- Full Coalesced Search --" << std::endl;
for (int offset = 1; offset < 65; offset+=1) {
foundIndex = Full_Coalesced_Search(d_testArray, uniqueValue, arraySize);
}
// Print out index of found unique value.
std::cout << "Located unique value at index = " << foundIndex << std::endl;
} | .text
.file "Test_Search_Unique_Value_CUDA.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z42__device_stub__dev_Strided_Offset_N_SearchPiiiiS_ # -- Begin function _Z42__device_stub__dev_Strided_Offset_N_SearchPiiiiS_
.p2align 4, 0x90
.type _Z42__device_stub__dev_Strided_Offset_N_SearchPiiiiS_,@function
_Z42__device_stub__dev_Strided_Offset_N_SearchPiiiiS_: # @_Z42__device_stub__dev_Strided_Offset_N_SearchPiiiiS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %r8, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z27dev_Strided_Offset_N_SearchPiiiiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z42__device_stub__dev_Strided_Offset_N_SearchPiiiiS_, .Lfunc_end0-_Z42__device_stub__dev_Strided_Offset_N_SearchPiiiiS_
.cfi_endproc
# -- End function
.globl _Z23Strided_Offset_N_SearchPiiii # -- Begin function _Z23Strided_Offset_N_SearchPiiii
.p2align 4, 0x90
.type _Z23Strided_Offset_N_SearchPiiii,@function
_Z23Strided_Offset_N_SearchPiiii: # @_Z23Strided_Offset_N_SearchPiiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movl %edx, %ebx
movl %esi, %r14d
movq %rdi, %r15
movl $-1, 4(%rsp)
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 4(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movl %ebp, %eax
cltd
idivl %ebx
movl %eax, %r12d
leal 1(%r12), %r13d
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
addl $512, %r12d # imm = 0x200
testl %r13d, %r13d
cmovnsl %r13d, %r12d
sarl $9, %r12d
incl %r12d
movabsq $4294967296, %r13 # imm = 0x100000000
orq %r13, %r12
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
orq $512, %r13 # imm = 0x200
movq %r12, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq %r15, 104(%rsp)
movl %r14d, 36(%rsp)
movl %ebx, 32(%rsp)
movl %ebp, 28(%rsp)
movq %rax, 96(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 96(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z27dev_Strided_Offset_N_SearchPiiiiS_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movl $0, 112(%rsp)
movq 40(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 112(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 112(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %rbx, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_7
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_5
# %bb.4:
movzbl 67(%rbx), %ecx
jmp .LBB1_6
.LBB1_5:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rsi
leaq 4(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl 4(%rsp), %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_7:
.cfi_def_cfa_offset 208
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size _Z23Strided_Offset_N_SearchPiiii, .Lfunc_end1-_Z23Strided_Offset_N_SearchPiiii
.cfi_endproc
# -- End function
.globl _Z37__device_stub__dev_Coalesced_N_SearchPiiiiiS_ # -- Begin function _Z37__device_stub__dev_Coalesced_N_SearchPiiiiiS_
.p2align 4, 0x90
.type _Z37__device_stub__dev_Coalesced_N_SearchPiiiiiS_,@function
_Z37__device_stub__dev_Coalesced_N_SearchPiiiiiS_: # @_Z37__device_stub__dev_Coalesced_N_SearchPiiiiiS_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %r9, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22dev_Coalesced_N_SearchPiiiiiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end2:
.size _Z37__device_stub__dev_Coalesced_N_SearchPiiiiiS_, .Lfunc_end2-_Z37__device_stub__dev_Coalesced_N_SearchPiiiiiS_
.cfi_endproc
# -- End function
.globl _Z18Coalesced_N_SearchPiiii # -- Begin function _Z18Coalesced_N_SearchPiiii
.p2align 4, 0x90
.type _Z18Coalesced_N_SearchPiiii,@function
_Z18Coalesced_N_SearchPiiii: # @_Z18Coalesced_N_SearchPiiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movl %edx, %ebx
movl %esi, 36(%rsp) # 4-byte Spill
movq %rdi, %r15
movl $-1, 12(%rsp)
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 24(%rsp), %rdi
leaq 12(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movl %ebp, %eax
cltd
idivl %ebx
movl %eax, %r12d
leal 1(%r12), %r14d
leaq 56(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
addl $512, %r12d # imm = 0x200
testl %r14d, %r14d
cmovnsl %r14d, %r12d
sarl $9, %r12d
incl %r12d
movabsq $4294967296, %r13 # imm = 0x100000000
orq %r13, %r12
movq 56(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
orq $512, %r13 # imm = 0x200
movq %r12, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq 24(%rsp), %rax
movq %r15, 120(%rsp)
movl 36(%rsp), %ecx # 4-byte Reload
movl %ecx, 52(%rsp)
movl %ebx, 48(%rsp)
movl %r14d, 44(%rsp)
movl %ebp, 40(%rsp)
movq %rax, 112(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 52(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rax
movq %rax, 144(%rsp)
leaq 44(%rsp), %rax
movq %rax, 152(%rsp)
leaq 40(%rsp), %rax
movq %rax, 160(%rsp)
leaq 112(%rsp), %rax
movq %rax, 168(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z22dev_Coalesced_N_SearchPiiiiiS_, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movl $0, 128(%rsp)
movq 56(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 128(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 128(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %rbx, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB3_7
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB3_5
# %bb.4:
movzbl 67(%rbx), %ecx
jmp .LBB3_6
.LBB3_5:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB3_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 24(%rsp), %rsi
leaq 12(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl 12(%rsp), %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_7:
.cfi_def_cfa_offset 240
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size _Z18Coalesced_N_SearchPiiii, .Lfunc_end3-_Z18Coalesced_N_SearchPiiii
.cfi_endproc
# -- End function
.globl _Z46__device_stub__dev_Unrolled_Coalesced_N_SearchPiiiiiS_ # -- Begin function _Z46__device_stub__dev_Unrolled_Coalesced_N_SearchPiiiiiS_
.p2align 4, 0x90
.type _Z46__device_stub__dev_Unrolled_Coalesced_N_SearchPiiiiiS_,@function
_Z46__device_stub__dev_Unrolled_Coalesced_N_SearchPiiiiiS_: # @_Z46__device_stub__dev_Unrolled_Coalesced_N_SearchPiiiiiS_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %r9, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z31dev_Unrolled_Coalesced_N_SearchPiiiiiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end4:
.size _Z46__device_stub__dev_Unrolled_Coalesced_N_SearchPiiiiiS_, .Lfunc_end4-_Z46__device_stub__dev_Unrolled_Coalesced_N_SearchPiiiiiS_
.cfi_endproc
# -- End function
.globl _Z27Unrolled_Coalesced_N_SearchPiiii # -- Begin function _Z27Unrolled_Coalesced_N_SearchPiiii
.p2align 4, 0x90
.type _Z27Unrolled_Coalesced_N_SearchPiiii,@function
_Z27Unrolled_Coalesced_N_SearchPiiii: # @_Z27Unrolled_Coalesced_N_SearchPiiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movl %edx, %ebx
movl %esi, 36(%rsp) # 4-byte Spill
movq %rdi, %r15
movl $-1, 12(%rsp)
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 24(%rsp), %rdi
leaq 12(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movl %ebp, %eax
cltd
idivl %ebx
movl %eax, %r12d
leal 1(%r12), %r14d
leaq 56(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
addl $512, %r12d # imm = 0x200
testl %r14d, %r14d
cmovnsl %r14d, %r12d
sarl $9, %r12d
incl %r12d
movabsq $4294967296, %r13 # imm = 0x100000000
orq %r13, %r12
movq 56(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
orq $512, %r13 # imm = 0x200
movq %r12, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_2
# %bb.1:
movq 24(%rsp), %rax
movq %r15, 120(%rsp)
movl 36(%rsp), %ecx # 4-byte Reload
movl %ecx, 52(%rsp)
movl %ebx, 48(%rsp)
movl %r14d, 44(%rsp)
movl %ebp, 40(%rsp)
movq %rax, 112(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 52(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rax
movq %rax, 144(%rsp)
leaq 44(%rsp), %rax
movq %rax, 152(%rsp)
leaq 40(%rsp), %rax
movq %rax, 160(%rsp)
leaq 112(%rsp), %rax
movq %rax, 168(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z31dev_Unrolled_Coalesced_N_SearchPiiiiiS_, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_2:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movl $0, 128(%rsp)
movq 56(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 128(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 128(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %rbx, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB5_7
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB5_5
# %bb.4:
movzbl 67(%rbx), %ecx
jmp .LBB5_6
.LBB5_5:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB5_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 24(%rsp), %rsi
leaq 12(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl 12(%rsp), %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB5_7:
.cfi_def_cfa_offset 240
callq _ZSt16__throw_bad_castv
.Lfunc_end5:
.size _Z27Unrolled_Coalesced_N_SearchPiiii, .Lfunc_end5-_Z27Unrolled_Coalesced_N_SearchPiiii
.cfi_endproc
# -- End function
.globl _Z40__device_stub__dev_Full_Coalesced_SearchPiiiS_ # -- Begin function _Z40__device_stub__dev_Full_Coalesced_SearchPiiiS_
.p2align 4, 0x90
.type _Z40__device_stub__dev_Full_Coalesced_SearchPiiiS_,@function
_Z40__device_stub__dev_Full_Coalesced_SearchPiiiS_: # @_Z40__device_stub__dev_Full_Coalesced_SearchPiiiS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z25dev_Full_Coalesced_SearchPiiiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end6:
.size _Z40__device_stub__dev_Full_Coalesced_SearchPiiiS_, .Lfunc_end6-_Z40__device_stub__dev_Full_Coalesced_SearchPiiiS_
.cfi_endproc
# -- End function
.globl _Z21Full_Coalesced_SearchPiii # -- Begin function _Z21Full_Coalesced_SearchPiii
.p2align 4, 0x90
.type _Z21Full_Coalesced_SearchPiii,@function
_Z21Full_Coalesced_SearchPiii: # @_Z21Full_Coalesced_SearchPiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movl %esi, %ebp
movq %rdi, %r14
movl $-1, 12(%rsp)
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 24(%rsp), %rdi
leaq 12(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
leal 511(%rbx), %r15d
testl %ebx, %ebx
cmovnsl %ebx, %r15d
sarl $9, %r15d
incl %r15d
movabsq $4294967296, %r12 # imm = 0x100000000
orq %r12, %r15
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
orq $512, %r12 # imm = 0x200
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_2
# %bb.1:
movq 24(%rsp), %rax
movq %r14, 136(%rsp)
movl %ebp, 36(%rsp)
movl %ebx, 32(%rsp)
movq %rax, 128(%rsp)
leaq 136(%rsp), %rax
movq %rax, 48(%rsp)
leaq 36(%rsp), %rax
movq %rax, 56(%rsp)
leaq 32(%rsp), %rax
movq %rax, 64(%rsp)
leaq 128(%rsp), %rax
movq %rax, 72(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z25dev_Full_Coalesced_SearchPiiiS_, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_2:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movl $0, 48(%rsp)
movq 40(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB7_7
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB7_5
# %bb.4:
movzbl 67(%rbx), %ecx
jmp .LBB7_6
.LBB7_5:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB7_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 24(%rsp), %rsi
leaq 12(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl 12(%rsp), %eax
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB7_7:
.cfi_def_cfa_offset 192
callq _ZSt16__throw_bad_castv
.Lfunc_end7:
.size _Z21Full_Coalesced_SearchPiii, .Lfunc_end7-_Z21Full_Coalesced_SearchPiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $2000024, %rsp # imm = 0x1E8498
.cfi_def_cfa_offset 2000048
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 16(%rsp), %rbx
movl $2000000, %edx # imm = 0x1E8480
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
movl $5, 288(%rsp)
movq %rsp, %rdi
movl $2000000, %esi # imm = 0x1E8480
callq hipMalloc
leaq 12(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq (%rsp), %rdi
movl $2000000, %edx # imm = 0x1E8480
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $29, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB8_41
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB8_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB8_4
.LBB8_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB8_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $1, %ebx
.p2align 4, 0x90
.LBB8_5: # =>This Inner Loop Header: Depth=1
movq (%rsp), %rdi
movl $5, %esi
movl %ebx, %edx
movl $500000, %ecx # imm = 0x7A120
callq _Z23Strided_Offset_N_SearchPiiii
incl %ebx
cmpl $65, %ebx
jne .LBB8_5
# %bb.6:
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $32, %edx
movl %eax, %ebx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB8_41
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i24
cmpb $0, 56(%rbx)
je .LBB8_9
# %bb.8:
movzbl 67(%rbx), %ecx
jmp .LBB8_10
.LBB8_9:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB8_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit27
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $24, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB8_41
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i29
cmpb $0, 56(%rbx)
je .LBB8_13
# %bb.12:
movzbl 67(%rbx), %eax
jmp .LBB8_14
.LBB8_13:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB8_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit32
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $1, %ebx
.p2align 4, 0x90
.LBB8_15: # =>This Inner Loop Header: Depth=1
movq (%rsp), %rdi
movl $5, %esi
movl %ebx, %edx
movl $500000, %ecx # imm = 0x7A120
callq _Z18Coalesced_N_SearchPiiii
incl %ebx
cmpl $65, %ebx
jne .LBB8_15
# %bb.16:
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $32, %edx
movl %eax, %ebx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB8_41
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i34
cmpb $0, 56(%rbx)
je .LBB8_19
# %bb.18:
movzbl 67(%rbx), %ecx
jmp .LBB8_20
.LBB8_19:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB8_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit37
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $33, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB8_41
# %bb.21: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i39
cmpb $0, 56(%rbx)
je .LBB8_23
# %bb.22:
movzbl 67(%rbx), %eax
jmp .LBB8_24
.LBB8_23:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB8_24: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit42
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $64, %ebx
.p2align 4, 0x90
.LBB8_25: # =>This Inner Loop Header: Depth=1
movq (%rsp), %rdi
movl $5, %esi
movl $12, %edx
movl $500000, %ecx # imm = 0x7A120
callq _Z27Unrolled_Coalesced_N_SearchPiiii
decl %ebx
jne .LBB8_25
# %bb.26:
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $32, %edx
movl %eax, %ebx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB8_41
# %bb.27: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i44
cmpb $0, 56(%rbx)
je .LBB8_29
# %bb.28:
movzbl 67(%rbx), %ecx
jmp .LBB8_30
.LBB8_29:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB8_30: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit47
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $27, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB8_41
# %bb.31: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i49
cmpb $0, 56(%rbx)
je .LBB8_33
# %bb.32:
movzbl 67(%rbx), %eax
jmp .LBB8_34
.LBB8_33:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB8_34: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit52
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $64, %ebx
.p2align 4, 0x90
.LBB8_35: # =>This Inner Loop Header: Depth=1
movq (%rsp), %rdi
movl $5, %esi
movl $500000, %edx # imm = 0x7A120
callq _Z21Full_Coalesced_SearchPiii
decl %ebx
jne .LBB8_35
# %bb.36:
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $32, %edx
movl %eax, %ebx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB8_41
# %bb.37: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i54
cmpb $0, 56(%rbx)
je .LBB8_39
# %bb.38:
movzbl 67(%rbx), %ecx
jmp .LBB8_40
.LBB8_39:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB8_40: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit57
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $2000024, %rsp # imm = 0x1E8498
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB8_41:
.cfi_def_cfa_offset 2000048
callq _ZSt16__throw_bad_castv
.Lfunc_end8:
.size main, .Lfunc_end8-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB9_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB9_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27dev_Strided_Offset_N_SearchPiiiiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22dev_Coalesced_N_SearchPiiiiiS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z31dev_Unrolled_Coalesced_N_SearchPiiiiiS_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25dev_Full_Coalesced_SearchPiiiS_, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end9:
.size __hip_module_ctor, .Lfunc_end9-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB10_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB10_2:
retq
.Lfunc_end10:
.size __hip_module_dtor, .Lfunc_end10-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z27dev_Strided_Offset_N_SearchPiiiiS_,@object # @_Z27dev_Strided_Offset_N_SearchPiiiiS_
.section .rodata,"a",@progbits
.globl _Z27dev_Strided_Offset_N_SearchPiiiiS_
.p2align 3, 0x0
_Z27dev_Strided_Offset_N_SearchPiiiiS_:
.quad _Z42__device_stub__dev_Strided_Offset_N_SearchPiiiiS_
.size _Z27dev_Strided_Offset_N_SearchPiiiiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type _Z22dev_Coalesced_N_SearchPiiiiiS_,@object # @_Z22dev_Coalesced_N_SearchPiiiiiS_
.section .rodata,"a",@progbits
.globl _Z22dev_Coalesced_N_SearchPiiiiiS_
.p2align 3, 0x0
_Z22dev_Coalesced_N_SearchPiiiiiS_:
.quad _Z37__device_stub__dev_Coalesced_N_SearchPiiiiiS_
.size _Z22dev_Coalesced_N_SearchPiiiiiS_, 8
.type _Z31dev_Unrolled_Coalesced_N_SearchPiiiiiS_,@object # @_Z31dev_Unrolled_Coalesced_N_SearchPiiiiiS_
.globl _Z31dev_Unrolled_Coalesced_N_SearchPiiiiiS_
.p2align 3, 0x0
_Z31dev_Unrolled_Coalesced_N_SearchPiiiiiS_:
.quad _Z46__device_stub__dev_Unrolled_Coalesced_N_SearchPiiiiiS_
.size _Z31dev_Unrolled_Coalesced_N_SearchPiiiiiS_, 8
.type _Z25dev_Full_Coalesced_SearchPiiiS_,@object # @_Z25dev_Full_Coalesced_SearchPiiiS_
.globl _Z25dev_Full_Coalesced_SearchPiiiS_
.p2align 3, 0x0
_Z25dev_Full_Coalesced_SearchPiiiS_:
.quad _Z40__device_stub__dev_Full_Coalesced_SearchPiiiS_
.size _Z25dev_Full_Coalesced_SearchPiiiS_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "1"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "-- Strided Offset N Search --"
.size .L.str.2, 30
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Located unique value at index = "
.size .L.str.3, 33
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "-- Coalesced N Search --"
.size .L.str.4, 25
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "-- Unrolled Coalesced N Search --"
.size .L.str.5, 34
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "-- Full Coalesced Search --"
.size .L.str.6, 28
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z27dev_Strided_Offset_N_SearchPiiiiS_"
.size .L__unnamed_1, 39
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z22dev_Coalesced_N_SearchPiiiiiS_"
.size .L__unnamed_2, 35
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z31dev_Unrolled_Coalesced_N_SearchPiiiiiS_"
.size .L__unnamed_3, 44
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z25dev_Full_Coalesced_SearchPiiiS_"
.size .L__unnamed_4, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z42__device_stub__dev_Strided_Offset_N_SearchPiiiiS_
.addrsig_sym _Z37__device_stub__dev_Coalesced_N_SearchPiiiiiS_
.addrsig_sym _Z46__device_stub__dev_Unrolled_Coalesced_N_SearchPiiiiiS_
.addrsig_sym _Z40__device_stub__dev_Full_Coalesced_SearchPiiiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z27dev_Strided_Offset_N_SearchPiiiiS_
.addrsig_sym _ZSt4cout
.addrsig_sym _Z22dev_Coalesced_N_SearchPiiiiiS_
.addrsig_sym _Z31dev_Unrolled_Coalesced_N_SearchPiiiiiS_
.addrsig_sym _Z25dev_Full_Coalesced_SearchPiiiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | extern "C" __global__ void sum ( const float *A
, const float *B
, float *C
, int N
)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i<N) {
C[i] = A[i] + B[i];
}
} | code for sm_80
Function : sum
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C" __global__ void sum ( const float *A
, const float *B
, float *C
, int N
)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i<N) {
C[i] = A[i] + B[i];
}
} | .file "tmpxft_00169dcd_00000000-6_sum_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z3sumPKfS0_PfiPKfS0_Pfi
.type _Z29__device_stub__Z3sumPKfS0_PfiPKfS0_Pfi, @function
_Z29__device_stub__Z3sumPKfS0_PfiPKfS0_Pfi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq sum(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z3sumPKfS0_PfiPKfS0_Pfi, .-_Z29__device_stub__Z3sumPKfS0_PfiPKfS0_Pfi
.globl sum
.type sum, @function
sum:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z3sumPKfS0_PfiPKfS0_Pfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size sum, .-sum
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "sum"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq sum(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C" __global__ void sum ( const float *A
, const float *B
, float *C
, int N
)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i<N) {
C[i] = A[i] + B[i];
}
} | #include <hip/hip_runtime.h>
extern "C" __global__ void sum ( const float *A
, const float *B
, float *C
, int N
)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i<N) {
C[i] = A[i] + B[i];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C" __global__ void sum ( const float *A
, const float *B
, float *C
, int N
)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i<N) {
C[i] = A[i] + B[i];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected sum
.globl sum
.p2align 8
.type sum,@function
sum:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel sum
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size sum, .Lfunc_end0-sum
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: sum
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: sum.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C" __global__ void sum ( const float *A
, const float *B
, float *C
, int N
)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i<N) {
C[i] = A[i] + B[i];
}
} | .text
.file "sum_kernel.hip"
.globl __device_stub__sum # -- Begin function __device_stub__sum
.p2align 4, 0x90
.type __device_stub__sum,@function
__device_stub__sum: # @__device_stub__sum
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $sum, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__sum, .Lfunc_end0-__device_stub__sum
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $sum, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type sum,@object # @sum
.section .rodata,"a",@progbits
.globl sum
.p2align 3, 0x0
sum:
.quad __device_stub__sum
.size sum, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "sum"
.size .L__unnamed_1, 4
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__sum
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym sum
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : sum
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected sum
.globl sum
.p2align 8
.type sum,@function
sum:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel sum
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size sum, .Lfunc_end0-sum
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: sum
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: sum.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00169dcd_00000000-6_sum_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z3sumPKfS0_PfiPKfS0_Pfi
.type _Z29__device_stub__Z3sumPKfS0_PfiPKfS0_Pfi, @function
_Z29__device_stub__Z3sumPKfS0_PfiPKfS0_Pfi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq sum(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z3sumPKfS0_PfiPKfS0_Pfi, .-_Z29__device_stub__Z3sumPKfS0_PfiPKfS0_Pfi
.globl sum
.type sum, @function
sum:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z3sumPKfS0_PfiPKfS0_Pfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size sum, .-sum
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "sum"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq sum(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sum_kernel.hip"
.globl __device_stub__sum # -- Begin function __device_stub__sum
.p2align 4, 0x90
.type __device_stub__sum,@function
__device_stub__sum: # @__device_stub__sum
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $sum, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__sum, .Lfunc_end0-__device_stub__sum
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $sum, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type sum,@object # @sum
.section .rodata,"a",@progbits
.globl sum
.p2align 3, 0x0
sum:
.quad __device_stub__sum
.size sum, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "sum"
.size .L__unnamed_1, 4
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__sum
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym sum
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void cuda_sgemm(float* matrix_a, float* matrix_b, float* matrix_c, size_t M, size_t K, size_t N) {
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float sum = 0;
if (col < N && row < M) {
for (int k = 0; k < K; k++) {
sum +=
matrix_a[INDEX(row, k, M, K)] * matrix_b[INDEX(k, col, K, N)];
}
matrix_c[INDEX(row, col, M, N)] = sum;
}
} | code for sm_80
Function : _Z10cuda_sgemmPfS_S_mmm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R10, SR_CTAID.X ; /* 0x00000000000a7919 */
/* 0x000e280000002500 */
/*0020*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000e280000002100 */
/*0030*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R10, R10, c[0x0][0x0], R11 ; /* 0x000000000a0a7a24 */
/* 0x001fca00078e020b */
/*0060*/ ISETP.GE.U32.AND P0, PT, R10, c[0x0][0x188], PT ; /* 0x000062000a007a0c */
/* 0x000fe40003f06070 */
/*0070*/ SHF.R.S32.HI R11, RZ, 0x1f, R10 ; /* 0x0000001fff0b7819 */
/* 0x000fe2000001140a */
/*0080*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x002fc600078e0203 */
/*0090*/ ISETP.GE.U32.AND.EX P0, PT, R11, c[0x0][0x18c], PT, P0 ; /* 0x000063000b007a0c */
/* 0x000fe40003f06100 */
/*00a0*/ ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe40003f26070 */
/*00b0*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x000fc80000011400 */
/*00c0*/ ISETP.GE.U32.OR.EX P0, PT, R2, c[0x0][0x17c], P0, P1 ; /* 0x00005f0002007a0c */
/* 0x000fda0000706510 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x180], PT ; /* 0x00006000ff007a0c */
/* 0x000fe20003f05070 */
/*00f0*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0100*/ IMAD.MOV.U32 R29, RZ, RZ, RZ ; /* 0x000000ffff1d7224 */
/* 0x000fe400078e00ff */
/*0110*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x184], PT, P0 ; /* 0x00006100ff007a0c */
/* 0x000fda0003f05300 */
/*0120*/ @!P0 BRA 0x1030 ; /* 0x00000f0000008947 */
/* 0x000fea0003800000 */
/*0130*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff047624 */
/* 0x000fe200078e00ff */
/*0140*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0150*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff037624 */
/* 0x000fe400078e00ff */
/*0160*/ IMAD.WIDE.U32 R12, R0, c[0x0][0x180], RZ ; /* 0x00006000000c7a25 */
/* 0x000fe200078e00ff */
/*0170*/ IADD3 R5, P1, R4, -0x1, RZ ; /* 0xffffffff04057810 */
/* 0x000fc60007f3e0ff */
/*0180*/ IMAD.MOV.U32 R29, RZ, RZ, RZ ; /* 0x000000ffff1d7224 */
/* 0x000fe200078e00ff */
/*0190*/ ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fe20003f06070 */
/*01a0*/ IMAD R5, R2, c[0x0][0x180], RZ ; /* 0x0000600002057a24 */
/* 0x000fe200078e02ff */
/*01b0*/ IADD3.X R3, R3, -0x1, RZ, P1, !PT ; /* 0xffffffff03037810 */
/* 0x000fc60000ffe4ff */
/*01c0*/ IMAD R5, R0, c[0x0][0x184], R5 ; /* 0x0000610000057a24 */
/* 0x000fe200078e0205 */
/*01d0*/ ISETP.GE.U32.AND.EX P0, PT, R3, RZ, PT, P0 ; /* 0x000000ff0300720c */
/* 0x000fe40003f06100 */
/*01e0*/ LOP3.LUT R3, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304037812 */
/* 0x000fe200078ec0ff */
/*01f0*/ IMAD.IADD R4, R13, 0x1, R5 ; /* 0x000000010d047824 */
/* 0x000fd400078e0205 */
/*0200*/ @!P0 BRA 0xe30 ; /* 0x00000c2000008947 */
/* 0x000fea0003800000 */
/*0210*/ IADD3 R5, P1, R3, -c[0x0][0x180], RZ ; /* 0x8000600003057a10 */
/* 0x000fe20007f3e0ff */
/*0220*/ UMOV UR6, 0x2 ; /* 0x0000000200067882 */
/* 0x000fe20000000000 */
/*0230*/ LEA R14, P2, R12, c[0x0][0x160], 0x2 ; /* 0x000058000c0e7a11 */
/* 0x000fe200078410ff */
/*0240*/ ULDC.64 UR4, c[0x0][0x188] ; /* 0x0000620000047ab9 */
/* 0x000fe20000000a00 */
/*0250*/ LEA R18, P0, R10, c[0x0][0x168], 0x2 ; /* 0x00005a000a127a11 */
/* 0x000fe200078010ff */
/*0260*/ IMAD.X R6, RZ, RZ, ~c[0x0][0x184], P1 ; /* 0x80006100ff067624 */
/* 0x000fe200008e06ff */
/*0270*/ USHF.L.U64.HI UR6, UR4, UR6, UR5 ; /* 0x0000000604067299 */
/* 0x000fe20008010205 */
/*0280*/ IADD3 R14, P3, R14, 0x8, RZ ; /* 0x000000080e0e7810 */
/* 0x000fe20007f7e0ff */
/*0290*/ USHF.L.U32 UR5, UR4, 0x2, URZ ; /* 0x0000000204057899 */
/* 0x000fe2000800063f */
/*02a0*/ LEA.HI.X R7, R12, c[0x0][0x164], R4, 0x2, P2 ; /* 0x000059000c077a11 */
/* 0x000fe200010f1404 */
/*02b0*/ IMAD.MOV.U32 R29, RZ, RZ, RZ ; /* 0x000000ffff1d7224 */
/* 0x000fe200078e00ff */
/*02c0*/ ISETP.GE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f26270 */
/*02d0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*02e0*/ LEA.HI.X R19, R10, c[0x0][0x16c], R11, 0x2, P0 ; /* 0x00005b000a137a11 */
/* 0x000fe200000f140b */
/*02f0*/ IMAD.X R15, RZ, RZ, R7, P3 ; /* 0x000000ffff0f7224 */
/* 0x000fd400018e0607 */
/*0300*/ @P1 BRA 0xc60 ; /* 0x0000095000001947 */
/* 0x000fea0003800000 */
/*0310*/ IADD3 R7, P0, RZ, -R5, RZ ; /* 0x80000005ff077210 */
/* 0x000fc80007f1e0ff */
/*0320*/ ISETP.GT.U32.AND P1, PT, R7, 0xc, PT ; /* 0x0000000c0700780c */
/* 0x000fe20003f24070 */
/*0330*/ IMAD.X R7, RZ, RZ, ~R6, P0 ; /* 0x000000ffff077224 */
/* 0x000fe200000e0e06 */
/*0340*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fc80003f0f070 */
/*0350*/ ISETP.GT.AND.EX P1, PT, R7, RZ, PT, P1 ; /* 0x000000ff0700720c */
/* 0x000fda0003f24310 */
/*0360*/ @!P1 BRA 0x900 ; /* 0x0000059000009947 */
/* 0x000fea0003800000 */
/*0370*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0380*/ LDG.E R27, [R14.64+-0x8] ; /* 0xfffff8080e1b7981 */
/* 0x000ea8000c1e1900 */
/*0390*/ LDG.E R16, [R18.64] ; /* 0x0000000812107981 */
/* 0x0000a8000c1e1900 */
/*03a0*/ LDG.E R28, [R14.64+-0x4] ; /* 0xfffffc080e1c7981 */
/* 0x000ee8000c1e1900 */
/*03b0*/ LDG.E R26, [R14.64] ; /* 0x000000080e1a7981 */
/* 0x000f22000c1e1900 */
/*03c0*/ IADD3 R18, P1, R18, UR5, RZ ; /* 0x0000000512127c10 */
/* 0x001fc6000ff3e0ff */
/*03d0*/ LDG.E R20, [R14.64+0x4] ; /* 0x000004080e147981 */
/* 0x000f22000c1e1900 */
/*03e0*/ IADD3.X R19, R19, UR6, RZ, P1, !PT ; /* 0x0000000613137c10 */
/* 0x000fe40008ffe4ff */
/*03f0*/ IADD3 R8, P1, R18, UR5, RZ ; /* 0x0000000512087c10 */
/* 0x000fe2000ff3e0ff */
/*0400*/ LDG.E R7, [R14.64+0x8] ; /* 0x000008080e077981 */
/* 0x000ee6000c1e1900 */
/*0410*/ IADD3.X R9, R19, UR6, RZ, P1, !PT ; /* 0x0000000613097c10 */
/* 0x000fe20008ffe4ff */
/*0420*/ LDG.E R21, [R18.64] ; /* 0x0000000812157981 */
/* 0x0000e2000c1e1900 */
/*0430*/ IADD3 R24, P1, R8, UR5, RZ ; /* 0x0000000508187c10 */
/* 0x000fc6000ff3e0ff */
/*0440*/ LDG.E R17, [R8.64] ; /* 0x0000000808117981 */
/* 0x000322000c1e1900 */
/*0450*/ IADD3.X R25, R9, UR6, RZ, P1, !PT ; /* 0x0000000609197c10 */
/* 0x000fe40008ffe4ff */
/*0460*/ IADD3 R22, P1, R24, UR5, RZ ; /* 0x0000000518167c10 */
/* 0x000fc6000ff3e0ff */
/*0470*/ LDG.E R9, [R24.64] ; /* 0x0000000818097981 */
/* 0x002322000c1e1900 */
/*0480*/ IADD3.X R23, R25, UR6, RZ, P1, !PT ; /* 0x0000000619177c10 */
/* 0x000fe40008ffe4ff */
/*0490*/ IADD3 R18, P1, R22, UR5, RZ ; /* 0x0000000516127c10 */
/* 0x001fc6000ff3e0ff */
/*04a0*/ LDG.E R8, [R22.64] ; /* 0x0000000816087981 */
/* 0x000122000c1e1900 */
/*04b0*/ IADD3.X R19, R23, UR6, RZ, P1, !PT ; /* 0x0000000617137c10 */
/* 0x000fe20008ffe4ff */
/*04c0*/ FFMA R29, R16, R27, R29 ; /* 0x0000001b101d7223 */
/* 0x004fc8000000001d */
/*04d0*/ LDG.E R27, [R18.64] ; /* 0x00000008121b7981 */
/* 0x000568000c1e1900 */
/*04e0*/ LDG.E R16, [R14.64+0xc] ; /* 0x00000c080e107981 */
/* 0x000f62000c1e1900 */
/*04f0*/ IADD3 R24, P1, R18, UR5, RZ ; /* 0x0000000512187c10 */
/* 0x002fc8000ff3e0ff */
/*0500*/ IADD3.X R25, R19, UR6, RZ, P1, !PT ; /* 0x0000000613197c10 */
/* 0x000fca0008ffe4ff */
/*0510*/ LDG.E R18, [R24.64] ; /* 0x0000000818127981 */
/* 0x0042a2000c1e1900 */
/*0520*/ FFMA R21, R21, R28, R29 ; /* 0x0000001c15157223 */
/* 0x008fe2000000001d */
/*0530*/ IADD3 R28, P1, R24, UR5, RZ ; /* 0x00000005181c7c10 */
/* 0x000fc6000ff3e0ff */
/*0540*/ FFMA R21, R17, R26, R21 ; /* 0x0000001a11157223 */
/* 0x010fe20000000015 */
/*0550*/ IADD3.X R29, R25, UR6, RZ, P1, !PT ; /* 0x00000006191d7c10 */
/* 0x000fe20008ffe4ff */
/*0560*/ LDG.E R17, [R14.64+0x10] ; /* 0x000010080e117981 */
/* 0x000ea2000c1e1900 */
/*0570*/ IADD3 R22, P1, R28, UR5, RZ ; /* 0x000000051c167c10 */
/* 0x001fc6000ff3e0ff */
/*0580*/ LDG.E R19, [R28.64] ; /* 0x000000081c137981 */
/* 0x0000e2000c1e1900 */
/*0590*/ IADD3.X R23, R29, UR6, RZ, P1, !PT ; /* 0x000000061d177c10 */
/* 0x000fc60008ffe4ff */
/*05a0*/ LDG.E R26, [R14.64+0x14] ; /* 0x000014080e1a7981 */
/* 0x000ee2000c1e1900 */
/*05b0*/ FFMA R24, R9, R20, R21 ; /* 0x0000001409187223 */
/* 0x002fe20000000015 */
/*05c0*/ IADD3 R20, P1, R22, UR5, RZ ; /* 0x0000000516147c10 */
/* 0x000fe4000ff3e0ff */
/*05d0*/ LDG.E R22, [R22.64] ; /* 0x0000000816167981 */
/* 0x000324000c1e1900 */
/*05e0*/ IADD3.X R21, R23, UR6, RZ, P1, !PT ; /* 0x0000000617157c10 */
/* 0x000fe40008ffe4ff */
/*05f0*/ LDG.E R9, [R14.64+0x18] ; /* 0x000018080e097981 */
/* 0x000f28000c1e1900 */
/*0600*/ LDG.E R28, [R14.64+0x20] ; /* 0x000020080e1c7981 */
/* 0x001f22000c1e1900 */
/*0610*/ FFMA R23, R8, R7, R24 ; /* 0x0000000708177223 */
/* 0x002fe20000000018 */
/*0620*/ IADD3 R24, P1, R20, UR5, RZ ; /* 0x0000000514187c10 */
/* 0x000fc4000ff3e0ff */
/*0630*/ LDG.E R7, [R20.64] ; /* 0x0000000814077981 */
/* 0x000128000c1e1900 */
/*0640*/ LDG.E R8, [R14.64+0x1c] ; /* 0x00001c080e087981 */
/* 0x000f22000c1e1900 */
/*0650*/ IADD3.X R25, R21, UR6, RZ, P1, !PT ; /* 0x0000000615197c10 */
/* 0x000fc60008ffe4ff */
/*0660*/ LDG.E R29, [R14.64+0x28] ; /* 0x000028080e1d7981 */
/* 0x000f22000c1e1900 */
/*0670*/ FFMA R27, R27, R16, R23 ; /* 0x000000101b1b7223 */
/* 0x020fc60000000017 */
/*0680*/ LDG.E R23, [R24.64] ; /* 0x0000000818177981 */
/* 0x000362000c1e1900 */
/*0690*/ IADD3 R16, P1, R24, UR5, RZ ; /* 0x0000000518107c10 */
/* 0x000fe2000ff3e0ff */
/*06a0*/ FFMA R27, R18, R17, R27 ; /* 0x00000011121b7223 */
/* 0x004fc6000000001b */
/*06b0*/ IADD3.X R17, R25, UR6, RZ, P1, !PT ; /* 0x0000000619117c10 */
/* 0x000fe40008ffe4ff */
/*06c0*/ IADD3 R18, P1, R16, UR5, RZ ; /* 0x0000000510127c10 */
/* 0x000fc6000ff3e0ff */
/*06d0*/ LDG.E R16, [R16.64] ; /* 0x0000000810107981 */
/* 0x000562000c1e1900 */
/*06e0*/ FFMA R26, R19, R26, R27 ; /* 0x0000001a131a7223 */
/* 0x008fe2000000001b */
/*06f0*/ IADD3.X R19, R17, UR6, RZ, P1, !PT ; /* 0x0000000611137c10 */
/* 0x000fe40008ffe4ff */
/*0700*/ LDG.E R27, [R14.64+0x24] ; /* 0x000024080e1b7981 */
/* 0x000ee2000c1e1900 */
/*0710*/ IADD3 R20, P1, R18, UR5, RZ ; /* 0x0000000512147c10 */
/* 0x001fc6000ff3e0ff */
/*0720*/ LDG.E R18, [R18.64] ; /* 0x0000000812127981 */
/* 0x000ee2000c1e1900 */
/*0730*/ IADD3.X R21, R19, UR6, RZ, P1, !PT ; /* 0x0000000613157c10 */
/* 0x000fe20008ffe4ff */
/*0740*/ FFMA R9, R22, R9, R26 ; /* 0x0000000916097223 */
/* 0x010fe2000000001a */
/*0750*/ IADD3 R24, P1, R20, UR5, RZ ; /* 0x0000000514187c10 */
/* 0x002fe2000ff3e0ff */
/*0760*/ LDG.E R26, [R14.64+0x2c] ; /* 0x00002c080e1a7981 */
/* 0x000126000c1e1900 */
/*0770*/ IADD3.X R25, R21, UR6, RZ, P1, !PT ; /* 0x0000000615197c10 */
/* 0x000fe20008ffe4ff */
/*0780*/ LDG.E R20, [R20.64] ; /* 0x0000000814147981 */
/* 0x000f28000c1e1900 */
/*0790*/ LDG.E R22, [R14.64+0x30] ; /* 0x000030080e167981 */
/* 0x000122000c1e1900 */
/*07a0*/ FFMA R17, R7, R8, R9 ; /* 0x0000000807117223 */
/* 0x004fe20000000009 */
/*07b0*/ IADD3 R8, P1, R24, UR5, RZ ; /* 0x0000000518087c10 */
/* 0x000fc4000ff3e0ff */
/*07c0*/ LDG.E R7, [R24.64] ; /* 0x0000000818077981 */
/* 0x000ea4000c1e1900 */
/*07d0*/ IADD3.X R9, R25, UR6, RZ, P1, !PT ; /* 0x0000000619097c10 */
/* 0x000fe20008ffe4ff */
/*07e0*/ FFMA R23, R23, R28, R17 ; /* 0x0000001c17177223 */
/* 0x020fc80000000011 */
/*07f0*/ LDG.E R28, [R8.64] ; /* 0x00000008081c7981 */
/* 0x000f68000c1e1900 */
/*0800*/ LDG.E R17, [R14.64+0x34] ; /* 0x000034080e117981 */
/* 0x000162000c1e1900 */
/*0810*/ IADD3 R5, P1, R5, 0x10, RZ ; /* 0x0000001005057810 */
/* 0x000fca0007f3e0ff */
/*0820*/ IMAD.X R6, RZ, RZ, R6, P1 ; /* 0x000000ffff067224 */
/* 0x000fe200008e0606 */
/*0830*/ ISETP.GE.U32.AND P1, PT, R5, -0xc, PT ; /* 0xfffffff40500780c */
/* 0x000fc80003f26070 */
/*0840*/ ISETP.GE.AND.EX P1, PT, R6, -0x1, PT, P1 ; /* 0xffffffff0600780c */
/* 0x000fe20003f26310 */
/*0850*/ FFMA R16, R16, R27, R23 ; /* 0x0000001b10107223 */
/* 0x008fc80000000017 */
/*0860*/ FFMA R29, R18, R29, R16 ; /* 0x0000001d121d7223 */
/* 0x000fe20000000010 */
/*0870*/ IADD3 R18, P3, R8, UR5, RZ ; /* 0x0000000508127c10 */
/* 0x000fe4000ff7e0ff */
/*0880*/ IADD3 R14, P2, R14, 0x40, RZ ; /* 0x000000400e0e7810 */
/* 0x001fe20007f5e0ff */
/*0890*/ FFMA R20, R20, R26, R29 ; /* 0x0000001a14147223 */
/* 0x010fe2000000001d */
/*08a0*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe2000fffe03f */
/*08b0*/ IADD3.X R19, R9, UR6, RZ, P3, !PT ; /* 0x0000000609137c10 */
/* 0x000fe40009ffe4ff */
/*08c0*/ IMAD.X R15, RZ, RZ, R15, P2 ; /* 0x000000ffff0f7224 */
/* 0x000fe400010e060f */
/*08d0*/ FFMA R7, R7, R22, R20 ; /* 0x0000001607077223 */
/* 0x004fc80000000014 */
/*08e0*/ FFMA R29, R28, R17, R7 ; /* 0x000000111c1d7223 */
/* 0x020fe20000000007 */
/*08f0*/ @!P1 BRA 0x380 ; /* 0xfffffa8000009947 */
/* 0x000fea000383ffff */
/*0900*/ IADD3 R7, P2, RZ, -R5, RZ ; /* 0x80000005ff077210 */
/* 0x000fc80007f5e0ff */
/*0910*/ ISETP.GT.U32.AND P1, PT, R7, 0x4, PT ; /* 0x000000040700780c */
/* 0x000fe20003f24070 */
/*0920*/ IMAD.X R7, RZ, RZ, ~R6, P2 ; /* 0x000000ffff077224 */
/* 0x000fca00010e0e06 */
/*0930*/ ISETP.GT.AND.EX P1, PT, R7, RZ, PT, P1 ; /* 0x000000ff0700720c */
/* 0x000fda0003f24310 */
/*0940*/ @!P1 BRA 0xc30 ; /* 0x000002e000009947 */
/* 0x000fea0003800000 */
/*0950*/ IADD3 R24, P0, R18, UR5, RZ ; /* 0x0000000512187c10 */
/* 0x000fe2000ff1e0ff */
/*0960*/ LDG.E R27, [R14.64+-0x8] ; /* 0xfffff8080e1b7981 */
/* 0x000ea8000c1e1900 */
/*0970*/ LDG.E R28, [R18.64] ; /* 0x00000008121c7981 */
/* 0x0000a2000c1e1900 */
/*0980*/ IADD3.X R25, R19, UR6, RZ, P0, !PT ; /* 0x0000000613197c10 */
/* 0x000fe400087fe4ff */
/*0990*/ IADD3 R20, P0, R24, UR5, RZ ; /* 0x0000000518147c10 */
/* 0x000fe2000ff1e0ff */
/*09a0*/ LDG.E R22, [R14.64+-0x4] ; /* 0xfffffc080e167981 */
/* 0x000ee6000c1e1900 */
/*09b0*/ IADD3.X R21, R25, UR6, RZ, P0, !PT ; /* 0x0000000619157c10 */
/* 0x000fe200087fe4ff */
/*09c0*/ LDG.E R7, [R24.64] ; /* 0x0000000818077981 */
/* 0x0002e8000c1e1900 */
/*09d0*/ LDG.E R23, [R20.64] ; /* 0x0000000814177981 */
/* 0x000968000c1e1900 */
/*09e0*/ LDG.E R26, [R14.64] ; /* 0x000000080e1a7981 */
/* 0x000f62000c1e1900 */
/*09f0*/ IADD3 R16, P0, R20, UR5, RZ ; /* 0x0000000514107c10 */
/* 0x000fc6000ff1e0ff */
/*0a00*/ LDG.E R25, [R14.64+0x4] ; /* 0x000004080e197981 */
/* 0x002f62000c1e1900 */
/*0a10*/ IADD3.X R17, R21, UR6, RZ, P0, !PT ; /* 0x0000000615117c10 */
/* 0x000fe400087fe4ff */
/*0a20*/ IADD3 R18, P0, R16, UR5, RZ ; /* 0x0000000510127c10 */
/* 0x001fc6000ff1e0ff */
/*0a30*/ LDG.E R24, [R16.64] ; /* 0x0000000810187981 */
/* 0x000162000c1e1900 */
/*0a40*/ IADD3.X R19, R17, UR6, RZ, P0, !PT ; /* 0x0000000611137c10 */
/* 0x000fe400087fe4ff */
/*0a50*/ IADD3 R8, P0, R18, UR5, RZ ; /* 0x0000000512087c10 */
/* 0x000fc6000ff1e0ff */
/*0a60*/ LDG.E R18, [R18.64] ; /* 0x0000000812127981 */
/* 0x000362000c1e1900 */
/*0a70*/ IADD3.X R9, R19, UR6, RZ, P0, !PT ; /* 0x0000000613097c10 */
/* 0x000fe400087fe4ff */
/*0a80*/ IADD3 R20, P0, R8, UR5, RZ ; /* 0x0000000508147c10 */
/* 0x010fc6000ff1e0ff */
/*0a90*/ LDG.E R8, [R8.64] ; /* 0x0000000808087981 */
/* 0x000f22000c1e1900 */
/*0aa0*/ IADD3.X R21, R9, UR6, RZ, P0, !PT ; /* 0x0000000609157c10 */
/* 0x000fe400087fe4ff */
/*0ab0*/ IADD3 R16, P0, R20, UR5, RZ ; /* 0x0000000514107c10 */
/* 0x001fc8000ff1e0ff */
/*0ac0*/ IADD3.X R17, R21, UR6, RZ, P0, !PT ; /* 0x0000000615117c10 */
/* 0x000fca00087fe4ff */
/*0ad0*/ LDG.E R19, [R16.64] ; /* 0x0000000810137981 */
/* 0x002f22000c1e1900 */
/*0ae0*/ FFMA R28, R28, R27, R29 ; /* 0x0000001b1c1c7223 */
/* 0x004fc6000000001d */
/*0af0*/ LDG.E R27, [R14.64+0x8] ; /* 0x000008080e1b7981 */
/* 0x0000a8000c1e1900 */
/*0b00*/ LDG.E R29, [R14.64+0xc] ; /* 0x00000c080e1d7981 */
/* 0x000122000c1e1900 */
/*0b10*/ FFMA R28, R7, R22, R28 ; /* 0x00000016071c7223 */
/* 0x008fc6000000001c */
/*0b20*/ LDG.E R7, [R20.64] ; /* 0x0000000814077981 */
/* 0x000ee8000c1e1900 */
/*0b30*/ LDG.E R22, [R14.64+0x10] ; /* 0x000010080e167981 */
/* 0x0000e2000c1e1900 */
/*0b40*/ FFMA R23, R23, R26, R28 ; /* 0x0000001a17177223 */
/* 0x020fc6000000001c */
/*0b50*/ LDG.E R26, [R14.64+0x14] ; /* 0x000014080e1a7981 */
/* 0x000162000c1e1900 */
/*0b60*/ FFMA R23, R24, R25, R23 ; /* 0x0000001918177223 */
/* 0x000fe20000000017 */
/*0b70*/ IADD3 R5, P3, R5, 0x8, RZ ; /* 0x0000000805057810 */
/* 0x000fe40007f7e0ff */
/*0b80*/ IADD3 R14, P2, R14, 0x20, RZ ; /* 0x000000200e0e7810 */
/* 0x001fe40007f5e0ff */
/*0b90*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0ba0*/ IMAD.X R6, RZ, RZ, R6, P3 ; /* 0x000000ffff067224 */
/* 0x000fe400018e0606 */
/*0bb0*/ IMAD.X R15, RZ, RZ, R15, P2 ; /* 0x000000ffff0f7224 */
/* 0x000fe200010e060f */
/*0bc0*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0bd0*/ FFMA R18, R18, R27, R23 ; /* 0x0000001b12127223 */
/* 0x004fc80000000017 */
/*0be0*/ FFMA R8, R8, R29, R18 ; /* 0x0000001d08087223 */
/* 0x010fe20000000012 */
/*0bf0*/ IADD3 R18, P1, R16, UR5, RZ ; /* 0x0000000510127c10 */
/* 0x000fc6000ff3e0ff */
/*0c00*/ FFMA R7, R7, R22, R8 ; /* 0x0000001607077223 */
/* 0x008fc80000000008 */
/*0c10*/ FFMA R29, R19, R26, R7 ; /* 0x0000001a131d7223 */
/* 0x020fe20000000007 */
/*0c20*/ IADD3.X R19, R17, UR6, RZ, P1, !PT ; /* 0x0000000611137c10 */
/* 0x000fe40008ffe4ff */
/*0c30*/ ISETP.NE.U32.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fc80003f25070 */
/*0c40*/ ISETP.NE.OR.EX P0, PT, R6, RZ, P0, P1 ; /* 0x000000ff0600720c */
/* 0x000fda0000705710 */
/*0c50*/ @!P0 BRA 0xe30 ; /* 0x000001d000008947 */
/* 0x000fea0003800000 */
/*0c60*/ IADD3 R16, P0, R18, UR5, RZ ; /* 0x0000000512107c10 */
/* 0x000fe2000ff1e0ff */
/*0c70*/ LDG.E R7, [R14.64+-0x8] ; /* 0xfffff8080e077981 */
/* 0x000ea6000c1e1900 */
/*0c80*/ IADD3.X R17, R19, UR6, RZ, P0, !PT ; /* 0x0000000613117c10 */
/* 0x000fe200087fe4ff */
/*0c90*/ LDG.E R18, [R18.64] ; /* 0x0000000812127981 */
/* 0x000ea2000c1e1900 */
/*0ca0*/ IADD3 R8, P0, R16, UR5, RZ ; /* 0x0000000510087c10 */
/* 0x000fc6000ff1e0ff */
/*0cb0*/ LDG.E R16, [R16.64] ; /* 0x0000000810107981 */
/* 0x000ee2000c1e1900 */
/*0cc0*/ IADD3.X R9, R17, UR6, RZ, P0, !PT ; /* 0x0000000611097c10 */
/* 0x000fe400087fe4ff */
/*0cd0*/ IADD3 R20, P0, R8, UR5, RZ ; /* 0x0000000508147c10 */
/* 0x000fe2000ff1e0ff */
/*0ce0*/ LDG.E R22, [R14.64+-0x4] ; /* 0xfffffc080e167981 */
/* 0x000ee6000c1e1900 */
/*0cf0*/ IADD3.X R21, R9, UR6, RZ, P0, !PT ; /* 0x0000000609157c10 */
/* 0x000fe200087fe4ff */
/*0d00*/ LDG.E R8, [R8.64] ; /* 0x0000000808087981 */
/* 0x000f28000c1e1900 */
/*0d10*/ LDG.E R23, [R14.64] ; /* 0x000000080e177981 */
/* 0x000f28000c1e1900 */
/*0d20*/ LDG.E R24, [R20.64] ; /* 0x0000000814187981 */
/* 0x000f68000c1e1900 */
/*0d30*/ LDG.E R25, [R14.64+0x4] ; /* 0x000004080e197981 */
/* 0x000162000c1e1900 */
/*0d40*/ IADD3 R5, P0, R5, 0x4, RZ ; /* 0x0000000405057810 */
/* 0x000fca0007f1e0ff */
/*0d50*/ IMAD.X R6, RZ, RZ, R6, P0 ; /* 0x000000ffff067224 */
/* 0x000fe200000e0606 */
/*0d60*/ ISETP.NE.U32.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fc80003f05070 */
/*0d70*/ ISETP.NE.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fe20003f05300 */
/*0d80*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0d90*/ FFMA R7, R18, R7, R29 ; /* 0x0000000712077223 */
/* 0x004fe2000000001d */
/*0da0*/ IADD3 R18, P2, R20, UR5, RZ ; /* 0x0000000514127c10 */
/* 0x000fc6000ff5e0ff */
/*0db0*/ FFMA R7, R16, R22, R7 ; /* 0x0000001610077223 */
/* 0x008fe20000000007 */
/*0dc0*/ IADD3.X R19, R21, UR6, RZ, P2, !PT ; /* 0x0000000615137c10 */
/* 0x000fc600097fe4ff */
/*0dd0*/ FFMA R7, R8, R23, R7 ; /* 0x0000001708077223 */
/* 0x010fe20000000007 */
/*0de0*/ IADD3 R8, P1, R14, 0x10, RZ ; /* 0x000000100e087810 */
/* 0x000fca0007f3e0ff */
/*0df0*/ IMAD.X R15, RZ, RZ, R15, P1 ; /* 0x000000ffff0f7224 */
/* 0x001fe400008e060f */
/*0e00*/ FFMA R29, R24, R25, R7 ; /* 0x00000019181d7223 */
/* 0x020fe40000000007 */
/*0e10*/ IMAD.MOV.U32 R14, RZ, RZ, R8 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0008 */
/*0e20*/ @P0 BRA 0xc60 ; /* 0xfffffe3000000947 */
/* 0x000fea000383ffff */
/*0e30*/ ISETP.NE.U32.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fc80003f05070 */
/*0e40*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fda0003f05300 */
/*0e50*/ @!P0 BRA 0x1030 ; /* 0x000001d000008947 */
/* 0x000fea0003800000 */
/*0e60*/ USHF.R.S32.HI UR5, URZ, 0x1f, UR4 ; /* 0x0000001f3f057899 */
/* 0x000fe20008011404 */
/*0e70*/ IADD3 R13, P0, R12, UR4, RZ ; /* 0x000000040c0d7c10 */
/* 0x000fe2000ff1e0ff */
/*0e80*/ IMAD.U32 R15, RZ, RZ, UR4 ; /* 0x00000004ff0f7e24 */
/* 0x000fe2000f8e00ff */
/*0e90*/ IADD3 R8, P1, RZ, -R3, RZ ; /* 0x80000003ff087210 */
/* 0x000fc60007f3e0ff */
/*0ea0*/ IADD3.X R4, R4, UR5, RZ, P0, !PT ; /* 0x0000000504047c10 */
/* 0x000fe200087fe4ff */
/*0eb0*/ IMAD.U32 R14, RZ, RZ, UR5 ; /* 0x00000005ff0e7e24 */
/* 0x000fe2000f8e00ff */
/*0ec0*/ LEA R12, P0, R13, c[0x0][0x160], 0x2 ; /* 0x000058000d0c7a11 */
/* 0x000fe200078010ff */
/*0ed0*/ IMAD.X R9, RZ, RZ, -0x1, P1 ; /* 0xffffffffff097424 */
/* 0x000fc600008e06ff */
/*0ee0*/ LEA.HI.X R13, R13, c[0x0][0x164], R4, 0x2, P0 ; /* 0x000059000d0d7a11 */
/* 0x000fe400000f1404 */
/*0ef0*/ IMAD R4, R14, c[0x0][0x188], RZ ; /* 0x000062000e047a24 */
/* 0x000fe400078e02ff */
/*0f00*/ IMAD.WIDE.U32 R6, R15, c[0x0][0x188], R10 ; /* 0x000062000f067a25 */
/* 0x000fc800078e000a */
/*0f10*/ IMAD R3, R15, c[0x0][0x18c], R4 ; /* 0x000063000f037a24 */
/* 0x000fe200078e0204 */
/*0f20*/ LEA R4, P0, R6, c[0x0][0x168], 0x2 ; /* 0x00005a0006047a11 */
/* 0x000fc600078010ff */
/*0f30*/ IMAD.IADD R3, R7, 0x1, R3 ; /* 0x0000000107037824 */
/* 0x000fe400078e0203 */
/*0f40*/ IMAD.MOV.U32 R7, RZ, RZ, R13 ; /* 0x000000ffff077224 */
/* 0x000fc600078e000d */
/*0f50*/ LEA.HI.X R5, R6, c[0x0][0x16c], R3, 0x2, P0 ; /* 0x00005b0006057a11 */
/* 0x000fe200000f1403 */
/*0f60*/ IMAD.MOV.U32 R6, RZ, RZ, R12 ; /* 0x000000ffff067224 */
/* 0x000fc800078e000c */
/*0f70*/ LDG.E R4, [R4.64] ; /* 0x0000000804047981 */
/* 0x000ea8000c1e1900 */
/*0f80*/ LDG.E R3, [R6.64] ; /* 0x0000000806037981 */
/* 0x000ea2000c1e1900 */
/*0f90*/ IADD3 R8, P0, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fca0007f1e0ff */
/*0fa0*/ IMAD.X R9, RZ, RZ, R9, P0 ; /* 0x000000ffff097224 */
/* 0x000fe200000e0609 */
/*0fb0*/ ISETP.NE.U32.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc80003f05070 */
/*0fc0*/ ISETP.NE.AND.EX P0, PT, R9, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x000fe40003f05300 */
/*0fd0*/ IADD3 R12, P2, R12, 0x4, RZ ; /* 0x000000040c0c7810 */
/* 0x000fe40007f5e0ff */
/*0fe0*/ IADD3 R15, P1, R15, 0x1, RZ ; /* 0x000000010f0f7810 */
/* 0x000fc60007f3e0ff */
/*0ff0*/ IMAD.X R13, RZ, RZ, R13, P2 ; /* 0x000000ffff0d7224 */
/* 0x000fe400010e060d */
/*1000*/ IMAD.X R14, RZ, RZ, R14, P1 ; /* 0x000000ffff0e7224 */
/* 0x000fe400008e060e */
/*1010*/ FFMA R29, R4, R3, R29 ; /* 0x00000003041d7223 */
/* 0x004fe4000000001d */
/*1020*/ @P0 BRA 0xef0 ; /* 0xfffffec000000947 */
/* 0x000fea000383ffff */
/*1030*/ IMAD R5, R2, c[0x0][0x188], RZ ; /* 0x0000620002057a24 */
/* 0x000fe400078e02ff */
/*1040*/ IMAD.MOV.U32 R2, RZ, RZ, R10 ; /* 0x000000ffff027224 */
/* 0x000fe400078e000a */
/*1050*/ IMAD.MOV.U32 R3, RZ, RZ, R11 ; /* 0x000000ffff037224 */
/* 0x000fc400078e000b */
/*1060*/ IMAD R5, R0.reuse, c[0x0][0x18c], R5 ; /* 0x0000630000057a24 */
/* 0x040fe400078e0205 */
/*1070*/ IMAD.WIDE.U32 R2, R0, c[0x0][0x188], R2 ; /* 0x0000620000027a25 */
/* 0x000fc800078e0002 */
/*1080*/ IMAD.IADD R3, R3, 0x1, R5 ; /* 0x0000000103037824 */
/* 0x000fe200078e0205 */
/*1090*/ LEA R4, P0, R2, c[0x0][0x170], 0x2 ; /* 0x00005c0002047a11 */
/* 0x000fc800078010ff */
/*10a0*/ LEA.HI.X R5, R2, c[0x0][0x174], R3, 0x2, P0 ; /* 0x00005d0002057a11 */
/* 0x000fca00000f1403 */
/*10b0*/ STG.E [R4.64], R29 ; /* 0x0000001d04007986 */
/* 0x000fe2000c101908 */
/*10c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*10d0*/ BRA 0x10d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void cuda_sgemm(float* matrix_a, float* matrix_b, float* matrix_c, size_t M, size_t K, size_t N) {
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float sum = 0;
if (col < N && row < M) {
for (int k = 0; k < K; k++) {
sum +=
matrix_a[INDEX(row, k, M, K)] * matrix_b[INDEX(k, col, K, N)];
}
matrix_c[INDEX(row, col, M, N)] = sum;
}
} | .file "tmpxft_000c1f49_00000000-6_cuda_sgemm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB12287:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE12287:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z10cuda_sgemmPfS_S_mmmPfS_S_mmm
.type _Z37__device_stub__Z10cuda_sgemmPfS_S_mmmPfS_S_mmm, @function
_Z37__device_stub__Z10cuda_sgemmPfS_S_mmmPfS_S_mmm:
.LFB12309:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10cuda_sgemmPfS_S_mmm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE12309:
.size _Z37__device_stub__Z10cuda_sgemmPfS_S_mmmPfS_S_mmm, .-_Z37__device_stub__Z10cuda_sgemmPfS_S_mmmPfS_S_mmm
.globl _Z10cuda_sgemmPfS_S_mmm
.type _Z10cuda_sgemmPfS_S_mmm, @function
_Z10cuda_sgemmPfS_S_mmm:
.LFB12310:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z10cuda_sgemmPfS_S_mmmPfS_S_mmm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE12310:
.size _Z10cuda_sgemmPfS_S_mmm, .-_Z10cuda_sgemmPfS_S_mmm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10cuda_sgemmPfS_S_mmm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB12312:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10cuda_sgemmPfS_S_mmm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE12312:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void cuda_sgemm(float* matrix_a, float* matrix_b, float* matrix_c, size_t M, size_t K, size_t N) {
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float sum = 0;
if (col < N && row < M) {
for (int k = 0; k < K; k++) {
sum +=
matrix_a[INDEX(row, k, M, K)] * matrix_b[INDEX(k, col, K, N)];
}
matrix_c[INDEX(row, col, M, N)] = sum;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cuda_sgemm(float* matrix_a, float* matrix_b, float* matrix_c, size_t M, size_t K, size_t N) {
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float sum = 0;
if (col < N && row < M) {
for (int k = 0; k < K; k++) {
sum +=
matrix_a[INDEX(row, k, M, K)] * matrix_b[INDEX(k, col, K, N)];
}
matrix_c[INDEX(row, col, M, N)] = sum;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cuda_sgemm(float* matrix_a, float* matrix_b, float* matrix_c, size_t M, size_t K, size_t N) {
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float sum = 0;
if (col < N && row < M) {
for (int k = 0; k < K; k++) {
sum +=
matrix_a[INDEX(row, k, M, K)] * matrix_b[INDEX(k, col, K, N)];
}
matrix_c[INDEX(row, col, M, N)] = sum;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10cuda_sgemmPfS_S_mmm
.globl _Z10cuda_sgemmPfS_S_mmm
.p2align 8
.type _Z10cuda_sgemmPfS_S_mmm,@function
_Z10cuda_sgemmPfS_S_mmm:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x3c
s_load_b64 s[2:3], s[0:1], 0x28
v_and_b32_e32 v3, 0x3ff, v0
s_add_u32 s4, s0, 48
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s6, v[3:4]
s_mov_b32 s6, exec_lo
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_7
s_load_b32 s6, s[4:5], 0xc
s_load_b64 s[4:5], s[0:1], 0x18
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s6, s6, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, s15, s6, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[3:4]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
s_load_b64 s[4:5], s[0:1], 0x20
s_mov_b64 s[6:7], 0
s_waitcnt lgkmcnt(0)
s_cmp_eq_u64 s[4:5], 0
s_cbranch_scc1 .LBB0_5
s_load_b128 s[8:11], s[0:1], 0x0
v_mul_lo_u32 v0, v4, s4
v_mul_lo_u32 v7, v3, s5
v_mad_u64_u32 v[5:6], null, v3, s4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add3_u32 v6, v6, v7, v0
v_lshlrev_b64 v[7:8], 2, v[1:2]
v_mov_b32_e32 v0, 0
v_lshlrev_b64 v[9:10], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s10, v7
v_add_co_ci_u32_e32 v6, vcc_lo, s11, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v7, vcc_lo, s8, v9
v_add_co_ci_u32_e32 v8, vcc_lo, s9, v10, vcc_lo
s_lshl_b64 s[8:9], s[2:3], 2
.p2align 6
.LBB0_4:
global_load_b32 v9, v[7:8], off
global_load_b32 v10, v[5:6], off
s_add_u32 s6, s6, 1
v_add_co_u32 v5, vcc_lo, v5, s8
s_addc_u32 s7, s7, 0
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
v_cmp_ge_u64_e64 s10, s[6:7], s[4:5]
v_add_co_u32 v7, vcc_lo, v7, 4
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
s_and_b32 vcc_lo, exec_lo, s10
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v0, v9, v10
s_cbranch_vccz .LBB0_4
s_branch .LBB0_6
.LBB0_5:
v_mov_b32_e32 v0, 0
.LBB0_6:
s_load_b64 s[0:1], s[0:1], 0x10
v_mul_lo_u32 v6, v4, s2
v_mul_lo_u32 v7, v3, s3
v_mad_u64_u32 v[4:5], null, v3, s2, 0
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v5, v5, v7, v6
v_lshlrev_b64 v[3:4], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, v3, v1
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10cuda_sgemmPfS_S_mmm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10cuda_sgemmPfS_S_mmm, .Lfunc_end0-_Z10cuda_sgemmPfS_S_mmm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10cuda_sgemmPfS_S_mmm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10cuda_sgemmPfS_S_mmm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cuda_sgemm(float* matrix_a, float* matrix_b, float* matrix_c, size_t M, size_t K, size_t N) {
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float sum = 0;
if (col < N && row < M) {
for (int k = 0; k < K; k++) {
sum +=
matrix_a[INDEX(row, k, M, K)] * matrix_b[INDEX(k, col, K, N)];
}
matrix_c[INDEX(row, col, M, N)] = sum;
}
} | .text
.file "cuda_sgemm.hip"
.globl _Z25__device_stub__cuda_sgemmPfS_S_mmm # -- Begin function _Z25__device_stub__cuda_sgemmPfS_S_mmm
.p2align 4, 0x90
.type _Z25__device_stub__cuda_sgemmPfS_S_mmm,@function
_Z25__device_stub__cuda_sgemmPfS_S_mmm: # @_Z25__device_stub__cuda_sgemmPfS_S_mmm
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10cuda_sgemmPfS_S_mmm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z25__device_stub__cuda_sgemmPfS_S_mmm, .Lfunc_end0-_Z25__device_stub__cuda_sgemmPfS_S_mmm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10cuda_sgemmPfS_S_mmm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10cuda_sgemmPfS_S_mmm,@object # @_Z10cuda_sgemmPfS_S_mmm
.section .rodata,"a",@progbits
.globl _Z10cuda_sgemmPfS_S_mmm
.p2align 3, 0x0
_Z10cuda_sgemmPfS_S_mmm:
.quad _Z25__device_stub__cuda_sgemmPfS_S_mmm
.size _Z10cuda_sgemmPfS_S_mmm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10cuda_sgemmPfS_S_mmm"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__cuda_sgemmPfS_S_mmm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10cuda_sgemmPfS_S_mmm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10cuda_sgemmPfS_S_mmm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R10, SR_CTAID.X ; /* 0x00000000000a7919 */
/* 0x000e280000002500 */
/*0020*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000e280000002100 */
/*0030*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R10, R10, c[0x0][0x0], R11 ; /* 0x000000000a0a7a24 */
/* 0x001fca00078e020b */
/*0060*/ ISETP.GE.U32.AND P0, PT, R10, c[0x0][0x188], PT ; /* 0x000062000a007a0c */
/* 0x000fe40003f06070 */
/*0070*/ SHF.R.S32.HI R11, RZ, 0x1f, R10 ; /* 0x0000001fff0b7819 */
/* 0x000fe2000001140a */
/*0080*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x002fc600078e0203 */
/*0090*/ ISETP.GE.U32.AND.EX P0, PT, R11, c[0x0][0x18c], PT, P0 ; /* 0x000063000b007a0c */
/* 0x000fe40003f06100 */
/*00a0*/ ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe40003f26070 */
/*00b0*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x000fc80000011400 */
/*00c0*/ ISETP.GE.U32.OR.EX P0, PT, R2, c[0x0][0x17c], P0, P1 ; /* 0x00005f0002007a0c */
/* 0x000fda0000706510 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x180], PT ; /* 0x00006000ff007a0c */
/* 0x000fe20003f05070 */
/*00f0*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0100*/ IMAD.MOV.U32 R29, RZ, RZ, RZ ; /* 0x000000ffff1d7224 */
/* 0x000fe400078e00ff */
/*0110*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x184], PT, P0 ; /* 0x00006100ff007a0c */
/* 0x000fda0003f05300 */
/*0120*/ @!P0 BRA 0x1030 ; /* 0x00000f0000008947 */
/* 0x000fea0003800000 */
/*0130*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff047624 */
/* 0x000fe200078e00ff */
/*0140*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0150*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff037624 */
/* 0x000fe400078e00ff */
/*0160*/ IMAD.WIDE.U32 R12, R0, c[0x0][0x180], RZ ; /* 0x00006000000c7a25 */
/* 0x000fe200078e00ff */
/*0170*/ IADD3 R5, P1, R4, -0x1, RZ ; /* 0xffffffff04057810 */
/* 0x000fc60007f3e0ff */
/*0180*/ IMAD.MOV.U32 R29, RZ, RZ, RZ ; /* 0x000000ffff1d7224 */
/* 0x000fe200078e00ff */
/*0190*/ ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fe20003f06070 */
/*01a0*/ IMAD R5, R2, c[0x0][0x180], RZ ; /* 0x0000600002057a24 */
/* 0x000fe200078e02ff */
/*01b0*/ IADD3.X R3, R3, -0x1, RZ, P1, !PT ; /* 0xffffffff03037810 */
/* 0x000fc60000ffe4ff */
/*01c0*/ IMAD R5, R0, c[0x0][0x184], R5 ; /* 0x0000610000057a24 */
/* 0x000fe200078e0205 */
/*01d0*/ ISETP.GE.U32.AND.EX P0, PT, R3, RZ, PT, P0 ; /* 0x000000ff0300720c */
/* 0x000fe40003f06100 */
/*01e0*/ LOP3.LUT R3, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304037812 */
/* 0x000fe200078ec0ff */
/*01f0*/ IMAD.IADD R4, R13, 0x1, R5 ; /* 0x000000010d047824 */
/* 0x000fd400078e0205 */
/*0200*/ @!P0 BRA 0xe30 ; /* 0x00000c2000008947 */
/* 0x000fea0003800000 */
/*0210*/ IADD3 R5, P1, R3, -c[0x0][0x180], RZ ; /* 0x8000600003057a10 */
/* 0x000fe20007f3e0ff */
/*0220*/ UMOV UR6, 0x2 ; /* 0x0000000200067882 */
/* 0x000fe20000000000 */
/*0230*/ LEA R14, P2, R12, c[0x0][0x160], 0x2 ; /* 0x000058000c0e7a11 */
/* 0x000fe200078410ff */
/*0240*/ ULDC.64 UR4, c[0x0][0x188] ; /* 0x0000620000047ab9 */
/* 0x000fe20000000a00 */
/*0250*/ LEA R18, P0, R10, c[0x0][0x168], 0x2 ; /* 0x00005a000a127a11 */
/* 0x000fe200078010ff */
/*0260*/ IMAD.X R6, RZ, RZ, ~c[0x0][0x184], P1 ; /* 0x80006100ff067624 */
/* 0x000fe200008e06ff */
/*0270*/ USHF.L.U64.HI UR6, UR4, UR6, UR5 ; /* 0x0000000604067299 */
/* 0x000fe20008010205 */
/*0280*/ IADD3 R14, P3, R14, 0x8, RZ ; /* 0x000000080e0e7810 */
/* 0x000fe20007f7e0ff */
/*0290*/ USHF.L.U32 UR5, UR4, 0x2, URZ ; /* 0x0000000204057899 */
/* 0x000fe2000800063f */
/*02a0*/ LEA.HI.X R7, R12, c[0x0][0x164], R4, 0x2, P2 ; /* 0x000059000c077a11 */
/* 0x000fe200010f1404 */
/*02b0*/ IMAD.MOV.U32 R29, RZ, RZ, RZ ; /* 0x000000ffff1d7224 */
/* 0x000fe200078e00ff */
/*02c0*/ ISETP.GE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f26270 */
/*02d0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*02e0*/ LEA.HI.X R19, R10, c[0x0][0x16c], R11, 0x2, P0 ; /* 0x00005b000a137a11 */
/* 0x000fe200000f140b */
/*02f0*/ IMAD.X R15, RZ, RZ, R7, P3 ; /* 0x000000ffff0f7224 */
/* 0x000fd400018e0607 */
/*0300*/ @P1 BRA 0xc60 ; /* 0x0000095000001947 */
/* 0x000fea0003800000 */
/*0310*/ IADD3 R7, P0, RZ, -R5, RZ ; /* 0x80000005ff077210 */
/* 0x000fc80007f1e0ff */
/*0320*/ ISETP.GT.U32.AND P1, PT, R7, 0xc, PT ; /* 0x0000000c0700780c */
/* 0x000fe20003f24070 */
/*0330*/ IMAD.X R7, RZ, RZ, ~R6, P0 ; /* 0x000000ffff077224 */
/* 0x000fe200000e0e06 */
/*0340*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fc80003f0f070 */
/*0350*/ ISETP.GT.AND.EX P1, PT, R7, RZ, PT, P1 ; /* 0x000000ff0700720c */
/* 0x000fda0003f24310 */
/*0360*/ @!P1 BRA 0x900 ; /* 0x0000059000009947 */
/* 0x000fea0003800000 */
/*0370*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0380*/ LDG.E R27, [R14.64+-0x8] ; /* 0xfffff8080e1b7981 */
/* 0x000ea8000c1e1900 */
/*0390*/ LDG.E R16, [R18.64] ; /* 0x0000000812107981 */
/* 0x0000a8000c1e1900 */
/*03a0*/ LDG.E R28, [R14.64+-0x4] ; /* 0xfffffc080e1c7981 */
/* 0x000ee8000c1e1900 */
/*03b0*/ LDG.E R26, [R14.64] ; /* 0x000000080e1a7981 */
/* 0x000f22000c1e1900 */
/*03c0*/ IADD3 R18, P1, R18, UR5, RZ ; /* 0x0000000512127c10 */
/* 0x001fc6000ff3e0ff */
/*03d0*/ LDG.E R20, [R14.64+0x4] ; /* 0x000004080e147981 */
/* 0x000f22000c1e1900 */
/*03e0*/ IADD3.X R19, R19, UR6, RZ, P1, !PT ; /* 0x0000000613137c10 */
/* 0x000fe40008ffe4ff */
/*03f0*/ IADD3 R8, P1, R18, UR5, RZ ; /* 0x0000000512087c10 */
/* 0x000fe2000ff3e0ff */
/*0400*/ LDG.E R7, [R14.64+0x8] ; /* 0x000008080e077981 */
/* 0x000ee6000c1e1900 */
/*0410*/ IADD3.X R9, R19, UR6, RZ, P1, !PT ; /* 0x0000000613097c10 */
/* 0x000fe20008ffe4ff */
/*0420*/ LDG.E R21, [R18.64] ; /* 0x0000000812157981 */
/* 0x0000e2000c1e1900 */
/*0430*/ IADD3 R24, P1, R8, UR5, RZ ; /* 0x0000000508187c10 */
/* 0x000fc6000ff3e0ff */
/*0440*/ LDG.E R17, [R8.64] ; /* 0x0000000808117981 */
/* 0x000322000c1e1900 */
/*0450*/ IADD3.X R25, R9, UR6, RZ, P1, !PT ; /* 0x0000000609197c10 */
/* 0x000fe40008ffe4ff */
/*0460*/ IADD3 R22, P1, R24, UR5, RZ ; /* 0x0000000518167c10 */
/* 0x000fc6000ff3e0ff */
/*0470*/ LDG.E R9, [R24.64] ; /* 0x0000000818097981 */
/* 0x002322000c1e1900 */
/*0480*/ IADD3.X R23, R25, UR6, RZ, P1, !PT ; /* 0x0000000619177c10 */
/* 0x000fe40008ffe4ff */
/*0490*/ IADD3 R18, P1, R22, UR5, RZ ; /* 0x0000000516127c10 */
/* 0x001fc6000ff3e0ff */
/*04a0*/ LDG.E R8, [R22.64] ; /* 0x0000000816087981 */
/* 0x000122000c1e1900 */
/*04b0*/ IADD3.X R19, R23, UR6, RZ, P1, !PT ; /* 0x0000000617137c10 */
/* 0x000fe20008ffe4ff */
/*04c0*/ FFMA R29, R16, R27, R29 ; /* 0x0000001b101d7223 */
/* 0x004fc8000000001d */
/*04d0*/ LDG.E R27, [R18.64] ; /* 0x00000008121b7981 */
/* 0x000568000c1e1900 */
/*04e0*/ LDG.E R16, [R14.64+0xc] ; /* 0x00000c080e107981 */
/* 0x000f62000c1e1900 */
/*04f0*/ IADD3 R24, P1, R18, UR5, RZ ; /* 0x0000000512187c10 */
/* 0x002fc8000ff3e0ff */
/*0500*/ IADD3.X R25, R19, UR6, RZ, P1, !PT ; /* 0x0000000613197c10 */
/* 0x000fca0008ffe4ff */
/*0510*/ LDG.E R18, [R24.64] ; /* 0x0000000818127981 */
/* 0x0042a2000c1e1900 */
/*0520*/ FFMA R21, R21, R28, R29 ; /* 0x0000001c15157223 */
/* 0x008fe2000000001d */
/*0530*/ IADD3 R28, P1, R24, UR5, RZ ; /* 0x00000005181c7c10 */
/* 0x000fc6000ff3e0ff */
/*0540*/ FFMA R21, R17, R26, R21 ; /* 0x0000001a11157223 */
/* 0x010fe20000000015 */
/*0550*/ IADD3.X R29, R25, UR6, RZ, P1, !PT ; /* 0x00000006191d7c10 */
/* 0x000fe20008ffe4ff */
/*0560*/ LDG.E R17, [R14.64+0x10] ; /* 0x000010080e117981 */
/* 0x000ea2000c1e1900 */
/*0570*/ IADD3 R22, P1, R28, UR5, RZ ; /* 0x000000051c167c10 */
/* 0x001fc6000ff3e0ff */
/*0580*/ LDG.E R19, [R28.64] ; /* 0x000000081c137981 */
/* 0x0000e2000c1e1900 */
/*0590*/ IADD3.X R23, R29, UR6, RZ, P1, !PT ; /* 0x000000061d177c10 */
/* 0x000fc60008ffe4ff */
/*05a0*/ LDG.E R26, [R14.64+0x14] ; /* 0x000014080e1a7981 */
/* 0x000ee2000c1e1900 */
/*05b0*/ FFMA R24, R9, R20, R21 ; /* 0x0000001409187223 */
/* 0x002fe20000000015 */
/*05c0*/ IADD3 R20, P1, R22, UR5, RZ ; /* 0x0000000516147c10 */
/* 0x000fe4000ff3e0ff */
/*05d0*/ LDG.E R22, [R22.64] ; /* 0x0000000816167981 */
/* 0x000324000c1e1900 */
/*05e0*/ IADD3.X R21, R23, UR6, RZ, P1, !PT ; /* 0x0000000617157c10 */
/* 0x000fe40008ffe4ff */
/*05f0*/ LDG.E R9, [R14.64+0x18] ; /* 0x000018080e097981 */
/* 0x000f28000c1e1900 */
/*0600*/ LDG.E R28, [R14.64+0x20] ; /* 0x000020080e1c7981 */
/* 0x001f22000c1e1900 */
/*0610*/ FFMA R23, R8, R7, R24 ; /* 0x0000000708177223 */
/* 0x002fe20000000018 */
/*0620*/ IADD3 R24, P1, R20, UR5, RZ ; /* 0x0000000514187c10 */
/* 0x000fc4000ff3e0ff */
/*0630*/ LDG.E R7, [R20.64] ; /* 0x0000000814077981 */
/* 0x000128000c1e1900 */
/*0640*/ LDG.E R8, [R14.64+0x1c] ; /* 0x00001c080e087981 */
/* 0x000f22000c1e1900 */
/*0650*/ IADD3.X R25, R21, UR6, RZ, P1, !PT ; /* 0x0000000615197c10 */
/* 0x000fc60008ffe4ff */
/*0660*/ LDG.E R29, [R14.64+0x28] ; /* 0x000028080e1d7981 */
/* 0x000f22000c1e1900 */
/*0670*/ FFMA R27, R27, R16, R23 ; /* 0x000000101b1b7223 */
/* 0x020fc60000000017 */
/*0680*/ LDG.E R23, [R24.64] ; /* 0x0000000818177981 */
/* 0x000362000c1e1900 */
/*0690*/ IADD3 R16, P1, R24, UR5, RZ ; /* 0x0000000518107c10 */
/* 0x000fe2000ff3e0ff */
/*06a0*/ FFMA R27, R18, R17, R27 ; /* 0x00000011121b7223 */
/* 0x004fc6000000001b */
/*06b0*/ IADD3.X R17, R25, UR6, RZ, P1, !PT ; /* 0x0000000619117c10 */
/* 0x000fe40008ffe4ff */
/*06c0*/ IADD3 R18, P1, R16, UR5, RZ ; /* 0x0000000510127c10 */
/* 0x000fc6000ff3e0ff */
/*06d0*/ LDG.E R16, [R16.64] ; /* 0x0000000810107981 */
/* 0x000562000c1e1900 */
/*06e0*/ FFMA R26, R19, R26, R27 ; /* 0x0000001a131a7223 */
/* 0x008fe2000000001b */
/*06f0*/ IADD3.X R19, R17, UR6, RZ, P1, !PT ; /* 0x0000000611137c10 */
/* 0x000fe40008ffe4ff */
/*0700*/ LDG.E R27, [R14.64+0x24] ; /* 0x000024080e1b7981 */
/* 0x000ee2000c1e1900 */
/*0710*/ IADD3 R20, P1, R18, UR5, RZ ; /* 0x0000000512147c10 */
/* 0x001fc6000ff3e0ff */
/*0720*/ LDG.E R18, [R18.64] ; /* 0x0000000812127981 */
/* 0x000ee2000c1e1900 */
/*0730*/ IADD3.X R21, R19, UR6, RZ, P1, !PT ; /* 0x0000000613157c10 */
/* 0x000fe20008ffe4ff */
/*0740*/ FFMA R9, R22, R9, R26 ; /* 0x0000000916097223 */
/* 0x010fe2000000001a */
/*0750*/ IADD3 R24, P1, R20, UR5, RZ ; /* 0x0000000514187c10 */
/* 0x002fe2000ff3e0ff */
/*0760*/ LDG.E R26, [R14.64+0x2c] ; /* 0x00002c080e1a7981 */
/* 0x000126000c1e1900 */
/*0770*/ IADD3.X R25, R21, UR6, RZ, P1, !PT ; /* 0x0000000615197c10 */
/* 0x000fe20008ffe4ff */
/*0780*/ LDG.E R20, [R20.64] ; /* 0x0000000814147981 */
/* 0x000f28000c1e1900 */
/*0790*/ LDG.E R22, [R14.64+0x30] ; /* 0x000030080e167981 */
/* 0x000122000c1e1900 */
/*07a0*/ FFMA R17, R7, R8, R9 ; /* 0x0000000807117223 */
/* 0x004fe20000000009 */
/*07b0*/ IADD3 R8, P1, R24, UR5, RZ ; /* 0x0000000518087c10 */
/* 0x000fc4000ff3e0ff */
/*07c0*/ LDG.E R7, [R24.64] ; /* 0x0000000818077981 */
/* 0x000ea4000c1e1900 */
/*07d0*/ IADD3.X R9, R25, UR6, RZ, P1, !PT ; /* 0x0000000619097c10 */
/* 0x000fe20008ffe4ff */
/*07e0*/ FFMA R23, R23, R28, R17 ; /* 0x0000001c17177223 */
/* 0x020fc80000000011 */
/*07f0*/ LDG.E R28, [R8.64] ; /* 0x00000008081c7981 */
/* 0x000f68000c1e1900 */
/*0800*/ LDG.E R17, [R14.64+0x34] ; /* 0x000034080e117981 */
/* 0x000162000c1e1900 */
/*0810*/ IADD3 R5, P1, R5, 0x10, RZ ; /* 0x0000001005057810 */
/* 0x000fca0007f3e0ff */
/*0820*/ IMAD.X R6, RZ, RZ, R6, P1 ; /* 0x000000ffff067224 */
/* 0x000fe200008e0606 */
/*0830*/ ISETP.GE.U32.AND P1, PT, R5, -0xc, PT ; /* 0xfffffff40500780c */
/* 0x000fc80003f26070 */
/*0840*/ ISETP.GE.AND.EX P1, PT, R6, -0x1, PT, P1 ; /* 0xffffffff0600780c */
/* 0x000fe20003f26310 */
/*0850*/ FFMA R16, R16, R27, R23 ; /* 0x0000001b10107223 */
/* 0x008fc80000000017 */
/*0860*/ FFMA R29, R18, R29, R16 ; /* 0x0000001d121d7223 */
/* 0x000fe20000000010 */
/*0870*/ IADD3 R18, P3, R8, UR5, RZ ; /* 0x0000000508127c10 */
/* 0x000fe4000ff7e0ff */
/*0880*/ IADD3 R14, P2, R14, 0x40, RZ ; /* 0x000000400e0e7810 */
/* 0x001fe20007f5e0ff */
/*0890*/ FFMA R20, R20, R26, R29 ; /* 0x0000001a14147223 */
/* 0x010fe2000000001d */
/*08a0*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe2000fffe03f */
/*08b0*/ IADD3.X R19, R9, UR6, RZ, P3, !PT ; /* 0x0000000609137c10 */
/* 0x000fe40009ffe4ff */
/*08c0*/ IMAD.X R15, RZ, RZ, R15, P2 ; /* 0x000000ffff0f7224 */
/* 0x000fe400010e060f */
/*08d0*/ FFMA R7, R7, R22, R20 ; /* 0x0000001607077223 */
/* 0x004fc80000000014 */
/*08e0*/ FFMA R29, R28, R17, R7 ; /* 0x000000111c1d7223 */
/* 0x020fe20000000007 */
/*08f0*/ @!P1 BRA 0x380 ; /* 0xfffffa8000009947 */
/* 0x000fea000383ffff */
/*0900*/ IADD3 R7, P2, RZ, -R5, RZ ; /* 0x80000005ff077210 */
/* 0x000fc80007f5e0ff */
/*0910*/ ISETP.GT.U32.AND P1, PT, R7, 0x4, PT ; /* 0x000000040700780c */
/* 0x000fe20003f24070 */
/*0920*/ IMAD.X R7, RZ, RZ, ~R6, P2 ; /* 0x000000ffff077224 */
/* 0x000fca00010e0e06 */
/*0930*/ ISETP.GT.AND.EX P1, PT, R7, RZ, PT, P1 ; /* 0x000000ff0700720c */
/* 0x000fda0003f24310 */
/*0940*/ @!P1 BRA 0xc30 ; /* 0x000002e000009947 */
/* 0x000fea0003800000 */
/*0950*/ IADD3 R24, P0, R18, UR5, RZ ; /* 0x0000000512187c10 */
/* 0x000fe2000ff1e0ff */
/*0960*/ LDG.E R27, [R14.64+-0x8] ; /* 0xfffff8080e1b7981 */
/* 0x000ea8000c1e1900 */
/*0970*/ LDG.E R28, [R18.64] ; /* 0x00000008121c7981 */
/* 0x0000a2000c1e1900 */
/*0980*/ IADD3.X R25, R19, UR6, RZ, P0, !PT ; /* 0x0000000613197c10 */
/* 0x000fe400087fe4ff */
/*0990*/ IADD3 R20, P0, R24, UR5, RZ ; /* 0x0000000518147c10 */
/* 0x000fe2000ff1e0ff */
/*09a0*/ LDG.E R22, [R14.64+-0x4] ; /* 0xfffffc080e167981 */
/* 0x000ee6000c1e1900 */
/*09b0*/ IADD3.X R21, R25, UR6, RZ, P0, !PT ; /* 0x0000000619157c10 */
/* 0x000fe200087fe4ff */
/*09c0*/ LDG.E R7, [R24.64] ; /* 0x0000000818077981 */
/* 0x0002e8000c1e1900 */
/*09d0*/ LDG.E R23, [R20.64] ; /* 0x0000000814177981 */
/* 0x000968000c1e1900 */
/*09e0*/ LDG.E R26, [R14.64] ; /* 0x000000080e1a7981 */
/* 0x000f62000c1e1900 */
/*09f0*/ IADD3 R16, P0, R20, UR5, RZ ; /* 0x0000000514107c10 */
/* 0x000fc6000ff1e0ff */
/*0a00*/ LDG.E R25, [R14.64+0x4] ; /* 0x000004080e197981 */
/* 0x002f62000c1e1900 */
/*0a10*/ IADD3.X R17, R21, UR6, RZ, P0, !PT ; /* 0x0000000615117c10 */
/* 0x000fe400087fe4ff */
/*0a20*/ IADD3 R18, P0, R16, UR5, RZ ; /* 0x0000000510127c10 */
/* 0x001fc6000ff1e0ff */
/*0a30*/ LDG.E R24, [R16.64] ; /* 0x0000000810187981 */
/* 0x000162000c1e1900 */
/*0a40*/ IADD3.X R19, R17, UR6, RZ, P0, !PT ; /* 0x0000000611137c10 */
/* 0x000fe400087fe4ff */
/*0a50*/ IADD3 R8, P0, R18, UR5, RZ ; /* 0x0000000512087c10 */
/* 0x000fc6000ff1e0ff */
/*0a60*/ LDG.E R18, [R18.64] ; /* 0x0000000812127981 */
/* 0x000362000c1e1900 */
/*0a70*/ IADD3.X R9, R19, UR6, RZ, P0, !PT ; /* 0x0000000613097c10 */
/* 0x000fe400087fe4ff */
/*0a80*/ IADD3 R20, P0, R8, UR5, RZ ; /* 0x0000000508147c10 */
/* 0x010fc6000ff1e0ff */
/*0a90*/ LDG.E R8, [R8.64] ; /* 0x0000000808087981 */
/* 0x000f22000c1e1900 */
/*0aa0*/ IADD3.X R21, R9, UR6, RZ, P0, !PT ; /* 0x0000000609157c10 */
/* 0x000fe400087fe4ff */
/*0ab0*/ IADD3 R16, P0, R20, UR5, RZ ; /* 0x0000000514107c10 */
/* 0x001fc8000ff1e0ff */
/*0ac0*/ IADD3.X R17, R21, UR6, RZ, P0, !PT ; /* 0x0000000615117c10 */
/* 0x000fca00087fe4ff */
/*0ad0*/ LDG.E R19, [R16.64] ; /* 0x0000000810137981 */
/* 0x002f22000c1e1900 */
/*0ae0*/ FFMA R28, R28, R27, R29 ; /* 0x0000001b1c1c7223 */
/* 0x004fc6000000001d */
/*0af0*/ LDG.E R27, [R14.64+0x8] ; /* 0x000008080e1b7981 */
/* 0x0000a8000c1e1900 */
/*0b00*/ LDG.E R29, [R14.64+0xc] ; /* 0x00000c080e1d7981 */
/* 0x000122000c1e1900 */
/*0b10*/ FFMA R28, R7, R22, R28 ; /* 0x00000016071c7223 */
/* 0x008fc6000000001c */
/*0b20*/ LDG.E R7, [R20.64] ; /* 0x0000000814077981 */
/* 0x000ee8000c1e1900 */
/*0b30*/ LDG.E R22, [R14.64+0x10] ; /* 0x000010080e167981 */
/* 0x0000e2000c1e1900 */
/*0b40*/ FFMA R23, R23, R26, R28 ; /* 0x0000001a17177223 */
/* 0x020fc6000000001c */
/*0b50*/ LDG.E R26, [R14.64+0x14] ; /* 0x000014080e1a7981 */
/* 0x000162000c1e1900 */
/*0b60*/ FFMA R23, R24, R25, R23 ; /* 0x0000001918177223 */
/* 0x000fe20000000017 */
/*0b70*/ IADD3 R5, P3, R5, 0x8, RZ ; /* 0x0000000805057810 */
/* 0x000fe40007f7e0ff */
/*0b80*/ IADD3 R14, P2, R14, 0x20, RZ ; /* 0x000000200e0e7810 */
/* 0x001fe40007f5e0ff */
/*0b90*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0ba0*/ IMAD.X R6, RZ, RZ, R6, P3 ; /* 0x000000ffff067224 */
/* 0x000fe400018e0606 */
/*0bb0*/ IMAD.X R15, RZ, RZ, R15, P2 ; /* 0x000000ffff0f7224 */
/* 0x000fe200010e060f */
/*0bc0*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0bd0*/ FFMA R18, R18, R27, R23 ; /* 0x0000001b12127223 */
/* 0x004fc80000000017 */
/*0be0*/ FFMA R8, R8, R29, R18 ; /* 0x0000001d08087223 */
/* 0x010fe20000000012 */
/*0bf0*/ IADD3 R18, P1, R16, UR5, RZ ; /* 0x0000000510127c10 */
/* 0x000fc6000ff3e0ff */
/*0c00*/ FFMA R7, R7, R22, R8 ; /* 0x0000001607077223 */
/* 0x008fc80000000008 */
/*0c10*/ FFMA R29, R19, R26, R7 ; /* 0x0000001a131d7223 */
/* 0x020fe20000000007 */
/*0c20*/ IADD3.X R19, R17, UR6, RZ, P1, !PT ; /* 0x0000000611137c10 */
/* 0x000fe40008ffe4ff */
/*0c30*/ ISETP.NE.U32.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fc80003f25070 */
/*0c40*/ ISETP.NE.OR.EX P0, PT, R6, RZ, P0, P1 ; /* 0x000000ff0600720c */
/* 0x000fda0000705710 */
/*0c50*/ @!P0 BRA 0xe30 ; /* 0x000001d000008947 */
/* 0x000fea0003800000 */
/*0c60*/ IADD3 R16, P0, R18, UR5, RZ ; /* 0x0000000512107c10 */
/* 0x000fe2000ff1e0ff */
/*0c70*/ LDG.E R7, [R14.64+-0x8] ; /* 0xfffff8080e077981 */
/* 0x000ea6000c1e1900 */
/*0c80*/ IADD3.X R17, R19, UR6, RZ, P0, !PT ; /* 0x0000000613117c10 */
/* 0x000fe200087fe4ff */
/*0c90*/ LDG.E R18, [R18.64] ; /* 0x0000000812127981 */
/* 0x000ea2000c1e1900 */
/*0ca0*/ IADD3 R8, P0, R16, UR5, RZ ; /* 0x0000000510087c10 */
/* 0x000fc6000ff1e0ff */
/*0cb0*/ LDG.E R16, [R16.64] ; /* 0x0000000810107981 */
/* 0x000ee2000c1e1900 */
/*0cc0*/ IADD3.X R9, R17, UR6, RZ, P0, !PT ; /* 0x0000000611097c10 */
/* 0x000fe400087fe4ff */
/*0cd0*/ IADD3 R20, P0, R8, UR5, RZ ; /* 0x0000000508147c10 */
/* 0x000fe2000ff1e0ff */
/*0ce0*/ LDG.E R22, [R14.64+-0x4] ; /* 0xfffffc080e167981 */
/* 0x000ee6000c1e1900 */
/*0cf0*/ IADD3.X R21, R9, UR6, RZ, P0, !PT ; /* 0x0000000609157c10 */
/* 0x000fe200087fe4ff */
/*0d00*/ LDG.E R8, [R8.64] ; /* 0x0000000808087981 */
/* 0x000f28000c1e1900 */
/*0d10*/ LDG.E R23, [R14.64] ; /* 0x000000080e177981 */
/* 0x000f28000c1e1900 */
/*0d20*/ LDG.E R24, [R20.64] ; /* 0x0000000814187981 */
/* 0x000f68000c1e1900 */
/*0d30*/ LDG.E R25, [R14.64+0x4] ; /* 0x000004080e197981 */
/* 0x000162000c1e1900 */
/*0d40*/ IADD3 R5, P0, R5, 0x4, RZ ; /* 0x0000000405057810 */
/* 0x000fca0007f1e0ff */
/*0d50*/ IMAD.X R6, RZ, RZ, R6, P0 ; /* 0x000000ffff067224 */
/* 0x000fe200000e0606 */
/*0d60*/ ISETP.NE.U32.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fc80003f05070 */
/*0d70*/ ISETP.NE.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fe20003f05300 */
/*0d80*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0d90*/ FFMA R7, R18, R7, R29 ; /* 0x0000000712077223 */
/* 0x004fe2000000001d */
/*0da0*/ IADD3 R18, P2, R20, UR5, RZ ; /* 0x0000000514127c10 */
/* 0x000fc6000ff5e0ff */
/*0db0*/ FFMA R7, R16, R22, R7 ; /* 0x0000001610077223 */
/* 0x008fe20000000007 */
/*0dc0*/ IADD3.X R19, R21, UR6, RZ, P2, !PT ; /* 0x0000000615137c10 */
/* 0x000fc600097fe4ff */
/*0dd0*/ FFMA R7, R8, R23, R7 ; /* 0x0000001708077223 */
/* 0x010fe20000000007 */
/*0de0*/ IADD3 R8, P1, R14, 0x10, RZ ; /* 0x000000100e087810 */
/* 0x000fca0007f3e0ff */
/*0df0*/ IMAD.X R15, RZ, RZ, R15, P1 ; /* 0x000000ffff0f7224 */
/* 0x001fe400008e060f */
/*0e00*/ FFMA R29, R24, R25, R7 ; /* 0x00000019181d7223 */
/* 0x020fe40000000007 */
/*0e10*/ IMAD.MOV.U32 R14, RZ, RZ, R8 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0008 */
/*0e20*/ @P0 BRA 0xc60 ; /* 0xfffffe3000000947 */
/* 0x000fea000383ffff */
/*0e30*/ ISETP.NE.U32.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fc80003f05070 */
/*0e40*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fda0003f05300 */
/*0e50*/ @!P0 BRA 0x1030 ; /* 0x000001d000008947 */
/* 0x000fea0003800000 */
/*0e60*/ USHF.R.S32.HI UR5, URZ, 0x1f, UR4 ; /* 0x0000001f3f057899 */
/* 0x000fe20008011404 */
/*0e70*/ IADD3 R13, P0, R12, UR4, RZ ; /* 0x000000040c0d7c10 */
/* 0x000fe2000ff1e0ff */
/*0e80*/ IMAD.U32 R15, RZ, RZ, UR4 ; /* 0x00000004ff0f7e24 */
/* 0x000fe2000f8e00ff */
/*0e90*/ IADD3 R8, P1, RZ, -R3, RZ ; /* 0x80000003ff087210 */
/* 0x000fc60007f3e0ff */
/*0ea0*/ IADD3.X R4, R4, UR5, RZ, P0, !PT ; /* 0x0000000504047c10 */
/* 0x000fe200087fe4ff */
/*0eb0*/ IMAD.U32 R14, RZ, RZ, UR5 ; /* 0x00000005ff0e7e24 */
/* 0x000fe2000f8e00ff */
/*0ec0*/ LEA R12, P0, R13, c[0x0][0x160], 0x2 ; /* 0x000058000d0c7a11 */
/* 0x000fe200078010ff */
/*0ed0*/ IMAD.X R9, RZ, RZ, -0x1, P1 ; /* 0xffffffffff097424 */
/* 0x000fc600008e06ff */
/*0ee0*/ LEA.HI.X R13, R13, c[0x0][0x164], R4, 0x2, P0 ; /* 0x000059000d0d7a11 */
/* 0x000fe400000f1404 */
/*0ef0*/ IMAD R4, R14, c[0x0][0x188], RZ ; /* 0x000062000e047a24 */
/* 0x000fe400078e02ff */
/*0f00*/ IMAD.WIDE.U32 R6, R15, c[0x0][0x188], R10 ; /* 0x000062000f067a25 */
/* 0x000fc800078e000a */
/*0f10*/ IMAD R3, R15, c[0x0][0x18c], R4 ; /* 0x000063000f037a24 */
/* 0x000fe200078e0204 */
/*0f20*/ LEA R4, P0, R6, c[0x0][0x168], 0x2 ; /* 0x00005a0006047a11 */
/* 0x000fc600078010ff */
/*0f30*/ IMAD.IADD R3, R7, 0x1, R3 ; /* 0x0000000107037824 */
/* 0x000fe400078e0203 */
/*0f40*/ IMAD.MOV.U32 R7, RZ, RZ, R13 ; /* 0x000000ffff077224 */
/* 0x000fc600078e000d */
/*0f50*/ LEA.HI.X R5, R6, c[0x0][0x16c], R3, 0x2, P0 ; /* 0x00005b0006057a11 */
/* 0x000fe200000f1403 */
/*0f60*/ IMAD.MOV.U32 R6, RZ, RZ, R12 ; /* 0x000000ffff067224 */
/* 0x000fc800078e000c */
/*0f70*/ LDG.E R4, [R4.64] ; /* 0x0000000804047981 */
/* 0x000ea8000c1e1900 */
/*0f80*/ LDG.E R3, [R6.64] ; /* 0x0000000806037981 */
/* 0x000ea2000c1e1900 */
/*0f90*/ IADD3 R8, P0, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fca0007f1e0ff */
/*0fa0*/ IMAD.X R9, RZ, RZ, R9, P0 ; /* 0x000000ffff097224 */
/* 0x000fe200000e0609 */
/*0fb0*/ ISETP.NE.U32.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc80003f05070 */
/*0fc0*/ ISETP.NE.AND.EX P0, PT, R9, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x000fe40003f05300 */
/*0fd0*/ IADD3 R12, P2, R12, 0x4, RZ ; /* 0x000000040c0c7810 */
/* 0x000fe40007f5e0ff */
/*0fe0*/ IADD3 R15, P1, R15, 0x1, RZ ; /* 0x000000010f0f7810 */
/* 0x000fc60007f3e0ff */
/*0ff0*/ IMAD.X R13, RZ, RZ, R13, P2 ; /* 0x000000ffff0d7224 */
/* 0x000fe400010e060d */
/*1000*/ IMAD.X R14, RZ, RZ, R14, P1 ; /* 0x000000ffff0e7224 */
/* 0x000fe400008e060e */
/*1010*/ FFMA R29, R4, R3, R29 ; /* 0x00000003041d7223 */
/* 0x004fe4000000001d */
/*1020*/ @P0 BRA 0xef0 ; /* 0xfffffec000000947 */
/* 0x000fea000383ffff */
/*1030*/ IMAD R5, R2, c[0x0][0x188], RZ ; /* 0x0000620002057a24 */
/* 0x000fe400078e02ff */
/*1040*/ IMAD.MOV.U32 R2, RZ, RZ, R10 ; /* 0x000000ffff027224 */
/* 0x000fe400078e000a */
/*1050*/ IMAD.MOV.U32 R3, RZ, RZ, R11 ; /* 0x000000ffff037224 */
/* 0x000fc400078e000b */
/*1060*/ IMAD R5, R0.reuse, c[0x0][0x18c], R5 ; /* 0x0000630000057a24 */
/* 0x040fe400078e0205 */
/*1070*/ IMAD.WIDE.U32 R2, R0, c[0x0][0x188], R2 ; /* 0x0000620000027a25 */
/* 0x000fc800078e0002 */
/*1080*/ IMAD.IADD R3, R3, 0x1, R5 ; /* 0x0000000103037824 */
/* 0x000fe200078e0205 */
/*1090*/ LEA R4, P0, R2, c[0x0][0x170], 0x2 ; /* 0x00005c0002047a11 */
/* 0x000fc800078010ff */
/*10a0*/ LEA.HI.X R5, R2, c[0x0][0x174], R3, 0x2, P0 ; /* 0x00005d0002057a11 */
/* 0x000fca00000f1403 */
/*10b0*/ STG.E [R4.64], R29 ; /* 0x0000001d04007986 */
/* 0x000fe2000c101908 */
/*10c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*10d0*/ BRA 0x10d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10cuda_sgemmPfS_S_mmm
.globl _Z10cuda_sgemmPfS_S_mmm
.p2align 8
.type _Z10cuda_sgemmPfS_S_mmm,@function
_Z10cuda_sgemmPfS_S_mmm:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x3c
s_load_b64 s[2:3], s[0:1], 0x28
v_and_b32_e32 v3, 0x3ff, v0
s_add_u32 s4, s0, 48
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s6, v[3:4]
s_mov_b32 s6, exec_lo
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_7
s_load_b32 s6, s[4:5], 0xc
s_load_b64 s[4:5], s[0:1], 0x18
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s6, s6, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, s15, s6, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[3:4]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
s_load_b64 s[4:5], s[0:1], 0x20
s_mov_b64 s[6:7], 0
s_waitcnt lgkmcnt(0)
s_cmp_eq_u64 s[4:5], 0
s_cbranch_scc1 .LBB0_5
s_load_b128 s[8:11], s[0:1], 0x0
v_mul_lo_u32 v0, v4, s4
v_mul_lo_u32 v7, v3, s5
v_mad_u64_u32 v[5:6], null, v3, s4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add3_u32 v6, v6, v7, v0
v_lshlrev_b64 v[7:8], 2, v[1:2]
v_mov_b32_e32 v0, 0
v_lshlrev_b64 v[9:10], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s10, v7
v_add_co_ci_u32_e32 v6, vcc_lo, s11, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v7, vcc_lo, s8, v9
v_add_co_ci_u32_e32 v8, vcc_lo, s9, v10, vcc_lo
s_lshl_b64 s[8:9], s[2:3], 2
.p2align 6
.LBB0_4:
global_load_b32 v9, v[7:8], off
global_load_b32 v10, v[5:6], off
s_add_u32 s6, s6, 1
v_add_co_u32 v5, vcc_lo, v5, s8
s_addc_u32 s7, s7, 0
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
v_cmp_ge_u64_e64 s10, s[6:7], s[4:5]
v_add_co_u32 v7, vcc_lo, v7, 4
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
s_and_b32 vcc_lo, exec_lo, s10
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v0, v9, v10
s_cbranch_vccz .LBB0_4
s_branch .LBB0_6
.LBB0_5:
v_mov_b32_e32 v0, 0
.LBB0_6:
s_load_b64 s[0:1], s[0:1], 0x10
v_mul_lo_u32 v6, v4, s2
v_mul_lo_u32 v7, v3, s3
v_mad_u64_u32 v[4:5], null, v3, s2, 0
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v5, v5, v7, v6
v_lshlrev_b64 v[3:4], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, v3, v1
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10cuda_sgemmPfS_S_mmm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10cuda_sgemmPfS_S_mmm, .Lfunc_end0-_Z10cuda_sgemmPfS_S_mmm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10cuda_sgemmPfS_S_mmm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10cuda_sgemmPfS_S_mmm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c1f49_00000000-6_cuda_sgemm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB12287:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE12287:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z10cuda_sgemmPfS_S_mmmPfS_S_mmm
.type _Z37__device_stub__Z10cuda_sgemmPfS_S_mmmPfS_S_mmm, @function
_Z37__device_stub__Z10cuda_sgemmPfS_S_mmmPfS_S_mmm:
.LFB12309:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10cuda_sgemmPfS_S_mmm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE12309:
.size _Z37__device_stub__Z10cuda_sgemmPfS_S_mmmPfS_S_mmm, .-_Z37__device_stub__Z10cuda_sgemmPfS_S_mmmPfS_S_mmm
.globl _Z10cuda_sgemmPfS_S_mmm
.type _Z10cuda_sgemmPfS_S_mmm, @function
_Z10cuda_sgemmPfS_S_mmm:
.LFB12310:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z10cuda_sgemmPfS_S_mmmPfS_S_mmm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE12310:
.size _Z10cuda_sgemmPfS_S_mmm, .-_Z10cuda_sgemmPfS_S_mmm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10cuda_sgemmPfS_S_mmm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB12312:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10cuda_sgemmPfS_S_mmm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE12312:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_sgemm.hip"
.globl _Z25__device_stub__cuda_sgemmPfS_S_mmm # -- Begin function _Z25__device_stub__cuda_sgemmPfS_S_mmm
.p2align 4, 0x90
.type _Z25__device_stub__cuda_sgemmPfS_S_mmm,@function
_Z25__device_stub__cuda_sgemmPfS_S_mmm: # @_Z25__device_stub__cuda_sgemmPfS_S_mmm
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10cuda_sgemmPfS_S_mmm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z25__device_stub__cuda_sgemmPfS_S_mmm, .Lfunc_end0-_Z25__device_stub__cuda_sgemmPfS_S_mmm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10cuda_sgemmPfS_S_mmm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10cuda_sgemmPfS_S_mmm,@object # @_Z10cuda_sgemmPfS_S_mmm
.section .rodata,"a",@progbits
.globl _Z10cuda_sgemmPfS_S_mmm
.p2align 3, 0x0
_Z10cuda_sgemmPfS_S_mmm:
.quad _Z25__device_stub__cuda_sgemmPfS_S_mmm
.size _Z10cuda_sgemmPfS_S_mmm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10cuda_sgemmPfS_S_mmm"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__cuda_sgemmPfS_S_mmm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10cuda_sgemmPfS_S_mmm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <math.h>
#include <cuda.h>
using namespace std;
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
// Divergence of a Vector with variable coefficient !
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
void DivCPU(double* Dn, double* Phi, double* U, double* V, int row, int col,double delX,double delY){
for(int i = 1; i<(row-1); ++i){
for(int j =1; j<(col-1); ++j){
int k = i*col+j;
double PhiP = Phi[k];
double PhiE = Phi[k+1];
double PhiW = Phi[k-1];
double PhiN = Phi[k-col];
double PhiS = Phi[k+col];
double UP = U[k];
double UE = U[k+1];
double UW = U[k-1];
//double UN = U[k-col];
//double US = U[k+col];
double VP = V[k];
//double VE = V[k+1];
//double VW = V[k-1];
double VN = V[k-col];
double VS = V[k+col];
double Ee = 0.5*(UE*PhiE+UP*PhiP);
double Ew = 0.5*(UW*PhiW+UP*PhiP);
double Fn = 0.5*(VN*PhiN+VP*PhiP);
double Fs = 0.5*(VS*PhiS+VP*PhiP);
Dn[k] = delX*(Fn-Fs)+delY*(Ee-Ew);
}
}
}
__global__ void Div(double* Dn, double* Phi, double* U, double* V, int row, int col,double delX,double delY){
// Get global thread ID
int k = blockIdx.x*blockDim.x+threadIdx.x;
int n = (row-1)*(col-1);
// Do for only inner points
if (k >0 && k<n) {
double PhiP = Phi[k];
double PhiE = Phi[k+1];
double PhiW = Phi[k-1];
double PhiN = Phi[k-col];
double PhiS = Phi[k+col];
double UP = U[k];
double UE = U[k+1];
double UW = U[k-1];
//double UN = U[k-col];
//double US = U[k+col];
double VP = V[k];
//double VE = V[k+1];
//double VW = V[k-1];
double VN = V[k-col];
double VS = V[k+col];
double Ee = 0.5*(UE*PhiE+UP*PhiP);
double Ew = 0.5*(UW*PhiW+UP*PhiP);
double Fn = 0.5*(VN*PhiN+VP*PhiP);
double Fs = 0.5*(VS*PhiS+VP*PhiP);
Dn[k] = delX*(Fn-Fs)+delY*(Ee-Ew);
}
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
// Divergence of a Vector with No coefficient !
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
__global__ void Divergence(double* Dn, double* U, double* V,int row, int col, double delX, double delY){
// Get global thread ID
int k = blockIdx.x*blockDim.x+threadIdx.x;
int n = (row-1)*(col-1);
// Do for only inner points
if (k >0 && k<n) {
double UP = U[k];
double UE = U[k+1];
double UW = U[k-1];
//double UN = U[k-col];
//double US = U[k+col];
double VP = V[k];
// double VE = V[k+1];
//double VW = V[k-1];
double VN = V[k-col];
double VS = V[k+col];
double Ue = 0.5*(UE+UP);
double Uw = 0.5*(UW+UP);
//double Un = 0.5*(UN+UP);
//double Us = 0.5*(US+UP);
// double Ve = 0.5*(VE+VP);
// double Vw = 0.5*(VW+VP);
double Vn = 0.5*(VN+VP);
double Vs = 0.5*(VS+VP);
Dn[k] = (Ue-Uw)*delY+(Vn-Vs)*delX;
}
}
void DivergenceCPU(double* Dn, double* U, double* V,int row, int col, double delX, double delY){
for(int i = 1; i<(row-1); ++i){
for(int j =1; j<(col-1); ++j){
int k = i*col+j;
double UP = U[k];
double UE = U[k+1];
double UW = U[k-1];
//double UN = U[k-col];
//double US = U[k+col];
double VP = V[k];
// double VE = V[k+1];
// double VW = V[k-1];
double VN = V[k-col];
double VS = V[k+col];
double Ue = 0.5*(UE+UP);
double Uw = 0.5*(UW+UP);
//double Un = 0.5*(UN+UP);
//double Us = 0.5*(US+UP);
// double Ve = 0.5*(VE+VP);
//double Vw = 0.5*(VW+VP);
double Vn = 0.5*(VN+VP);
double Vs = 0.5*(VS+VP);
Dn[k] = (Ue-Uw)*delY+(Vn-Vs)*delX;
}
}
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
// Laplacian of a Scalar !
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
void LaplacianCPU(double* Ln, double *Phi, int row, int col, double delX, double delY){
for(int i = 1; i<(row-1); i++){
for(int j =1; j<(col-1); j++){
int k = i*col+j;
double PhiP = Phi[k];
double PhiE = Phi[k+1];
double PhiW = Phi[k-1];
double PhiN = Phi[k-col];
double PhiS = Phi[k+col];
double Ee = (PhiE-PhiP)/delX;
double Ew = (PhiP-PhiW)/delX;
double Fn = (PhiN-PhiP)/delY;
double Fs = (PhiP-PhiS)/delY;
Ln[k] = delX*(Fn-Fs)+delY*(Ee-Ew);
}
}
}
__global__ void Laplacian(double* Ln, double *Phi, int row, int col, double delX, double delY){
// Get global thread ID
int k = blockIdx.x*blockDim.x+threadIdx.x;
int n = (row-1)*(col-1);
// Do for only inner points
if (k >0 && k<n) {
double PhiP = Phi[k];
double PhiE = Phi[k+1];
double PhiW = Phi[k-1];
double PhiN = Phi[k-col];
double PhiS = Phi[k+col];
double Ee = (PhiE-PhiP)/delX;
double Ew = (PhiP-PhiW)/delX;
double Fn = (PhiN-PhiP)/delY;
double Fs = (PhiP-PhiS)/delY;
Ln[k] = delX*(Fn-Fs)+delY*(Ee-Ew);
}
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
// Gradient Computation using Finite Volume !
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
void gradient(double* gradxPhi,double* gradyPhi,
double* vfacePhi,double* hfacePhi,
int cellRow, int cellCol, double delX, double delY,
int vfaceCol, int hfaceCol){
for(int i = 1; i<(cellRow-1); ++i){
for(int j =1; j<(cellCol-1); ++j){
double Phie = vfacePhi[i*vfaceCol+(j+1)];
double Phiw = vfacePhi[i*vfaceCol+j];
double Phin = hfacePhi[i*hfaceCol+j];
double Phis = hfacePhi[(i+1)*hfaceCol+j];
gradxPhi[i*cellCol+j] = (Phie-Phiw)/delX;
gradyPhi[i*cellCol+j] = (Phin-Phis)/delY;
}
}
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
// Gradient Computation using Finite Difference !
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
__global__ void gradient(double* gradxPhi,double* gradyPhi,double* Phi,
int row, int col, double delX, double delY){
// Get global thread ID
int k = blockIdx.x*blockDim.x+threadIdx.x;
int n = (row-1)*(col-1);
// Do for only inner points
if (k >0 && k<n) {
double Phie = Phi[k+1];
double Phiw = Phi[k-1];
double Phin = Phi[k-col];
double Phis = Phi[k+col];
gradxPhi[k] = (Phie-Phiw)/(2*delX);
gradyPhi[k] = (Phin-Phis)/(2*delY);
}
}
void gradientCPU(double* gradxPhi,double* gradyPhi,double* Phi,
int row, int col, double delX, double delY){
for(int i = 1; i<(row-1); ++i){
for(int j =1; j<(col-1); ++j){
int k = i*col+j;
double Phie = Phi[k+1];
double Phiw = Phi[k-1];
double Phin = Phi[k-col];
double Phis = Phi[k+col];
gradxPhi[k] = (Phie-Phiw)/(2*delX);
gradyPhi[k] = (Phin-Phis)/(2*delY);
}
}
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
// Interpolation of Vertex Values !
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
void vertexInterpolate(double* vertPhi, double* cellPhi, int vertRow, int vertCol, int cellCol){
// Inner Points
for(int i = 1; i<(vertRow-1); ++i){
for(int j =1; j<(vertCol-1); ++j){
double Ta = cellPhi[(i-1)*cellCol+(j-1)]; // NW
double Tb = cellPhi[(i-1)*cellCol+j]; // NE
double Tc = cellPhi[(i*cellCol)+(j-1)]; // SW
double Td = cellPhi[i*cellCol+j]; //SE
vertPhi[i*vertCol+j]=0.25*(Ta+Tb+Tc+Td);
}
}
//Boundary points - Set it to Boundary Cell points
//North Boundary
for (int i = 0; i<vertCol; i++){
vertPhi[i]= cellPhi[i+vertCol];
}
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
// Interpolation of Vertical FaceCenter Interpolation !
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
void vfaceInterpolate(double* vfacePhi, double* vertPhi,
double* cellPhi, int vfaceRow, int vfaceCol,
int vertCol, int cellCol){
for(int i = 1; i<(vfaceRow-1); ++i){
for(int j =1; j<(vfaceCol-1); ++j){
double Ta = cellPhi[i*cellCol+(j-1)]; // West cell
double Tb = cellPhi[i*cellCol+j]; // East cell
double Tc = vertPhi[i*vertCol+j]; // North Vertex
double Td = vertPhi[(i+1)*vertCol+j]; //South Vertex
vfacePhi[i*vfaceCol+j]=0.25*(Ta+Tb+Tc+Td);
}
}
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
// Interpolation of Horizontal FaceCenter Interpolation !
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
void hfaceInterpolate(double* hfacePhi, double* vertPhi,
double* cellPhi, int hfaceRow, int hfaceCol,
int vertCol, int cellCol){
for(int i = 1; i<(hfaceRow-1); ++i){
for(int j =1; j<(hfaceCol-1); ++j){
double Ta = vertPhi[i*vertCol+j]; // West vertex
double Tb = vertPhi[i*vertCol+(j+1)]; // East vertex
double Tc = cellPhi[(i-1)*cellCol+j]; // North cell
double Td = cellPhi[i*cellCol+j]; //South cell
hfacePhi[i*hfaceCol+j]=0.25*(Ta+Tb+Tc+Td);
}
}
} | .file "tmpxft_0015eed1_00000000-6_finiteVolumeOperators.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3679:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3679:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6DivCPUPdS_S_S_iidd
.type _Z6DivCPUPdS_S_S_iidd, @function
_Z6DivCPUPdS_S_S_iidd:
.LFB3669:
.cfi_startproc
endbr64
cmpl $2, %r8d
jle .L11
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rdi, %r11
movq %rcx, %r10
movl %r9d, %r13d
movapd %xmm0, %xmm4
leal -1(%r8), %r14d
movslq %r9d, %rdi
movq %rdi, %r8
negq %r8
salq $3, %r8
leaq (%rsi,%r8), %rbx
salq $3, %rdi
leaq (%rsi,%rdi), %r9
addq %rcx, %r8
addq %rcx, %rdi
movl %r13d, %r12d
movl $1, %ebp
leal -1(%r13), %r15d
movsd .LC0(%rip), %xmm3
jmp .L5
.L7:
movslq %r12d, %rcx
leaq 8(,%rcx,8), %rax
addq %r15, %rcx
salq $3, %rcx
.L6:
movsd (%rsi,%rax), %xmm6
movapd %xmm6, %xmm7
mulsd (%rdx,%rax), %xmm7
mulsd (%r10,%rax), %xmm6
movsd (%rbx,%rax), %xmm0
mulsd (%r8,%rax), %xmm0
addsd %xmm6, %xmm0
mulsd %xmm3, %xmm0
movsd (%r9,%rax), %xmm5
mulsd (%rdi,%rax), %xmm5
movapd %xmm5, %xmm2
addsd %xmm6, %xmm2
mulsd %xmm3, %xmm2
subsd %xmm2, %xmm0
mulsd %xmm4, %xmm0
movsd 8(%rsi,%rax), %xmm2
mulsd 8(%rdx,%rax), %xmm2
addsd %xmm7, %xmm2
mulsd %xmm3, %xmm2
movsd -8(%rsi,%rax), %xmm6
mulsd -8(%rdx,%rax), %xmm6
movapd %xmm6, %xmm5
addsd %xmm7, %xmm5
mulsd %xmm3, %xmm5
subsd %xmm5, %xmm2
mulsd %xmm1, %xmm2
addsd %xmm2, %xmm0
movsd %xmm0, (%r11,%rax)
addq $8, %rax
cmpq %rcx, %rax
jne .L6
.L8:
addl $1, %ebp
addl %r13d, %r12d
cmpl %r14d, %ebp
je .L3
.L5:
cmpl $2, %r13d
jg .L7
jmp .L8
.L3:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE3669:
.size _Z6DivCPUPdS_S_S_iidd, .-_Z6DivCPUPdS_S_S_iidd
.globl _Z13DivergenceCPUPdS_S_iidd
.type _Z13DivergenceCPUPdS_S_iidd, @function
_Z13DivergenceCPUPdS_S_iidd:
.LFB3670:
.cfi_startproc
endbr64
cmpl $2, %ecx
jle .L22
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r9
movq %rdx, %rdi
movl %r8d, %ebx
movapd %xmm0, %xmm5
leal -1(%rcx), %ebp
movslq %r8d, %rax
movq %rax, %rdx
negq %rdx
leaq (%rdi,%rdx,8), %r10
leaq (%rdi,%rax,8), %rcx
movl $1, %r11d
leal -1(%r8), %r12d
movsd .LC0(%rip), %xmm4
jmp .L16
.L18:
movslq %r8d, %rdx
leaq 8(,%rdx,8), %rax
addq %r12, %rdx
salq $3, %rdx
.L17:
movsd (%rsi,%rax), %xmm2
movsd (%rdi,%rax), %xmm3
movapd %xmm2, %xmm0
addsd 8(%rsi,%rax), %xmm0
mulsd %xmm4, %xmm0
addsd -8(%rsi,%rax), %xmm2
mulsd %xmm4, %xmm2
subsd %xmm2, %xmm0
mulsd %xmm1, %xmm0
movapd %xmm3, %xmm2
addsd (%r10,%rax), %xmm2
mulsd %xmm4, %xmm2
addsd (%rcx,%rax), %xmm3
mulsd %xmm4, %xmm3
subsd %xmm3, %xmm2
mulsd %xmm5, %xmm2
addsd %xmm2, %xmm0
movsd %xmm0, (%r9,%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L17
.L19:
addl $1, %r11d
addl %ebx, %r8d
cmpl %ebp, %r11d
je .L14
.L16:
cmpl $2, %ebx
jg .L18
jmp .L19
.L14:
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE3670:
.size _Z13DivergenceCPUPdS_S_iidd, .-_Z13DivergenceCPUPdS_S_iidd
.globl _Z12LaplacianCPUPdS_iidd
.type _Z12LaplacianCPUPdS_iidd, @function
_Z12LaplacianCPUPdS_iidd:
.LFB3671:
.cfi_startproc
endbr64
cmpl $2, %edx
jle .L33
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
movq %rdi, %rbx
movq %rsi, %rbp
movl %ecx, %r10d
movapd %xmm0, %xmm4
leal -1(%rdx), %r11d
movslq %ecx, %rdi
movq %rdi, %rsi
negq %rsi
salq $3, %rsi
movl %ecx, %r9d
movl $1, %r8d
leal -3(%rcx), %r13d
leaq 8(%rbp), %r12
jmp .L27
.L29:
movslq %r9d, %rcx
leaq 0(,%rcx,8), %rdx
leaq 0(%rbp,%rdx), %rax
addq %rbx, %rdx
addq %r13, %rcx
leaq (%r12,%rcx,8), %rcx
.L28:
movsd 8(%rax), %xmm3
movsd 8(%rax,%rsi), %xmm0
subsd %xmm3, %xmm0
divsd %xmm1, %xmm0
movapd %xmm3, %xmm2
subsd 8(%rax,%rdi,8), %xmm2
divsd %xmm1, %xmm2
subsd %xmm2, %xmm0
mulsd %xmm4, %xmm0
movsd 16(%rax), %xmm2
subsd %xmm3, %xmm2
divsd %xmm4, %xmm2
subsd (%rax), %xmm3
divsd %xmm4, %xmm3
subsd %xmm3, %xmm2
mulsd %xmm1, %xmm2
addsd %xmm2, %xmm0
movsd %xmm0, 8(%rdx)
addq $8, %rax
addq $8, %rdx
cmpq %rcx, %rax
jne .L28
.L30:
addl $1, %r8d
addl %r10d, %r9d
cmpl %r11d, %r8d
je .L25
.L27:
cmpl $2, %r10d
jg .L29
jmp .L30
.L25:
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
ret
.cfi_endproc
.LFE3671:
.size _Z12LaplacianCPUPdS_iidd, .-_Z12LaplacianCPUPdS_iidd
.globl _Z8gradientPdS_S_S_iiddii
.type _Z8gradientPdS_S_S_iiddii, @function
_Z8gradientPdS_S_S_iiddii:
.LFB3672:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rdi, -24(%rsp)
movq %rsi, -16(%rsp)
movq %rdx, -8(%rsp)
movl 64(%rsp), %r14d
cmpl $2, %r8d
jle .L36
movq %rcx, %r13
movl %r9d, %r12d
leal -1(%r8), %r15d
movl %r9d, %ebp
movl %r14d, %r11d
movl 56(%rsp), %ebx
movl $1, %r9d
leal -1(%r12), %r10d
jmp .L38
.L40:
movslq %ebx, %rax
movq -8(%rsp), %rsi
leaq (%rsi,%rax,8), %rdx
movslq %r11d, %rax
leaq 0(%r13,%rax,8), %r8
leal (%r11,%r14), %eax
cltq
leaq 0(%r13,%rax,8), %rdi
movslq %ebp, %rcx
salq $3, %rcx
movq -24(%rsp), %rax
leaq (%rax,%rcx), %rsi
movq -16(%rsp), %rax
addq %rax, %rcx
movl $1, %eax
.L39:
movsd (%r8,%rax,8), %xmm2
movsd (%rdi,%rax,8), %xmm4
movsd 8(%rdx,%rax,8), %xmm3
subsd (%rdx,%rax,8), %xmm3
divsd %xmm0, %xmm3
movsd %xmm3, (%rsi,%rax,8)
subsd %xmm4, %xmm2
divsd %xmm1, %xmm2
movsd %xmm2, (%rcx,%rax,8)
addq $1, %rax
cmpq %r10, %rax
jne .L39
.L41:
addl $1, %r9d
addl 56(%rsp), %ebx
addl %r14d, %r11d
addl %r12d, %ebp
cmpl %r15d, %r9d
je .L36
.L38:
cmpl $2, %r12d
jg .L40
jmp .L41
.L36:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _Z8gradientPdS_S_S_iiddii, .-_Z8gradientPdS_S_S_iiddii
.globl _Z11gradientCPUPdS_S_iidd
.type _Z11gradientCPUPdS_S_iidd, @function
_Z11gradientCPUPdS_S_iidd:
.LFB3673:
.cfi_startproc
endbr64
cmpl $2, %ecx
jle .L52
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl %r8d, %ebx
leal -1(%rcx), %ebp
movslq %r8d, %rax
movq %rax, %rcx
negq %rcx
leaq (%rdx,%rcx,8), %r10
leaq (%rdx,%rax,8), %r9
movl $1, %r11d
leal -1(%r8), %r12d
jmp .L46
.L48:
movapd %xmm0, %xmm6
addsd %xmm0, %xmm6
movapd %xmm1, %xmm5
addsd %xmm1, %xmm5
movslq %r8d, %rcx
leaq 8(,%rcx,8), %rax
addq %r12, %rcx
salq $3, %rcx
.L47:
movsd (%r10,%rax), %xmm2
movsd (%r9,%rax), %xmm4
movsd 8(%rdx,%rax), %xmm3
subsd -8(%rdx,%rax), %xmm3
divsd %xmm6, %xmm3
movsd %xmm3, (%rdi,%rax)
subsd %xmm4, %xmm2
divsd %xmm5, %xmm2
movsd %xmm2, (%rsi,%rax)
addq $8, %rax
cmpq %rcx, %rax
jne .L47
.L49:
addl $1, %r11d
addl %ebx, %r8d
cmpl %ebp, %r11d
je .L44
.L46:
cmpl $2, %ebx
jg .L48
jmp .L49
.L44:
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE3673:
.size _Z11gradientCPUPdS_S_iidd, .-_Z11gradientCPUPdS_S_iidd
.globl _Z17vertexInterpolatePdS_iii
.type _Z17vertexInterpolatePdS_iii, @function
_Z17vertexInterpolatePdS_iii:
.LFB3674:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
movq %rdi, %rbx
movq %rsi, %r11
movl %ecx, %r9d
cmpl $2, %edx
jle .L56
movl %r8d, %r12d
leal -1(%rdx), %r13d
movl %ecx, %ebp
movl $0, %r10d
movl $1, %r8d
leal -1(%rcx), %edi
movsd .LC1(%rip), %xmm1
jmp .L57
.L59:
movslq %r10d, %rax
leaq (%r11,%rax,8), %rcx
leal (%r10,%r12), %eax
cltq
leaq (%r11,%rax,8), %rdx
movslq %ebp, %rax
leaq (%rbx,%rax,8), %rsi
movl $1, %eax
.L58:
movsd -8(%rcx,%rax,8), %xmm0
addsd (%rcx,%rax,8), %xmm0
addsd -8(%rdx,%rax,8), %xmm0
addsd (%rdx,%rax,8), %xmm0
mulsd %xmm1, %xmm0
movsd %xmm0, (%rsi,%rax,8)
addq $1, %rax
cmpq %rdi, %rax
jne .L58
.L60:
addl $1, %r8d
addl %r12d, %r10d
addl %r9d, %ebp
cmpl %r13d, %r8d
je .L56
.L57:
cmpl $2, %r9d
jg .L59
jmp .L60
.L56:
testl %r9d, %r9d
jle .L55
movslq %r9d, %rdx
salq $3, %rdx
addq %rdx, %r11
movl $0, %eax
.L62:
movsd (%r11,%rax), %xmm0
movsd %xmm0, (%rbx,%rax)
addq $8, %rax
cmpq %rax, %rdx
jne .L62
.L55:
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _Z17vertexInterpolatePdS_iii, .-_Z17vertexInterpolatePdS_iii
.globl _Z16vfaceInterpolatePdS_S_iiii
.type _Z16vfaceInterpolatePdS_S_iiii, @function
_Z16vfaceInterpolatePdS_S_iiii:
.LFB3675:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rdi, -16(%rsp)
movq %rdx, -8(%rsp)
movl 56(%rsp), %r15d
cmpl $2, %ecx
jle .L66
movq %rsi, %rbp
movl %r8d, %r12d
movl %r9d, %r13d
leal -1(%rcx), %r14d
movl %r8d, %ebx
movl %r9d, %r11d
movl %r15d, %r9d
movl $1, %r8d
leal -1(%r12), %r10d
movsd .LC1(%rip), %xmm1
jmp .L68
.L70:
movslq %r9d, %rax
movq -8(%rsp), %rsi
leaq (%rsi,%rax,8), %rdx
movslq %r11d, %rax
leaq 0(%rbp,%rax,8), %rdi
leal (%r11,%r13), %eax
cltq
leaq 0(%rbp,%rax,8), %rsi
movslq %ebx, %rax
movq -16(%rsp), %rcx
leaq (%rcx,%rax,8), %rcx
movl $1, %eax
.L69:
movsd -8(%rdx,%rax,8), %xmm0
addsd (%rdx,%rax,8), %xmm0
addsd (%rdi,%rax,8), %xmm0
addsd (%rsi,%rax,8), %xmm0
mulsd %xmm1, %xmm0
movsd %xmm0, (%rcx,%rax,8)
addq $1, %rax
cmpq %r10, %rax
jne .L69
.L71:
addl $1, %r8d
addl %r15d, %r9d
addl %r13d, %r11d
addl %r12d, %ebx
cmpl %r14d, %r8d
je .L66
.L68:
cmpl $2, %r12d
jg .L70
jmp .L71
.L66:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size _Z16vfaceInterpolatePdS_S_iiii, .-_Z16vfaceInterpolatePdS_S_iiii
.globl _Z16hfaceInterpolatePdS_S_iiii
.type _Z16hfaceInterpolatePdS_S_iiii, @function
_Z16hfaceInterpolatePdS_S_iiii:
.LFB3676:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rdi, -16(%rsp)
movq %rsi, -8(%rsp)
movl 56(%rsp), %r13d
cmpl $2, %ecx
jle .L74
movq %rdx, %r12
movl %r8d, %ebp
movl %r9d, %r15d
leal -1(%rcx), %r14d
movl %r8d, %ebx
movl $0, %r11d
movl $1, %r8d
leal -1(%rbp), %r10d
movsd .LC1(%rip), %xmm1
jmp .L76
.L78:
movslq %r9d, %rax
movq -8(%rsp), %rsi
leaq (%rsi,%rax,8), %rdx
movslq %r11d, %rax
leaq (%r12,%rax,8), %rdi
leal (%r11,%r13), %eax
cltq
leaq (%r12,%rax,8), %rsi
movslq %ebx, %rax
movq -16(%rsp), %rcx
leaq (%rcx,%rax,8), %rcx
movl $1, %eax
.L77:
movsd (%rdx,%rax,8), %xmm0
addsd 8(%rdx,%rax,8), %xmm0
addsd (%rdi,%rax,8), %xmm0
addsd (%rsi,%rax,8), %xmm0
mulsd %xmm1, %xmm0
movsd %xmm0, (%rcx,%rax,8)
addq $1, %rax
cmpq %r10, %rax
jne .L77
.L79:
addl $1, %r8d
addl %r15d, %r9d
addl %r13d, %r11d
addl %ebp, %ebx
cmpl %r14d, %r8d
je .L74
.L76:
cmpl $2, %ebp
jg .L78
jmp .L79
.L74:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3676:
.size _Z16hfaceInterpolatePdS_S_iiii, .-_Z16hfaceInterpolatePdS_S_iiii
.globl _Z32__device_stub__Z3DivPdS_S_S_iiddPdS_S_S_iidd
.type _Z32__device_stub__Z3DivPdS_S_S_iiddPdS_S_S_iidd, @function
_Z32__device_stub__Z3DivPdS_S_S_iiddPdS_S_S_iidd:
.LFB3701:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movl %r8d, 28(%rsp)
movl %r9d, 24(%rsp)
movsd %xmm0, 16(%rsp)
movsd %xmm1, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 28(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L86
.L82:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L87
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L86:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z3DivPdS_S_S_iidd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L82
.L87:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3701:
.size _Z32__device_stub__Z3DivPdS_S_S_iiddPdS_S_S_iidd, .-_Z32__device_stub__Z3DivPdS_S_S_iiddPdS_S_S_iidd
.globl _Z3DivPdS_S_S_iidd
.type _Z3DivPdS_S_S_iidd, @function
_Z3DivPdS_S_S_iidd:
.LFB3702:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z3DivPdS_S_S_iiddPdS_S_S_iidd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3702:
.size _Z3DivPdS_S_S_iidd, .-_Z3DivPdS_S_S_iidd
.globl _Z38__device_stub__Z10DivergencePdS_S_iiddPdS_S_iidd
.type _Z38__device_stub__Z10DivergencePdS_S_iiddPdS_S_iidd, @function
_Z38__device_stub__Z10DivergencePdS_S_iiddPdS_S_iidd:
.LFB3703:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movsd %xmm0, 8(%rsp)
movsd %xmm1, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L94
.L90:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L95
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L94:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10DivergencePdS_S_iidd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L90
.L95:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3703:
.size _Z38__device_stub__Z10DivergencePdS_S_iiddPdS_S_iidd, .-_Z38__device_stub__Z10DivergencePdS_S_iiddPdS_S_iidd
.globl _Z10DivergencePdS_S_iidd
.type _Z10DivergencePdS_S_iidd, @function
_Z10DivergencePdS_S_iidd:
.LFB3704:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z10DivergencePdS_S_iiddPdS_S_iidd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3704:
.size _Z10DivergencePdS_S_iidd, .-_Z10DivergencePdS_S_iidd
.globl _Z34__device_stub__Z9LaplacianPdS_iiddPdS_iidd
.type _Z34__device_stub__Z9LaplacianPdS_iiddPdS_iidd, @function
_Z34__device_stub__Z9LaplacianPdS_iiddPdS_iidd:
.LFB3705:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movsd %xmm0, 16(%rsp)
movsd %xmm1, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L102
.L98:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L103
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L102:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9LaplacianPdS_iidd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L98
.L103:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3705:
.size _Z34__device_stub__Z9LaplacianPdS_iiddPdS_iidd, .-_Z34__device_stub__Z9LaplacianPdS_iiddPdS_iidd
.globl _Z9LaplacianPdS_iidd
.type _Z9LaplacianPdS_iidd, @function
_Z9LaplacianPdS_iidd:
.LFB3706:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z9LaplacianPdS_iiddPdS_iidd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3706:
.size _Z9LaplacianPdS_iidd, .-_Z9LaplacianPdS_iidd
.globl _Z35__device_stub__Z8gradientPdS_S_iiddPdS_S_iidd
.type _Z35__device_stub__Z8gradientPdS_S_iiddPdS_S_iidd, @function
_Z35__device_stub__Z8gradientPdS_S_iiddPdS_S_iidd:
.LFB3707:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movsd %xmm0, 8(%rsp)
movsd %xmm1, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L110
.L106:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L111
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L110:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z8gradientPdS_S_iidd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L106
.L111:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3707:
.size _Z35__device_stub__Z8gradientPdS_S_iiddPdS_S_iidd, .-_Z35__device_stub__Z8gradientPdS_S_iiddPdS_S_iidd
.globl _Z8gradientPdS_S_iidd
.type _Z8gradientPdS_S_iidd, @function
_Z8gradientPdS_S_iidd:
.LFB3708:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z8gradientPdS_S_iiddPdS_S_iidd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3708:
.size _Z8gradientPdS_S_iidd, .-_Z8gradientPdS_S_iidd
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z8gradientPdS_S_iidd"
.LC3:
.string "_Z9LaplacianPdS_iidd"
.LC4:
.string "_Z10DivergencePdS_S_iidd"
.LC5:
.string "_Z3DivPdS_S_S_iidd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3710:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z8gradientPdS_S_iidd(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z9LaplacianPdS_iidd(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z10DivergencePdS_S_iidd(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z3DivPdS_S_S_iidd(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3710:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1071644672
.align 8
.LC1:
.long 0
.long 1070596096
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <math.h>
#include <cuda.h>
using namespace std;
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
// Divergence of a Vector with variable coefficient !
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
void DivCPU(double* Dn, double* Phi, double* U, double* V, int row, int col,double delX,double delY){
for(int i = 1; i<(row-1); ++i){
for(int j =1; j<(col-1); ++j){
int k = i*col+j;
double PhiP = Phi[k];
double PhiE = Phi[k+1];
double PhiW = Phi[k-1];
double PhiN = Phi[k-col];
double PhiS = Phi[k+col];
double UP = U[k];
double UE = U[k+1];
double UW = U[k-1];
//double UN = U[k-col];
//double US = U[k+col];
double VP = V[k];
//double VE = V[k+1];
//double VW = V[k-1];
double VN = V[k-col];
double VS = V[k+col];
double Ee = 0.5*(UE*PhiE+UP*PhiP);
double Ew = 0.5*(UW*PhiW+UP*PhiP);
double Fn = 0.5*(VN*PhiN+VP*PhiP);
double Fs = 0.5*(VS*PhiS+VP*PhiP);
Dn[k] = delX*(Fn-Fs)+delY*(Ee-Ew);
}
}
}
__global__ void Div(double* Dn, double* Phi, double* U, double* V, int row, int col,double delX,double delY){
// Get global thread ID
int k = blockIdx.x*blockDim.x+threadIdx.x;
int n = (row-1)*(col-1);
// Do for only inner points
if (k >0 && k<n) {
double PhiP = Phi[k];
double PhiE = Phi[k+1];
double PhiW = Phi[k-1];
double PhiN = Phi[k-col];
double PhiS = Phi[k+col];
double UP = U[k];
double UE = U[k+1];
double UW = U[k-1];
//double UN = U[k-col];
//double US = U[k+col];
double VP = V[k];
//double VE = V[k+1];
//double VW = V[k-1];
double VN = V[k-col];
double VS = V[k+col];
double Ee = 0.5*(UE*PhiE+UP*PhiP);
double Ew = 0.5*(UW*PhiW+UP*PhiP);
double Fn = 0.5*(VN*PhiN+VP*PhiP);
double Fs = 0.5*(VS*PhiS+VP*PhiP);
Dn[k] = delX*(Fn-Fs)+delY*(Ee-Ew);
}
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
// Divergence of a Vector with No coefficient !
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
__global__ void Divergence(double* Dn, double* U, double* V,int row, int col, double delX, double delY){
// Get global thread ID
int k = blockIdx.x*blockDim.x+threadIdx.x;
int n = (row-1)*(col-1);
// Do for only inner points
if (k >0 && k<n) {
double UP = U[k];
double UE = U[k+1];
double UW = U[k-1];
//double UN = U[k-col];
//double US = U[k+col];
double VP = V[k];
// double VE = V[k+1];
//double VW = V[k-1];
double VN = V[k-col];
double VS = V[k+col];
double Ue = 0.5*(UE+UP);
double Uw = 0.5*(UW+UP);
//double Un = 0.5*(UN+UP);
//double Us = 0.5*(US+UP);
// double Ve = 0.5*(VE+VP);
// double Vw = 0.5*(VW+VP);
double Vn = 0.5*(VN+VP);
double Vs = 0.5*(VS+VP);
Dn[k] = (Ue-Uw)*delY+(Vn-Vs)*delX;
}
}
void DivergenceCPU(double* Dn, double* U, double* V,int row, int col, double delX, double delY){
for(int i = 1; i<(row-1); ++i){
for(int j =1; j<(col-1); ++j){
int k = i*col+j;
double UP = U[k];
double UE = U[k+1];
double UW = U[k-1];
//double UN = U[k-col];
//double US = U[k+col];
double VP = V[k];
// double VE = V[k+1];
// double VW = V[k-1];
double VN = V[k-col];
double VS = V[k+col];
double Ue = 0.5*(UE+UP);
double Uw = 0.5*(UW+UP);
//double Un = 0.5*(UN+UP);
//double Us = 0.5*(US+UP);
// double Ve = 0.5*(VE+VP);
//double Vw = 0.5*(VW+VP);
double Vn = 0.5*(VN+VP);
double Vs = 0.5*(VS+VP);
Dn[k] = (Ue-Uw)*delY+(Vn-Vs)*delX;
}
}
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
// Laplacian of a Scalar !
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
void LaplacianCPU(double* Ln, double *Phi, int row, int col, double delX, double delY){
for(int i = 1; i<(row-1); i++){
for(int j =1; j<(col-1); j++){
int k = i*col+j;
double PhiP = Phi[k];
double PhiE = Phi[k+1];
double PhiW = Phi[k-1];
double PhiN = Phi[k-col];
double PhiS = Phi[k+col];
double Ee = (PhiE-PhiP)/delX;
double Ew = (PhiP-PhiW)/delX;
double Fn = (PhiN-PhiP)/delY;
double Fs = (PhiP-PhiS)/delY;
Ln[k] = delX*(Fn-Fs)+delY*(Ee-Ew);
}
}
}
__global__ void Laplacian(double* Ln, double *Phi, int row, int col, double delX, double delY){
// Get global thread ID
int k = blockIdx.x*blockDim.x+threadIdx.x;
int n = (row-1)*(col-1);
// Do for only inner points
if (k >0 && k<n) {
double PhiP = Phi[k];
double PhiE = Phi[k+1];
double PhiW = Phi[k-1];
double PhiN = Phi[k-col];
double PhiS = Phi[k+col];
double Ee = (PhiE-PhiP)/delX;
double Ew = (PhiP-PhiW)/delX;
double Fn = (PhiN-PhiP)/delY;
double Fs = (PhiP-PhiS)/delY;
Ln[k] = delX*(Fn-Fs)+delY*(Ee-Ew);
}
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
// Gradient Computation using Finite Volume !
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
void gradient(double* gradxPhi,double* gradyPhi,
double* vfacePhi,double* hfacePhi,
int cellRow, int cellCol, double delX, double delY,
int vfaceCol, int hfaceCol){
for(int i = 1; i<(cellRow-1); ++i){
for(int j =1; j<(cellCol-1); ++j){
double Phie = vfacePhi[i*vfaceCol+(j+1)];
double Phiw = vfacePhi[i*vfaceCol+j];
double Phin = hfacePhi[i*hfaceCol+j];
double Phis = hfacePhi[(i+1)*hfaceCol+j];
gradxPhi[i*cellCol+j] = (Phie-Phiw)/delX;
gradyPhi[i*cellCol+j] = (Phin-Phis)/delY;
}
}
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
// Gradient Computation using Finite Difference !
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
__global__ void gradient(double* gradxPhi,double* gradyPhi,double* Phi,
int row, int col, double delX, double delY){
// Get global thread ID
int k = blockIdx.x*blockDim.x+threadIdx.x;
int n = (row-1)*(col-1);
// Do for only inner points
if (k >0 && k<n) {
double Phie = Phi[k+1];
double Phiw = Phi[k-1];
double Phin = Phi[k-col];
double Phis = Phi[k+col];
gradxPhi[k] = (Phie-Phiw)/(2*delX);
gradyPhi[k] = (Phin-Phis)/(2*delY);
}
}
void gradientCPU(double* gradxPhi,double* gradyPhi,double* Phi,
int row, int col, double delX, double delY){
for(int i = 1; i<(row-1); ++i){
for(int j =1; j<(col-1); ++j){
int k = i*col+j;
double Phie = Phi[k+1];
double Phiw = Phi[k-1];
double Phin = Phi[k-col];
double Phis = Phi[k+col];
gradxPhi[k] = (Phie-Phiw)/(2*delX);
gradyPhi[k] = (Phin-Phis)/(2*delY);
}
}
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
// Interpolation of Vertex Values !
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
void vertexInterpolate(double* vertPhi, double* cellPhi, int vertRow, int vertCol, int cellCol){
// Inner Points
for(int i = 1; i<(vertRow-1); ++i){
for(int j =1; j<(vertCol-1); ++j){
double Ta = cellPhi[(i-1)*cellCol+(j-1)]; // NW
double Tb = cellPhi[(i-1)*cellCol+j]; // NE
double Tc = cellPhi[(i*cellCol)+(j-1)]; // SW
double Td = cellPhi[i*cellCol+j]; //SE
vertPhi[i*vertCol+j]=0.25*(Ta+Tb+Tc+Td);
}
}
//Boundary points - Set it to Boundary Cell points
//North Boundary
for (int i = 0; i<vertCol; i++){
vertPhi[i]= cellPhi[i+vertCol];
}
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
// Interpolation of Vertical FaceCenter Interpolation !
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
void vfaceInterpolate(double* vfacePhi, double* vertPhi,
double* cellPhi, int vfaceRow, int vfaceCol,
int vertCol, int cellCol){
for(int i = 1; i<(vfaceRow-1); ++i){
for(int j =1; j<(vfaceCol-1); ++j){
double Ta = cellPhi[i*cellCol+(j-1)]; // West cell
double Tb = cellPhi[i*cellCol+j]; // East cell
double Tc = vertPhi[i*vertCol+j]; // North Vertex
double Td = vertPhi[(i+1)*vertCol+j]; //South Vertex
vfacePhi[i*vfaceCol+j]=0.25*(Ta+Tb+Tc+Td);
}
}
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
// Interpolation of Horizontal FaceCenter Interpolation !
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
void hfaceInterpolate(double* hfacePhi, double* vertPhi,
double* cellPhi, int hfaceRow, int hfaceCol,
int vertCol, int cellCol){
for(int i = 1; i<(hfaceRow-1); ++i){
for(int j =1; j<(hfaceCol-1); ++j){
double Ta = vertPhi[i*vertCol+j]; // West vertex
double Tb = vertPhi[i*vertCol+(j+1)]; // East vertex
double Tc = cellPhi[(i-1)*cellCol+j]; // North cell
double Td = cellPhi[i*cellCol+j]; //South cell
hfacePhi[i*hfaceCol+j]=0.25*(Ta+Tb+Tc+Td);
}
}
} | #include <iostream>
#include <math.h>
#include <hip/hip_runtime.h>
using namespace std;
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
// Divergence of a Vector with variable coefficient !
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
void DivCPU(double* Dn, double* Phi, double* U, double* V, int row, int col,double delX,double delY){
for(int i = 1; i<(row-1); ++i){
for(int j =1; j<(col-1); ++j){
int k = i*col+j;
double PhiP = Phi[k];
double PhiE = Phi[k+1];
double PhiW = Phi[k-1];
double PhiN = Phi[k-col];
double PhiS = Phi[k+col];
double UP = U[k];
double UE = U[k+1];
double UW = U[k-1];
//double UN = U[k-col];
//double US = U[k+col];
double VP = V[k];
//double VE = V[k+1];
//double VW = V[k-1];
double VN = V[k-col];
double VS = V[k+col];
double Ee = 0.5*(UE*PhiE+UP*PhiP);
double Ew = 0.5*(UW*PhiW+UP*PhiP);
double Fn = 0.5*(VN*PhiN+VP*PhiP);
double Fs = 0.5*(VS*PhiS+VP*PhiP);
Dn[k] = delX*(Fn-Fs)+delY*(Ee-Ew);
}
}
}
__global__ void Div(double* Dn, double* Phi, double* U, double* V, int row, int col,double delX,double delY){
// Get global thread ID
int k = blockIdx.x*blockDim.x+threadIdx.x;
int n = (row-1)*(col-1);
// Do for only inner points
if (k >0 && k<n) {
double PhiP = Phi[k];
double PhiE = Phi[k+1];
double PhiW = Phi[k-1];
double PhiN = Phi[k-col];
double PhiS = Phi[k+col];
double UP = U[k];
double UE = U[k+1];
double UW = U[k-1];
//double UN = U[k-col];
//double US = U[k+col];
double VP = V[k];
//double VE = V[k+1];
//double VW = V[k-1];
double VN = V[k-col];
double VS = V[k+col];
double Ee = 0.5*(UE*PhiE+UP*PhiP);
double Ew = 0.5*(UW*PhiW+UP*PhiP);
double Fn = 0.5*(VN*PhiN+VP*PhiP);
double Fs = 0.5*(VS*PhiS+VP*PhiP);
Dn[k] = delX*(Fn-Fs)+delY*(Ee-Ew);
}
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
// Divergence of a Vector with No coefficient !
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
__global__ void Divergence(double* Dn, double* U, double* V,int row, int col, double delX, double delY){
// Get global thread ID
int k = blockIdx.x*blockDim.x+threadIdx.x;
int n = (row-1)*(col-1);
// Do for only inner points
if (k >0 && k<n) {
double UP = U[k];
double UE = U[k+1];
double UW = U[k-1];
//double UN = U[k-col];
//double US = U[k+col];
double VP = V[k];
// double VE = V[k+1];
//double VW = V[k-1];
double VN = V[k-col];
double VS = V[k+col];
double Ue = 0.5*(UE+UP);
double Uw = 0.5*(UW+UP);
//double Un = 0.5*(UN+UP);
//double Us = 0.5*(US+UP);
// double Ve = 0.5*(VE+VP);
// double Vw = 0.5*(VW+VP);
double Vn = 0.5*(VN+VP);
double Vs = 0.5*(VS+VP);
Dn[k] = (Ue-Uw)*delY+(Vn-Vs)*delX;
}
}
void DivergenceCPU(double* Dn, double* U, double* V,int row, int col, double delX, double delY){
for(int i = 1; i<(row-1); ++i){
for(int j =1; j<(col-1); ++j){
int k = i*col+j;
double UP = U[k];
double UE = U[k+1];
double UW = U[k-1];
//double UN = U[k-col];
//double US = U[k+col];
double VP = V[k];
// double VE = V[k+1];
// double VW = V[k-1];
double VN = V[k-col];
double VS = V[k+col];
double Ue = 0.5*(UE+UP);
double Uw = 0.5*(UW+UP);
//double Un = 0.5*(UN+UP);
//double Us = 0.5*(US+UP);
// double Ve = 0.5*(VE+VP);
//double Vw = 0.5*(VW+VP);
double Vn = 0.5*(VN+VP);
double Vs = 0.5*(VS+VP);
Dn[k] = (Ue-Uw)*delY+(Vn-Vs)*delX;
}
}
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
// Laplacian of a Scalar !
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
void LaplacianCPU(double* Ln, double *Phi, int row, int col, double delX, double delY){
for(int i = 1; i<(row-1); i++){
for(int j =1; j<(col-1); j++){
int k = i*col+j;
double PhiP = Phi[k];
double PhiE = Phi[k+1];
double PhiW = Phi[k-1];
double PhiN = Phi[k-col];
double PhiS = Phi[k+col];
double Ee = (PhiE-PhiP)/delX;
double Ew = (PhiP-PhiW)/delX;
double Fn = (PhiN-PhiP)/delY;
double Fs = (PhiP-PhiS)/delY;
Ln[k] = delX*(Fn-Fs)+delY*(Ee-Ew);
}
}
}
__global__ void Laplacian(double* Ln, double *Phi, int row, int col, double delX, double delY){
// Get global thread ID
int k = blockIdx.x*blockDim.x+threadIdx.x;
int n = (row-1)*(col-1);
// Do for only inner points
if (k >0 && k<n) {
double PhiP = Phi[k];
double PhiE = Phi[k+1];
double PhiW = Phi[k-1];
double PhiN = Phi[k-col];
double PhiS = Phi[k+col];
double Ee = (PhiE-PhiP)/delX;
double Ew = (PhiP-PhiW)/delX;
double Fn = (PhiN-PhiP)/delY;
double Fs = (PhiP-PhiS)/delY;
Ln[k] = delX*(Fn-Fs)+delY*(Ee-Ew);
}
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
// Gradient Computation using Finite Volume !
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
void gradient(double* gradxPhi,double* gradyPhi,
double* vfacePhi,double* hfacePhi,
int cellRow, int cellCol, double delX, double delY,
int vfaceCol, int hfaceCol){
for(int i = 1; i<(cellRow-1); ++i){
for(int j =1; j<(cellCol-1); ++j){
double Phie = vfacePhi[i*vfaceCol+(j+1)];
double Phiw = vfacePhi[i*vfaceCol+j];
double Phin = hfacePhi[i*hfaceCol+j];
double Phis = hfacePhi[(i+1)*hfaceCol+j];
gradxPhi[i*cellCol+j] = (Phie-Phiw)/delX;
gradyPhi[i*cellCol+j] = (Phin-Phis)/delY;
}
}
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
// Gradient Computation using Finite Difference !
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
__global__ void gradient(double* gradxPhi,double* gradyPhi,double* Phi,
int row, int col, double delX, double delY){
// Get global thread ID
int k = blockIdx.x*blockDim.x+threadIdx.x;
int n = (row-1)*(col-1);
// Do for only inner points
if (k >0 && k<n) {
double Phie = Phi[k+1];
double Phiw = Phi[k-1];
double Phin = Phi[k-col];
double Phis = Phi[k+col];
gradxPhi[k] = (Phie-Phiw)/(2*delX);
gradyPhi[k] = (Phin-Phis)/(2*delY);
}
}
void gradientCPU(double* gradxPhi,double* gradyPhi,double* Phi,
int row, int col, double delX, double delY){
for(int i = 1; i<(row-1); ++i){
for(int j =1; j<(col-1); ++j){
int k = i*col+j;
double Phie = Phi[k+1];
double Phiw = Phi[k-1];
double Phin = Phi[k-col];
double Phis = Phi[k+col];
gradxPhi[k] = (Phie-Phiw)/(2*delX);
gradyPhi[k] = (Phin-Phis)/(2*delY);
}
}
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
// Interpolation of Vertex Values !
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
void vertexInterpolate(double* vertPhi, double* cellPhi, int vertRow, int vertCol, int cellCol){
// Inner Points
for(int i = 1; i<(vertRow-1); ++i){
for(int j =1; j<(vertCol-1); ++j){
double Ta = cellPhi[(i-1)*cellCol+(j-1)]; // NW
double Tb = cellPhi[(i-1)*cellCol+j]; // NE
double Tc = cellPhi[(i*cellCol)+(j-1)]; // SW
double Td = cellPhi[i*cellCol+j]; //SE
vertPhi[i*vertCol+j]=0.25*(Ta+Tb+Tc+Td);
}
}
//Boundary points - Set it to Boundary Cell points
//North Boundary
for (int i = 0; i<vertCol; i++){
vertPhi[i]= cellPhi[i+vertCol];
}
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
// Interpolation of Vertical FaceCenter Interpolation !
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
void vfaceInterpolate(double* vfacePhi, double* vertPhi,
double* cellPhi, int vfaceRow, int vfaceCol,
int vertCol, int cellCol){
for(int i = 1; i<(vfaceRow-1); ++i){
for(int j =1; j<(vfaceCol-1); ++j){
double Ta = cellPhi[i*cellCol+(j-1)]; // West cell
double Tb = cellPhi[i*cellCol+j]; // East cell
double Tc = vertPhi[i*vertCol+j]; // North Vertex
double Td = vertPhi[(i+1)*vertCol+j]; //South Vertex
vfacePhi[i*vfaceCol+j]=0.25*(Ta+Tb+Tc+Td);
}
}
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
// Interpolation of Horizontal FaceCenter Interpolation !
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
void hfaceInterpolate(double* hfacePhi, double* vertPhi,
double* cellPhi, int hfaceRow, int hfaceCol,
int vertCol, int cellCol){
for(int i = 1; i<(hfaceRow-1); ++i){
for(int j =1; j<(hfaceCol-1); ++j){
double Ta = vertPhi[i*vertCol+j]; // West vertex
double Tb = vertPhi[i*vertCol+(j+1)]; // East vertex
double Tc = cellPhi[(i-1)*cellCol+j]; // North cell
double Td = cellPhi[i*cellCol+j]; //South cell
hfacePhi[i*hfaceCol+j]=0.25*(Ta+Tb+Tc+Td);
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <iostream>
#include <math.h>
#include <hip/hip_runtime.h>
using namespace std;
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
// Divergence of a Vector with variable coefficient !
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
void DivCPU(double* Dn, double* Phi, double* U, double* V, int row, int col,double delX,double delY){
for(int i = 1; i<(row-1); ++i){
for(int j =1; j<(col-1); ++j){
int k = i*col+j;
double PhiP = Phi[k];
double PhiE = Phi[k+1];
double PhiW = Phi[k-1];
double PhiN = Phi[k-col];
double PhiS = Phi[k+col];
double UP = U[k];
double UE = U[k+1];
double UW = U[k-1];
//double UN = U[k-col];
//double US = U[k+col];
double VP = V[k];
//double VE = V[k+1];
//double VW = V[k-1];
double VN = V[k-col];
double VS = V[k+col];
double Ee = 0.5*(UE*PhiE+UP*PhiP);
double Ew = 0.5*(UW*PhiW+UP*PhiP);
double Fn = 0.5*(VN*PhiN+VP*PhiP);
double Fs = 0.5*(VS*PhiS+VP*PhiP);
Dn[k] = delX*(Fn-Fs)+delY*(Ee-Ew);
}
}
}
__global__ void Div(double* Dn, double* Phi, double* U, double* V, int row, int col,double delX,double delY){
// Get global thread ID
int k = blockIdx.x*blockDim.x+threadIdx.x;
int n = (row-1)*(col-1);
// Do for only inner points
if (k >0 && k<n) {
double PhiP = Phi[k];
double PhiE = Phi[k+1];
double PhiW = Phi[k-1];
double PhiN = Phi[k-col];
double PhiS = Phi[k+col];
double UP = U[k];
double UE = U[k+1];
double UW = U[k-1];
//double UN = U[k-col];
//double US = U[k+col];
double VP = V[k];
//double VE = V[k+1];
//double VW = V[k-1];
double VN = V[k-col];
double VS = V[k+col];
double Ee = 0.5*(UE*PhiE+UP*PhiP);
double Ew = 0.5*(UW*PhiW+UP*PhiP);
double Fn = 0.5*(VN*PhiN+VP*PhiP);
double Fs = 0.5*(VS*PhiS+VP*PhiP);
Dn[k] = delX*(Fn-Fs)+delY*(Ee-Ew);
}
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
// Divergence of a Vector with No coefficient !
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
__global__ void Divergence(double* Dn, double* U, double* V,int row, int col, double delX, double delY){
// Get global thread ID
int k = blockIdx.x*blockDim.x+threadIdx.x;
int n = (row-1)*(col-1);
// Do for only inner points
if (k >0 && k<n) {
double UP = U[k];
double UE = U[k+1];
double UW = U[k-1];
//double UN = U[k-col];
//double US = U[k+col];
double VP = V[k];
// double VE = V[k+1];
//double VW = V[k-1];
double VN = V[k-col];
double VS = V[k+col];
double Ue = 0.5*(UE+UP);
double Uw = 0.5*(UW+UP);
//double Un = 0.5*(UN+UP);
//double Us = 0.5*(US+UP);
// double Ve = 0.5*(VE+VP);
// double Vw = 0.5*(VW+VP);
double Vn = 0.5*(VN+VP);
double Vs = 0.5*(VS+VP);
Dn[k] = (Ue-Uw)*delY+(Vn-Vs)*delX;
}
}
void DivergenceCPU(double* Dn, double* U, double* V,int row, int col, double delX, double delY){
for(int i = 1; i<(row-1); ++i){
for(int j =1; j<(col-1); ++j){
int k = i*col+j;
double UP = U[k];
double UE = U[k+1];
double UW = U[k-1];
//double UN = U[k-col];
//double US = U[k+col];
double VP = V[k];
// double VE = V[k+1];
// double VW = V[k-1];
double VN = V[k-col];
double VS = V[k+col];
double Ue = 0.5*(UE+UP);
double Uw = 0.5*(UW+UP);
//double Un = 0.5*(UN+UP);
//double Us = 0.5*(US+UP);
// double Ve = 0.5*(VE+VP);
//double Vw = 0.5*(VW+VP);
double Vn = 0.5*(VN+VP);
double Vs = 0.5*(VS+VP);
Dn[k] = (Ue-Uw)*delY+(Vn-Vs)*delX;
}
}
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
// Laplacian of a Scalar !
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
void LaplacianCPU(double* Ln, double *Phi, int row, int col, double delX, double delY){
for(int i = 1; i<(row-1); i++){
for(int j =1; j<(col-1); j++){
int k = i*col+j;
double PhiP = Phi[k];
double PhiE = Phi[k+1];
double PhiW = Phi[k-1];
double PhiN = Phi[k-col];
double PhiS = Phi[k+col];
double Ee = (PhiE-PhiP)/delX;
double Ew = (PhiP-PhiW)/delX;
double Fn = (PhiN-PhiP)/delY;
double Fs = (PhiP-PhiS)/delY;
Ln[k] = delX*(Fn-Fs)+delY*(Ee-Ew);
}
}
}
__global__ void Laplacian(double* Ln, double *Phi, int row, int col, double delX, double delY){
// Get global thread ID
int k = blockIdx.x*blockDim.x+threadIdx.x;
int n = (row-1)*(col-1);
// Do for only inner points
if (k >0 && k<n) {
double PhiP = Phi[k];
double PhiE = Phi[k+1];
double PhiW = Phi[k-1];
double PhiN = Phi[k-col];
double PhiS = Phi[k+col];
double Ee = (PhiE-PhiP)/delX;
double Ew = (PhiP-PhiW)/delX;
double Fn = (PhiN-PhiP)/delY;
double Fs = (PhiP-PhiS)/delY;
Ln[k] = delX*(Fn-Fs)+delY*(Ee-Ew);
}
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
// Gradient Computation using Finite Volume !
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
void gradient(double* gradxPhi,double* gradyPhi,
double* vfacePhi,double* hfacePhi,
int cellRow, int cellCol, double delX, double delY,
int vfaceCol, int hfaceCol){
for(int i = 1; i<(cellRow-1); ++i){
for(int j =1; j<(cellCol-1); ++j){
double Phie = vfacePhi[i*vfaceCol+(j+1)];
double Phiw = vfacePhi[i*vfaceCol+j];
double Phin = hfacePhi[i*hfaceCol+j];
double Phis = hfacePhi[(i+1)*hfaceCol+j];
gradxPhi[i*cellCol+j] = (Phie-Phiw)/delX;
gradyPhi[i*cellCol+j] = (Phin-Phis)/delY;
}
}
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
// Gradient Computation using Finite Difference !
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
__global__ void gradient(double* gradxPhi,double* gradyPhi,double* Phi,
int row, int col, double delX, double delY){
// Get global thread ID
int k = blockIdx.x*blockDim.x+threadIdx.x;
int n = (row-1)*(col-1);
// Do for only inner points
if (k >0 && k<n) {
double Phie = Phi[k+1];
double Phiw = Phi[k-1];
double Phin = Phi[k-col];
double Phis = Phi[k+col];
gradxPhi[k] = (Phie-Phiw)/(2*delX);
gradyPhi[k] = (Phin-Phis)/(2*delY);
}
}
void gradientCPU(double* gradxPhi,double* gradyPhi,double* Phi,
int row, int col, double delX, double delY){
for(int i = 1; i<(row-1); ++i){
for(int j =1; j<(col-1); ++j){
int k = i*col+j;
double Phie = Phi[k+1];
double Phiw = Phi[k-1];
double Phin = Phi[k-col];
double Phis = Phi[k+col];
gradxPhi[k] = (Phie-Phiw)/(2*delX);
gradyPhi[k] = (Phin-Phis)/(2*delY);
}
}
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
// Interpolation of Vertex Values !
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
void vertexInterpolate(double* vertPhi, double* cellPhi, int vertRow, int vertCol, int cellCol){
// Inner Points
for(int i = 1; i<(vertRow-1); ++i){
for(int j =1; j<(vertCol-1); ++j){
double Ta = cellPhi[(i-1)*cellCol+(j-1)]; // NW
double Tb = cellPhi[(i-1)*cellCol+j]; // NE
double Tc = cellPhi[(i*cellCol)+(j-1)]; // SW
double Td = cellPhi[i*cellCol+j]; //SE
vertPhi[i*vertCol+j]=0.25*(Ta+Tb+Tc+Td);
}
}
//Boundary points - Set it to Boundary Cell points
//North Boundary
for (int i = 0; i<vertCol; i++){
vertPhi[i]= cellPhi[i+vertCol];
}
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
// Interpolation of Vertical FaceCenter Interpolation !
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
void vfaceInterpolate(double* vfacePhi, double* vertPhi,
double* cellPhi, int vfaceRow, int vfaceCol,
int vertCol, int cellCol){
for(int i = 1; i<(vfaceRow-1); ++i){
for(int j =1; j<(vfaceCol-1); ++j){
double Ta = cellPhi[i*cellCol+(j-1)]; // West cell
double Tb = cellPhi[i*cellCol+j]; // East cell
double Tc = vertPhi[i*vertCol+j]; // North Vertex
double Td = vertPhi[(i+1)*vertCol+j]; //South Vertex
vfacePhi[i*vfaceCol+j]=0.25*(Ta+Tb+Tc+Td);
}
}
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
// Interpolation of Horizontal FaceCenter Interpolation !
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
void hfaceInterpolate(double* hfacePhi, double* vertPhi,
double* cellPhi, int hfaceRow, int hfaceCol,
int vertCol, int cellCol){
for(int i = 1; i<(hfaceRow-1); ++i){
for(int j =1; j<(hfaceCol-1); ++j){
double Ta = vertPhi[i*vertCol+j]; // West vertex
double Tb = vertPhi[i*vertCol+(j+1)]; // East vertex
double Tc = cellPhi[(i-1)*cellCol+j]; // North cell
double Td = cellPhi[i*cellCol+j]; //South cell
hfacePhi[i*hfaceCol+j]=0.25*(Ta+Tb+Tc+Td);
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3DivPdS_S_S_iidd
.globl _Z3DivPdS_S_S_iidd
.p2align 8
.type _Z3DivPdS_S_S_iidd,@function
_Z3DivPdS_S_S_iidd:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x44
s_load_b64 s[2:3], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_add_i32 s2, s2, -1
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_add_i32 s4, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s4, s4, s2
v_cmp_lt_i32_e32 vcc_lo, 0, v1
v_cmp_gt_i32_e64 s2, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_2
s_load_b256 s[4:11], s[0:1], 0x0
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v9, s3, v1
v_subrev_nc_u32_e32 v15, s3, v1
v_add_nc_u32_e32 v17, -1, v1
s_load_b128 s[0:3], s[0:1], 0x28
s_delay_alu instid0(VALU_DEP_3)
v_mov_b32_e32 v18, v2
v_lshlrev_b64 v[3:4], 3, v[1:2]
v_ashrrev_i32_e32 v10, 31, v9
v_ashrrev_i32_e32 v16, 31, v15
v_add_nc_u32_e32 v1, 1, v1
v_lshlrev_b64 v[17:18], 3, v[17:18]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[9:10], 3, v[9:10]
v_lshlrev_b64 v[15:16], 3, v[15:16]
s_delay_alu instid0(VALU_DEP_4)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s10, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s11, v4, vcc_lo
v_add_co_u32 v11, vcc_lo, s6, v9
global_load_b64 v[5:6], v[5:6], off
global_load_b64 v[7:8], v[7:8], off
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v10, vcc_lo
v_add_co_u32 v9, vcc_lo, s10, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s11, v10, vcc_lo
v_add_co_u32 v13, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v14, vcc_lo, s9, v4, vcc_lo
global_load_b64 v[11:12], v[11:12], off
global_load_b64 v[9:10], v[9:10], off
global_load_b64 v[13:14], v[13:14], off
v_add_co_u32 v19, vcc_lo, s10, v15
v_add_co_ci_u32_e32 v20, vcc_lo, s11, v16, vcc_lo
v_add_co_u32 v21, vcc_lo, s6, v17
v_add_co_ci_u32_e32 v22, vcc_lo, s7, v18, vcc_lo
v_add_co_u32 v15, vcc_lo, s6, v15
v_add_co_ci_u32_e32 v16, vcc_lo, s7, v16, vcc_lo
v_add_co_u32 v17, vcc_lo, s8, v17
v_add_co_ci_u32_e32 v18, vcc_lo, s9, v18, vcc_lo
global_load_b64 v[19:20], v[19:20], off
s_clause 0x1
global_load_b64 v[15:16], v[15:16], off
global_load_b64 v[21:22], v[21:22], off
global_load_b64 v[17:18], v[17:18], off
v_add_co_u32 v23, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v24, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
global_load_b64 v[23:24], v[23:24], off
global_load_b64 v[0:1], v[0:1], off
v_add_co_u32 v2, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v4, vcc_lo
s_waitcnt vmcnt(9)
v_mul_f64 v[7:8], v[5:6], v[7:8]
s_waitcnt vmcnt(6)
v_mul_f64 v[5:6], v[5:6], v[13:14]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_fma_f64 v[9:10], v[11:12], v[9:10], v[7:8]
s_waitcnt vmcnt(4)
v_fma_f64 v[7:8], v[15:16], v[19:20], v[7:8]
s_waitcnt vmcnt(2)
v_fma_f64 v[11:12], v[21:22], v[17:18], v[5:6]
s_waitcnt vmcnt(0)
v_fma_f64 v[0:1], v[23:24], v[0:1], v[5:6]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[9:10], v[9:10], 0.5
v_fma_f64 v[5:6], v[7:8], 0.5, -v[9:10]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[7:8], v[11:12], 0.5
v_mul_f64 v[5:6], v[5:6], s[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[0:1], v[0:1], 0.5, -v[7:8]
v_fma_f64 v[0:1], v[0:1], s[2:3], v[5:6]
global_store_b64 v[2:3], v[0:1], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3DivPdS_S_S_iidd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 25
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3DivPdS_S_S_iidd, .Lfunc_end0-_Z3DivPdS_S_S_iidd
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10DivergencePdS_S_iidd
.globl _Z10DivergencePdS_S_iidd
.p2align 8
.type _Z10DivergencePdS_S_iidd,@function
_Z10DivergencePdS_S_iidd:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_add_i32 s2, s2, -1
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_add_i32 s4, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s4, s4, s2
v_cmp_lt_i32_e32 vcc_lo, 0, v1
v_cmp_gt_i32_e64 s2, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB1_2
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v3, s3, v1
v_subrev_nc_u32_e32 v0, s3, v1
s_load_b128 s[0:3], s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[5:6], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[2:3], 3, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s8, v5
v_add_co_ci_u32_e32 v8, vcc_lo, s9, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
v_add_co_u32 v11, vcc_lo, s6, v5
s_clause 0x1
global_load_b64 v[7:8], v[7:8], off
global_load_b64 v[9:10], v[2:3], off
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v6, vcc_lo
v_add_co_u32 v13, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v14, vcc_lo, s9, v1, vcc_lo
s_clause 0x1
global_load_b128 v[0:3], v[11:12], off
global_load_b64 v[11:12], v[11:12], off offset:-8
global_load_b64 v[13:14], v[13:14], off
s_waitcnt vmcnt(3)
v_add_f64 v[9:10], v[7:8], v[9:10]
s_waitcnt vmcnt(1)
v_add_f64 v[11:12], v[0:1], v[11:12]
s_waitcnt vmcnt(0)
v_add_f64 v[7:8], v[7:8], v[13:14]
v_add_f64 v[0:1], v[0:1], v[2:3]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_f64 v[9:10], v[9:10], 0.5
v_mul_f64 v[2:3], v[11:12], 0.5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[7:8], v[7:8], 0.5, -v[9:10]
v_fma_f64 v[0:1], v[0:1], 0.5, -v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[2:3], v[7:8], s[0:1]
v_fma_f64 v[0:1], v[0:1], s[2:3], v[2:3]
v_add_co_u32 v2, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v6, vcc_lo
global_store_b64 v[2:3], v[0:1], off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10DivergencePdS_S_iidd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10DivergencePdS_S_iidd, .Lfunc_end1-_Z10DivergencePdS_S_iidd
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9LaplacianPdS_iidd
.globl _Z9LaplacianPdS_iidd
.p2align 8
.type _Z9LaplacianPdS_iidd,@function
_Z9LaplacianPdS_iidd:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_add_i32 s2, s2, -1
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_add_i32 s4, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s4, s4, s2
v_cmp_lt_i32_e32 vcc_lo, 0, v1
v_cmp_gt_i32_e64 s2, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB2_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b128 s[8:11], s[0:1], 0x18
v_subrev_nc_u32_e32 v3, s3, v1
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v5, s3, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[7:8], 3, v[1:2]
v_lshlrev_b64 v[0:1], 3, v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[4:5], 3, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v8, vcc_lo
v_add_co_u32 v11, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v4
s_clause 0x1
global_load_b128 v[0:3], v[9:10], off
global_load_b64 v[9:10], v[9:10], off offset:-8
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
s_clause 0x1
global_load_b64 v[11:12], v[11:12], off
global_load_b64 v[4:5], v[4:5], off
s_waitcnt vmcnt(3)
v_add_f64 v[2:3], v[2:3], -v[0:1]
s_waitcnt vmcnt(2)
v_add_f64 v[9:10], v[0:1], -v[9:10]
s_waitcnt vmcnt(1)
v_add_f64 v[11:12], v[11:12], -v[0:1]
s_waitcnt vmcnt(0)
v_add_f64 v[0:1], v[0:1], -v[4:5]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_div_scale_f64 v[4:5], null, s[8:9], s[8:9], v[2:3]
v_div_scale_f64 v[13:14], null, s[8:9], s[8:9], v[9:10]
v_div_scale_f64 v[35:36], vcc_lo, v[2:3], s[8:9], v[2:3]
v_div_scale_f64 v[15:16], null, s[10:11], s[10:11], v[11:12]
v_div_scale_f64 v[17:18], null, s[10:11], s[10:11], v[0:1]
v_rcp_f64_e32 v[19:20], v[4:5]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f64_e32 v[21:22], v[13:14]
v_rcp_f64_e32 v[23:24], v[15:16]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(TRANS32_DEP_3)
v_rcp_f64_e32 v[25:26], v[17:18]
v_fma_f64 v[27:28], -v[4:5], v[19:20], 1.0
v_fma_f64 v[29:30], -v[13:14], v[21:22], 1.0
s_waitcnt_depctr 0xfff
v_fma_f64 v[31:32], -v[15:16], v[23:24], 1.0
v_fma_f64 v[33:34], -v[17:18], v[25:26], 1.0
v_fma_f64 v[19:20], v[19:20], v[27:28], v[19:20]
v_fma_f64 v[21:22], v[21:22], v[29:30], v[21:22]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[23:24], v[23:24], v[31:32], v[23:24]
v_fma_f64 v[25:26], v[25:26], v[33:34], v[25:26]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[27:28], -v[4:5], v[19:20], 1.0
v_fma_f64 v[29:30], -v[13:14], v[21:22], 1.0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[31:32], -v[15:16], v[23:24], 1.0
v_fma_f64 v[33:34], -v[17:18], v[25:26], 1.0
s_delay_alu instid0(VALU_DEP_4)
v_fma_f64 v[19:20], v[19:20], v[27:28], v[19:20]
v_div_scale_f64 v[27:28], s0, v[9:10], s[8:9], v[9:10]
v_fma_f64 v[21:22], v[21:22], v[29:30], v[21:22]
v_div_scale_f64 v[29:30], s1, v[11:12], s[10:11], v[11:12]
v_fma_f64 v[23:24], v[23:24], v[31:32], v[23:24]
v_div_scale_f64 v[31:32], s2, v[0:1], s[10:11], v[0:1]
v_fma_f64 v[25:26], v[25:26], v[33:34], v[25:26]
v_mul_f64 v[33:34], v[35:36], v[19:20]
v_mul_f64 v[37:38], v[27:28], v[21:22]
v_mul_f64 v[39:40], v[29:30], v[23:24]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_f64 v[41:42], v[31:32], v[25:26]
v_fma_f64 v[4:5], -v[4:5], v[33:34], v[35:36]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[13:14], -v[13:14], v[37:38], v[27:28]
v_fma_f64 v[15:16], -v[15:16], v[39:40], v[29:30]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[17:18], -v[17:18], v[41:42], v[31:32]
v_div_fmas_f64 v[4:5], v[4:5], v[19:20], v[33:34]
s_mov_b32 vcc_lo, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_div_fmas_f64 v[13:14], v[13:14], v[21:22], v[37:38]
s_mov_b32 vcc_lo, s1
v_div_fmas_f64 v[15:16], v[15:16], v[23:24], v[39:40]
s_mov_b32 vcc_lo, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_div_fmas_f64 v[17:18], v[17:18], v[25:26], v[41:42]
v_div_fixup_f64 v[2:3], v[4:5], s[8:9], v[2:3]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_div_fixup_f64 v[4:5], v[13:14], s[8:9], v[9:10]
v_div_fixup_f64 v[11:12], v[15:16], s[10:11], v[11:12]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fixup_f64 v[0:1], v[17:18], s[10:11], v[0:1]
v_add_f64 v[2:3], v[2:3], -v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[0:1], v[11:12], -v[0:1]
v_mul_f64 v[0:1], v[0:1], s[8:9]
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[0:1], v[2:3], s[10:11], v[0:1]
v_add_co_u32 v2, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v8, vcc_lo
global_store_b64 v[2:3], v[0:1], off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9LaplacianPdS_iidd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 43
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z9LaplacianPdS_iidd, .Lfunc_end2-_Z9LaplacianPdS_iidd
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8gradientPdS_S_iidd
.globl _Z8gradientPdS_S_iidd
.p2align 8
.type _Z8gradientPdS_S_iidd,@function
_Z8gradientPdS_S_iidd:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_add_i32 s2, s2, -1
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_add_i32 s4, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s4, s4, s2
v_cmp_lt_i32_e32 vcc_lo, 0, v1
v_cmp_gt_i32_e64 s2, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB3_2
s_load_b64 s[4:5], s[0:1], 0x10
v_subrev_nc_u32_e32 v3, s3, v1
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v5, s3, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_lshlrev_b64 v[3:4], 3, v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 3, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v6, vcc_lo
v_add_co_u32 v6, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v1, vcc_lo
s_clause 0x3
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
global_load_b64 v[8:9], v[6:7], off offset:8
global_load_b64 v[6:7], v[6:7], off offset:-8
s_load_b128 s[4:7], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
v_add_f64 v[10:11], s[4:5], s[4:5]
s_waitcnt vmcnt(2)
v_add_f64 v[2:3], v[2:3], -v[4:5]
s_waitcnt vmcnt(0)
v_add_f64 v[6:7], v[8:9], -v[6:7]
v_add_f64 v[8:9], s[6:7], s[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_scale_f64 v[4:5], null, v[10:11], v[10:11], v[6:7]
v_div_scale_f64 v[12:13], null, v[8:9], v[8:9], v[2:3]
v_div_scale_f64 v[22:23], vcc_lo, v[6:7], v[10:11], v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f64_e32 v[14:15], v[4:5]
v_rcp_f64_e32 v[16:17], v[12:13]
s_waitcnt_depctr 0xfff
v_fma_f64 v[18:19], -v[4:5], v[14:15], 1.0
v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[18:19], -v[4:5], v[14:15], 1.0
v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
v_div_scale_f64 v[18:19], s2, v[2:3], v[8:9], v[2:3]
v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[20:21], v[22:23], v[14:15]
v_mul_f64 v[24:25], v[18:19], v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[4:5], -v[4:5], v[20:21], v[22:23]
v_fma_f64 v[12:13], -v[12:13], v[24:25], v[18:19]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[4:5], v[4:5], v[14:15], v[20:21]
s_mov_b32 vcc_lo, s2
s_load_b128 s[0:3], s[0:1], 0x0
v_div_fmas_f64 v[12:13], v[12:13], v[16:17], v[24:25]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fixup_f64 v[4:5], v[4:5], v[10:11], v[6:7]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s0, v0
v_div_fixup_f64 v[2:3], v[12:13], v[8:9], v[2:3]
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b64 v[6:7], v[4:5], off
global_store_b64 v[0:1], v[2:3], off
.LBB3_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8gradientPdS_S_iidd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 26
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z8gradientPdS_S_iidd, .Lfunc_end3-_Z8gradientPdS_S_iidd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
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amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <iostream>
#include <math.h>
#include <hip/hip_runtime.h>
using namespace std;
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
// Divergence of a Vector with variable coefficient !
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
void DivCPU(double* Dn, double* Phi, double* U, double* V, int row, int col,double delX,double delY){
for(int i = 1; i<(row-1); ++i){
for(int j =1; j<(col-1); ++j){
int k = i*col+j;
double PhiP = Phi[k];
double PhiE = Phi[k+1];
double PhiW = Phi[k-1];
double PhiN = Phi[k-col];
double PhiS = Phi[k+col];
double UP = U[k];
double UE = U[k+1];
double UW = U[k-1];
//double UN = U[k-col];
//double US = U[k+col];
double VP = V[k];
//double VE = V[k+1];
//double VW = V[k-1];
double VN = V[k-col];
double VS = V[k+col];
double Ee = 0.5*(UE*PhiE+UP*PhiP);
double Ew = 0.5*(UW*PhiW+UP*PhiP);
double Fn = 0.5*(VN*PhiN+VP*PhiP);
double Fs = 0.5*(VS*PhiS+VP*PhiP);
Dn[k] = delX*(Fn-Fs)+delY*(Ee-Ew);
}
}
}
__global__ void Div(double* Dn, double* Phi, double* U, double* V, int row, int col,double delX,double delY){
// Get global thread ID
int k = blockIdx.x*blockDim.x+threadIdx.x;
int n = (row-1)*(col-1);
// Do for only inner points
if (k >0 && k<n) {
double PhiP = Phi[k];
double PhiE = Phi[k+1];
double PhiW = Phi[k-1];
double PhiN = Phi[k-col];
double PhiS = Phi[k+col];
double UP = U[k];
double UE = U[k+1];
double UW = U[k-1];
//double UN = U[k-col];
//double US = U[k+col];
double VP = V[k];
//double VE = V[k+1];
//double VW = V[k-1];
double VN = V[k-col];
double VS = V[k+col];
double Ee = 0.5*(UE*PhiE+UP*PhiP);
double Ew = 0.5*(UW*PhiW+UP*PhiP);
double Fn = 0.5*(VN*PhiN+VP*PhiP);
double Fs = 0.5*(VS*PhiS+VP*PhiP);
Dn[k] = delX*(Fn-Fs)+delY*(Ee-Ew);
}
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
// Divergence of a Vector with No coefficient !
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
__global__ void Divergence(double* Dn, double* U, double* V,int row, int col, double delX, double delY){
// Get global thread ID
int k = blockIdx.x*blockDim.x+threadIdx.x;
int n = (row-1)*(col-1);
// Do for only inner points
if (k >0 && k<n) {
double UP = U[k];
double UE = U[k+1];
double UW = U[k-1];
//double UN = U[k-col];
//double US = U[k+col];
double VP = V[k];
// double VE = V[k+1];
//double VW = V[k-1];
double VN = V[k-col];
double VS = V[k+col];
double Ue = 0.5*(UE+UP);
double Uw = 0.5*(UW+UP);
//double Un = 0.5*(UN+UP);
//double Us = 0.5*(US+UP);
// double Ve = 0.5*(VE+VP);
// double Vw = 0.5*(VW+VP);
double Vn = 0.5*(VN+VP);
double Vs = 0.5*(VS+VP);
Dn[k] = (Ue-Uw)*delY+(Vn-Vs)*delX;
}
}
void DivergenceCPU(double* Dn, double* U, double* V,int row, int col, double delX, double delY){
for(int i = 1; i<(row-1); ++i){
for(int j =1; j<(col-1); ++j){
int k = i*col+j;
double UP = U[k];
double UE = U[k+1];
double UW = U[k-1];
//double UN = U[k-col];
//double US = U[k+col];
double VP = V[k];
// double VE = V[k+1];
// double VW = V[k-1];
double VN = V[k-col];
double VS = V[k+col];
double Ue = 0.5*(UE+UP);
double Uw = 0.5*(UW+UP);
//double Un = 0.5*(UN+UP);
//double Us = 0.5*(US+UP);
// double Ve = 0.5*(VE+VP);
//double Vw = 0.5*(VW+VP);
double Vn = 0.5*(VN+VP);
double Vs = 0.5*(VS+VP);
Dn[k] = (Ue-Uw)*delY+(Vn-Vs)*delX;
}
}
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
// Laplacian of a Scalar !
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
void LaplacianCPU(double* Ln, double *Phi, int row, int col, double delX, double delY){
for(int i = 1; i<(row-1); i++){
for(int j =1; j<(col-1); j++){
int k = i*col+j;
double PhiP = Phi[k];
double PhiE = Phi[k+1];
double PhiW = Phi[k-1];
double PhiN = Phi[k-col];
double PhiS = Phi[k+col];
double Ee = (PhiE-PhiP)/delX;
double Ew = (PhiP-PhiW)/delX;
double Fn = (PhiN-PhiP)/delY;
double Fs = (PhiP-PhiS)/delY;
Ln[k] = delX*(Fn-Fs)+delY*(Ee-Ew);
}
}
}
__global__ void Laplacian(double* Ln, double *Phi, int row, int col, double delX, double delY){
// Get global thread ID
int k = blockIdx.x*blockDim.x+threadIdx.x;
int n = (row-1)*(col-1);
// Do for only inner points
if (k >0 && k<n) {
double PhiP = Phi[k];
double PhiE = Phi[k+1];
double PhiW = Phi[k-1];
double PhiN = Phi[k-col];
double PhiS = Phi[k+col];
double Ee = (PhiE-PhiP)/delX;
double Ew = (PhiP-PhiW)/delX;
double Fn = (PhiN-PhiP)/delY;
double Fs = (PhiP-PhiS)/delY;
Ln[k] = delX*(Fn-Fs)+delY*(Ee-Ew);
}
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
// Gradient Computation using Finite Volume !
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
void gradient(double* gradxPhi,double* gradyPhi,
double* vfacePhi,double* hfacePhi,
int cellRow, int cellCol, double delX, double delY,
int vfaceCol, int hfaceCol){
for(int i = 1; i<(cellRow-1); ++i){
for(int j =1; j<(cellCol-1); ++j){
double Phie = vfacePhi[i*vfaceCol+(j+1)];
double Phiw = vfacePhi[i*vfaceCol+j];
double Phin = hfacePhi[i*hfaceCol+j];
double Phis = hfacePhi[(i+1)*hfaceCol+j];
gradxPhi[i*cellCol+j] = (Phie-Phiw)/delX;
gradyPhi[i*cellCol+j] = (Phin-Phis)/delY;
}
}
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
// Gradient Computation using Finite Difference !
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
__global__ void gradient(double* gradxPhi,double* gradyPhi,double* Phi,
int row, int col, double delX, double delY){
// Get global thread ID
int k = blockIdx.x*blockDim.x+threadIdx.x;
int n = (row-1)*(col-1);
// Do for only inner points
if (k >0 && k<n) {
double Phie = Phi[k+1];
double Phiw = Phi[k-1];
double Phin = Phi[k-col];
double Phis = Phi[k+col];
gradxPhi[k] = (Phie-Phiw)/(2*delX);
gradyPhi[k] = (Phin-Phis)/(2*delY);
}
}
void gradientCPU(double* gradxPhi,double* gradyPhi,double* Phi,
int row, int col, double delX, double delY){
for(int i = 1; i<(row-1); ++i){
for(int j =1; j<(col-1); ++j){
int k = i*col+j;
double Phie = Phi[k+1];
double Phiw = Phi[k-1];
double Phin = Phi[k-col];
double Phis = Phi[k+col];
gradxPhi[k] = (Phie-Phiw)/(2*delX);
gradyPhi[k] = (Phin-Phis)/(2*delY);
}
}
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
// Interpolation of Vertex Values !
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
void vertexInterpolate(double* vertPhi, double* cellPhi, int vertRow, int vertCol, int cellCol){
// Inner Points
for(int i = 1; i<(vertRow-1); ++i){
for(int j =1; j<(vertCol-1); ++j){
double Ta = cellPhi[(i-1)*cellCol+(j-1)]; // NW
double Tb = cellPhi[(i-1)*cellCol+j]; // NE
double Tc = cellPhi[(i*cellCol)+(j-1)]; // SW
double Td = cellPhi[i*cellCol+j]; //SE
vertPhi[i*vertCol+j]=0.25*(Ta+Tb+Tc+Td);
}
}
//Boundary points - Set it to Boundary Cell points
//North Boundary
for (int i = 0; i<vertCol; i++){
vertPhi[i]= cellPhi[i+vertCol];
}
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
// Interpolation of Vertical FaceCenter Interpolation !
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
void vfaceInterpolate(double* vfacePhi, double* vertPhi,
double* cellPhi, int vfaceRow, int vfaceCol,
int vertCol, int cellCol){
for(int i = 1; i<(vfaceRow-1); ++i){
for(int j =1; j<(vfaceCol-1); ++j){
double Ta = cellPhi[i*cellCol+(j-1)]; // West cell
double Tb = cellPhi[i*cellCol+j]; // East cell
double Tc = vertPhi[i*vertCol+j]; // North Vertex
double Td = vertPhi[(i+1)*vertCol+j]; //South Vertex
vfacePhi[i*vfaceCol+j]=0.25*(Ta+Tb+Tc+Td);
}
}
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
// Interpolation of Horizontal FaceCenter Interpolation !
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++!
void hfaceInterpolate(double* hfacePhi, double* vertPhi,
double* cellPhi, int hfaceRow, int hfaceCol,
int vertCol, int cellCol){
for(int i = 1; i<(hfaceRow-1); ++i){
for(int j =1; j<(hfaceCol-1); ++j){
double Ta = vertPhi[i*vertCol+j]; // West vertex
double Tb = vertPhi[i*vertCol+(j+1)]; // East vertex
double Tc = cellPhi[(i-1)*cellCol+j]; // North cell
double Td = cellPhi[i*cellCol+j]; //South cell
hfacePhi[i*hfaceCol+j]=0.25*(Ta+Tb+Tc+Td);
}
}
} | .text
.file "finiteVolumeOperators.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z6DivCPUPdS_S_S_iidd
.LCPI0_0:
.quad 0x3fe0000000000000 # double 0.5
.text
.globl _Z6DivCPUPdS_S_S_iidd
.p2align 4, 0x90
.type _Z6DivCPUPdS_S_S_iidd,@function
_Z6DivCPUPdS_S_S_iidd: # @_Z6DivCPUPdS_S_S_iidd
.cfi_startproc
# %bb.0:
# kill: def $r9d killed $r9d def $r9
# kill: def $r8d killed $r8d def $r8
cmpl $3, %r8d
jl .LBB0_7
# %bb.1: # %.preheader.lr.ph
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
decl %r8d
leal -1(%r9), %r15d
movslq %r9d, %r14
leaq (,%r14,8), %rax
leaq (%rdi,%r14,8), %rdi
addq $8, %rdi
leaq (%rcx,%r14,8), %r10
addq $8, %r10
leaq (%rdx,%r14,8), %rdx
addq $16, %rdx
leaq (%rsi,%r14,8), %r11
addq $16, %r11
shlq $4, %r14
leaq (%rcx,%r14), %rbx
addq $8, %rbx
addq $8, %rcx
addq %rsi, %r14
addq $8, %r14
leaq -8(,%r15,8), %r15
movl $1, %r12d
movsd .LCPI0_0(%rip), %xmm2 # xmm2 = mem[0],zero
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_5: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
incq %r12
addq %rax, %rdi
addq %rax, %r10
addq %rax, %rdx
addq %rax, %r11
addq %rax, %rsi
addq %rax, %rcx
addq %rax, %rbx
addq %rax, %r14
cmpq %r8, %r12
je .LBB0_6
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
cmpl $3, %r9d
jl .LBB0_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB0_2 Depth=1
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movsd -16(%r11,%r13), %xmm7 # xmm7 = mem[0],zero
movsd -8(%r11,%r13), %xmm6 # xmm6 = mem[0],zero
movsd (%r11,%r13), %xmm3 # xmm3 = mem[0],zero
movsd 8(%rsi,%r13), %xmm4 # xmm4 = mem[0],zero
movsd (%r14,%r13), %xmm5 # xmm5 = mem[0],zero
mulsd (%rdx,%r13), %xmm3
movsd -8(%rdx,%r13), %xmm8 # xmm8 = mem[0],zero
mulsd %xmm6, %xmm8
addsd %xmm8, %xmm3
mulsd %xmm2, %xmm3
mulsd -16(%rdx,%r13), %xmm7
addsd %xmm8, %xmm7
mulsd %xmm2, %xmm7
mulsd (%rcx,%r13), %xmm4
subsd %xmm7, %xmm3
mulsd (%r10,%r13), %xmm6
addsd %xmm6, %xmm4
mulsd %xmm2, %xmm4
mulsd (%rbx,%r13), %xmm5
addsd %xmm6, %xmm5
mulsd %xmm2, %xmm5
subsd %xmm5, %xmm4
mulsd %xmm0, %xmm4
mulsd %xmm1, %xmm3
addsd %xmm4, %xmm3
movsd %xmm3, (%rdi,%r13)
addq $8, %r13
cmpq %r13, %r15
jne .LBB0_4
jmp .LBB0_5
.LBB0_6:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.LBB0_7: # %._crit_edge61
retq
.Lfunc_end0:
.size _Z6DivCPUPdS_S_S_iidd, .Lfunc_end0-_Z6DivCPUPdS_S_S_iidd
.cfi_endproc
# -- End function
.globl _Z18__device_stub__DivPdS_S_S_iidd # -- Begin function _Z18__device_stub__DivPdS_S_S_iidd
.p2align 4, 0x90
.type _Z18__device_stub__DivPdS_S_S_iidd,@function
_Z18__device_stub__DivPdS_S_S_iidd: # @_Z18__device_stub__DivPdS_S_S_iidd
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movsd %xmm0, 72(%rsp)
movsd %xmm1, 64(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 72(%rsp), %rax
movq %rax, 160(%rsp)
leaq 64(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3DivPdS_S_S_iidd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end1:
.size _Z18__device_stub__DivPdS_S_S_iidd, .Lfunc_end1-_Z18__device_stub__DivPdS_S_S_iidd
.cfi_endproc
# -- End function
.globl _Z25__device_stub__DivergencePdS_S_iidd # -- Begin function _Z25__device_stub__DivergencePdS_S_iidd
.p2align 4, 0x90
.type _Z25__device_stub__DivergencePdS_S_iidd,@function
_Z25__device_stub__DivergencePdS_S_iidd: # @_Z25__device_stub__DivergencePdS_S_iidd
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movsd %xmm0, 64(%rsp)
movsd %xmm1, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10DivergencePdS_S_iidd, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _Z25__device_stub__DivergencePdS_S_iidd, .Lfunc_end2-_Z25__device_stub__DivergencePdS_S_iidd
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z13DivergenceCPUPdS_S_iidd
.LCPI3_0:
.quad 0x3fe0000000000000 # double 0.5
.text
.globl _Z13DivergenceCPUPdS_S_iidd
.p2align 4, 0x90
.type _Z13DivergenceCPUPdS_S_iidd,@function
_Z13DivergenceCPUPdS_S_iidd: # @_Z13DivergenceCPUPdS_S_iidd
.cfi_startproc
# %bb.0:
# kill: def $r8d killed $r8d def $r8
# kill: def $ecx killed $ecx def $rcx
cmpl $3, %ecx
jl .LBB3_7
# %bb.1: # %.preheader.lr.ph
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
decl %ecx
leal -1(%r8), %r11d
movslq %r8d, %r10
leaq (,%r10,8), %rax
leaq (%rdi,%r10,8), %rdi
addq $8, %rdi
leaq (%rdx,%r10,8), %r9
addq $8, %r9
leaq (%rsi,%r10,8), %rsi
addq $16, %rsi
shlq $4, %r10
addq %rdx, %r10
addq $8, %r10
addq $8, %rdx
leaq -8(,%r11,8), %r11
movl $1, %ebx
movsd .LCPI3_0(%rip), %xmm2 # xmm2 = mem[0],zero
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_5: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
incq %rbx
addq %rax, %r10
addq %rax, %rdi
addq %rax, %r9
addq %rax, %rsi
addq %rax, %rdx
cmpq %rcx, %rbx
je .LBB3_6
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
cmpl $3, %r8d
jl .LBB3_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB3_2 Depth=1
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_4: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movsd -8(%rsi,%r14), %xmm3 # xmm3 = mem[0],zero
movsd (%r9,%r14), %xmm4 # xmm4 = mem[0],zero
movsd (%rsi,%r14), %xmm5 # xmm5 = mem[0],zero
addsd %xmm3, %xmm5
addsd -16(%rsi,%r14), %xmm3
mulsd %xmm2, %xmm5
mulsd %xmm2, %xmm3
subsd %xmm3, %xmm5
movsd (%rdx,%r14), %xmm3 # xmm3 = mem[0],zero
addsd %xmm4, %xmm3
mulsd %xmm2, %xmm3
addsd (%r10,%r14), %xmm4
mulsd %xmm2, %xmm4
subsd %xmm4, %xmm3
mulsd %xmm1, %xmm5
mulsd %xmm0, %xmm3
addsd %xmm5, %xmm3
movsd %xmm3, (%rdi,%r14)
addq $8, %r14
cmpq %r14, %r11
jne .LBB3_4
jmp .LBB3_5
.LBB3_6:
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.LBB3_7: # %._crit_edge41
retq
.Lfunc_end3:
.size _Z13DivergenceCPUPdS_S_iidd, .Lfunc_end3-_Z13DivergenceCPUPdS_S_iidd
.cfi_endproc
# -- End function
.globl _Z12LaplacianCPUPdS_iidd # -- Begin function _Z12LaplacianCPUPdS_iidd
.p2align 4, 0x90
.type _Z12LaplacianCPUPdS_iidd,@function
_Z12LaplacianCPUPdS_iidd: # @_Z12LaplacianCPUPdS_iidd
.cfi_startproc
# %bb.0:
# kill: def $ecx killed $ecx def $rcx
# kill: def $edx killed $edx def $rdx
cmpl $3, %edx
jl .LBB4_7
# %bb.1: # %.preheader.lr.ph
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
decl %edx
leal -1(%rcx), %r10d
movslq %ecx, %r9
leaq (,%r9,8), %rax
leaq (%rdi,%r9,8), %rdi
addq $8, %rdi
leaq (%rsi,%r9,8), %r8
addq $16, %r8
shlq $4, %r9
addq %rsi, %r9
addq $8, %r9
leaq -8(,%r10,8), %r10
movl $1, %r11d
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_5: # %._crit_edge
# in Loop: Header=BB4_2 Depth=1
incq %r11
addq %rax, %r9
addq %rax, %rdi
addq %rax, %r8
addq %rax, %rsi
cmpq %rdx, %r11
je .LBB4_6
.LBB4_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_4 Depth 2
cmpl $3, %ecx
jl .LBB4_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB4_2 Depth=1
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_4: # Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
movsd -8(%r8,%rbx), %xmm2 # xmm2 = mem[0],zero
movsd (%r8,%rbx), %xmm3 # xmm3 = mem[0],zero
movsd 8(%rsi,%rbx), %xmm4 # xmm4 = mem[0],zero
subsd %xmm2, %xmm3
divsd %xmm0, %xmm3
movapd %xmm2, %xmm5
subsd -16(%r8,%rbx), %xmm5
divsd %xmm0, %xmm5
subsd %xmm5, %xmm3
subsd %xmm2, %xmm4
divsd %xmm1, %xmm4
subsd (%r9,%rbx), %xmm2
divsd %xmm1, %xmm2
subsd %xmm2, %xmm4
mulsd %xmm0, %xmm4
mulsd %xmm1, %xmm3
addsd %xmm4, %xmm3
movsd %xmm3, (%rdi,%rbx)
addq $8, %rbx
cmpq %rbx, %r10
jne .LBB4_4
jmp .LBB4_5
.LBB4_6:
popq %rbx
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.LBB4_7: # %._crit_edge43
retq
.Lfunc_end4:
.size _Z12LaplacianCPUPdS_iidd, .Lfunc_end4-_Z12LaplacianCPUPdS_iidd
.cfi_endproc
# -- End function
.globl _Z24__device_stub__LaplacianPdS_iidd # -- Begin function _Z24__device_stub__LaplacianPdS_iidd
.p2align 4, 0x90
.type _Z24__device_stub__LaplacianPdS_iidd,@function
_Z24__device_stub__LaplacianPdS_iidd: # @_Z24__device_stub__LaplacianPdS_iidd
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movsd %xmm0, 72(%rsp)
movsd %xmm1, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9LaplacianPdS_iidd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end5:
.size _Z24__device_stub__LaplacianPdS_iidd, .Lfunc_end5-_Z24__device_stub__LaplacianPdS_iidd
.cfi_endproc
# -- End function
.globl _Z8gradientPdS_S_S_iiddii # -- Begin function _Z8gradientPdS_S_S_iiddii
.p2align 4, 0x90
.type _Z8gradientPdS_S_S_iiddii,@function
_Z8gradientPdS_S_S_iiddii: # @_Z8gradientPdS_S_S_iiddii
.cfi_startproc
# %bb.0:
# kill: def $r9d killed $r9d def $r9
# kill: def $r8d killed $r8d def $r8
cmpl $3, %r8d
jl .LBB6_7
# %bb.1: # %.preheader.lr.ph
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
decl %r8d
leal -1(%r9), %r14d
movslq 40(%rsp), %rax
movslq 48(%rsp), %r10
movslq %r9d, %r15
movq %r10, %r11
shlq $4, %r11
addq %rcx, %r11
addq $8, %r11
leaq (%rcx,%r10,8), %rcx
addq $8, %rcx
shlq $3, %r10
leaq (%rdx,%rax,8), %rdx
addq $16, %rdx
shlq $3, %rax
leaq (,%r15,8), %rbx
leaq (%rsi,%r15,8), %rsi
addq $8, %rsi
leaq (%rdi,%r15,8), %rdi
addq $8, %rdi
leaq -8(,%r14,8), %r14
movl $1, %r15d
jmp .LBB6_2
.p2align 4, 0x90
.LBB6_5: # %._crit_edge
# in Loop: Header=BB6_2 Depth=1
incq %r15
addq %r10, %r11
addq %r10, %rcx
addq %rax, %rdx
addq %rbx, %rsi
addq %rbx, %rdi
cmpq %r8, %r15
je .LBB6_6
.LBB6_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB6_4 Depth 2
cmpl $3, %r9d
jl .LBB6_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB6_2 Depth=1
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB6_4: # Parent Loop BB6_2 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rdx,%r12), %xmm2 # xmm2 = mem[0],zero
movsd (%rcx,%r12), %xmm3 # xmm3 = mem[0],zero
subsd -8(%rdx,%r12), %xmm2
divsd %xmm0, %xmm2
subsd (%r11,%r12), %xmm3
movsd %xmm2, (%rdi,%r12)
divsd %xmm1, %xmm3
movsd %xmm3, (%rsi,%r12)
addq $8, %r12
cmpq %r12, %r14
jne .LBB6_4
jmp .LBB6_5
.LBB6_6:
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.LBB6_7: # %._crit_edge38
retq
.Lfunc_end6:
.size _Z8gradientPdS_S_S_iiddii, .Lfunc_end6-_Z8gradientPdS_S_S_iiddii
.cfi_endproc
# -- End function
.globl _Z23__device_stub__gradientPdS_S_iidd # -- Begin function _Z23__device_stub__gradientPdS_S_iidd
.p2align 4, 0x90
.type _Z23__device_stub__gradientPdS_S_iidd,@function
_Z23__device_stub__gradientPdS_S_iidd: # @_Z23__device_stub__gradientPdS_S_iidd
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movsd %xmm0, 64(%rsp)
movsd %xmm1, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8gradientPdS_S_iidd, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end7:
.size _Z23__device_stub__gradientPdS_S_iidd, .Lfunc_end7-_Z23__device_stub__gradientPdS_S_iidd
.cfi_endproc
# -- End function
.globl _Z11gradientCPUPdS_S_iidd # -- Begin function _Z11gradientCPUPdS_S_iidd
.p2align 4, 0x90
.type _Z11gradientCPUPdS_S_iidd,@function
_Z11gradientCPUPdS_S_iidd: # @_Z11gradientCPUPdS_S_iidd
.cfi_startproc
# %bb.0:
# kill: def $r8d killed $r8d def $r8
# kill: def $ecx killed $ecx def $rcx
cmpl $3, %ecx
jl .LBB8_7
# %bb.1: # %.preheader.lr.ph
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
decl %ecx
leal -1(%r8), %r11d
addsd %xmm0, %xmm0
addsd %xmm1, %xmm1
movslq %r8d, %r10
leaq (,%r10,8), %rax
leaq (%rdi,%r10,8), %rdi
addq $8, %rdi
leaq (%rsi,%r10,8), %rsi
addq $8, %rsi
leaq (%rdx,%r10,8), %r9
addq $16, %r9
shlq $4, %r10
addq %rdx, %r10
addq $8, %r10
leaq -8(,%r11,8), %r11
movl $1, %ebx
jmp .LBB8_2
.p2align 4, 0x90
.LBB8_5: # %._crit_edge
# in Loop: Header=BB8_2 Depth=1
incq %rbx
addq %rax, %r10
addq %rax, %rdi
addq %rax, %rsi
addq %rax, %r9
addq %rax, %rdx
cmpq %rcx, %rbx
je .LBB8_6
.LBB8_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB8_4 Depth 2
cmpl $3, %r8d
jl .LBB8_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB8_2 Depth=1
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB8_4: # Parent Loop BB8_2 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r9,%r14), %xmm2 # xmm2 = mem[0],zero
movsd 8(%rdx,%r14), %xmm3 # xmm3 = mem[0],zero
subsd -16(%r9,%r14), %xmm2
divsd %xmm0, %xmm2
subsd (%r10,%r14), %xmm3
divsd %xmm1, %xmm3
movsd %xmm2, (%rdi,%r14)
movsd %xmm3, (%rsi,%r14)
addq $8, %r14
cmpq %r14, %r11
jne .LBB8_4
jmp .LBB8_5
.LBB8_6:
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.LBB8_7: # %._crit_edge31
retq
.Lfunc_end8:
.size _Z11gradientCPUPdS_S_iidd, .Lfunc_end8-_Z11gradientCPUPdS_S_iidd
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z17vertexInterpolatePdS_iii
.LCPI9_0:
.quad 0x3fd0000000000000 # double 0.25
.text
.globl _Z17vertexInterpolatePdS_iii
.p2align 4, 0x90
.type _Z17vertexInterpolatePdS_iii,@function
_Z17vertexInterpolatePdS_iii: # @_Z17vertexInterpolatePdS_iii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
# kill: def $ecx killed $ecx def $rcx
# kill: def $edx killed $edx def $rdx
cmpl $3, %edx
jl .LBB9_6
# %bb.1: # %.preheader40.lr.ph
decl %edx
leal -1(%rcx), %eax
movslq %r8d, %r8
movslq %ecx, %r9
leaq (%rdi,%r9,8), %r10
shlq $3, %r9
leaq (%rsi,%r8,8), %r11
shlq $3, %r8
movl $1, %ebx
movsd .LCPI9_0(%rip), %xmm0 # xmm0 = mem[0],zero
movq %rsi, %r14
jmp .LBB9_2
.p2align 4, 0x90
.LBB9_5: # %._crit_edge
# in Loop: Header=BB9_2 Depth=1
incq %rbx
addq %r9, %r10
addq %r8, %r11
addq %r8, %r14
cmpq %rdx, %rbx
je .LBB9_6
.LBB9_2: # %.preheader40
# =>This Loop Header: Depth=1
# Child Loop BB9_4 Depth 2
cmpl $3, %ecx
jl .LBB9_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB9_2 Depth=1
movl $1, %r15d
.p2align 4, 0x90
.LBB9_4: # Parent Loop BB9_2 Depth=1
# => This Inner Loop Header: Depth=2
movsd -8(%r14,%r15,8), %xmm1 # xmm1 = mem[0],zero
addsd (%r14,%r15,8), %xmm1
addsd -8(%r11,%r15,8), %xmm1
addsd (%r11,%r15,8), %xmm1
mulsd %xmm0, %xmm1
movsd %xmm1, (%r10,%r15,8)
incq %r15
cmpq %r15, %rax
jne .LBB9_4
jmp .LBB9_5
.LBB9_6: # %.preheader
testl %ecx, %ecx
jle .LBB9_9
# %bb.7: # %.lr.ph44.preheader
movl %ecx, %eax
leaq (%rsi,%rax,8), %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB9_8: # %.lr.ph44
# =>This Inner Loop Header: Depth=1
movsd (%rcx,%rdx,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%rdi,%rdx,8)
incq %rdx
cmpq %rdx, %rax
jne .LBB9_8
.LBB9_9: # %._crit_edge45
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end9:
.size _Z17vertexInterpolatePdS_iii, .Lfunc_end9-_Z17vertexInterpolatePdS_iii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z16vfaceInterpolatePdS_S_iiii
.LCPI10_0:
.quad 0x3fd0000000000000 # double 0.25
.text
.globl _Z16vfaceInterpolatePdS_S_iiii
.p2align 4, 0x90
.type _Z16vfaceInterpolatePdS_S_iiii,@function
_Z16vfaceInterpolatePdS_S_iiii: # @_Z16vfaceInterpolatePdS_S_iiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
# kill: def $r8d killed $r8d def $r8
movq %r8, -16(%rsp) # 8-byte Spill
# kill: def $ecx killed $ecx def $rcx
movq %rcx, -24(%rsp) # 8-byte Spill
cmpl $3, %ecx
jl .LBB10_6
# %bb.1: # %.preheader.lr.ph
movq -24(%rsp), %rax # 8-byte Reload
decl %eax
movq %rax, -24(%rsp) # 8-byte Spill
movq -16(%rsp), %r8 # 8-byte Reload
leal -1(%r8), %eax
movslq 56(%rsp), %rcx
movslq %r9d, %r9
movslq %r8d, %r8
leaq (%rdi,%r8,8), %rdi
shlq $3, %r8
movq %r8, -8(%rsp) # 8-byte Spill
movq %r9, %rbx
shlq $4, %rbx
addq %rsi, %rbx
leaq (%rsi,%r9,8), %rsi
shlq $3, %r9
leaq (,%rcx,8), %r14
leaq (%rdx,%rcx,8), %r15
shlq $32, %rcx
movl $1, %r12d
movsd .LCPI10_0(%rip), %xmm0 # xmm0 = mem[0],zero
movabsq $4294967296, %r13 # imm = 0x100000000
movq %rcx, %r8
jmp .LBB10_2
.p2align 4, 0x90
.LBB10_5: # %._crit_edge
# in Loop: Header=BB10_2 Depth=1
incq %r12
addq -8(%rsp), %rdi # 8-byte Folded Reload
addq %r9, %rbx
addq %r9, %rsi
addq %r14, %r15
addq %rcx, %r8
cmpq -24(%rsp), %r12 # 8-byte Folded Reload
je .LBB10_6
.LBB10_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB10_4 Depth 2
cmpl $3, -16(%rsp) # 4-byte Folded Reload
jl .LBB10_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB10_2 Depth=1
movl $1, %r11d
movq %r8, %r10
.p2align 4, 0x90
.LBB10_4: # Parent Loop BB10_2 Depth=1
# => This Inner Loop Header: Depth=2
movq %r10, %rbp
sarq $29, %rbp
movsd (%rdx,%rbp), %xmm1 # xmm1 = mem[0],zero
addsd (%r15,%r11,8), %xmm1
addsd (%rsi,%r11,8), %xmm1
addsd (%rbx,%r11,8), %xmm1
mulsd %xmm0, %xmm1
movsd %xmm1, (%rdi,%r11,8)
incq %r11
addq %r13, %r10
cmpq %r11, %rax
jne .LBB10_4
jmp .LBB10_5
.LBB10_6: # %._crit_edge32
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end10:
.size _Z16vfaceInterpolatePdS_S_iiii, .Lfunc_end10-_Z16vfaceInterpolatePdS_S_iiii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z16hfaceInterpolatePdS_S_iiii
.LCPI11_0:
.quad 0x3fd0000000000000 # double 0.25
.text
.globl _Z16hfaceInterpolatePdS_S_iiii
.p2align 4, 0x90
.type _Z16hfaceInterpolatePdS_S_iiii,@function
_Z16hfaceInterpolatePdS_S_iiii: # @_Z16hfaceInterpolatePdS_S_iiii
.cfi_startproc
# %bb.0:
# kill: def $r8d killed $r8d def $r8
# kill: def $ecx killed $ecx def $rcx
cmpl $3, %ecx
jl .LBB11_7
# %bb.1: # %.preheader.lr.ph
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
decl %ecx
leal -1(%r8), %ebx
movslq %r9d, %rax
movslq 32(%rsp), %r9
movslq %r8d, %r10
leaq (%rdi,%r10,8), %rdi
addq $8, %rdi
shlq $3, %r10
leaq (%rdx,%r9,8), %r11
addq $8, %r11
shlq $3, %r9
addq $8, %rdx
leaq (%rsi,%rax,8), %rsi
addq $16, %rsi
shlq $3, %rax
leaq -8(,%rbx,8), %rbx
movl $1, %r14d
movsd .LCPI11_0(%rip), %xmm0 # xmm0 = mem[0],zero
jmp .LBB11_2
.p2align 4, 0x90
.LBB11_5: # %._crit_edge
# in Loop: Header=BB11_2 Depth=1
incq %r14
addq %r10, %rdi
addq %r9, %r11
addq %r9, %rdx
addq %rax, %rsi
cmpq %rcx, %r14
je .LBB11_6
.LBB11_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB11_4 Depth 2
cmpl $3, %r8d
jl .LBB11_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB11_2 Depth=1
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB11_4: # Parent Loop BB11_2 Depth=1
# => This Inner Loop Header: Depth=2
movsd -8(%rsi,%r15), %xmm1 # xmm1 = mem[0],zero
addsd (%rsi,%r15), %xmm1
addsd (%rdx,%r15), %xmm1
addsd (%r11,%r15), %xmm1
mulsd %xmm0, %xmm1
movsd %xmm1, (%rdi,%r15)
addq $8, %r15
cmpq %r15, %rbx
jne .LBB11_4
jmp .LBB11_5
.LBB11_6:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB11_7: # %._crit_edge32
retq
.Lfunc_end11:
.size _Z16hfaceInterpolatePdS_S_iiii, .Lfunc_end11-_Z16hfaceInterpolatePdS_S_iiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB12_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB12_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3DivPdS_S_S_iidd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10DivergencePdS_S_iidd, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9LaplacianPdS_iidd, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8gradientPdS_S_iidd, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end12:
.size __hip_module_ctor, .Lfunc_end12-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB13_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB13_2:
retq
.Lfunc_end13:
.size __hip_module_dtor, .Lfunc_end13-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3DivPdS_S_S_iidd,@object # @_Z3DivPdS_S_S_iidd
.section .rodata,"a",@progbits
.globl _Z3DivPdS_S_S_iidd
.p2align 3, 0x0
_Z3DivPdS_S_S_iidd:
.quad _Z18__device_stub__DivPdS_S_S_iidd
.size _Z3DivPdS_S_S_iidd, 8
.type _Z10DivergencePdS_S_iidd,@object # @_Z10DivergencePdS_S_iidd
.globl _Z10DivergencePdS_S_iidd
.p2align 3, 0x0
_Z10DivergencePdS_S_iidd:
.quad _Z25__device_stub__DivergencePdS_S_iidd
.size _Z10DivergencePdS_S_iidd, 8
.type _Z9LaplacianPdS_iidd,@object # @_Z9LaplacianPdS_iidd
.globl _Z9LaplacianPdS_iidd
.p2align 3, 0x0
_Z9LaplacianPdS_iidd:
.quad _Z24__device_stub__LaplacianPdS_iidd
.size _Z9LaplacianPdS_iidd, 8
.type _Z8gradientPdS_S_iidd,@object # @_Z8gradientPdS_S_iidd
.globl _Z8gradientPdS_S_iidd
.p2align 3, 0x0
_Z8gradientPdS_S_iidd:
.quad _Z23__device_stub__gradientPdS_S_iidd
.size _Z8gradientPdS_S_iidd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3DivPdS_S_S_iidd"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10DivergencePdS_S_iidd"
.size .L__unnamed_2, 25
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z9LaplacianPdS_iidd"
.size .L__unnamed_3, 21
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z8gradientPdS_S_iidd"
.size .L__unnamed_4, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__DivPdS_S_S_iidd
.addrsig_sym _Z25__device_stub__DivergencePdS_S_iidd
.addrsig_sym _Z24__device_stub__LaplacianPdS_iidd
.addrsig_sym _Z23__device_stub__gradientPdS_S_iidd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3DivPdS_S_S_iidd
.addrsig_sym _Z10DivergencePdS_S_iidd
.addrsig_sym _Z9LaplacianPdS_iidd
.addrsig_sym _Z8gradientPdS_S_iidd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda_runtime.h>
#define REP1(x) x
#define REP2(x) REP1(x) REP1(x)
#define REP4(x) REP2(x) REP2(x)
#define REP8(x) REP4(x) REP4(x)
#define REP16(x) REP8(x) REP8(x)
#define REP32(x) REP16(x) REP16(x)
#define REP64(x) REP32(x) REP32(x)
#define REP128(x) REP64(x) REP64(x)
#define REP256(x) REP128(x) REP128(x)
#define REP512(x) REP256(x) REP256(x)
#define REP1024(x) REP512(x) REP512(x)
#define REP2048(x) REP1024(x) REP1024(x)
#define REP4096(x) REP2048(x) REP2048(x)
#define REP8192(x) REP4096(x) REP4096(x)
#define REP16384(x) REP8192(x) REP8192(x)
#define REP32768(x) REP16384(x) REP16384(x)
//#define ARRAY_SIZE 17000
//#define STRIDE 11
#define DATA_TYPE long long
__global__ void read_cache(DATA_TYPE* device_array) {
DATA_TYPE* j = &device_array[0];
REP4096(j=*(DATA_TYPE**)j;)
device_array[0] = (DATA_TYPE)j;
}
int main(int argc, char* argv[]) {
cudaError_t err = cudaSuccess;
DATA_TYPE* host_array = NULL;
DATA_TYPE* device_array = NULL;
size_t size;
int i;
if (argc < 3) {
printf("Not enough parameters! Exitting...\n");
return -1;
}
int ARRAY_SIZE = atoi(argv[1]);
int STRIDE = atoi(argv[2]);
size = sizeof(DATA_TYPE) * ARRAY_SIZE;
host_array = (DATA_TYPE*)malloc(size);
if (host_array == NULL) {
printf("Failed to malloc!\n");
return -1;
}
err = cudaMalloc((void**)&device_array, size);
if (err != cudaSuccess) {
printf("Failed to cudaMalloc!\n");
free(host_array);
return -1;
}
for (i = 0; i < ARRAY_SIZE; i++) {
DATA_TYPE t = i + STRIDE;
if (t >= ARRAY_SIZE) t %= STRIDE;
host_array[i] = (DATA_TYPE)device_array + (DATA_TYPE)sizeof(DATA_TYPE) * t;
}
err = cudaMemcpy(device_array, host_array, size, cudaMemcpyHostToDevice);
if (err != cudaSuccess) {
printf("Failed to cudaMemcpy!\n");
free(host_array);
cudaFree(device_array);
return -1;
}
read_cache<<<1, 1>>>(device_array);
err = cudaGetLastError();
if (err != cudaSuccess) {
printf("Failed to invoke kernel!\n");
free(host_array);
cudaFree(device_array);
return -1;
}
free(host_array);
cudaFree(device_array);
return 0;
} | .file "tmpxft_00076d6e_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z10read_cachePxPx
.type _Z30__device_stub__Z10read_cachePxPx, @function
_Z30__device_stub__Z10read_cachePxPx:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10read_cachePx(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z10read_cachePxPx, .-_Z30__device_stub__Z10read_cachePxPx
.globl _Z10read_cachePx
.type _Z10read_cachePx, @function
_Z10read_cachePx:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10read_cachePxPx
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10read_cachePx, .-_Z10read_cachePx
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Not enough parameters! Exitting...\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Failed to malloc!\n"
.LC2:
.string "Failed to cudaMalloc!\n"
.LC3:
.string "Failed to cudaMemcpy!\n"
.LC4:
.string "Failed to invoke kernel!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
cmpl $2, %edi
jle .L26
movq %rsi, %rbp
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
movl %eax, %ebx
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movl %eax, %r14d
movslq %r15d, %r12
salq $3, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
testq %rax, %rax
je .L27
leaq 8(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L15
testl %r15d, %r15d
jle .L17
movq 8(%rsp), %r8
movslq %r13d, %rax
leal -1(%r15), %edx
leaq 1(%rax,%rdx), %r9
movq %rax, %rdx
negq %rdx
leaq 0(%rbp,%rdx,8), %rdi
movq %rax, %rcx
subl %eax, %r13d
movslq %r14d, %rsi
jmp .L19
.L26:
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $-1, %eax
jmp .L11
.L27:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %eax
jmp .L11
.L15:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movl $-1, %eax
jmp .L11
.L18:
leaq (%r8,%rdx,8), %rax
movq %rax, (%rdi,%rcx,8)
addq $1, %rcx
cmpq %r9, %rcx
je .L17
.L19:
movq %rcx, %rdx
leal 0(%r13,%rcx), %eax
cmpl %eax, %ebx
jg .L18
movq %rcx, %rax
cqto
idivq %rsi
jmp .L18
.L17:
movl $1, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L28
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L21:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L30
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
.L11:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L31
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl $-1, %eax
jmp .L11
.L29:
movq 8(%rsp), %rdi
call _Z30__device_stub__Z10read_cachePxPx
jmp .L21
.L30:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl $-1, %eax
jmp .L11
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z10read_cachePx"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z10read_cachePx(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda_runtime.h>
#define REP1(x) x
#define REP2(x) REP1(x) REP1(x)
#define REP4(x) REP2(x) REP2(x)
#define REP8(x) REP4(x) REP4(x)
#define REP16(x) REP8(x) REP8(x)
#define REP32(x) REP16(x) REP16(x)
#define REP64(x) REP32(x) REP32(x)
#define REP128(x) REP64(x) REP64(x)
#define REP256(x) REP128(x) REP128(x)
#define REP512(x) REP256(x) REP256(x)
#define REP1024(x) REP512(x) REP512(x)
#define REP2048(x) REP1024(x) REP1024(x)
#define REP4096(x) REP2048(x) REP2048(x)
#define REP8192(x) REP4096(x) REP4096(x)
#define REP16384(x) REP8192(x) REP8192(x)
#define REP32768(x) REP16384(x) REP16384(x)
//#define ARRAY_SIZE 17000
//#define STRIDE 11
#define DATA_TYPE long long
__global__ void read_cache(DATA_TYPE* device_array) {
DATA_TYPE* j = &device_array[0];
REP4096(j=*(DATA_TYPE**)j;)
device_array[0] = (DATA_TYPE)j;
}
int main(int argc, char* argv[]) {
cudaError_t err = cudaSuccess;
DATA_TYPE* host_array = NULL;
DATA_TYPE* device_array = NULL;
size_t size;
int i;
if (argc < 3) {
printf("Not enough parameters! Exitting...\n");
return -1;
}
int ARRAY_SIZE = atoi(argv[1]);
int STRIDE = atoi(argv[2]);
size = sizeof(DATA_TYPE) * ARRAY_SIZE;
host_array = (DATA_TYPE*)malloc(size);
if (host_array == NULL) {
printf("Failed to malloc!\n");
return -1;
}
err = cudaMalloc((void**)&device_array, size);
if (err != cudaSuccess) {
printf("Failed to cudaMalloc!\n");
free(host_array);
return -1;
}
for (i = 0; i < ARRAY_SIZE; i++) {
DATA_TYPE t = i + STRIDE;
if (t >= ARRAY_SIZE) t %= STRIDE;
host_array[i] = (DATA_TYPE)device_array + (DATA_TYPE)sizeof(DATA_TYPE) * t;
}
err = cudaMemcpy(device_array, host_array, size, cudaMemcpyHostToDevice);
if (err != cudaSuccess) {
printf("Failed to cudaMemcpy!\n");
free(host_array);
cudaFree(device_array);
return -1;
}
read_cache<<<1, 1>>>(device_array);
err = cudaGetLastError();
if (err != cudaSuccess) {
printf("Failed to invoke kernel!\n");
free(host_array);
cudaFree(device_array);
return -1;
}
free(host_array);
cudaFree(device_array);
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#define REP1(x) x
#define REP2(x) REP1(x) REP1(x)
#define REP4(x) REP2(x) REP2(x)
#define REP8(x) REP4(x) REP4(x)
#define REP16(x) REP8(x) REP8(x)
#define REP32(x) REP16(x) REP16(x)
#define REP64(x) REP32(x) REP32(x)
#define REP128(x) REP64(x) REP64(x)
#define REP256(x) REP128(x) REP128(x)
#define REP512(x) REP256(x) REP256(x)
#define REP1024(x) REP512(x) REP512(x)
#define REP2048(x) REP1024(x) REP1024(x)
#define REP4096(x) REP2048(x) REP2048(x)
#define REP8192(x) REP4096(x) REP4096(x)
#define REP16384(x) REP8192(x) REP8192(x)
#define REP32768(x) REP16384(x) REP16384(x)
//#define ARRAY_SIZE 17000
//#define STRIDE 11
#define DATA_TYPE long long
__global__ void read_cache(DATA_TYPE* device_array) {
DATA_TYPE* j = &device_array[0];
REP4096(j=*(DATA_TYPE**)j;)
device_array[0] = (DATA_TYPE)j;
}
int main(int argc, char* argv[]) {
hipError_t err = hipSuccess;
DATA_TYPE* host_array = NULL;
DATA_TYPE* device_array = NULL;
size_t size;
int i;
if (argc < 3) {
printf("Not enough parameters! Exitting...\n");
return -1;
}
int ARRAY_SIZE = atoi(argv[1]);
int STRIDE = atoi(argv[2]);
size = sizeof(DATA_TYPE) * ARRAY_SIZE;
host_array = (DATA_TYPE*)malloc(size);
if (host_array == NULL) {
printf("Failed to malloc!\n");
return -1;
}
err = hipMalloc((void**)&device_array, size);
if (err != hipSuccess) {
printf("Failed to cudaMalloc!\n");
free(host_array);
return -1;
}
for (i = 0; i < ARRAY_SIZE; i++) {
DATA_TYPE t = i + STRIDE;
if (t >= ARRAY_SIZE) t %= STRIDE;
host_array[i] = (DATA_TYPE)device_array + (DATA_TYPE)sizeof(DATA_TYPE) * t;
}
err = hipMemcpy(device_array, host_array, size, hipMemcpyHostToDevice);
if (err != hipSuccess) {
printf("Failed to cudaMemcpy!\n");
free(host_array);
hipFree(device_array);
return -1;
}
read_cache<<<1, 1>>>(device_array);
err = hipGetLastError();
if (err != hipSuccess) {
printf("Failed to invoke kernel!\n");
free(host_array);
hipFree(device_array);
return -1;
}
free(host_array);
hipFree(device_array);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#define REP1(x) x
#define REP2(x) REP1(x) REP1(x)
#define REP4(x) REP2(x) REP2(x)
#define REP8(x) REP4(x) REP4(x)
#define REP16(x) REP8(x) REP8(x)
#define REP32(x) REP16(x) REP16(x)
#define REP64(x) REP32(x) REP32(x)
#define REP128(x) REP64(x) REP64(x)
#define REP256(x) REP128(x) REP128(x)
#define REP512(x) REP256(x) REP256(x)
#define REP1024(x) REP512(x) REP512(x)
#define REP2048(x) REP1024(x) REP1024(x)
#define REP4096(x) REP2048(x) REP2048(x)
#define REP8192(x) REP4096(x) REP4096(x)
#define REP16384(x) REP8192(x) REP8192(x)
#define REP32768(x) REP16384(x) REP16384(x)
//#define ARRAY_SIZE 17000
//#define STRIDE 11
#define DATA_TYPE long long
__global__ void read_cache(DATA_TYPE* device_array) {
DATA_TYPE* j = &device_array[0];
REP4096(j=*(DATA_TYPE**)j;)
device_array[0] = (DATA_TYPE)j;
}
int main(int argc, char* argv[]) {
hipError_t err = hipSuccess;
DATA_TYPE* host_array = NULL;
DATA_TYPE* device_array = NULL;
size_t size;
int i;
if (argc < 3) {
printf("Not enough parameters! Exitting...\n");
return -1;
}
int ARRAY_SIZE = atoi(argv[1]);
int STRIDE = atoi(argv[2]);
size = sizeof(DATA_TYPE) * ARRAY_SIZE;
host_array = (DATA_TYPE*)malloc(size);
if (host_array == NULL) {
printf("Failed to malloc!\n");
return -1;
}
err = hipMalloc((void**)&device_array, size);
if (err != hipSuccess) {
printf("Failed to cudaMalloc!\n");
free(host_array);
return -1;
}
for (i = 0; i < ARRAY_SIZE; i++) {
DATA_TYPE t = i + STRIDE;
if (t >= ARRAY_SIZE) t %= STRIDE;
host_array[i] = (DATA_TYPE)device_array + (DATA_TYPE)sizeof(DATA_TYPE) * t;
}
err = hipMemcpy(device_array, host_array, size, hipMemcpyHostToDevice);
if (err != hipSuccess) {
printf("Failed to cudaMemcpy!\n");
free(host_array);
hipFree(device_array);
return -1;
}
read_cache<<<1, 1>>>(device_array);
err = hipGetLastError();
if (err != hipSuccess) {
printf("Failed to invoke kernel!\n");
free(host_array);
hipFree(device_array);
return -1;
}
free(host_array);
hipFree(device_array);
return 0;
} | .text
.file "main.hip"
.globl _Z25__device_stub__read_cachePx # -- Begin function _Z25__device_stub__read_cachePx
.p2align 4, 0x90
.type _Z25__device_stub__read_cachePx,@function
_Z25__device_stub__read_cachePx: # @_Z25__device_stub__read_cachePx
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10read_cachePx, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z25__device_stub__read_cachePx, .Lfunc_end0-_Z25__device_stub__read_cachePx
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq $0, (%rsp)
cmpl $2, %edi
jg .LBB1_2
# %bb.1:
movl $.Lstr.4, %edi
jmp .LBB1_6
.LBB1_2:
movq 8(%rsi), %rdi
movq %rsi, %rbx
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movslq %r15d, %r14
shlq $3, %r14
movq %r14, %rdi
callq malloc
testq %rax, %rax
je .LBB1_5
# %bb.3:
movq %rax, %rbx
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
je .LBB1_9
# %bb.4:
movl $.Lstr.2, %edi
callq puts@PLT
movq %rbx, %rdi
callq free
jmp .LBB1_7
.LBB1_5:
movl $.Lstr.3, %edi
.LBB1_6:
callq puts@PLT
.LBB1_7:
movl $-1, %eax
.LBB1_8:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_9: # %.preheader
.cfi_def_cfa_offset 48
testl %r15d, %r15d
jle .LBB1_14
# %bb.10: # %.lr.ph
movslq %r12d, %rcx
movq (%rsp), %rsi
movl %r15d, %edi
xorl %r8d, %r8d
jmp .LBB1_12
.p2align 4, 0x90
.LBB1_11: # in Loop: Header=BB1_12 Depth=1
leaq (%rsi,%rax,8), %rax
movq %rax, (%rbx,%r8,8)
incq %r8
cmpq %r8, %rdi
je .LBB1_14
.LBB1_12: # =>This Inner Loop Header: Depth=1
leaq (%rcx,%r8), %rax
cmpq %rdi, %rax
jl .LBB1_11
# %bb.13: # in Loop: Header=BB1_12 Depth=1
cqto
idivq %rcx
movq %rdx, %rax
jmp .LBB1_11
.LBB1_14: # %._crit_edge
movq (%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_16
# %bb.15:
movl $.Lstr.1, %edi
jmp .LBB1_20
.LBB1_16:
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_18
# %bb.17:
movq (%rsp), %rdi
callq _Z25__device_stub__read_cachePx
.LBB1_18:
callq hipGetLastError
testl %eax, %eax
je .LBB1_21
# %bb.19:
movl $.Lstr, %edi
.LBB1_20:
callq puts@PLT
movq %rbx, %rdi
callq free
movq (%rsp), %rdi
callq hipFree
jmp .LBB1_7
.LBB1_21:
movq %rbx, %rdi
callq free
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
jmp .LBB1_8
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10read_cachePx, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10read_cachePx,@object # @_Z10read_cachePx
.section .rodata,"a",@progbits
.globl _Z10read_cachePx
.p2align 3, 0x0
_Z10read_cachePx:
.quad _Z25__device_stub__read_cachePx
.size _Z10read_cachePx, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10read_cachePx"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Failed to invoke kernel!"
.size .Lstr, 25
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Failed to cudaMemcpy!"
.size .Lstr.1, 22
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Failed to cudaMalloc!"
.size .Lstr.2, 22
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Failed to malloc!"
.size .Lstr.3, 18
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Not enough parameters! Exitting..."
.size .Lstr.4, 35
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__read_cachePx
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10read_cachePx
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00076d6e_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z10read_cachePxPx
.type _Z30__device_stub__Z10read_cachePxPx, @function
_Z30__device_stub__Z10read_cachePxPx:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10read_cachePx(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z10read_cachePxPx, .-_Z30__device_stub__Z10read_cachePxPx
.globl _Z10read_cachePx
.type _Z10read_cachePx, @function
_Z10read_cachePx:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10read_cachePxPx
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10read_cachePx, .-_Z10read_cachePx
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Not enough parameters! Exitting...\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Failed to malloc!\n"
.LC2:
.string "Failed to cudaMalloc!\n"
.LC3:
.string "Failed to cudaMemcpy!\n"
.LC4:
.string "Failed to invoke kernel!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
cmpl $2, %edi
jle .L26
movq %rsi, %rbp
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
movl %eax, %ebx
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movl %eax, %r14d
movslq %r15d, %r12
salq $3, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
testq %rax, %rax
je .L27
leaq 8(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L15
testl %r15d, %r15d
jle .L17
movq 8(%rsp), %r8
movslq %r13d, %rax
leal -1(%r15), %edx
leaq 1(%rax,%rdx), %r9
movq %rax, %rdx
negq %rdx
leaq 0(%rbp,%rdx,8), %rdi
movq %rax, %rcx
subl %eax, %r13d
movslq %r14d, %rsi
jmp .L19
.L26:
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $-1, %eax
jmp .L11
.L27:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %eax
jmp .L11
.L15:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movl $-1, %eax
jmp .L11
.L18:
leaq (%r8,%rdx,8), %rax
movq %rax, (%rdi,%rcx,8)
addq $1, %rcx
cmpq %r9, %rcx
je .L17
.L19:
movq %rcx, %rdx
leal 0(%r13,%rcx), %eax
cmpl %eax, %ebx
jg .L18
movq %rcx, %rax
cqto
idivq %rsi
jmp .L18
.L17:
movl $1, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L28
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L21:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L30
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
.L11:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L31
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl $-1, %eax
jmp .L11
.L29:
movq 8(%rsp), %rdi
call _Z30__device_stub__Z10read_cachePxPx
jmp .L21
.L30:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl $-1, %eax
jmp .L11
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z10read_cachePx"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z10read_cachePx(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z25__device_stub__read_cachePx # -- Begin function _Z25__device_stub__read_cachePx
.p2align 4, 0x90
.type _Z25__device_stub__read_cachePx,@function
_Z25__device_stub__read_cachePx: # @_Z25__device_stub__read_cachePx
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10read_cachePx, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z25__device_stub__read_cachePx, .Lfunc_end0-_Z25__device_stub__read_cachePx
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq $0, (%rsp)
cmpl $2, %edi
jg .LBB1_2
# %bb.1:
movl $.Lstr.4, %edi
jmp .LBB1_6
.LBB1_2:
movq 8(%rsi), %rdi
movq %rsi, %rbx
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movslq %r15d, %r14
shlq $3, %r14
movq %r14, %rdi
callq malloc
testq %rax, %rax
je .LBB1_5
# %bb.3:
movq %rax, %rbx
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
je .LBB1_9
# %bb.4:
movl $.Lstr.2, %edi
callq puts@PLT
movq %rbx, %rdi
callq free
jmp .LBB1_7
.LBB1_5:
movl $.Lstr.3, %edi
.LBB1_6:
callq puts@PLT
.LBB1_7:
movl $-1, %eax
.LBB1_8:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_9: # %.preheader
.cfi_def_cfa_offset 48
testl %r15d, %r15d
jle .LBB1_14
# %bb.10: # %.lr.ph
movslq %r12d, %rcx
movq (%rsp), %rsi
movl %r15d, %edi
xorl %r8d, %r8d
jmp .LBB1_12
.p2align 4, 0x90
.LBB1_11: # in Loop: Header=BB1_12 Depth=1
leaq (%rsi,%rax,8), %rax
movq %rax, (%rbx,%r8,8)
incq %r8
cmpq %r8, %rdi
je .LBB1_14
.LBB1_12: # =>This Inner Loop Header: Depth=1
leaq (%rcx,%r8), %rax
cmpq %rdi, %rax
jl .LBB1_11
# %bb.13: # in Loop: Header=BB1_12 Depth=1
cqto
idivq %rcx
movq %rdx, %rax
jmp .LBB1_11
.LBB1_14: # %._crit_edge
movq (%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_16
# %bb.15:
movl $.Lstr.1, %edi
jmp .LBB1_20
.LBB1_16:
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_18
# %bb.17:
movq (%rsp), %rdi
callq _Z25__device_stub__read_cachePx
.LBB1_18:
callq hipGetLastError
testl %eax, %eax
je .LBB1_21
# %bb.19:
movl $.Lstr, %edi
.LBB1_20:
callq puts@PLT
movq %rbx, %rdi
callq free
movq (%rsp), %rdi
callq hipFree
jmp .LBB1_7
.LBB1_21:
movq %rbx, %rdi
callq free
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
jmp .LBB1_8
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10read_cachePx, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10read_cachePx,@object # @_Z10read_cachePx
.section .rodata,"a",@progbits
.globl _Z10read_cachePx
.p2align 3, 0x0
_Z10read_cachePx:
.quad _Z25__device_stub__read_cachePx
.size _Z10read_cachePx, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10read_cachePx"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Failed to invoke kernel!"
.size .Lstr, 25
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Failed to cudaMemcpy!"
.size .Lstr.1, 22
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Failed to cudaMalloc!"
.size .Lstr.2, 22
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Failed to malloc!"
.size .Lstr.3, 18
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Not enough parameters! Exitting..."
.size .Lstr.4, 35
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__read_cachePx
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10read_cachePx
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cstdio>
#include <thrust/scan.h>
#include <thrust/device_vector.h>
__global__ void computeLengths(int* data, int* lengths, int* symbolSizes, int n) {
int thid = (blockIdx.x * blockDim.x) + threadIdx.x;
if (thid >= n) return;
lengths[thid] = symbolSizes[data[thid]];
//printf("%d %d\n", thid, lengths[thid]);
}
int* toIntPtr(thrust::device_vector<int>& v) {
return thrust::raw_pointer_cast(&v[0]);
}
__global__ void computeFirstByteSym(int* lengthSum, int* firstByteSym, int n, int outSize) {
int thid = (blockIdx.x * blockDim.x) + threadIdx.x;
if (thid >= n || thid == 0) return;
int curr = (lengthSum[thid - 1] / 8);
int prev = (thid == 1) ? 0 : (lengthSum[thid - 2]/8);
if (prev != curr) {
//printf("sym: %d, curr: %d\n", thid, curr);
firstByteSym[curr] = thid;
}
}
__global__ void computeResult(int* symbols, int* data, int* firstByteSym, int* lengthSum, int* results, int n, int outSize) {
int thid = (blockIdx.x * blockDim.x) + threadIdx.x;
if (thid >= outSize) return;
int symI = firstByteSym[thid];
if (symI != 0) symI --;
int offsetDelta = thid * 8;
//printf("thid: %d, sym: %d\n", thid, symI);
int result = 0;
while (symI < n) {
int shift = (symI == 0 ? 0 : lengthSum[symI-1]) - offsetDelta;
//printf("thid: %d | symI: %d, shift: %d\n", thid, symI, shift);
if (shift > 8) break;
int code = symbols[data[symI]];
if (shift >= 0)
result |= code << shift;
else
result |= code >> (-shift);
symI ++;
}
results[thid] = result;
}
int main(){
cudaSetDevice(1);
int symbolsData[] = {0b1, 0b01, 0b001, 0b000};
int sizesData[] = {1, 2, 3, 3};
const int symN = 4;
const int dataN = 10000;
thrust::device_vector<int> data;
for (int i=0; i < dataN; i ++) data.push_back(i % symN);
thrust::device_vector<int> symbols (symbolsData, symbolsData + symN);
thrust::device_vector<int> symbolSizes (sizesData, sizesData + symN);
thrust::device_vector<int> lengthSum (dataN);
computeLengths<<<(dataN + 1023) / 1024, 1024>>>
(toIntPtr(data), toIntPtr(lengthSum),
toIntPtr(symbolSizes), dataN);
thrust::inclusive_scan(lengthSum.begin(), lengthSum.end(), lengthSum.begin());
//for (int i : lengthSum) printf("l=%d\n", i);
int outSize = (lengthSum.back() / 8 + 1);
thrust::device_vector<int> firstByteSym;
firstByteSym.resize(outSize, 0);
computeFirstByteSym<<<(outSize + 1023) / 1024, 1024>>>
(toIntPtr(lengthSum),
toIntPtr(firstByteSym),
dataN, outSize);
//for (int i : firstByteSym) printf("s=%d\n", i);
thrust::device_vector<int> result;
result.resize(outSize, 0);
computeResult<<<(outSize + 1023) / 1024, 1024>>>
(toIntPtr(symbols),
toIntPtr(data),
toIntPtr(firstByteSym),
toIntPtr(lengthSum),
toIntPtr(result),
dataN, outSize);
//for (int i : result) printf("result=%d\n", i);
cudaDeviceSynchronize ();
return 0;
} | #include <hip/hip_runtime.h>
#include <cstdio>
#include <thrust/scan.h>
#include <thrust/device_vector.h>
__global__ void computeLengths(int* data, int* lengths, int* symbolSizes, int n) {
int thid = (blockIdx.x * blockDim.x) + threadIdx.x;
if (thid >= n) return;
lengths[thid] = symbolSizes[data[thid]];
//printf("%d %d\n", thid, lengths[thid]);
}
int* toIntPtr(thrust::device_vector<int>& v) {
return thrust::raw_pointer_cast(&v[0]);
}
__global__ void computeFirstByteSym(int* lengthSum, int* firstByteSym, int n, int outSize) {
int thid = (blockIdx.x * blockDim.x) + threadIdx.x;
if (thid >= n || thid == 0) return;
int curr = (lengthSum[thid - 1] / 8);
int prev = (thid == 1) ? 0 : (lengthSum[thid - 2]/8);
if (prev != curr) {
//printf("sym: %d, curr: %d\n", thid, curr);
firstByteSym[curr] = thid;
}
}
__global__ void computeResult(int* symbols, int* data, int* firstByteSym, int* lengthSum, int* results, int n, int outSize) {
int thid = (blockIdx.x * blockDim.x) + threadIdx.x;
if (thid >= outSize) return;
int symI = firstByteSym[thid];
if (symI != 0) symI --;
int offsetDelta = thid * 8;
//printf("thid: %d, sym: %d\n", thid, symI);
int result = 0;
while (symI < n) {
int shift = (symI == 0 ? 0 : lengthSum[symI-1]) - offsetDelta;
//printf("thid: %d | symI: %d, shift: %d\n", thid, symI, shift);
if (shift > 8) break;
int code = symbols[data[symI]];
if (shift >= 0)
result |= code << shift;
else
result |= code >> (-shift);
symI ++;
}
results[thid] = result;
}
int main(){
hipSetDevice(1);
int symbolsData[] = {0b1, 0b01, 0b001, 0b000};
int sizesData[] = {1, 2, 3, 3};
const int symN = 4;
const int dataN = 10000;
thrust::device_vector<int> data;
for (int i=0; i < dataN; i ++) data.push_back(i % symN);
thrust::device_vector<int> symbols (symbolsData, symbolsData + symN);
thrust::device_vector<int> symbolSizes (sizesData, sizesData + symN);
thrust::device_vector<int> lengthSum (dataN);
computeLengths<<<(dataN + 1023) / 1024, 1024>>>
(toIntPtr(data), toIntPtr(lengthSum),
toIntPtr(symbolSizes), dataN);
thrust::inclusive_scan(lengthSum.begin(), lengthSum.end(), lengthSum.begin());
//for (int i : lengthSum) printf("l=%d\n", i);
int outSize = (lengthSum.back() / 8 + 1);
thrust::device_vector<int> firstByteSym;
firstByteSym.resize(outSize, 0);
computeFirstByteSym<<<(outSize + 1023) / 1024, 1024>>>
(toIntPtr(lengthSum),
toIntPtr(firstByteSym),
dataN, outSize);
//for (int i : firstByteSym) printf("s=%d\n", i);
thrust::device_vector<int> result;
result.resize(outSize, 0);
computeResult<<<(outSize + 1023) / 1024, 1024>>>
(toIntPtr(symbols),
toIntPtr(data),
toIntPtr(firstByteSym),
toIntPtr(lengthSum),
toIntPtr(result),
dataN, outSize);
//for (int i : result) printf("result=%d\n", i);
hipDeviceSynchronize ();
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <stdbool.h>
#include <time.h>
#include <cuda.h>
void initialize(int *menacc, int *womenacc, int *menpre, int *womenlock, int n) {
int i;
for(i=0; i<=n; i++) {
menacc[i] = -1;
womenacc[i] = -1;
menpre[i] = 1;
womenlock[i] = 0;
}
}
__global__ void stable_matching(int n, int *d_men, int *d_women,
int *d_menacc, int *d_womenacc, int *d_menpre, int *d_matched, int *d_matched_, int *d_womenlock) {
int j = threadIdx.x + 1, idx, ct=0;
while(1) {
__syncthreads();
if(*d_matched_ == 0) break;
if(*d_matched_ == 1 && j <= n && d_menacc[j] == -1) {
idx = d_men[j*(n+1) + d_menpre[j]];
*d_matched = 0;
// locking mechanism
bool isSet = false;
do {
if(isSet = atomicCAS(&d_womenlock[idx], 0, 1) == 0) {
if(d_womenacc[idx] == -1) {
d_womenacc[idx] = j;
d_menacc[j] = idx;
}
else if(d_women[idx*(n+1) + d_womenacc[idx]] > d_women[idx*(n+1) + j]) {
d_menacc[d_womenacc[idx]] = -1;
d_menacc[j] = idx;
d_womenacc[idx] = j;
}
}
if(isSet) {
atomicCAS(&d_womenlock[idx], 1, 0);
}
} while(!isSet);
d_menpre[j]++;
}
__syncthreads();
if(j == 1 && *d_matched == 1) {
*d_matched_ = 0;
}
else if(j == 1 && *d_matched == 0) {
*d_matched = 1;
}
ct++;
}
__syncthreads();
}
int main()
{
int n,i,j,k;
int *d_matched, *d_matched_;
int *men, *women;
int *menacc, *womenacc, *menpre, *womenlock;
int *d_men, *d_women;
int *d_menacc, *d_womenacc, *d_menpre, *d_womenlock;
clock_t beg, end;
double time_taken;
scanf("%d",&n);
men = (int *) malloc((n+1)*(n+1)*sizeof(int));
women = (int *) malloc((n+1)*(n+1)*sizeof(int));
menacc = (int *) malloc((n+1)*sizeof(int));
womenacc = (int *) malloc((n+1)*sizeof(int));
womenlock = (int *) malloc((n+1)*sizeof(int));
menpre = (int *) malloc((n+1)*sizeof(int));
cudaMalloc(&d_men, (n+1)*(n+1)*sizeof(int));
cudaMalloc(&d_women, (n+1)*(n+1)*sizeof(int));
cudaMalloc(&d_menacc, (n+1)*sizeof(int));
cudaMalloc(&d_womenacc, (n+1)*sizeof(int));
cudaMalloc(&d_womenlock, (n+1)*sizeof(int));
cudaMalloc(&d_menpre, (n+1)*sizeof(int));
cudaMalloc(&d_matched, sizeof(int));
cudaMalloc(&d_matched_, sizeof(int));
initialize(menacc, womenacc, menpre, womenlock, n);
beg = clock();
for(i=1; i<=n; i++) {
for(j=0; j<=n; j++) {
scanf("%d", &men[i*(n+1) + j]);
}
}
for(i=1; i<=n; i++) {
for(j=0; j<=n; j++) {
scanf("%d", &k);
women[i*(n+1) + k] = j;
}
}
end = clock();
time_taken = ((double)(end-beg) * 1000000)/CLOCKS_PER_SEC;
printf("read time : %f us, ", time_taken);
cudaMemcpy(d_men, men, (n+1)*(n+1)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_women, women, (n+1)*(n+1)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_menacc, menacc, (n+1)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_womenlock, womenlock, (n+1)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_womenacc, womenacc, (n+1)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_menpre, menpre, (n+1)*sizeof(int), cudaMemcpyHostToDevice);
int matched = 1;
cudaMemcpy(d_matched, &matched, sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_matched_, &matched, sizeof(int), cudaMemcpyHostToDevice);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float milliseconds = 0;
cudaEventRecord(start,0);
stable_matching <<< 1, n >>>(n, d_men, d_women, d_menacc, d_womenacc, d_menpre, d_matched, d_matched_, d_womenlock);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&milliseconds, start, stop);
cudaMemcpy(menacc, d_menacc, (n+1)*sizeof(int), cudaMemcpyDeviceToHost);
printf("compute time : %f us\n", milliseconds*1000);
for(j=1;j<=n;j++)
printf("%d %d\n", j, menacc[j]);
free(men); free(women);
free(menacc); free(womenacc); free(menpre); free(womenlock);
cudaFree(&d_men); cudaFree(&d_women); cudaFree(&d_matched); cudaFree(&d_matched_);
cudaFree(&d_menacc); cudaFree(&d_womenacc); cudaFree(&d_menpre); cudaFree(&d_womenlock);
return 0;
} | code for sm_80
Function : _Z15stable_matchingiPiS_S_S_S_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0020*/ IMAD.MOV.U32 R18, RZ, RZ, c[0x0][0x198] ; /* 0x00006600ff127624 */
/* 0x000fe400078e00ff */
/*0030*/ IMAD.MOV.U32 R19, RZ, RZ, c[0x0][0x19c] ; /* 0x00006700ff137624 */
/* 0x000fc600078e00ff */
/*0040*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0050*/ LDG.E R2, [R18.64] ; /* 0x0000000612027981 */
/* 0x000ea4000c1e1900 */
/*0060*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x004fda0003f05270 */
/*0070*/ @!P0 BRA 0x600 ; /* 0x0000058000008947 */
/* 0x000fea0003800000 */
/*0080*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0090*/ ULDC UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe20000000800 */
/*00a0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*00b0*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*00c0*/ IMAD.MOV.U32 R8, RZ, RZ, R2 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0002 */
/*00d0*/ IADD3 R6, R0.reuse, 0x1, RZ ; /* 0x0000000100067810 */
/* 0x041fe20007ffe0ff */
/*00e0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fc800078e0205 */
/*00f0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x188] ; /* 0x0000620000047625 */
/* 0x000fc800078e0205 */
/*0100*/ IMAD R7, R6, UR4, RZ ; /* 0x0000000406077c24 */
/* 0x000fe4000f8e02ff */
/*0110*/ ISETP.NE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fc80003f05270 */
/*0120*/ ISETP.GT.OR P0, PT, R6, c[0x0][0x160], P0 ; /* 0x0000580006007a0c */
/* 0x000fda0000704670 */
/*0130*/ @P0 BRA 0x4b0 ; /* 0x0000037000000947 */
/* 0x020fea0003800000 */
/*0140*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040602087981 */
/* 0x000ea4000c1e1900 */
/*0150*/ ISETP.NE.AND P0, PT, R8, -0x1, PT ; /* 0xffffffff0800780c */
/* 0x004fda0003f05270 */
/*0160*/ @P0 BRA 0x4b0 ; /* 0x0000034000000947 */
/* 0x000fea0003800000 */
/*0170*/ LDG.E R8, [R4.64+0x4] ; /* 0x0000040604087981 */
/* 0x000ea2000c1e1900 */
/*0180*/ HFMA2.MMA R12, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0c7435 */
/* 0x000fe200000001ff */
/*0190*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x190] ; /* 0x00006400ff0e7624 */
/* 0x000fe400078e00ff */
/*01a0*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x194] ; /* 0x00006500ff0f7624 */
/* 0x000fe400078e00ff */
/*01b0*/ IMAD.IADD R11, R7, 0x1, R8 ; /* 0x00000001070b7824 */
/* 0x004fca00078e0208 */
/*01c0*/ IMAD.WIDE R10, R11, R12, c[0x0][0x168] ; /* 0x00005a000b0a7625 */
/* 0x000fca00078e020c */
/*01d0*/ LDG.E R13, [R10.64] ; /* 0x000000060a0d7981 */
/* 0x000ea2000c1e1900 */
/*01e0*/ BSSY B0, 0x290 ; /* 0x000000a000007945 */
/* 0x000fe20003800000 */
/*01f0*/ IMAD.MOV.U32 R21, RZ, RZ, 0x1 ; /* 0x00000001ff157424 */
/* 0x000fe400078e00ff */
/*0200*/ STG.E [R14.64], RZ ; /* 0x000000ff0e007986 */
/* 0x0001e2000c101906 */
/*0210*/ SHF.R.S32.HI R16, RZ, 0x1f, R13 ; /* 0x0000001fff107819 */
/* 0x004fe2000001140d */
/*0220*/ IMAD.WIDE R8, R13, R12, c[0x0][0x1a0] ; /* 0x000068000d087625 */
/* 0x001fc800078e020c */
/*0230*/ MOV R20, RZ ; /* 0x000000ff00147202 */
/* 0x000fe20000000f00 */
/*0240*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe80003800000 */
/*0250*/ ATOMG.E.CAS.STRONG.GPU PT, R10, [R8], R20, R21 ; /* 0x00000014080a73a9 */
/* 0x000ea400001ee115 */
/*0260*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x004fda0003f05270 */
/*0270*/ @P0 BRA 0x230 ; /* 0xffffffb000000947 */
/* 0x000fea000383ffff */
/*0280*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0290*/ LEA R10, P0, R13, c[0x0][0x180], 0x2 ; /* 0x000060000d0a7a11 */
/* 0x000fc800078010ff */
/*02a0*/ LEA.HI.X R11, R13, c[0x0][0x184], R16, 0x2, P0 ; /* 0x000061000d0b7a11 */
/* 0x000fca00000f1410 */
/*02b0*/ LDG.E R20, [R10.64] ; /* 0x000000060a147981 */
/* 0x000ea2000c1e1900 */
/*02c0*/ BSSY B0, 0x450 ; /* 0x0000018000007945 */
/* 0x000fe20003800000 */
/*02d0*/ ISETP.NE.U32.AND P0, PT, R20, -0x1, PT ; /* 0xffffffff1400780c */
/* 0x004fe40003f05070 */
/*02e0*/ SHF.R.S32.HI R21, RZ, 0x1f, R20 ; /* 0x0000001fff157819 */
/* 0x000fc80000011414 */
/*02f0*/ ISETP.NE.AND.EX P0, PT, R21, -0x1, PT, P0 ; /* 0xffffffff1500780c */
/* 0x000fda0003f05300 */
/*0300*/ @!P0 BRA 0x410 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0310*/ IMAD R15, R13.reuse, UR4, R20 ; /* 0x000000040d0f7c24 */
/* 0x040fe4000f8e0214 */
/*0320*/ IMAD R17, R13, UR4, R6 ; /* 0x000000040d117c24 */
/* 0x000fe4000f8e0206 */
/*0330*/ IMAD.WIDE R14, R15, R12, c[0x0][0x170] ; /* 0x00005c000f0e7625 */
/* 0x000fc800078e020c */
/*0340*/ IMAD.WIDE R16, R17, R12, c[0x0][0x170] ; /* 0x00005c0011107625 */
/* 0x000fe400078e020c */
/*0350*/ LDG.E R15, [R14.64] ; /* 0x000000060e0f7981 */
/* 0x000ea8000c1e1900 */
/*0360*/ LDG.E R16, [R16.64] ; /* 0x0000000610107981 */
/* 0x000ea4000c1e1900 */
/*0370*/ ISETP.GT.AND P0, PT, R15, R16, PT ; /* 0x000000100f00720c */
/* 0x004fda0003f04270 */
/*0380*/ @!P0 BRA 0x440 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0390*/ LEA R14, P0, R20, c[0x0][0x178], 0x2 ; /* 0x00005e00140e7a11 */
/* 0x000fe200078010ff */
/*03a0*/ IMAD.MOV.U32 R17, RZ, RZ, -0x1 ; /* 0xffffffffff117424 */
/* 0x000fe200078e00ff */
/*03b0*/ IADD3 R6, R0, 0x1, RZ ; /* 0x0000000100067810 */
/* 0x000fe40007ffe0ff */
/*03c0*/ LEA.HI.X R15, R20, c[0x0][0x17c], R21, 0x2, P0 ; /* 0x00005f00140f7a11 */
/* 0x000fca00000f1415 */
/*03d0*/ STG.E [R14.64], R17 ; /* 0x000000110e007986 */
/* 0x0001e8000c101906 */
/*03e0*/ STG.E [R2.64+0x4], R13 ; /* 0x0000040d02007986 */
/* 0x0001e8000c101906 */
/*03f0*/ STG.E [R10.64], R6 ; /* 0x000000060a007986 */
/* 0x0001e2000c101906 */
/*0400*/ BRA 0x440 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0410*/ IADD3 R6, R0, 0x1, RZ ; /* 0x0000000100067810 */
/* 0x000fca0007ffe0ff */
/*0420*/ STG.E [R10.64], R6 ; /* 0x000000060a007986 */
/* 0x0001e8000c101906 */
/*0430*/ STG.E [R2.64+0x4], R13 ; /* 0x0000040d02007986 */
/* 0x0001e4000c101906 */
/*0440*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0450*/ IMAD.MOV.U32 R12, RZ, RZ, 0x1 ; /* 0x00000001ff0c7424 */
/* 0x000fe400078e00ff */
/*0460*/ IMAD.MOV.U32 R13, RZ, RZ, RZ ; /* 0x000000ffff0d7224 */
/* 0x001fca00078e00ff */
/*0470*/ ATOMG.E.CAS.STRONG.GPU PT, RZ, [R8], R12, R13 ; /* 0x0000000c08ff73a9 */
/* 0x00016800001ee10d */
/*0480*/ LDG.E R10, [R4.64+0x4] ; /* 0x00000406040a7981 */
/* 0x000ea4000c1e1900 */
/*0490*/ IADD3 R11, R10, 0x1, RZ ; /* 0x000000010a0b7810 */
/* 0x004fca0007ffe0ff */
/*04a0*/ STG.E [R4.64+0x4], R11 ; /* 0x0000040b04007986 */
/* 0x0001e4000c101906 */
/*04b0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*04c0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*04d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04e0*/ BSSY B0, 0x5c0 ; /* 0x000000d000007945 */
/* 0x000fea0003800000 */
/*04f0*/ @P0 BRA 0x5b0 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0500*/ MOV R8, c[0x0][0x190] ; /* 0x0000640000087a02 */
/* 0x001fe20000000f00 */
/*0510*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x194] ; /* 0x00006500ff097624 */
/* 0x000fca00078e00ff */
/*0520*/ LDG.E R10, [R8.64] ; /* 0x00000006080a7981 */
/* 0x000ea4000c1e1900 */
/*0530*/ ISETP.NE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x004fda0003f05270 */
/*0540*/ @!P0 BRA 0x5a0 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0550*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f05270 */
/*0560*/ @P0 BRA 0x5b0 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0570*/ IMAD.MOV.U32 R11, RZ, RZ, 0x1 ; /* 0x00000001ff0b7424 */
/* 0x000fca00078e00ff */
/*0580*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x0001e2000c101906 */
/*0590*/ BRA 0x5b0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*05a0*/ STG.E [R18.64], RZ ; /* 0x000000ff12007986 */
/* 0x0001e4000c101906 */
/*05b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*05d0*/ LDG.E R8, [R18.64] ; /* 0x0000000612087981 */
/* 0x001ea4000c1e1900 */
/*05e0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x004fda0003f05270 */
/*05f0*/ @P0 BRA 0x110 ; /* 0xfffffb1000000947 */
/* 0x000fea000383ffff */
/*0600*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0610*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0620*/ BRA 0x620; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <stdbool.h>
#include <time.h>
#include <cuda.h>
void initialize(int *menacc, int *womenacc, int *menpre, int *womenlock, int n) {
int i;
for(i=0; i<=n; i++) {
menacc[i] = -1;
womenacc[i] = -1;
menpre[i] = 1;
womenlock[i] = 0;
}
}
__global__ void stable_matching(int n, int *d_men, int *d_women,
int *d_menacc, int *d_womenacc, int *d_menpre, int *d_matched, int *d_matched_, int *d_womenlock) {
int j = threadIdx.x + 1, idx, ct=0;
while(1) {
__syncthreads();
if(*d_matched_ == 0) break;
if(*d_matched_ == 1 && j <= n && d_menacc[j] == -1) {
idx = d_men[j*(n+1) + d_menpre[j]];
*d_matched = 0;
// locking mechanism
bool isSet = false;
do {
if(isSet = atomicCAS(&d_womenlock[idx], 0, 1) == 0) {
if(d_womenacc[idx] == -1) {
d_womenacc[idx] = j;
d_menacc[j] = idx;
}
else if(d_women[idx*(n+1) + d_womenacc[idx]] > d_women[idx*(n+1) + j]) {
d_menacc[d_womenacc[idx]] = -1;
d_menacc[j] = idx;
d_womenacc[idx] = j;
}
}
if(isSet) {
atomicCAS(&d_womenlock[idx], 1, 0);
}
} while(!isSet);
d_menpre[j]++;
}
__syncthreads();
if(j == 1 && *d_matched == 1) {
*d_matched_ = 0;
}
else if(j == 1 && *d_matched == 0) {
*d_matched = 1;
}
ct++;
}
__syncthreads();
}
int main()
{
int n,i,j,k;
int *d_matched, *d_matched_;
int *men, *women;
int *menacc, *womenacc, *menpre, *womenlock;
int *d_men, *d_women;
int *d_menacc, *d_womenacc, *d_menpre, *d_womenlock;
clock_t beg, end;
double time_taken;
scanf("%d",&n);
men = (int *) malloc((n+1)*(n+1)*sizeof(int));
women = (int *) malloc((n+1)*(n+1)*sizeof(int));
menacc = (int *) malloc((n+1)*sizeof(int));
womenacc = (int *) malloc((n+1)*sizeof(int));
womenlock = (int *) malloc((n+1)*sizeof(int));
menpre = (int *) malloc((n+1)*sizeof(int));
cudaMalloc(&d_men, (n+1)*(n+1)*sizeof(int));
cudaMalloc(&d_women, (n+1)*(n+1)*sizeof(int));
cudaMalloc(&d_menacc, (n+1)*sizeof(int));
cudaMalloc(&d_womenacc, (n+1)*sizeof(int));
cudaMalloc(&d_womenlock, (n+1)*sizeof(int));
cudaMalloc(&d_menpre, (n+1)*sizeof(int));
cudaMalloc(&d_matched, sizeof(int));
cudaMalloc(&d_matched_, sizeof(int));
initialize(menacc, womenacc, menpre, womenlock, n);
beg = clock();
for(i=1; i<=n; i++) {
for(j=0; j<=n; j++) {
scanf("%d", &men[i*(n+1) + j]);
}
}
for(i=1; i<=n; i++) {
for(j=0; j<=n; j++) {
scanf("%d", &k);
women[i*(n+1) + k] = j;
}
}
end = clock();
time_taken = ((double)(end-beg) * 1000000)/CLOCKS_PER_SEC;
printf("read time : %f us, ", time_taken);
cudaMemcpy(d_men, men, (n+1)*(n+1)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_women, women, (n+1)*(n+1)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_menacc, menacc, (n+1)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_womenlock, womenlock, (n+1)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_womenacc, womenacc, (n+1)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_menpre, menpre, (n+1)*sizeof(int), cudaMemcpyHostToDevice);
int matched = 1;
cudaMemcpy(d_matched, &matched, sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_matched_, &matched, sizeof(int), cudaMemcpyHostToDevice);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float milliseconds = 0;
cudaEventRecord(start,0);
stable_matching <<< 1, n >>>(n, d_men, d_women, d_menacc, d_womenacc, d_menpre, d_matched, d_matched_, d_womenlock);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&milliseconds, start, stop);
cudaMemcpy(menacc, d_menacc, (n+1)*sizeof(int), cudaMemcpyDeviceToHost);
printf("compute time : %f us\n", milliseconds*1000);
for(j=1;j<=n;j++)
printf("%d %d\n", j, menacc[j]);
free(men); free(women);
free(menacc); free(womenacc); free(menpre); free(womenlock);
cudaFree(&d_men); cudaFree(&d_women); cudaFree(&d_matched); cudaFree(&d_matched_);
cudaFree(&d_menacc); cudaFree(&d_womenacc); cudaFree(&d_menpre); cudaFree(&d_womenlock);
return 0;
} | .file "tmpxft_00112b3b_00000000-6_parallel_final.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10initializePiS_S_S_i
.type _Z10initializePiS_S_S_i, @function
_Z10initializePiS_S_S_i:
.LFB2057:
.cfi_startproc
endbr64
testl %r8d, %r8d
js .L3
leal 1(%r8), %r8d
salq $2, %r8
movl $0, %eax
.L5:
movl $-1, (%rdi,%rax)
movl $-1, (%rsi,%rax)
movl $1, (%rdx,%rax)
movl $0, (%rcx,%rax)
addq $4, %rax
cmpq %r8, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z10initializePiS_S_S_i, .-_Z10initializePiS_S_S_i
.globl _Z50__device_stub__Z15stable_matchingiPiS_S_S_S_S_S_S_iPiS_S_S_S_S_S_S_
.type _Z50__device_stub__Z15stable_matchingiPiS_S_S_S_S_S_S_iPiS_S_S_S_S_S_S_, @function
_Z50__device_stub__Z15stable_matchingiPiS_S_S_S_S_S_S_iPiS_S_S_S_S_S_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movl %edi, 76(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
movq %r8, 40(%rsp)
movq %r9, 32(%rsp)
movq 240(%rsp), %rax
movq %rax, 24(%rsp)
movq 248(%rsp), %rax
movq %rax, 16(%rsp)
movq 256(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 76(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 24(%rsp), %rax
movq %rax, 192(%rsp)
leaq 16(%rsp), %rax
movq %rax, 200(%rsp)
leaq 8(%rsp), %rax
movq %rax, 208(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 248
pushq 88(%rsp)
.cfi_def_cfa_offset 256
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z15stable_matchingiPiS_S_S_S_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z50__device_stub__Z15stable_matchingiPiS_S_S_S_S_S_S_iPiS_S_S_S_S_S_S_, .-_Z50__device_stub__Z15stable_matchingiPiS_S_S_S_S_S_S_iPiS_S_S_S_S_S_S_
.globl _Z15stable_matchingiPiS_S_S_S_S_S_S_
.type _Z15stable_matchingiPiS_S_S_S_S_S_S_, @function
_Z15stable_matchingiPiS_S_S_S_S_S_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z50__device_stub__Z15stable_matchingiPiS_S_S_S_S_S_S_iPiS_S_S_S_S_S_S_
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z15stable_matchingiPiS_S_S_S_S_S_S_, .-_Z15stable_matchingiPiS_S_S_S_S_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d"
.LC2:
.string "read time : %f us, "
.LC5:
.string "compute time : %f us\n"
.LC6:
.string "%d %d\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $168, %rsp
.cfi_def_cfa_offset 224
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rsi
leaq .LC0(%rip), %rdi
call __isoc23_scanf@PLT
movl 32(%rsp), %eax
leal 1(%rax), %ebp
movl %ebp, %ebx
imull %ebp, %ebx
movslq %ebx, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movslq %ebp, %rbp
salq $2, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbp, %rdi
call malloc@PLT
movq %rax, (%rsp)
movq %rbp, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r15
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl 32(%rsp), %edi
leal 1(%rdi), %eax
imull %eax, %eax
movslq %eax, %rsi
salq $2, %rsi
leaq 72(%rsp), %rdi
call cudaMalloc@PLT
movl 32(%rsp), %edi
leal 1(%rdi), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 80(%rsp), %rdi
call cudaMalloc@PLT
movl 32(%rsp), %edi
leal 1(%rdi), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 88(%rsp), %rdi
call cudaMalloc@PLT
movl 32(%rsp), %edi
leal 1(%rdi), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 104(%rsp), %rdi
call cudaMalloc@PLT
movl 32(%rsp), %edi
leal 1(%rdi), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 96(%rsp), %rdi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl 32(%rsp), %r8d
movq 8(%rsp), %rcx
movq %r15, %rdx
movq (%rsp), %rsi
movq %r14, %rdi
call _Z10initializePiS_S_S_i
call clock@PLT
movq %rax, 24(%rsp)
movl $1, %ebp
leaq .LC0(%rip), %r15
cmpl $0, 32(%rsp)
jg .L16
.L17:
call clock@PLT
movq 24(%rsp), %rcx
subq %rcx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
movsd .LC1(%rip), %xmm1
mulsd %xmm1, %xmm0
divsd %xmm1, %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl 32(%rsp), %eax
addl $1, %eax
imull %eax, %eax
movslq %eax, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r13, %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl 32(%rsp), %eax
addl $1, %eax
imull %eax, %eax
movslq %eax, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r12, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl 32(%rsp), %eax
leal 1(%rax), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r14, %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl 32(%rsp), %eax
leal 1(%rax), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq 8(%rsp), %rsi
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
movl 32(%rsp), %eax
leal 1(%rax), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq (%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl 32(%rsp), %eax
leal 1(%rax), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq 16(%rsp), %rsi
movq 96(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 40(%rsp)
leaq 40(%rsp), %rbx
movl $1, %ecx
movl $4, %edx
movq %rbx, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4, %edx
movq %rbx, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
leaq 112(%rsp), %rdi
call cudaEventCreate@PLT
leaq 120(%rsp), %rdi
call cudaEventCreate@PLT
movl $0x00000000, 44(%rsp)
movl $0, %esi
movq 112(%rsp), %rdi
call cudaEventRecord@PLT
movl 32(%rsp), %eax
movl %eax, 140(%rsp)
movl $1, 144(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 140(%rsp), %rdx
movl $1, %ecx
movq 128(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L24:
movl $0, %esi
movq 120(%rsp), %rdi
call cudaEventRecord@PLT
movq 120(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 44(%rsp), %rdi
movq 120(%rsp), %rdx
movq 112(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl 32(%rsp), %eax
leal 1(%rax), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $2, %ecx
movq 80(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movss .LC4(%rip), %xmm0
mulss 44(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
cmpl $0, 32(%rsp)
jle .L25
movl $1, %ebx
leaq .LC6(%rip), %rbp
.L26:
movl (%r14,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpl %ebx, 32(%rsp)
jge .L26
.L25:
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq (%rsp), %rdi
call free@PLT
movq 16(%rsp), %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
leaq 64(%rsp), %rdi
call cudaFree@PLT
leaq 72(%rsp), %rdi
call cudaFree@PLT
leaq 48(%rsp), %rdi
call cudaFree@PLT
leaq 56(%rsp), %rdi
call cudaFree@PLT
leaq 80(%rsp), %rdi
call cudaFree@PLT
leaq 88(%rsp), %rdi
call cudaFree@PLT
leaq 96(%rsp), %rdi
call cudaFree@PLT
leaq 104(%rsp), %rdi
call cudaFree@PLT
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L40
movl $0, %eax
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
addl $1, %eax
imull %ebp, %eax
addl %ebx, %eax
cltq
leaq 0(%r13,%rax,4), %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
movl 32(%rsp), %eax
cmpl %ebx, %eax
jge .L18
.L20:
addl $1, %ebp
movl 32(%rsp), %eax
cmpl %ebp, %eax
jl .L19
.L16:
movl 32(%rsp), %eax
movl $0, %ebx
testl %eax, %eax
jns .L18
jmp .L20
.L19:
testl %eax, %eax
jle .L17
movl $1, %ebp
leaq .LC0(%rip), %r15
jmp .L21
.L22:
leaq 36(%rsp), %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 32(%rsp), %edx
leal 1(%rdx), %eax
imull %ebp, %eax
addl 36(%rsp), %eax
cltq
movl %ebx, (%r12,%rax,4)
addl $1, %ebx
cmpl %ebx, %edx
jge .L22
.L23:
addl $1, %ebp
cmpl %ebp, 32(%rsp)
jl .L17
.L21:
movl $0, %ebx
cmpl $0, 32(%rsp)
jns .L22
jmp .L23
.L39:
subq $8, %rsp
.cfi_def_cfa_offset 232
pushq 112(%rsp)
.cfi_def_cfa_offset 240
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
movq 128(%rsp), %r9
movq 120(%rsp), %r8
movq 112(%rsp), %rcx
movq 104(%rsp), %rdx
movq 96(%rsp), %rsi
movl 64(%rsp), %edi
call _Z50__device_stub__Z15stable_matchingiPiS_S_S_S_S_S_S_iPiS_S_S_S_S_S_S_
addq $32, %rsp
.cfi_def_cfa_offset 224
jmp .L24
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "_Z15stable_matchingiPiS_S_S_S_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z15stable_matchingiPiS_S_S_S_S_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1093567616
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <stdbool.h>
#include <time.h>
#include <cuda.h>
void initialize(int *menacc, int *womenacc, int *menpre, int *womenlock, int n) {
int i;
for(i=0; i<=n; i++) {
menacc[i] = -1;
womenacc[i] = -1;
menpre[i] = 1;
womenlock[i] = 0;
}
}
__global__ void stable_matching(int n, int *d_men, int *d_women,
int *d_menacc, int *d_womenacc, int *d_menpre, int *d_matched, int *d_matched_, int *d_womenlock) {
int j = threadIdx.x + 1, idx, ct=0;
while(1) {
__syncthreads();
if(*d_matched_ == 0) break;
if(*d_matched_ == 1 && j <= n && d_menacc[j] == -1) {
idx = d_men[j*(n+1) + d_menpre[j]];
*d_matched = 0;
// locking mechanism
bool isSet = false;
do {
if(isSet = atomicCAS(&d_womenlock[idx], 0, 1) == 0) {
if(d_womenacc[idx] == -1) {
d_womenacc[idx] = j;
d_menacc[j] = idx;
}
else if(d_women[idx*(n+1) + d_womenacc[idx]] > d_women[idx*(n+1) + j]) {
d_menacc[d_womenacc[idx]] = -1;
d_menacc[j] = idx;
d_womenacc[idx] = j;
}
}
if(isSet) {
atomicCAS(&d_womenlock[idx], 1, 0);
}
} while(!isSet);
d_menpre[j]++;
}
__syncthreads();
if(j == 1 && *d_matched == 1) {
*d_matched_ = 0;
}
else if(j == 1 && *d_matched == 0) {
*d_matched = 1;
}
ct++;
}
__syncthreads();
}
int main()
{
int n,i,j,k;
int *d_matched, *d_matched_;
int *men, *women;
int *menacc, *womenacc, *menpre, *womenlock;
int *d_men, *d_women;
int *d_menacc, *d_womenacc, *d_menpre, *d_womenlock;
clock_t beg, end;
double time_taken;
scanf("%d",&n);
men = (int *) malloc((n+1)*(n+1)*sizeof(int));
women = (int *) malloc((n+1)*(n+1)*sizeof(int));
menacc = (int *) malloc((n+1)*sizeof(int));
womenacc = (int *) malloc((n+1)*sizeof(int));
womenlock = (int *) malloc((n+1)*sizeof(int));
menpre = (int *) malloc((n+1)*sizeof(int));
cudaMalloc(&d_men, (n+1)*(n+1)*sizeof(int));
cudaMalloc(&d_women, (n+1)*(n+1)*sizeof(int));
cudaMalloc(&d_menacc, (n+1)*sizeof(int));
cudaMalloc(&d_womenacc, (n+1)*sizeof(int));
cudaMalloc(&d_womenlock, (n+1)*sizeof(int));
cudaMalloc(&d_menpre, (n+1)*sizeof(int));
cudaMalloc(&d_matched, sizeof(int));
cudaMalloc(&d_matched_, sizeof(int));
initialize(menacc, womenacc, menpre, womenlock, n);
beg = clock();
for(i=1; i<=n; i++) {
for(j=0; j<=n; j++) {
scanf("%d", &men[i*(n+1) + j]);
}
}
for(i=1; i<=n; i++) {
for(j=0; j<=n; j++) {
scanf("%d", &k);
women[i*(n+1) + k] = j;
}
}
end = clock();
time_taken = ((double)(end-beg) * 1000000)/CLOCKS_PER_SEC;
printf("read time : %f us, ", time_taken);
cudaMemcpy(d_men, men, (n+1)*(n+1)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_women, women, (n+1)*(n+1)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_menacc, menacc, (n+1)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_womenlock, womenlock, (n+1)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_womenacc, womenacc, (n+1)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_menpre, menpre, (n+1)*sizeof(int), cudaMemcpyHostToDevice);
int matched = 1;
cudaMemcpy(d_matched, &matched, sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_matched_, &matched, sizeof(int), cudaMemcpyHostToDevice);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float milliseconds = 0;
cudaEventRecord(start,0);
stable_matching <<< 1, n >>>(n, d_men, d_women, d_menacc, d_womenacc, d_menpre, d_matched, d_matched_, d_womenlock);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&milliseconds, start, stop);
cudaMemcpy(menacc, d_menacc, (n+1)*sizeof(int), cudaMemcpyDeviceToHost);
printf("compute time : %f us\n", milliseconds*1000);
for(j=1;j<=n;j++)
printf("%d %d\n", j, menacc[j]);
free(men); free(women);
free(menacc); free(womenacc); free(menpre); free(womenlock);
cudaFree(&d_men); cudaFree(&d_women); cudaFree(&d_matched); cudaFree(&d_matched_);
cudaFree(&d_menacc); cudaFree(&d_womenacc); cudaFree(&d_menpre); cudaFree(&d_womenlock);
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <stdbool.h>
#include <time.h>
#include <hip/hip_runtime.h>
void initialize(int *menacc, int *womenacc, int *menpre, int *womenlock, int n) {
int i;
for(i=0; i<=n; i++) {
menacc[i] = -1;
womenacc[i] = -1;
menpre[i] = 1;
womenlock[i] = 0;
}
}
__global__ void stable_matching(int n, int *d_men, int *d_women,
int *d_menacc, int *d_womenacc, int *d_menpre, int *d_matched, int *d_matched_, int *d_womenlock) {
int j = threadIdx.x + 1, idx, ct=0;
while(1) {
__syncthreads();
if(*d_matched_ == 0) break;
if(*d_matched_ == 1 && j <= n && d_menacc[j] == -1) {
idx = d_men[j*(n+1) + d_menpre[j]];
*d_matched = 0;
// locking mechanism
bool isSet = false;
do {
if(isSet = atomicCAS(&d_womenlock[idx], 0, 1) == 0) {
if(d_womenacc[idx] == -1) {
d_womenacc[idx] = j;
d_menacc[j] = idx;
}
else if(d_women[idx*(n+1) + d_womenacc[idx]] > d_women[idx*(n+1) + j]) {
d_menacc[d_womenacc[idx]] = -1;
d_menacc[j] = idx;
d_womenacc[idx] = j;
}
}
if(isSet) {
atomicCAS(&d_womenlock[idx], 1, 0);
}
} while(!isSet);
d_menpre[j]++;
}
__syncthreads();
if(j == 1 && *d_matched == 1) {
*d_matched_ = 0;
}
else if(j == 1 && *d_matched == 0) {
*d_matched = 1;
}
ct++;
}
__syncthreads();
}
int main()
{
int n,i,j,k;
int *d_matched, *d_matched_;
int *men, *women;
int *menacc, *womenacc, *menpre, *womenlock;
int *d_men, *d_women;
int *d_menacc, *d_womenacc, *d_menpre, *d_womenlock;
clock_t beg, end;
double time_taken;
scanf("%d",&n);
men = (int *) malloc((n+1)*(n+1)*sizeof(int));
women = (int *) malloc((n+1)*(n+1)*sizeof(int));
menacc = (int *) malloc((n+1)*sizeof(int));
womenacc = (int *) malloc((n+1)*sizeof(int));
womenlock = (int *) malloc((n+1)*sizeof(int));
menpre = (int *) malloc((n+1)*sizeof(int));
hipMalloc(&d_men, (n+1)*(n+1)*sizeof(int));
hipMalloc(&d_women, (n+1)*(n+1)*sizeof(int));
hipMalloc(&d_menacc, (n+1)*sizeof(int));
hipMalloc(&d_womenacc, (n+1)*sizeof(int));
hipMalloc(&d_womenlock, (n+1)*sizeof(int));
hipMalloc(&d_menpre, (n+1)*sizeof(int));
hipMalloc(&d_matched, sizeof(int));
hipMalloc(&d_matched_, sizeof(int));
initialize(menacc, womenacc, menpre, womenlock, n);
beg = clock();
for(i=1; i<=n; i++) {
for(j=0; j<=n; j++) {
scanf("%d", &men[i*(n+1) + j]);
}
}
for(i=1; i<=n; i++) {
for(j=0; j<=n; j++) {
scanf("%d", &k);
women[i*(n+1) + k] = j;
}
}
end = clock();
time_taken = ((double)(end-beg) * 1000000)/CLOCKS_PER_SEC;
printf("read time : %f us, ", time_taken);
hipMemcpy(d_men, men, (n+1)*(n+1)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_women, women, (n+1)*(n+1)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_menacc, menacc, (n+1)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_womenlock, womenlock, (n+1)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_womenacc, womenacc, (n+1)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_menpre, menpre, (n+1)*sizeof(int), hipMemcpyHostToDevice);
int matched = 1;
hipMemcpy(d_matched, &matched, sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_matched_, &matched, sizeof(int), hipMemcpyHostToDevice);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float milliseconds = 0;
hipEventRecord(start,0);
stable_matching <<< 1, n >>>(n, d_men, d_women, d_menacc, d_womenacc, d_menpre, d_matched, d_matched_, d_womenlock);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&milliseconds, start, stop);
hipMemcpy(menacc, d_menacc, (n+1)*sizeof(int), hipMemcpyDeviceToHost);
printf("compute time : %f us\n", milliseconds*1000);
for(j=1;j<=n;j++)
printf("%d %d\n", j, menacc[j]);
free(men); free(women);
free(menacc); free(womenacc); free(menpre); free(womenlock);
hipFree(&d_men); hipFree(&d_women); hipFree(&d_matched); hipFree(&d_matched_);
hipFree(&d_menacc); hipFree(&d_womenacc); hipFree(&d_menpre); hipFree(&d_womenlock);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <stdbool.h>
#include <time.h>
#include <hip/hip_runtime.h>
void initialize(int *menacc, int *womenacc, int *menpre, int *womenlock, int n) {
int i;
for(i=0; i<=n; i++) {
menacc[i] = -1;
womenacc[i] = -1;
menpre[i] = 1;
womenlock[i] = 0;
}
}
__global__ void stable_matching(int n, int *d_men, int *d_women,
int *d_menacc, int *d_womenacc, int *d_menpre, int *d_matched, int *d_matched_, int *d_womenlock) {
int j = threadIdx.x + 1, idx, ct=0;
while(1) {
__syncthreads();
if(*d_matched_ == 0) break;
if(*d_matched_ == 1 && j <= n && d_menacc[j] == -1) {
idx = d_men[j*(n+1) + d_menpre[j]];
*d_matched = 0;
// locking mechanism
bool isSet = false;
do {
if(isSet = atomicCAS(&d_womenlock[idx], 0, 1) == 0) {
if(d_womenacc[idx] == -1) {
d_womenacc[idx] = j;
d_menacc[j] = idx;
}
else if(d_women[idx*(n+1) + d_womenacc[idx]] > d_women[idx*(n+1) + j]) {
d_menacc[d_womenacc[idx]] = -1;
d_menacc[j] = idx;
d_womenacc[idx] = j;
}
}
if(isSet) {
atomicCAS(&d_womenlock[idx], 1, 0);
}
} while(!isSet);
d_menpre[j]++;
}
__syncthreads();
if(j == 1 && *d_matched == 1) {
*d_matched_ = 0;
}
else if(j == 1 && *d_matched == 0) {
*d_matched = 1;
}
ct++;
}
__syncthreads();
}
int main()
{
int n,i,j,k;
int *d_matched, *d_matched_;
int *men, *women;
int *menacc, *womenacc, *menpre, *womenlock;
int *d_men, *d_women;
int *d_menacc, *d_womenacc, *d_menpre, *d_womenlock;
clock_t beg, end;
double time_taken;
scanf("%d",&n);
men = (int *) malloc((n+1)*(n+1)*sizeof(int));
women = (int *) malloc((n+1)*(n+1)*sizeof(int));
menacc = (int *) malloc((n+1)*sizeof(int));
womenacc = (int *) malloc((n+1)*sizeof(int));
womenlock = (int *) malloc((n+1)*sizeof(int));
menpre = (int *) malloc((n+1)*sizeof(int));
hipMalloc(&d_men, (n+1)*(n+1)*sizeof(int));
hipMalloc(&d_women, (n+1)*(n+1)*sizeof(int));
hipMalloc(&d_menacc, (n+1)*sizeof(int));
hipMalloc(&d_womenacc, (n+1)*sizeof(int));
hipMalloc(&d_womenlock, (n+1)*sizeof(int));
hipMalloc(&d_menpre, (n+1)*sizeof(int));
hipMalloc(&d_matched, sizeof(int));
hipMalloc(&d_matched_, sizeof(int));
initialize(menacc, womenacc, menpre, womenlock, n);
beg = clock();
for(i=1; i<=n; i++) {
for(j=0; j<=n; j++) {
scanf("%d", &men[i*(n+1) + j]);
}
}
for(i=1; i<=n; i++) {
for(j=0; j<=n; j++) {
scanf("%d", &k);
women[i*(n+1) + k] = j;
}
}
end = clock();
time_taken = ((double)(end-beg) * 1000000)/CLOCKS_PER_SEC;
printf("read time : %f us, ", time_taken);
hipMemcpy(d_men, men, (n+1)*(n+1)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_women, women, (n+1)*(n+1)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_menacc, menacc, (n+1)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_womenlock, womenlock, (n+1)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_womenacc, womenacc, (n+1)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_menpre, menpre, (n+1)*sizeof(int), hipMemcpyHostToDevice);
int matched = 1;
hipMemcpy(d_matched, &matched, sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_matched_, &matched, sizeof(int), hipMemcpyHostToDevice);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float milliseconds = 0;
hipEventRecord(start,0);
stable_matching <<< 1, n >>>(n, d_men, d_women, d_menacc, d_womenacc, d_menpre, d_matched, d_matched_, d_womenlock);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&milliseconds, start, stop);
hipMemcpy(menacc, d_menacc, (n+1)*sizeof(int), hipMemcpyDeviceToHost);
printf("compute time : %f us\n", milliseconds*1000);
for(j=1;j<=n;j++)
printf("%d %d\n", j, menacc[j]);
free(men); free(women);
free(menacc); free(womenacc); free(menpre); free(womenlock);
hipFree(&d_men); hipFree(&d_women); hipFree(&d_matched); hipFree(&d_matched_);
hipFree(&d_menacc); hipFree(&d_womenacc); hipFree(&d_menpre); hipFree(&d_womenlock);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15stable_matchingiPiS_S_S_S_S_S_S_
.globl _Z15stable_matchingiPiS_S_S_S_S_S_S_
.p2align 8
.type _Z15stable_matchingiPiS_S_S_S_S_S_S_,@function
_Z15stable_matchingiPiS_S_S_S_S_S_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x0
s_load_b256 s[4:11], s[0:1], 0x8
s_load_b256 s[12:19], s[0:1], 0x28
v_dual_mov_b32 v13, 0 :: v_dual_add_nc_u32 v12, 1, v0
v_mov_b32_e32 v15, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v3, 2, v12
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s0, s2, v0
s_add_i32 s2, s2, 1
v_add_co_u32 v1, s1, s8, v3
v_mul_lo_u32 v14, s2, v12
v_add_co_ci_u32_e64 v2, null, s9, 0, s1
v_add_co_u32 v3, s1, s12, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, null, s13, 0, s1
v_cmp_eq_u32_e64 s1, 0, v0
v_mov_b32_e32 v0, -1
s_branch .LBB0_3
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s3
s_mov_b32 s3, 0
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s3
s_cbranch_vccz .LBB0_29
.LBB0_3:
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
global_load_b32 v16, v13, s[16:17]
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, 1, v16
s_cbranch_vccnz .LBB0_18
v_cmp_eq_u32_e32 vcc_lo, 1, v16
s_cbranch_vccz .LBB0_17
s_and_saveexec_b32 s3, s0
s_cbranch_execz .LBB0_16
global_load_b32 v5, v[1:2], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, -1, v5
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_16
global_load_b32 v5, v[3:4], off
s_mov_b32 s12, 0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v5, v5, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_load_b32 v7, v[5:6], off
global_store_b32 v13, v13, s[14:15]
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[7:8]
v_add_co_u32 v5, vcc_lo, s18, v8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s19, v9, vcc_lo
.LBB0_8:
v_dual_mov_b32 v10, 1 :: v_dual_mov_b32 v11, 0
global_atomic_cmpswap_b32 v10, v[5:6], v[10:11], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 0, v10
s_or_b32 s12, vcc_lo, s12
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execnz .LBB0_8
s_or_b32 exec_lo, exec_lo, s12
v_add_co_u32 v8, vcc_lo, s10, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s11, v9, vcc_lo
s_mov_b32 s12, exec_lo
global_load_b32 v10, v[8:9], off
s_waitcnt vmcnt(0)
v_cmpx_ne_u32_e32 -1, v10
s_xor_b32 s12, exec_lo, s12
s_cbranch_execz .LBB0_13
v_mul_lo_u32 v11, v7, s2
s_mov_b32 s13, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v10, v11
v_add_nc_u32_e32 v19, v11, v12
v_ashrrev_i32_e32 v18, 31, v17
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v20, 31, v19
v_lshlrev_b64 v[17:18], 2, v[17:18]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[19:20], 2, v[19:20]
v_add_co_u32 v17, vcc_lo, s6, v17
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v18, vcc_lo, s7, v18, vcc_lo
v_add_co_u32 v19, vcc_lo, s6, v19
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v20, vcc_lo, s7, v20, vcc_lo
s_clause 0x1
global_load_b32 v11, v[17:18], off
global_load_b32 v17, v[19:20], off
s_waitcnt vmcnt(0)
v_cmpx_gt_i32_e64 v11, v17
s_cbranch_execz .LBB0_12
v_ashrrev_i32_e32 v11, 31, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], 2, v[10:11]
v_add_co_u32 v10, vcc_lo, s8, v10
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v11, vcc_lo
s_clause 0x1
global_store_b32 v[10:11], v0, off
global_store_b32 v[1:2], v7, off
global_store_b32 v[8:9], v12, off
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s13
.LBB0_13:
s_and_not1_saveexec_b32 s12, s12
s_cbranch_execz .LBB0_15
global_store_b32 v[8:9], v12, off
global_store_b32 v[1:2], v7, off
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s12
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v8, 1
global_atomic_cmpswap_b32 v[5:6], v[7:8], off
global_load_b32 v5, v[3:4], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v5, 1, v5
global_store_b32 v[3:4], v5, off
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s3
.LBB0_17:
s_mov_b32 s12, 0
s_mov_b32 s3, -1
s_cbranch_execz .LBB0_19
s_branch .LBB0_20
.LBB0_18:
s_mov_b32 s12, -1
s_mov_b32 s3, 0
.LBB0_19:
v_cmp_ne_u32_e64 s3, 0, v16
.LBB0_20:
s_delay_alu instid0(VALU_DEP_1)
s_and_not1_b32 vcc_lo, exec_lo, s3
s_mov_b32 s3, -1
s_cbranch_vccnz .LBB0_2
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s3, s1
s_cbranch_execz .LBB0_1
global_load_b32 v5, v13, s[14:15]
s_mov_b32 s13, -1
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, 1, v5
v_readfirstlane_b32 s12, v5
s_cbranch_vccnz .LBB0_26
s_delay_alu instid0(VALU_DEP_1)
s_cmp_eq_u32 s12, 1
s_cbranch_scc0 .LBB0_25
global_store_b32 v13, v13, s[16:17]
.LBB0_25:
s_mov_b32 s13, 0
.LBB0_26:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s13
s_cbranch_vccnz .LBB0_1
s_delay_alu instid0(VALU_DEP_1)
s_cmp_eq_u32 s12, 0
s_cbranch_scc0 .LBB0_1
global_store_b32 v13, v15, s[14:15]
s_branch .LBB0_1
.LBB0_29:
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15stable_matchingiPiS_S_S_S_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 72
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15stable_matchingiPiS_S_S_S_S_S_S_, .Lfunc_end0-_Z15stable_matchingiPiS_S_S_S_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 72
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15stable_matchingiPiS_S_S_S_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z15stable_matchingiPiS_S_S_S_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <stdbool.h>
#include <time.h>
#include <hip/hip_runtime.h>
void initialize(int *menacc, int *womenacc, int *menpre, int *womenlock, int n) {
int i;
for(i=0; i<=n; i++) {
menacc[i] = -1;
womenacc[i] = -1;
menpre[i] = 1;
womenlock[i] = 0;
}
}
__global__ void stable_matching(int n, int *d_men, int *d_women,
int *d_menacc, int *d_womenacc, int *d_menpre, int *d_matched, int *d_matched_, int *d_womenlock) {
int j = threadIdx.x + 1, idx, ct=0;
while(1) {
__syncthreads();
if(*d_matched_ == 0) break;
if(*d_matched_ == 1 && j <= n && d_menacc[j] == -1) {
idx = d_men[j*(n+1) + d_menpre[j]];
*d_matched = 0;
// locking mechanism
bool isSet = false;
do {
if(isSet = atomicCAS(&d_womenlock[idx], 0, 1) == 0) {
if(d_womenacc[idx] == -1) {
d_womenacc[idx] = j;
d_menacc[j] = idx;
}
else if(d_women[idx*(n+1) + d_womenacc[idx]] > d_women[idx*(n+1) + j]) {
d_menacc[d_womenacc[idx]] = -1;
d_menacc[j] = idx;
d_womenacc[idx] = j;
}
}
if(isSet) {
atomicCAS(&d_womenlock[idx], 1, 0);
}
} while(!isSet);
d_menpre[j]++;
}
__syncthreads();
if(j == 1 && *d_matched == 1) {
*d_matched_ = 0;
}
else if(j == 1 && *d_matched == 0) {
*d_matched = 1;
}
ct++;
}
__syncthreads();
}
int main()
{
int n,i,j,k;
int *d_matched, *d_matched_;
int *men, *women;
int *menacc, *womenacc, *menpre, *womenlock;
int *d_men, *d_women;
int *d_menacc, *d_womenacc, *d_menpre, *d_womenlock;
clock_t beg, end;
double time_taken;
scanf("%d",&n);
men = (int *) malloc((n+1)*(n+1)*sizeof(int));
women = (int *) malloc((n+1)*(n+1)*sizeof(int));
menacc = (int *) malloc((n+1)*sizeof(int));
womenacc = (int *) malloc((n+1)*sizeof(int));
womenlock = (int *) malloc((n+1)*sizeof(int));
menpre = (int *) malloc((n+1)*sizeof(int));
hipMalloc(&d_men, (n+1)*(n+1)*sizeof(int));
hipMalloc(&d_women, (n+1)*(n+1)*sizeof(int));
hipMalloc(&d_menacc, (n+1)*sizeof(int));
hipMalloc(&d_womenacc, (n+1)*sizeof(int));
hipMalloc(&d_womenlock, (n+1)*sizeof(int));
hipMalloc(&d_menpre, (n+1)*sizeof(int));
hipMalloc(&d_matched, sizeof(int));
hipMalloc(&d_matched_, sizeof(int));
initialize(menacc, womenacc, menpre, womenlock, n);
beg = clock();
for(i=1; i<=n; i++) {
for(j=0; j<=n; j++) {
scanf("%d", &men[i*(n+1) + j]);
}
}
for(i=1; i<=n; i++) {
for(j=0; j<=n; j++) {
scanf("%d", &k);
women[i*(n+1) + k] = j;
}
}
end = clock();
time_taken = ((double)(end-beg) * 1000000)/CLOCKS_PER_SEC;
printf("read time : %f us, ", time_taken);
hipMemcpy(d_men, men, (n+1)*(n+1)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_women, women, (n+1)*(n+1)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_menacc, menacc, (n+1)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_womenlock, womenlock, (n+1)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_womenacc, womenacc, (n+1)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_menpre, menpre, (n+1)*sizeof(int), hipMemcpyHostToDevice);
int matched = 1;
hipMemcpy(d_matched, &matched, sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_matched_, &matched, sizeof(int), hipMemcpyHostToDevice);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float milliseconds = 0;
hipEventRecord(start,0);
stable_matching <<< 1, n >>>(n, d_men, d_women, d_menacc, d_womenacc, d_menpre, d_matched, d_matched_, d_womenlock);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&milliseconds, start, stop);
hipMemcpy(menacc, d_menacc, (n+1)*sizeof(int), hipMemcpyDeviceToHost);
printf("compute time : %f us\n", milliseconds*1000);
for(j=1;j<=n;j++)
printf("%d %d\n", j, menacc[j]);
free(men); free(women);
free(menacc); free(womenacc); free(menpre); free(womenlock);
hipFree(&d_men); hipFree(&d_women); hipFree(&d_matched); hipFree(&d_matched_);
hipFree(&d_menacc); hipFree(&d_womenacc); hipFree(&d_menpre); hipFree(&d_womenlock);
return 0;
} | .text
.file "parallel_final.hip"
.globl _Z10initializePiS_S_S_i # -- Begin function _Z10initializePiS_S_S_i
.p2align 4, 0x90
.type _Z10initializePiS_S_S_i,@function
_Z10initializePiS_S_S_i: # @_Z10initializePiS_S_S_i
.cfi_startproc
# %bb.0:
# kill: def $r8d killed $r8d def $r8
testl %r8d, %r8d
js .LBB0_3
# %bb.1: # %.lr.ph.preheader
incl %r8d
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $-1, (%rdi,%rax,4)
movl $-1, (%rsi,%rax,4)
movl $1, (%rdx,%rax,4)
movl $0, (%rcx,%rax,4)
incq %rax
cmpq %rax, %r8
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z10initializePiS_S_S_i, .Lfunc_end0-_Z10initializePiS_S_S_i
.cfi_endproc
# -- End function
.globl _Z30__device_stub__stable_matchingiPiS_S_S_S_S_S_S_ # -- Begin function _Z30__device_stub__stable_matchingiPiS_S_S_S_S_S_S_
.p2align 4, 0x90
.type _Z30__device_stub__stable_matchingiPiS_S_S_S_S_S_S_,@function
_Z30__device_stub__stable_matchingiPiS_S_S_S_S_S_S_: # @_Z30__device_stub__stable_matchingiPiS_S_S_S_S_S_S_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 4(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15stable_matchingiPiS_S_S_S_S_S_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end1:
.size _Z30__device_stub__stable_matchingiPiS_S_S_S_S_S_S_, .Lfunc_end1-_Z30__device_stub__stable_matchingiPiS_S_S_S_S_S_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI2_1:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $328, %rsp # imm = 0x148
.cfi_def_cfa_offset 384
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsp, %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq (%rsp), %r15
leaq 1(%r15), %r12
imull %r12d, %r12d
shlq $2, %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
movq %r12, %rdi
callq malloc
movq %rax, %r14
leaq 4(,%r15,4), %r13
movq %r13, %rdi
callq malloc
movq %rax, %rbp
movq %r13, %rdi
callq malloc
movq %rax, 104(%rsp) # 8-byte Spill
movq %r13, %rdi
callq malloc
movq %rax, 112(%rsp) # 8-byte Spill
movq %r13, %rdi
callq malloc
movq %rax, 16(%rsp) # 8-byte Spill
leaq 64(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movl (%rsp), %esi
incl %esi
imull %esi, %esi
shlq $2, %rsi
leaq 56(%rsp), %rdi
callq hipMalloc
movslq (%rsp), %rax
leaq 4(,%rax,4), %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
movslq (%rsp), %rax
leaq 4(,%rax,4), %rsi
leaq 48(%rsp), %rdi
callq hipMalloc
movslq (%rsp), %rax
leaq 4(,%rax,4), %rsi
leaq 32(%rsp), %rdi
callq hipMalloc
movslq (%rsp), %rax
leaq 4(,%rax,4), %rsi
leaq 40(%rsp), %rdi
callq hipMalloc
leaq 80(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 72(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movl (%rsp), %r13d
testl %r13d, %r13d
js .LBB2_3
# %bb.1: # %.lr.ph.preheader.i
leaq 4(,%r13,4), %r12
incq %r13
movq %rbp, %rdi
movl $255, %esi
movq %r12, %rdx
callq memset@PLT
movq 104(%rsp), %rdi # 8-byte Reload
movl $255, %esi
movq %r12, %rdx
callq memset@PLT
xorl %r15d, %r15d
movq 112(%rsp), %rdi # 8-byte Reload
xorl %esi, %esi
movq %r12, %rdx
callq memset@PLT
movq 16(%rsp), %rax # 8-byte Reload
.p2align 4, 0x90
.LBB2_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl $1, (%rax,%r15,4)
incq %r15
cmpq %r15, %r13
jne .LBB2_2
.LBB2_3: # %_Z10initializePiS_S_S_i.exit
callq clock
movq %rax, 128(%rsp) # 8-byte Spill
cmpl $0, (%rsp)
jle .LBB2_9
# %bb.4: # %.preheader52.preheader
movl $1, %r13d
jmp .LBB2_5
.p2align 4, 0x90
.LBB2_8: # %._crit_edge
# in Loop: Header=BB2_5 Depth=1
leal 1(%r13), %eax
cmpl (%rsp), %r13d
movl %eax, %r13d
jge .LBB2_9
.LBB2_5: # %.preheader52
# =>This Loop Header: Depth=1
# Child Loop BB2_7 Depth 2
movl (%rsp), %eax
testl %eax, %eax
js .LBB2_8
# %bb.6: # %.lr.ph.preheader
# in Loop: Header=BB2_5 Depth=1
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_7: # %.lr.ph
# Parent Loop BB2_5 Depth=1
# => This Inner Loop Header: Depth=2
incl %eax
imull %r13d, %eax
cltq
addq %r12, %rax
leaq (%rbx,%rax,4), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl (%rsp), %eax
incq %r12
leal -1(%r12), %ecx
cmpl %eax, %ecx
jl .LBB2_7
jmp .LBB2_8
.LBB2_9: # %.preheader51
movq %rbp, 136(%rsp) # 8-byte Spill
cmpl $0, (%rsp)
jle .LBB2_15
# %bb.10: # %.preheader.preheader
movl $1, %r12d
leaq 96(%rsp), %r13
jmp .LBB2_11
.p2align 4, 0x90
.LBB2_14: # %._crit_edge60
# in Loop: Header=BB2_11 Depth=1
leal 1(%r12), %eax
cmpl (%rsp), %r12d
movl %eax, %r12d
jge .LBB2_15
.LBB2_11: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_13 Depth 2
cmpl $0, (%rsp)
js .LBB2_14
# %bb.12: # %.lr.ph59.preheader
# in Loop: Header=BB2_11 Depth=1
movl $-1, %ebp
movslq %r12d, %r15
.p2align 4, 0x90
.LBB2_13: # %.lr.ph59
# Parent Loop BB2_11 Depth=1
# => This Inner Loop Header: Depth=2
incl %ebp
movl $.L.str, %edi
movq %r13, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movslq (%rsp), %rax
incq %rax
imulq %r15, %rax
movslq 96(%rsp), %rcx
addq %rax, %rcx
movl %ebp, (%r14,%rcx,4)
cmpl (%rsp), %ebp
jl .LBB2_13
jmp .LBB2_14
.LBB2_15: # %._crit_edge63
callq clock
subq 128(%rsp), %rax # 8-byte Folded Reload
cvtsi2sd %rax, %xmm0
movsd .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
divsd %xmm1, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 64(%rsp), %rdi
movl (%rsp), %edx
incl %edx
imull %edx, %edx
shlq $2, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rdi
movl (%rsp), %edx
incl %edx
imull %edx, %edx
shlq $2, %rdx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movslq (%rsp), %rax
leaq 4(,%rax,4), %rdx
movq 136(%rsp), %r15 # 8-byte Reload
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movslq (%rsp), %rax
leaq 4(,%rax,4), %rdx
movq 112(%rsp), %r13 # 8-byte Reload
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movslq (%rsp), %rax
leaq 4(,%rax,4), %rdx
movq 104(%rsp), %rbp # 8-byte Reload
movq %rbp, %rsi
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movslq (%rsp), %rax
leaq 4(,%rax,4), %rdx
movq 16(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movl $1, 92(%rsp)
movq 80(%rsp), %rdi
leaq 92(%rsp), %r12
movl $4, %edx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq 72(%rsp), %rdi
movl $4, %edx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 120(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movl $0, 4(%rsp)
movq 120(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl (%rsp), %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_17
# %bb.16:
movl (%rsp), %eax
movq 64(%rsp), %rcx
movq 56(%rsp), %rdx
movq 8(%rsp), %rsi
movq 48(%rsp), %rdi
movq 40(%rsp), %r8
movq 80(%rsp), %r9
movq 72(%rsp), %r10
movq 32(%rsp), %r11
movl %eax, 100(%rsp)
movq %rcx, 248(%rsp)
movq %rdx, 240(%rsp)
movq %rsi, 232(%rsp)
movq %rdi, 224(%rsp)
movq %r8, 216(%rsp)
movq %r9, 208(%rsp)
movq %r10, 200(%rsp)
movq %r11, 192(%rsp)
leaq 100(%rsp), %rax
movq %rax, 256(%rsp)
leaq 248(%rsp), %rax
movq %rax, 264(%rsp)
leaq 240(%rsp), %rax
movq %rax, 272(%rsp)
leaq 232(%rsp), %rax
movq %rax, 280(%rsp)
leaq 224(%rsp), %rax
movq %rax, 288(%rsp)
leaq 216(%rsp), %rax
movq %rax, 296(%rsp)
leaq 208(%rsp), %rax
movq %rax, 304(%rsp)
leaq 200(%rsp), %rax
movq %rax, 312(%rsp)
leaq 192(%rsp), %rax
movq %rax, 320(%rsp)
leaq 176(%rsp), %rdi
leaq 160(%rsp), %rsi
leaq 152(%rsp), %rdx
leaq 144(%rsp), %rcx
callq __hipPopCallConfiguration
movq 176(%rsp), %rsi
movl 184(%rsp), %edx
movq 160(%rsp), %rcx
movl 168(%rsp), %r8d
leaq 256(%rsp), %r9
movl $_Z15stable_matchingiPiS_S_S_S_S_S_S_, %edi
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
pushq 160(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_17:
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 120(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movq 8(%rsp), %rsi
movslq (%rsp), %rax
leaq 4(,%rax,4), %rdx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss .LCPI2_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
cmpl $0, (%rsp)
jle .LBB2_20
# %bb.18: # %.lr.ph67.preheader
movl $1, %r12d
.p2align 4, 0x90
.LBB2_19: # %.lr.ph67
# =>This Inner Loop Header: Depth=1
movl (%r15,%r12,4), %edx
movl $.L.str.3, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
leaq 1(%r12), %rax
movslq (%rsp), %rcx
cmpq %rcx, %r12
movq %rax, %r12
jl .LBB2_19
.LBB2_20: # %._crit_edge68
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %rbp, %rdi
callq free
movq 16(%rsp), %rdi # 8-byte Reload
callq free
movq %r13, %rdi
callq free
leaq 64(%rsp), %rdi
callq hipFree
leaq 56(%rsp), %rdi
callq hipFree
leaq 80(%rsp), %rdi
callq hipFree
leaq 72(%rsp), %rdi
callq hipFree
leaq 8(%rsp), %rdi
callq hipFree
leaq 48(%rsp), %rdi
callq hipFree
leaq 40(%rsp), %rdi
callq hipFree
leaq 32(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $328, %rsp # imm = 0x148
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15stable_matchingiPiS_S_S_S_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15stable_matchingiPiS_S_S_S_S_S_S_,@object # @_Z15stable_matchingiPiS_S_S_S_S_S_S_
.section .rodata,"a",@progbits
.globl _Z15stable_matchingiPiS_S_S_S_S_S_S_
.p2align 3, 0x0
_Z15stable_matchingiPiS_S_S_S_S_S_S_:
.quad _Z30__device_stub__stable_matchingiPiS_S_S_S_S_S_S_
.size _Z15stable_matchingiPiS_S_S_S_S_S_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "read time : %f us, "
.size .L.str.1, 20
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "compute time : %f us\n"
.size .L.str.2, 22
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d %d\n"
.size .L.str.3, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15stable_matchingiPiS_S_S_S_S_S_S_"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__stable_matchingiPiS_S_S_S_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15stable_matchingiPiS_S_S_S_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15stable_matchingiPiS_S_S_S_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0020*/ IMAD.MOV.U32 R18, RZ, RZ, c[0x0][0x198] ; /* 0x00006600ff127624 */
/* 0x000fe400078e00ff */
/*0030*/ IMAD.MOV.U32 R19, RZ, RZ, c[0x0][0x19c] ; /* 0x00006700ff137624 */
/* 0x000fc600078e00ff */
/*0040*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0050*/ LDG.E R2, [R18.64] ; /* 0x0000000612027981 */
/* 0x000ea4000c1e1900 */
/*0060*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x004fda0003f05270 */
/*0070*/ @!P0 BRA 0x600 ; /* 0x0000058000008947 */
/* 0x000fea0003800000 */
/*0080*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0090*/ ULDC UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe20000000800 */
/*00a0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*00b0*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*00c0*/ IMAD.MOV.U32 R8, RZ, RZ, R2 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0002 */
/*00d0*/ IADD3 R6, R0.reuse, 0x1, RZ ; /* 0x0000000100067810 */
/* 0x041fe20007ffe0ff */
/*00e0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fc800078e0205 */
/*00f0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x188] ; /* 0x0000620000047625 */
/* 0x000fc800078e0205 */
/*0100*/ IMAD R7, R6, UR4, RZ ; /* 0x0000000406077c24 */
/* 0x000fe4000f8e02ff */
/*0110*/ ISETP.NE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fc80003f05270 */
/*0120*/ ISETP.GT.OR P0, PT, R6, c[0x0][0x160], P0 ; /* 0x0000580006007a0c */
/* 0x000fda0000704670 */
/*0130*/ @P0 BRA 0x4b0 ; /* 0x0000037000000947 */
/* 0x020fea0003800000 */
/*0140*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040602087981 */
/* 0x000ea4000c1e1900 */
/*0150*/ ISETP.NE.AND P0, PT, R8, -0x1, PT ; /* 0xffffffff0800780c */
/* 0x004fda0003f05270 */
/*0160*/ @P0 BRA 0x4b0 ; /* 0x0000034000000947 */
/* 0x000fea0003800000 */
/*0170*/ LDG.E R8, [R4.64+0x4] ; /* 0x0000040604087981 */
/* 0x000ea2000c1e1900 */
/*0180*/ HFMA2.MMA R12, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0c7435 */
/* 0x000fe200000001ff */
/*0190*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x190] ; /* 0x00006400ff0e7624 */
/* 0x000fe400078e00ff */
/*01a0*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x194] ; /* 0x00006500ff0f7624 */
/* 0x000fe400078e00ff */
/*01b0*/ IMAD.IADD R11, R7, 0x1, R8 ; /* 0x00000001070b7824 */
/* 0x004fca00078e0208 */
/*01c0*/ IMAD.WIDE R10, R11, R12, c[0x0][0x168] ; /* 0x00005a000b0a7625 */
/* 0x000fca00078e020c */
/*01d0*/ LDG.E R13, [R10.64] ; /* 0x000000060a0d7981 */
/* 0x000ea2000c1e1900 */
/*01e0*/ BSSY B0, 0x290 ; /* 0x000000a000007945 */
/* 0x000fe20003800000 */
/*01f0*/ IMAD.MOV.U32 R21, RZ, RZ, 0x1 ; /* 0x00000001ff157424 */
/* 0x000fe400078e00ff */
/*0200*/ STG.E [R14.64], RZ ; /* 0x000000ff0e007986 */
/* 0x0001e2000c101906 */
/*0210*/ SHF.R.S32.HI R16, RZ, 0x1f, R13 ; /* 0x0000001fff107819 */
/* 0x004fe2000001140d */
/*0220*/ IMAD.WIDE R8, R13, R12, c[0x0][0x1a0] ; /* 0x000068000d087625 */
/* 0x001fc800078e020c */
/*0230*/ MOV R20, RZ ; /* 0x000000ff00147202 */
/* 0x000fe20000000f00 */
/*0240*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe80003800000 */
/*0250*/ ATOMG.E.CAS.STRONG.GPU PT, R10, [R8], R20, R21 ; /* 0x00000014080a73a9 */
/* 0x000ea400001ee115 */
/*0260*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x004fda0003f05270 */
/*0270*/ @P0 BRA 0x230 ; /* 0xffffffb000000947 */
/* 0x000fea000383ffff */
/*0280*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0290*/ LEA R10, P0, R13, c[0x0][0x180], 0x2 ; /* 0x000060000d0a7a11 */
/* 0x000fc800078010ff */
/*02a0*/ LEA.HI.X R11, R13, c[0x0][0x184], R16, 0x2, P0 ; /* 0x000061000d0b7a11 */
/* 0x000fca00000f1410 */
/*02b0*/ LDG.E R20, [R10.64] ; /* 0x000000060a147981 */
/* 0x000ea2000c1e1900 */
/*02c0*/ BSSY B0, 0x450 ; /* 0x0000018000007945 */
/* 0x000fe20003800000 */
/*02d0*/ ISETP.NE.U32.AND P0, PT, R20, -0x1, PT ; /* 0xffffffff1400780c */
/* 0x004fe40003f05070 */
/*02e0*/ SHF.R.S32.HI R21, RZ, 0x1f, R20 ; /* 0x0000001fff157819 */
/* 0x000fc80000011414 */
/*02f0*/ ISETP.NE.AND.EX P0, PT, R21, -0x1, PT, P0 ; /* 0xffffffff1500780c */
/* 0x000fda0003f05300 */
/*0300*/ @!P0 BRA 0x410 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0310*/ IMAD R15, R13.reuse, UR4, R20 ; /* 0x000000040d0f7c24 */
/* 0x040fe4000f8e0214 */
/*0320*/ IMAD R17, R13, UR4, R6 ; /* 0x000000040d117c24 */
/* 0x000fe4000f8e0206 */
/*0330*/ IMAD.WIDE R14, R15, R12, c[0x0][0x170] ; /* 0x00005c000f0e7625 */
/* 0x000fc800078e020c */
/*0340*/ IMAD.WIDE R16, R17, R12, c[0x0][0x170] ; /* 0x00005c0011107625 */
/* 0x000fe400078e020c */
/*0350*/ LDG.E R15, [R14.64] ; /* 0x000000060e0f7981 */
/* 0x000ea8000c1e1900 */
/*0360*/ LDG.E R16, [R16.64] ; /* 0x0000000610107981 */
/* 0x000ea4000c1e1900 */
/*0370*/ ISETP.GT.AND P0, PT, R15, R16, PT ; /* 0x000000100f00720c */
/* 0x004fda0003f04270 */
/*0380*/ @!P0 BRA 0x440 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0390*/ LEA R14, P0, R20, c[0x0][0x178], 0x2 ; /* 0x00005e00140e7a11 */
/* 0x000fe200078010ff */
/*03a0*/ IMAD.MOV.U32 R17, RZ, RZ, -0x1 ; /* 0xffffffffff117424 */
/* 0x000fe200078e00ff */
/*03b0*/ IADD3 R6, R0, 0x1, RZ ; /* 0x0000000100067810 */
/* 0x000fe40007ffe0ff */
/*03c0*/ LEA.HI.X R15, R20, c[0x0][0x17c], R21, 0x2, P0 ; /* 0x00005f00140f7a11 */
/* 0x000fca00000f1415 */
/*03d0*/ STG.E [R14.64], R17 ; /* 0x000000110e007986 */
/* 0x0001e8000c101906 */
/*03e0*/ STG.E [R2.64+0x4], R13 ; /* 0x0000040d02007986 */
/* 0x0001e8000c101906 */
/*03f0*/ STG.E [R10.64], R6 ; /* 0x000000060a007986 */
/* 0x0001e2000c101906 */
/*0400*/ BRA 0x440 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0410*/ IADD3 R6, R0, 0x1, RZ ; /* 0x0000000100067810 */
/* 0x000fca0007ffe0ff */
/*0420*/ STG.E [R10.64], R6 ; /* 0x000000060a007986 */
/* 0x0001e8000c101906 */
/*0430*/ STG.E [R2.64+0x4], R13 ; /* 0x0000040d02007986 */
/* 0x0001e4000c101906 */
/*0440*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0450*/ IMAD.MOV.U32 R12, RZ, RZ, 0x1 ; /* 0x00000001ff0c7424 */
/* 0x000fe400078e00ff */
/*0460*/ IMAD.MOV.U32 R13, RZ, RZ, RZ ; /* 0x000000ffff0d7224 */
/* 0x001fca00078e00ff */
/*0470*/ ATOMG.E.CAS.STRONG.GPU PT, RZ, [R8], R12, R13 ; /* 0x0000000c08ff73a9 */
/* 0x00016800001ee10d */
/*0480*/ LDG.E R10, [R4.64+0x4] ; /* 0x00000406040a7981 */
/* 0x000ea4000c1e1900 */
/*0490*/ IADD3 R11, R10, 0x1, RZ ; /* 0x000000010a0b7810 */
/* 0x004fca0007ffe0ff */
/*04a0*/ STG.E [R4.64+0x4], R11 ; /* 0x0000040b04007986 */
/* 0x0001e4000c101906 */
/*04b0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*04c0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*04d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04e0*/ BSSY B0, 0x5c0 ; /* 0x000000d000007945 */
/* 0x000fea0003800000 */
/*04f0*/ @P0 BRA 0x5b0 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0500*/ MOV R8, c[0x0][0x190] ; /* 0x0000640000087a02 */
/* 0x001fe20000000f00 */
/*0510*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x194] ; /* 0x00006500ff097624 */
/* 0x000fca00078e00ff */
/*0520*/ LDG.E R10, [R8.64] ; /* 0x00000006080a7981 */
/* 0x000ea4000c1e1900 */
/*0530*/ ISETP.NE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x004fda0003f05270 */
/*0540*/ @!P0 BRA 0x5a0 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0550*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f05270 */
/*0560*/ @P0 BRA 0x5b0 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0570*/ IMAD.MOV.U32 R11, RZ, RZ, 0x1 ; /* 0x00000001ff0b7424 */
/* 0x000fca00078e00ff */
/*0580*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x0001e2000c101906 */
/*0590*/ BRA 0x5b0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*05a0*/ STG.E [R18.64], RZ ; /* 0x000000ff12007986 */
/* 0x0001e4000c101906 */
/*05b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*05d0*/ LDG.E R8, [R18.64] ; /* 0x0000000612087981 */
/* 0x001ea4000c1e1900 */
/*05e0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x004fda0003f05270 */
/*05f0*/ @P0 BRA 0x110 ; /* 0xfffffb1000000947 */
/* 0x000fea000383ffff */
/*0600*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0610*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0620*/ BRA 0x620; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15stable_matchingiPiS_S_S_S_S_S_S_
.globl _Z15stable_matchingiPiS_S_S_S_S_S_S_
.p2align 8
.type _Z15stable_matchingiPiS_S_S_S_S_S_S_,@function
_Z15stable_matchingiPiS_S_S_S_S_S_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x0
s_load_b256 s[4:11], s[0:1], 0x8
s_load_b256 s[12:19], s[0:1], 0x28
v_dual_mov_b32 v13, 0 :: v_dual_add_nc_u32 v12, 1, v0
v_mov_b32_e32 v15, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v3, 2, v12
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s0, s2, v0
s_add_i32 s2, s2, 1
v_add_co_u32 v1, s1, s8, v3
v_mul_lo_u32 v14, s2, v12
v_add_co_ci_u32_e64 v2, null, s9, 0, s1
v_add_co_u32 v3, s1, s12, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, null, s13, 0, s1
v_cmp_eq_u32_e64 s1, 0, v0
v_mov_b32_e32 v0, -1
s_branch .LBB0_3
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s3
s_mov_b32 s3, 0
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s3
s_cbranch_vccz .LBB0_29
.LBB0_3:
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
global_load_b32 v16, v13, s[16:17]
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, 1, v16
s_cbranch_vccnz .LBB0_18
v_cmp_eq_u32_e32 vcc_lo, 1, v16
s_cbranch_vccz .LBB0_17
s_and_saveexec_b32 s3, s0
s_cbranch_execz .LBB0_16
global_load_b32 v5, v[1:2], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, -1, v5
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_16
global_load_b32 v5, v[3:4], off
s_mov_b32 s12, 0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v5, v5, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_load_b32 v7, v[5:6], off
global_store_b32 v13, v13, s[14:15]
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[7:8]
v_add_co_u32 v5, vcc_lo, s18, v8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s19, v9, vcc_lo
.LBB0_8:
v_dual_mov_b32 v10, 1 :: v_dual_mov_b32 v11, 0
global_atomic_cmpswap_b32 v10, v[5:6], v[10:11], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 0, v10
s_or_b32 s12, vcc_lo, s12
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execnz .LBB0_8
s_or_b32 exec_lo, exec_lo, s12
v_add_co_u32 v8, vcc_lo, s10, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s11, v9, vcc_lo
s_mov_b32 s12, exec_lo
global_load_b32 v10, v[8:9], off
s_waitcnt vmcnt(0)
v_cmpx_ne_u32_e32 -1, v10
s_xor_b32 s12, exec_lo, s12
s_cbranch_execz .LBB0_13
v_mul_lo_u32 v11, v7, s2
s_mov_b32 s13, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v10, v11
v_add_nc_u32_e32 v19, v11, v12
v_ashrrev_i32_e32 v18, 31, v17
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v20, 31, v19
v_lshlrev_b64 v[17:18], 2, v[17:18]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[19:20], 2, v[19:20]
v_add_co_u32 v17, vcc_lo, s6, v17
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v18, vcc_lo, s7, v18, vcc_lo
v_add_co_u32 v19, vcc_lo, s6, v19
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v20, vcc_lo, s7, v20, vcc_lo
s_clause 0x1
global_load_b32 v11, v[17:18], off
global_load_b32 v17, v[19:20], off
s_waitcnt vmcnt(0)
v_cmpx_gt_i32_e64 v11, v17
s_cbranch_execz .LBB0_12
v_ashrrev_i32_e32 v11, 31, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], 2, v[10:11]
v_add_co_u32 v10, vcc_lo, s8, v10
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v11, vcc_lo
s_clause 0x1
global_store_b32 v[10:11], v0, off
global_store_b32 v[1:2], v7, off
global_store_b32 v[8:9], v12, off
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s13
.LBB0_13:
s_and_not1_saveexec_b32 s12, s12
s_cbranch_execz .LBB0_15
global_store_b32 v[8:9], v12, off
global_store_b32 v[1:2], v7, off
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s12
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v8, 1
global_atomic_cmpswap_b32 v[5:6], v[7:8], off
global_load_b32 v5, v[3:4], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v5, 1, v5
global_store_b32 v[3:4], v5, off
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s3
.LBB0_17:
s_mov_b32 s12, 0
s_mov_b32 s3, -1
s_cbranch_execz .LBB0_19
s_branch .LBB0_20
.LBB0_18:
s_mov_b32 s12, -1
s_mov_b32 s3, 0
.LBB0_19:
v_cmp_ne_u32_e64 s3, 0, v16
.LBB0_20:
s_delay_alu instid0(VALU_DEP_1)
s_and_not1_b32 vcc_lo, exec_lo, s3
s_mov_b32 s3, -1
s_cbranch_vccnz .LBB0_2
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s3, s1
s_cbranch_execz .LBB0_1
global_load_b32 v5, v13, s[14:15]
s_mov_b32 s13, -1
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, 1, v5
v_readfirstlane_b32 s12, v5
s_cbranch_vccnz .LBB0_26
s_delay_alu instid0(VALU_DEP_1)
s_cmp_eq_u32 s12, 1
s_cbranch_scc0 .LBB0_25
global_store_b32 v13, v13, s[16:17]
.LBB0_25:
s_mov_b32 s13, 0
.LBB0_26:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s13
s_cbranch_vccnz .LBB0_1
s_delay_alu instid0(VALU_DEP_1)
s_cmp_eq_u32 s12, 0
s_cbranch_scc0 .LBB0_1
global_store_b32 v13, v15, s[14:15]
s_branch .LBB0_1
.LBB0_29:
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15stable_matchingiPiS_S_S_S_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 72
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15stable_matchingiPiS_S_S_S_S_S_S_, .Lfunc_end0-_Z15stable_matchingiPiS_S_S_S_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 72
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15stable_matchingiPiS_S_S_S_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z15stable_matchingiPiS_S_S_S_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00112b3b_00000000-6_parallel_final.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10initializePiS_S_S_i
.type _Z10initializePiS_S_S_i, @function
_Z10initializePiS_S_S_i:
.LFB2057:
.cfi_startproc
endbr64
testl %r8d, %r8d
js .L3
leal 1(%r8), %r8d
salq $2, %r8
movl $0, %eax
.L5:
movl $-1, (%rdi,%rax)
movl $-1, (%rsi,%rax)
movl $1, (%rdx,%rax)
movl $0, (%rcx,%rax)
addq $4, %rax
cmpq %r8, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z10initializePiS_S_S_i, .-_Z10initializePiS_S_S_i
.globl _Z50__device_stub__Z15stable_matchingiPiS_S_S_S_S_S_S_iPiS_S_S_S_S_S_S_
.type _Z50__device_stub__Z15stable_matchingiPiS_S_S_S_S_S_S_iPiS_S_S_S_S_S_S_, @function
_Z50__device_stub__Z15stable_matchingiPiS_S_S_S_S_S_S_iPiS_S_S_S_S_S_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movl %edi, 76(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
movq %r8, 40(%rsp)
movq %r9, 32(%rsp)
movq 240(%rsp), %rax
movq %rax, 24(%rsp)
movq 248(%rsp), %rax
movq %rax, 16(%rsp)
movq 256(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 76(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 24(%rsp), %rax
movq %rax, 192(%rsp)
leaq 16(%rsp), %rax
movq %rax, 200(%rsp)
leaq 8(%rsp), %rax
movq %rax, 208(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 248
pushq 88(%rsp)
.cfi_def_cfa_offset 256
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z15stable_matchingiPiS_S_S_S_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z50__device_stub__Z15stable_matchingiPiS_S_S_S_S_S_S_iPiS_S_S_S_S_S_S_, .-_Z50__device_stub__Z15stable_matchingiPiS_S_S_S_S_S_S_iPiS_S_S_S_S_S_S_
.globl _Z15stable_matchingiPiS_S_S_S_S_S_S_
.type _Z15stable_matchingiPiS_S_S_S_S_S_S_, @function
_Z15stable_matchingiPiS_S_S_S_S_S_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z50__device_stub__Z15stable_matchingiPiS_S_S_S_S_S_S_iPiS_S_S_S_S_S_S_
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z15stable_matchingiPiS_S_S_S_S_S_S_, .-_Z15stable_matchingiPiS_S_S_S_S_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d"
.LC2:
.string "read time : %f us, "
.LC5:
.string "compute time : %f us\n"
.LC6:
.string "%d %d\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $168, %rsp
.cfi_def_cfa_offset 224
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rsi
leaq .LC0(%rip), %rdi
call __isoc23_scanf@PLT
movl 32(%rsp), %eax
leal 1(%rax), %ebp
movl %ebp, %ebx
imull %ebp, %ebx
movslq %ebx, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movslq %ebp, %rbp
salq $2, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbp, %rdi
call malloc@PLT
movq %rax, (%rsp)
movq %rbp, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r15
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl 32(%rsp), %edi
leal 1(%rdi), %eax
imull %eax, %eax
movslq %eax, %rsi
salq $2, %rsi
leaq 72(%rsp), %rdi
call cudaMalloc@PLT
movl 32(%rsp), %edi
leal 1(%rdi), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 80(%rsp), %rdi
call cudaMalloc@PLT
movl 32(%rsp), %edi
leal 1(%rdi), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 88(%rsp), %rdi
call cudaMalloc@PLT
movl 32(%rsp), %edi
leal 1(%rdi), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 104(%rsp), %rdi
call cudaMalloc@PLT
movl 32(%rsp), %edi
leal 1(%rdi), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 96(%rsp), %rdi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl 32(%rsp), %r8d
movq 8(%rsp), %rcx
movq %r15, %rdx
movq (%rsp), %rsi
movq %r14, %rdi
call _Z10initializePiS_S_S_i
call clock@PLT
movq %rax, 24(%rsp)
movl $1, %ebp
leaq .LC0(%rip), %r15
cmpl $0, 32(%rsp)
jg .L16
.L17:
call clock@PLT
movq 24(%rsp), %rcx
subq %rcx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
movsd .LC1(%rip), %xmm1
mulsd %xmm1, %xmm0
divsd %xmm1, %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl 32(%rsp), %eax
addl $1, %eax
imull %eax, %eax
movslq %eax, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r13, %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl 32(%rsp), %eax
addl $1, %eax
imull %eax, %eax
movslq %eax, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r12, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl 32(%rsp), %eax
leal 1(%rax), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r14, %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl 32(%rsp), %eax
leal 1(%rax), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq 8(%rsp), %rsi
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
movl 32(%rsp), %eax
leal 1(%rax), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq (%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl 32(%rsp), %eax
leal 1(%rax), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq 16(%rsp), %rsi
movq 96(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 40(%rsp)
leaq 40(%rsp), %rbx
movl $1, %ecx
movl $4, %edx
movq %rbx, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4, %edx
movq %rbx, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
leaq 112(%rsp), %rdi
call cudaEventCreate@PLT
leaq 120(%rsp), %rdi
call cudaEventCreate@PLT
movl $0x00000000, 44(%rsp)
movl $0, %esi
movq 112(%rsp), %rdi
call cudaEventRecord@PLT
movl 32(%rsp), %eax
movl %eax, 140(%rsp)
movl $1, 144(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 140(%rsp), %rdx
movl $1, %ecx
movq 128(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L24:
movl $0, %esi
movq 120(%rsp), %rdi
call cudaEventRecord@PLT
movq 120(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 44(%rsp), %rdi
movq 120(%rsp), %rdx
movq 112(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl 32(%rsp), %eax
leal 1(%rax), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $2, %ecx
movq 80(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movss .LC4(%rip), %xmm0
mulss 44(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
cmpl $0, 32(%rsp)
jle .L25
movl $1, %ebx
leaq .LC6(%rip), %rbp
.L26:
movl (%r14,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpl %ebx, 32(%rsp)
jge .L26
.L25:
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq (%rsp), %rdi
call free@PLT
movq 16(%rsp), %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
leaq 64(%rsp), %rdi
call cudaFree@PLT
leaq 72(%rsp), %rdi
call cudaFree@PLT
leaq 48(%rsp), %rdi
call cudaFree@PLT
leaq 56(%rsp), %rdi
call cudaFree@PLT
leaq 80(%rsp), %rdi
call cudaFree@PLT
leaq 88(%rsp), %rdi
call cudaFree@PLT
leaq 96(%rsp), %rdi
call cudaFree@PLT
leaq 104(%rsp), %rdi
call cudaFree@PLT
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L40
movl $0, %eax
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
addl $1, %eax
imull %ebp, %eax
addl %ebx, %eax
cltq
leaq 0(%r13,%rax,4), %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
movl 32(%rsp), %eax
cmpl %ebx, %eax
jge .L18
.L20:
addl $1, %ebp
movl 32(%rsp), %eax
cmpl %ebp, %eax
jl .L19
.L16:
movl 32(%rsp), %eax
movl $0, %ebx
testl %eax, %eax
jns .L18
jmp .L20
.L19:
testl %eax, %eax
jle .L17
movl $1, %ebp
leaq .LC0(%rip), %r15
jmp .L21
.L22:
leaq 36(%rsp), %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 32(%rsp), %edx
leal 1(%rdx), %eax
imull %ebp, %eax
addl 36(%rsp), %eax
cltq
movl %ebx, (%r12,%rax,4)
addl $1, %ebx
cmpl %ebx, %edx
jge .L22
.L23:
addl $1, %ebp
cmpl %ebp, 32(%rsp)
jl .L17
.L21:
movl $0, %ebx
cmpl $0, 32(%rsp)
jns .L22
jmp .L23
.L39:
subq $8, %rsp
.cfi_def_cfa_offset 232
pushq 112(%rsp)
.cfi_def_cfa_offset 240
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
movq 128(%rsp), %r9
movq 120(%rsp), %r8
movq 112(%rsp), %rcx
movq 104(%rsp), %rdx
movq 96(%rsp), %rsi
movl 64(%rsp), %edi
call _Z50__device_stub__Z15stable_matchingiPiS_S_S_S_S_S_S_iPiS_S_S_S_S_S_S_
addq $32, %rsp
.cfi_def_cfa_offset 224
jmp .L24
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "_Z15stable_matchingiPiS_S_S_S_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z15stable_matchingiPiS_S_S_S_S_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1093567616
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "parallel_final.hip"
.globl _Z10initializePiS_S_S_i # -- Begin function _Z10initializePiS_S_S_i
.p2align 4, 0x90
.type _Z10initializePiS_S_S_i,@function
_Z10initializePiS_S_S_i: # @_Z10initializePiS_S_S_i
.cfi_startproc
# %bb.0:
# kill: def $r8d killed $r8d def $r8
testl %r8d, %r8d
js .LBB0_3
# %bb.1: # %.lr.ph.preheader
incl %r8d
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $-1, (%rdi,%rax,4)
movl $-1, (%rsi,%rax,4)
movl $1, (%rdx,%rax,4)
movl $0, (%rcx,%rax,4)
incq %rax
cmpq %rax, %r8
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z10initializePiS_S_S_i, .Lfunc_end0-_Z10initializePiS_S_S_i
.cfi_endproc
# -- End function
.globl _Z30__device_stub__stable_matchingiPiS_S_S_S_S_S_S_ # -- Begin function _Z30__device_stub__stable_matchingiPiS_S_S_S_S_S_S_
.p2align 4, 0x90
.type _Z30__device_stub__stable_matchingiPiS_S_S_S_S_S_S_,@function
_Z30__device_stub__stable_matchingiPiS_S_S_S_S_S_S_: # @_Z30__device_stub__stable_matchingiPiS_S_S_S_S_S_S_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 4(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15stable_matchingiPiS_S_S_S_S_S_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end1:
.size _Z30__device_stub__stable_matchingiPiS_S_S_S_S_S_S_, .Lfunc_end1-_Z30__device_stub__stable_matchingiPiS_S_S_S_S_S_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI2_1:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $328, %rsp # imm = 0x148
.cfi_def_cfa_offset 384
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsp, %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq (%rsp), %r15
leaq 1(%r15), %r12
imull %r12d, %r12d
shlq $2, %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
movq %r12, %rdi
callq malloc
movq %rax, %r14
leaq 4(,%r15,4), %r13
movq %r13, %rdi
callq malloc
movq %rax, %rbp
movq %r13, %rdi
callq malloc
movq %rax, 104(%rsp) # 8-byte Spill
movq %r13, %rdi
callq malloc
movq %rax, 112(%rsp) # 8-byte Spill
movq %r13, %rdi
callq malloc
movq %rax, 16(%rsp) # 8-byte Spill
leaq 64(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movl (%rsp), %esi
incl %esi
imull %esi, %esi
shlq $2, %rsi
leaq 56(%rsp), %rdi
callq hipMalloc
movslq (%rsp), %rax
leaq 4(,%rax,4), %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
movslq (%rsp), %rax
leaq 4(,%rax,4), %rsi
leaq 48(%rsp), %rdi
callq hipMalloc
movslq (%rsp), %rax
leaq 4(,%rax,4), %rsi
leaq 32(%rsp), %rdi
callq hipMalloc
movslq (%rsp), %rax
leaq 4(,%rax,4), %rsi
leaq 40(%rsp), %rdi
callq hipMalloc
leaq 80(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 72(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movl (%rsp), %r13d
testl %r13d, %r13d
js .LBB2_3
# %bb.1: # %.lr.ph.preheader.i
leaq 4(,%r13,4), %r12
incq %r13
movq %rbp, %rdi
movl $255, %esi
movq %r12, %rdx
callq memset@PLT
movq 104(%rsp), %rdi # 8-byte Reload
movl $255, %esi
movq %r12, %rdx
callq memset@PLT
xorl %r15d, %r15d
movq 112(%rsp), %rdi # 8-byte Reload
xorl %esi, %esi
movq %r12, %rdx
callq memset@PLT
movq 16(%rsp), %rax # 8-byte Reload
.p2align 4, 0x90
.LBB2_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl $1, (%rax,%r15,4)
incq %r15
cmpq %r15, %r13
jne .LBB2_2
.LBB2_3: # %_Z10initializePiS_S_S_i.exit
callq clock
movq %rax, 128(%rsp) # 8-byte Spill
cmpl $0, (%rsp)
jle .LBB2_9
# %bb.4: # %.preheader52.preheader
movl $1, %r13d
jmp .LBB2_5
.p2align 4, 0x90
.LBB2_8: # %._crit_edge
# in Loop: Header=BB2_5 Depth=1
leal 1(%r13), %eax
cmpl (%rsp), %r13d
movl %eax, %r13d
jge .LBB2_9
.LBB2_5: # %.preheader52
# =>This Loop Header: Depth=1
# Child Loop BB2_7 Depth 2
movl (%rsp), %eax
testl %eax, %eax
js .LBB2_8
# %bb.6: # %.lr.ph.preheader
# in Loop: Header=BB2_5 Depth=1
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_7: # %.lr.ph
# Parent Loop BB2_5 Depth=1
# => This Inner Loop Header: Depth=2
incl %eax
imull %r13d, %eax
cltq
addq %r12, %rax
leaq (%rbx,%rax,4), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl (%rsp), %eax
incq %r12
leal -1(%r12), %ecx
cmpl %eax, %ecx
jl .LBB2_7
jmp .LBB2_8
.LBB2_9: # %.preheader51
movq %rbp, 136(%rsp) # 8-byte Spill
cmpl $0, (%rsp)
jle .LBB2_15
# %bb.10: # %.preheader.preheader
movl $1, %r12d
leaq 96(%rsp), %r13
jmp .LBB2_11
.p2align 4, 0x90
.LBB2_14: # %._crit_edge60
# in Loop: Header=BB2_11 Depth=1
leal 1(%r12), %eax
cmpl (%rsp), %r12d
movl %eax, %r12d
jge .LBB2_15
.LBB2_11: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_13 Depth 2
cmpl $0, (%rsp)
js .LBB2_14
# %bb.12: # %.lr.ph59.preheader
# in Loop: Header=BB2_11 Depth=1
movl $-1, %ebp
movslq %r12d, %r15
.p2align 4, 0x90
.LBB2_13: # %.lr.ph59
# Parent Loop BB2_11 Depth=1
# => This Inner Loop Header: Depth=2
incl %ebp
movl $.L.str, %edi
movq %r13, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movslq (%rsp), %rax
incq %rax
imulq %r15, %rax
movslq 96(%rsp), %rcx
addq %rax, %rcx
movl %ebp, (%r14,%rcx,4)
cmpl (%rsp), %ebp
jl .LBB2_13
jmp .LBB2_14
.LBB2_15: # %._crit_edge63
callq clock
subq 128(%rsp), %rax # 8-byte Folded Reload
cvtsi2sd %rax, %xmm0
movsd .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
divsd %xmm1, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 64(%rsp), %rdi
movl (%rsp), %edx
incl %edx
imull %edx, %edx
shlq $2, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rdi
movl (%rsp), %edx
incl %edx
imull %edx, %edx
shlq $2, %rdx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movslq (%rsp), %rax
leaq 4(,%rax,4), %rdx
movq 136(%rsp), %r15 # 8-byte Reload
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movslq (%rsp), %rax
leaq 4(,%rax,4), %rdx
movq 112(%rsp), %r13 # 8-byte Reload
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movslq (%rsp), %rax
leaq 4(,%rax,4), %rdx
movq 104(%rsp), %rbp # 8-byte Reload
movq %rbp, %rsi
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movslq (%rsp), %rax
leaq 4(,%rax,4), %rdx
movq 16(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movl $1, 92(%rsp)
movq 80(%rsp), %rdi
leaq 92(%rsp), %r12
movl $4, %edx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq 72(%rsp), %rdi
movl $4, %edx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 120(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movl $0, 4(%rsp)
movq 120(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl (%rsp), %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_17
# %bb.16:
movl (%rsp), %eax
movq 64(%rsp), %rcx
movq 56(%rsp), %rdx
movq 8(%rsp), %rsi
movq 48(%rsp), %rdi
movq 40(%rsp), %r8
movq 80(%rsp), %r9
movq 72(%rsp), %r10
movq 32(%rsp), %r11
movl %eax, 100(%rsp)
movq %rcx, 248(%rsp)
movq %rdx, 240(%rsp)
movq %rsi, 232(%rsp)
movq %rdi, 224(%rsp)
movq %r8, 216(%rsp)
movq %r9, 208(%rsp)
movq %r10, 200(%rsp)
movq %r11, 192(%rsp)
leaq 100(%rsp), %rax
movq %rax, 256(%rsp)
leaq 248(%rsp), %rax
movq %rax, 264(%rsp)
leaq 240(%rsp), %rax
movq %rax, 272(%rsp)
leaq 232(%rsp), %rax
movq %rax, 280(%rsp)
leaq 224(%rsp), %rax
movq %rax, 288(%rsp)
leaq 216(%rsp), %rax
movq %rax, 296(%rsp)
leaq 208(%rsp), %rax
movq %rax, 304(%rsp)
leaq 200(%rsp), %rax
movq %rax, 312(%rsp)
leaq 192(%rsp), %rax
movq %rax, 320(%rsp)
leaq 176(%rsp), %rdi
leaq 160(%rsp), %rsi
leaq 152(%rsp), %rdx
leaq 144(%rsp), %rcx
callq __hipPopCallConfiguration
movq 176(%rsp), %rsi
movl 184(%rsp), %edx
movq 160(%rsp), %rcx
movl 168(%rsp), %r8d
leaq 256(%rsp), %r9
movl $_Z15stable_matchingiPiS_S_S_S_S_S_S_, %edi
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
pushq 160(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_17:
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 120(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movq 8(%rsp), %rsi
movslq (%rsp), %rax
leaq 4(,%rax,4), %rdx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss .LCPI2_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
cmpl $0, (%rsp)
jle .LBB2_20
# %bb.18: # %.lr.ph67.preheader
movl $1, %r12d
.p2align 4, 0x90
.LBB2_19: # %.lr.ph67
# =>This Inner Loop Header: Depth=1
movl (%r15,%r12,4), %edx
movl $.L.str.3, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
leaq 1(%r12), %rax
movslq (%rsp), %rcx
cmpq %rcx, %r12
movq %rax, %r12
jl .LBB2_19
.LBB2_20: # %._crit_edge68
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %rbp, %rdi
callq free
movq 16(%rsp), %rdi # 8-byte Reload
callq free
movq %r13, %rdi
callq free
leaq 64(%rsp), %rdi
callq hipFree
leaq 56(%rsp), %rdi
callq hipFree
leaq 80(%rsp), %rdi
callq hipFree
leaq 72(%rsp), %rdi
callq hipFree
leaq 8(%rsp), %rdi
callq hipFree
leaq 48(%rsp), %rdi
callq hipFree
leaq 40(%rsp), %rdi
callq hipFree
leaq 32(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $328, %rsp # imm = 0x148
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15stable_matchingiPiS_S_S_S_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15stable_matchingiPiS_S_S_S_S_S_S_,@object # @_Z15stable_matchingiPiS_S_S_S_S_S_S_
.section .rodata,"a",@progbits
.globl _Z15stable_matchingiPiS_S_S_S_S_S_S_
.p2align 3, 0x0
_Z15stable_matchingiPiS_S_S_S_S_S_S_:
.quad _Z30__device_stub__stable_matchingiPiS_S_S_S_S_S_S_
.size _Z15stable_matchingiPiS_S_S_S_S_S_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "read time : %f us, "
.size .L.str.1, 20
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "compute time : %f us\n"
.size .L.str.2, 22
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d %d\n"
.size .L.str.3, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15stable_matchingiPiS_S_S_S_S_S_S_"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__stable_matchingiPiS_S_S_S_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15stable_matchingiPiS_S_S_S_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include "curand_kernel.h"
#include <memory>
#include <ctime>
#include <stdio.h>
#include <stdlib.h>
#include <chrono>
#include <algorithm>
#include <numeric>
using defer = std::shared_ptr<void>;
#define HEIGHT 32
#define WIDTH 32
#define hBLOCKS 6
#define wBLOCKS 6
//return resurl of this expression (x*x + y*y <= 1)
__device__ bool inCircle(curandState_t* state)
{
float x = curand_uniform(state);
float y = curand_uniform(state);
return x * x + y * y <= 1.0f;
}
__global__ void CalculatePointsIntheCircle(int* result, int randseed)
{
curandState_t state;
unsigned long long seed = (threadIdx.x + blockDim.x * blockIdx.x) + (threadIdx.y + blockDim.y * blockIdx.y) * (randseed % 1000);
//init curand
curand_init(seed, 0, 0, &state);
if (inCircle(&state))
{
atomicAdd(&result[threadIdx.x * HEIGHT + threadIdx.y], 1);
}
return;
}
int main()
{
const size_t size = WIDTH * HEIGHT;
int count [size];
memset(&count, 0, size * sizeof(int));
int* dev_count;
cudaMalloc((void**)&dev_count, size * sizeof(int));
// starting the timer here so that we include the cost of
// all of the operations on the GPU.
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
//use un_ptr, that don`t forget free memory
defer _(nullptr, [&](...)
{ cudaFree(dev_count); cudaEventDestroy(start); cudaEventDestroy(stop); printf("free"); });
dim3 blocks(hBLOCKS, wBLOCKS, 1);
dim3 threads(HEIGHT, WIDTH, 1);
int randseed = std::chrono::duration_cast<std::chrono::milliseconds>
(std::chrono::system_clock::now().time_since_epoch()).count();
CalculatePointsIntheCircle <<<blocks, threads >>> (dev_count, randseed);
cudaMemcpy(&count, dev_count, size * sizeof(int), cudaMemcpyDeviceToHost);
// result pi
int ans = 0;
ans = std::accumulate(&count[0], &count[size - 1], ans);
float fullsize = static_cast<float>(HEIGHT * WIDTH * hBLOCKS * wBLOCKS);
float pi = (4.0f * static_cast<float>(ans));
pi /= fullsize;
printf("Result pi %f \n", pi);
//print elapsed time
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
printf( "Elapsed time %3.1f ms\n", elapsedTime );
return 0;
} | code for sm_80
Function : _Z26CalculatePointsIntheCirclePii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIMAD.WIDE UR4, UR6, 0x10624dd3, URZ ; /* 0x10624dd3060478a5 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e260000002500 */
/*0050*/ USHF.R.U32.HI UR4, URZ, 0x1f, UR5 ; /* 0x0000001f3f047899 */
/* 0x000fe20008011605 */
/*0060*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e660000002600 */
/*0070*/ ULEA.HI.SX32 UR4, UR5, UR4, 0x1a ; /* 0x0000000405047291 */
/* 0x000fe2000f8fd23f */
/*0080*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e660000002200 */
/*0090*/ UIMAD UR4, UR4, -0x3e8, UR6 ; /* 0xfffffc18040478a4 */
/* 0x000fe2000f8e0206 */
/*00a0*/ IMAD R2, R5, c[0x0][0x0], R0 ; /* 0x0000000005027a24 */
/* 0x001fc400078e0200 */
/*00b0*/ IMAD R5, R4, c[0x0][0x4], R3 ; /* 0x0000010004057a24 */
/* 0x002fc800078e0203 */
/*00c0*/ IMAD R2, R5, UR4, R2 ; /* 0x0000000405027c24 */
/* 0x000fca000f8e0202 */
/*00d0*/ LOP3.LUT R2, R2, 0xaad26b49, RZ, 0x3c, !PT ; /* 0xaad26b4902027812 */
/* 0x000fca00078e3cff */
/*00e0*/ IMAD R2, R2, 0x4182bed5, RZ ; /* 0x4182bed502027824 */
/* 0x000fca00078e02ff */
/*00f0*/ IADD3 R4, R2.reuse, 0x75bcd15, RZ ; /* 0x075bcd1502047810 */
/* 0x040fe40007ffe0ff */
/*0100*/ LOP3.LUT R5, R2.reuse, 0x159a55e5, RZ, 0x3c, !PT ; /* 0x159a55e502057812 */
/* 0x040fe400078e3cff */
/*0110*/ IADD3 R6, R2, 0x583f19, RZ ; /* 0x00583f1902067810 */
/* 0x000fe40007ffe0ff */
/*0120*/ SHF.R.U32.HI R7, RZ, 0x2, R4 ; /* 0x00000002ff077819 */
/* 0x000fe40000011604 */
/*0130*/ SHF.R.U32.HI R9, RZ, 0x2, R5 ; /* 0x00000002ff097819 */
/* 0x000fe20000011605 */
/*0140*/ IMAD.SHL.U32 R5, R6, 0x10, RZ ; /* 0x0000001006057824 */
/* 0x000fe200078e00ff */
/*0150*/ LOP3.LUT R7, R7, R4, RZ, 0x3c, !PT ; /* 0x0000000407077212 */
/* 0x000fc400078e3cff */
/*0160*/ LOP3.LUT R4, R9, 0x159a55e5, R2, 0x96, !PT ; /* 0x159a55e509047812 */
/* 0x000fe400078e9602 */
/*0170*/ LOP3.LUT R6, R7.reuse, R5, R6, 0x96, !PT ; /* 0x0000000507067212 */
/* 0x040fe200078e9606 */
/*0180*/ IMAD.SHL.U32 R7, R7, 0x2, RZ ; /* 0x0000000207077824 */
/* 0x000fe200078e00ff */
/*0190*/ SHF.L.U32 R5, R4, 0x1, RZ ; /* 0x0000000104057819 */
/* 0x000fc800000006ff */
/*01a0*/ LOP3.LUT R7, R6, R7, RZ, 0x3c, !PT ; /* 0x0000000706077212 */
/* 0x000fc800078e3cff */
/*01b0*/ LOP3.LUT R5, R7.reuse, R5, R4, 0x96, !PT ; /* 0x0000000507057212 */
/* 0x040fe200078e9604 */
/*01c0*/ IMAD.SHL.U32 R4, R7, 0x10, RZ ; /* 0x0000001007047824 */
/* 0x000fca00078e00ff */
/*01d0*/ LOP3.LUT R5, R5, R4, RZ, 0x3c, !PT ; /* 0x0000000405057212 */
/* 0x000fe200078e3cff */
/*01e0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x2f800000 ; /* 0x2f800000ff047424 */
/* 0x000fc600078e00ff */
/*01f0*/ IADD3 R5, R2.reuse, -0x25fe145e, R5 ; /* 0xda01eba202057810 */
/* 0x040fe40007ffe005 */
/*0200*/ IADD3 R2, R2, -0x26039c23, R7 ; /* 0xd9fc63dd02027810 */
/* 0x000fc80007ffe007 */
/*0210*/ I2F.U32 R5, R5 ; /* 0x0000000500057306 */
/* 0x000e300000201000 */
/*0220*/ I2F.U32 R2, R2 ; /* 0x0000000200027306 */
/* 0x000e620000201000 */
/*0230*/ FFMA R6, R5, R4, 1.1641532182693481445e-10 ; /* 0x2f00000005067423 */
/* 0x001fc80000000004 */
/*0240*/ FMUL R7, R6, R6 ; /* 0x0000000606077220 */
/* 0x000fe40000400000 */
/*0250*/ FFMA R4, R2, R4, 1.1641532182693481445e-10 ; /* 0x2f00000002047423 */
/* 0x002fc80000000004 */
/*0260*/ FFMA R7, R4, R4, R7 ; /* 0x0000000404077223 */
/* 0x000fca0000000007 */
/*0270*/ FSETP.GTU.AND P0, PT, R7, 1, PT ; /* 0x3f8000000700780b */
/* 0x000fda0003f0c000 */
/*0280*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0290*/ LEA R3, R0, R3, 0x5 ; /* 0x0000000300037211 */
/* 0x000fe200078e28ff */
/*02a0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*02b0*/ HFMA2.MMA R5, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff057435 */
/* 0x000fe200000001ff */
/*02c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*02d0*/ IMAD.WIDE.U32 R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0002 */
/*02e0*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x000fe2000c10e184 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ BRA 0x300; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include "curand_kernel.h"
#include <memory>
#include <ctime>
#include <stdio.h>
#include <stdlib.h>
#include <chrono>
#include <algorithm>
#include <numeric>
using defer = std::shared_ptr<void>;
#define HEIGHT 32
#define WIDTH 32
#define hBLOCKS 6
#define wBLOCKS 6
//return resurl of this expression (x*x + y*y <= 1)
__device__ bool inCircle(curandState_t* state)
{
float x = curand_uniform(state);
float y = curand_uniform(state);
return x * x + y * y <= 1.0f;
}
__global__ void CalculatePointsIntheCircle(int* result, int randseed)
{
curandState_t state;
unsigned long long seed = (threadIdx.x + blockDim.x * blockIdx.x) + (threadIdx.y + blockDim.y * blockIdx.y) * (randseed % 1000);
//init curand
curand_init(seed, 0, 0, &state);
if (inCircle(&state))
{
atomicAdd(&result[threadIdx.x * HEIGHT + threadIdx.y], 1);
}
return;
}
int main()
{
const size_t size = WIDTH * HEIGHT;
int count [size];
memset(&count, 0, size * sizeof(int));
int* dev_count;
cudaMalloc((void**)&dev_count, size * sizeof(int));
// starting the timer here so that we include the cost of
// all of the operations on the GPU.
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
//use un_ptr, that don`t forget free memory
defer _(nullptr, [&](...)
{ cudaFree(dev_count); cudaEventDestroy(start); cudaEventDestroy(stop); printf("free"); });
dim3 blocks(hBLOCKS, wBLOCKS, 1);
dim3 threads(HEIGHT, WIDTH, 1);
int randseed = std::chrono::duration_cast<std::chrono::milliseconds>
(std::chrono::system_clock::now().time_since_epoch()).count();
CalculatePointsIntheCircle <<<blocks, threads >>> (dev_count, randseed);
cudaMemcpy(&count, dev_count, size * sizeof(int), cudaMemcpyDeviceToHost);
// result pi
int ans = 0;
ans = std::accumulate(&count[0], &count[size - 1], ans);
float fullsize = static_cast<float>(HEIGHT * WIDTH * hBLOCKS * wBLOCKS);
float pi = (4.0f * static_cast<float>(ans));
pi /= fullsize;
printf("Result pi %f \n", pi);
//print elapsed time
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
printf( "Elapsed time %3.1f ms\n", elapsedTime );
return 0;
} | .file "tmpxft_000666fa_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.align 2
.type _ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EED2Ev, @function
_ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EED2Ev:
.LFB4128:
.cfi_startproc
endbr64
ret
.cfi_endproc
.LFE4128:
.size _ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EED2Ev, .-_ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EED2Ev
.set _ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EED1Ev,_ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EED2Ev
.align 2
.type _ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info, @function
_ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info:
.LFB4133:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq 8(%rsi), %rdi
leaq _ZTSZ4mainEUlzE_(%rip), %rax
cmpq %rax, %rdi
je .L3
movl $0, %eax
cmpb $42, (%rdi)
je .L2
leaq 1+_ZTSZ4mainEUlzE_(%rip), %rsi
call strcmp@PLT
testl %eax, %eax
jne .L6
.L3:
leaq 16(%rbx), %rax
.L2:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl $0, %eax
jmp .L2
.cfi_endproc
.LFE4133:
.size _ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info, .-_ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info
.align 2
.type _ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv, @function
_ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv:
.LFB4132:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $48, %esi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4132:
.size _ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv, .-_ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv
.align 2
.type _ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev, @function
_ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev:
.LFB4130:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $48, %esi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4130:
.size _ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev, .-_ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3852:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3852:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "free"
.text
.align 2
.type _ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv, @function
_ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv:
.LFB4131:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4131
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq 16(%rdi), %rax
movq (%rax), %rdi
call cudaFree@PLT
movq 24(%rbx), %rax
movq (%rax), %rdi
call cudaEventDestroy@PLT
movq 32(%rbx), %rax
movq (%rax), %rdi
call cudaEventDestroy@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4131:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4131:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4131-.LLSDACSB4131
.LLSDACSB4131:
.LLSDACSE4131:
.text
.size _ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv, .-_ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv
.globl _Z8inCircleP17curandStateXORWOW
.type _Z8inCircleP17curandStateXORWOW, @function
_Z8inCircleP17curandStateXORWOW:
.LFB3841:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3841:
.size _Z8inCircleP17curandStateXORWOW, .-_Z8inCircleP17curandStateXORWOW
.globl _Z47__device_stub__Z26CalculatePointsIntheCirclePiiPii
.type _Z47__device_stub__Z26CalculatePointsIntheCirclePiiPii, @function
_Z47__device_stub__Z26CalculatePointsIntheCirclePiiPii:
.LFB3874:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z26CalculatePointsIntheCirclePii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3874:
.size _Z47__device_stub__Z26CalculatePointsIntheCirclePiiPii, .-_Z47__device_stub__Z26CalculatePointsIntheCirclePiiPii
.globl _Z26CalculatePointsIntheCirclePii
.type _Z26CalculatePointsIntheCirclePii, @function
_Z26CalculatePointsIntheCirclePii:
.LFB3875:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z26CalculatePointsIntheCirclePiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3875:
.size _Z26CalculatePointsIntheCirclePii, .-_Z26CalculatePointsIntheCirclePii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z26CalculatePointsIntheCirclePii"
.section .rodata.str1.1
.LC2:
.string "precalc_xorwow_matrix"
.LC3:
.string "precalc_xorwow_offset_matrix"
.LC4:
.string "mrg32k3aM1"
.LC5:
.string "mrg32k3aM2"
.LC6:
.string "mrg32k3aM1SubSeq"
.LC7:
.string "mrg32k3aM2SubSeq"
.LC8:
.string "mrg32k3aM1Seq"
.LC9:
.string "mrg32k3aM2Seq"
.LC10:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3877:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z26CalculatePointsIntheCirclePii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3877:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv,"axG",@progbits,_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv,comdat
.align 2
.weak _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv
.type _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv, @function
_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv:
.LFB3929:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq (%rdi), %rax
call *16(%rax)
cmpb $0, __libc_single_threaded(%rip)
je .L29
movl 12(%rbx), %eax
leal -1(%rax), %edx
movl %edx, 12(%rbx)
.L30:
cmpl $1, %eax
je .L33
.L28:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movl $-1, %eax
lock xaddl %eax, 12(%rbx)
jmp .L30
.L33:
movq (%rbx), %rax
movq %rbx, %rdi
call *24(%rax)
jmp .L28
.cfi_endproc
.LFE3929:
.size _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv, .-_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv
.section .text._ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_releaseEv,"axG",@progbits,_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_releaseEv,comdat
.align 2
.weak _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_releaseEv
.type _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_releaseEv, @function
_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_releaseEv:
.LFB3058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq 8(%rdi), %rdx
movabsq $4294967297, %rax
cmpq %rax, %rdx
je .L40
leaq 8(%rdi), %rcx
cmpb $0, __libc_single_threaded(%rip)
je .L37
movl 8(%rdi), %eax
leal -1(%rax), %edx
movl %edx, 8(%rdi)
.L38:
cmpl $1, %eax
je .L41
.L34:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
movl $0, 8(%rdi)
movl $0, 12(%rdi)
movq (%rdi), %rax
call *16(%rax)
movq (%rbx), %rax
movq %rbx, %rdi
call *24(%rax)
jmp .L34
.L37:
movl $-1, %eax
lock xaddl %eax, (%rcx)
jmp .L38
.L41:
movq %rbx, %rdi
call _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE24_M_release_last_use_coldEv
jmp .L34
.cfi_endproc
.LFE3058:
.size _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_releaseEv, .-_ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_releaseEv
.section .rodata.str1.1
.LC13:
.string "Result pi %f \n"
.LC14:
.string "Elapsed time %3.1f ms\n"
.text
.globl main
.type main, @function
main:
.LFB3842:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3842
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $4096, %rsp
.cfi_def_cfa_offset 4120
orq $0, (%rsp)
subq $88, %rsp
.cfi_def_cfa_offset 4208
movq %fs:40, %rax
movq %rax, 4168(%rsp)
xorl %eax, %eax
leaq 64(%rsp), %rdx
movl $512, %ecx
movq %rdx, %rdi
rep stosq
leaq 16(%rsp), %rdi
movl $4096, %esi
.LEHB0:
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
.LEHE0:
movl $48, %edi
.LEHB1:
call _Znwm@PLT
.LEHE1:
movq %rax, %rbx
movl $1, 8(%rax)
movl $1, 12(%rax)
leaq 16+_ZTVSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE(%rip), %rax
movq %rax, (%rbx)
leaq 16(%rsp), %rax
movq %rax, 16(%rbx)
leaq 24(%rsp), %rax
movq %rax, 24(%rbx)
leaq 32(%rsp), %rax
movq %rax, 32(%rbx)
movq $0, 40(%rbx)
movl $6, 40(%rsp)
movl $6, 44(%rsp)
movl $1, 48(%rsp)
movl $32, 52(%rsp)
movl $32, 56(%rsp)
movl $1, 60(%rsp)
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbp
movl 60(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movq 40(%rsp), %rdi
movl 48(%rsp), %esi
.LEHB2:
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L48
movl $1000000, %ecx
movq %rbp, %rax
cqto
idivq %rcx
movq %rax, %rsi
movq 16(%rsp), %rdi
call _Z47__device_stub__Z26CalculatePointsIntheCirclePiiPii
.LEHE2:
jmp .L48
.L55:
endbr64
movq %rax, %rdi
call __cxa_begin_catch@PLT
movq 16(%rsp), %rdi
.LEHB3:
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 4168(%rsp), %rax
subq %fs:40, %rax
je .L45
call __stack_chk_fail@PLT
.L45:
call __cxa_rethrow@PLT
.LEHE3:
.L54:
endbr64
movq %rax, %rbx
call __cxa_end_catch@PLT
movq 4168(%rsp), %rax
subq %fs:40, %rax
je .L47
call __stack_chk_fail@PLT
.L47:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L48:
leaq 64(%rsp), %rdi
movl $2, %ecx
movl $4096, %edx
movq 16(%rsp), %rsi
.LEHB5:
call cudaMemcpy@PLT
movl $0, %ecx
leaq 64(%rsp), %rax
leaq 4156(%rsp), %rsi
.L49:
movl %ecx, %edx
addl (%rax), %edx
movl %edx, %ecx
addq $4, %rax
cmpq %rsi, %rax
jne .L49
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
mulss .LC11(%rip), %xmm0
divss .LC12(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
.LEHE5:
movq %rbx, %rdi
call _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_releaseEv
movq 4168(%rsp), %rax
subq %fs:40, %rax
jne .L60
movl $0, %eax
addq $4184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
endbr64
movq %rax, %rbp
movq %rbx, %rdi
call _ZNSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE10_M_releaseEv
movq 4168(%rsp), %rax
subq %fs:40, %rax
je .L51
call __stack_chk_fail@PLT
.L51:
movq %rbp, %rdi
.LEHB6:
call _Unwind_Resume@PLT
.LEHE6:
.L60:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3842:
.section .gcc_except_table
.align 4
.LLSDA3842:
.byte 0xff
.byte 0x9b
.uleb128 .LLSDATT3842-.LLSDATTD3842
.LLSDATTD3842:
.byte 0x1
.uleb128 .LLSDACSE3842-.LLSDACSB3842
.LLSDACSB3842:
.uleb128 .LEHB0-.LFB3842
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3842
.uleb128 .LEHE1-.LEHB1
.uleb128 .L55-.LFB3842
.uleb128 0x1
.uleb128 .LEHB2-.LFB3842
.uleb128 .LEHE2-.LEHB2
.uleb128 .L53-.LFB3842
.uleb128 0
.uleb128 .LEHB3-.LFB3842
.uleb128 .LEHE3-.LEHB3
.uleb128 .L54-.LFB3842
.uleb128 0
.uleb128 .LEHB4-.LFB3842
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.uleb128 .LEHB5-.LFB3842
.uleb128 .LEHE5-.LEHB5
.uleb128 .L53-.LFB3842
.uleb128 0
.uleb128 .LEHB6-.LFB3842
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.LLSDACSE3842:
.byte 0x1
.byte 0
.align 4
.long 0
.LLSDATT3842:
.text
.size main, .-main
.weak _ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE
.section .rodata._ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE,"aG",@progbits,_ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE,comdat
.align 32
.type _ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE, @object
.size _ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE, 47
_ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE:
.string "St11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE"
.weak _ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE
.section .data.rel.ro._ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE,"awG",@progbits,_ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE,comdat
.align 8
.type _ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE, @object
.size _ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE, 16
_ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE:
.quad _ZTVN10__cxxabiv117__class_type_infoE+16
.quad _ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE
.section .rodata
.align 8
.type _ZTSZ4mainEUlzE_, @object
.size _ZTSZ4mainEUlzE_, 14
_ZTSZ4mainEUlzE_:
.string "*Z4mainEUlzE_"
.weak _ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE
.section .rodata._ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE,"aG",@progbits,_ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE,comdat
.align 32
.type _ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE, @object
.size _ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE, 52
_ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE:
.string "St16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE"
.weak _ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE
.section .data.rel.ro._ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE,"awG",@progbits,_ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE,comdat
.align 8
.type _ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE, @object
.size _ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE, 24
_ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE
.quad _ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE
.section .data.rel.ro,"aw"
.align 8
.type _ZTISt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE, @object
.size _ZTISt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE, 24
_ZTISt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTSSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE
.quad _ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE
.section .rodata
.align 32
.type _ZTSSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE, @object
.size _ZTSSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE, 75
_ZTSSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE:
.string "*St19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE"
.section .data.rel.ro.local,"aw"
.align 8
.type _ZTVSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE, @object
.size _ZTVSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE, 56
_ZTVSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE:
.quad 0
.quad _ZTISt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE
.quad _ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EED1Ev
.quad _ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EED0Ev
.quad _ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_disposeEv
.quad _ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE10_M_destroyEv
.quad _ZNSt19_Sp_counted_deleterIDnZ4mainEUlzE_SaIvELN9__gnu_cxx12_Lock_policyE2EE14_M_get_deleterERKSt9type_info
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC11:
.long 1082130432
.align 4
.LC12:
.long 1192230912
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
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