system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void cudaclaw5_update_q_cuda(int mbc, double dtdx, double dtdy, double* qold, double* fm, double* fp, double* gm, double* gp)
{
int mq = threadIdx.z;
int x = threadIdx.x;
int x_stride = blockDim.z;
int y = threadIdx.y;
int y_stride = (blockDim.x + 2*mbc)*x_stride;
int i = mq + (x+mbc)*x_stride + (y+mbc)*y_stride;
qold[i] = qold[i] - dtdx * (fm[i+x_stride] - fp[i])
- dtdy * (gm[i+y_stride] - gp[i]);
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cudaclaw5_update_q_cuda(int mbc, double dtdx, double dtdy, double* qold, double* fm, double* fp, double* gm, double* gp)
{
int mq = threadIdx.z;
int x = threadIdx.x;
int x_stride = blockDim.z;
int y = threadIdx.y;
int y_stride = (blockDim.x + 2*mbc)*x_stride;
int i = mq + (x+mbc)*x_stride + (y+mbc)*y_stride;
qold[i] = qold[i] - dtdx * (fm[i+x_stride] - fp[i])
- dtdy * (gm[i+y_stride] - gp[i]);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cudaclaw5_update_q_cuda(int mbc, double dtdx, double dtdy, double* qold, double* fm, double* fp, double* gm, double* gp)
{
int mq = threadIdx.z;
int x = threadIdx.x;
int x_stride = blockDim.z;
int y = threadIdx.y;
int y_stride = (blockDim.x + 2*mbc)*x_stride;
int i = mq + (x+mbc)*x_stride + (y+mbc)*y_stride;
qold[i] = qold[i] - dtdx * (fm[i+x_stride] - fp[i])
- dtdy * (gm[i+y_stride] - gp[i]);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_
.globl _Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_
.p2align 8
.type _Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_,@function
_Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x4c
s_load_b32 s4, s[0:1], 0x0
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v2, v0, 10, 10
v_bfe_u32 v0, v0, 20, 10
s_load_b128 s[12:15], s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_lshl_b32 s5, s4, 1
v_add_nc_u32_e32 v1, s4, v1
v_add_nc_u32_e32 v2, s4, v2
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s5, s2
s_load_b256 s[4:11], s[0:1], 0x8
s_mul_i32 s2, s2, s3
v_mul_lo_u32 v1, v1, s3
v_mul_lo_u32 v2, s2, v2
s_load_b64 s[0:1], s[0:1], 0x38
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, v1, v0, v2
v_add_nc_u32_e32 v2, s3, v0
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v8, s2, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[4:5], 3, v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[1:2], 3, v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v6, vcc_lo, s12, v4
v_add_co_ci_u32_e32 v7, vcc_lo, s13, v5, vcc_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s10, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s11, v2, vcc_lo
global_load_b64 v[6:7], v[6:7], off
global_load_b64 v[1:2], v[1:2], off
v_lshlrev_b64 v[8:9], 3, v[8:9]
v_add_co_u32 v10, vcc_lo, s8, v4
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v5, vcc_lo
v_add_co_u32 v3, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v5, vcc_lo
v_add_co_u32 v8, vcc_lo, s14, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s15, v9, vcc_lo
global_load_b64 v[12:13], v[10:11], off
global_load_b64 v[3:4], v[3:4], off
global_load_b64 v[8:9], v[8:9], off
s_waitcnt vmcnt(3)
v_add_f64 v[0:1], v[1:2], -v[6:7]
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[8:9], -v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[0:1], -v[0:1], s[4:5], v[12:13]
v_fma_f64 v[0:1], -v[2:3], s[6:7], v[0:1]
global_store_b64 v[10:11], v[0:1], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_, .Lfunc_end0-_Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cudaclaw5_update_q_cuda(int mbc, double dtdx, double dtdy, double* qold, double* fm, double* fp, double* gm, double* gp)
{
int mq = threadIdx.z;
int x = threadIdx.x;
int x_stride = blockDim.z;
int y = threadIdx.y;
int y_stride = (blockDim.x + 2*mbc)*x_stride;
int i = mq + (x+mbc)*x_stride + (y+mbc)*y_stride;
qold[i] = qold[i] - dtdx * (fm[i+x_stride] - fp[i])
- dtdy * (gm[i+y_stride] - gp[i]);
} | .text
.file "cudaclaw5_update_q_cuda.hip"
.globl _Z38__device_stub__cudaclaw5_update_q_cudaiddPdS_S_S_S_ # -- Begin function _Z38__device_stub__cudaclaw5_update_q_cudaiddPdS_S_S_S_
.p2align 4, 0x90
.type _Z38__device_stub__cudaclaw5_update_q_cudaiddPdS_S_S_S_,@function
_Z38__device_stub__cudaclaw5_update_q_cudaiddPdS_S_S_S_: # @_Z38__device_stub__cudaclaw5_update_q_cudaiddPdS_S_S_S_
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 4(%rsp)
movsd %xmm0, 104(%rsp)
movsd %xmm1, 96(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 104(%rsp), %rax
movq %rax, 120(%rsp)
leaq 96(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z38__device_stub__cudaclaw5_update_q_cudaiddPdS_S_S_S_, .Lfunc_end0-_Z38__device_stub__cudaclaw5_update_q_cudaiddPdS_S_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_,@object # @_Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_
.section .rodata,"a",@progbits
.globl _Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_
.p2align 3, 0x0
_Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_:
.quad _Z38__device_stub__cudaclaw5_update_q_cudaiddPdS_S_S_S_
.size _Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_"
.size .L__unnamed_1, 41
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__cudaclaw5_update_q_cudaiddPdS_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ HFMA2.MMA R2, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff027435 */
/* 0x000fe200000001ff */
/*0040*/ ULDC UR5, c[0x0][0x0] ; /* 0x0000000000057ab9 */
/* 0x000fe20000000800 */
/*0050*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*0060*/ ULEA UR4, UR4, UR5, 0x1 ; /* 0x0000000504047291 */
/* 0x000fc6000f8e083f */
/*0070*/ S2R R5, SR_TID.Z ; /* 0x0000000000057919 */
/* 0x000ea20000002300 */
/*0080*/ ULDC UR5, c[0x0][0x8] ; /* 0x0000020000057ab9 */
/* 0x000fe40000000800 */
/*0090*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fe2000f8e023f */
/*00a0*/ IADD3 R0, R0, c[0x0][0x160], RZ ; /* 0x0000580000007a10 */
/* 0x001fe40007ffe0ff */
/*00b0*/ IADD3 R3, R3, c[0x0][0x160], RZ ; /* 0x0000580003037a10 */
/* 0x002fc60007ffe0ff */
/*00c0*/ IMAD R0, R0, c[0x0][0x8], R5 ; /* 0x0000020000007a24 */
/* 0x004fc800078e0205 */
/*00d0*/ IMAD R3, R3, UR4, R0 ; /* 0x0000000403037c24 */
/* 0x000fc8000f8e0200 */
/*00e0*/ IMAD.WIDE R8, R3.reuse, R2.reuse, c[0x0][0x188] ; /* 0x0000620003087625 */
/* 0x0c0fe200078e0202 */
/*00f0*/ IADD3 R6, R3.reuse, c[0x0][0x8], RZ ; /* 0x0000020003067a10 */
/* 0x040fe40007ffe0ff */
/*0100*/ IADD3 R12, R3.reuse, UR4, RZ ; /* 0x00000004030c7c10 */
/* 0x040fe2000fffe0ff */
/*0110*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0120*/ IMAD.WIDE R14, R3, R2.reuse, c[0x0][0x198] ; /* 0x00006600030e7625 */
/* 0x080fe200078e0202 */
/*0130*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea6000c1e1b00 */
/*0140*/ IMAD.WIDE R6, R6, R2.reuse, c[0x0][0x180] ; /* 0x0000600006067625 */
/* 0x080fe400078e0202 */
/*0150*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee4000c1e1b00 */
/*0160*/ IMAD.WIDE R12, R12, R2, c[0x0][0x190] ; /* 0x000064000c0c7625 */
/* 0x000fc400078e0202 */
/*0170*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea4000c1e1b00 */
/*0180*/ IMAD.WIDE R2, R3, R2, c[0x0][0x178] ; /* 0x00005e0003027625 */
/* 0x000fe400078e0202 */
/*0190*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ee8000c1e1b00 */
/*01a0*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000f22000c1e1b00 */
/*01b0*/ DADD R10, R6, -R8 ; /* 0x00000000060a7229 */
/* 0x004f080000000808 */
/*01c0*/ DADD R16, R12, -R14 ; /* 0x000000000c107229 */
/* 0x008fc8000000080e */
/*01d0*/ DFMA R4, -R10, c[0x0][0x168], R4 ; /* 0x00005a000a047a2b */
/* 0x010e0c0000000104 */
/*01e0*/ DFMA R4, -R16, c[0x0][0x170], R4 ; /* 0x00005c0010047a2b */
/* 0x001e0e0000000104 */
/*01f0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x001fe2000c101b04 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_
.globl _Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_
.p2align 8
.type _Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_,@function
_Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x4c
s_load_b32 s4, s[0:1], 0x0
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v2, v0, 10, 10
v_bfe_u32 v0, v0, 20, 10
s_load_b128 s[12:15], s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_lshl_b32 s5, s4, 1
v_add_nc_u32_e32 v1, s4, v1
v_add_nc_u32_e32 v2, s4, v2
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s5, s2
s_load_b256 s[4:11], s[0:1], 0x8
s_mul_i32 s2, s2, s3
v_mul_lo_u32 v1, v1, s3
v_mul_lo_u32 v2, s2, v2
s_load_b64 s[0:1], s[0:1], 0x38
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, v1, v0, v2
v_add_nc_u32_e32 v2, s3, v0
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v8, s2, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[4:5], 3, v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[1:2], 3, v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v6, vcc_lo, s12, v4
v_add_co_ci_u32_e32 v7, vcc_lo, s13, v5, vcc_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s10, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s11, v2, vcc_lo
global_load_b64 v[6:7], v[6:7], off
global_load_b64 v[1:2], v[1:2], off
v_lshlrev_b64 v[8:9], 3, v[8:9]
v_add_co_u32 v10, vcc_lo, s8, v4
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v5, vcc_lo
v_add_co_u32 v3, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v5, vcc_lo
v_add_co_u32 v8, vcc_lo, s14, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s15, v9, vcc_lo
global_load_b64 v[12:13], v[10:11], off
global_load_b64 v[3:4], v[3:4], off
global_load_b64 v[8:9], v[8:9], off
s_waitcnt vmcnt(3)
v_add_f64 v[0:1], v[1:2], -v[6:7]
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[8:9], -v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[0:1], -v[0:1], s[4:5], v[12:13]
v_fma_f64 v[0:1], -v[2:3], s[6:7], v[0:1]
global_store_b64 v[10:11], v[0:1], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_, .Lfunc_end0-_Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000178a1_00000000-6_cudaclaw5_update_q_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z54__device_stub__Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_iddPdS_S_S_S_
.type _Z54__device_stub__Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_iddPdS_S_S_S_, @function
_Z54__device_stub__Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_iddPdS_S_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edi, 60(%rsp)
movsd %xmm0, 48(%rsp)
movsd %xmm1, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movq %rsp, %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z54__device_stub__Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_iddPdS_S_S_S_, .-_Z54__device_stub__Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_iddPdS_S_S_S_
.globl _Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_
.type _Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_, @function
_Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z54__device_stub__Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_iddPdS_S_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_, .-_Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cudaclaw5_update_q_cuda.hip"
.globl _Z38__device_stub__cudaclaw5_update_q_cudaiddPdS_S_S_S_ # -- Begin function _Z38__device_stub__cudaclaw5_update_q_cudaiddPdS_S_S_S_
.p2align 4, 0x90
.type _Z38__device_stub__cudaclaw5_update_q_cudaiddPdS_S_S_S_,@function
_Z38__device_stub__cudaclaw5_update_q_cudaiddPdS_S_S_S_: # @_Z38__device_stub__cudaclaw5_update_q_cudaiddPdS_S_S_S_
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 4(%rsp)
movsd %xmm0, 104(%rsp)
movsd %xmm1, 96(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 104(%rsp), %rax
movq %rax, 120(%rsp)
leaq 96(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z38__device_stub__cudaclaw5_update_q_cudaiddPdS_S_S_S_, .Lfunc_end0-_Z38__device_stub__cudaclaw5_update_q_cudaiddPdS_S_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_,@object # @_Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_
.section .rodata,"a",@progbits
.globl _Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_
.p2align 3, 0x0
_Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_:
.quad _Z38__device_stub__cudaclaw5_update_q_cudaiddPdS_S_S_S_
.size _Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_"
.size .L__unnamed_1, 41
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__cudaclaw5_update_q_cudaiddPdS_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23cudaclaw5_update_q_cudaiddPdS_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <cstdio>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <cmath>
using namespace std;
const int TILE_WIDTH = 16;
__global__ void MatrixMulKernel(int *d_M,int *d_N,int *d_P,int m,int n,int k)
{
__shared__ int ds_M[TILE_WIDTH][TILE_WIDTH];
__shared__ int ds_N[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
//Identify the row and column of the Pd element to work on
int row = by * TILE_WIDTH + ty;
int col = bx * TILE_WIDTH + tx;
int pValue = 0;
//loop over the Md and Nd tiles required to comput the Pd element
for(int t = 0; t < (n-1) / TILE_WIDTH + 1; ++t)
{
if(row < m && t * TILE_WIDTH + tx < n)
ds_M[ty][tx] = d_M[row * n + t * TILE_WIDTH + tx];
else
ds_M[ty][tx] = 0;
if(col < k && t * TILE_WIDTH + ty < n)
ds_N[ty][tx] = d_N[(t * TILE_WIDTH + ty) * k + col];
else
ds_N[ty][tx] = 0;
__syncthreads();
for(int i = 0; i < TILE_WIDTH; ++i)
pValue += ds_M[ty][i] * ds_N[i][tx];
__syncthreads();
}
if(row < m && col < k)
d_P[row * k + col] = pValue;
}
int main()
{
//freopen("out","w",stdout);
int m = 600, n = 700, k = 1000;
int *h_M, *h_N, *d_M, *d_N;
int *h_P, *d_P;
size_t sizeM = m * n * sizeof(int);
size_t sizeN = n * k * sizeof(int);
size_t sizeP = m * k * sizeof(int);
h_M = (int *) malloc(sizeM);
h_N = (int *) malloc(sizeN);
h_P = (int *) malloc(sizeP);
cudaMalloc(&d_M,sizeM);
cudaMalloc(&d_N,sizeN);
cudaMalloc(&d_P,sizeP);
for(int i = 0; i < m * n; ++i)
{
if(i % 2 == 0)
h_M[i] = 1;
else
h_M[i] = 0;
}
for(int i = 0;i < n * k; ++i)
{
if(i % 2 == 0)
h_N[i] = 0;
else
h_N[i] = 1;
}
cudaMemcpy(d_M,h_M,sizeM,cudaMemcpyHostToDevice);
cudaMemcpy(d_N,h_N,sizeN,cudaMemcpyHostToDevice);
cudaEvent_t start,stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start,0);
dim3 grid((int)ceil(k*1.0 / TILE_WIDTH), (int)ceil(m*1.0/ TILE_WIDTH));
dim3 block(TILE_WIDTH,TILE_WIDTH);
MatrixMulKernel<<<grid,block>>>(d_M,d_N,d_P,m,n,k);
cudaEventRecord(stop,0);
//cudaDeviceSynchronize();
cudaEventSynchronize(stop);
float ElapsedTime;
cudaEventElapsedTime(&ElapsedTime,start,stop);
printf("Kernel Elpased Time: %.3f ms\n",ElapsedTime);
cudaMemcpy(h_P,d_P,sizeP,cudaMemcpyDeviceToHost);
/*
for(int i = 0; i < m * k; ++i)
printf("%d\n",h_P[i]);
printf("\n");
*/
return 0;
} | code for sm_80
Function : _Z15MatrixMulKernelPiS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff067624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R21, -RZ, RZ, 0, 0 ; /* 0x00000000ff157435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R12, SR_TID.X ; /* 0x00000000000c7919 */
/* 0x000e240000002100 */
/*0060*/ ISETP.GE.AND P1, PT, R6, -0xe, PT ; /* 0xfffffff20600780c */
/* 0x000fe40003f26270 */
/*0070*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0080*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0090*/ LEA R0, R9, R12, 0x4 ; /* 0x0000000c09007211 */
/* 0x001fc800078e20ff */
/*00a0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe40003f06270 */
/*00b0*/ LEA R3, R3, R2, 0x4 ; /* 0x0000000203037211 */
/* 0x002fc800078e20ff */
/*00c0*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fe20000706670 */
/*00d0*/ @!P1 BRA 0x5b0 ; /* 0x000004d000009947 */
/* 0x000fd80003800000 */
/*00e0*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe20007ffe0ff */
/*00f0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0100*/ SHF.L.U32 R15, R2.reuse, 0x6, RZ ; /* 0x00000006020f7819 */
/* 0x040fe200000006ff */
/*0110*/ IMAD R4, R3, c[0x0][0x17c], R12 ; /* 0x00005f0003047a24 */
/* 0x000fe200078e020c */
/*0120*/ SHF.R.S32.HI R7, RZ, 0x1f, R6 ; /* 0x0000001fff077819 */
/* 0x000fe20000011406 */
/*0130*/ IMAD R16, R2, c[0x0][0x180], R12 ; /* 0x0000600002107a24 */
/* 0x000fe200078e020c */
/*0140*/ MOV R21, RZ ; /* 0x000000ff00157202 */
/* 0x000fe20000000f00 */
/*0150*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe200078e0205 */
/*0160*/ LEA.HI R7, R7, R6, RZ, 0x4 ; /* 0x0000000607077211 */
/* 0x000fe200078f20ff */
/*0170*/ UMOV UR4, 0xffffffff ; /* 0xffffffff00047882 */
/* 0x000fe20000000000 */
/*0180*/ LEA R16, R9, R16, 0x4 ; /* 0x0000001009107211 */
/* 0x000fe200078e20ff */
/*0190*/ IMAD.MOV.U32 R14, RZ, RZ, R4 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0004 */
/*01a0*/ MOV R13, R5 ; /* 0x00000005000d7202 */
/* 0x000fe20000000f00 */
/*01b0*/ IMAD R19, R12.reuse, 0x4, R15 ; /* 0x000000040c137824 */
/* 0x040fe200078e020f */
/*01c0*/ LEA R18, R12, 0x400, 0x2 ; /* 0x000004000c127811 */
/* 0x000fc400078e10ff */
/*01d0*/ SHF.R.S32.HI R17, RZ, 0x4, R7 ; /* 0x00000004ff117819 */
/* 0x000fe40000011407 */
/*01e0*/ ISETP.GE.AND P1, PT, R2, c[0x0][0x17c], PT ; /* 0x00005f0002007a0c */
/* 0x000fe20003f26270 */
/*01f0*/ HFMA2.MMA R22, -RZ, RZ, 0, 0 ; /* 0x00000000ff167435 */
/* 0x000fe200000001ff */
/*0200*/ ISETP.GE.AND P2, PT, R12, c[0x0][0x17c], PT ; /* 0x00005f000c007a0c */
/* 0x000fe20003f46270 */
/*0210*/ IMAD.MOV.U32 R28, RZ, RZ, RZ ; /* 0x000000ffff1c7224 */
/* 0x000fe200078e00ff */
/*0220*/ ISETP.GE.OR P1, PT, R0, c[0x0][0x180], P1 ; /* 0x0000600000007a0c */
/* 0x000fe40000f26670 */
/*0230*/ ISETP.GE.OR P2, PT, R3, c[0x0][0x178], P2 ; /* 0x00005e0003007a0c */
/* 0x000fd60001746670 */
/*0240*/ @!P1 MOV R25, 0x4 ; /* 0x0000000400199802 */
/* 0x000fe40000000f00 */
/*0250*/ @!P2 MOV R4, R14 ; /* 0x0000000e0004a202 */
/* 0x000fe40000000f00 */
/*0260*/ @!P2 MOV R5, R13 ; /* 0x0000000d0005a202 */
/* 0x000fe20000000f00 */
/*0270*/ @!P1 IMAD.WIDE R24, R16, R25, c[0x0][0x168] ; /* 0x00005a0010189625 */
/* 0x000fc800078e0219 */
/*0280*/ @!P2 LDG.E R22, [R4.64] ; /* 0x000000060416a981 */
/* 0x000ea8000c1e1900 */
/*0290*/ @!P1 LDG.E R28, [R24.64] ; /* 0x00000006181c9981 */
/* 0x000ee2000c1e1900 */
/*02a0*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*02b0*/ IADD3 R14, P2, R14, 0x40, RZ ; /* 0x000000400e0e7810 */
/* 0x000fe40007f5e0ff */
/*02c0*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe40007ffe0ff */
/*02d0*/ IADD3 R12, R12, 0x10, RZ ; /* 0x000000100c0c7810 */
/* 0x000fc40007ffe0ff */
/*02e0*/ ISETP.LE.AND P1, PT, R17, UR4, PT ; /* 0x0000000411007c0c */
/* 0x000fe4000bf23270 */
/*02f0*/ IADD3.X R13, RZ, R13, RZ, P2, !PT ; /* 0x0000000dff0d7210 */
/* 0x000fe200017fe4ff */
/*0300*/ STS [R19], R22 ; /* 0x0000001613007388 */
/* 0x004fe80000000800 */
/*0310*/ STS [R19+0x400], R28 ; /* 0x0004001c13007388 */
/* 0x008fe80000000800 */
/*0320*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0330*/ LDS R29, [R18] ; /* 0x00000000121d7984 */
/* 0x000fe80000000800 */
/*0340*/ LDS.128 R8, [R15] ; /* 0x000000000f087984 */
/* 0x000e280000000c00 */
/*0350*/ LDS R24, [R18+0x40] ; /* 0x0000400012187984 */
/* 0x000e680000000800 */
/*0360*/ LDS R27, [R18+0x80] ; /* 0x00008000121b7984 */
/* 0x000ea80000000800 */
/*0370*/ LDS R26, [R18+0xc0] ; /* 0x0000c000121a7984 */
/* 0x000ee80000000800 */
/*0380*/ LDS R23, [R18+0x100] ; /* 0x0001000012177984 */
/* 0x000fe80000000800 */
/*0390*/ LDS.128 R4, [R15+0x10] ; /* 0x000010000f047984 */
/* 0x000f280000000c00 */
/*03a0*/ LDS R20, [R18+0x140] ; /* 0x0001400012147984 */
/* 0x000f680000000800 */
/*03b0*/ LDS R25, [R18+0x180] ; /* 0x0001800012197984 */
/* 0x000f680000000800 */
/*03c0*/ LDS R22, [R18+0x1c0] ; /* 0x0001c00012167984 */
/* 0x000f620000000800 */
/*03d0*/ IMAD R8, R29, R8, R21 ; /* 0x000000081d087224 */
/* 0x001fc600078e0215 */
/*03e0*/ LDS R21, [R18+0x200] ; /* 0x0002000012157984 */
/* 0x000fe20000000800 */
/*03f0*/ IMAD R8, R24, R9, R8 ; /* 0x0000000918087224 */
/* 0x002fc600078e0208 */
/*0400*/ LDS R24, [R18+0x240] ; /* 0x0002400012187984 */
/* 0x000fe20000000800 */
/*0410*/ IMAD R8, R27, R10, R8 ; /* 0x0000000a1b087224 */
/* 0x004fc800078e0208 */
/*0420*/ IMAD R26, R26, R11, R8 ; /* 0x0000000b1a1a7224 */
/* 0x008fe400078e0208 */
/*0430*/ LDS.128 R8, [R15+0x20] ; /* 0x000020000f087984 */
/* 0x000e240000000c00 */
/*0440*/ IMAD R4, R23, R4, R26 ; /* 0x0000000417047224 */
/* 0x010fe400078e021a */
/*0450*/ LDS R23, [R18+0x280] ; /* 0x0002800012177984 */
/* 0x000e640000000800 */
/*0460*/ IMAD R4, R20, R5, R4 ; /* 0x0000000514047224 */
/* 0x020fe400078e0204 */
/*0470*/ LDS R20, [R18+0x2c0] ; /* 0x0002c00012147984 */
/* 0x000ea40000000800 */
/*0480*/ IMAD R4, R25, R6, R4 ; /* 0x0000000619047224 */
/* 0x000fc400078e0204 */
/*0490*/ LDS R25, [R18+0x300] ; /* 0x0003000012197984 */
/* 0x000fe40000000800 */
/*04a0*/ IMAD R26, R22, R7, R4 ; /* 0x00000007161a7224 */
/* 0x000fe400078e0204 */
/*04b0*/ LDS.128 R4, [R15+0x30] ; /* 0x000030000f047984 */
/* 0x000ee80000000c00 */
/*04c0*/ LDS R22, [R18+0x340] ; /* 0x0003400012167984 */
/* 0x000f220000000800 */
/*04d0*/ IMAD R26, R21, R8, R26 ; /* 0x00000008151a7224 */
/* 0x001fc600078e021a */
/*04e0*/ LDS R21, [R18+0x380] ; /* 0x0003800012157984 */
/* 0x000e220000000800 */
/*04f0*/ IMAD R9, R24, R9, R26 ; /* 0x0000000918097224 */
/* 0x000fc600078e021a */
/*0500*/ LDS R8, [R18+0x3c0] ; /* 0x0003c00012087984 */
/* 0x000f620000000800 */
/*0510*/ IMAD R9, R23, R10, R9 ; /* 0x0000000a17097224 */
/* 0x002fc800078e0209 */
/*0520*/ IMAD R9, R20, R11, R9 ; /* 0x0000000b14097224 */
/* 0x004fc800078e0209 */
/*0530*/ IMAD R4, R25, R4, R9 ; /* 0x0000000419047224 */
/* 0x008fc800078e0209 */
/*0540*/ IMAD R4, R22, R5, R4 ; /* 0x0000000516047224 */
/* 0x010fe400078e0204 */
/*0550*/ IMAD.MOV.U32 R5, RZ, RZ, 0x10 ; /* 0x00000010ff057424 */
/* 0x000fc800078e00ff */
/*0560*/ IMAD R16, R5, c[0x0][0x180], R16 ; /* 0x0000600005107a24 */
/* 0x000fe400078e0210 */
/*0570*/ IMAD R21, R21, R6, R4 ; /* 0x0000000615157224 */
/* 0x001fc800078e0204 */
/*0580*/ IMAD R21, R8, R7, R21 ; /* 0x0000000708157224 */
/* 0x020fe200078e0215 */
/*0590*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*05a0*/ @!P1 BRA 0x1e0 ; /* 0xfffffc3000009947 */
/* 0x000fea000383ffff */
/*05b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*05c0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*05d0*/ IMAD R3, R3, c[0x0][0x180], R0 ; /* 0x0000600003037a24 */
/* 0x000fd200078e0200 */
/*05e0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*05f0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe2000c101906 */
/*0600*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0610*/ BRA 0x610; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <cstdio>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <cmath>
using namespace std;
const int TILE_WIDTH = 16;
__global__ void MatrixMulKernel(int *d_M,int *d_N,int *d_P,int m,int n,int k)
{
__shared__ int ds_M[TILE_WIDTH][TILE_WIDTH];
__shared__ int ds_N[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
//Identify the row and column of the Pd element to work on
int row = by * TILE_WIDTH + ty;
int col = bx * TILE_WIDTH + tx;
int pValue = 0;
//loop over the Md and Nd tiles required to comput the Pd element
for(int t = 0; t < (n-1) / TILE_WIDTH + 1; ++t)
{
if(row < m && t * TILE_WIDTH + tx < n)
ds_M[ty][tx] = d_M[row * n + t * TILE_WIDTH + tx];
else
ds_M[ty][tx] = 0;
if(col < k && t * TILE_WIDTH + ty < n)
ds_N[ty][tx] = d_N[(t * TILE_WIDTH + ty) * k + col];
else
ds_N[ty][tx] = 0;
__syncthreads();
for(int i = 0; i < TILE_WIDTH; ++i)
pValue += ds_M[ty][i] * ds_N[i][tx];
__syncthreads();
}
if(row < m && col < k)
d_P[row * k + col] = pValue;
}
int main()
{
//freopen("out","w",stdout);
int m = 600, n = 700, k = 1000;
int *h_M, *h_N, *d_M, *d_N;
int *h_P, *d_P;
size_t sizeM = m * n * sizeof(int);
size_t sizeN = n * k * sizeof(int);
size_t sizeP = m * k * sizeof(int);
h_M = (int *) malloc(sizeM);
h_N = (int *) malloc(sizeN);
h_P = (int *) malloc(sizeP);
cudaMalloc(&d_M,sizeM);
cudaMalloc(&d_N,sizeN);
cudaMalloc(&d_P,sizeP);
for(int i = 0; i < m * n; ++i)
{
if(i % 2 == 0)
h_M[i] = 1;
else
h_M[i] = 0;
}
for(int i = 0;i < n * k; ++i)
{
if(i % 2 == 0)
h_N[i] = 0;
else
h_N[i] = 1;
}
cudaMemcpy(d_M,h_M,sizeM,cudaMemcpyHostToDevice);
cudaMemcpy(d_N,h_N,sizeN,cudaMemcpyHostToDevice);
cudaEvent_t start,stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start,0);
dim3 grid((int)ceil(k*1.0 / TILE_WIDTH), (int)ceil(m*1.0/ TILE_WIDTH));
dim3 block(TILE_WIDTH,TILE_WIDTH);
MatrixMulKernel<<<grid,block>>>(d_M,d_N,d_P,m,n,k);
cudaEventRecord(stop,0);
//cudaDeviceSynchronize();
cudaEventSynchronize(stop);
float ElapsedTime;
cudaEventElapsedTime(&ElapsedTime,start,stop);
printf("Kernel Elpased Time: %.3f ms\n",ElapsedTime);
cudaMemcpy(h_P,d_P,sizeP,cudaMemcpyDeviceToHost);
/*
for(int i = 0; i < m * k; ++i)
printf("%d\n",h_P[i]);
printf("\n");
*/
return 0;
} | .file "tmpxft_0003bc8d_00000000-6_matrix.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z15MatrixMulKernelPiS_S_iiiPiS_S_iii
.type _Z42__device_stub__Z15MatrixMulKernelPiS_S_iiiPiS_S_iii, @function
_Z42__device_stub__Z15MatrixMulKernelPiS_S_iiiPiS_S_iii:
.LFB3694:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15MatrixMulKernelPiS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z42__device_stub__Z15MatrixMulKernelPiS_S_iiiPiS_S_iii, .-_Z42__device_stub__Z15MatrixMulKernelPiS_S_iiiPiS_S_iii
.globl _Z15MatrixMulKernelPiS_S_iii
.type _Z15MatrixMulKernelPiS_S_iii, @function
_Z15MatrixMulKernelPiS_S_iii:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z15MatrixMulKernelPiS_S_iiiPiS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z15MatrixMulKernelPiS_S_iii, .-_Z15MatrixMulKernelPiS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Kernel Elpased Time: %.3f ms\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1680000, %edi
call malloc@PLT
movq %rax, %rbp
movl $2800000, %edi
call malloc@PLT
movq %rax, %rbx
movl $2400000, %edi
call malloc@PLT
movq %rax, %r12
leaq 8(%rsp), %rdi
movl $1680000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $2800000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $2400000, %esi
call cudaMalloc@PLT
movl $0, %eax
jmp .L14
.L12:
movl $0, 0(%rbp,%rax,4)
.L13:
addq $1, %rax
cmpq $420000, %rax
je .L23
.L14:
testb $1, %al
jne .L12
movl $1, 0(%rbp,%rax,4)
jmp .L13
.L23:
movl $0, %eax
jmp .L17
.L15:
movl $1, (%rbx,%rax,4)
.L16:
addq $1, %rax
cmpq $700000, %rax
je .L24
.L17:
testb $1, %al
jne .L15
movl $0, (%rbx,%rax,4)
jmp .L16
.L24:
movl $1, %ecx
movl $1680000, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $2800000, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $63, 48(%rsp)
movl $38, 52(%rsp)
movl $16, 60(%rsp)
movl $16, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L18:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $2400000, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movl $1000, %r9d
movl $700, %r8d
movl $600, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z42__device_stub__Z15MatrixMulKernelPiS_S_iiiPiS_S_iii
jmp .L18
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z15MatrixMulKernelPiS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z15MatrixMulKernelPiS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cstdio>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <cmath>
using namespace std;
const int TILE_WIDTH = 16;
__global__ void MatrixMulKernel(int *d_M,int *d_N,int *d_P,int m,int n,int k)
{
__shared__ int ds_M[TILE_WIDTH][TILE_WIDTH];
__shared__ int ds_N[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
//Identify the row and column of the Pd element to work on
int row = by * TILE_WIDTH + ty;
int col = bx * TILE_WIDTH + tx;
int pValue = 0;
//loop over the Md and Nd tiles required to comput the Pd element
for(int t = 0; t < (n-1) / TILE_WIDTH + 1; ++t)
{
if(row < m && t * TILE_WIDTH + tx < n)
ds_M[ty][tx] = d_M[row * n + t * TILE_WIDTH + tx];
else
ds_M[ty][tx] = 0;
if(col < k && t * TILE_WIDTH + ty < n)
ds_N[ty][tx] = d_N[(t * TILE_WIDTH + ty) * k + col];
else
ds_N[ty][tx] = 0;
__syncthreads();
for(int i = 0; i < TILE_WIDTH; ++i)
pValue += ds_M[ty][i] * ds_N[i][tx];
__syncthreads();
}
if(row < m && col < k)
d_P[row * k + col] = pValue;
}
int main()
{
//freopen("out","w",stdout);
int m = 600, n = 700, k = 1000;
int *h_M, *h_N, *d_M, *d_N;
int *h_P, *d_P;
size_t sizeM = m * n * sizeof(int);
size_t sizeN = n * k * sizeof(int);
size_t sizeP = m * k * sizeof(int);
h_M = (int *) malloc(sizeM);
h_N = (int *) malloc(sizeN);
h_P = (int *) malloc(sizeP);
cudaMalloc(&d_M,sizeM);
cudaMalloc(&d_N,sizeN);
cudaMalloc(&d_P,sizeP);
for(int i = 0; i < m * n; ++i)
{
if(i % 2 == 0)
h_M[i] = 1;
else
h_M[i] = 0;
}
for(int i = 0;i < n * k; ++i)
{
if(i % 2 == 0)
h_N[i] = 0;
else
h_N[i] = 1;
}
cudaMemcpy(d_M,h_M,sizeM,cudaMemcpyHostToDevice);
cudaMemcpy(d_N,h_N,sizeN,cudaMemcpyHostToDevice);
cudaEvent_t start,stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start,0);
dim3 grid((int)ceil(k*1.0 / TILE_WIDTH), (int)ceil(m*1.0/ TILE_WIDTH));
dim3 block(TILE_WIDTH,TILE_WIDTH);
MatrixMulKernel<<<grid,block>>>(d_M,d_N,d_P,m,n,k);
cudaEventRecord(stop,0);
//cudaDeviceSynchronize();
cudaEventSynchronize(stop);
float ElapsedTime;
cudaEventElapsedTime(&ElapsedTime,start,stop);
printf("Kernel Elpased Time: %.3f ms\n",ElapsedTime);
cudaMemcpy(h_P,d_P,sizeP,cudaMemcpyDeviceToHost);
/*
for(int i = 0; i < m * k; ++i)
printf("%d\n",h_P[i]);
printf("\n");
*/
return 0;
} | #include <iostream>
#include <cstdio>
#include <hip/hip_runtime.h>
#include <cmath>
using namespace std;
const int TILE_WIDTH = 16;
__global__ void MatrixMulKernel(int *d_M,int *d_N,int *d_P,int m,int n,int k)
{
__shared__ int ds_M[TILE_WIDTH][TILE_WIDTH];
__shared__ int ds_N[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
//Identify the row and column of the Pd element to work on
int row = by * TILE_WIDTH + ty;
int col = bx * TILE_WIDTH + tx;
int pValue = 0;
//loop over the Md and Nd tiles required to comput the Pd element
for(int t = 0; t < (n-1) / TILE_WIDTH + 1; ++t)
{
if(row < m && t * TILE_WIDTH + tx < n)
ds_M[ty][tx] = d_M[row * n + t * TILE_WIDTH + tx];
else
ds_M[ty][tx] = 0;
if(col < k && t * TILE_WIDTH + ty < n)
ds_N[ty][tx] = d_N[(t * TILE_WIDTH + ty) * k + col];
else
ds_N[ty][tx] = 0;
__syncthreads();
for(int i = 0; i < TILE_WIDTH; ++i)
pValue += ds_M[ty][i] * ds_N[i][tx];
__syncthreads();
}
if(row < m && col < k)
d_P[row * k + col] = pValue;
}
int main()
{
//freopen("out","w",stdout);
int m = 600, n = 700, k = 1000;
int *h_M, *h_N, *d_M, *d_N;
int *h_P, *d_P;
size_t sizeM = m * n * sizeof(int);
size_t sizeN = n * k * sizeof(int);
size_t sizeP = m * k * sizeof(int);
h_M = (int *) malloc(sizeM);
h_N = (int *) malloc(sizeN);
h_P = (int *) malloc(sizeP);
hipMalloc(&d_M,sizeM);
hipMalloc(&d_N,sizeN);
hipMalloc(&d_P,sizeP);
for(int i = 0; i < m * n; ++i)
{
if(i % 2 == 0)
h_M[i] = 1;
else
h_M[i] = 0;
}
for(int i = 0;i < n * k; ++i)
{
if(i % 2 == 0)
h_N[i] = 0;
else
h_N[i] = 1;
}
hipMemcpy(d_M,h_M,sizeM,hipMemcpyHostToDevice);
hipMemcpy(d_N,h_N,sizeN,hipMemcpyHostToDevice);
hipEvent_t start,stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start,0);
dim3 grid((int)ceil(k*1.0 / TILE_WIDTH), (int)ceil(m*1.0/ TILE_WIDTH));
dim3 block(TILE_WIDTH,TILE_WIDTH);
MatrixMulKernel<<<grid,block>>>(d_M,d_N,d_P,m,n,k);
hipEventRecord(stop,0);
//cudaDeviceSynchronize();
hipEventSynchronize(stop);
float ElapsedTime;
hipEventElapsedTime(&ElapsedTime,start,stop);
printf("Kernel Elpased Time: %.3f ms\n",ElapsedTime);
hipMemcpy(h_P,d_P,sizeP,hipMemcpyDeviceToHost);
/*
for(int i = 0; i < m * k; ++i)
printf("%d\n",h_P[i]);
printf("\n");
*/
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <iostream>
#include <cstdio>
#include <hip/hip_runtime.h>
#include <cmath>
using namespace std;
const int TILE_WIDTH = 16;
__global__ void MatrixMulKernel(int *d_M,int *d_N,int *d_P,int m,int n,int k)
{
__shared__ int ds_M[TILE_WIDTH][TILE_WIDTH];
__shared__ int ds_N[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
//Identify the row and column of the Pd element to work on
int row = by * TILE_WIDTH + ty;
int col = bx * TILE_WIDTH + tx;
int pValue = 0;
//loop over the Md and Nd tiles required to comput the Pd element
for(int t = 0; t < (n-1) / TILE_WIDTH + 1; ++t)
{
if(row < m && t * TILE_WIDTH + tx < n)
ds_M[ty][tx] = d_M[row * n + t * TILE_WIDTH + tx];
else
ds_M[ty][tx] = 0;
if(col < k && t * TILE_WIDTH + ty < n)
ds_N[ty][tx] = d_N[(t * TILE_WIDTH + ty) * k + col];
else
ds_N[ty][tx] = 0;
__syncthreads();
for(int i = 0; i < TILE_WIDTH; ++i)
pValue += ds_M[ty][i] * ds_N[i][tx];
__syncthreads();
}
if(row < m && col < k)
d_P[row * k + col] = pValue;
}
int main()
{
//freopen("out","w",stdout);
int m = 600, n = 700, k = 1000;
int *h_M, *h_N, *d_M, *d_N;
int *h_P, *d_P;
size_t sizeM = m * n * sizeof(int);
size_t sizeN = n * k * sizeof(int);
size_t sizeP = m * k * sizeof(int);
h_M = (int *) malloc(sizeM);
h_N = (int *) malloc(sizeN);
h_P = (int *) malloc(sizeP);
hipMalloc(&d_M,sizeM);
hipMalloc(&d_N,sizeN);
hipMalloc(&d_P,sizeP);
for(int i = 0; i < m * n; ++i)
{
if(i % 2 == 0)
h_M[i] = 1;
else
h_M[i] = 0;
}
for(int i = 0;i < n * k; ++i)
{
if(i % 2 == 0)
h_N[i] = 0;
else
h_N[i] = 1;
}
hipMemcpy(d_M,h_M,sizeM,hipMemcpyHostToDevice);
hipMemcpy(d_N,h_N,sizeN,hipMemcpyHostToDevice);
hipEvent_t start,stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start,0);
dim3 grid((int)ceil(k*1.0 / TILE_WIDTH), (int)ceil(m*1.0/ TILE_WIDTH));
dim3 block(TILE_WIDTH,TILE_WIDTH);
MatrixMulKernel<<<grid,block>>>(d_M,d_N,d_P,m,n,k);
hipEventRecord(stop,0);
//cudaDeviceSynchronize();
hipEventSynchronize(stop);
float ElapsedTime;
hipEventElapsedTime(&ElapsedTime,start,stop);
printf("Kernel Elpased Time: %.3f ms\n",ElapsedTime);
hipMemcpy(h_P,d_P,sizeP,hipMemcpyDeviceToHost);
/*
for(int i = 0; i < m * k; ++i)
printf("%d\n",h_P[i]);
printf("\n");
*/
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15MatrixMulKernelPiS_S_iii
.globl _Z15MatrixMulKernelPiS_S_iii
.p2align 8
.type _Z15MatrixMulKernelPiS_S_iii,@function
_Z15MatrixMulKernelPiS_S_iii:
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x18
s_load_b32 s10, s[0:1], 0x20
v_bfe_u32 v6, v0, 10, 10
v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v1, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v5, s15, 4, v6
v_lshl_add_u32 v0, s14, 4, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s8, v5
v_cmp_gt_i32_e64 s2, s10, v0
s_cmp_lt_i32 s9, -14
s_cbranch_scc1 .LBB0_18
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 2, v1
s_add_i32 s3, s9, -1
v_lshlrev_b32_e32 v7, 6, v6
s_ashr_i32 s11, s3, 31
v_cmp_le_i32_e64 s12, s10, v0
v_add_nc_u32_e32 v8, 0x400, v2
s_lshr_b32 s11, s11, 28
v_mad_u64_u32 v[3:4], null, v5, s9, v[1:2]
s_add_i32 s3, s3, s11
v_cmp_le_i32_e64 s11, s8, v5
v_dual_mov_b32 v10, 0 :: v_dual_add_nc_u32 v9, v7, v2
v_mov_b32_e32 v2, 0
v_add_nc_u32_e32 v4, v8, v7
s_ashr_i32 s3, s3, 4
s_mov_b32 s14, 0
s_max_i32 s13, s3, 0
.LBB0_2:
s_mov_b32 s3, s11
s_mov_b32 s15, 0
s_and_saveexec_b32 s16, vcc_lo
s_lshl_b32 s17, s14, 4
s_mov_b32 s15, exec_lo
v_add_nc_u32_e32 v12, s17, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_le_i32_e64 s3, s9, v12
v_mov_b32_e32 v12, s17
s_and_not1_b32 s17, s11, exec_lo
s_and_b32 s3, s3, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s3, s17, s3
s_or_b32 exec_lo, exec_lo, s16
s_and_saveexec_b32 s16, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s3, exec_lo, s16
s_cbranch_execz .LBB0_6
s_and_not1_b32 s15, s15, exec_lo
ds_store_b32 v9, v10
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s16, s15
s_cbranch_execz .LBB0_8
v_add_nc_u32_e32 v13, v3, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v14, 31, v13
v_lshlrev_b64 v[13:14], 2, v[13:14]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v13, s3, s4, v13
v_add_co_ci_u32_e64 v14, s3, s5, v14, s3
global_load_b32 v13, v[13:14], off
s_waitcnt vmcnt(0)
ds_store_b32 v9, v13
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s16
s_mov_b32 s15, 0
s_mov_b32 s3, s12
s_and_saveexec_b32 s16, s2
v_lshl_add_u32 v11, s14, 4, v6
s_and_not1_b32 s17, s12, exec_lo
s_mov_b32 s15, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s3, s9, v11
s_and_b32 s3, s3, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s3, s17, s3
s_or_b32 exec_lo, exec_lo, s16
s_and_saveexec_b32 s16, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s3, exec_lo, s16
s_cbranch_execz .LBB0_12
s_and_not1_b32 s15, s15, exec_lo
ds_store_b32 v4, v10
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s16, s15
s_cbranch_execz .LBB0_14
v_mad_u64_u32 v[13:14], null, v11, s10, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v14, 31, v13
v_lshlrev_b64 v[13:14], 2, v[13:14]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v13, s3, s6, v13
v_add_co_ci_u32_e64 v14, s3, s7, v14, s3
global_load_b32 v13, v[13:14], off
s_waitcnt vmcnt(0)
ds_store_b32 v4, v13
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s16
v_mov_b32_e32 v13, v8
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_15:
v_add_nc_u32_e32 v14, s3, v7
s_add_i32 s3, s3, 4
ds_load_b32 v16, v13
ds_load_b32 v17, v14
s_cmp_eq_u32 s3, 64
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[14:15], null, v16, v17, v[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v2, v14 :: v_dual_add_nc_u32 v13, 64, v13
s_cbranch_scc0 .LBB0_15
s_add_i32 s3, s14, 1
s_cmp_eq_u32 s14, s13
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_18
s_mov_b32 s14, s3
s_branch .LBB0_2
.LBB0_18:
v_cmp_gt_i32_e32 vcc_lo, s8, v5
v_cmp_gt_i32_e64 s2, s10, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_20
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[3:4], null, v5, s10, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_20:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15MatrixMulKernelPiS_S_iii
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15MatrixMulKernelPiS_S_iii, .Lfunc_end0-_Z15MatrixMulKernelPiS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15MatrixMulKernelPiS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z15MatrixMulKernelPiS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <iostream>
#include <cstdio>
#include <hip/hip_runtime.h>
#include <cmath>
using namespace std;
const int TILE_WIDTH = 16;
__global__ void MatrixMulKernel(int *d_M,int *d_N,int *d_P,int m,int n,int k)
{
__shared__ int ds_M[TILE_WIDTH][TILE_WIDTH];
__shared__ int ds_N[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
//Identify the row and column of the Pd element to work on
int row = by * TILE_WIDTH + ty;
int col = bx * TILE_WIDTH + tx;
int pValue = 0;
//loop over the Md and Nd tiles required to comput the Pd element
for(int t = 0; t < (n-1) / TILE_WIDTH + 1; ++t)
{
if(row < m && t * TILE_WIDTH + tx < n)
ds_M[ty][tx] = d_M[row * n + t * TILE_WIDTH + tx];
else
ds_M[ty][tx] = 0;
if(col < k && t * TILE_WIDTH + ty < n)
ds_N[ty][tx] = d_N[(t * TILE_WIDTH + ty) * k + col];
else
ds_N[ty][tx] = 0;
__syncthreads();
for(int i = 0; i < TILE_WIDTH; ++i)
pValue += ds_M[ty][i] * ds_N[i][tx];
__syncthreads();
}
if(row < m && col < k)
d_P[row * k + col] = pValue;
}
int main()
{
//freopen("out","w",stdout);
int m = 600, n = 700, k = 1000;
int *h_M, *h_N, *d_M, *d_N;
int *h_P, *d_P;
size_t sizeM = m * n * sizeof(int);
size_t sizeN = n * k * sizeof(int);
size_t sizeP = m * k * sizeof(int);
h_M = (int *) malloc(sizeM);
h_N = (int *) malloc(sizeN);
h_P = (int *) malloc(sizeP);
hipMalloc(&d_M,sizeM);
hipMalloc(&d_N,sizeN);
hipMalloc(&d_P,sizeP);
for(int i = 0; i < m * n; ++i)
{
if(i % 2 == 0)
h_M[i] = 1;
else
h_M[i] = 0;
}
for(int i = 0;i < n * k; ++i)
{
if(i % 2 == 0)
h_N[i] = 0;
else
h_N[i] = 1;
}
hipMemcpy(d_M,h_M,sizeM,hipMemcpyHostToDevice);
hipMemcpy(d_N,h_N,sizeN,hipMemcpyHostToDevice);
hipEvent_t start,stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start,0);
dim3 grid((int)ceil(k*1.0 / TILE_WIDTH), (int)ceil(m*1.0/ TILE_WIDTH));
dim3 block(TILE_WIDTH,TILE_WIDTH);
MatrixMulKernel<<<grid,block>>>(d_M,d_N,d_P,m,n,k);
hipEventRecord(stop,0);
//cudaDeviceSynchronize();
hipEventSynchronize(stop);
float ElapsedTime;
hipEventElapsedTime(&ElapsedTime,start,stop);
printf("Kernel Elpased Time: %.3f ms\n",ElapsedTime);
hipMemcpy(h_P,d_P,sizeP,hipMemcpyDeviceToHost);
/*
for(int i = 0; i < m * k; ++i)
printf("%d\n",h_P[i]);
printf("\n");
*/
return 0;
} | .text
.file "matrix.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z30__device_stub__MatrixMulKernelPiS_S_iii # -- Begin function _Z30__device_stub__MatrixMulKernelPiS_S_iii
.p2align 4, 0x90
.type _Z30__device_stub__MatrixMulKernelPiS_S_iii,@function
_Z30__device_stub__MatrixMulKernelPiS_S_iii: # @_Z30__device_stub__MatrixMulKernelPiS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15MatrixMulKernelPiS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z30__device_stub__MatrixMulKernelPiS_S_iii, .Lfunc_end0-_Z30__device_stub__MatrixMulKernelPiS_S_iii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $176, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $1680000, %edi # imm = 0x19A280
callq malloc
movq %rax, %r15
movl $2800000, %edi # imm = 0x2AB980
callq malloc
movq %rax, %r14
movl $2400000, %edi # imm = 0x249F00
callq malloc
movq %rax, %rbx
leaq 48(%rsp), %rdi
movl $1680000, %esi # imm = 0x19A280
callq hipMalloc
leaq 40(%rsp), %rdi
movl $2800000, %esi # imm = 0x2AB980
callq hipMalloc
leaq 32(%rsp), %rdi
movl $2400000, %esi # imm = 0x249F00
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, %ecx
notl %ecx
andl $1, %ecx
movl %ecx, (%r15,%rax,4)
incq %rax
cmpq $420000, %rax # imm = 0x668A0
jne .LBB1_1
# %bb.2: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_3: # %.preheader
# =>This Inner Loop Header: Depth=1
movl %eax, %ecx
andl $1, %ecx
movl %ecx, (%r14,%rax,4)
incq %rax
cmpq $700000, %rax # imm = 0xAAE60
jne .LBB1_3
# %bb.4:
movq 48(%rsp), %rdi
movl $1680000, %edx # imm = 0x19A280
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movl $2800000, %edx # imm = 0x2AB980
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 24(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $163208757311, %rdi # imm = 0x260000003F
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl $600, 20(%rsp) # imm = 0x258
movl $700, 16(%rsp) # imm = 0x2BC
movl $1000, 12(%rsp) # imm = 0x3E8
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z15MatrixMulKernelPiS_S_iii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq (%rsp), %rdx
leaq 128(%rsp), %rdi
callq hipEventElapsedTime
movss 128(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rsi
movl $2400000, %edx # imm = 0x249F00
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
addq $176, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15MatrixMulKernelPiS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15MatrixMulKernelPiS_S_iii,@object # @_Z15MatrixMulKernelPiS_S_iii
.section .rodata,"a",@progbits
.globl _Z15MatrixMulKernelPiS_S_iii
.p2align 3, 0x0
_Z15MatrixMulKernelPiS_S_iii:
.quad _Z30__device_stub__MatrixMulKernelPiS_S_iii
.size _Z15MatrixMulKernelPiS_S_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Kernel Elpased Time: %.3f ms\n"
.size .L.str, 30
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15MatrixMulKernelPiS_S_iii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__MatrixMulKernelPiS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15MatrixMulKernelPiS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15MatrixMulKernelPiS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff067624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R21, -RZ, RZ, 0, 0 ; /* 0x00000000ff157435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R12, SR_TID.X ; /* 0x00000000000c7919 */
/* 0x000e240000002100 */
/*0060*/ ISETP.GE.AND P1, PT, R6, -0xe, PT ; /* 0xfffffff20600780c */
/* 0x000fe40003f26270 */
/*0070*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0080*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0090*/ LEA R0, R9, R12, 0x4 ; /* 0x0000000c09007211 */
/* 0x001fc800078e20ff */
/*00a0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe40003f06270 */
/*00b0*/ LEA R3, R3, R2, 0x4 ; /* 0x0000000203037211 */
/* 0x002fc800078e20ff */
/*00c0*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fe20000706670 */
/*00d0*/ @!P1 BRA 0x5b0 ; /* 0x000004d000009947 */
/* 0x000fd80003800000 */
/*00e0*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe20007ffe0ff */
/*00f0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0100*/ SHF.L.U32 R15, R2.reuse, 0x6, RZ ; /* 0x00000006020f7819 */
/* 0x040fe200000006ff */
/*0110*/ IMAD R4, R3, c[0x0][0x17c], R12 ; /* 0x00005f0003047a24 */
/* 0x000fe200078e020c */
/*0120*/ SHF.R.S32.HI R7, RZ, 0x1f, R6 ; /* 0x0000001fff077819 */
/* 0x000fe20000011406 */
/*0130*/ IMAD R16, R2, c[0x0][0x180], R12 ; /* 0x0000600002107a24 */
/* 0x000fe200078e020c */
/*0140*/ MOV R21, RZ ; /* 0x000000ff00157202 */
/* 0x000fe20000000f00 */
/*0150*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe200078e0205 */
/*0160*/ LEA.HI R7, R7, R6, RZ, 0x4 ; /* 0x0000000607077211 */
/* 0x000fe200078f20ff */
/*0170*/ UMOV UR4, 0xffffffff ; /* 0xffffffff00047882 */
/* 0x000fe20000000000 */
/*0180*/ LEA R16, R9, R16, 0x4 ; /* 0x0000001009107211 */
/* 0x000fe200078e20ff */
/*0190*/ IMAD.MOV.U32 R14, RZ, RZ, R4 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0004 */
/*01a0*/ MOV R13, R5 ; /* 0x00000005000d7202 */
/* 0x000fe20000000f00 */
/*01b0*/ IMAD R19, R12.reuse, 0x4, R15 ; /* 0x000000040c137824 */
/* 0x040fe200078e020f */
/*01c0*/ LEA R18, R12, 0x400, 0x2 ; /* 0x000004000c127811 */
/* 0x000fc400078e10ff */
/*01d0*/ SHF.R.S32.HI R17, RZ, 0x4, R7 ; /* 0x00000004ff117819 */
/* 0x000fe40000011407 */
/*01e0*/ ISETP.GE.AND P1, PT, R2, c[0x0][0x17c], PT ; /* 0x00005f0002007a0c */
/* 0x000fe20003f26270 */
/*01f0*/ HFMA2.MMA R22, -RZ, RZ, 0, 0 ; /* 0x00000000ff167435 */
/* 0x000fe200000001ff */
/*0200*/ ISETP.GE.AND P2, PT, R12, c[0x0][0x17c], PT ; /* 0x00005f000c007a0c */
/* 0x000fe20003f46270 */
/*0210*/ IMAD.MOV.U32 R28, RZ, RZ, RZ ; /* 0x000000ffff1c7224 */
/* 0x000fe200078e00ff */
/*0220*/ ISETP.GE.OR P1, PT, R0, c[0x0][0x180], P1 ; /* 0x0000600000007a0c */
/* 0x000fe40000f26670 */
/*0230*/ ISETP.GE.OR P2, PT, R3, c[0x0][0x178], P2 ; /* 0x00005e0003007a0c */
/* 0x000fd60001746670 */
/*0240*/ @!P1 MOV R25, 0x4 ; /* 0x0000000400199802 */
/* 0x000fe40000000f00 */
/*0250*/ @!P2 MOV R4, R14 ; /* 0x0000000e0004a202 */
/* 0x000fe40000000f00 */
/*0260*/ @!P2 MOV R5, R13 ; /* 0x0000000d0005a202 */
/* 0x000fe20000000f00 */
/*0270*/ @!P1 IMAD.WIDE R24, R16, R25, c[0x0][0x168] ; /* 0x00005a0010189625 */
/* 0x000fc800078e0219 */
/*0280*/ @!P2 LDG.E R22, [R4.64] ; /* 0x000000060416a981 */
/* 0x000ea8000c1e1900 */
/*0290*/ @!P1 LDG.E R28, [R24.64] ; /* 0x00000006181c9981 */
/* 0x000ee2000c1e1900 */
/*02a0*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*02b0*/ IADD3 R14, P2, R14, 0x40, RZ ; /* 0x000000400e0e7810 */
/* 0x000fe40007f5e0ff */
/*02c0*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe40007ffe0ff */
/*02d0*/ IADD3 R12, R12, 0x10, RZ ; /* 0x000000100c0c7810 */
/* 0x000fc40007ffe0ff */
/*02e0*/ ISETP.LE.AND P1, PT, R17, UR4, PT ; /* 0x0000000411007c0c */
/* 0x000fe4000bf23270 */
/*02f0*/ IADD3.X R13, RZ, R13, RZ, P2, !PT ; /* 0x0000000dff0d7210 */
/* 0x000fe200017fe4ff */
/*0300*/ STS [R19], R22 ; /* 0x0000001613007388 */
/* 0x004fe80000000800 */
/*0310*/ STS [R19+0x400], R28 ; /* 0x0004001c13007388 */
/* 0x008fe80000000800 */
/*0320*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0330*/ LDS R29, [R18] ; /* 0x00000000121d7984 */
/* 0x000fe80000000800 */
/*0340*/ LDS.128 R8, [R15] ; /* 0x000000000f087984 */
/* 0x000e280000000c00 */
/*0350*/ LDS R24, [R18+0x40] ; /* 0x0000400012187984 */
/* 0x000e680000000800 */
/*0360*/ LDS R27, [R18+0x80] ; /* 0x00008000121b7984 */
/* 0x000ea80000000800 */
/*0370*/ LDS R26, [R18+0xc0] ; /* 0x0000c000121a7984 */
/* 0x000ee80000000800 */
/*0380*/ LDS R23, [R18+0x100] ; /* 0x0001000012177984 */
/* 0x000fe80000000800 */
/*0390*/ LDS.128 R4, [R15+0x10] ; /* 0x000010000f047984 */
/* 0x000f280000000c00 */
/*03a0*/ LDS R20, [R18+0x140] ; /* 0x0001400012147984 */
/* 0x000f680000000800 */
/*03b0*/ LDS R25, [R18+0x180] ; /* 0x0001800012197984 */
/* 0x000f680000000800 */
/*03c0*/ LDS R22, [R18+0x1c0] ; /* 0x0001c00012167984 */
/* 0x000f620000000800 */
/*03d0*/ IMAD R8, R29, R8, R21 ; /* 0x000000081d087224 */
/* 0x001fc600078e0215 */
/*03e0*/ LDS R21, [R18+0x200] ; /* 0x0002000012157984 */
/* 0x000fe20000000800 */
/*03f0*/ IMAD R8, R24, R9, R8 ; /* 0x0000000918087224 */
/* 0x002fc600078e0208 */
/*0400*/ LDS R24, [R18+0x240] ; /* 0x0002400012187984 */
/* 0x000fe20000000800 */
/*0410*/ IMAD R8, R27, R10, R8 ; /* 0x0000000a1b087224 */
/* 0x004fc800078e0208 */
/*0420*/ IMAD R26, R26, R11, R8 ; /* 0x0000000b1a1a7224 */
/* 0x008fe400078e0208 */
/*0430*/ LDS.128 R8, [R15+0x20] ; /* 0x000020000f087984 */
/* 0x000e240000000c00 */
/*0440*/ IMAD R4, R23, R4, R26 ; /* 0x0000000417047224 */
/* 0x010fe400078e021a */
/*0450*/ LDS R23, [R18+0x280] ; /* 0x0002800012177984 */
/* 0x000e640000000800 */
/*0460*/ IMAD R4, R20, R5, R4 ; /* 0x0000000514047224 */
/* 0x020fe400078e0204 */
/*0470*/ LDS R20, [R18+0x2c0] ; /* 0x0002c00012147984 */
/* 0x000ea40000000800 */
/*0480*/ IMAD R4, R25, R6, R4 ; /* 0x0000000619047224 */
/* 0x000fc400078e0204 */
/*0490*/ LDS R25, [R18+0x300] ; /* 0x0003000012197984 */
/* 0x000fe40000000800 */
/*04a0*/ IMAD R26, R22, R7, R4 ; /* 0x00000007161a7224 */
/* 0x000fe400078e0204 */
/*04b0*/ LDS.128 R4, [R15+0x30] ; /* 0x000030000f047984 */
/* 0x000ee80000000c00 */
/*04c0*/ LDS R22, [R18+0x340] ; /* 0x0003400012167984 */
/* 0x000f220000000800 */
/*04d0*/ IMAD R26, R21, R8, R26 ; /* 0x00000008151a7224 */
/* 0x001fc600078e021a */
/*04e0*/ LDS R21, [R18+0x380] ; /* 0x0003800012157984 */
/* 0x000e220000000800 */
/*04f0*/ IMAD R9, R24, R9, R26 ; /* 0x0000000918097224 */
/* 0x000fc600078e021a */
/*0500*/ LDS R8, [R18+0x3c0] ; /* 0x0003c00012087984 */
/* 0x000f620000000800 */
/*0510*/ IMAD R9, R23, R10, R9 ; /* 0x0000000a17097224 */
/* 0x002fc800078e0209 */
/*0520*/ IMAD R9, R20, R11, R9 ; /* 0x0000000b14097224 */
/* 0x004fc800078e0209 */
/*0530*/ IMAD R4, R25, R4, R9 ; /* 0x0000000419047224 */
/* 0x008fc800078e0209 */
/*0540*/ IMAD R4, R22, R5, R4 ; /* 0x0000000516047224 */
/* 0x010fe400078e0204 */
/*0550*/ IMAD.MOV.U32 R5, RZ, RZ, 0x10 ; /* 0x00000010ff057424 */
/* 0x000fc800078e00ff */
/*0560*/ IMAD R16, R5, c[0x0][0x180], R16 ; /* 0x0000600005107a24 */
/* 0x000fe400078e0210 */
/*0570*/ IMAD R21, R21, R6, R4 ; /* 0x0000000615157224 */
/* 0x001fc800078e0204 */
/*0580*/ IMAD R21, R8, R7, R21 ; /* 0x0000000708157224 */
/* 0x020fe200078e0215 */
/*0590*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*05a0*/ @!P1 BRA 0x1e0 ; /* 0xfffffc3000009947 */
/* 0x000fea000383ffff */
/*05b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*05c0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*05d0*/ IMAD R3, R3, c[0x0][0x180], R0 ; /* 0x0000600003037a24 */
/* 0x000fd200078e0200 */
/*05e0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*05f0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe2000c101906 */
/*0600*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0610*/ BRA 0x610; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15MatrixMulKernelPiS_S_iii
.globl _Z15MatrixMulKernelPiS_S_iii
.p2align 8
.type _Z15MatrixMulKernelPiS_S_iii,@function
_Z15MatrixMulKernelPiS_S_iii:
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x18
s_load_b32 s10, s[0:1], 0x20
v_bfe_u32 v6, v0, 10, 10
v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v1, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v5, s15, 4, v6
v_lshl_add_u32 v0, s14, 4, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s8, v5
v_cmp_gt_i32_e64 s2, s10, v0
s_cmp_lt_i32 s9, -14
s_cbranch_scc1 .LBB0_18
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 2, v1
s_add_i32 s3, s9, -1
v_lshlrev_b32_e32 v7, 6, v6
s_ashr_i32 s11, s3, 31
v_cmp_le_i32_e64 s12, s10, v0
v_add_nc_u32_e32 v8, 0x400, v2
s_lshr_b32 s11, s11, 28
v_mad_u64_u32 v[3:4], null, v5, s9, v[1:2]
s_add_i32 s3, s3, s11
v_cmp_le_i32_e64 s11, s8, v5
v_dual_mov_b32 v10, 0 :: v_dual_add_nc_u32 v9, v7, v2
v_mov_b32_e32 v2, 0
v_add_nc_u32_e32 v4, v8, v7
s_ashr_i32 s3, s3, 4
s_mov_b32 s14, 0
s_max_i32 s13, s3, 0
.LBB0_2:
s_mov_b32 s3, s11
s_mov_b32 s15, 0
s_and_saveexec_b32 s16, vcc_lo
s_lshl_b32 s17, s14, 4
s_mov_b32 s15, exec_lo
v_add_nc_u32_e32 v12, s17, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_le_i32_e64 s3, s9, v12
v_mov_b32_e32 v12, s17
s_and_not1_b32 s17, s11, exec_lo
s_and_b32 s3, s3, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s3, s17, s3
s_or_b32 exec_lo, exec_lo, s16
s_and_saveexec_b32 s16, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s3, exec_lo, s16
s_cbranch_execz .LBB0_6
s_and_not1_b32 s15, s15, exec_lo
ds_store_b32 v9, v10
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s16, s15
s_cbranch_execz .LBB0_8
v_add_nc_u32_e32 v13, v3, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v14, 31, v13
v_lshlrev_b64 v[13:14], 2, v[13:14]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v13, s3, s4, v13
v_add_co_ci_u32_e64 v14, s3, s5, v14, s3
global_load_b32 v13, v[13:14], off
s_waitcnt vmcnt(0)
ds_store_b32 v9, v13
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s16
s_mov_b32 s15, 0
s_mov_b32 s3, s12
s_and_saveexec_b32 s16, s2
v_lshl_add_u32 v11, s14, 4, v6
s_and_not1_b32 s17, s12, exec_lo
s_mov_b32 s15, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s3, s9, v11
s_and_b32 s3, s3, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s3, s17, s3
s_or_b32 exec_lo, exec_lo, s16
s_and_saveexec_b32 s16, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s3, exec_lo, s16
s_cbranch_execz .LBB0_12
s_and_not1_b32 s15, s15, exec_lo
ds_store_b32 v4, v10
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s16, s15
s_cbranch_execz .LBB0_14
v_mad_u64_u32 v[13:14], null, v11, s10, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v14, 31, v13
v_lshlrev_b64 v[13:14], 2, v[13:14]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v13, s3, s6, v13
v_add_co_ci_u32_e64 v14, s3, s7, v14, s3
global_load_b32 v13, v[13:14], off
s_waitcnt vmcnt(0)
ds_store_b32 v4, v13
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s16
v_mov_b32_e32 v13, v8
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_15:
v_add_nc_u32_e32 v14, s3, v7
s_add_i32 s3, s3, 4
ds_load_b32 v16, v13
ds_load_b32 v17, v14
s_cmp_eq_u32 s3, 64
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[14:15], null, v16, v17, v[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v2, v14 :: v_dual_add_nc_u32 v13, 64, v13
s_cbranch_scc0 .LBB0_15
s_add_i32 s3, s14, 1
s_cmp_eq_u32 s14, s13
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_18
s_mov_b32 s14, s3
s_branch .LBB0_2
.LBB0_18:
v_cmp_gt_i32_e32 vcc_lo, s8, v5
v_cmp_gt_i32_e64 s2, s10, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_20
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[3:4], null, v5, s10, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_20:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15MatrixMulKernelPiS_S_iii
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15MatrixMulKernelPiS_S_iii, .Lfunc_end0-_Z15MatrixMulKernelPiS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15MatrixMulKernelPiS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z15MatrixMulKernelPiS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003bc8d_00000000-6_matrix.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z15MatrixMulKernelPiS_S_iiiPiS_S_iii
.type _Z42__device_stub__Z15MatrixMulKernelPiS_S_iiiPiS_S_iii, @function
_Z42__device_stub__Z15MatrixMulKernelPiS_S_iiiPiS_S_iii:
.LFB3694:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15MatrixMulKernelPiS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z42__device_stub__Z15MatrixMulKernelPiS_S_iiiPiS_S_iii, .-_Z42__device_stub__Z15MatrixMulKernelPiS_S_iiiPiS_S_iii
.globl _Z15MatrixMulKernelPiS_S_iii
.type _Z15MatrixMulKernelPiS_S_iii, @function
_Z15MatrixMulKernelPiS_S_iii:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z15MatrixMulKernelPiS_S_iiiPiS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z15MatrixMulKernelPiS_S_iii, .-_Z15MatrixMulKernelPiS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Kernel Elpased Time: %.3f ms\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1680000, %edi
call malloc@PLT
movq %rax, %rbp
movl $2800000, %edi
call malloc@PLT
movq %rax, %rbx
movl $2400000, %edi
call malloc@PLT
movq %rax, %r12
leaq 8(%rsp), %rdi
movl $1680000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $2800000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $2400000, %esi
call cudaMalloc@PLT
movl $0, %eax
jmp .L14
.L12:
movl $0, 0(%rbp,%rax,4)
.L13:
addq $1, %rax
cmpq $420000, %rax
je .L23
.L14:
testb $1, %al
jne .L12
movl $1, 0(%rbp,%rax,4)
jmp .L13
.L23:
movl $0, %eax
jmp .L17
.L15:
movl $1, (%rbx,%rax,4)
.L16:
addq $1, %rax
cmpq $700000, %rax
je .L24
.L17:
testb $1, %al
jne .L15
movl $0, (%rbx,%rax,4)
jmp .L16
.L24:
movl $1, %ecx
movl $1680000, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $2800000, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $63, 48(%rsp)
movl $38, 52(%rsp)
movl $16, 60(%rsp)
movl $16, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L18:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $2400000, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movl $1000, %r9d
movl $700, %r8d
movl $600, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z42__device_stub__Z15MatrixMulKernelPiS_S_iiiPiS_S_iii
jmp .L18
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z15MatrixMulKernelPiS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z15MatrixMulKernelPiS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrix.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z30__device_stub__MatrixMulKernelPiS_S_iii # -- Begin function _Z30__device_stub__MatrixMulKernelPiS_S_iii
.p2align 4, 0x90
.type _Z30__device_stub__MatrixMulKernelPiS_S_iii,@function
_Z30__device_stub__MatrixMulKernelPiS_S_iii: # @_Z30__device_stub__MatrixMulKernelPiS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15MatrixMulKernelPiS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z30__device_stub__MatrixMulKernelPiS_S_iii, .Lfunc_end0-_Z30__device_stub__MatrixMulKernelPiS_S_iii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $176, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $1680000, %edi # imm = 0x19A280
callq malloc
movq %rax, %r15
movl $2800000, %edi # imm = 0x2AB980
callq malloc
movq %rax, %r14
movl $2400000, %edi # imm = 0x249F00
callq malloc
movq %rax, %rbx
leaq 48(%rsp), %rdi
movl $1680000, %esi # imm = 0x19A280
callq hipMalloc
leaq 40(%rsp), %rdi
movl $2800000, %esi # imm = 0x2AB980
callq hipMalloc
leaq 32(%rsp), %rdi
movl $2400000, %esi # imm = 0x249F00
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, %ecx
notl %ecx
andl $1, %ecx
movl %ecx, (%r15,%rax,4)
incq %rax
cmpq $420000, %rax # imm = 0x668A0
jne .LBB1_1
# %bb.2: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_3: # %.preheader
# =>This Inner Loop Header: Depth=1
movl %eax, %ecx
andl $1, %ecx
movl %ecx, (%r14,%rax,4)
incq %rax
cmpq $700000, %rax # imm = 0xAAE60
jne .LBB1_3
# %bb.4:
movq 48(%rsp), %rdi
movl $1680000, %edx # imm = 0x19A280
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movl $2800000, %edx # imm = 0x2AB980
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 24(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $163208757311, %rdi # imm = 0x260000003F
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl $600, 20(%rsp) # imm = 0x258
movl $700, 16(%rsp) # imm = 0x2BC
movl $1000, 12(%rsp) # imm = 0x3E8
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z15MatrixMulKernelPiS_S_iii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq (%rsp), %rdx
leaq 128(%rsp), %rdi
callq hipEventElapsedTime
movss 128(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rsi
movl $2400000, %edx # imm = 0x249F00
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
addq $176, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15MatrixMulKernelPiS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15MatrixMulKernelPiS_S_iii,@object # @_Z15MatrixMulKernelPiS_S_iii
.section .rodata,"a",@progbits
.globl _Z15MatrixMulKernelPiS_S_iii
.p2align 3, 0x0
_Z15MatrixMulKernelPiS_S_iii:
.quad _Z30__device_stub__MatrixMulKernelPiS_S_iii
.size _Z15MatrixMulKernelPiS_S_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Kernel Elpased Time: %.3f ms\n"
.size .L.str, 30
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15MatrixMulKernelPiS_S_iii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__MatrixMulKernelPiS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15MatrixMulKernelPiS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<math.h>
#include<stdlib.h>
#include<sys/time.h>
void usage(int exitStatus, char* programName);
int sumArray(int* array, int arraySize);
void getSeqPrimes(int* array, int arraySize);
__host__ __device__ int isPrime(int value);
__global__ void getPrimes(int* d_array, int N){
int threadId = 0;
threadId = blockIdx.x * blockDim.x + threadIdx.x;
int thisValue = 0;
thisValue = (threadId * 2) + 1;
if(threadId < 1)
return;
if(thisValue < N){
d_array[thisValue] = isPrime(thisValue);
}
}
__host__ __device__ int isPrime(int value){
int limit = 0;
limit = (int) sqrt( (float) value ) + 1;
int j = 0;
for(j = 2; j < limit; j++){
if(value % j == 0){
return 0;
}
}
return 1;
}
int main(int argc, char** argv){
if(argc != 3)
usage(1, argv[0]);
int N = 0;
N = (int) atoi(argv[1]);
int blockSize = 0;
blockSize = (int) atoi(argv[2]);
if(!(N | blockSize))
usage(2, argv[0]);
int arraySizeInBytes = 0;
arraySizeInBytes = 0;
arraySizeInBytes = sizeof(int) * (N + 1);
// index 0 : start time, index 1: end time
struct timeval sequentialTimes[2] = {{0,0},{0,0}};
struct timeval parallelTimes[2] = {{0,0},{0,0}};
// allocate our arrays
int* h_array = NULL;
int* d_array = NULL;
int* seqArray = NULL;
h_array = (int*) malloc(arraySizeInBytes);
seqArray = (int*) calloc(sizeof(int), N + 1);
// caculate the grid size
int gridSize = 0;
gridSize = (int)ceil((N + 1) / 2.0 / blockSize);
// start parallel timer
gettimeofday( &(parallelTimes[0]), NULL);
// allocate device memory for the array
cudaMalloc(&d_array, arraySizeInBytes);
// zero the memory in cuda
cudaMemset(d_array, 0, arraySizeInBytes);
// run the kernel
getPrimes<<<gridSize, blockSize>>>(d_array, N);
// copy the results back to the host array
cudaMemcpy(h_array, d_array, arraySizeInBytes, cudaMemcpyDeviceToHost);
// release the device array
cudaFree(d_array);
// stop parallel timer
gettimeofday( &(parallelTimes[1]) , NULL);
// start sequential timer
gettimeofday( &(sequentialTimes[0]), NULL);
// run the sequential version
getSeqPrimes(seqArray, N + 1);
// stop sequential timer
gettimeofday( &(sequentialTimes[1]), NULL);
// calculated time values
double parallelSeconds[2] = {0.0, 0.0};
parallelSeconds[0] = parallelTimes[0].tv_sec + ((double)parallelTimes[0].tv_usec / 1000000);
parallelSeconds[1] = parallelTimes[1].tv_sec + ((double)parallelTimes[1].tv_usec / 1000000);
double sequentialSeconds[2] = {0.0, 0.0};
sequentialSeconds[0] = sequentialTimes[0].tv_sec + ((double)sequentialTimes[0].tv_usec / 1000000);
sequentialSeconds[1] = sequentialTimes[1].tv_sec + ((double)sequentialTimes[1].tv_usec / 1000000);
double parallelCost = 0;
parallelCost = parallelSeconds[1] - parallelSeconds[0];
double sequentialCost = 0;
sequentialCost = sequentialSeconds[1] - sequentialSeconds[0];
double speedup = 0;
speedup = sequentialCost / parallelCost;
int seqSum = 0;
seqSum = sumArray(seqArray, N + 1);
int parSum = 0;
parSum = sumArray(h_array, N + 1);
printf(" N: %d\n", N);
printf(" blockSize: %d\n", blockSize);
printf(" gridSize: %d\n", gridSize);
printf("sequential prime count: %d\n", seqSum);
printf(" parallel prime count: %d\n", parSum);
printf(" parallel time cost: %lf\n", parallelCost);
printf(" sequential time cost: %lf\n", sequentialCost);
printf(" speedup: %lf\n", speedup);
free(h_array);
free(seqArray);
return 0;
}
void getSeqPrimes(int* array, int arraySize){
int thisValue = 0;
for(thisValue = 3; thisValue < arraySize; thisValue += 2){
array[thisValue] = isPrime(thisValue);
}
}
int sumArray(int* array, int arraySize){
int sum = 0;
int index = 0;
for(; index < arraySize; ++index){
sum += array[index];
}
return sum;
}
void usage(int exitStatus, char* programName){
fprintf(stderr, "usage: %s N blockSize\n", programName);
exit(exitStatus);
} | code for sm_80
Function : _Z9getPrimesPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ LEA R0, R2, 0x1, 0x1 ; /* 0x0000000102007811 */
/* 0x000fc800078e08ff */
/*0050*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fc80003f06270 */
/*0060*/ ISETP.LT.OR P0, PT, R2, 0x1, P0 ; /* 0x000000010200780c */
/* 0x000fda0000701670 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ I2F R2, R0 ; /* 0x0000000000027306 */
/* 0x000e220000201400 */
/*0090*/ BSSY B0, 0x190 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*00a0*/ IADD3 R4, R2, -0xd000000, RZ ; /* 0xf300000002047810 */
/* 0x001fcc0007ffe0ff */
/*00b0*/ MUFU.RSQ R3, R2 ; /* 0x0000000200037308 */
/* 0x0000620000001400 */
/*00c0*/ ISETP.GT.U32.AND P0, PT, R4, 0x727fffff, PT ; /* 0x727fffff0400780c */
/* 0x000fda0003f04070 */
/*00d0*/ @!P0 BRA 0x140 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*00e0*/ BSSY B1, 0x120 ; /* 0x0000003000017945 */
/* 0x003fe20003800000 */
/*00f0*/ MOV R8, 0x110 ; /* 0x0000011000087802 */
/* 0x000fe40000000f00 */
/*0100*/ CALL.REL.NOINC 0x430 ; /* 0x0000032000007944 */
/* 0x000fea0003c00000 */
/*0110*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0120*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0004 */
/*0130*/ BRA 0x180 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0140*/ FMUL.FTZ R5, R2, R3 ; /* 0x0000000302057220 */
/* 0x003fe40000410000 */
/*0150*/ FMUL.FTZ R3, R3, 0.5 ; /* 0x3f00000003037820 */
/* 0x000fe40000410000 */
/*0160*/ FFMA R2, -R5, R5, R2 ; /* 0x0000000505027223 */
/* 0x000fc80000000102 */
/*0170*/ FFMA R2, R2, R3, R5 ; /* 0x0000000302027223 */
/* 0x000fe40000000005 */
/*0180*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0190*/ F2I.TRUNC.NTZ R9, R2 ; /* 0x0000000200097305 */
/* 0x000e22000020f100 */
/*01a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*01b0*/ BSSY B0, 0x3f0 ; /* 0x0000023000007945 */
/* 0x000fe20003800000 */
/*01c0*/ HFMA2.MMA R5, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff057435 */
/* 0x000fe200000001ff */
/*01d0*/ ISETP.GE.AND P0, PT, R9, 0x2, PT ; /* 0x000000020900780c */
/* 0x001fda0003f06270 */
/*01e0*/ @!P0 BRA 0x3e0 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*01f0*/ IABS R6, R0 ; /* 0x0000000000067213 */
/* 0x000fe20000000000 */
/*0200*/ IMAD.MOV.U32 R4, RZ, RZ, 0x2 ; /* 0x00000002ff047424 */
/* 0x000fca00078e00ff */
/*0210*/ IABS R8, R4.reuse ; /* 0x0000000400087213 */
/* 0x080fe40000000000 */
/*0220*/ IABS R10, R4 ; /* 0x00000004000a7213 */
/* 0x000fe40000000000 */
/*0230*/ I2F.RP R5, R8 ; /* 0x0000000800057306 */
/* 0x000e220000209400 */
/*0240*/ ISETP.GE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f46270 */
/*0250*/ IMAD.MOV R10, RZ, RZ, -R10 ; /* 0x000000ffff0a7224 */
/* 0x000fca00078e0a0a */
/*0260*/ MUFU.RCP R5, R5 ; /* 0x0000000500057308 */
/* 0x001e240000001000 */
/*0270*/ IADD3 R2, R5, 0xffffffe, RZ ; /* 0x0ffffffe05027810 */
/* 0x001fe40007ffe0ff */
/*0280*/ IABS R5, R0 ; /* 0x0000000000057213 */
/* 0x000fc80000000000 */
/*0290*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*02a0*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*02b0*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a03 */
/*02c0*/ IMAD R7, R7, R8, RZ ; /* 0x0000000807077224 */
/* 0x000fca00078e02ff */
/*02d0*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*02e0*/ IMAD.HI.U32 R3, R3, R6, RZ ; /* 0x0000000603037227 */
/* 0x000fc800078e00ff */
/*02f0*/ IMAD R3, R3, R10, R5 ; /* 0x0000000a03037224 */
/* 0x000fe200078e0205 */
/*0300*/ MOV R5, RZ ; /* 0x000000ff00057202 */
/* 0x000fc80000000f00 */
/*0310*/ ISETP.GT.U32.AND P0, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fda0003f04070 */
/*0320*/ @!P0 IMAD.IADD R3, R3, 0x1, -R8 ; /* 0x0000000103038824 */
/* 0x000fe200078e0a08 */
/*0330*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc80003f05270 */
/*0340*/ ISETP.GT.U32.AND P1, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fda0003f24070 */
/*0350*/ @!P1 IADD3 R3, R3, -R8, RZ ; /* 0x8000000803039210 */
/* 0x000fca0007ffe0ff */
/*0360*/ @!P2 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff03a224 */
/* 0x000fe200078e0a03 */
/*0370*/ @!P0 LOP3.LUT R3, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff038212 */
/* 0x000fc800078e33ff */
/*0380*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*0390*/ @!P0 BRA 0x3e0 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*03a0*/ ISETP.GE.AND P0, PT, R4.reuse, R9, PT ; /* 0x000000090400720c */
/* 0x040fe40003f06270 */
/*03b0*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fd60007ffe0ff */
/*03c0*/ @!P0 BRA 0x210 ; /* 0xfffffe4000008947 */
/* 0x000fea000383ffff */
/*03d0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fe400078e00ff */
/*03e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03f0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*0400*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0410*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0420*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0430*/ LOP3.LUT P0, RZ, R2, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff02ff7812 */
/* 0x000fda000780c0ff */
/*0440*/ @!P0 IMAD.MOV.U32 R3, RZ, RZ, R2 ; /* 0x000000ffff038224 */
/* 0x000fe200078e0002 */
/*0450*/ @!P0 BRA 0x560 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0460*/ FSETP.GEU.FTZ.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720b */
/* 0x000fda0003f1e000 */
/*0470*/ @!P0 MOV R3, 0x7fffffff ; /* 0x7fffffff00038802 */
/* 0x000fe20000000f00 */
/*0480*/ @!P0 BRA 0x560 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0490*/ FSETP.GTU.FTZ.AND P0, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fda0003f1c200 */
/*04a0*/ @P0 FADD.FTZ R3, R2, 1 ; /* 0x3f80000002030421 */
/* 0x000fe20000010000 */
/*04b0*/ @P0 BRA 0x560 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*04c0*/ FSETP.NEU.FTZ.AND P0, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fda0003f1d200 */
/*04d0*/ @P0 FFMA R4, R2, 1.84467440737095516160e+19, RZ ; /* 0x5f80000002040823 */
/* 0x000fc800000000ff */
/*04e0*/ @P0 MUFU.RSQ R3, R4 ; /* 0x0000000400030308 */
/* 0x000e240000001400 */
/*04f0*/ @P0 FMUL.FTZ R5, R4, R3 ; /* 0x0000000304050220 */
/* 0x001fe40000410000 */
/*0500*/ @P0 FMUL.FTZ R7, R3, 0.5 ; /* 0x3f00000003070820 */
/* 0x000fe40000410000 */
/*0510*/ @P0 FADD.FTZ R6, -R5.reuse, -RZ ; /* 0x800000ff05060221 */
/* 0x040fe40000010100 */
/*0520*/ @!P0 IMAD.MOV.U32 R3, RZ, RZ, R2 ; /* 0x000000ffff038224 */
/* 0x000fe400078e0002 */
/*0530*/ @P0 FFMA R6, R5, R6, R4 ; /* 0x0000000605060223 */
/* 0x000fc80000000004 */
/*0540*/ @P0 FFMA R6, R6, R7, R5 ; /* 0x0000000706060223 */
/* 0x000fc80000000005 */
/*0550*/ @P0 FMUL.FTZ R3, R6, 2.3283064365386962891e-10 ; /* 0x2f80000006030820 */
/* 0x000fca0000410000 */
/*0560*/ MOV R4, R3 ; /* 0x0000000300047202 */
/* 0x000fe20000000f00 */
/*0570*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0580*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x000fca00078e0008 */
/*0590*/ RET.REL.NODEC R2 0x0 ; /* 0xfffffa6002007950 */
/* 0x000fea0003c3ffff */
/*05a0*/ BRA 0x5a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<math.h>
#include<stdlib.h>
#include<sys/time.h>
void usage(int exitStatus, char* programName);
int sumArray(int* array, int arraySize);
void getSeqPrimes(int* array, int arraySize);
__host__ __device__ int isPrime(int value);
__global__ void getPrimes(int* d_array, int N){
int threadId = 0;
threadId = blockIdx.x * blockDim.x + threadIdx.x;
int thisValue = 0;
thisValue = (threadId * 2) + 1;
if(threadId < 1)
return;
if(thisValue < N){
d_array[thisValue] = isPrime(thisValue);
}
}
__host__ __device__ int isPrime(int value){
int limit = 0;
limit = (int) sqrt( (float) value ) + 1;
int j = 0;
for(j = 2; j < limit; j++){
if(value % j == 0){
return 0;
}
}
return 1;
}
int main(int argc, char** argv){
if(argc != 3)
usage(1, argv[0]);
int N = 0;
N = (int) atoi(argv[1]);
int blockSize = 0;
blockSize = (int) atoi(argv[2]);
if(!(N | blockSize))
usage(2, argv[0]);
int arraySizeInBytes = 0;
arraySizeInBytes = 0;
arraySizeInBytes = sizeof(int) * (N + 1);
// index 0 : start time, index 1: end time
struct timeval sequentialTimes[2] = {{0,0},{0,0}};
struct timeval parallelTimes[2] = {{0,0},{0,0}};
// allocate our arrays
int* h_array = NULL;
int* d_array = NULL;
int* seqArray = NULL;
h_array = (int*) malloc(arraySizeInBytes);
seqArray = (int*) calloc(sizeof(int), N + 1);
// caculate the grid size
int gridSize = 0;
gridSize = (int)ceil((N + 1) / 2.0 / blockSize);
// start parallel timer
gettimeofday( &(parallelTimes[0]), NULL);
// allocate device memory for the array
cudaMalloc(&d_array, arraySizeInBytes);
// zero the memory in cuda
cudaMemset(d_array, 0, arraySizeInBytes);
// run the kernel
getPrimes<<<gridSize, blockSize>>>(d_array, N);
// copy the results back to the host array
cudaMemcpy(h_array, d_array, arraySizeInBytes, cudaMemcpyDeviceToHost);
// release the device array
cudaFree(d_array);
// stop parallel timer
gettimeofday( &(parallelTimes[1]) , NULL);
// start sequential timer
gettimeofday( &(sequentialTimes[0]), NULL);
// run the sequential version
getSeqPrimes(seqArray, N + 1);
// stop sequential timer
gettimeofday( &(sequentialTimes[1]), NULL);
// calculated time values
double parallelSeconds[2] = {0.0, 0.0};
parallelSeconds[0] = parallelTimes[0].tv_sec + ((double)parallelTimes[0].tv_usec / 1000000);
parallelSeconds[1] = parallelTimes[1].tv_sec + ((double)parallelTimes[1].tv_usec / 1000000);
double sequentialSeconds[2] = {0.0, 0.0};
sequentialSeconds[0] = sequentialTimes[0].tv_sec + ((double)sequentialTimes[0].tv_usec / 1000000);
sequentialSeconds[1] = sequentialTimes[1].tv_sec + ((double)sequentialTimes[1].tv_usec / 1000000);
double parallelCost = 0;
parallelCost = parallelSeconds[1] - parallelSeconds[0];
double sequentialCost = 0;
sequentialCost = sequentialSeconds[1] - sequentialSeconds[0];
double speedup = 0;
speedup = sequentialCost / parallelCost;
int seqSum = 0;
seqSum = sumArray(seqArray, N + 1);
int parSum = 0;
parSum = sumArray(h_array, N + 1);
printf(" N: %d\n", N);
printf(" blockSize: %d\n", blockSize);
printf(" gridSize: %d\n", gridSize);
printf("sequential prime count: %d\n", seqSum);
printf(" parallel prime count: %d\n", parSum);
printf(" parallel time cost: %lf\n", parallelCost);
printf(" sequential time cost: %lf\n", sequentialCost);
printf(" speedup: %lf\n", speedup);
free(h_array);
free(seqArray);
return 0;
}
void getSeqPrimes(int* array, int arraySize){
int thisValue = 0;
for(thisValue = 3; thisValue < arraySize; thisValue += 2){
array[thisValue] = isPrime(thisValue);
}
}
int sumArray(int* array, int arraySize){
int sum = 0;
int index = 0;
for(; index < arraySize; ++index){
sum += array[index];
}
return sum;
}
void usage(int exitStatus, char* programName){
fprintf(stderr, "usage: %s N blockSize\n", programName);
exit(exitStatus);
} | .file "tmpxft_0019588d_00000000-6_lab1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7isPrimei
.type _Z7isPrimei, @function
_Z7isPrimei:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %edi, %ebx
pxor %xmm0, %xmm0
cvtsi2ssl %edi, %xmm0
pxor %xmm1, %xmm1
ucomiss %xmm0, %xmm1
ja .L13
sqrtss %xmm0, %xmm0
.L6:
cvttss2sil %xmm0, %esi
cmpl $1, %esi
jle .L10
movl %ebx, %edi
andl $1, %edi
je .L3
movl $2, %ecx
.L8:
addl $1, %ecx
cmpl %ecx, %esi
jl .L3
movl %ebx, %eax
cltd
idivl %ecx
testl %edx, %edx
jne .L8
movl %edx, %edi
.L3:
movl %edi, %eax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
call sqrtf@PLT
jmp .L6
.L10:
movl $1, %edi
jmp .L3
.cfi_endproc
.LFE2057:
.size _Z7isPrimei, .-_Z7isPrimei
.globl _Z12getSeqPrimesPii
.type _Z12getSeqPrimesPii, @function
_Z12getSeqPrimesPii:
.LFB2059:
.cfi_startproc
endbr64
cmpl $3, %esi
jle .L20
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbp
subl $4, %esi
shrl %esi
leal (%rsi,%rsi), %r12d
addq $5, %r12
movl $3, %ebx
.L17:
movl %ebx, %edi
call _Z7isPrimei
movl %eax, 0(%rbp,%rbx,4)
addq $2, %rbx
cmpq %r12, %rbx
jne .L17
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE2059:
.size _Z12getSeqPrimesPii, .-_Z12getSeqPrimesPii
.globl _Z8sumArrayPii
.type _Z8sumArrayPii, @function
_Z8sumArrayPii:
.LFB2060:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L26
movq %rdi, %rax
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rcx
movl $0, %edx
.L25:
addl (%rax), %edx
addq $4, %rax
cmpq %rcx, %rax
jne .L25
.L23:
movl %edx, %eax
ret
.L26:
movl $0, %edx
jmp .L23
.cfi_endproc
.LFE2060:
.size _Z8sumArrayPii, .-_Z8sumArrayPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "usage: %s N blockSize\n"
.text
.globl _Z5usageiPc
.type _Z5usageiPc, @function
_Z5usageiPc:
.LFB2061:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %edi, %ebx
movq %rsi, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE2061:
.size _Z5usageiPc, .-_Z5usageiPc
.globl _Z29__device_stub__Z9getPrimesPiiPii
.type _Z29__device_stub__Z9getPrimesPiiPii, @function
_Z29__device_stub__Z9getPrimesPiiPii:
.LFB2086:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L34
.L30:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L35
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9getPrimesPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L30
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z29__device_stub__Z9getPrimesPiiPii, .-_Z29__device_stub__Z9getPrimesPiiPii
.globl _Z9getPrimesPii
.type _Z9getPrimesPii, @function
_Z9getPrimesPii:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z9getPrimesPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z9getPrimesPii, .-_Z9getPrimesPii
.section .rodata.str1.1
.LC7:
.string " N: %d\n"
.LC8:
.string " blockSize: %d\n"
.LC9:
.string " gridSize: %d\n"
.LC10:
.string "sequential prime count: %d\n"
.LC11:
.string " parallel prime count: %d\n"
.LC12:
.string " parallel time cost: %lf\n"
.LC13:
.string " sequential time cost: %lf\n"
.LC14:
.string " speedup: %lf\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
cmpl $3, %edi
jne .L47
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, 24(%rsp)
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movl %eax, 28(%rsp)
movl %ebx, %eax
orl %r12d, %eax
je .L48
addl $1, %ebx
movslq %ebx, %r13
movq $0, 64(%rsp)
movq $0, 72(%rsp)
movq $0, 80(%rsp)
movq $0, 88(%rsp)
movq $0, 96(%rsp)
movq $0, 104(%rsp)
movq $0, 112(%rsp)
movq $0, 120(%rsp)
movq $0, 32(%rsp)
leal 0(,%rbx,4), %ebp
movslq %ebp, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r14
movq %r13, %rsi
movl $4, %edi
call calloc@PLT
movq %rax, %r13
pxor %xmm0, %xmm0
cvtsi2sdl %ebx, %xmm0
mulsd .LC2(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdl %r12d, %xmm1
divsd %xmm1, %xmm0
movapd %xmm0, %xmm3
movsd .LC15(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC3(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L43
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC5(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L43:
cvttsd2sil %xmm3, %r15d
leaq 96(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
leaq 32(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movq %rbp, %rdx
movl $0, %esi
movq 32(%rsp), %rdi
call cudaMemset@PLT
movl %r12d, 52(%rsp)
movl $1, 56(%rsp)
movl %r15d, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L49
.L44:
movl $2, %ecx
movq %rbp, %rdx
movq 32(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
leaq 112(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl %ebx, %esi
movq %r13, %rdi
call _Z12getSeqPrimesPii
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 120(%rsp), %xmm0
movsd .LC6(%rip), %xmm2
divsd %xmm2, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 112(%rsp), %xmm1
addsd %xmm0, %xmm1
pxor %xmm0, %xmm0
cvtsi2sdq 104(%rsp), %xmm0
divsd %xmm2, %xmm0
pxor %xmm3, %xmm3
cvtsi2sdq 96(%rsp), %xmm3
addsd %xmm3, %xmm0
movapd %xmm1, %xmm6
subsd %xmm0, %xmm6
pxor %xmm0, %xmm0
cvtsi2sdq 88(%rsp), %xmm0
divsd %xmm2, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 80(%rsp), %xmm1
addsd %xmm0, %xmm1
pxor %xmm0, %xmm0
cvtsi2sdq 72(%rsp), %xmm0
divsd %xmm2, %xmm0
pxor %xmm2, %xmm2
cvtsi2sdq 64(%rsp), %xmm2
addsd %xmm2, %xmm0
subsd %xmm0, %xmm1
movsd %xmm1, 16(%rsp)
movapd %xmm1, %xmm5
movsd %xmm6, 8(%rsp)
divsd %xmm6, %xmm5
movq %xmm5, %rbp
movl %ebx, %esi
movq %r13, %rdi
call _Z8sumArrayPii
movl %eax, %r12d
movl %ebx, %esi
movq %r14, %rdi
call _Z8sumArrayPii
movl %eax, %ebx
movl 24(%rsp), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 28(%rsp), %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r15d, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 16(%rsp), %xmm0
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %xmm0
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L50
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L51
movq (%rsi), %rsi
movl $1, %edi
call _Z5usageiPc
.L51:
call __stack_chk_fail@PLT
.L48:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L52
movq 0(%rbp), %rsi
movl $2, %edi
call _Z5usageiPc
.L52:
call __stack_chk_fail@PLT
.L49:
movl 24(%rsp), %esi
movq 32(%rsp), %rdi
call _Z29__device_stub__Z9getPrimesPiiPii
jmp .L44
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC16:
.string "_Z9getPrimesPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z9getPrimesPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1071644672
.align 8
.LC3:
.long 0
.long 1127219200
.align 8
.LC5:
.long 0
.long 1072693248
.align 8
.LC6:
.long 0
.long 1093567616
.align 8
.LC15:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<math.h>
#include<stdlib.h>
#include<sys/time.h>
void usage(int exitStatus, char* programName);
int sumArray(int* array, int arraySize);
void getSeqPrimes(int* array, int arraySize);
__host__ __device__ int isPrime(int value);
__global__ void getPrimes(int* d_array, int N){
int threadId = 0;
threadId = blockIdx.x * blockDim.x + threadIdx.x;
int thisValue = 0;
thisValue = (threadId * 2) + 1;
if(threadId < 1)
return;
if(thisValue < N){
d_array[thisValue] = isPrime(thisValue);
}
}
__host__ __device__ int isPrime(int value){
int limit = 0;
limit = (int) sqrt( (float) value ) + 1;
int j = 0;
for(j = 2; j < limit; j++){
if(value % j == 0){
return 0;
}
}
return 1;
}
int main(int argc, char** argv){
if(argc != 3)
usage(1, argv[0]);
int N = 0;
N = (int) atoi(argv[1]);
int blockSize = 0;
blockSize = (int) atoi(argv[2]);
if(!(N | blockSize))
usage(2, argv[0]);
int arraySizeInBytes = 0;
arraySizeInBytes = 0;
arraySizeInBytes = sizeof(int) * (N + 1);
// index 0 : start time, index 1: end time
struct timeval sequentialTimes[2] = {{0,0},{0,0}};
struct timeval parallelTimes[2] = {{0,0},{0,0}};
// allocate our arrays
int* h_array = NULL;
int* d_array = NULL;
int* seqArray = NULL;
h_array = (int*) malloc(arraySizeInBytes);
seqArray = (int*) calloc(sizeof(int), N + 1);
// caculate the grid size
int gridSize = 0;
gridSize = (int)ceil((N + 1) / 2.0 / blockSize);
// start parallel timer
gettimeofday( &(parallelTimes[0]), NULL);
// allocate device memory for the array
cudaMalloc(&d_array, arraySizeInBytes);
// zero the memory in cuda
cudaMemset(d_array, 0, arraySizeInBytes);
// run the kernel
getPrimes<<<gridSize, blockSize>>>(d_array, N);
// copy the results back to the host array
cudaMemcpy(h_array, d_array, arraySizeInBytes, cudaMemcpyDeviceToHost);
// release the device array
cudaFree(d_array);
// stop parallel timer
gettimeofday( &(parallelTimes[1]) , NULL);
// start sequential timer
gettimeofday( &(sequentialTimes[0]), NULL);
// run the sequential version
getSeqPrimes(seqArray, N + 1);
// stop sequential timer
gettimeofday( &(sequentialTimes[1]), NULL);
// calculated time values
double parallelSeconds[2] = {0.0, 0.0};
parallelSeconds[0] = parallelTimes[0].tv_sec + ((double)parallelTimes[0].tv_usec / 1000000);
parallelSeconds[1] = parallelTimes[1].tv_sec + ((double)parallelTimes[1].tv_usec / 1000000);
double sequentialSeconds[2] = {0.0, 0.0};
sequentialSeconds[0] = sequentialTimes[0].tv_sec + ((double)sequentialTimes[0].tv_usec / 1000000);
sequentialSeconds[1] = sequentialTimes[1].tv_sec + ((double)sequentialTimes[1].tv_usec / 1000000);
double parallelCost = 0;
parallelCost = parallelSeconds[1] - parallelSeconds[0];
double sequentialCost = 0;
sequentialCost = sequentialSeconds[1] - sequentialSeconds[0];
double speedup = 0;
speedup = sequentialCost / parallelCost;
int seqSum = 0;
seqSum = sumArray(seqArray, N + 1);
int parSum = 0;
parSum = sumArray(h_array, N + 1);
printf(" N: %d\n", N);
printf(" blockSize: %d\n", blockSize);
printf(" gridSize: %d\n", gridSize);
printf("sequential prime count: %d\n", seqSum);
printf(" parallel prime count: %d\n", parSum);
printf(" parallel time cost: %lf\n", parallelCost);
printf(" sequential time cost: %lf\n", sequentialCost);
printf(" speedup: %lf\n", speedup);
free(h_array);
free(seqArray);
return 0;
}
void getSeqPrimes(int* array, int arraySize){
int thisValue = 0;
for(thisValue = 3; thisValue < arraySize; thisValue += 2){
array[thisValue] = isPrime(thisValue);
}
}
int sumArray(int* array, int arraySize){
int sum = 0;
int index = 0;
for(; index < arraySize; ++index){
sum += array[index];
}
return sum;
}
void usage(int exitStatus, char* programName){
fprintf(stderr, "usage: %s N blockSize\n", programName);
exit(exitStatus);
} | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<math.h>
#include<stdlib.h>
#include<sys/time.h>
void usage(int exitStatus, char* programName);
int sumArray(int* array, int arraySize);
void getSeqPrimes(int* array, int arraySize);
__host__ __device__ int isPrime(int value);
__global__ void getPrimes(int* d_array, int N){
int threadId = 0;
threadId = blockIdx.x * blockDim.x + threadIdx.x;
int thisValue = 0;
thisValue = (threadId * 2) + 1;
if(threadId < 1)
return;
if(thisValue < N){
d_array[thisValue] = isPrime(thisValue);
}
}
__host__ __device__ int isPrime(int value){
int limit = 0;
limit = (int) sqrt( (float) value ) + 1;
int j = 0;
for(j = 2; j < limit; j++){
if(value % j == 0){
return 0;
}
}
return 1;
}
int main(int argc, char** argv){
if(argc != 3)
usage(1, argv[0]);
int N = 0;
N = (int) atoi(argv[1]);
int blockSize = 0;
blockSize = (int) atoi(argv[2]);
if(!(N | blockSize))
usage(2, argv[0]);
int arraySizeInBytes = 0;
arraySizeInBytes = 0;
arraySizeInBytes = sizeof(int) * (N + 1);
// index 0 : start time, index 1: end time
struct timeval sequentialTimes[2] = {{0,0},{0,0}};
struct timeval parallelTimes[2] = {{0,0},{0,0}};
// allocate our arrays
int* h_array = NULL;
int* d_array = NULL;
int* seqArray = NULL;
h_array = (int*) malloc(arraySizeInBytes);
seqArray = (int*) calloc(sizeof(int), N + 1);
// caculate the grid size
int gridSize = 0;
gridSize = (int)ceil((N + 1) / 2.0 / blockSize);
// start parallel timer
gettimeofday( &(parallelTimes[0]), NULL);
// allocate device memory for the array
hipMalloc(&d_array, arraySizeInBytes);
// zero the memory in cuda
hipMemset(d_array, 0, arraySizeInBytes);
// run the kernel
getPrimes<<<gridSize, blockSize>>>(d_array, N);
// copy the results back to the host array
hipMemcpy(h_array, d_array, arraySizeInBytes, hipMemcpyDeviceToHost);
// release the device array
hipFree(d_array);
// stop parallel timer
gettimeofday( &(parallelTimes[1]) , NULL);
// start sequential timer
gettimeofday( &(sequentialTimes[0]), NULL);
// run the sequential version
getSeqPrimes(seqArray, N + 1);
// stop sequential timer
gettimeofday( &(sequentialTimes[1]), NULL);
// calculated time values
double parallelSeconds[2] = {0.0, 0.0};
parallelSeconds[0] = parallelTimes[0].tv_sec + ((double)parallelTimes[0].tv_usec / 1000000);
parallelSeconds[1] = parallelTimes[1].tv_sec + ((double)parallelTimes[1].tv_usec / 1000000);
double sequentialSeconds[2] = {0.0, 0.0};
sequentialSeconds[0] = sequentialTimes[0].tv_sec + ((double)sequentialTimes[0].tv_usec / 1000000);
sequentialSeconds[1] = sequentialTimes[1].tv_sec + ((double)sequentialTimes[1].tv_usec / 1000000);
double parallelCost = 0;
parallelCost = parallelSeconds[1] - parallelSeconds[0];
double sequentialCost = 0;
sequentialCost = sequentialSeconds[1] - sequentialSeconds[0];
double speedup = 0;
speedup = sequentialCost / parallelCost;
int seqSum = 0;
seqSum = sumArray(seqArray, N + 1);
int parSum = 0;
parSum = sumArray(h_array, N + 1);
printf(" N: %d\n", N);
printf(" blockSize: %d\n", blockSize);
printf(" gridSize: %d\n", gridSize);
printf("sequential prime count: %d\n", seqSum);
printf(" parallel prime count: %d\n", parSum);
printf(" parallel time cost: %lf\n", parallelCost);
printf(" sequential time cost: %lf\n", sequentialCost);
printf(" speedup: %lf\n", speedup);
free(h_array);
free(seqArray);
return 0;
}
void getSeqPrimes(int* array, int arraySize){
int thisValue = 0;
for(thisValue = 3; thisValue < arraySize; thisValue += 2){
array[thisValue] = isPrime(thisValue);
}
}
int sumArray(int* array, int arraySize){
int sum = 0;
int index = 0;
for(; index < arraySize; ++index){
sum += array[index];
}
return sum;
}
void usage(int exitStatus, char* programName){
fprintf(stderr, "usage: %s N blockSize\n", programName);
exit(exitStatus);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<math.h>
#include<stdlib.h>
#include<sys/time.h>
void usage(int exitStatus, char* programName);
int sumArray(int* array, int arraySize);
void getSeqPrimes(int* array, int arraySize);
__host__ __device__ int isPrime(int value);
__global__ void getPrimes(int* d_array, int N){
int threadId = 0;
threadId = blockIdx.x * blockDim.x + threadIdx.x;
int thisValue = 0;
thisValue = (threadId * 2) + 1;
if(threadId < 1)
return;
if(thisValue < N){
d_array[thisValue] = isPrime(thisValue);
}
}
__host__ __device__ int isPrime(int value){
int limit = 0;
limit = (int) sqrt( (float) value ) + 1;
int j = 0;
for(j = 2; j < limit; j++){
if(value % j == 0){
return 0;
}
}
return 1;
}
int main(int argc, char** argv){
if(argc != 3)
usage(1, argv[0]);
int N = 0;
N = (int) atoi(argv[1]);
int blockSize = 0;
blockSize = (int) atoi(argv[2]);
if(!(N | blockSize))
usage(2, argv[0]);
int arraySizeInBytes = 0;
arraySizeInBytes = 0;
arraySizeInBytes = sizeof(int) * (N + 1);
// index 0 : start time, index 1: end time
struct timeval sequentialTimes[2] = {{0,0},{0,0}};
struct timeval parallelTimes[2] = {{0,0},{0,0}};
// allocate our arrays
int* h_array = NULL;
int* d_array = NULL;
int* seqArray = NULL;
h_array = (int*) malloc(arraySizeInBytes);
seqArray = (int*) calloc(sizeof(int), N + 1);
// caculate the grid size
int gridSize = 0;
gridSize = (int)ceil((N + 1) / 2.0 / blockSize);
// start parallel timer
gettimeofday( &(parallelTimes[0]), NULL);
// allocate device memory for the array
hipMalloc(&d_array, arraySizeInBytes);
// zero the memory in cuda
hipMemset(d_array, 0, arraySizeInBytes);
// run the kernel
getPrimes<<<gridSize, blockSize>>>(d_array, N);
// copy the results back to the host array
hipMemcpy(h_array, d_array, arraySizeInBytes, hipMemcpyDeviceToHost);
// release the device array
hipFree(d_array);
// stop parallel timer
gettimeofday( &(parallelTimes[1]) , NULL);
// start sequential timer
gettimeofday( &(sequentialTimes[0]), NULL);
// run the sequential version
getSeqPrimes(seqArray, N + 1);
// stop sequential timer
gettimeofday( &(sequentialTimes[1]), NULL);
// calculated time values
double parallelSeconds[2] = {0.0, 0.0};
parallelSeconds[0] = parallelTimes[0].tv_sec + ((double)parallelTimes[0].tv_usec / 1000000);
parallelSeconds[1] = parallelTimes[1].tv_sec + ((double)parallelTimes[1].tv_usec / 1000000);
double sequentialSeconds[2] = {0.0, 0.0};
sequentialSeconds[0] = sequentialTimes[0].tv_sec + ((double)sequentialTimes[0].tv_usec / 1000000);
sequentialSeconds[1] = sequentialTimes[1].tv_sec + ((double)sequentialTimes[1].tv_usec / 1000000);
double parallelCost = 0;
parallelCost = parallelSeconds[1] - parallelSeconds[0];
double sequentialCost = 0;
sequentialCost = sequentialSeconds[1] - sequentialSeconds[0];
double speedup = 0;
speedup = sequentialCost / parallelCost;
int seqSum = 0;
seqSum = sumArray(seqArray, N + 1);
int parSum = 0;
parSum = sumArray(h_array, N + 1);
printf(" N: %d\n", N);
printf(" blockSize: %d\n", blockSize);
printf(" gridSize: %d\n", gridSize);
printf("sequential prime count: %d\n", seqSum);
printf(" parallel prime count: %d\n", parSum);
printf(" parallel time cost: %lf\n", parallelCost);
printf(" sequential time cost: %lf\n", sequentialCost);
printf(" speedup: %lf\n", speedup);
free(h_array);
free(seqArray);
return 0;
}
void getSeqPrimes(int* array, int arraySize){
int thisValue = 0;
for(thisValue = 3; thisValue < arraySize; thisValue += 2){
array[thisValue] = isPrime(thisValue);
}
}
int sumArray(int* array, int arraySize){
int sum = 0;
int index = 0;
for(; index < arraySize; ++index){
sum += array[index];
}
return sum;
}
void usage(int exitStatus, char* programName){
fprintf(stderr, "usage: %s N blockSize\n", programName);
exit(exitStatus);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9getPrimesPii
.globl _Z9getPrimesPii
.p2align 8
.type _Z9getPrimesPii,@function
_Z9getPrimesPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_lshl_or_b32 v0, v1, 1, 1
v_cmp_lt_i32_e32 vcc_lo, 0, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_8
v_cvt_f32_i32_e32 v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v2, 0x4f800000, v1
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v1
v_cndmask_b32_e32 v1, v1, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v2, v1
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v3, -1, v2
v_add_nc_u32_e32 v4, 1, v2
v_fma_f32 v5, -v3, v2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v6, -v4, v2, v1
v_cmp_ge_f32_e64 s2, 0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v2, v2, v3, s2
v_cmp_lt_f32_e64 s2, 0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v2, v2, v4, s2
v_mov_b32_e32 v4, 1
s_mov_b32 s2, exec_lo
v_mul_f32_e32 v3, 0x37800000, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v1, 0x260
v_cndmask_b32_e32 v1, v2, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_i32_f32_e32 v2, v1
v_cmpx_lt_i32_e32 1, v2
s_cbranch_execz .LBB0_7
v_ashrrev_i32_e32 v1, 31, v0
v_sub_nc_u32_e32 v2, 1, v2
s_mov_b32 s4, 2
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v0, v1
v_xor_b32_e32 v3, v3, v1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s6, exec_lo, s5
s_or_b32 s3, s6, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB0_6
.LBB0_4:
s_ashr_i32 s6, s4, 31
s_or_b32 s5, s5, exec_lo
s_add_i32 s7, s4, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s6, s7, s6
v_cvt_f32_u32_e32 v4, s6
s_sub_i32 s7, 0, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, 0x4f7ffffe, v4
v_cvt_u32_f32_e32 v4, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, s7, v4
v_mul_hi_u32 v5, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v4, v5
v_mul_hi_u32 v4, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v4, s6
v_sub_nc_u32_e32 v4, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s6, v4
v_cmp_le_u32_e32 vcc_lo, s6, v4
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s6, v4
v_cmp_le_u32_e32 vcc_lo, s6, v4
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v4, v4, v1
v_sub_nc_u32_e32 v4, v4, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, 0, v4
v_mov_b32_e32 v4, 0
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz .LBB0_3
s_add_i32 s4, s4, 1
s_and_not1_b32 s5, s5, exec_lo
v_add_nc_u32_e32 v4, s4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, 2, v4
v_mov_b32_e32 v4, 1
s_and_b32 s7, vcc_lo, exec_lo
s_or_b32 s5, s5, s7
s_branch .LBB0_3
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s3
.LBB0_7:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v1, 0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9getPrimesPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9getPrimesPii, .Lfunc_end0-_Z9getPrimesPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9getPrimesPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9getPrimesPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<math.h>
#include<stdlib.h>
#include<sys/time.h>
void usage(int exitStatus, char* programName);
int sumArray(int* array, int arraySize);
void getSeqPrimes(int* array, int arraySize);
__host__ __device__ int isPrime(int value);
__global__ void getPrimes(int* d_array, int N){
int threadId = 0;
threadId = blockIdx.x * blockDim.x + threadIdx.x;
int thisValue = 0;
thisValue = (threadId * 2) + 1;
if(threadId < 1)
return;
if(thisValue < N){
d_array[thisValue] = isPrime(thisValue);
}
}
__host__ __device__ int isPrime(int value){
int limit = 0;
limit = (int) sqrt( (float) value ) + 1;
int j = 0;
for(j = 2; j < limit; j++){
if(value % j == 0){
return 0;
}
}
return 1;
}
int main(int argc, char** argv){
if(argc != 3)
usage(1, argv[0]);
int N = 0;
N = (int) atoi(argv[1]);
int blockSize = 0;
blockSize = (int) atoi(argv[2]);
if(!(N | blockSize))
usage(2, argv[0]);
int arraySizeInBytes = 0;
arraySizeInBytes = 0;
arraySizeInBytes = sizeof(int) * (N + 1);
// index 0 : start time, index 1: end time
struct timeval sequentialTimes[2] = {{0,0},{0,0}};
struct timeval parallelTimes[2] = {{0,0},{0,0}};
// allocate our arrays
int* h_array = NULL;
int* d_array = NULL;
int* seqArray = NULL;
h_array = (int*) malloc(arraySizeInBytes);
seqArray = (int*) calloc(sizeof(int), N + 1);
// caculate the grid size
int gridSize = 0;
gridSize = (int)ceil((N + 1) / 2.0 / blockSize);
// start parallel timer
gettimeofday( &(parallelTimes[0]), NULL);
// allocate device memory for the array
hipMalloc(&d_array, arraySizeInBytes);
// zero the memory in cuda
hipMemset(d_array, 0, arraySizeInBytes);
// run the kernel
getPrimes<<<gridSize, blockSize>>>(d_array, N);
// copy the results back to the host array
hipMemcpy(h_array, d_array, arraySizeInBytes, hipMemcpyDeviceToHost);
// release the device array
hipFree(d_array);
// stop parallel timer
gettimeofday( &(parallelTimes[1]) , NULL);
// start sequential timer
gettimeofday( &(sequentialTimes[0]), NULL);
// run the sequential version
getSeqPrimes(seqArray, N + 1);
// stop sequential timer
gettimeofday( &(sequentialTimes[1]), NULL);
// calculated time values
double parallelSeconds[2] = {0.0, 0.0};
parallelSeconds[0] = parallelTimes[0].tv_sec + ((double)parallelTimes[0].tv_usec / 1000000);
parallelSeconds[1] = parallelTimes[1].tv_sec + ((double)parallelTimes[1].tv_usec / 1000000);
double sequentialSeconds[2] = {0.0, 0.0};
sequentialSeconds[0] = sequentialTimes[0].tv_sec + ((double)sequentialTimes[0].tv_usec / 1000000);
sequentialSeconds[1] = sequentialTimes[1].tv_sec + ((double)sequentialTimes[1].tv_usec / 1000000);
double parallelCost = 0;
parallelCost = parallelSeconds[1] - parallelSeconds[0];
double sequentialCost = 0;
sequentialCost = sequentialSeconds[1] - sequentialSeconds[0];
double speedup = 0;
speedup = sequentialCost / parallelCost;
int seqSum = 0;
seqSum = sumArray(seqArray, N + 1);
int parSum = 0;
parSum = sumArray(h_array, N + 1);
printf(" N: %d\n", N);
printf(" blockSize: %d\n", blockSize);
printf(" gridSize: %d\n", gridSize);
printf("sequential prime count: %d\n", seqSum);
printf(" parallel prime count: %d\n", parSum);
printf(" parallel time cost: %lf\n", parallelCost);
printf(" sequential time cost: %lf\n", sequentialCost);
printf(" speedup: %lf\n", speedup);
free(h_array);
free(seqArray);
return 0;
}
void getSeqPrimes(int* array, int arraySize){
int thisValue = 0;
for(thisValue = 3; thisValue < arraySize; thisValue += 2){
array[thisValue] = isPrime(thisValue);
}
}
int sumArray(int* array, int arraySize){
int sum = 0;
int index = 0;
for(; index < arraySize; ++index){
sum += array[index];
}
return sum;
}
void usage(int exitStatus, char* programName){
fprintf(stderr, "usage: %s N blockSize\n", programName);
exit(exitStatus);
} | .text
.file "lab1.hip"
.globl _Z24__device_stub__getPrimesPii # -- Begin function _Z24__device_stub__getPrimesPii
.p2align 4, 0x90
.type _Z24__device_stub__getPrimesPii,@function
_Z24__device_stub__getPrimesPii: # @_Z24__device_stub__getPrimesPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9getPrimesPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__getPrimesPii, .Lfunc_end0-_Z24__device_stub__getPrimesPii
.cfi_endproc
# -- End function
.globl _Z7isPrimei # -- Begin function _Z7isPrimei
.p2align 4, 0x90
.type _Z7isPrimei,@function
_Z7isPrimei: # @_Z7isPrimei
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %edi, %ebx
cvtsi2ss %edi, %xmm0
xorps %xmm1, %xmm1
ucomiss %xmm1, %xmm0
jb .LBB1_2
# %bb.1:
sqrtss %xmm0, %xmm0
jmp .LBB1_3
.LBB1_2: # %call.sqrt
callq sqrtf
.LBB1_3: # %.split
cvttss2si %xmm0, %ecx
movl $1, %eax
cmpl $2, %ecx
jl .LBB1_9
# %bb.4: # %.lr.ph.preheader
negl %ecx
movl $2, %esi
.p2align 4, 0x90
.LBB1_5: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ebx, %eax
cltd
idivl %esi
testl %edx, %edx
je .LBB1_8
# %bb.6: # in Loop: Header=BB1_5 Depth=1
leal (%rcx,%rsi), %eax
incl %eax
movl %esi, %edx
incl %edx
movl %edx, %esi
cmpl $1, %eax
jne .LBB1_5
# %bb.7:
movl $1, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_8:
.cfi_def_cfa_offset 16
xorl %eax, %eax
.LBB1_9: # %._crit_edge
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z7isPrimei, .Lfunc_end1-_Z7isPrimei
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x3fe0000000000000 # double 0.5
.LCPI2_1:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
cmpl $3, %edi
jne .LBB2_24
# %bb.1:
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
orl %r15d, %eax
je .LBB2_25
# %bb.2:
leal 1(%r15), %eax
movl %eax, 16(%rsp) # 4-byte Spill
movslq %eax, %r14
leal 4(,%r15,4), %eax
xorps %xmm0, %xmm0
movaps %xmm0, 80(%rsp)
movaps %xmm0, 64(%rsp)
movaps %xmm0, 48(%rsp)
movaps %xmm0, 32(%rsp)
movq $0, 8(%rsp)
movslq %eax, %rbp
movq %rbp, %rdi
callq malloc
movq %rax, %rbx
movl $4, %edi
movq %r14, %rsi
callq calloc
xorps %xmm0, %xmm0
cvtsi2sd %r14d, %xmm0
mulsd .LCPI2_0(%rip), %xmm0
movq %rax, %r14
cvtsi2sd %r12d, %xmm1
divsd %xmm1, %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %r13d
leaq 32(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
leaq 8(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
xorl %esi, %esi
movq %rbp, %rdx
callq hipMemset
movabsq $4294967296, %rax # imm = 0x100000000
movq %r13, 120(%rsp) # 8-byte Spill
leaq (%rax,%r13), %rdi
movq %r12, 128(%rsp) # 8-byte Spill
movl %r12d, %edx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 184(%rsp)
movl %r15d, 28(%rsp)
leaq 184(%rsp), %rax
movq %rax, 192(%rsp)
leaq 28(%rsp), %rax
movq %rax, 200(%rsp)
leaq 168(%rsp), %rdi
leaq 152(%rsp), %rsi
leaq 144(%rsp), %rdx
leaq 136(%rsp), %rcx
callq __hipPopCallConfiguration
movq 168(%rsp), %rsi
movl 176(%rsp), %edx
movq 152(%rsp), %rcx
movl 160(%rsp), %r8d
leaq 192(%rsp), %r9
movl $_Z9getPrimesPii, %edi
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
leaq 48(%rsp), %rdi
xorl %ebp, %ebp
xorl %esi, %esi
callq gettimeofday
leaq 64(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl 16(%rsp), %r12d # 4-byte Reload
cmpl $3, %r15d
jl .LBB2_16
# %bb.5: # %.lr.ph.preheader.i
movl $3, %r13d
xorpd %xmm1, %xmm1
jmp .LBB2_8
.p2align 4, 0x90
.LBB2_6: # in Loop: Header=BB2_8 Depth=1
movl $1, %edi
.LBB2_7: # %_Z7isPrimei.exit.i
# in Loop: Header=BB2_8 Depth=1
movl %edi, (%r14,%r13,4)
addq $2, %r13
cmpq %r12, %r13
jae .LBB2_16
.LBB2_8: # %.lr.ph.i
# =>This Loop Header: Depth=1
# Child Loop BB2_13 Depth 2
xorps %xmm0, %xmm0
cvtsi2ss %r13d, %xmm0
ucomiss %xmm1, %xmm0
jb .LBB2_10
# %bb.9: # in Loop: Header=BB2_8 Depth=1
sqrtss %xmm0, %xmm0
jmp .LBB2_11
.p2align 4, 0x90
.LBB2_10: # %call.sqrt
# in Loop: Header=BB2_8 Depth=1
callq sqrtf
xorps %xmm1, %xmm1
.LBB2_11: # %.lr.ph.i.split
# in Loop: Header=BB2_8 Depth=1
cvttss2si %xmm0, %ecx
cmpl $2, %ecx
jl .LBB2_6
# %bb.12: # %.lr.ph.i.i.preheader
# in Loop: Header=BB2_8 Depth=1
negl %ecx
movl $2, %esi
.p2align 4, 0x90
.LBB2_13: # %.lr.ph.i.i
# Parent Loop BB2_8 Depth=1
# => This Inner Loop Header: Depth=2
xorl %edi, %edi
movl %r13d, %eax
xorl %edx, %edx
divl %esi
testl %edx, %edx
je .LBB2_7
# %bb.14: # in Loop: Header=BB2_13 Depth=2
leal (%rcx,%rsi), %eax
incl %eax
movl %esi, %edx
incl %edx
movl %edx, %esi
cmpl $1, %eax
jne .LBB2_13
jmp .LBB2_6
.LBB2_16: # %_Z12getSeqPrimesPii.exit
leaq 80(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
testl %r15d, %r15d
js .LBB2_19
# %bb.17: # %.lr.ph.preheader.i44
xorl %eax, %eax
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_18: # %.lr.ph.i45
# =>This Inner Loop Header: Depth=1
addl (%r14,%rax,4), %ebp
incq %rax
cmpq %rax, %r12
jne .LBB2_18
.LBB2_19: # %_Z8sumArrayPii.exit
movq 32(%rsp), %rax
movq 40(%rsp), %rcx
movq 48(%rsp), %rdx
movq 56(%rsp), %rsi
movq 64(%rsp), %rdi
movq 72(%rsp), %r8
movq 80(%rsp), %r9
movq 88(%rsp), %r10
testl %r15d, %r15d
js .LBB2_22
# %bb.20: # %.lr.ph.preheader.i49
xorl %r11d, %r11d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_21: # %.lr.ph.i51
# =>This Inner Loop Header: Depth=1
addl (%rbx,%r11,4), %r13d
incq %r11
cmpq %r11, %r12
jne .LBB2_21
jmp .LBB2_23
.LBB2_22:
xorl %r13d, %r13d
.LBB2_23: # %_Z8sumArrayPii.exit56
xorps %xmm0, %xmm0
cvtsi2sd %r10, %xmm0
movsd .LCPI2_1(%rip), %xmm1 # xmm1 = mem[0],zero
cvtsi2sd %r9, %xmm3
divsd %xmm1, %xmm0
addsd %xmm0, %xmm3
xorps %xmm0, %xmm0
cvtsi2sd %r8, %xmm0
divsd %xmm1, %xmm0
cvtsi2sd %rdi, %xmm2
addsd %xmm0, %xmm2
subsd %xmm2, %xmm3
movsd %xmm3, 112(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sd %rsi, %xmm0
divsd %xmm1, %xmm0
cvtsi2sd %rdx, %xmm4
xorps %xmm2, %xmm2
cvtsi2sd %rcx, %xmm2
addsd %xmm0, %xmm4
divsd %xmm1, %xmm2
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
addsd %xmm2, %xmm0
subsd %xmm0, %xmm4
movsd %xmm4, 104(%rsp) # 8-byte Spill
movapd %xmm3, %xmm0
divsd %xmm4, %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
movl $.L.str, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movq 128(%rsp), %rsi # 8-byte Reload
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movq 120(%rsp), %rsi # 8-byte Reload
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl $.L.str.4, %edi
movl %r13d, %esi
xorl %eax, %eax
callq printf
movl $.L.str.5, %edi
movsd 104(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $.L.str.6, %edi
movsd 112(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $.L.str.7, %edi
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_24:
.cfi_def_cfa_offset 272
movq (%rbx), %rdx
movq stderr(%rip), %rdi
movl $.L.str.8, %esi
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB2_25:
movq (%rbx), %rdx
movq stderr(%rip), %rdi
movl $.L.str.8, %esi
xorl %eax, %eax
callq fprintf
movl $2, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.globl _Z5usageiPc # -- Begin function _Z5usageiPc
.p2align 4, 0x90
.type _Z5usageiPc,@function
_Z5usageiPc: # @_Z5usageiPc
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rsi, %rdx
movl %edi, %ebx
movq stderr(%rip), %rdi
movl $.L.str.8, %esi
xorl %eax, %eax
callq fprintf
movl %ebx, %edi
callq exit
.Lfunc_end3:
.size _Z5usageiPc, .Lfunc_end3-_Z5usageiPc
.cfi_endproc
# -- End function
.globl _Z12getSeqPrimesPii # -- Begin function _Z12getSeqPrimesPii
.p2align 4, 0x90
.type _Z12getSeqPrimesPii,@function
_Z12getSeqPrimesPii: # @_Z12getSeqPrimesPii
.cfi_startproc
# %bb.0:
cmpl $4, %esi
jl .LBB4_13
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r15d
movl $3, %r14d
xorps %xmm1, %xmm1
jmp .LBB4_4
.p2align 4, 0x90
.LBB4_2: # in Loop: Header=BB4_4 Depth=1
movl $1, %edi
.LBB4_3: # %_Z7isPrimei.exit
# in Loop: Header=BB4_4 Depth=1
movl %edi, (%rbx,%r14,4)
addq $2, %r14
cmpq %r15, %r14
jae .LBB4_12
.LBB4_4: # %.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB4_9 Depth 2
xorps %xmm0, %xmm0
cvtsi2ss %r14d, %xmm0
ucomiss %xmm1, %xmm0
jb .LBB4_6
# %bb.5: # in Loop: Header=BB4_4 Depth=1
sqrtss %xmm0, %xmm0
jmp .LBB4_7
.p2align 4, 0x90
.LBB4_6: # %call.sqrt
# in Loop: Header=BB4_4 Depth=1
callq sqrtf
xorps %xmm1, %xmm1
.LBB4_7: # %.lr.ph.split
# in Loop: Header=BB4_4 Depth=1
cvttss2si %xmm0, %ecx
cmpl $2, %ecx
jl .LBB4_2
# %bb.8: # %.lr.ph.i.preheader
# in Loop: Header=BB4_4 Depth=1
negl %ecx
movl $2, %esi
.p2align 4, 0x90
.LBB4_9: # %.lr.ph.i
# Parent Loop BB4_4 Depth=1
# => This Inner Loop Header: Depth=2
xorl %edi, %edi
movl %r14d, %eax
xorl %edx, %edx
divl %esi
testl %edx, %edx
je .LBB4_3
# %bb.10: # in Loop: Header=BB4_9 Depth=2
leal (%rcx,%rsi), %eax
incl %eax
movl %esi, %edx
incl %edx
movl %edx, %esi
cmpl $1, %eax
jne .LBB4_9
jmp .LBB4_2
.LBB4_12:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB4_13: # %._crit_edge
retq
.Lfunc_end4:
.size _Z12getSeqPrimesPii, .Lfunc_end4-_Z12getSeqPrimesPii
.cfi_endproc
# -- End function
.globl _Z8sumArrayPii # -- Begin function _Z8sumArrayPii
.p2align 4, 0x90
.type _Z8sumArrayPii,@function
_Z8sumArrayPii: # @_Z8sumArrayPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB5_1
# %bb.2: # %.lr.ph.preheader
movl %esi, %ecx
xorl %edx, %edx
xorl %eax, %eax
.p2align 4, 0x90
.LBB5_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
addl (%rdi,%rdx,4), %eax
incq %rdx
cmpq %rdx, %rcx
jne .LBB5_3
# %bb.4: # %._crit_edge
retq
.LBB5_1:
xorl %eax, %eax
retq
.Lfunc_end5:
.size _Z8sumArrayPii, .Lfunc_end5-_Z8sumArrayPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9getPrimesPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9getPrimesPii,@object # @_Z9getPrimesPii
.section .rodata,"a",@progbits
.globl _Z9getPrimesPii
.p2align 3, 0x0
_Z9getPrimesPii:
.quad _Z24__device_stub__getPrimesPii
.size _Z9getPrimesPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " N: %d\n"
.size .L.str, 28
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " blockSize: %d\n"
.size .L.str.1, 28
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " gridSize: %d\n"
.size .L.str.2, 28
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "sequential prime count: %d\n"
.size .L.str.3, 28
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " parallel prime count: %d\n"
.size .L.str.4, 28
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " parallel time cost: %lf\n"
.size .L.str.5, 29
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " sequential time cost: %lf\n"
.size .L.str.6, 29
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " speedup: %lf\n"
.size .L.str.7, 29
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "usage: %s N blockSize\n"
.size .L.str.8, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9getPrimesPii"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__getPrimesPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9getPrimesPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9getPrimesPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ LEA R0, R2, 0x1, 0x1 ; /* 0x0000000102007811 */
/* 0x000fc800078e08ff */
/*0050*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fc80003f06270 */
/*0060*/ ISETP.LT.OR P0, PT, R2, 0x1, P0 ; /* 0x000000010200780c */
/* 0x000fda0000701670 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ I2F R2, R0 ; /* 0x0000000000027306 */
/* 0x000e220000201400 */
/*0090*/ BSSY B0, 0x190 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*00a0*/ IADD3 R4, R2, -0xd000000, RZ ; /* 0xf300000002047810 */
/* 0x001fcc0007ffe0ff */
/*00b0*/ MUFU.RSQ R3, R2 ; /* 0x0000000200037308 */
/* 0x0000620000001400 */
/*00c0*/ ISETP.GT.U32.AND P0, PT, R4, 0x727fffff, PT ; /* 0x727fffff0400780c */
/* 0x000fda0003f04070 */
/*00d0*/ @!P0 BRA 0x140 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*00e0*/ BSSY B1, 0x120 ; /* 0x0000003000017945 */
/* 0x003fe20003800000 */
/*00f0*/ MOV R8, 0x110 ; /* 0x0000011000087802 */
/* 0x000fe40000000f00 */
/*0100*/ CALL.REL.NOINC 0x430 ; /* 0x0000032000007944 */
/* 0x000fea0003c00000 */
/*0110*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0120*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0004 */
/*0130*/ BRA 0x180 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0140*/ FMUL.FTZ R5, R2, R3 ; /* 0x0000000302057220 */
/* 0x003fe40000410000 */
/*0150*/ FMUL.FTZ R3, R3, 0.5 ; /* 0x3f00000003037820 */
/* 0x000fe40000410000 */
/*0160*/ FFMA R2, -R5, R5, R2 ; /* 0x0000000505027223 */
/* 0x000fc80000000102 */
/*0170*/ FFMA R2, R2, R3, R5 ; /* 0x0000000302027223 */
/* 0x000fe40000000005 */
/*0180*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0190*/ F2I.TRUNC.NTZ R9, R2 ; /* 0x0000000200097305 */
/* 0x000e22000020f100 */
/*01a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*01b0*/ BSSY B0, 0x3f0 ; /* 0x0000023000007945 */
/* 0x000fe20003800000 */
/*01c0*/ HFMA2.MMA R5, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff057435 */
/* 0x000fe200000001ff */
/*01d0*/ ISETP.GE.AND P0, PT, R9, 0x2, PT ; /* 0x000000020900780c */
/* 0x001fda0003f06270 */
/*01e0*/ @!P0 BRA 0x3e0 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*01f0*/ IABS R6, R0 ; /* 0x0000000000067213 */
/* 0x000fe20000000000 */
/*0200*/ IMAD.MOV.U32 R4, RZ, RZ, 0x2 ; /* 0x00000002ff047424 */
/* 0x000fca00078e00ff */
/*0210*/ IABS R8, R4.reuse ; /* 0x0000000400087213 */
/* 0x080fe40000000000 */
/*0220*/ IABS R10, R4 ; /* 0x00000004000a7213 */
/* 0x000fe40000000000 */
/*0230*/ I2F.RP R5, R8 ; /* 0x0000000800057306 */
/* 0x000e220000209400 */
/*0240*/ ISETP.GE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f46270 */
/*0250*/ IMAD.MOV R10, RZ, RZ, -R10 ; /* 0x000000ffff0a7224 */
/* 0x000fca00078e0a0a */
/*0260*/ MUFU.RCP R5, R5 ; /* 0x0000000500057308 */
/* 0x001e240000001000 */
/*0270*/ IADD3 R2, R5, 0xffffffe, RZ ; /* 0x0ffffffe05027810 */
/* 0x001fe40007ffe0ff */
/*0280*/ IABS R5, R0 ; /* 0x0000000000057213 */
/* 0x000fc80000000000 */
/*0290*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*02a0*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*02b0*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a03 */
/*02c0*/ IMAD R7, R7, R8, RZ ; /* 0x0000000807077224 */
/* 0x000fca00078e02ff */
/*02d0*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*02e0*/ IMAD.HI.U32 R3, R3, R6, RZ ; /* 0x0000000603037227 */
/* 0x000fc800078e00ff */
/*02f0*/ IMAD R3, R3, R10, R5 ; /* 0x0000000a03037224 */
/* 0x000fe200078e0205 */
/*0300*/ MOV R5, RZ ; /* 0x000000ff00057202 */
/* 0x000fc80000000f00 */
/*0310*/ ISETP.GT.U32.AND P0, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fda0003f04070 */
/*0320*/ @!P0 IMAD.IADD R3, R3, 0x1, -R8 ; /* 0x0000000103038824 */
/* 0x000fe200078e0a08 */
/*0330*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc80003f05270 */
/*0340*/ ISETP.GT.U32.AND P1, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fda0003f24070 */
/*0350*/ @!P1 IADD3 R3, R3, -R8, RZ ; /* 0x8000000803039210 */
/* 0x000fca0007ffe0ff */
/*0360*/ @!P2 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff03a224 */
/* 0x000fe200078e0a03 */
/*0370*/ @!P0 LOP3.LUT R3, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff038212 */
/* 0x000fc800078e33ff */
/*0380*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*0390*/ @!P0 BRA 0x3e0 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*03a0*/ ISETP.GE.AND P0, PT, R4.reuse, R9, PT ; /* 0x000000090400720c */
/* 0x040fe40003f06270 */
/*03b0*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fd60007ffe0ff */
/*03c0*/ @!P0 BRA 0x210 ; /* 0xfffffe4000008947 */
/* 0x000fea000383ffff */
/*03d0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fe400078e00ff */
/*03e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03f0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*0400*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0410*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0420*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0430*/ LOP3.LUT P0, RZ, R2, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff02ff7812 */
/* 0x000fda000780c0ff */
/*0440*/ @!P0 IMAD.MOV.U32 R3, RZ, RZ, R2 ; /* 0x000000ffff038224 */
/* 0x000fe200078e0002 */
/*0450*/ @!P0 BRA 0x560 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0460*/ FSETP.GEU.FTZ.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720b */
/* 0x000fda0003f1e000 */
/*0470*/ @!P0 MOV R3, 0x7fffffff ; /* 0x7fffffff00038802 */
/* 0x000fe20000000f00 */
/*0480*/ @!P0 BRA 0x560 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0490*/ FSETP.GTU.FTZ.AND P0, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fda0003f1c200 */
/*04a0*/ @P0 FADD.FTZ R3, R2, 1 ; /* 0x3f80000002030421 */
/* 0x000fe20000010000 */
/*04b0*/ @P0 BRA 0x560 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*04c0*/ FSETP.NEU.FTZ.AND P0, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fda0003f1d200 */
/*04d0*/ @P0 FFMA R4, R2, 1.84467440737095516160e+19, RZ ; /* 0x5f80000002040823 */
/* 0x000fc800000000ff */
/*04e0*/ @P0 MUFU.RSQ R3, R4 ; /* 0x0000000400030308 */
/* 0x000e240000001400 */
/*04f0*/ @P0 FMUL.FTZ R5, R4, R3 ; /* 0x0000000304050220 */
/* 0x001fe40000410000 */
/*0500*/ @P0 FMUL.FTZ R7, R3, 0.5 ; /* 0x3f00000003070820 */
/* 0x000fe40000410000 */
/*0510*/ @P0 FADD.FTZ R6, -R5.reuse, -RZ ; /* 0x800000ff05060221 */
/* 0x040fe40000010100 */
/*0520*/ @!P0 IMAD.MOV.U32 R3, RZ, RZ, R2 ; /* 0x000000ffff038224 */
/* 0x000fe400078e0002 */
/*0530*/ @P0 FFMA R6, R5, R6, R4 ; /* 0x0000000605060223 */
/* 0x000fc80000000004 */
/*0540*/ @P0 FFMA R6, R6, R7, R5 ; /* 0x0000000706060223 */
/* 0x000fc80000000005 */
/*0550*/ @P0 FMUL.FTZ R3, R6, 2.3283064365386962891e-10 ; /* 0x2f80000006030820 */
/* 0x000fca0000410000 */
/*0560*/ MOV R4, R3 ; /* 0x0000000300047202 */
/* 0x000fe20000000f00 */
/*0570*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0580*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x000fca00078e0008 */
/*0590*/ RET.REL.NODEC R2 0x0 ; /* 0xfffffa6002007950 */
/* 0x000fea0003c3ffff */
/*05a0*/ BRA 0x5a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9getPrimesPii
.globl _Z9getPrimesPii
.p2align 8
.type _Z9getPrimesPii,@function
_Z9getPrimesPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_lshl_or_b32 v0, v1, 1, 1
v_cmp_lt_i32_e32 vcc_lo, 0, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_8
v_cvt_f32_i32_e32 v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v2, 0x4f800000, v1
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v1
v_cndmask_b32_e32 v1, v1, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v2, v1
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v3, -1, v2
v_add_nc_u32_e32 v4, 1, v2
v_fma_f32 v5, -v3, v2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v6, -v4, v2, v1
v_cmp_ge_f32_e64 s2, 0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v2, v2, v3, s2
v_cmp_lt_f32_e64 s2, 0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v2, v2, v4, s2
v_mov_b32_e32 v4, 1
s_mov_b32 s2, exec_lo
v_mul_f32_e32 v3, 0x37800000, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v1, 0x260
v_cndmask_b32_e32 v1, v2, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_i32_f32_e32 v2, v1
v_cmpx_lt_i32_e32 1, v2
s_cbranch_execz .LBB0_7
v_ashrrev_i32_e32 v1, 31, v0
v_sub_nc_u32_e32 v2, 1, v2
s_mov_b32 s4, 2
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v0, v1
v_xor_b32_e32 v3, v3, v1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s6, exec_lo, s5
s_or_b32 s3, s6, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB0_6
.LBB0_4:
s_ashr_i32 s6, s4, 31
s_or_b32 s5, s5, exec_lo
s_add_i32 s7, s4, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s6, s7, s6
v_cvt_f32_u32_e32 v4, s6
s_sub_i32 s7, 0, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, 0x4f7ffffe, v4
v_cvt_u32_f32_e32 v4, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, s7, v4
v_mul_hi_u32 v5, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v4, v5
v_mul_hi_u32 v4, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v4, s6
v_sub_nc_u32_e32 v4, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s6, v4
v_cmp_le_u32_e32 vcc_lo, s6, v4
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s6, v4
v_cmp_le_u32_e32 vcc_lo, s6, v4
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v4, v4, v1
v_sub_nc_u32_e32 v4, v4, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, 0, v4
v_mov_b32_e32 v4, 0
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz .LBB0_3
s_add_i32 s4, s4, 1
s_and_not1_b32 s5, s5, exec_lo
v_add_nc_u32_e32 v4, s4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, 2, v4
v_mov_b32_e32 v4, 1
s_and_b32 s7, vcc_lo, exec_lo
s_or_b32 s5, s5, s7
s_branch .LBB0_3
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s3
.LBB0_7:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v1, 0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9getPrimesPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9getPrimesPii, .Lfunc_end0-_Z9getPrimesPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9getPrimesPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9getPrimesPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019588d_00000000-6_lab1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7isPrimei
.type _Z7isPrimei, @function
_Z7isPrimei:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %edi, %ebx
pxor %xmm0, %xmm0
cvtsi2ssl %edi, %xmm0
pxor %xmm1, %xmm1
ucomiss %xmm0, %xmm1
ja .L13
sqrtss %xmm0, %xmm0
.L6:
cvttss2sil %xmm0, %esi
cmpl $1, %esi
jle .L10
movl %ebx, %edi
andl $1, %edi
je .L3
movl $2, %ecx
.L8:
addl $1, %ecx
cmpl %ecx, %esi
jl .L3
movl %ebx, %eax
cltd
idivl %ecx
testl %edx, %edx
jne .L8
movl %edx, %edi
.L3:
movl %edi, %eax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
call sqrtf@PLT
jmp .L6
.L10:
movl $1, %edi
jmp .L3
.cfi_endproc
.LFE2057:
.size _Z7isPrimei, .-_Z7isPrimei
.globl _Z12getSeqPrimesPii
.type _Z12getSeqPrimesPii, @function
_Z12getSeqPrimesPii:
.LFB2059:
.cfi_startproc
endbr64
cmpl $3, %esi
jle .L20
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbp
subl $4, %esi
shrl %esi
leal (%rsi,%rsi), %r12d
addq $5, %r12
movl $3, %ebx
.L17:
movl %ebx, %edi
call _Z7isPrimei
movl %eax, 0(%rbp,%rbx,4)
addq $2, %rbx
cmpq %r12, %rbx
jne .L17
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE2059:
.size _Z12getSeqPrimesPii, .-_Z12getSeqPrimesPii
.globl _Z8sumArrayPii
.type _Z8sumArrayPii, @function
_Z8sumArrayPii:
.LFB2060:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L26
movq %rdi, %rax
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rcx
movl $0, %edx
.L25:
addl (%rax), %edx
addq $4, %rax
cmpq %rcx, %rax
jne .L25
.L23:
movl %edx, %eax
ret
.L26:
movl $0, %edx
jmp .L23
.cfi_endproc
.LFE2060:
.size _Z8sumArrayPii, .-_Z8sumArrayPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "usage: %s N blockSize\n"
.text
.globl _Z5usageiPc
.type _Z5usageiPc, @function
_Z5usageiPc:
.LFB2061:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %edi, %ebx
movq %rsi, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE2061:
.size _Z5usageiPc, .-_Z5usageiPc
.globl _Z29__device_stub__Z9getPrimesPiiPii
.type _Z29__device_stub__Z9getPrimesPiiPii, @function
_Z29__device_stub__Z9getPrimesPiiPii:
.LFB2086:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L34
.L30:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L35
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9getPrimesPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L30
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z29__device_stub__Z9getPrimesPiiPii, .-_Z29__device_stub__Z9getPrimesPiiPii
.globl _Z9getPrimesPii
.type _Z9getPrimesPii, @function
_Z9getPrimesPii:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z9getPrimesPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z9getPrimesPii, .-_Z9getPrimesPii
.section .rodata.str1.1
.LC7:
.string " N: %d\n"
.LC8:
.string " blockSize: %d\n"
.LC9:
.string " gridSize: %d\n"
.LC10:
.string "sequential prime count: %d\n"
.LC11:
.string " parallel prime count: %d\n"
.LC12:
.string " parallel time cost: %lf\n"
.LC13:
.string " sequential time cost: %lf\n"
.LC14:
.string " speedup: %lf\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
cmpl $3, %edi
jne .L47
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, 24(%rsp)
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movl %eax, 28(%rsp)
movl %ebx, %eax
orl %r12d, %eax
je .L48
addl $1, %ebx
movslq %ebx, %r13
movq $0, 64(%rsp)
movq $0, 72(%rsp)
movq $0, 80(%rsp)
movq $0, 88(%rsp)
movq $0, 96(%rsp)
movq $0, 104(%rsp)
movq $0, 112(%rsp)
movq $0, 120(%rsp)
movq $0, 32(%rsp)
leal 0(,%rbx,4), %ebp
movslq %ebp, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r14
movq %r13, %rsi
movl $4, %edi
call calloc@PLT
movq %rax, %r13
pxor %xmm0, %xmm0
cvtsi2sdl %ebx, %xmm0
mulsd .LC2(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdl %r12d, %xmm1
divsd %xmm1, %xmm0
movapd %xmm0, %xmm3
movsd .LC15(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC3(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L43
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC5(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L43:
cvttsd2sil %xmm3, %r15d
leaq 96(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
leaq 32(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movq %rbp, %rdx
movl $0, %esi
movq 32(%rsp), %rdi
call cudaMemset@PLT
movl %r12d, 52(%rsp)
movl $1, 56(%rsp)
movl %r15d, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L49
.L44:
movl $2, %ecx
movq %rbp, %rdx
movq 32(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
leaq 112(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl %ebx, %esi
movq %r13, %rdi
call _Z12getSeqPrimesPii
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 120(%rsp), %xmm0
movsd .LC6(%rip), %xmm2
divsd %xmm2, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 112(%rsp), %xmm1
addsd %xmm0, %xmm1
pxor %xmm0, %xmm0
cvtsi2sdq 104(%rsp), %xmm0
divsd %xmm2, %xmm0
pxor %xmm3, %xmm3
cvtsi2sdq 96(%rsp), %xmm3
addsd %xmm3, %xmm0
movapd %xmm1, %xmm6
subsd %xmm0, %xmm6
pxor %xmm0, %xmm0
cvtsi2sdq 88(%rsp), %xmm0
divsd %xmm2, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 80(%rsp), %xmm1
addsd %xmm0, %xmm1
pxor %xmm0, %xmm0
cvtsi2sdq 72(%rsp), %xmm0
divsd %xmm2, %xmm0
pxor %xmm2, %xmm2
cvtsi2sdq 64(%rsp), %xmm2
addsd %xmm2, %xmm0
subsd %xmm0, %xmm1
movsd %xmm1, 16(%rsp)
movapd %xmm1, %xmm5
movsd %xmm6, 8(%rsp)
divsd %xmm6, %xmm5
movq %xmm5, %rbp
movl %ebx, %esi
movq %r13, %rdi
call _Z8sumArrayPii
movl %eax, %r12d
movl %ebx, %esi
movq %r14, %rdi
call _Z8sumArrayPii
movl %eax, %ebx
movl 24(%rsp), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 28(%rsp), %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r15d, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 16(%rsp), %xmm0
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %xmm0
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L50
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L51
movq (%rsi), %rsi
movl $1, %edi
call _Z5usageiPc
.L51:
call __stack_chk_fail@PLT
.L48:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L52
movq 0(%rbp), %rsi
movl $2, %edi
call _Z5usageiPc
.L52:
call __stack_chk_fail@PLT
.L49:
movl 24(%rsp), %esi
movq 32(%rsp), %rdi
call _Z29__device_stub__Z9getPrimesPiiPii
jmp .L44
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC16:
.string "_Z9getPrimesPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z9getPrimesPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1071644672
.align 8
.LC3:
.long 0
.long 1127219200
.align 8
.LC5:
.long 0
.long 1072693248
.align 8
.LC6:
.long 0
.long 1093567616
.align 8
.LC15:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "lab1.hip"
.globl _Z24__device_stub__getPrimesPii # -- Begin function _Z24__device_stub__getPrimesPii
.p2align 4, 0x90
.type _Z24__device_stub__getPrimesPii,@function
_Z24__device_stub__getPrimesPii: # @_Z24__device_stub__getPrimesPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9getPrimesPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__getPrimesPii, .Lfunc_end0-_Z24__device_stub__getPrimesPii
.cfi_endproc
# -- End function
.globl _Z7isPrimei # -- Begin function _Z7isPrimei
.p2align 4, 0x90
.type _Z7isPrimei,@function
_Z7isPrimei: # @_Z7isPrimei
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %edi, %ebx
cvtsi2ss %edi, %xmm0
xorps %xmm1, %xmm1
ucomiss %xmm1, %xmm0
jb .LBB1_2
# %bb.1:
sqrtss %xmm0, %xmm0
jmp .LBB1_3
.LBB1_2: # %call.sqrt
callq sqrtf
.LBB1_3: # %.split
cvttss2si %xmm0, %ecx
movl $1, %eax
cmpl $2, %ecx
jl .LBB1_9
# %bb.4: # %.lr.ph.preheader
negl %ecx
movl $2, %esi
.p2align 4, 0x90
.LBB1_5: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ebx, %eax
cltd
idivl %esi
testl %edx, %edx
je .LBB1_8
# %bb.6: # in Loop: Header=BB1_5 Depth=1
leal (%rcx,%rsi), %eax
incl %eax
movl %esi, %edx
incl %edx
movl %edx, %esi
cmpl $1, %eax
jne .LBB1_5
# %bb.7:
movl $1, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_8:
.cfi_def_cfa_offset 16
xorl %eax, %eax
.LBB1_9: # %._crit_edge
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z7isPrimei, .Lfunc_end1-_Z7isPrimei
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x3fe0000000000000 # double 0.5
.LCPI2_1:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
cmpl $3, %edi
jne .LBB2_24
# %bb.1:
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
orl %r15d, %eax
je .LBB2_25
# %bb.2:
leal 1(%r15), %eax
movl %eax, 16(%rsp) # 4-byte Spill
movslq %eax, %r14
leal 4(,%r15,4), %eax
xorps %xmm0, %xmm0
movaps %xmm0, 80(%rsp)
movaps %xmm0, 64(%rsp)
movaps %xmm0, 48(%rsp)
movaps %xmm0, 32(%rsp)
movq $0, 8(%rsp)
movslq %eax, %rbp
movq %rbp, %rdi
callq malloc
movq %rax, %rbx
movl $4, %edi
movq %r14, %rsi
callq calloc
xorps %xmm0, %xmm0
cvtsi2sd %r14d, %xmm0
mulsd .LCPI2_0(%rip), %xmm0
movq %rax, %r14
cvtsi2sd %r12d, %xmm1
divsd %xmm1, %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %r13d
leaq 32(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
leaq 8(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
xorl %esi, %esi
movq %rbp, %rdx
callq hipMemset
movabsq $4294967296, %rax # imm = 0x100000000
movq %r13, 120(%rsp) # 8-byte Spill
leaq (%rax,%r13), %rdi
movq %r12, 128(%rsp) # 8-byte Spill
movl %r12d, %edx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 184(%rsp)
movl %r15d, 28(%rsp)
leaq 184(%rsp), %rax
movq %rax, 192(%rsp)
leaq 28(%rsp), %rax
movq %rax, 200(%rsp)
leaq 168(%rsp), %rdi
leaq 152(%rsp), %rsi
leaq 144(%rsp), %rdx
leaq 136(%rsp), %rcx
callq __hipPopCallConfiguration
movq 168(%rsp), %rsi
movl 176(%rsp), %edx
movq 152(%rsp), %rcx
movl 160(%rsp), %r8d
leaq 192(%rsp), %r9
movl $_Z9getPrimesPii, %edi
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
leaq 48(%rsp), %rdi
xorl %ebp, %ebp
xorl %esi, %esi
callq gettimeofday
leaq 64(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl 16(%rsp), %r12d # 4-byte Reload
cmpl $3, %r15d
jl .LBB2_16
# %bb.5: # %.lr.ph.preheader.i
movl $3, %r13d
xorpd %xmm1, %xmm1
jmp .LBB2_8
.p2align 4, 0x90
.LBB2_6: # in Loop: Header=BB2_8 Depth=1
movl $1, %edi
.LBB2_7: # %_Z7isPrimei.exit.i
# in Loop: Header=BB2_8 Depth=1
movl %edi, (%r14,%r13,4)
addq $2, %r13
cmpq %r12, %r13
jae .LBB2_16
.LBB2_8: # %.lr.ph.i
# =>This Loop Header: Depth=1
# Child Loop BB2_13 Depth 2
xorps %xmm0, %xmm0
cvtsi2ss %r13d, %xmm0
ucomiss %xmm1, %xmm0
jb .LBB2_10
# %bb.9: # in Loop: Header=BB2_8 Depth=1
sqrtss %xmm0, %xmm0
jmp .LBB2_11
.p2align 4, 0x90
.LBB2_10: # %call.sqrt
# in Loop: Header=BB2_8 Depth=1
callq sqrtf
xorps %xmm1, %xmm1
.LBB2_11: # %.lr.ph.i.split
# in Loop: Header=BB2_8 Depth=1
cvttss2si %xmm0, %ecx
cmpl $2, %ecx
jl .LBB2_6
# %bb.12: # %.lr.ph.i.i.preheader
# in Loop: Header=BB2_8 Depth=1
negl %ecx
movl $2, %esi
.p2align 4, 0x90
.LBB2_13: # %.lr.ph.i.i
# Parent Loop BB2_8 Depth=1
# => This Inner Loop Header: Depth=2
xorl %edi, %edi
movl %r13d, %eax
xorl %edx, %edx
divl %esi
testl %edx, %edx
je .LBB2_7
# %bb.14: # in Loop: Header=BB2_13 Depth=2
leal (%rcx,%rsi), %eax
incl %eax
movl %esi, %edx
incl %edx
movl %edx, %esi
cmpl $1, %eax
jne .LBB2_13
jmp .LBB2_6
.LBB2_16: # %_Z12getSeqPrimesPii.exit
leaq 80(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
testl %r15d, %r15d
js .LBB2_19
# %bb.17: # %.lr.ph.preheader.i44
xorl %eax, %eax
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_18: # %.lr.ph.i45
# =>This Inner Loop Header: Depth=1
addl (%r14,%rax,4), %ebp
incq %rax
cmpq %rax, %r12
jne .LBB2_18
.LBB2_19: # %_Z8sumArrayPii.exit
movq 32(%rsp), %rax
movq 40(%rsp), %rcx
movq 48(%rsp), %rdx
movq 56(%rsp), %rsi
movq 64(%rsp), %rdi
movq 72(%rsp), %r8
movq 80(%rsp), %r9
movq 88(%rsp), %r10
testl %r15d, %r15d
js .LBB2_22
# %bb.20: # %.lr.ph.preheader.i49
xorl %r11d, %r11d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_21: # %.lr.ph.i51
# =>This Inner Loop Header: Depth=1
addl (%rbx,%r11,4), %r13d
incq %r11
cmpq %r11, %r12
jne .LBB2_21
jmp .LBB2_23
.LBB2_22:
xorl %r13d, %r13d
.LBB2_23: # %_Z8sumArrayPii.exit56
xorps %xmm0, %xmm0
cvtsi2sd %r10, %xmm0
movsd .LCPI2_1(%rip), %xmm1 # xmm1 = mem[0],zero
cvtsi2sd %r9, %xmm3
divsd %xmm1, %xmm0
addsd %xmm0, %xmm3
xorps %xmm0, %xmm0
cvtsi2sd %r8, %xmm0
divsd %xmm1, %xmm0
cvtsi2sd %rdi, %xmm2
addsd %xmm0, %xmm2
subsd %xmm2, %xmm3
movsd %xmm3, 112(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sd %rsi, %xmm0
divsd %xmm1, %xmm0
cvtsi2sd %rdx, %xmm4
xorps %xmm2, %xmm2
cvtsi2sd %rcx, %xmm2
addsd %xmm0, %xmm4
divsd %xmm1, %xmm2
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
addsd %xmm2, %xmm0
subsd %xmm0, %xmm4
movsd %xmm4, 104(%rsp) # 8-byte Spill
movapd %xmm3, %xmm0
divsd %xmm4, %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
movl $.L.str, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movq 128(%rsp), %rsi # 8-byte Reload
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movq 120(%rsp), %rsi # 8-byte Reload
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl $.L.str.4, %edi
movl %r13d, %esi
xorl %eax, %eax
callq printf
movl $.L.str.5, %edi
movsd 104(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $.L.str.6, %edi
movsd 112(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $.L.str.7, %edi
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_24:
.cfi_def_cfa_offset 272
movq (%rbx), %rdx
movq stderr(%rip), %rdi
movl $.L.str.8, %esi
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB2_25:
movq (%rbx), %rdx
movq stderr(%rip), %rdi
movl $.L.str.8, %esi
xorl %eax, %eax
callq fprintf
movl $2, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.globl _Z5usageiPc # -- Begin function _Z5usageiPc
.p2align 4, 0x90
.type _Z5usageiPc,@function
_Z5usageiPc: # @_Z5usageiPc
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rsi, %rdx
movl %edi, %ebx
movq stderr(%rip), %rdi
movl $.L.str.8, %esi
xorl %eax, %eax
callq fprintf
movl %ebx, %edi
callq exit
.Lfunc_end3:
.size _Z5usageiPc, .Lfunc_end3-_Z5usageiPc
.cfi_endproc
# -- End function
.globl _Z12getSeqPrimesPii # -- Begin function _Z12getSeqPrimesPii
.p2align 4, 0x90
.type _Z12getSeqPrimesPii,@function
_Z12getSeqPrimesPii: # @_Z12getSeqPrimesPii
.cfi_startproc
# %bb.0:
cmpl $4, %esi
jl .LBB4_13
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r15d
movl $3, %r14d
xorps %xmm1, %xmm1
jmp .LBB4_4
.p2align 4, 0x90
.LBB4_2: # in Loop: Header=BB4_4 Depth=1
movl $1, %edi
.LBB4_3: # %_Z7isPrimei.exit
# in Loop: Header=BB4_4 Depth=1
movl %edi, (%rbx,%r14,4)
addq $2, %r14
cmpq %r15, %r14
jae .LBB4_12
.LBB4_4: # %.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB4_9 Depth 2
xorps %xmm0, %xmm0
cvtsi2ss %r14d, %xmm0
ucomiss %xmm1, %xmm0
jb .LBB4_6
# %bb.5: # in Loop: Header=BB4_4 Depth=1
sqrtss %xmm0, %xmm0
jmp .LBB4_7
.p2align 4, 0x90
.LBB4_6: # %call.sqrt
# in Loop: Header=BB4_4 Depth=1
callq sqrtf
xorps %xmm1, %xmm1
.LBB4_7: # %.lr.ph.split
# in Loop: Header=BB4_4 Depth=1
cvttss2si %xmm0, %ecx
cmpl $2, %ecx
jl .LBB4_2
# %bb.8: # %.lr.ph.i.preheader
# in Loop: Header=BB4_4 Depth=1
negl %ecx
movl $2, %esi
.p2align 4, 0x90
.LBB4_9: # %.lr.ph.i
# Parent Loop BB4_4 Depth=1
# => This Inner Loop Header: Depth=2
xorl %edi, %edi
movl %r14d, %eax
xorl %edx, %edx
divl %esi
testl %edx, %edx
je .LBB4_3
# %bb.10: # in Loop: Header=BB4_9 Depth=2
leal (%rcx,%rsi), %eax
incl %eax
movl %esi, %edx
incl %edx
movl %edx, %esi
cmpl $1, %eax
jne .LBB4_9
jmp .LBB4_2
.LBB4_12:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB4_13: # %._crit_edge
retq
.Lfunc_end4:
.size _Z12getSeqPrimesPii, .Lfunc_end4-_Z12getSeqPrimesPii
.cfi_endproc
# -- End function
.globl _Z8sumArrayPii # -- Begin function _Z8sumArrayPii
.p2align 4, 0x90
.type _Z8sumArrayPii,@function
_Z8sumArrayPii: # @_Z8sumArrayPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB5_1
# %bb.2: # %.lr.ph.preheader
movl %esi, %ecx
xorl %edx, %edx
xorl %eax, %eax
.p2align 4, 0x90
.LBB5_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
addl (%rdi,%rdx,4), %eax
incq %rdx
cmpq %rdx, %rcx
jne .LBB5_3
# %bb.4: # %._crit_edge
retq
.LBB5_1:
xorl %eax, %eax
retq
.Lfunc_end5:
.size _Z8sumArrayPii, .Lfunc_end5-_Z8sumArrayPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9getPrimesPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9getPrimesPii,@object # @_Z9getPrimesPii
.section .rodata,"a",@progbits
.globl _Z9getPrimesPii
.p2align 3, 0x0
_Z9getPrimesPii:
.quad _Z24__device_stub__getPrimesPii
.size _Z9getPrimesPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " N: %d\n"
.size .L.str, 28
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " blockSize: %d\n"
.size .L.str.1, 28
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " gridSize: %d\n"
.size .L.str.2, 28
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "sequential prime count: %d\n"
.size .L.str.3, 28
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " parallel prime count: %d\n"
.size .L.str.4, 28
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " parallel time cost: %lf\n"
.size .L.str.5, 29
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " sequential time cost: %lf\n"
.size .L.str.6, 29
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " speedup: %lf\n"
.size .L.str.7, 29
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "usage: %s N blockSize\n"
.size .L.str.8, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9getPrimesPii"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__getPrimesPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9getPrimesPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <cuda.h>
#include <cuda_runtime.h>
__device__ int _inv(double *m, double *invOut);
__device__ void mult(double *A, double *B, double *C);
__device__ void copy(double *A, double *B);
__device__ void _eye(double *data);
// TODO: device level link class
// TODO: block >= 2048 error
/*
* Params
* T: double(N, 4, 4) the final transform matrix of all points (shared)
* tool: double(N, 4, 4) the tool transform matrix of all points (shared)
* nlinks_pt: long(N,): the number of links associated with each (shared)
* link_A: double(N, max_nlinks, 4, 4) the transformation matrix of all joints
* link_axes: long(max_nlinks, ): axes of all links
* link_isjoint: long(max_nlinks, ): 1/0 whether links are joints
* N: (int) number of points
* njoints: (int) number of joints
* out: (N, 6, njoints)
*/
__global__ void _jacob0(double *T,
double *tool,
double *etool,
double *link_A,
long *nlinks_pt,
long *link_axes,
long *link_isjoint,
int N,
int max_nlinks,
int njoints,
double *out)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
double *T_i;
double *tool_i;
double *U;
double *temp;
double *etool_i;
double *invU;
double *link_iA;
U = (double*) malloc(sizeof(double) * 16);
invU = (double*) malloc(sizeof(double) * 16);
temp = (double*) malloc(sizeof(double) * 16);
int j = 0;
tool_i = &tool[tid * 16];
etool_i = &etool[tid * 16];
_eye(U);
T_i = &T[tid * 16];
if (tid >= N) {
free(U);
free(invU);
free(temp);
return;
}
long nlinks = nlinks_pt[tid];
double *link_A_tid = &link_A[tid * max_nlinks * 4 * 4];
// printf("Hello from tid %d nlinks %ld\n", tid, nlinks);
for (int i = 0; i < nlinks; i++) {
// printf("Hello from tid %d link_i %d link_axis %ld isjoint %ld \n", tid, i, link_axes[i], link_isjoint[i]);
if (link_isjoint[i] == 1) {
link_iA = &link_A_tid[i * 16];
mult(U, link_iA, temp);
copy(temp, U);
if (i == nlinks - 1) {
mult(U, etool_i, temp);
copy(temp, U);
mult(U, tool_i, temp);
copy(temp , U);
}
_inv(U, invU);
mult(invU, T_i, temp);
double *out_tid = &out[tid * 6 * njoints];
if (link_axes[i] == 0) {
out_tid[0 * njoints + j] = U[0 * 4 + 2] * temp[1 * 4 + 3] - U[0 * 4 + 1] * temp[2 * 4 + 3];
out_tid[1 * njoints + j] = U[1 * 4 + 2] * temp[1 * 4 + 3] - U[1 * 4 + 1] * temp[2 * 4 + 3];
out_tid[2 * njoints + j] = U[2 * 4 + 2] * temp[1 * 4 + 3] - U[2 * 4 + 1] * temp[2 * 4 + 3];
out_tid[3 * njoints + j] = U[0 * 4 + 2];
out_tid[4 * njoints + j] = U[1 * 4 + 2];
out_tid[5 * njoints + j] = U[2 * 4 + 2];
}
else if (link_axes[i] == 1)
{
out_tid[0 * njoints + j] = U[0 * 4 + 0] * temp[2 * 4 + 3] - U[0 * 4 + 2] * temp[0 * 4 + 3];
out_tid[1 * njoints + j] = U[1 * 4 + 0] * temp[2 * 4 + 3] - U[1 * 4 + 2] * temp[0 * 4 + 3];
out_tid[2 * njoints + j] = U[2 * 4 + 0] * temp[2 * 4 + 3] - U[2 * 4 + 2] * temp[0 * 4 + 3];
out_tid[3 * njoints + j] = U[0 * 4 + 1];
out_tid[4 * njoints + j] = U[1 * 4 + 1];
out_tid[5 * njoints + j] = U[2 * 4 + 1];
}
else if (link_axes[i] == 2)
{
out_tid[0 * njoints + j] = U[0 * 4 + 1] * temp[0 * 4 + 3] - U[0 * 4 + 0] * temp[1 * 4 + 3];
out_tid[1 * njoints + j] = U[1 * 4 + 1] * temp[0 * 4 + 3] - U[1 * 4 + 0] * temp[1 * 4 + 3];
out_tid[2 * njoints + j] = U[2 * 4 + 1] * temp[0 * 4 + 3] - U[2 * 4 + 0] * temp[1 * 4 + 3];
out_tid[3 * njoints + j] = U[0 * 4 + 2];
out_tid[4 * njoints + j] = U[1 * 4 + 2];
out_tid[5 * njoints + j] = U[2 * 4 + 2];
}
else if (link_axes[i] == 3)
{
out_tid[0 * njoints + j] = U[0 * 4 + 0];
out_tid[1 * njoints + j] = U[1 * 4 + 0];
out_tid[2 * njoints + j] = U[2 * 4 + 0];
out_tid[3 * njoints + j] = 0.0;
out_tid[4 * njoints + j] = 0.0;
out_tid[5 * njoints + j] = 0.0;
}
else if (link_axes[i] == 4)
{
out_tid[0 * njoints + j] = U[0 * 4 + 1];
out_tid[1 * njoints + j] = U[1 * 4 + 1];
out_tid[2 * njoints + j] = U[2 * 4 + 1];
out_tid[3 * njoints + j] = 0.0;
out_tid[4 * njoints + j] = 0.0;
out_tid[5 * njoints + j] = 0.0;
}
else if (link_axes[i] == 5)
{
out_tid[0 * njoints + j] = U[0 * 4 + 2];
out_tid[1 * njoints + j] = U[1 * 4 + 2];
out_tid[2 * njoints + j] = U[2 * 4 + 2];
out_tid[3 * njoints + j] = 0.0;
out_tid[4 * njoints + j] = 0.0;
out_tid[5 * njoints + j] = 0.0;
}
j++;
}
else
{
link_iA = &link_A_tid[i * 16];
mult(U, link_iA, temp);
copy(temp, U);
}
}
free(U);
free(invU);
free(temp);
}
__device__ void _eye(double *data)
{
data[0] = 1;
data[1] = 0;
data[2] = 0;
data[3] = 0;
data[4] = 0;
data[5] = 1;
data[6] = 0;
data[7] = 0;
data[8] = 0;
data[9] = 0;
data[10] = 1;
data[11] = 0;
data[12] = 0;
data[13] = 0;
data[14] = 0;
data[15] = 1;
}
__device__ void copy(double *A, double *B)
{
// copy A into B
B[0] = A[0];
B[1] = A[1];
B[2] = A[2];
B[3] = A[3];
B[4] = A[4];
B[5] = A[5];
B[6] = A[6];
B[7] = A[7];
B[8] = A[8];
B[9] = A[9];
B[10] = A[10];
B[11] = A[11];
B[12] = A[12];
B[13] = A[13];
B[14] = A[14];
B[15] = A[15];
}
__device__ void mult(double *A, double *B, double *C)
{
const int N = 4;
int i, j, k;
double num;
for (i = 0; i < N; i++)
{
for (j = 0; j < N; j++)
{
num = 0;
for (k = 0; k < N; k++)
{
num += A[i * N + k] * B[k * N + j];
}
C[i * N + j] = num;
}
}
}
__device__ int _inv(double *m, double *invOut)
{
double *inv = (double*) malloc(sizeof(double) * 16);
double det;
int i;
inv[0] = m[5] * m[10] * m[15] -
m[5] * m[11] * m[14] -
m[9] * m[6] * m[15] +
m[9] * m[7] * m[14] +
m[13] * m[6] * m[11] -
m[13] * m[7] * m[10];
inv[4] = -m[4] * m[10] * m[15] +
m[4] * m[11] * m[14] +
m[8] * m[6] * m[15] -
m[8] * m[7] * m[14] -
m[12] * m[6] * m[11] +
m[12] * m[7] * m[10];
inv[8] = m[4] * m[9] * m[15] -
m[4] * m[11] * m[13] -
m[8] * m[5] * m[15] +
m[8] * m[7] * m[13] +
m[12] * m[5] * m[11] -
m[12] * m[7] * m[9];
inv[12] = -m[4] * m[9] * m[14] +
m[4] * m[10] * m[13] +
m[8] * m[5] * m[14] -
m[8] * m[6] * m[13] -
m[12] * m[5] * m[10] +
m[12] * m[6] * m[9];
inv[1] = -m[1] * m[10] * m[15] +
m[1] * m[11] * m[14] +
m[9] * m[2] * m[15] -
m[9] * m[3] * m[14] -
m[13] * m[2] * m[11] +
m[13] * m[3] * m[10];
inv[5] = m[0] * m[10] * m[15] -
m[0] * m[11] * m[14] -
m[8] * m[2] * m[15] +
m[8] * m[3] * m[14] +
m[12] * m[2] * m[11] -
m[12] * m[3] * m[10];
inv[9] = -m[0] * m[9] * m[15] +
m[0] * m[11] * m[13] +
m[8] * m[1] * m[15] -
m[8] * m[3] * m[13] -
m[12] * m[1] * m[11] +
m[12] * m[3] * m[9];
inv[13] = m[0] * m[9] * m[14] -
m[0] * m[10] * m[13] -
m[8] * m[1] * m[14] +
m[8] * m[2] * m[13] +
m[12] * m[1] * m[10] -
m[12] * m[2] * m[9];
inv[2] = m[1] * m[6] * m[15] -
m[1] * m[7] * m[14] -
m[5] * m[2] * m[15] +
m[5] * m[3] * m[14] +
m[13] * m[2] * m[7] -
m[13] * m[3] * m[6];
inv[6] = -m[0] * m[6] * m[15] +
m[0] * m[7] * m[14] +
m[4] * m[2] * m[15] -
m[4] * m[3] * m[14] -
m[12] * m[2] * m[7] +
m[12] * m[3] * m[6];
inv[10] = m[0] * m[5] * m[15] -
m[0] * m[7] * m[13] -
m[4] * m[1] * m[15] +
m[4] * m[3] * m[13] +
m[12] * m[1] * m[7] -
m[12] * m[3] * m[5];
inv[14] = -m[0] * m[5] * m[14] +
m[0] * m[6] * m[13] +
m[4] * m[1] * m[14] -
m[4] * m[2] * m[13] -
m[12] * m[1] * m[6] +
m[12] * m[2] * m[5];
inv[3] = -m[1] * m[6] * m[11] +
m[1] * m[7] * m[10] +
m[5] * m[2] * m[11] -
m[5] * m[3] * m[10] -
m[9] * m[2] * m[7] +
m[9] * m[3] * m[6];
inv[7] = m[0] * m[6] * m[11] -
m[0] * m[7] * m[10] -
m[4] * m[2] * m[11] +
m[4] * m[3] * m[10] +
m[8] * m[2] * m[7] -
m[8] * m[3] * m[6];
inv[11] = -m[0] * m[5] * m[11] +
m[0] * m[7] * m[9] +
m[4] * m[1] * m[11] -
m[4] * m[3] * m[9] -
m[8] * m[1] * m[7] +
m[8] * m[3] * m[5];
inv[15] = m[0] * m[5] * m[10] -
m[0] * m[6] * m[9] -
m[4] * m[1] * m[10] +
m[4] * m[2] * m[9] +
m[8] * m[1] * m[6] -
m[8] * m[2] * m[5];
det = m[0] * inv[0] + m[1] * inv[4] + m[2] * inv[8] + m[3] * inv[12];
if (det == 0) {
free(inv);
return 0;
}
det = 1.0 / det;
for (i = 0; i < 16; i++)
invOut[i] = inv[i] * det;
free(inv);
return 1;
}
extern "C"{
/*
* Params
* T: double(N, 4, 4) the final transform matrix of all points (shared)
* tool: double(N, 4, 4) the tool transform matrix of all points (shared)
* nlinks_pt: long(N,): the number of links associated with each (shared)
* link_A: double(N, max_nlinks, 4, 4) the transformation matrix of all joints
* link_axes: long(max_nlinks, ): axes of all links
* link_isjoint: long(max_nlinks, ): 1/0 whether links are joints
* N: (int) number of points
* max_nlinks: (int) max number of links on the path
* njoints: (int) number of joints
* out: (N, 6, njoints)
*/
void jacob0(double *T,
double *tool,
double *etool,
double *link_A,
long *nlinks_pt,
long *link_axes,
long *link_isjoint,
int N,
int max_nlinks,
int njoints,
double *out)
{
int block_size = 768;
int grid_size = ((N + block_size) / block_size);
// printf("Block size %d N %d gid size %d\n", block_size, N, grid_size);
double *d_T, *d_tool, *d_etool, *d_link_A;
long *d_link_axes, *d_link_isjoint, *d_nlinks_pt;
double *d_out;
cudaMalloc((void**)&d_T, sizeof(double) * N * 16);
cudaMalloc((void**)&d_tool, sizeof(double) * N * 16);
cudaMalloc((void**)&d_etool, sizeof(double) * N * 16);
cudaMalloc((void**)&d_link_A, sizeof(double) * N * max_nlinks * 16);
cudaMalloc((void**)&d_nlinks_pt, sizeof(long) * N);
cudaMalloc((void**)&d_link_axes, sizeof(long) * max_nlinks);
cudaMalloc((void**)&d_link_isjoint, sizeof(long) * max_nlinks);
cudaMalloc((void**)&d_out, sizeof(double) * N * 6 * njoints);
// Transfer data from host to device memory
cudaMemcpy(d_T, T, sizeof(double) * N * 16, cudaMemcpyHostToDevice);
cudaMemcpy(d_tool, tool, sizeof(double) * N * 16, cudaMemcpyHostToDevice);
cudaMemcpy(d_etool, etool, sizeof(double) * N * 16, cudaMemcpyHostToDevice);
cudaMemcpy(d_link_A, link_A, sizeof(double) * N * max_nlinks * 16, cudaMemcpyHostToDevice);
cudaMemcpy(d_nlinks_pt, nlinks_pt, sizeof(long) * N, cudaMemcpyHostToDevice);
cudaMemcpy(d_link_axes, link_axes, sizeof(long) * max_nlinks, cudaMemcpyHostToDevice);
cudaMemcpy(d_link_isjoint, link_isjoint, sizeof(long) * max_nlinks, cudaMemcpyHostToDevice);
cudaMemcpy(d_out, out, sizeof(double) * N * 6 * njoints, cudaMemcpyHostToDevice);
_jacob0<<<grid_size,block_size>>>(d_T,
d_tool,
d_etool,
d_link_A,
d_nlinks_pt,
d_link_axes,
d_link_isjoint,
N,
max_nlinks,
njoints,
d_out);
cudaError_t cudaerr = cudaDeviceSynchronize();
// if (cudaerr != cudaSuccess)
// printf("kernel launch failed with error \"%s\".\n",
// cudaGetErrorString(cudaerr));
// memset(out, 1, N * 6 * njoints);
// out[0] = 1;
cudaMemcpy(out, d_out, sizeof(double) * N * 6 * njoints, cudaMemcpyDeviceToHost);
// Deallocate device memory
cudaFree(d_T);
cudaFree(d_tool);
cudaFree(d_nlinks_pt);
cudaFree(d_etool);
cudaFree(d_link_A);
cudaFree(d_link_axes);
cudaFree(d_link_isjoint);
cudaFree(d_out);
}
}//extern "C" | .file "tmpxft_0017824e_00000000-6_fknm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4_eyePd
.type _Z4_eyePd, @function
_Z4_eyePd:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z4_eyePd, .-_Z4_eyePd
.globl _Z4copyPdS_
.type _Z4copyPdS_, @function
_Z4copyPdS_:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z4copyPdS_, .-_Z4copyPdS_
.globl _Z4multPdS_S_
.type _Z4multPdS_S_, @function
_Z4multPdS_S_:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z4multPdS_S_, .-_Z4multPdS_S_
.globl _Z4_invPdS_
.type _Z4_invPdS_, @function
_Z4_invPdS_:
.LFB2060:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size _Z4_invPdS_, .-_Z4_invPdS_
.globl _Z45__device_stub__Z7_jacob0PdS_S_S_PlS0_S0_iiiS_PdS_S_S_PlS0_S0_iiiS_
.type _Z45__device_stub__Z7_jacob0PdS_S_S_PlS0_S0_iiiS_PdS_S_S_PlS0_S0_iiiS_, @function
_Z45__device_stub__Z7_jacob0PdS_S_S_PlS0_S0_iiiS_PdS_S_S_PlS0_S0_iiiS_:
.LFB2086:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 240(%rsp), %rax
movq %rax, 8(%rsp)
movq 272(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 264(%rsp), %rax
movq %rax, 200(%rsp)
movq %rsp, %rax
movq %rax, 208(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z7_jacob0PdS_S_S_PlS0_S0_iiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z45__device_stub__Z7_jacob0PdS_S_S_PlS0_S0_iiiS_PdS_S_S_PlS0_S0_iiiS_, .-_Z45__device_stub__Z7_jacob0PdS_S_S_PlS0_S0_iiiS_PdS_S_S_PlS0_S0_iiiS_
.globl _Z7_jacob0PdS_S_S_PlS0_S0_iiiS_
.type _Z7_jacob0PdS_S_S_PlS0_S0_iiiS_, @function
_Z7_jacob0PdS_S_S_PlS0_S0_iiiS_:
.LFB2087:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 56(%rsp)
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z45__device_stub__Z7_jacob0PdS_S_S_PlS0_S0_iiiS_PdS_S_S_PlS0_S0_iiiS_
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z7_jacob0PdS_S_S_PlS0_S0_iiiS_, .-_Z7_jacob0PdS_S_S_PlS0_S0_iiiS_
.globl jacob0
.type jacob0, @function
jacob0:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $168, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 40(%rsp)
movq %r9, 48(%rsp)
movq 224(%rsp), %rax
movq %rax, 56(%rsp)
movq 256(%rsp), %r14
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movslq 232(%rsp), %r12
movq %r12, %rbp
salq $7, %rbp
leaq 64(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movslq 240(%rsp), %rbx
movq %r12, %r13
imulq %rbx, %r13
salq $7, %r13
leaq 88(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 0(,%r12,8), %r15
leaq 112(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
salq $3, %rbx
leaq 96(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 104(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movslq 248(%rsp), %rax
imulq %r12, %rax
leaq (%rax,%rax,2), %r12
salq $4, %r12
leaq 120(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq 8(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq 16(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq 24(%rsp), %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq 32(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r15, %rdx
movq 40(%rsp), %rsi
movq 112(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 48(%rsp), %rsi
movq 96(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 56(%rsp), %rsi
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq %r14, %rsi
movq 120(%rsp), %rdi
call cudaMemcpy@PLT
movl $768, 140(%rsp)
movl $1, 144(%rsp)
movl 232(%rsp), %eax
leal 768(%rax), %edx
movslq %edx, %rax
imulq $715827883, %rax, %rax
sarq $39, %rax
sarl $31, %edx
subl %edx, %eax
movl %eax, 128(%rsp)
movl $1, 132(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 140(%rsp), %rdx
movl $1, %ecx
movq 128(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L20:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %r12, %rdx
movq 120(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 112(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rdi
call cudaFree@PLT
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 232
pushq 128(%rsp)
.cfi_def_cfa_offset 240
movl 264(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 248
movl 264(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 256
movl 264(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 264
pushq 144(%rsp)
.cfi_def_cfa_offset 272
movq 144(%rsp), %r9
movq 160(%rsp), %r8
movq 136(%rsp), %rcx
movq 128(%rsp), %rdx
movq 120(%rsp), %rsi
movq 112(%rsp), %rdi
call _Z45__device_stub__Z7_jacob0PdS_S_S_PlS0_S0_iiiS_PdS_S_S_PlS0_S0_iiiS_
addq $48, %rsp
.cfi_def_cfa_offset 224
jmp .L20
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size jacob0, .-jacob0
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z7_jacob0PdS_S_S_PlS0_S0_iiiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7_jacob0PdS_S_S_PlS0_S0_iiiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <cuda.h>
#include <cuda_runtime.h>
__device__ int _inv(double *m, double *invOut);
__device__ void mult(double *A, double *B, double *C);
__device__ void copy(double *A, double *B);
__device__ void _eye(double *data);
// TODO: device level link class
// TODO: block >= 2048 error
/*
* Params
* T: double(N, 4, 4) the final transform matrix of all points (shared)
* tool: double(N, 4, 4) the tool transform matrix of all points (shared)
* nlinks_pt: long(N,): the number of links associated with each (shared)
* link_A: double(N, max_nlinks, 4, 4) the transformation matrix of all joints
* link_axes: long(max_nlinks, ): axes of all links
* link_isjoint: long(max_nlinks, ): 1/0 whether links are joints
* N: (int) number of points
* njoints: (int) number of joints
* out: (N, 6, njoints)
*/
__global__ void _jacob0(double *T,
double *tool,
double *etool,
double *link_A,
long *nlinks_pt,
long *link_axes,
long *link_isjoint,
int N,
int max_nlinks,
int njoints,
double *out)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
double *T_i;
double *tool_i;
double *U;
double *temp;
double *etool_i;
double *invU;
double *link_iA;
U = (double*) malloc(sizeof(double) * 16);
invU = (double*) malloc(sizeof(double) * 16);
temp = (double*) malloc(sizeof(double) * 16);
int j = 0;
tool_i = &tool[tid * 16];
etool_i = &etool[tid * 16];
_eye(U);
T_i = &T[tid * 16];
if (tid >= N) {
free(U);
free(invU);
free(temp);
return;
}
long nlinks = nlinks_pt[tid];
double *link_A_tid = &link_A[tid * max_nlinks * 4 * 4];
// printf("Hello from tid %d nlinks %ld\n", tid, nlinks);
for (int i = 0; i < nlinks; i++) {
// printf("Hello from tid %d link_i %d link_axis %ld isjoint %ld \n", tid, i, link_axes[i], link_isjoint[i]);
if (link_isjoint[i] == 1) {
link_iA = &link_A_tid[i * 16];
mult(U, link_iA, temp);
copy(temp, U);
if (i == nlinks - 1) {
mult(U, etool_i, temp);
copy(temp, U);
mult(U, tool_i, temp);
copy(temp , U);
}
_inv(U, invU);
mult(invU, T_i, temp);
double *out_tid = &out[tid * 6 * njoints];
if (link_axes[i] == 0) {
out_tid[0 * njoints + j] = U[0 * 4 + 2] * temp[1 * 4 + 3] - U[0 * 4 + 1] * temp[2 * 4 + 3];
out_tid[1 * njoints + j] = U[1 * 4 + 2] * temp[1 * 4 + 3] - U[1 * 4 + 1] * temp[2 * 4 + 3];
out_tid[2 * njoints + j] = U[2 * 4 + 2] * temp[1 * 4 + 3] - U[2 * 4 + 1] * temp[2 * 4 + 3];
out_tid[3 * njoints + j] = U[0 * 4 + 2];
out_tid[4 * njoints + j] = U[1 * 4 + 2];
out_tid[5 * njoints + j] = U[2 * 4 + 2];
}
else if (link_axes[i] == 1)
{
out_tid[0 * njoints + j] = U[0 * 4 + 0] * temp[2 * 4 + 3] - U[0 * 4 + 2] * temp[0 * 4 + 3];
out_tid[1 * njoints + j] = U[1 * 4 + 0] * temp[2 * 4 + 3] - U[1 * 4 + 2] * temp[0 * 4 + 3];
out_tid[2 * njoints + j] = U[2 * 4 + 0] * temp[2 * 4 + 3] - U[2 * 4 + 2] * temp[0 * 4 + 3];
out_tid[3 * njoints + j] = U[0 * 4 + 1];
out_tid[4 * njoints + j] = U[1 * 4 + 1];
out_tid[5 * njoints + j] = U[2 * 4 + 1];
}
else if (link_axes[i] == 2)
{
out_tid[0 * njoints + j] = U[0 * 4 + 1] * temp[0 * 4 + 3] - U[0 * 4 + 0] * temp[1 * 4 + 3];
out_tid[1 * njoints + j] = U[1 * 4 + 1] * temp[0 * 4 + 3] - U[1 * 4 + 0] * temp[1 * 4 + 3];
out_tid[2 * njoints + j] = U[2 * 4 + 1] * temp[0 * 4 + 3] - U[2 * 4 + 0] * temp[1 * 4 + 3];
out_tid[3 * njoints + j] = U[0 * 4 + 2];
out_tid[4 * njoints + j] = U[1 * 4 + 2];
out_tid[5 * njoints + j] = U[2 * 4 + 2];
}
else if (link_axes[i] == 3)
{
out_tid[0 * njoints + j] = U[0 * 4 + 0];
out_tid[1 * njoints + j] = U[1 * 4 + 0];
out_tid[2 * njoints + j] = U[2 * 4 + 0];
out_tid[3 * njoints + j] = 0.0;
out_tid[4 * njoints + j] = 0.0;
out_tid[5 * njoints + j] = 0.0;
}
else if (link_axes[i] == 4)
{
out_tid[0 * njoints + j] = U[0 * 4 + 1];
out_tid[1 * njoints + j] = U[1 * 4 + 1];
out_tid[2 * njoints + j] = U[2 * 4 + 1];
out_tid[3 * njoints + j] = 0.0;
out_tid[4 * njoints + j] = 0.0;
out_tid[5 * njoints + j] = 0.0;
}
else if (link_axes[i] == 5)
{
out_tid[0 * njoints + j] = U[0 * 4 + 2];
out_tid[1 * njoints + j] = U[1 * 4 + 2];
out_tid[2 * njoints + j] = U[2 * 4 + 2];
out_tid[3 * njoints + j] = 0.0;
out_tid[4 * njoints + j] = 0.0;
out_tid[5 * njoints + j] = 0.0;
}
j++;
}
else
{
link_iA = &link_A_tid[i * 16];
mult(U, link_iA, temp);
copy(temp, U);
}
}
free(U);
free(invU);
free(temp);
}
__device__ void _eye(double *data)
{
data[0] = 1;
data[1] = 0;
data[2] = 0;
data[3] = 0;
data[4] = 0;
data[5] = 1;
data[6] = 0;
data[7] = 0;
data[8] = 0;
data[9] = 0;
data[10] = 1;
data[11] = 0;
data[12] = 0;
data[13] = 0;
data[14] = 0;
data[15] = 1;
}
__device__ void copy(double *A, double *B)
{
// copy A into B
B[0] = A[0];
B[1] = A[1];
B[2] = A[2];
B[3] = A[3];
B[4] = A[4];
B[5] = A[5];
B[6] = A[6];
B[7] = A[7];
B[8] = A[8];
B[9] = A[9];
B[10] = A[10];
B[11] = A[11];
B[12] = A[12];
B[13] = A[13];
B[14] = A[14];
B[15] = A[15];
}
__device__ void mult(double *A, double *B, double *C)
{
const int N = 4;
int i, j, k;
double num;
for (i = 0; i < N; i++)
{
for (j = 0; j < N; j++)
{
num = 0;
for (k = 0; k < N; k++)
{
num += A[i * N + k] * B[k * N + j];
}
C[i * N + j] = num;
}
}
}
__device__ int _inv(double *m, double *invOut)
{
double *inv = (double*) malloc(sizeof(double) * 16);
double det;
int i;
inv[0] = m[5] * m[10] * m[15] -
m[5] * m[11] * m[14] -
m[9] * m[6] * m[15] +
m[9] * m[7] * m[14] +
m[13] * m[6] * m[11] -
m[13] * m[7] * m[10];
inv[4] = -m[4] * m[10] * m[15] +
m[4] * m[11] * m[14] +
m[8] * m[6] * m[15] -
m[8] * m[7] * m[14] -
m[12] * m[6] * m[11] +
m[12] * m[7] * m[10];
inv[8] = m[4] * m[9] * m[15] -
m[4] * m[11] * m[13] -
m[8] * m[5] * m[15] +
m[8] * m[7] * m[13] +
m[12] * m[5] * m[11] -
m[12] * m[7] * m[9];
inv[12] = -m[4] * m[9] * m[14] +
m[4] * m[10] * m[13] +
m[8] * m[5] * m[14] -
m[8] * m[6] * m[13] -
m[12] * m[5] * m[10] +
m[12] * m[6] * m[9];
inv[1] = -m[1] * m[10] * m[15] +
m[1] * m[11] * m[14] +
m[9] * m[2] * m[15] -
m[9] * m[3] * m[14] -
m[13] * m[2] * m[11] +
m[13] * m[3] * m[10];
inv[5] = m[0] * m[10] * m[15] -
m[0] * m[11] * m[14] -
m[8] * m[2] * m[15] +
m[8] * m[3] * m[14] +
m[12] * m[2] * m[11] -
m[12] * m[3] * m[10];
inv[9] = -m[0] * m[9] * m[15] +
m[0] * m[11] * m[13] +
m[8] * m[1] * m[15] -
m[8] * m[3] * m[13] -
m[12] * m[1] * m[11] +
m[12] * m[3] * m[9];
inv[13] = m[0] * m[9] * m[14] -
m[0] * m[10] * m[13] -
m[8] * m[1] * m[14] +
m[8] * m[2] * m[13] +
m[12] * m[1] * m[10] -
m[12] * m[2] * m[9];
inv[2] = m[1] * m[6] * m[15] -
m[1] * m[7] * m[14] -
m[5] * m[2] * m[15] +
m[5] * m[3] * m[14] +
m[13] * m[2] * m[7] -
m[13] * m[3] * m[6];
inv[6] = -m[0] * m[6] * m[15] +
m[0] * m[7] * m[14] +
m[4] * m[2] * m[15] -
m[4] * m[3] * m[14] -
m[12] * m[2] * m[7] +
m[12] * m[3] * m[6];
inv[10] = m[0] * m[5] * m[15] -
m[0] * m[7] * m[13] -
m[4] * m[1] * m[15] +
m[4] * m[3] * m[13] +
m[12] * m[1] * m[7] -
m[12] * m[3] * m[5];
inv[14] = -m[0] * m[5] * m[14] +
m[0] * m[6] * m[13] +
m[4] * m[1] * m[14] -
m[4] * m[2] * m[13] -
m[12] * m[1] * m[6] +
m[12] * m[2] * m[5];
inv[3] = -m[1] * m[6] * m[11] +
m[1] * m[7] * m[10] +
m[5] * m[2] * m[11] -
m[5] * m[3] * m[10] -
m[9] * m[2] * m[7] +
m[9] * m[3] * m[6];
inv[7] = m[0] * m[6] * m[11] -
m[0] * m[7] * m[10] -
m[4] * m[2] * m[11] +
m[4] * m[3] * m[10] +
m[8] * m[2] * m[7] -
m[8] * m[3] * m[6];
inv[11] = -m[0] * m[5] * m[11] +
m[0] * m[7] * m[9] +
m[4] * m[1] * m[11] -
m[4] * m[3] * m[9] -
m[8] * m[1] * m[7] +
m[8] * m[3] * m[5];
inv[15] = m[0] * m[5] * m[10] -
m[0] * m[6] * m[9] -
m[4] * m[1] * m[10] +
m[4] * m[2] * m[9] +
m[8] * m[1] * m[6] -
m[8] * m[2] * m[5];
det = m[0] * inv[0] + m[1] * inv[4] + m[2] * inv[8] + m[3] * inv[12];
if (det == 0) {
free(inv);
return 0;
}
det = 1.0 / det;
for (i = 0; i < 16; i++)
invOut[i] = inv[i] * det;
free(inv);
return 1;
}
extern "C"{
/*
* Params
* T: double(N, 4, 4) the final transform matrix of all points (shared)
* tool: double(N, 4, 4) the tool transform matrix of all points (shared)
* nlinks_pt: long(N,): the number of links associated with each (shared)
* link_A: double(N, max_nlinks, 4, 4) the transformation matrix of all joints
* link_axes: long(max_nlinks, ): axes of all links
* link_isjoint: long(max_nlinks, ): 1/0 whether links are joints
* N: (int) number of points
* max_nlinks: (int) max number of links on the path
* njoints: (int) number of joints
* out: (N, 6, njoints)
*/
void jacob0(double *T,
double *tool,
double *etool,
double *link_A,
long *nlinks_pt,
long *link_axes,
long *link_isjoint,
int N,
int max_nlinks,
int njoints,
double *out)
{
int block_size = 768;
int grid_size = ((N + block_size) / block_size);
// printf("Block size %d N %d gid size %d\n", block_size, N, grid_size);
double *d_T, *d_tool, *d_etool, *d_link_A;
long *d_link_axes, *d_link_isjoint, *d_nlinks_pt;
double *d_out;
cudaMalloc((void**)&d_T, sizeof(double) * N * 16);
cudaMalloc((void**)&d_tool, sizeof(double) * N * 16);
cudaMalloc((void**)&d_etool, sizeof(double) * N * 16);
cudaMalloc((void**)&d_link_A, sizeof(double) * N * max_nlinks * 16);
cudaMalloc((void**)&d_nlinks_pt, sizeof(long) * N);
cudaMalloc((void**)&d_link_axes, sizeof(long) * max_nlinks);
cudaMalloc((void**)&d_link_isjoint, sizeof(long) * max_nlinks);
cudaMalloc((void**)&d_out, sizeof(double) * N * 6 * njoints);
// Transfer data from host to device memory
cudaMemcpy(d_T, T, sizeof(double) * N * 16, cudaMemcpyHostToDevice);
cudaMemcpy(d_tool, tool, sizeof(double) * N * 16, cudaMemcpyHostToDevice);
cudaMemcpy(d_etool, etool, sizeof(double) * N * 16, cudaMemcpyHostToDevice);
cudaMemcpy(d_link_A, link_A, sizeof(double) * N * max_nlinks * 16, cudaMemcpyHostToDevice);
cudaMemcpy(d_nlinks_pt, nlinks_pt, sizeof(long) * N, cudaMemcpyHostToDevice);
cudaMemcpy(d_link_axes, link_axes, sizeof(long) * max_nlinks, cudaMemcpyHostToDevice);
cudaMemcpy(d_link_isjoint, link_isjoint, sizeof(long) * max_nlinks, cudaMemcpyHostToDevice);
cudaMemcpy(d_out, out, sizeof(double) * N * 6 * njoints, cudaMemcpyHostToDevice);
_jacob0<<<grid_size,block_size>>>(d_T,
d_tool,
d_etool,
d_link_A,
d_nlinks_pt,
d_link_axes,
d_link_isjoint,
N,
max_nlinks,
njoints,
d_out);
cudaError_t cudaerr = cudaDeviceSynchronize();
// if (cudaerr != cudaSuccess)
// printf("kernel launch failed with error \"%s\".\n",
// cudaGetErrorString(cudaerr));
// memset(out, 1, N * 6 * njoints);
// out[0] = 1;
cudaMemcpy(out, d_out, sizeof(double) * N * 6 * njoints, cudaMemcpyDeviceToHost);
// Deallocate device memory
cudaFree(d_T);
cudaFree(d_tool);
cudaFree(d_nlinks_pt);
cudaFree(d_etool);
cudaFree(d_link_A);
cudaFree(d_link_axes);
cudaFree(d_link_isjoint);
cudaFree(d_out);
}
}//extern "C" | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <hip/hip_runtime.h>
__device__ int _inv(double *m, double *invOut);
__device__ void mult(double *A, double *B, double *C);
__device__ void copy(double *A, double *B);
__device__ void _eye(double *data);
// TODO: device level link class
// TODO: block >= 2048 error
/*
* Params
* T: double(N, 4, 4) the final transform matrix of all points (shared)
* tool: double(N, 4, 4) the tool transform matrix of all points (shared)
* nlinks_pt: long(N,): the number of links associated with each (shared)
* link_A: double(N, max_nlinks, 4, 4) the transformation matrix of all joints
* link_axes: long(max_nlinks, ): axes of all links
* link_isjoint: long(max_nlinks, ): 1/0 whether links are joints
* N: (int) number of points
* njoints: (int) number of joints
* out: (N, 6, njoints)
*/
__global__ void _jacob0(double *T,
double *tool,
double *etool,
double *link_A,
long *nlinks_pt,
long *link_axes,
long *link_isjoint,
int N,
int max_nlinks,
int njoints,
double *out)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
double *T_i;
double *tool_i;
double *U;
double *temp;
double *etool_i;
double *invU;
double *link_iA;
U = (double*) malloc(sizeof(double) * 16);
invU = (double*) malloc(sizeof(double) * 16);
temp = (double*) malloc(sizeof(double) * 16);
int j = 0;
tool_i = &tool[tid * 16];
etool_i = &etool[tid * 16];
_eye(U);
T_i = &T[tid * 16];
if (tid >= N) {
free(U);
free(invU);
free(temp);
return;
}
long nlinks = nlinks_pt[tid];
double *link_A_tid = &link_A[tid * max_nlinks * 4 * 4];
// printf("Hello from tid %d nlinks %ld\n", tid, nlinks);
for (int i = 0; i < nlinks; i++) {
// printf("Hello from tid %d link_i %d link_axis %ld isjoint %ld \n", tid, i, link_axes[i], link_isjoint[i]);
if (link_isjoint[i] == 1) {
link_iA = &link_A_tid[i * 16];
mult(U, link_iA, temp);
copy(temp, U);
if (i == nlinks - 1) {
mult(U, etool_i, temp);
copy(temp, U);
mult(U, tool_i, temp);
copy(temp , U);
}
_inv(U, invU);
mult(invU, T_i, temp);
double *out_tid = &out[tid * 6 * njoints];
if (link_axes[i] == 0) {
out_tid[0 * njoints + j] = U[0 * 4 + 2] * temp[1 * 4 + 3] - U[0 * 4 + 1] * temp[2 * 4 + 3];
out_tid[1 * njoints + j] = U[1 * 4 + 2] * temp[1 * 4 + 3] - U[1 * 4 + 1] * temp[2 * 4 + 3];
out_tid[2 * njoints + j] = U[2 * 4 + 2] * temp[1 * 4 + 3] - U[2 * 4 + 1] * temp[2 * 4 + 3];
out_tid[3 * njoints + j] = U[0 * 4 + 2];
out_tid[4 * njoints + j] = U[1 * 4 + 2];
out_tid[5 * njoints + j] = U[2 * 4 + 2];
}
else if (link_axes[i] == 1)
{
out_tid[0 * njoints + j] = U[0 * 4 + 0] * temp[2 * 4 + 3] - U[0 * 4 + 2] * temp[0 * 4 + 3];
out_tid[1 * njoints + j] = U[1 * 4 + 0] * temp[2 * 4 + 3] - U[1 * 4 + 2] * temp[0 * 4 + 3];
out_tid[2 * njoints + j] = U[2 * 4 + 0] * temp[2 * 4 + 3] - U[2 * 4 + 2] * temp[0 * 4 + 3];
out_tid[3 * njoints + j] = U[0 * 4 + 1];
out_tid[4 * njoints + j] = U[1 * 4 + 1];
out_tid[5 * njoints + j] = U[2 * 4 + 1];
}
else if (link_axes[i] == 2)
{
out_tid[0 * njoints + j] = U[0 * 4 + 1] * temp[0 * 4 + 3] - U[0 * 4 + 0] * temp[1 * 4 + 3];
out_tid[1 * njoints + j] = U[1 * 4 + 1] * temp[0 * 4 + 3] - U[1 * 4 + 0] * temp[1 * 4 + 3];
out_tid[2 * njoints + j] = U[2 * 4 + 1] * temp[0 * 4 + 3] - U[2 * 4 + 0] * temp[1 * 4 + 3];
out_tid[3 * njoints + j] = U[0 * 4 + 2];
out_tid[4 * njoints + j] = U[1 * 4 + 2];
out_tid[5 * njoints + j] = U[2 * 4 + 2];
}
else if (link_axes[i] == 3)
{
out_tid[0 * njoints + j] = U[0 * 4 + 0];
out_tid[1 * njoints + j] = U[1 * 4 + 0];
out_tid[2 * njoints + j] = U[2 * 4 + 0];
out_tid[3 * njoints + j] = 0.0;
out_tid[4 * njoints + j] = 0.0;
out_tid[5 * njoints + j] = 0.0;
}
else if (link_axes[i] == 4)
{
out_tid[0 * njoints + j] = U[0 * 4 + 1];
out_tid[1 * njoints + j] = U[1 * 4 + 1];
out_tid[2 * njoints + j] = U[2 * 4 + 1];
out_tid[3 * njoints + j] = 0.0;
out_tid[4 * njoints + j] = 0.0;
out_tid[5 * njoints + j] = 0.0;
}
else if (link_axes[i] == 5)
{
out_tid[0 * njoints + j] = U[0 * 4 + 2];
out_tid[1 * njoints + j] = U[1 * 4 + 2];
out_tid[2 * njoints + j] = U[2 * 4 + 2];
out_tid[3 * njoints + j] = 0.0;
out_tid[4 * njoints + j] = 0.0;
out_tid[5 * njoints + j] = 0.0;
}
j++;
}
else
{
link_iA = &link_A_tid[i * 16];
mult(U, link_iA, temp);
copy(temp, U);
}
}
free(U);
free(invU);
free(temp);
}
__device__ void _eye(double *data)
{
data[0] = 1;
data[1] = 0;
data[2] = 0;
data[3] = 0;
data[4] = 0;
data[5] = 1;
data[6] = 0;
data[7] = 0;
data[8] = 0;
data[9] = 0;
data[10] = 1;
data[11] = 0;
data[12] = 0;
data[13] = 0;
data[14] = 0;
data[15] = 1;
}
__device__ void copy(double *A, double *B)
{
// copy A into B
B[0] = A[0];
B[1] = A[1];
B[2] = A[2];
B[3] = A[3];
B[4] = A[4];
B[5] = A[5];
B[6] = A[6];
B[7] = A[7];
B[8] = A[8];
B[9] = A[9];
B[10] = A[10];
B[11] = A[11];
B[12] = A[12];
B[13] = A[13];
B[14] = A[14];
B[15] = A[15];
}
__device__ void mult(double *A, double *B, double *C)
{
const int N = 4;
int i, j, k;
double num;
for (i = 0; i < N; i++)
{
for (j = 0; j < N; j++)
{
num = 0;
for (k = 0; k < N; k++)
{
num += A[i * N + k] * B[k * N + j];
}
C[i * N + j] = num;
}
}
}
__device__ int _inv(double *m, double *invOut)
{
double *inv = (double*) malloc(sizeof(double) * 16);
double det;
int i;
inv[0] = m[5] * m[10] * m[15] -
m[5] * m[11] * m[14] -
m[9] * m[6] * m[15] +
m[9] * m[7] * m[14] +
m[13] * m[6] * m[11] -
m[13] * m[7] * m[10];
inv[4] = -m[4] * m[10] * m[15] +
m[4] * m[11] * m[14] +
m[8] * m[6] * m[15] -
m[8] * m[7] * m[14] -
m[12] * m[6] * m[11] +
m[12] * m[7] * m[10];
inv[8] = m[4] * m[9] * m[15] -
m[4] * m[11] * m[13] -
m[8] * m[5] * m[15] +
m[8] * m[7] * m[13] +
m[12] * m[5] * m[11] -
m[12] * m[7] * m[9];
inv[12] = -m[4] * m[9] * m[14] +
m[4] * m[10] * m[13] +
m[8] * m[5] * m[14] -
m[8] * m[6] * m[13] -
m[12] * m[5] * m[10] +
m[12] * m[6] * m[9];
inv[1] = -m[1] * m[10] * m[15] +
m[1] * m[11] * m[14] +
m[9] * m[2] * m[15] -
m[9] * m[3] * m[14] -
m[13] * m[2] * m[11] +
m[13] * m[3] * m[10];
inv[5] = m[0] * m[10] * m[15] -
m[0] * m[11] * m[14] -
m[8] * m[2] * m[15] +
m[8] * m[3] * m[14] +
m[12] * m[2] * m[11] -
m[12] * m[3] * m[10];
inv[9] = -m[0] * m[9] * m[15] +
m[0] * m[11] * m[13] +
m[8] * m[1] * m[15] -
m[8] * m[3] * m[13] -
m[12] * m[1] * m[11] +
m[12] * m[3] * m[9];
inv[13] = m[0] * m[9] * m[14] -
m[0] * m[10] * m[13] -
m[8] * m[1] * m[14] +
m[8] * m[2] * m[13] +
m[12] * m[1] * m[10] -
m[12] * m[2] * m[9];
inv[2] = m[1] * m[6] * m[15] -
m[1] * m[7] * m[14] -
m[5] * m[2] * m[15] +
m[5] * m[3] * m[14] +
m[13] * m[2] * m[7] -
m[13] * m[3] * m[6];
inv[6] = -m[0] * m[6] * m[15] +
m[0] * m[7] * m[14] +
m[4] * m[2] * m[15] -
m[4] * m[3] * m[14] -
m[12] * m[2] * m[7] +
m[12] * m[3] * m[6];
inv[10] = m[0] * m[5] * m[15] -
m[0] * m[7] * m[13] -
m[4] * m[1] * m[15] +
m[4] * m[3] * m[13] +
m[12] * m[1] * m[7] -
m[12] * m[3] * m[5];
inv[14] = -m[0] * m[5] * m[14] +
m[0] * m[6] * m[13] +
m[4] * m[1] * m[14] -
m[4] * m[2] * m[13] -
m[12] * m[1] * m[6] +
m[12] * m[2] * m[5];
inv[3] = -m[1] * m[6] * m[11] +
m[1] * m[7] * m[10] +
m[5] * m[2] * m[11] -
m[5] * m[3] * m[10] -
m[9] * m[2] * m[7] +
m[9] * m[3] * m[6];
inv[7] = m[0] * m[6] * m[11] -
m[0] * m[7] * m[10] -
m[4] * m[2] * m[11] +
m[4] * m[3] * m[10] +
m[8] * m[2] * m[7] -
m[8] * m[3] * m[6];
inv[11] = -m[0] * m[5] * m[11] +
m[0] * m[7] * m[9] +
m[4] * m[1] * m[11] -
m[4] * m[3] * m[9] -
m[8] * m[1] * m[7] +
m[8] * m[3] * m[5];
inv[15] = m[0] * m[5] * m[10] -
m[0] * m[6] * m[9] -
m[4] * m[1] * m[10] +
m[4] * m[2] * m[9] +
m[8] * m[1] * m[6] -
m[8] * m[2] * m[5];
det = m[0] * inv[0] + m[1] * inv[4] + m[2] * inv[8] + m[3] * inv[12];
if (det == 0) {
free(inv);
return 0;
}
det = 1.0 / det;
for (i = 0; i < 16; i++)
invOut[i] = inv[i] * det;
free(inv);
return 1;
}
extern "C"{
/*
* Params
* T: double(N, 4, 4) the final transform matrix of all points (shared)
* tool: double(N, 4, 4) the tool transform matrix of all points (shared)
* nlinks_pt: long(N,): the number of links associated with each (shared)
* link_A: double(N, max_nlinks, 4, 4) the transformation matrix of all joints
* link_axes: long(max_nlinks, ): axes of all links
* link_isjoint: long(max_nlinks, ): 1/0 whether links are joints
* N: (int) number of points
* max_nlinks: (int) max number of links on the path
* njoints: (int) number of joints
* out: (N, 6, njoints)
*/
void jacob0(double *T,
double *tool,
double *etool,
double *link_A,
long *nlinks_pt,
long *link_axes,
long *link_isjoint,
int N,
int max_nlinks,
int njoints,
double *out)
{
int block_size = 768;
int grid_size = ((N + block_size) / block_size);
// printf("Block size %d N %d gid size %d\n", block_size, N, grid_size);
double *d_T, *d_tool, *d_etool, *d_link_A;
long *d_link_axes, *d_link_isjoint, *d_nlinks_pt;
double *d_out;
hipMalloc((void**)&d_T, sizeof(double) * N * 16);
hipMalloc((void**)&d_tool, sizeof(double) * N * 16);
hipMalloc((void**)&d_etool, sizeof(double) * N * 16);
hipMalloc((void**)&d_link_A, sizeof(double) * N * max_nlinks * 16);
hipMalloc((void**)&d_nlinks_pt, sizeof(long) * N);
hipMalloc((void**)&d_link_axes, sizeof(long) * max_nlinks);
hipMalloc((void**)&d_link_isjoint, sizeof(long) * max_nlinks);
hipMalloc((void**)&d_out, sizeof(double) * N * 6 * njoints);
// Transfer data from host to device memory
hipMemcpy(d_T, T, sizeof(double) * N * 16, hipMemcpyHostToDevice);
hipMemcpy(d_tool, tool, sizeof(double) * N * 16, hipMemcpyHostToDevice);
hipMemcpy(d_etool, etool, sizeof(double) * N * 16, hipMemcpyHostToDevice);
hipMemcpy(d_link_A, link_A, sizeof(double) * N * max_nlinks * 16, hipMemcpyHostToDevice);
hipMemcpy(d_nlinks_pt, nlinks_pt, sizeof(long) * N, hipMemcpyHostToDevice);
hipMemcpy(d_link_axes, link_axes, sizeof(long) * max_nlinks, hipMemcpyHostToDevice);
hipMemcpy(d_link_isjoint, link_isjoint, sizeof(long) * max_nlinks, hipMemcpyHostToDevice);
hipMemcpy(d_out, out, sizeof(double) * N * 6 * njoints, hipMemcpyHostToDevice);
_jacob0<<<grid_size,block_size>>>(d_T,
d_tool,
d_etool,
d_link_A,
d_nlinks_pt,
d_link_axes,
d_link_isjoint,
N,
max_nlinks,
njoints,
d_out);
hipError_t cudaerr = hipDeviceSynchronize();
// if (cudaerr != cudaSuccess)
// printf("kernel launch failed with error \"%s\".\n",
// cudaGetErrorString(cudaerr));
// memset(out, 1, N * 6 * njoints);
// out[0] = 1;
hipMemcpy(out, d_out, sizeof(double) * N * 6 * njoints, hipMemcpyDeviceToHost);
// Deallocate device memory
hipFree(d_T);
hipFree(d_tool);
hipFree(d_nlinks_pt);
hipFree(d_etool);
hipFree(d_link_A);
hipFree(d_link_axes);
hipFree(d_link_isjoint);
hipFree(d_out);
}
}//extern "C" |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <hip/hip_runtime.h>
__device__ int _inv(double *m, double *invOut);
__device__ void mult(double *A, double *B, double *C);
__device__ void copy(double *A, double *B);
__device__ void _eye(double *data);
// TODO: device level link class
// TODO: block >= 2048 error
/*
* Params
* T: double(N, 4, 4) the final transform matrix of all points (shared)
* tool: double(N, 4, 4) the tool transform matrix of all points (shared)
* nlinks_pt: long(N,): the number of links associated with each (shared)
* link_A: double(N, max_nlinks, 4, 4) the transformation matrix of all joints
* link_axes: long(max_nlinks, ): axes of all links
* link_isjoint: long(max_nlinks, ): 1/0 whether links are joints
* N: (int) number of points
* njoints: (int) number of joints
* out: (N, 6, njoints)
*/
__global__ void _jacob0(double *T,
double *tool,
double *etool,
double *link_A,
long *nlinks_pt,
long *link_axes,
long *link_isjoint,
int N,
int max_nlinks,
int njoints,
double *out)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
double *T_i;
double *tool_i;
double *U;
double *temp;
double *etool_i;
double *invU;
double *link_iA;
U = (double*) malloc(sizeof(double) * 16);
invU = (double*) malloc(sizeof(double) * 16);
temp = (double*) malloc(sizeof(double) * 16);
int j = 0;
tool_i = &tool[tid * 16];
etool_i = &etool[tid * 16];
_eye(U);
T_i = &T[tid * 16];
if (tid >= N) {
free(U);
free(invU);
free(temp);
return;
}
long nlinks = nlinks_pt[tid];
double *link_A_tid = &link_A[tid * max_nlinks * 4 * 4];
// printf("Hello from tid %d nlinks %ld\n", tid, nlinks);
for (int i = 0; i < nlinks; i++) {
// printf("Hello from tid %d link_i %d link_axis %ld isjoint %ld \n", tid, i, link_axes[i], link_isjoint[i]);
if (link_isjoint[i] == 1) {
link_iA = &link_A_tid[i * 16];
mult(U, link_iA, temp);
copy(temp, U);
if (i == nlinks - 1) {
mult(U, etool_i, temp);
copy(temp, U);
mult(U, tool_i, temp);
copy(temp , U);
}
_inv(U, invU);
mult(invU, T_i, temp);
double *out_tid = &out[tid * 6 * njoints];
if (link_axes[i] == 0) {
out_tid[0 * njoints + j] = U[0 * 4 + 2] * temp[1 * 4 + 3] - U[0 * 4 + 1] * temp[2 * 4 + 3];
out_tid[1 * njoints + j] = U[1 * 4 + 2] * temp[1 * 4 + 3] - U[1 * 4 + 1] * temp[2 * 4 + 3];
out_tid[2 * njoints + j] = U[2 * 4 + 2] * temp[1 * 4 + 3] - U[2 * 4 + 1] * temp[2 * 4 + 3];
out_tid[3 * njoints + j] = U[0 * 4 + 2];
out_tid[4 * njoints + j] = U[1 * 4 + 2];
out_tid[5 * njoints + j] = U[2 * 4 + 2];
}
else if (link_axes[i] == 1)
{
out_tid[0 * njoints + j] = U[0 * 4 + 0] * temp[2 * 4 + 3] - U[0 * 4 + 2] * temp[0 * 4 + 3];
out_tid[1 * njoints + j] = U[1 * 4 + 0] * temp[2 * 4 + 3] - U[1 * 4 + 2] * temp[0 * 4 + 3];
out_tid[2 * njoints + j] = U[2 * 4 + 0] * temp[2 * 4 + 3] - U[2 * 4 + 2] * temp[0 * 4 + 3];
out_tid[3 * njoints + j] = U[0 * 4 + 1];
out_tid[4 * njoints + j] = U[1 * 4 + 1];
out_tid[5 * njoints + j] = U[2 * 4 + 1];
}
else if (link_axes[i] == 2)
{
out_tid[0 * njoints + j] = U[0 * 4 + 1] * temp[0 * 4 + 3] - U[0 * 4 + 0] * temp[1 * 4 + 3];
out_tid[1 * njoints + j] = U[1 * 4 + 1] * temp[0 * 4 + 3] - U[1 * 4 + 0] * temp[1 * 4 + 3];
out_tid[2 * njoints + j] = U[2 * 4 + 1] * temp[0 * 4 + 3] - U[2 * 4 + 0] * temp[1 * 4 + 3];
out_tid[3 * njoints + j] = U[0 * 4 + 2];
out_tid[4 * njoints + j] = U[1 * 4 + 2];
out_tid[5 * njoints + j] = U[2 * 4 + 2];
}
else if (link_axes[i] == 3)
{
out_tid[0 * njoints + j] = U[0 * 4 + 0];
out_tid[1 * njoints + j] = U[1 * 4 + 0];
out_tid[2 * njoints + j] = U[2 * 4 + 0];
out_tid[3 * njoints + j] = 0.0;
out_tid[4 * njoints + j] = 0.0;
out_tid[5 * njoints + j] = 0.0;
}
else if (link_axes[i] == 4)
{
out_tid[0 * njoints + j] = U[0 * 4 + 1];
out_tid[1 * njoints + j] = U[1 * 4 + 1];
out_tid[2 * njoints + j] = U[2 * 4 + 1];
out_tid[3 * njoints + j] = 0.0;
out_tid[4 * njoints + j] = 0.0;
out_tid[5 * njoints + j] = 0.0;
}
else if (link_axes[i] == 5)
{
out_tid[0 * njoints + j] = U[0 * 4 + 2];
out_tid[1 * njoints + j] = U[1 * 4 + 2];
out_tid[2 * njoints + j] = U[2 * 4 + 2];
out_tid[3 * njoints + j] = 0.0;
out_tid[4 * njoints + j] = 0.0;
out_tid[5 * njoints + j] = 0.0;
}
j++;
}
else
{
link_iA = &link_A_tid[i * 16];
mult(U, link_iA, temp);
copy(temp, U);
}
}
free(U);
free(invU);
free(temp);
}
__device__ void _eye(double *data)
{
data[0] = 1;
data[1] = 0;
data[2] = 0;
data[3] = 0;
data[4] = 0;
data[5] = 1;
data[6] = 0;
data[7] = 0;
data[8] = 0;
data[9] = 0;
data[10] = 1;
data[11] = 0;
data[12] = 0;
data[13] = 0;
data[14] = 0;
data[15] = 1;
}
__device__ void copy(double *A, double *B)
{
// copy A into B
B[0] = A[0];
B[1] = A[1];
B[2] = A[2];
B[3] = A[3];
B[4] = A[4];
B[5] = A[5];
B[6] = A[6];
B[7] = A[7];
B[8] = A[8];
B[9] = A[9];
B[10] = A[10];
B[11] = A[11];
B[12] = A[12];
B[13] = A[13];
B[14] = A[14];
B[15] = A[15];
}
__device__ void mult(double *A, double *B, double *C)
{
const int N = 4;
int i, j, k;
double num;
for (i = 0; i < N; i++)
{
for (j = 0; j < N; j++)
{
num = 0;
for (k = 0; k < N; k++)
{
num += A[i * N + k] * B[k * N + j];
}
C[i * N + j] = num;
}
}
}
__device__ int _inv(double *m, double *invOut)
{
double *inv = (double*) malloc(sizeof(double) * 16);
double det;
int i;
inv[0] = m[5] * m[10] * m[15] -
m[5] * m[11] * m[14] -
m[9] * m[6] * m[15] +
m[9] * m[7] * m[14] +
m[13] * m[6] * m[11] -
m[13] * m[7] * m[10];
inv[4] = -m[4] * m[10] * m[15] +
m[4] * m[11] * m[14] +
m[8] * m[6] * m[15] -
m[8] * m[7] * m[14] -
m[12] * m[6] * m[11] +
m[12] * m[7] * m[10];
inv[8] = m[4] * m[9] * m[15] -
m[4] * m[11] * m[13] -
m[8] * m[5] * m[15] +
m[8] * m[7] * m[13] +
m[12] * m[5] * m[11] -
m[12] * m[7] * m[9];
inv[12] = -m[4] * m[9] * m[14] +
m[4] * m[10] * m[13] +
m[8] * m[5] * m[14] -
m[8] * m[6] * m[13] -
m[12] * m[5] * m[10] +
m[12] * m[6] * m[9];
inv[1] = -m[1] * m[10] * m[15] +
m[1] * m[11] * m[14] +
m[9] * m[2] * m[15] -
m[9] * m[3] * m[14] -
m[13] * m[2] * m[11] +
m[13] * m[3] * m[10];
inv[5] = m[0] * m[10] * m[15] -
m[0] * m[11] * m[14] -
m[8] * m[2] * m[15] +
m[8] * m[3] * m[14] +
m[12] * m[2] * m[11] -
m[12] * m[3] * m[10];
inv[9] = -m[0] * m[9] * m[15] +
m[0] * m[11] * m[13] +
m[8] * m[1] * m[15] -
m[8] * m[3] * m[13] -
m[12] * m[1] * m[11] +
m[12] * m[3] * m[9];
inv[13] = m[0] * m[9] * m[14] -
m[0] * m[10] * m[13] -
m[8] * m[1] * m[14] +
m[8] * m[2] * m[13] +
m[12] * m[1] * m[10] -
m[12] * m[2] * m[9];
inv[2] = m[1] * m[6] * m[15] -
m[1] * m[7] * m[14] -
m[5] * m[2] * m[15] +
m[5] * m[3] * m[14] +
m[13] * m[2] * m[7] -
m[13] * m[3] * m[6];
inv[6] = -m[0] * m[6] * m[15] +
m[0] * m[7] * m[14] +
m[4] * m[2] * m[15] -
m[4] * m[3] * m[14] -
m[12] * m[2] * m[7] +
m[12] * m[3] * m[6];
inv[10] = m[0] * m[5] * m[15] -
m[0] * m[7] * m[13] -
m[4] * m[1] * m[15] +
m[4] * m[3] * m[13] +
m[12] * m[1] * m[7] -
m[12] * m[3] * m[5];
inv[14] = -m[0] * m[5] * m[14] +
m[0] * m[6] * m[13] +
m[4] * m[1] * m[14] -
m[4] * m[2] * m[13] -
m[12] * m[1] * m[6] +
m[12] * m[2] * m[5];
inv[3] = -m[1] * m[6] * m[11] +
m[1] * m[7] * m[10] +
m[5] * m[2] * m[11] -
m[5] * m[3] * m[10] -
m[9] * m[2] * m[7] +
m[9] * m[3] * m[6];
inv[7] = m[0] * m[6] * m[11] -
m[0] * m[7] * m[10] -
m[4] * m[2] * m[11] +
m[4] * m[3] * m[10] +
m[8] * m[2] * m[7] -
m[8] * m[3] * m[6];
inv[11] = -m[0] * m[5] * m[11] +
m[0] * m[7] * m[9] +
m[4] * m[1] * m[11] -
m[4] * m[3] * m[9] -
m[8] * m[1] * m[7] +
m[8] * m[3] * m[5];
inv[15] = m[0] * m[5] * m[10] -
m[0] * m[6] * m[9] -
m[4] * m[1] * m[10] +
m[4] * m[2] * m[9] +
m[8] * m[1] * m[6] -
m[8] * m[2] * m[5];
det = m[0] * inv[0] + m[1] * inv[4] + m[2] * inv[8] + m[3] * inv[12];
if (det == 0) {
free(inv);
return 0;
}
det = 1.0 / det;
for (i = 0; i < 16; i++)
invOut[i] = inv[i] * det;
free(inv);
return 1;
}
extern "C"{
/*
* Params
* T: double(N, 4, 4) the final transform matrix of all points (shared)
* tool: double(N, 4, 4) the tool transform matrix of all points (shared)
* nlinks_pt: long(N,): the number of links associated with each (shared)
* link_A: double(N, max_nlinks, 4, 4) the transformation matrix of all joints
* link_axes: long(max_nlinks, ): axes of all links
* link_isjoint: long(max_nlinks, ): 1/0 whether links are joints
* N: (int) number of points
* max_nlinks: (int) max number of links on the path
* njoints: (int) number of joints
* out: (N, 6, njoints)
*/
void jacob0(double *T,
double *tool,
double *etool,
double *link_A,
long *nlinks_pt,
long *link_axes,
long *link_isjoint,
int N,
int max_nlinks,
int njoints,
double *out)
{
int block_size = 768;
int grid_size = ((N + block_size) / block_size);
// printf("Block size %d N %d gid size %d\n", block_size, N, grid_size);
double *d_T, *d_tool, *d_etool, *d_link_A;
long *d_link_axes, *d_link_isjoint, *d_nlinks_pt;
double *d_out;
hipMalloc((void**)&d_T, sizeof(double) * N * 16);
hipMalloc((void**)&d_tool, sizeof(double) * N * 16);
hipMalloc((void**)&d_etool, sizeof(double) * N * 16);
hipMalloc((void**)&d_link_A, sizeof(double) * N * max_nlinks * 16);
hipMalloc((void**)&d_nlinks_pt, sizeof(long) * N);
hipMalloc((void**)&d_link_axes, sizeof(long) * max_nlinks);
hipMalloc((void**)&d_link_isjoint, sizeof(long) * max_nlinks);
hipMalloc((void**)&d_out, sizeof(double) * N * 6 * njoints);
// Transfer data from host to device memory
hipMemcpy(d_T, T, sizeof(double) * N * 16, hipMemcpyHostToDevice);
hipMemcpy(d_tool, tool, sizeof(double) * N * 16, hipMemcpyHostToDevice);
hipMemcpy(d_etool, etool, sizeof(double) * N * 16, hipMemcpyHostToDevice);
hipMemcpy(d_link_A, link_A, sizeof(double) * N * max_nlinks * 16, hipMemcpyHostToDevice);
hipMemcpy(d_nlinks_pt, nlinks_pt, sizeof(long) * N, hipMemcpyHostToDevice);
hipMemcpy(d_link_axes, link_axes, sizeof(long) * max_nlinks, hipMemcpyHostToDevice);
hipMemcpy(d_link_isjoint, link_isjoint, sizeof(long) * max_nlinks, hipMemcpyHostToDevice);
hipMemcpy(d_out, out, sizeof(double) * N * 6 * njoints, hipMemcpyHostToDevice);
_jacob0<<<grid_size,block_size>>>(d_T,
d_tool,
d_etool,
d_link_A,
d_nlinks_pt,
d_link_axes,
d_link_isjoint,
N,
max_nlinks,
njoints,
d_out);
hipError_t cudaerr = hipDeviceSynchronize();
// if (cudaerr != cudaSuccess)
// printf("kernel launch failed with error \"%s\".\n",
// cudaGetErrorString(cudaerr));
// memset(out, 1, N * 6 * njoints);
// out[0] = 1;
hipMemcpy(out, d_out, sizeof(double) * N * 6 * njoints, hipMemcpyDeviceToHost);
// Deallocate device memory
hipFree(d_T);
hipFree(d_tool);
hipFree(d_nlinks_pt);
hipFree(d_etool);
hipFree(d_link_A);
hipFree(d_link_axes);
hipFree(d_link_isjoint);
hipFree(d_out);
}
}//extern "C" | .text
.file "fknm.hip"
.globl _Z22__device_stub___jacob0PdS_S_S_PlS0_S0_iiiS_ # -- Begin function _Z22__device_stub___jacob0PdS_S_S_PlS0_S0_iiiS_
.p2align 4, 0x90
.type _Z22__device_stub___jacob0PdS_S_S_PlS0_S0_iiiS_,@function
_Z22__device_stub___jacob0PdS_S_S_PlS0_S0_iiiS_: # @_Z22__device_stub___jacob0PdS_S_S_PlS0_S0_iiiS_
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7_jacob0PdS_S_S_PlS0_S0_iiiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z22__device_stub___jacob0PdS_S_S_PlS0_S0_iiiS_, .Lfunc_end0-_Z22__device_stub___jacob0PdS_S_S_PlS0_S0_iiiS_
.cfi_endproc
# -- End function
.globl jacob0 # -- Begin function jacob0
.p2align 4, 0x90
.type jacob0,@function
jacob0: # @jacob0
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $360, %rsp # imm = 0x168
.cfi_def_cfa_offset 416
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, 152(%rsp) # 8-byte Spill
movq %r8, 144(%rsp) # 8-byte Spill
movq %rcx, 136(%rsp) # 8-byte Spill
movq %rdx, 128(%rsp) # 8-byte Spill
movq %rsi, 120(%rsp) # 8-byte Spill
movq %rdi, 112(%rsp) # 8-byte Spill
movslq 440(%rsp), %rax
movq %rax, 88(%rsp) # 8-byte Spill
movslq 432(%rsp), %rbp
movslq 424(%rsp), %r14
leal 768(%r14), %eax
cltq
imulq $715827883, %rax, %r15 # imm = 0x2AAAAAAB
movq %r15, %rax
shrq $63, %rax
sarq $39, %r15
addl %eax, %r15d
leaq (,%r14,8), %r12
movq %r14, %r13
shlq $7, %r13
leaq 64(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 56(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq %rbp, %rbx
imulq %r12, %rbx
shlq $4, %rbx
leaq 40(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq %rbp, 104(%rsp) # 8-byte Spill
leaq (,%rbp,8), %rbp
leaq 32(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movq %r14, 96(%rsp) # 8-byte Spill
movq 88(%rsp), %rcx # 8-byte Reload
imulq %rcx, %r14
shlq $4, %r14
leaq (%r14,%r14,2), %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 64(%rsp), %rdi
movq 112(%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rdi
movq 120(%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movq 128(%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movq 136(%rsp), %rsi # 8-byte Reload
movq %rbx, %rdx
movq 448(%rsp), %rbx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq 144(%rsp), %rsi # 8-byte Reload
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movq 152(%rsp), %rsi # 8-byte Reload
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq 416(%rsp), %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %r15
orq $768, %rdx # imm = 0x300
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 64(%rsp), %rax
movq 56(%rsp), %rcx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 16(%rsp), %rdi
movq 32(%rsp), %r8
movq 24(%rsp), %r9
movq 8(%rsp), %r10
movq %rax, 264(%rsp)
movq %rcx, 256(%rsp)
movq %rdx, 248(%rsp)
movq %rsi, 240(%rsp)
movq %rdi, 232(%rsp)
movq %r8, 224(%rsp)
movq %r9, 216(%rsp)
movq 96(%rsp), %rax # 8-byte Reload
movl %eax, 84(%rsp)
movq 104(%rsp), %rax # 8-byte Reload
movl %eax, 80(%rsp)
movq 88(%rsp), %rax # 8-byte Reload
movl %eax, 76(%rsp)
movq %r10, 208(%rsp)
leaq 264(%rsp), %rax
movq %rax, 272(%rsp)
leaq 256(%rsp), %rax
movq %rax, 280(%rsp)
leaq 248(%rsp), %rax
movq %rax, 288(%rsp)
leaq 240(%rsp), %rax
movq %rax, 296(%rsp)
leaq 232(%rsp), %rax
movq %rax, 304(%rsp)
leaq 224(%rsp), %rax
movq %rax, 312(%rsp)
leaq 216(%rsp), %rax
movq %rax, 320(%rsp)
leaq 84(%rsp), %rax
movq %rax, 328(%rsp)
leaq 80(%rsp), %rax
movq %rax, 336(%rsp)
leaq 76(%rsp), %rax
movq %rax, 344(%rsp)
leaq 208(%rsp), %rax
movq %rax, 352(%rsp)
leaq 192(%rsp), %rdi
leaq 176(%rsp), %rsi
leaq 168(%rsp), %rdx
leaq 160(%rsp), %rcx
callq __hipPopCallConfiguration
movq 192(%rsp), %rsi
movl 200(%rsp), %edx
movq 176(%rsp), %rcx
movl 184(%rsp), %r8d
leaq 272(%rsp), %r9
movl $_Z7_jacob0PdS_S_S_PlS0_S0_iiiS_, %edi
pushq 160(%rsp)
.cfi_adjust_cfa_offset 8
pushq 176(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 64(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $360, %rsp # imm = 0x168
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size jacob0, .Lfunc_end1-jacob0
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7_jacob0PdS_S_S_PlS0_S0_iiiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7_jacob0PdS_S_S_PlS0_S0_iiiS_,@object # @_Z7_jacob0PdS_S_S_PlS0_S0_iiiS_
.section .rodata,"a",@progbits
.globl _Z7_jacob0PdS_S_S_PlS0_S0_iiiS_
.p2align 3, 0x0
_Z7_jacob0PdS_S_S_PlS0_S0_iiiS_:
.quad _Z22__device_stub___jacob0PdS_S_S_PlS0_S0_iiiS_
.size _Z7_jacob0PdS_S_S_PlS0_S0_iiiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7_jacob0PdS_S_S_PlS0_S0_iiiS_"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub___jacob0PdS_S_S_PlS0_S0_iiiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7_jacob0PdS_S_S_PlS0_S0_iiiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0017824e_00000000-6_fknm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4_eyePd
.type _Z4_eyePd, @function
_Z4_eyePd:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z4_eyePd, .-_Z4_eyePd
.globl _Z4copyPdS_
.type _Z4copyPdS_, @function
_Z4copyPdS_:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z4copyPdS_, .-_Z4copyPdS_
.globl _Z4multPdS_S_
.type _Z4multPdS_S_, @function
_Z4multPdS_S_:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z4multPdS_S_, .-_Z4multPdS_S_
.globl _Z4_invPdS_
.type _Z4_invPdS_, @function
_Z4_invPdS_:
.LFB2060:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size _Z4_invPdS_, .-_Z4_invPdS_
.globl _Z45__device_stub__Z7_jacob0PdS_S_S_PlS0_S0_iiiS_PdS_S_S_PlS0_S0_iiiS_
.type _Z45__device_stub__Z7_jacob0PdS_S_S_PlS0_S0_iiiS_PdS_S_S_PlS0_S0_iiiS_, @function
_Z45__device_stub__Z7_jacob0PdS_S_S_PlS0_S0_iiiS_PdS_S_S_PlS0_S0_iiiS_:
.LFB2086:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 240(%rsp), %rax
movq %rax, 8(%rsp)
movq 272(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 264(%rsp), %rax
movq %rax, 200(%rsp)
movq %rsp, %rax
movq %rax, 208(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z7_jacob0PdS_S_S_PlS0_S0_iiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z45__device_stub__Z7_jacob0PdS_S_S_PlS0_S0_iiiS_PdS_S_S_PlS0_S0_iiiS_, .-_Z45__device_stub__Z7_jacob0PdS_S_S_PlS0_S0_iiiS_PdS_S_S_PlS0_S0_iiiS_
.globl _Z7_jacob0PdS_S_S_PlS0_S0_iiiS_
.type _Z7_jacob0PdS_S_S_PlS0_S0_iiiS_, @function
_Z7_jacob0PdS_S_S_PlS0_S0_iiiS_:
.LFB2087:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 56(%rsp)
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z45__device_stub__Z7_jacob0PdS_S_S_PlS0_S0_iiiS_PdS_S_S_PlS0_S0_iiiS_
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z7_jacob0PdS_S_S_PlS0_S0_iiiS_, .-_Z7_jacob0PdS_S_S_PlS0_S0_iiiS_
.globl jacob0
.type jacob0, @function
jacob0:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $168, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 40(%rsp)
movq %r9, 48(%rsp)
movq 224(%rsp), %rax
movq %rax, 56(%rsp)
movq 256(%rsp), %r14
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movslq 232(%rsp), %r12
movq %r12, %rbp
salq $7, %rbp
leaq 64(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movslq 240(%rsp), %rbx
movq %r12, %r13
imulq %rbx, %r13
salq $7, %r13
leaq 88(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 0(,%r12,8), %r15
leaq 112(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
salq $3, %rbx
leaq 96(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 104(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movslq 248(%rsp), %rax
imulq %r12, %rax
leaq (%rax,%rax,2), %r12
salq $4, %r12
leaq 120(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq 8(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq 16(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq 24(%rsp), %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq 32(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r15, %rdx
movq 40(%rsp), %rsi
movq 112(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 48(%rsp), %rsi
movq 96(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 56(%rsp), %rsi
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq %r14, %rsi
movq 120(%rsp), %rdi
call cudaMemcpy@PLT
movl $768, 140(%rsp)
movl $1, 144(%rsp)
movl 232(%rsp), %eax
leal 768(%rax), %edx
movslq %edx, %rax
imulq $715827883, %rax, %rax
sarq $39, %rax
sarl $31, %edx
subl %edx, %eax
movl %eax, 128(%rsp)
movl $1, 132(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 140(%rsp), %rdx
movl $1, %ecx
movq 128(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L20:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %r12, %rdx
movq 120(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 112(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rdi
call cudaFree@PLT
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 232
pushq 128(%rsp)
.cfi_def_cfa_offset 240
movl 264(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 248
movl 264(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 256
movl 264(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 264
pushq 144(%rsp)
.cfi_def_cfa_offset 272
movq 144(%rsp), %r9
movq 160(%rsp), %r8
movq 136(%rsp), %rcx
movq 128(%rsp), %rdx
movq 120(%rsp), %rsi
movq 112(%rsp), %rdi
call _Z45__device_stub__Z7_jacob0PdS_S_S_PlS0_S0_iiiS_PdS_S_S_PlS0_S0_iiiS_
addq $48, %rsp
.cfi_def_cfa_offset 224
jmp .L20
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size jacob0, .-jacob0
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z7_jacob0PdS_S_S_PlS0_S0_iiiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7_jacob0PdS_S_S_PlS0_S0_iiiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "fknm.hip"
.globl _Z22__device_stub___jacob0PdS_S_S_PlS0_S0_iiiS_ # -- Begin function _Z22__device_stub___jacob0PdS_S_S_PlS0_S0_iiiS_
.p2align 4, 0x90
.type _Z22__device_stub___jacob0PdS_S_S_PlS0_S0_iiiS_,@function
_Z22__device_stub___jacob0PdS_S_S_PlS0_S0_iiiS_: # @_Z22__device_stub___jacob0PdS_S_S_PlS0_S0_iiiS_
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7_jacob0PdS_S_S_PlS0_S0_iiiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z22__device_stub___jacob0PdS_S_S_PlS0_S0_iiiS_, .Lfunc_end0-_Z22__device_stub___jacob0PdS_S_S_PlS0_S0_iiiS_
.cfi_endproc
# -- End function
.globl jacob0 # -- Begin function jacob0
.p2align 4, 0x90
.type jacob0,@function
jacob0: # @jacob0
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $360, %rsp # imm = 0x168
.cfi_def_cfa_offset 416
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, 152(%rsp) # 8-byte Spill
movq %r8, 144(%rsp) # 8-byte Spill
movq %rcx, 136(%rsp) # 8-byte Spill
movq %rdx, 128(%rsp) # 8-byte Spill
movq %rsi, 120(%rsp) # 8-byte Spill
movq %rdi, 112(%rsp) # 8-byte Spill
movslq 440(%rsp), %rax
movq %rax, 88(%rsp) # 8-byte Spill
movslq 432(%rsp), %rbp
movslq 424(%rsp), %r14
leal 768(%r14), %eax
cltq
imulq $715827883, %rax, %r15 # imm = 0x2AAAAAAB
movq %r15, %rax
shrq $63, %rax
sarq $39, %r15
addl %eax, %r15d
leaq (,%r14,8), %r12
movq %r14, %r13
shlq $7, %r13
leaq 64(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 56(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq %rbp, %rbx
imulq %r12, %rbx
shlq $4, %rbx
leaq 40(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq %rbp, 104(%rsp) # 8-byte Spill
leaq (,%rbp,8), %rbp
leaq 32(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movq %r14, 96(%rsp) # 8-byte Spill
movq 88(%rsp), %rcx # 8-byte Reload
imulq %rcx, %r14
shlq $4, %r14
leaq (%r14,%r14,2), %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 64(%rsp), %rdi
movq 112(%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rdi
movq 120(%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movq 128(%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movq 136(%rsp), %rsi # 8-byte Reload
movq %rbx, %rdx
movq 448(%rsp), %rbx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq 144(%rsp), %rsi # 8-byte Reload
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movq 152(%rsp), %rsi # 8-byte Reload
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq 416(%rsp), %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %r15
orq $768, %rdx # imm = 0x300
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 64(%rsp), %rax
movq 56(%rsp), %rcx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 16(%rsp), %rdi
movq 32(%rsp), %r8
movq 24(%rsp), %r9
movq 8(%rsp), %r10
movq %rax, 264(%rsp)
movq %rcx, 256(%rsp)
movq %rdx, 248(%rsp)
movq %rsi, 240(%rsp)
movq %rdi, 232(%rsp)
movq %r8, 224(%rsp)
movq %r9, 216(%rsp)
movq 96(%rsp), %rax # 8-byte Reload
movl %eax, 84(%rsp)
movq 104(%rsp), %rax # 8-byte Reload
movl %eax, 80(%rsp)
movq 88(%rsp), %rax # 8-byte Reload
movl %eax, 76(%rsp)
movq %r10, 208(%rsp)
leaq 264(%rsp), %rax
movq %rax, 272(%rsp)
leaq 256(%rsp), %rax
movq %rax, 280(%rsp)
leaq 248(%rsp), %rax
movq %rax, 288(%rsp)
leaq 240(%rsp), %rax
movq %rax, 296(%rsp)
leaq 232(%rsp), %rax
movq %rax, 304(%rsp)
leaq 224(%rsp), %rax
movq %rax, 312(%rsp)
leaq 216(%rsp), %rax
movq %rax, 320(%rsp)
leaq 84(%rsp), %rax
movq %rax, 328(%rsp)
leaq 80(%rsp), %rax
movq %rax, 336(%rsp)
leaq 76(%rsp), %rax
movq %rax, 344(%rsp)
leaq 208(%rsp), %rax
movq %rax, 352(%rsp)
leaq 192(%rsp), %rdi
leaq 176(%rsp), %rsi
leaq 168(%rsp), %rdx
leaq 160(%rsp), %rcx
callq __hipPopCallConfiguration
movq 192(%rsp), %rsi
movl 200(%rsp), %edx
movq 176(%rsp), %rcx
movl 184(%rsp), %r8d
leaq 272(%rsp), %r9
movl $_Z7_jacob0PdS_S_S_PlS0_S0_iiiS_, %edi
pushq 160(%rsp)
.cfi_adjust_cfa_offset 8
pushq 176(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 64(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $360, %rsp # imm = 0x168
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size jacob0, .Lfunc_end1-jacob0
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7_jacob0PdS_S_S_PlS0_S0_iiiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7_jacob0PdS_S_S_PlS0_S0_iiiS_,@object # @_Z7_jacob0PdS_S_S_PlS0_S0_iiiS_
.section .rodata,"a",@progbits
.globl _Z7_jacob0PdS_S_S_PlS0_S0_iiiS_
.p2align 3, 0x0
_Z7_jacob0PdS_S_S_PlS0_S0_iiiS_:
.quad _Z22__device_stub___jacob0PdS_S_S_PlS0_S0_iiiS_
.size _Z7_jacob0PdS_S_S_PlS0_S0_iiiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7_jacob0PdS_S_S_PlS0_S0_iiiS_"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub___jacob0PdS_S_S_PlS0_S0_iiiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7_jacob0PdS_S_S_PlS0_S0_iiiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "stdio.h"
#include<iostream>
//Defining Number of elements in Array
#define N 5
//Defining vector addition function for CPU
void cpuAdd(int *h_a, int *h_b, int *h_c) {
int tid = 0;
while (tid < N)
{
h_c[tid] = h_a[tid] + h_b[tid];
tid += 1;
}
}
int main(void) {
int h_a[N], h_b[N], h_c[N];
//Initializing two arrays for addition
for (int i = 0; i < N; i++) {
h_a[i] = 2 * i*i;
h_b[i] = i;
}
//Calling CPU function for vector addition
cpuAdd (h_a, h_b, h_c);
//Printing Answer
printf("Vector addition on CPU\n");
for (int i = 0; i < N; i++) {
printf("The sum of %d element is %d + %d = %d\n", i, h_a[i], h_b[i], h_c[i]);
}
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "stdio.h"
#include<iostream>
//Defining Number of elements in Array
#define N 5
//Defining vector addition function for CPU
void cpuAdd(int *h_a, int *h_b, int *h_c) {
int tid = 0;
while (tid < N)
{
h_c[tid] = h_a[tid] + h_b[tid];
tid += 1;
}
}
int main(void) {
int h_a[N], h_b[N], h_c[N];
//Initializing two arrays for addition
for (int i = 0; i < N; i++) {
h_a[i] = 2 * i*i;
h_b[i] = i;
}
//Calling CPU function for vector addition
cpuAdd (h_a, h_b, h_c);
//Printing Answer
printf("Vector addition on CPU\n");
for (int i = 0; i < N; i++) {
printf("The sum of %d element is %d + %d = %d\n", i, h_a[i], h_b[i], h_c[i]);
}
return 0;
} | .file "tmpxft_0015501e_00000000-6_06_vector_addition_cpu.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6cpuAddPiS_S_
.type _Z6cpuAddPiS_S_, @function
_Z6cpuAddPiS_S_:
.LFB3669:
.cfi_startproc
endbr64
movl $0, %eax
.L4:
movl (%rsi,%rax), %ecx
addl (%rdi,%rax), %ecx
movl %ecx, (%rdx,%rax)
addq $4, %rax
cmpq $20, %rax
jne .L4
ret
.cfi_endproc
.LFE3669:
.size _Z6cpuAddPiS_S_, .-_Z6cpuAddPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Vector addition on CPU\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "The sum of %d element is %d + %d = %d\n"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $104, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $0, (%rsp)
movl $0, 32(%rsp)
movl $2, 4(%rsp)
movl $1, 36(%rsp)
movl $8, 8(%rsp)
movl $2, 40(%rsp)
movl $18, 12(%rsp)
movl $3, 44(%rsp)
movl $32, 16(%rsp)
movl $4, 48(%rsp)
leaq 64(%rsp), %rdx
leaq 32(%rsp), %rsi
movq %rsp, %rdi
call _Z6cpuAddPiS_S_
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC1(%rip), %rbp
.L7:
movl (%rsp,%rbx,4), %ecx
movl 64(%rsp,%rbx,4), %r9d
movl 32(%rsp,%rbx,4), %r8d
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $5, %rbx
jne .L7
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L11
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "stdio.h"
#include<iostream>
//Defining Number of elements in Array
#define N 5
//Defining vector addition function for CPU
void cpuAdd(int *h_a, int *h_b, int *h_c) {
int tid = 0;
while (tid < N)
{
h_c[tid] = h_a[tid] + h_b[tid];
tid += 1;
}
}
int main(void) {
int h_a[N], h_b[N], h_c[N];
//Initializing two arrays for addition
for (int i = 0; i < N; i++) {
h_a[i] = 2 * i*i;
h_b[i] = i;
}
//Calling CPU function for vector addition
cpuAdd (h_a, h_b, h_c);
//Printing Answer
printf("Vector addition on CPU\n");
for (int i = 0; i < N; i++) {
printf("The sum of %d element is %d + %d = %d\n", i, h_a[i], h_b[i], h_c[i]);
}
return 0;
} | #include <hip/hip_runtime.h>
#include "stdio.h"
#include<iostream>
//Defining Number of elements in Array
#define N 5
//Defining vector addition function for CPU
void cpuAdd(int *h_a, int *h_b, int *h_c) {
int tid = 0;
while (tid < N)
{
h_c[tid] = h_a[tid] + h_b[tid];
tid += 1;
}
}
int main(void) {
int h_a[N], h_b[N], h_c[N];
//Initializing two arrays for addition
for (int i = 0; i < N; i++) {
h_a[i] = 2 * i*i;
h_b[i] = i;
}
//Calling CPU function for vector addition
cpuAdd (h_a, h_b, h_c);
//Printing Answer
printf("Vector addition on CPU\n");
for (int i = 0; i < N; i++) {
printf("The sum of %d element is %d + %d = %d\n", i, h_a[i], h_b[i], h_c[i]);
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "stdio.h"
#include<iostream>
//Defining Number of elements in Array
#define N 5
//Defining vector addition function for CPU
void cpuAdd(int *h_a, int *h_b, int *h_c) {
int tid = 0;
while (tid < N)
{
h_c[tid] = h_a[tid] + h_b[tid];
tid += 1;
}
}
int main(void) {
int h_a[N], h_b[N], h_c[N];
//Initializing two arrays for addition
for (int i = 0; i < N; i++) {
h_a[i] = 2 * i*i;
h_b[i] = i;
}
//Calling CPU function for vector addition
cpuAdd (h_a, h_b, h_c);
//Printing Answer
printf("Vector addition on CPU\n");
for (int i = 0; i < N; i++) {
printf("The sum of %d element is %d + %d = %d\n", i, h_a[i], h_b[i], h_c[i]);
}
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "stdio.h"
#include<iostream>
//Defining Number of elements in Array
#define N 5
//Defining vector addition function for CPU
void cpuAdd(int *h_a, int *h_b, int *h_c) {
int tid = 0;
while (tid < N)
{
h_c[tid] = h_a[tid] + h_b[tid];
tid += 1;
}
}
int main(void) {
int h_a[N], h_b[N], h_c[N];
//Initializing two arrays for addition
for (int i = 0; i < N; i++) {
h_a[i] = 2 * i*i;
h_b[i] = i;
}
//Calling CPU function for vector addition
cpuAdd (h_a, h_b, h_c);
//Printing Answer
printf("Vector addition on CPU\n");
for (int i = 0; i < N; i++) {
printf("The sum of %d element is %d + %d = %d\n", i, h_a[i], h_b[i], h_c[i]);
}
return 0;
} | .text
.file "06_vector_addition_cpu.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z6cpuAddPiS_S_ # -- Begin function _Z6cpuAddPiS_S_
.p2align 4, 0x90
.type _Z6cpuAddPiS_S_,@function
_Z6cpuAddPiS_S_: # @_Z6cpuAddPiS_S_
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl (%rsi,%rax,4), %ecx
addl (%rdi,%rax,4), %ecx
movl %ecx, (%rdx,%rax,4)
incq %rax
cmpq $5, %rax
jne .LBB0_1
# %bb.2:
retq
.Lfunc_end0:
.size _Z6cpuAddPiS_S_, .Lfunc_end0-_Z6cpuAddPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $96, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, %ecx
imull %eax, %ecx
addl %ecx, %ecx
movl %ecx, 32(%rsp,%rax,4)
movl %eax, (%rsp,%rax,4)
incq %rax
cmpq $5, %rax
jne .LBB1_1
# %bb.2: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_3: # %.preheader
# =>This Inner Loop Header: Depth=1
movl (%rsp,%rax,4), %ecx
addl 32(%rsp,%rax,4), %ecx
movl %ecx, 64(%rsp,%rax,4)
incq %rax
cmpq $5, %rax
jne .LBB1_3
# %bb.4: # %_Z6cpuAddPiS_S_.exit
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 32(%rsp,%rbx,4), %edx
movl (%rsp,%rbx,4), %ecx
movl 64(%rsp,%rbx,4), %r8d
movl $.L.str.1, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $5, %rbx
jne .LBB1_5
# %bb.6:
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "The sum of %d element is %d + %d = %d\n"
.size .L.str.1, 39
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Vector addition on CPU"
.size .Lstr, 23
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0015501e_00000000-6_06_vector_addition_cpu.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6cpuAddPiS_S_
.type _Z6cpuAddPiS_S_, @function
_Z6cpuAddPiS_S_:
.LFB3669:
.cfi_startproc
endbr64
movl $0, %eax
.L4:
movl (%rsi,%rax), %ecx
addl (%rdi,%rax), %ecx
movl %ecx, (%rdx,%rax)
addq $4, %rax
cmpq $20, %rax
jne .L4
ret
.cfi_endproc
.LFE3669:
.size _Z6cpuAddPiS_S_, .-_Z6cpuAddPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Vector addition on CPU\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "The sum of %d element is %d + %d = %d\n"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $104, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $0, (%rsp)
movl $0, 32(%rsp)
movl $2, 4(%rsp)
movl $1, 36(%rsp)
movl $8, 8(%rsp)
movl $2, 40(%rsp)
movl $18, 12(%rsp)
movl $3, 44(%rsp)
movl $32, 16(%rsp)
movl $4, 48(%rsp)
leaq 64(%rsp), %rdx
leaq 32(%rsp), %rsi
movq %rsp, %rdi
call _Z6cpuAddPiS_S_
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC1(%rip), %rbp
.L7:
movl (%rsp,%rbx,4), %ecx
movl 64(%rsp,%rbx,4), %r9d
movl 32(%rsp,%rbx,4), %r8d
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $5, %rbx
jne .L7
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L11
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "06_vector_addition_cpu.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z6cpuAddPiS_S_ # -- Begin function _Z6cpuAddPiS_S_
.p2align 4, 0x90
.type _Z6cpuAddPiS_S_,@function
_Z6cpuAddPiS_S_: # @_Z6cpuAddPiS_S_
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl (%rsi,%rax,4), %ecx
addl (%rdi,%rax,4), %ecx
movl %ecx, (%rdx,%rax,4)
incq %rax
cmpq $5, %rax
jne .LBB0_1
# %bb.2:
retq
.Lfunc_end0:
.size _Z6cpuAddPiS_S_, .Lfunc_end0-_Z6cpuAddPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $96, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, %ecx
imull %eax, %ecx
addl %ecx, %ecx
movl %ecx, 32(%rsp,%rax,4)
movl %eax, (%rsp,%rax,4)
incq %rax
cmpq $5, %rax
jne .LBB1_1
# %bb.2: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_3: # %.preheader
# =>This Inner Loop Header: Depth=1
movl (%rsp,%rax,4), %ecx
addl 32(%rsp,%rax,4), %ecx
movl %ecx, 64(%rsp,%rax,4)
incq %rax
cmpq $5, %rax
jne .LBB1_3
# %bb.4: # %_Z6cpuAddPiS_S_.exit
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 32(%rsp,%rbx,4), %edx
movl (%rsp,%rbx,4), %ecx
movl 64(%rsp,%rbx,4), %r8d
movl $.L.str.1, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $5, %rbx
jne .LBB1_5
# %bb.6:
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "The sum of %d element is %d + %d = %d\n"
.size .L.str.1, 39
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Vector addition on CPU"
.size .Lstr, 23
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cstdio>
#include <iostream>
#include <limits>
#include <string>
using namespace std;
#define CSC(call) do { cudaError_t res = call; if (res != cudaSuccess) { fprintf(stderr, "CUDA Error in %s:%d: %s\n", __FILE__, __LINE__, cudaGetErrorString(res)); exit(0); } } while (0)
typedef long long ll;
const int BLOCK_SIZE = 512; // must be power of 2
const int GRID_SIZE = 32768;
const ll INF = numeric_limits<ll>::max();
__device__ void swap(ll *a, ll *b) {
ll tmp = *a;
*a = *b;
*b = tmp;
}
__global__ void oddEvenBlockSort(ll *arr, int len) {
int arrOffset = blockIdx.x * BLOCK_SIZE;
if (arrOffset >= len) {
return;
}
__shared__ ll block[BLOCK_SIZE];
int idx = threadIdx.x;
int sortIndx = 2 * idx;
for (int i = 0; i < 2; i++) {
block[sortIndx + i] = arr[arrOffset + sortIndx + i];
}
for (int k = 0; k < BLOCK_SIZE / 2; k++) {
__syncthreads();
if (sortIndx + 1 < BLOCK_SIZE) {
if (block[sortIndx] > block[sortIndx + 1]) {
swap(block + sortIndx, block + sortIndx + 1);
}
}
__syncthreads();
if (sortIndx + 2 < BLOCK_SIZE) {
if (block[sortIndx + 1] > block[sortIndx + 2]) {
swap(block + sortIndx + 1, block + sortIndx + 2);
}
}
}
__syncthreads();
for (int i = 0; i < 2; i++) {
arr[arrOffset + sortIndx + i] = block[sortIndx + i];
}
}
__global__ void bitonicMerge(ll *arr, int len, bool oddPhase) {
int arrOffset = blockIdx.x * BLOCK_SIZE * 2;
if (oddPhase) {
arrOffset += BLOCK_SIZE;
}
if (arrOffset + BLOCK_SIZE * 2 > len) {
return;
}
__shared__ ll block[BLOCK_SIZE * 2];
int idx = threadIdx.x;
int sortIndx = 2 * idx;
for (int i = 0; i < 2; i++) {
block[sortIndx + i] = arr[arrOffset + sortIndx + i];
}
__syncthreads();
if (idx < BLOCK_SIZE && block[idx] > block[BLOCK_SIZE * 2 - idx - 1]) {
swap(block + idx, block + BLOCK_SIZE * 2 - idx - 1);
}
int tmpIdx;
int step = BLOCK_SIZE / 2;
while (step != 0) {
__syncthreads();
if ((idx / step) % 2 == 0) {
tmpIdx = idx;
}
else {
tmpIdx = idx - step + BLOCK_SIZE;
}
if (block[tmpIdx] > block[tmpIdx + step]) {
swap(block + tmpIdx, block + tmpIdx + step);
}
step /= 2;
}
__syncthreads();
for (int i = 0; i < 2; i++) {
arr[arrOffset + sortIndx + i] = block[sortIndx + i];
}
}
int main() {
ios_base::sync_with_stdio(false);
int n;
fread(&n, sizeof(int), 1, stdin);
int len = n;
if (n % BLOCK_SIZE != 0) {
len += BLOCK_SIZE - n % BLOCK_SIZE;
}
ll *arr = new ll[len];
int elem;
for (int i = 0; i < n; i++) {
fread(&elem, sizeof(int), 1, stdin);
arr[i] = elem;
}
for (int i = n; i < len; i++) {
arr[i] = INF;
}
ll *devArr;
CSC(cudaMalloc(&devArr, sizeof(ll) * len));
CSC(cudaMemcpy(devArr, arr, sizeof(ll) * len, cudaMemcpyHostToDevice));
oddEvenBlockSort<<<GRID_SIZE, BLOCK_SIZE / 2>>>(devArr, len);
CSC(cudaGetLastError());
if (len > BLOCK_SIZE) {
for (int step = 0; step < len / BLOCK_SIZE; step++) {
bitonicMerge<<<GRID_SIZE, BLOCK_SIZE>>>(devArr, len, step & 1);
CSC(cudaGetLastError());
}
}
CSC(cudaMemcpy(arr, devArr, sizeof(ll) * len, cudaMemcpyDeviceToHost));
CSC(cudaFree(devArr));
for (int i = 0; i < n; i++) {
elem = (int)arr[i];
fwrite(&elem, sizeof(int), 1, stdout);
}
delete[] arr;
return 0;
} | .file "tmpxft_00101b55_00000000-6_lab_5.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4swapPxS_
.type _Z4swapPxS_, @function
_Z4swapPxS_:
.LFB3669:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z4swapPxS_, .-_Z4swapPxS_
.globl _Z37__device_stub__Z16oddEvenBlockSortPxiPxi
.type _Z37__device_stub__Z16oddEvenBlockSortPxiPxi, @function
_Z37__device_stub__Z16oddEvenBlockSortPxiPxi:
.LFB3695:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16oddEvenBlockSortPxi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z37__device_stub__Z16oddEvenBlockSortPxiPxi, .-_Z37__device_stub__Z16oddEvenBlockSortPxiPxi
.globl _Z16oddEvenBlockSortPxi
.type _Z16oddEvenBlockSortPxi, @function
_Z16oddEvenBlockSortPxi:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z16oddEvenBlockSortPxiPxi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z16oddEvenBlockSortPxi, .-_Z16oddEvenBlockSortPxi
.globl _Z34__device_stub__Z12bitonicMergePxibPxib
.type _Z34__device_stub__Z12bitonicMergePxibPxib, @function
_Z34__device_stub__Z12bitonicMergePxibPxib:
.LFB3697:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movb %dl, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12bitonicMergePxib(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z34__device_stub__Z12bitonicMergePxibPxib, .-_Z34__device_stub__Z12bitonicMergePxibPxib
.globl _Z12bitonicMergePxib
.type _Z12bitonicMergePxib, @function
_Z12bitonicMergePxib:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movzbl %dl, %edx
call _Z34__device_stub__Z12bitonicMergePxibPxib
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z12bitonicMergePxib, .-_Z12bitonicMergePxib
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/kri-k/GPGPU_CUDA/master/lab5/lab_5.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "CUDA Error in %s:%d: %s\n"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $0, %edi
call _ZNSt8ios_base15sync_with_stdioEb@PLT
movq %rsp, %rdi
movq stdin(%rip), %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
call __fread_chk@PLT
movl (%rsp), %r12d
testl $511, %r12d
je .L22
movl $512, %ecx
movl %r12d, %eax
cltd
idivl %ecx
subl %edx, %ecx
addl %ecx, %r12d
.L22:
movslq %r12d, %r13
movq %r13, %rax
shrq $60, %rax
jne .L23
salq $3, %r13
movq %r13, %rdi
call _Znam@PLT
movq %rax, %rbp
movl (%rsp), %edx
movl $0, %ebx
leaq 4(%rsp), %r14
testl %edx, %edx
jle .L25
.L24:
movq stdin(%rip), %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
movq %r14, %rdi
call __fread_chk@PLT
movslq 4(%rsp), %rax
movq %rax, 0(%rbp,%rbx,8)
movl (%rsp), %edx
addq $1, %rbx
cmpl %ebx, %edx
jg .L24
.L25:
cmpl %edx, %r12d
jle .L27
movslq %edx, %rsi
leaq 0(%rbp,%rsi,8), %rax
movl %r12d, %ecx
subl %edx, %ecx
leaq (%rcx,%rsi), %rdx
leaq 0(%rbp,%rdx,8), %rcx
movabsq $9223372036854775807, %rdx
.L28:
movq %rdx, (%rax)
addq $8, %rax
cmpq %rcx, %rax
jne .L28
.L27:
leaq 8(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
testl %eax, %eax
je .L29
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $136, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L23:
movq 40(%rsp), %rax
subq %fs:40, %rax
je .L26
call __stack_chk_fail@PLT
.L26:
call __cxa_throw_bad_array_new_length@PLT
.L29:
movl $1, %ecx
movq %r13, %rdx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
je .L30
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $137, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L30:
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $32768, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L49
.L31:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L50
cmpl $512, %r12d
jle .L33
movl $512, %ecx
movl %r12d, %eax
cltd
idivl %ecx
movl %eax, %r14d
movl $0, %ebx
jmp .L36
.L49:
movl %r12d, %esi
movq 8(%rsp), %rdi
call _Z37__device_stub__Z16oddEvenBlockSortPxiPxi
jmp .L31
.L50:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $140, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L34:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L51
addl $1, %ebx
cmpl %ebx, %r14d
je .L33
.L36:
movl $512, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $32768, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L34
movl %ebx, %edx
andl $1, %edx
movl %r12d, %esi
movq 8(%rsp), %rdi
call _Z34__device_stub__Z12bitonicMergePxibPxib
jmp .L34
.L51:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $145, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L33:
movl $2, %ecx
movq %r13, %rdx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
je .L37
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $149, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L37:
movq 8(%rsp), %rdi
call cudaFree@PLT
movl $0, %ebx
leaq 4(%rsp), %r12
testl %eax, %eax
je .L38
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $150, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L39:
movq 0(%rbp,%rbx,8), %rax
movl %eax, 4(%rsp)
movq stdout(%rip), %rcx
movl $1, %edx
movl $4, %esi
movq %r12, %rdi
call fwrite@PLT
addq $1, %rbx
.L38:
cmpl %ebx, (%rsp)
jg .L39
movq %rbp, %rdi
call _ZdaPv@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L52
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z12bitonicMergePxib"
.LC3:
.string "_Z16oddEvenBlockSortPxi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3700:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z12bitonicMergePxib(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z16oddEvenBlockSortPxi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cstdio>
#include <iostream>
#include <limits>
#include <string>
using namespace std;
#define CSC(call) do { cudaError_t res = call; if (res != cudaSuccess) { fprintf(stderr, "CUDA Error in %s:%d: %s\n", __FILE__, __LINE__, cudaGetErrorString(res)); exit(0); } } while (0)
typedef long long ll;
const int BLOCK_SIZE = 512; // must be power of 2
const int GRID_SIZE = 32768;
const ll INF = numeric_limits<ll>::max();
__device__ void swap(ll *a, ll *b) {
ll tmp = *a;
*a = *b;
*b = tmp;
}
__global__ void oddEvenBlockSort(ll *arr, int len) {
int arrOffset = blockIdx.x * BLOCK_SIZE;
if (arrOffset >= len) {
return;
}
__shared__ ll block[BLOCK_SIZE];
int idx = threadIdx.x;
int sortIndx = 2 * idx;
for (int i = 0; i < 2; i++) {
block[sortIndx + i] = arr[arrOffset + sortIndx + i];
}
for (int k = 0; k < BLOCK_SIZE / 2; k++) {
__syncthreads();
if (sortIndx + 1 < BLOCK_SIZE) {
if (block[sortIndx] > block[sortIndx + 1]) {
swap(block + sortIndx, block + sortIndx + 1);
}
}
__syncthreads();
if (sortIndx + 2 < BLOCK_SIZE) {
if (block[sortIndx + 1] > block[sortIndx + 2]) {
swap(block + sortIndx + 1, block + sortIndx + 2);
}
}
}
__syncthreads();
for (int i = 0; i < 2; i++) {
arr[arrOffset + sortIndx + i] = block[sortIndx + i];
}
}
__global__ void bitonicMerge(ll *arr, int len, bool oddPhase) {
int arrOffset = blockIdx.x * BLOCK_SIZE * 2;
if (oddPhase) {
arrOffset += BLOCK_SIZE;
}
if (arrOffset + BLOCK_SIZE * 2 > len) {
return;
}
__shared__ ll block[BLOCK_SIZE * 2];
int idx = threadIdx.x;
int sortIndx = 2 * idx;
for (int i = 0; i < 2; i++) {
block[sortIndx + i] = arr[arrOffset + sortIndx + i];
}
__syncthreads();
if (idx < BLOCK_SIZE && block[idx] > block[BLOCK_SIZE * 2 - idx - 1]) {
swap(block + idx, block + BLOCK_SIZE * 2 - idx - 1);
}
int tmpIdx;
int step = BLOCK_SIZE / 2;
while (step != 0) {
__syncthreads();
if ((idx / step) % 2 == 0) {
tmpIdx = idx;
}
else {
tmpIdx = idx - step + BLOCK_SIZE;
}
if (block[tmpIdx] > block[tmpIdx + step]) {
swap(block + tmpIdx, block + tmpIdx + step);
}
step /= 2;
}
__syncthreads();
for (int i = 0; i < 2; i++) {
arr[arrOffset + sortIndx + i] = block[sortIndx + i];
}
}
int main() {
ios_base::sync_with_stdio(false);
int n;
fread(&n, sizeof(int), 1, stdin);
int len = n;
if (n % BLOCK_SIZE != 0) {
len += BLOCK_SIZE - n % BLOCK_SIZE;
}
ll *arr = new ll[len];
int elem;
for (int i = 0; i < n; i++) {
fread(&elem, sizeof(int), 1, stdin);
arr[i] = elem;
}
for (int i = n; i < len; i++) {
arr[i] = INF;
}
ll *devArr;
CSC(cudaMalloc(&devArr, sizeof(ll) * len));
CSC(cudaMemcpy(devArr, arr, sizeof(ll) * len, cudaMemcpyHostToDevice));
oddEvenBlockSort<<<GRID_SIZE, BLOCK_SIZE / 2>>>(devArr, len);
CSC(cudaGetLastError());
if (len > BLOCK_SIZE) {
for (int step = 0; step < len / BLOCK_SIZE; step++) {
bitonicMerge<<<GRID_SIZE, BLOCK_SIZE>>>(devArr, len, step & 1);
CSC(cudaGetLastError());
}
}
CSC(cudaMemcpy(arr, devArr, sizeof(ll) * len, cudaMemcpyDeviceToHost));
CSC(cudaFree(devArr));
for (int i = 0; i < n; i++) {
elem = (int)arr[i];
fwrite(&elem, sizeof(int), 1, stdout);
}
delete[] arr;
return 0;
} | #include <hip/hip_runtime.h>
#include <cstdio>
#include <iostream>
#include <limits>
#include <string>
using namespace std;
#define CSC(call) do { hipError_t res = call; if (res != hipSuccess) { fprintf(stderr, "CUDA Error in %s:%d: %s\n", __FILE__, __LINE__, hipGetErrorString(res)); exit(0); } } while (0)
typedef long long ll;
const int BLOCK_SIZE = 512; // must be power of 2
const int GRID_SIZE = 32768;
const ll INF = numeric_limits<ll>::max();
__device__ void swap(ll *a, ll *b) {
ll tmp = *a;
*a = *b;
*b = tmp;
}
__global__ void oddEvenBlockSort(ll *arr, int len) {
int arrOffset = blockIdx.x * BLOCK_SIZE;
if (arrOffset >= len) {
return;
}
__shared__ ll block[BLOCK_SIZE];
int idx = threadIdx.x;
int sortIndx = 2 * idx;
for (int i = 0; i < 2; i++) {
block[sortIndx + i] = arr[arrOffset + sortIndx + i];
}
for (int k = 0; k < BLOCK_SIZE / 2; k++) {
__syncthreads();
if (sortIndx + 1 < BLOCK_SIZE) {
if (block[sortIndx] > block[sortIndx + 1]) {
swap(block + sortIndx, block + sortIndx + 1);
}
}
__syncthreads();
if (sortIndx + 2 < BLOCK_SIZE) {
if (block[sortIndx + 1] > block[sortIndx + 2]) {
swap(block + sortIndx + 1, block + sortIndx + 2);
}
}
}
__syncthreads();
for (int i = 0; i < 2; i++) {
arr[arrOffset + sortIndx + i] = block[sortIndx + i];
}
}
__global__ void bitonicMerge(ll *arr, int len, bool oddPhase) {
int arrOffset = blockIdx.x * BLOCK_SIZE * 2;
if (oddPhase) {
arrOffset += BLOCK_SIZE;
}
if (arrOffset + BLOCK_SIZE * 2 > len) {
return;
}
__shared__ ll block[BLOCK_SIZE * 2];
int idx = threadIdx.x;
int sortIndx = 2 * idx;
for (int i = 0; i < 2; i++) {
block[sortIndx + i] = arr[arrOffset + sortIndx + i];
}
__syncthreads();
if (idx < BLOCK_SIZE && block[idx] > block[BLOCK_SIZE * 2 - idx - 1]) {
swap(block + idx, block + BLOCK_SIZE * 2 - idx - 1);
}
int tmpIdx;
int step = BLOCK_SIZE / 2;
while (step != 0) {
__syncthreads();
if ((idx / step) % 2 == 0) {
tmpIdx = idx;
}
else {
tmpIdx = idx - step + BLOCK_SIZE;
}
if (block[tmpIdx] > block[tmpIdx + step]) {
swap(block + tmpIdx, block + tmpIdx + step);
}
step /= 2;
}
__syncthreads();
for (int i = 0; i < 2; i++) {
arr[arrOffset + sortIndx + i] = block[sortIndx + i];
}
}
int main() {
ios_base::sync_with_stdio(false);
int n;
fread(&n, sizeof(int), 1, stdin);
int len = n;
if (n % BLOCK_SIZE != 0) {
len += BLOCK_SIZE - n % BLOCK_SIZE;
}
ll *arr = new ll[len];
int elem;
for (int i = 0; i < n; i++) {
fread(&elem, sizeof(int), 1, stdin);
arr[i] = elem;
}
for (int i = n; i < len; i++) {
arr[i] = INF;
}
ll *devArr;
CSC(hipMalloc(&devArr, sizeof(ll) * len));
CSC(hipMemcpy(devArr, arr, sizeof(ll) * len, hipMemcpyHostToDevice));
oddEvenBlockSort<<<GRID_SIZE, BLOCK_SIZE / 2>>>(devArr, len);
CSC(hipGetLastError());
if (len > BLOCK_SIZE) {
for (int step = 0; step < len / BLOCK_SIZE; step++) {
bitonicMerge<<<GRID_SIZE, BLOCK_SIZE>>>(devArr, len, step & 1);
CSC(hipGetLastError());
}
}
CSC(hipMemcpy(arr, devArr, sizeof(ll) * len, hipMemcpyDeviceToHost));
CSC(hipFree(devArr));
for (int i = 0; i < n; i++) {
elem = (int)arr[i];
fwrite(&elem, sizeof(int), 1, stdout);
}
delete[] arr;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
#include <iostream>
#include <limits>
#include <string>
using namespace std;
#define CSC(call) do { hipError_t res = call; if (res != hipSuccess) { fprintf(stderr, "CUDA Error in %s:%d: %s\n", __FILE__, __LINE__, hipGetErrorString(res)); exit(0); } } while (0)
typedef long long ll;
const int BLOCK_SIZE = 512; // must be power of 2
const int GRID_SIZE = 32768;
const ll INF = numeric_limits<ll>::max();
__device__ void swap(ll *a, ll *b) {
ll tmp = *a;
*a = *b;
*b = tmp;
}
__global__ void oddEvenBlockSort(ll *arr, int len) {
int arrOffset = blockIdx.x * BLOCK_SIZE;
if (arrOffset >= len) {
return;
}
__shared__ ll block[BLOCK_SIZE];
int idx = threadIdx.x;
int sortIndx = 2 * idx;
for (int i = 0; i < 2; i++) {
block[sortIndx + i] = arr[arrOffset + sortIndx + i];
}
for (int k = 0; k < BLOCK_SIZE / 2; k++) {
__syncthreads();
if (sortIndx + 1 < BLOCK_SIZE) {
if (block[sortIndx] > block[sortIndx + 1]) {
swap(block + sortIndx, block + sortIndx + 1);
}
}
__syncthreads();
if (sortIndx + 2 < BLOCK_SIZE) {
if (block[sortIndx + 1] > block[sortIndx + 2]) {
swap(block + sortIndx + 1, block + sortIndx + 2);
}
}
}
__syncthreads();
for (int i = 0; i < 2; i++) {
arr[arrOffset + sortIndx + i] = block[sortIndx + i];
}
}
__global__ void bitonicMerge(ll *arr, int len, bool oddPhase) {
int arrOffset = blockIdx.x * BLOCK_SIZE * 2;
if (oddPhase) {
arrOffset += BLOCK_SIZE;
}
if (arrOffset + BLOCK_SIZE * 2 > len) {
return;
}
__shared__ ll block[BLOCK_SIZE * 2];
int idx = threadIdx.x;
int sortIndx = 2 * idx;
for (int i = 0; i < 2; i++) {
block[sortIndx + i] = arr[arrOffset + sortIndx + i];
}
__syncthreads();
if (idx < BLOCK_SIZE && block[idx] > block[BLOCK_SIZE * 2 - idx - 1]) {
swap(block + idx, block + BLOCK_SIZE * 2 - idx - 1);
}
int tmpIdx;
int step = BLOCK_SIZE / 2;
while (step != 0) {
__syncthreads();
if ((idx / step) % 2 == 0) {
tmpIdx = idx;
}
else {
tmpIdx = idx - step + BLOCK_SIZE;
}
if (block[tmpIdx] > block[tmpIdx + step]) {
swap(block + tmpIdx, block + tmpIdx + step);
}
step /= 2;
}
__syncthreads();
for (int i = 0; i < 2; i++) {
arr[arrOffset + sortIndx + i] = block[sortIndx + i];
}
}
int main() {
ios_base::sync_with_stdio(false);
int n;
fread(&n, sizeof(int), 1, stdin);
int len = n;
if (n % BLOCK_SIZE != 0) {
len += BLOCK_SIZE - n % BLOCK_SIZE;
}
ll *arr = new ll[len];
int elem;
for (int i = 0; i < n; i++) {
fread(&elem, sizeof(int), 1, stdin);
arr[i] = elem;
}
for (int i = n; i < len; i++) {
arr[i] = INF;
}
ll *devArr;
CSC(hipMalloc(&devArr, sizeof(ll) * len));
CSC(hipMemcpy(devArr, arr, sizeof(ll) * len, hipMemcpyHostToDevice));
oddEvenBlockSort<<<GRID_SIZE, BLOCK_SIZE / 2>>>(devArr, len);
CSC(hipGetLastError());
if (len > BLOCK_SIZE) {
for (int step = 0; step < len / BLOCK_SIZE; step++) {
bitonicMerge<<<GRID_SIZE, BLOCK_SIZE>>>(devArr, len, step & 1);
CSC(hipGetLastError());
}
}
CSC(hipMemcpy(arr, devArr, sizeof(ll) * len, hipMemcpyDeviceToHost));
CSC(hipFree(devArr));
for (int i = 0; i < n; i++) {
elem = (int)arr[i];
fwrite(&elem, sizeof(int), 1, stdout);
}
delete[] arr;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16oddEvenBlockSortPxi
.globl _Z16oddEvenBlockSortPxi
.p2align 8
.type _Z16oddEvenBlockSortPxi,@function
_Z16oddEvenBlockSortPxi:
s_load_b32 s2, s[0:1], 0x8
s_lshl_b32 s4, s15, 9
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s4, s2
s_cbranch_scc1 .LBB0_13
v_lshlrev_b32_e32 v5, 1, v0
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v6, 4, v0
s_mov_b32 s0, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, s4, v5
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
.LBB0_2:
global_load_b64 v[7:8], v[3:4], off
v_add_co_u32 v3, vcc_lo, v3, 8
v_add_nc_u32_e32 v9, s0, v6
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_add_i32 s0, s0, 8
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s0, 8
s_waitcnt vmcnt(0)
ds_store_b64 v9, v[7:8]
s_cbranch_scc0 .LBB0_2
v_or_b32_e32 v4, 1, v5
v_lshlrev_b32_e32 v3, 3, v5
v_cmp_gt_u32_e32 vcc_lo, 0xff, v0
s_movk_i32 s4, 0x100
s_delay_alu instid0(VALU_DEP_3)
v_cmp_gt_u32_e64 s0, 0x200, v4
v_lshlrev_b32_e32 v4, 3, v4
v_add_nc_u32_e32 v5, 16, v3
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_5
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s5
s_add_i32 s4, s4, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s4, 0
s_cbranch_scc1 .LBB0_11
.LBB0_5:
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s5, s0
s_cbranch_execz .LBB0_8
ds_load_b64 v[6:7], v3
ds_load_b64 v[8:9], v4
s_waitcnt lgkmcnt(0)
v_cmp_gt_i64_e64 s1, v[6:7], v[8:9]
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB0_8
ds_load_2addr_b64 v[6:9], v3 offset1:1
s_waitcnt lgkmcnt(0)
ds_store_2addr_b64 v3, v[8:9], v[6:7] offset1:1
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s5, vcc_lo
s_cbranch_execz .LBB0_4
ds_load_b64 v[6:7], v4
ds_load_b64 v[8:9], v5
s_waitcnt lgkmcnt(0)
v_cmp_gt_i64_e64 s1, v[6:7], v[8:9]
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB0_4
ds_load_2addr_b64 v[6:9], v3 offset0:1 offset1:2
s_waitcnt lgkmcnt(0)
ds_store_2addr_b64 v3, v[8:9], v[6:7] offset0:1 offset1:2
s_branch .LBB0_4
.LBB0_11:
s_set_inst_prefetch_distance 0x2
v_lshlrev_b64 v[3:4], 3, v[1:2]
v_lshlrev_b32_e32 v2, 4, v0
s_mov_b32 s0, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_add_co_u32 v0, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v4, vcc_lo
.LBB0_12:
v_add_nc_u32_e32 v3, s0, v2
s_add_i32 s0, s0, 8
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s0, 8
ds_load_b64 v[3:4], v3
s_waitcnt lgkmcnt(0)
global_store_b64 v[0:1], v[3:4], off
v_add_co_u32 v0, vcc_lo, v0, 8
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_cbranch_scc1 .LBB0_12
.LBB0_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16oddEvenBlockSortPxi
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16oddEvenBlockSortPxi, .Lfunc_end0-_Z16oddEvenBlockSortPxi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12bitonicMergePxib
.globl _Z12bitonicMergePxib
.p2align 8
.type _Z12bitonicMergePxib,@function
_Z12bitonicMergePxib:
s_load_b64 s[4:5], s[0:1], 0x8
s_lshl_b32 s2, s15, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, 1, s5
s_or_b32 s5, s2, 0x200
s_cmp_eq_u32 s3, 1
s_cselect_b32 s2, s5, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s2, 0x400
s_cmp_gt_i32 s3, s4
s_cbranch_scc1 .LBB1_12
v_lshlrev_b32_e32 v1, 1, v0
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v5, 4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, s2, v1
s_mov_b32 s2, 0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
.LBB1_2:
global_load_b64 v[6:7], v[3:4], off
v_add_co_u32 v3, vcc_lo, v3, 8
v_add_nc_u32_e32 v8, s2, v5
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_add_i32 s2, s2, 8
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s2, 8
s_waitcnt vmcnt(0)
ds_store_b64 v8, v[6:7]
s_cbranch_scc0 .LBB1_2
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 0x200, v0
s_cbranch_execz .LBB1_6
v_xor_b32_e32 v4, 0x3ff, v0
v_lshlrev_b32_e32 v3, 3, v0
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b32_e32 v6, 3, v4
ds_load_b64 v[4:5], v3
ds_load_b64 v[6:7], v6
s_waitcnt lgkmcnt(0)
v_cmp_gt_i64_e32 vcc_lo, v[4:5], v[6:7]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB1_6
v_xor_b32_e32 v8, 0x1ff8, v3
ds_load_b64 v[4:5], v8
ds_load_b64 v[6:7], v3
s_waitcnt lgkmcnt(1)
ds_store_b64 v3, v[4:5]
s_waitcnt lgkmcnt(1)
ds_store_b64 v8, v[6:7]
.LBB1_6:
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v3, 0x200, v0
s_movk_i32 s2, 0x100
s_branch .LBB1_8
.LBB1_7:
s_or_b32 exec_lo, exec_lo, s3
s_lshr_b32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s3, s2, s3
s_add_i32 s2, s2, 1
s_ashr_i32 s3, s3, 1
s_cmp_gt_u32 s2, 2
s_mov_b32 s2, s3
s_cbranch_scc0 .LBB1_10
.LBB1_8:
s_ashr_i32 s3, s2, 31
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s2, s3
s_barrier
s_xor_b32 s4, s4, s3
buffer_gl0_inv
v_cvt_f32_u32_e32 v4, s4
s_sub_i32 s5, 0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, 0x4f7ffffe, v4
v_cvt_u32_f32_e32 v4, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, s5, v4
v_mul_hi_u32 v5, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v4, v5
v_mul_hi_u32 v4, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v5, v4, s4
v_add_nc_u32_e32 v6, 1, v4
v_sub_nc_u32_e32 v5, v0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v7, s4, v5
v_cmp_le_u32_e32 vcc_lo, s4, v5
v_dual_cndmask_b32 v4, v4, v6 :: v_dual_cndmask_b32 v5, v5, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, 1, v4
v_cmp_le_u32_e32 vcc_lo, s4, v5
v_subrev_nc_u32_e32 v5, s2, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, v4, v6, vcc_lo
v_xor_b32_e32 v4, s3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v4, s3, v4
s_mov_b32 s3, exec_lo
v_and_b32_e32 v4, 1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e32 vcc_lo, 0, v4
v_cndmask_b32_e32 v5, v5, v0, vcc_lo
v_lshlrev_b32_e32 v4, 3, v5
v_add_lshl_u32 v7, v5, s2, 3
ds_load_b64 v[5:6], v4
ds_load_b64 v[7:8], v7
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i64_e64 v[5:6], v[7:8]
s_cbranch_execz .LBB1_7
v_lshl_add_u32 v9, s2, 3, v4
ds_load_b64 v[5:6], v9
ds_load_b64 v[7:8], v4
s_waitcnt lgkmcnt(1)
ds_store_b64 v4, v[5:6]
s_waitcnt lgkmcnt(1)
ds_store_b64 v9, v[7:8]
s_branch .LBB1_7
.LBB1_10:
v_lshlrev_b64 v[3:4], 3, v[1:2]
v_lshlrev_b32_e32 v2, 4, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_add_co_u32 v0, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v4, vcc_lo
s_mov_b32 s0, 0
.LBB1_11:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v3, s0, v2
s_add_i32 s0, s0, 8
s_cmp_eq_u32 s0, 8
ds_load_b64 v[3:4], v3
s_waitcnt lgkmcnt(0)
global_store_b64 v[0:1], v[3:4], off
v_add_co_u32 v0, vcc_lo, v0, 8
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_cbranch_scc1 .LBB1_11
.LBB1_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12bitonicMergePxib
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z12bitonicMergePxib, .Lfunc_end1-_Z12bitonicMergePxib
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16oddEvenBlockSortPxi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16oddEvenBlockSortPxi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 1
.value_kind: by_value
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12bitonicMergePxib
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12bitonicMergePxib.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
#include <iostream>
#include <limits>
#include <string>
using namespace std;
#define CSC(call) do { hipError_t res = call; if (res != hipSuccess) { fprintf(stderr, "CUDA Error in %s:%d: %s\n", __FILE__, __LINE__, hipGetErrorString(res)); exit(0); } } while (0)
typedef long long ll;
const int BLOCK_SIZE = 512; // must be power of 2
const int GRID_SIZE = 32768;
const ll INF = numeric_limits<ll>::max();
__device__ void swap(ll *a, ll *b) {
ll tmp = *a;
*a = *b;
*b = tmp;
}
__global__ void oddEvenBlockSort(ll *arr, int len) {
int arrOffset = blockIdx.x * BLOCK_SIZE;
if (arrOffset >= len) {
return;
}
__shared__ ll block[BLOCK_SIZE];
int idx = threadIdx.x;
int sortIndx = 2 * idx;
for (int i = 0; i < 2; i++) {
block[sortIndx + i] = arr[arrOffset + sortIndx + i];
}
for (int k = 0; k < BLOCK_SIZE / 2; k++) {
__syncthreads();
if (sortIndx + 1 < BLOCK_SIZE) {
if (block[sortIndx] > block[sortIndx + 1]) {
swap(block + sortIndx, block + sortIndx + 1);
}
}
__syncthreads();
if (sortIndx + 2 < BLOCK_SIZE) {
if (block[sortIndx + 1] > block[sortIndx + 2]) {
swap(block + sortIndx + 1, block + sortIndx + 2);
}
}
}
__syncthreads();
for (int i = 0; i < 2; i++) {
arr[arrOffset + sortIndx + i] = block[sortIndx + i];
}
}
__global__ void bitonicMerge(ll *arr, int len, bool oddPhase) {
int arrOffset = blockIdx.x * BLOCK_SIZE * 2;
if (oddPhase) {
arrOffset += BLOCK_SIZE;
}
if (arrOffset + BLOCK_SIZE * 2 > len) {
return;
}
__shared__ ll block[BLOCK_SIZE * 2];
int idx = threadIdx.x;
int sortIndx = 2 * idx;
for (int i = 0; i < 2; i++) {
block[sortIndx + i] = arr[arrOffset + sortIndx + i];
}
__syncthreads();
if (idx < BLOCK_SIZE && block[idx] > block[BLOCK_SIZE * 2 - idx - 1]) {
swap(block + idx, block + BLOCK_SIZE * 2 - idx - 1);
}
int tmpIdx;
int step = BLOCK_SIZE / 2;
while (step != 0) {
__syncthreads();
if ((idx / step) % 2 == 0) {
tmpIdx = idx;
}
else {
tmpIdx = idx - step + BLOCK_SIZE;
}
if (block[tmpIdx] > block[tmpIdx + step]) {
swap(block + tmpIdx, block + tmpIdx + step);
}
step /= 2;
}
__syncthreads();
for (int i = 0; i < 2; i++) {
arr[arrOffset + sortIndx + i] = block[sortIndx + i];
}
}
int main() {
ios_base::sync_with_stdio(false);
int n;
fread(&n, sizeof(int), 1, stdin);
int len = n;
if (n % BLOCK_SIZE != 0) {
len += BLOCK_SIZE - n % BLOCK_SIZE;
}
ll *arr = new ll[len];
int elem;
for (int i = 0; i < n; i++) {
fread(&elem, sizeof(int), 1, stdin);
arr[i] = elem;
}
for (int i = n; i < len; i++) {
arr[i] = INF;
}
ll *devArr;
CSC(hipMalloc(&devArr, sizeof(ll) * len));
CSC(hipMemcpy(devArr, arr, sizeof(ll) * len, hipMemcpyHostToDevice));
oddEvenBlockSort<<<GRID_SIZE, BLOCK_SIZE / 2>>>(devArr, len);
CSC(hipGetLastError());
if (len > BLOCK_SIZE) {
for (int step = 0; step < len / BLOCK_SIZE; step++) {
bitonicMerge<<<GRID_SIZE, BLOCK_SIZE>>>(devArr, len, step & 1);
CSC(hipGetLastError());
}
}
CSC(hipMemcpy(arr, devArr, sizeof(ll) * len, hipMemcpyDeviceToHost));
CSC(hipFree(devArr));
for (int i = 0; i < n; i++) {
elem = (int)arr[i];
fwrite(&elem, sizeof(int), 1, stdout);
}
delete[] arr;
return 0;
} | .text
.file "lab_5.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z31__device_stub__oddEvenBlockSortPxi # -- Begin function _Z31__device_stub__oddEvenBlockSortPxi
.p2align 4, 0x90
.type _Z31__device_stub__oddEvenBlockSortPxi,@function
_Z31__device_stub__oddEvenBlockSortPxi: # @_Z31__device_stub__oddEvenBlockSortPxi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16oddEvenBlockSortPxi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z31__device_stub__oddEvenBlockSortPxi, .Lfunc_end0-_Z31__device_stub__oddEvenBlockSortPxi
.cfi_endproc
# -- End function
.globl _Z27__device_stub__bitonicMergePxib # -- Begin function _Z27__device_stub__bitonicMergePxib
.p2align 4, 0x90
.type _Z27__device_stub__bitonicMergePxib,@function
_Z27__device_stub__bitonicMergePxib: # @_Z27__device_stub__bitonicMergePxib
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movb %dl, 3(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 3(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12bitonicMergePxib, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z27__device_stub__bitonicMergePxib, .Lfunc_end1-_Z27__device_stub__bitonicMergePxib
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %edi, %edi
callq _ZNSt8ios_base15sync_with_stdioEb
movq stdin(%rip), %rcx
leaq 84(%rsp), %rdi
movl $4, %esi
movl $1, %edx
callq fread
movslq 84(%rsp), %rbp
leal 511(%rbp), %eax
testq %rbp, %rbp
cmovnsl %ebp, %eax
andl $-512, %eax # imm = 0xFE00
leal 512(%rax), %ecx
cmpl %eax, %ebp
cmovel %ebp, %ecx
movl %ecx, 4(%rsp) # 4-byte Spill
movslq %ecx, %r15
leaq (,%r15,8), %rax
testl %r15d, %r15d
movq $-1, %rdi
movq %rax, 88(%rsp) # 8-byte Spill
cmovnsq %rax, %rdi
callq _Znam
movq %rax, %rbx
movl %ebp, %r13d
testq %rbp, %rbp
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
xorl %r12d, %r12d
leaq 8(%rsp), %r14
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq stdin(%rip), %rcx
movl $4, %esi
movl $1, %edx
movq %r14, %rdi
callq fread
movslq 8(%rsp), %rax
movq %rax, (%rbx,%r12,8)
incq %r12
cmpq %r12, %r13
jne .LBB2_2
.LBB2_3: # %.preheader81
cmpl 4(%rsp), %ebp # 4-byte Folded Reload
jge .LBB2_6
# %bb.4: # %.lr.ph84.preheader
movabsq $9223372036854775807, %rax # imm = 0x7FFFFFFFFFFFFFFF
movq %rbp, %rcx
.p2align 4, 0x90
.LBB2_5: # %.lr.ph84
# =>This Inner Loop Header: Depth=1
movq %rax, (%rbx,%rcx,8)
incq %rcx
cmpq %rcx, %r15
jne .LBB2_5
.LBB2_6: # %._crit_edge
leaq 16(%rsp), %rdi
movq 88(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_7
# %bb.9:
movq 16(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_10
# %bb.11:
movabsq $4295000064, %r15 # imm = 0x100008000
leaq -32512(%r15), %rdx
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_13
# %bb.12:
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl 4(%rsp), %eax # 4-byte Reload
movl %eax, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16oddEvenBlockSortPxi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_13:
movq %rbp, 128(%rsp) # 8-byte Spill
callq hipGetLastError
testl %eax, %eax
jne .LBB2_14
# %bb.15:
cmpl $513, 4(%rsp) # 4-byte Folded Reload
# imm = 0x201
jl .LBB2_22
# %bb.16: # %.preheader80
movl 4(%rsp), %ebp # 4-byte Reload
shrl $9, %ebp
xorl %r14d, %r14d
leaq -32256(%r15), %r12
.p2align 4, 0x90
.LBB2_18: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_20
# %bb.19: # in Loop: Header=BB2_18 Depth=1
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl 4(%rsp), %eax # 4-byte Reload
movl %eax, 12(%rsp)
movl %r14d, %eax
andb $1, %al
movb %al, 3(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 3(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z12bitonicMergePxib, %edi
leaq 96(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_20: # in Loop: Header=BB2_18 Depth=1
callq hipGetLastError
testl %eax, %eax
jne .LBB2_21
# %bb.17: # in Loop: Header=BB2_18 Depth=1
incl %r14d
cmpl %r14d, %ebp
jne .LBB2_18
.LBB2_22: # %.loopexit
movq 16(%rsp), %rsi
movq %rbx, %rdi
movq 88(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_23
# %bb.24:
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
movq 128(%rsp), %rcx # 8-byte Reload
jne .LBB2_29
# %bb.25: # %.preheader
testl %ecx, %ecx
jle .LBB2_28
# %bb.26: # %.lr.ph88.preheader
xorl %r15d, %r15d
leaq 8(%rsp), %r14
.p2align 4, 0x90
.LBB2_27: # %.lr.ph88
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,8), %eax
movl %eax, 8(%rsp)
movq stdout(%rip), %rcx
movl $4, %esi
movl $1, %edx
movq %r14, %rdi
callq fwrite
incq %r15
cmpq %r15, %r13
jne .LBB2_27
.LBB2_28: # %._crit_edge89
movq %rbx, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_21:
.cfi_def_cfa_offset 192
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movq %rbx, %rdi
movl $147, %ecx
.LBB2_8:
movq %rax, %r8
xorl %eax, %eax
callq fprintf
xorl %edi, %edi
callq exit
.LBB2_7:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movq %rbx, %rdi
movl $138, %ecx
jmp .LBB2_8
.LBB2_10:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movq %rbx, %rdi
movl $139, %ecx
jmp .LBB2_8
.LBB2_14:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movq %rbx, %rdi
movl $142, %ecx
jmp .LBB2_8
.LBB2_23:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movq %rbx, %rdi
movl $151, %ecx
jmp .LBB2_8
.LBB2_29:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movq %rbx, %rdi
movl $152, %ecx
jmp .LBB2_8
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16oddEvenBlockSortPxi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12bitonicMergePxib, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16oddEvenBlockSortPxi,@object # @_Z16oddEvenBlockSortPxi
.section .rodata,"a",@progbits
.globl _Z16oddEvenBlockSortPxi
.p2align 3, 0x0
_Z16oddEvenBlockSortPxi:
.quad _Z31__device_stub__oddEvenBlockSortPxi
.size _Z16oddEvenBlockSortPxi, 8
.type _Z12bitonicMergePxib,@object # @_Z12bitonicMergePxib
.globl _Z12bitonicMergePxib
.p2align 3, 0x0
_Z12bitonicMergePxib:
.quad _Z27__device_stub__bitonicMergePxib
.size _Z12bitonicMergePxib, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA Error in %s:%d: %s\n"
.size .L.str, 25
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/kri-k/GPGPU_CUDA/master/lab5/lab_5.hip"
.size .L.str.1, 96
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16oddEvenBlockSortPxi"
.size .L__unnamed_1, 24
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12bitonicMergePxib"
.size .L__unnamed_2, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__oddEvenBlockSortPxi
.addrsig_sym _Z27__device_stub__bitonicMergePxib
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16oddEvenBlockSortPxi
.addrsig_sym _Z12bitonicMergePxib
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00101b55_00000000-6_lab_5.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4swapPxS_
.type _Z4swapPxS_, @function
_Z4swapPxS_:
.LFB3669:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z4swapPxS_, .-_Z4swapPxS_
.globl _Z37__device_stub__Z16oddEvenBlockSortPxiPxi
.type _Z37__device_stub__Z16oddEvenBlockSortPxiPxi, @function
_Z37__device_stub__Z16oddEvenBlockSortPxiPxi:
.LFB3695:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16oddEvenBlockSortPxi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z37__device_stub__Z16oddEvenBlockSortPxiPxi, .-_Z37__device_stub__Z16oddEvenBlockSortPxiPxi
.globl _Z16oddEvenBlockSortPxi
.type _Z16oddEvenBlockSortPxi, @function
_Z16oddEvenBlockSortPxi:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z16oddEvenBlockSortPxiPxi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z16oddEvenBlockSortPxi, .-_Z16oddEvenBlockSortPxi
.globl _Z34__device_stub__Z12bitonicMergePxibPxib
.type _Z34__device_stub__Z12bitonicMergePxibPxib, @function
_Z34__device_stub__Z12bitonicMergePxibPxib:
.LFB3697:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movb %dl, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12bitonicMergePxib(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z34__device_stub__Z12bitonicMergePxibPxib, .-_Z34__device_stub__Z12bitonicMergePxibPxib
.globl _Z12bitonicMergePxib
.type _Z12bitonicMergePxib, @function
_Z12bitonicMergePxib:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movzbl %dl, %edx
call _Z34__device_stub__Z12bitonicMergePxibPxib
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z12bitonicMergePxib, .-_Z12bitonicMergePxib
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/kri-k/GPGPU_CUDA/master/lab5/lab_5.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "CUDA Error in %s:%d: %s\n"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $0, %edi
call _ZNSt8ios_base15sync_with_stdioEb@PLT
movq %rsp, %rdi
movq stdin(%rip), %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
call __fread_chk@PLT
movl (%rsp), %r12d
testl $511, %r12d
je .L22
movl $512, %ecx
movl %r12d, %eax
cltd
idivl %ecx
subl %edx, %ecx
addl %ecx, %r12d
.L22:
movslq %r12d, %r13
movq %r13, %rax
shrq $60, %rax
jne .L23
salq $3, %r13
movq %r13, %rdi
call _Znam@PLT
movq %rax, %rbp
movl (%rsp), %edx
movl $0, %ebx
leaq 4(%rsp), %r14
testl %edx, %edx
jle .L25
.L24:
movq stdin(%rip), %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
movq %r14, %rdi
call __fread_chk@PLT
movslq 4(%rsp), %rax
movq %rax, 0(%rbp,%rbx,8)
movl (%rsp), %edx
addq $1, %rbx
cmpl %ebx, %edx
jg .L24
.L25:
cmpl %edx, %r12d
jle .L27
movslq %edx, %rsi
leaq 0(%rbp,%rsi,8), %rax
movl %r12d, %ecx
subl %edx, %ecx
leaq (%rcx,%rsi), %rdx
leaq 0(%rbp,%rdx,8), %rcx
movabsq $9223372036854775807, %rdx
.L28:
movq %rdx, (%rax)
addq $8, %rax
cmpq %rcx, %rax
jne .L28
.L27:
leaq 8(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
testl %eax, %eax
je .L29
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $136, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L23:
movq 40(%rsp), %rax
subq %fs:40, %rax
je .L26
call __stack_chk_fail@PLT
.L26:
call __cxa_throw_bad_array_new_length@PLT
.L29:
movl $1, %ecx
movq %r13, %rdx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
je .L30
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $137, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L30:
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $32768, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L49
.L31:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L50
cmpl $512, %r12d
jle .L33
movl $512, %ecx
movl %r12d, %eax
cltd
idivl %ecx
movl %eax, %r14d
movl $0, %ebx
jmp .L36
.L49:
movl %r12d, %esi
movq 8(%rsp), %rdi
call _Z37__device_stub__Z16oddEvenBlockSortPxiPxi
jmp .L31
.L50:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $140, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L34:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L51
addl $1, %ebx
cmpl %ebx, %r14d
je .L33
.L36:
movl $512, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $32768, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L34
movl %ebx, %edx
andl $1, %edx
movl %r12d, %esi
movq 8(%rsp), %rdi
call _Z34__device_stub__Z12bitonicMergePxibPxib
jmp .L34
.L51:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $145, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L33:
movl $2, %ecx
movq %r13, %rdx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
je .L37
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $149, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L37:
movq 8(%rsp), %rdi
call cudaFree@PLT
movl $0, %ebx
leaq 4(%rsp), %r12
testl %eax, %eax
je .L38
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $150, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L39:
movq 0(%rbp,%rbx,8), %rax
movl %eax, 4(%rsp)
movq stdout(%rip), %rcx
movl $1, %edx
movl $4, %esi
movq %r12, %rdi
call fwrite@PLT
addq $1, %rbx
.L38:
cmpl %ebx, (%rsp)
jg .L39
movq %rbp, %rdi
call _ZdaPv@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L52
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z12bitonicMergePxib"
.LC3:
.string "_Z16oddEvenBlockSortPxi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3700:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z12bitonicMergePxib(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z16oddEvenBlockSortPxi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "lab_5.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z31__device_stub__oddEvenBlockSortPxi # -- Begin function _Z31__device_stub__oddEvenBlockSortPxi
.p2align 4, 0x90
.type _Z31__device_stub__oddEvenBlockSortPxi,@function
_Z31__device_stub__oddEvenBlockSortPxi: # @_Z31__device_stub__oddEvenBlockSortPxi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16oddEvenBlockSortPxi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z31__device_stub__oddEvenBlockSortPxi, .Lfunc_end0-_Z31__device_stub__oddEvenBlockSortPxi
.cfi_endproc
# -- End function
.globl _Z27__device_stub__bitonicMergePxib # -- Begin function _Z27__device_stub__bitonicMergePxib
.p2align 4, 0x90
.type _Z27__device_stub__bitonicMergePxib,@function
_Z27__device_stub__bitonicMergePxib: # @_Z27__device_stub__bitonicMergePxib
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movb %dl, 3(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 3(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12bitonicMergePxib, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z27__device_stub__bitonicMergePxib, .Lfunc_end1-_Z27__device_stub__bitonicMergePxib
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %edi, %edi
callq _ZNSt8ios_base15sync_with_stdioEb
movq stdin(%rip), %rcx
leaq 84(%rsp), %rdi
movl $4, %esi
movl $1, %edx
callq fread
movslq 84(%rsp), %rbp
leal 511(%rbp), %eax
testq %rbp, %rbp
cmovnsl %ebp, %eax
andl $-512, %eax # imm = 0xFE00
leal 512(%rax), %ecx
cmpl %eax, %ebp
cmovel %ebp, %ecx
movl %ecx, 4(%rsp) # 4-byte Spill
movslq %ecx, %r15
leaq (,%r15,8), %rax
testl %r15d, %r15d
movq $-1, %rdi
movq %rax, 88(%rsp) # 8-byte Spill
cmovnsq %rax, %rdi
callq _Znam
movq %rax, %rbx
movl %ebp, %r13d
testq %rbp, %rbp
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
xorl %r12d, %r12d
leaq 8(%rsp), %r14
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq stdin(%rip), %rcx
movl $4, %esi
movl $1, %edx
movq %r14, %rdi
callq fread
movslq 8(%rsp), %rax
movq %rax, (%rbx,%r12,8)
incq %r12
cmpq %r12, %r13
jne .LBB2_2
.LBB2_3: # %.preheader81
cmpl 4(%rsp), %ebp # 4-byte Folded Reload
jge .LBB2_6
# %bb.4: # %.lr.ph84.preheader
movabsq $9223372036854775807, %rax # imm = 0x7FFFFFFFFFFFFFFF
movq %rbp, %rcx
.p2align 4, 0x90
.LBB2_5: # %.lr.ph84
# =>This Inner Loop Header: Depth=1
movq %rax, (%rbx,%rcx,8)
incq %rcx
cmpq %rcx, %r15
jne .LBB2_5
.LBB2_6: # %._crit_edge
leaq 16(%rsp), %rdi
movq 88(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_7
# %bb.9:
movq 16(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_10
# %bb.11:
movabsq $4295000064, %r15 # imm = 0x100008000
leaq -32512(%r15), %rdx
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_13
# %bb.12:
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl 4(%rsp), %eax # 4-byte Reload
movl %eax, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16oddEvenBlockSortPxi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_13:
movq %rbp, 128(%rsp) # 8-byte Spill
callq hipGetLastError
testl %eax, %eax
jne .LBB2_14
# %bb.15:
cmpl $513, 4(%rsp) # 4-byte Folded Reload
# imm = 0x201
jl .LBB2_22
# %bb.16: # %.preheader80
movl 4(%rsp), %ebp # 4-byte Reload
shrl $9, %ebp
xorl %r14d, %r14d
leaq -32256(%r15), %r12
.p2align 4, 0x90
.LBB2_18: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_20
# %bb.19: # in Loop: Header=BB2_18 Depth=1
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl 4(%rsp), %eax # 4-byte Reload
movl %eax, 12(%rsp)
movl %r14d, %eax
andb $1, %al
movb %al, 3(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 3(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z12bitonicMergePxib, %edi
leaq 96(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_20: # in Loop: Header=BB2_18 Depth=1
callq hipGetLastError
testl %eax, %eax
jne .LBB2_21
# %bb.17: # in Loop: Header=BB2_18 Depth=1
incl %r14d
cmpl %r14d, %ebp
jne .LBB2_18
.LBB2_22: # %.loopexit
movq 16(%rsp), %rsi
movq %rbx, %rdi
movq 88(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_23
# %bb.24:
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
movq 128(%rsp), %rcx # 8-byte Reload
jne .LBB2_29
# %bb.25: # %.preheader
testl %ecx, %ecx
jle .LBB2_28
# %bb.26: # %.lr.ph88.preheader
xorl %r15d, %r15d
leaq 8(%rsp), %r14
.p2align 4, 0x90
.LBB2_27: # %.lr.ph88
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,8), %eax
movl %eax, 8(%rsp)
movq stdout(%rip), %rcx
movl $4, %esi
movl $1, %edx
movq %r14, %rdi
callq fwrite
incq %r15
cmpq %r15, %r13
jne .LBB2_27
.LBB2_28: # %._crit_edge89
movq %rbx, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_21:
.cfi_def_cfa_offset 192
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movq %rbx, %rdi
movl $147, %ecx
.LBB2_8:
movq %rax, %r8
xorl %eax, %eax
callq fprintf
xorl %edi, %edi
callq exit
.LBB2_7:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movq %rbx, %rdi
movl $138, %ecx
jmp .LBB2_8
.LBB2_10:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movq %rbx, %rdi
movl $139, %ecx
jmp .LBB2_8
.LBB2_14:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movq %rbx, %rdi
movl $142, %ecx
jmp .LBB2_8
.LBB2_23:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movq %rbx, %rdi
movl $151, %ecx
jmp .LBB2_8
.LBB2_29:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movq %rbx, %rdi
movl $152, %ecx
jmp .LBB2_8
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16oddEvenBlockSortPxi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12bitonicMergePxib, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16oddEvenBlockSortPxi,@object # @_Z16oddEvenBlockSortPxi
.section .rodata,"a",@progbits
.globl _Z16oddEvenBlockSortPxi
.p2align 3, 0x0
_Z16oddEvenBlockSortPxi:
.quad _Z31__device_stub__oddEvenBlockSortPxi
.size _Z16oddEvenBlockSortPxi, 8
.type _Z12bitonicMergePxib,@object # @_Z12bitonicMergePxib
.globl _Z12bitonicMergePxib
.p2align 3, 0x0
_Z12bitonicMergePxib:
.quad _Z27__device_stub__bitonicMergePxib
.size _Z12bitonicMergePxib, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA Error in %s:%d: %s\n"
.size .L.str, 25
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/kri-k/GPGPU_CUDA/master/lab5/lab_5.hip"
.size .L.str.1, 96
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16oddEvenBlockSortPxi"
.size .L__unnamed_1, 24
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12bitonicMergePxib"
.size .L__unnamed_2, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__oddEvenBlockSortPxi
.addrsig_sym _Z27__device_stub__bitonicMergePxib
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16oddEvenBlockSortPxi
.addrsig_sym _Z12bitonicMergePxib
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <fstream>
#include <iostream>
#include <string>
#include <cstring>
#include <cstdlib>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/generate.h>
#include <thrust/sort.h>
#include <thrust/copy.h>
#include <thrust/binary_search.h>
#include <thrust/pair.h>
#define GPU_MEM 10000000
using namespace std;
//the particle index in the r200 file
bool isIndexBin = true;
string index_file_txt = "";//"/home/lyang/data/vl2b.00400.r200.index";
string index_file_bin = "";// "/home/lyang/data/vl2b.00400.r200.index";
//the particle file in the AHF particles
bool isAHFPartFileBin = false;
string ahf_part_file_txt = "";//"/home/lyang/halodata/vl_400_rhovesc.z0.000.AHF_particles";
string ahf_part_file_bin = "";//"/home/lyang/halodata/vl_400_rhovesc.z0.000.AHF_particles";
//the output halo flags (a binary file)
string output_file = "";//"vl2b.00400.r200.ahf.haloflags";
//halo ids to be selected
//the first int is a number of total number to be selected
//followed by the list of halo ids
bool isHaloIdsBin = false;
string haloids_to_be_selected_bin = "to_be_seleted.ids";
string haloids_to_be_selected_txt = "";
int * haloParticles_;
int * haloIds_;
int * searchParts_;
int * searchIndex_;
bool * searchResult_;
char * flags_;
int * particles_;
//bool verbose = false;
int numParts_ = 0;
int numOfHalos_ = 0;
void getSearchRes(int requiredSearchPartNum, int numPartsRead_,
thrust::device_vector<int> &dev_searchParts_,
thrust::device_vector<int> &dev_searchResult_,
thrust::device_vector<int> &dev_val){
//do the search
thrust::copy(searchParts_, searchParts_ + requiredSearchPartNum, dev_searchParts_.begin());
thrust::binary_search(dev_val.begin(), dev_val.begin() + numPartsRead_,
dev_searchParts_.begin(),
dev_searchParts_.begin() + requiredSearchPartNum,
dev_searchResult_.begin());
thrust::copy(dev_searchResult_.begin(), dev_searchResult_.begin() + requiredSearchPartNum, searchResult_);
for(int l = 0; l < requiredSearchPartNum; l++){
if(searchResult_[l]){
flags_[searchIndex_[l]] = 1;
}
}
}
void doSearch(int numPartsRead_, thrust::device_vector<int> &dev_searchParts_,
thrust::device_vector<int> &dev_searchResult_,
thrust::device_vector<int> &dev_val){
printf("Start testing %d halo particles...\n", numPartsRead_);
//start filling the tags
//step 1: sorting
printf("Sorting ...\n");
thrust::copy(haloParticles_, haloParticles_ + numPartsRead_, dev_val.begin());
thrust::sort(dev_val.begin(), dev_val.begin() + numPartsRead_);
//step 2: testing
printf("Searching ...\n");
//test every particle whether it's in the array
int requiredSearchPartNum = 0;
for(int k = 0; k < numParts_; k ++){
if(flags_[k] == 0){
searchParts_[requiredSearchPartNum] = particles_[k];
searchIndex_[requiredSearchPartNum] = k;
requiredSearchPartNum ++;
}
if(requiredSearchPartNum >= GPU_MEM){
getSearchRes(requiredSearchPartNum, numPartsRead_,
dev_searchParts_, dev_searchResult_, dev_val);
requiredSearchPartNum = 0;
}
}
if(requiredSearchPartNum > 0){
getSearchRes(requiredSearchPartNum, numPartsRead_,
dev_searchParts_, dev_searchResult_, dev_val);
requiredSearchPartNum = 0;
}
}
//get flags
void getFlag(){
thrust::device_vector<int> dev_searchParts_(GPU_MEM);
thrust::device_vector<int> dev_searchResult_(GPU_MEM);
thrust::device_vector<int> dev_val(GPU_MEM);
thrust::device_vector<int> dev_searchHaloIds_(numOfHalos_);
//thrust::binary_search(input.begin(), input.end(), 0, thrust::less<int>()); // returns true
thrust::copy(haloIds_, haloIds_ + numOfHalos_, dev_searchHaloIds_.begin());
thrust::sort(dev_searchHaloIds_.begin(), dev_searchHaloIds_.begin() + numOfHalos_);
//int currentHalo = 0;
int totalNumHalos = 0;
for(int i = 0; i < numParts_; i++){
flags_[i] = 0;
}
haloParticles_ = new int[GPU_MEM];
searchParts_ = new int[GPU_MEM];
searchIndex_ = new int[GPU_MEM];
searchResult_ = new bool[GPU_MEM];
ifstream haloInputFile_;
if(isAHFPartFileBin){
haloInputFile_.open(ahf_part_file_bin.c_str(), ios::binary | ios::in);
haloInputFile_.read((char *)&totalNumHalos, sizeof(int));
}else{
haloInputFile_.open(ahf_part_file_txt.c_str());
haloInputFile_ >> totalNumHalos;
}
if(!haloInputFile_.good()){
printf("AHF Particle File Error!\n");
exit(1);
}
int numPartsRead_ = 0;
printf("Start reading halo particles...\n", numOfHalos_);
for(int i = 0; i < totalNumHalos; i ++){
int numHaloParts;
if(isAHFPartFileBin){
haloInputFile_.read((char *) &numHaloParts, sizeof(int));
}else{
haloInputFile_ >> numHaloParts;
}
//printf("%d %d\n", i, numHaloParts);
if(thrust::binary_search(dev_searchHaloIds_.begin(),
dev_searchHaloIds_.end(),
i,
thrust::less<int>())){
printf("Halo: %d, Particles: %d.\n", i, numHaloParts);
for(int j = 0; j < numHaloParts; j++){
int partindex;
int ch;
if(isAHFPartFileBin){
haloInputFile_.read((char *) &partindex, sizeof(int));
haloInputFile_.read((char *) &ch, sizeof(int));
}else{
haloInputFile_ >> partindex;
haloInputFile_ >> ch;
}
haloParticles_[numPartsRead_] = partindex;
numPartsRead_ ++;
if(numPartsRead_ >= GPU_MEM){
doSearch(numPartsRead_, dev_searchParts_, dev_searchResult_, dev_val);
numPartsRead_ = 0;
}
}
}else{
string line;
if(isAHFPartFileBin){
haloInputFile_.seekg(sizeof(int) * numHaloParts, ios_base::cur);
}else{
for(int j = 0; j < numHaloParts + 1; j++){
getline(haloInputFile_, line);
//haloInputFile_.ignore(std::numeric_limits<std::streamsize>::max(), '\n');
}
//printf("%s\n", line.c_str());
}
}
}
if(numPartsRead_ > 0){
doSearch(numPartsRead_, dev_searchParts_, dev_searchResult_, dev_val);
numPartsRead_ = 0;
}
printf("\n");
haloInputFile_.close();
delete haloParticles_;
delete searchParts_;
delete searchIndex_;
delete searchResult_;
}
void printUsage(const char * name){
printf("%s \n%s \n%s \n%s \n%s\n", name,
"-[bin/txt]_index <index file>",
"-[bin/txt]_ahf <AHF particle output file>",
"-[bin/txt]_haloid <ids of halo to be selected>",
"-output <outputfile>");
}
int main(int argc, const char **argv){
int m=1;
if(argc < 9){
printUsage(argv[0]);
exit(1);
}
while (m<argc)
{
string arg = argv[m];
if (arg == "-bin_index") {
isIndexBin = true;
index_file_bin = argv[m+1];
m+=1;
}else if (arg == "-txt_index") {
isIndexBin = false;
index_file_txt = argv[m+1];
m+=1;
}else if (arg == "-bin_ahf") {
isAHFPartFileBin = true;
ahf_part_file_bin = argv[m+1];
m+=1;
}else if (arg == "-txt_ahf") {
isAHFPartFileBin = false;
ahf_part_file_txt = argv[m+1];
m+=1;
}else if (arg == "-output") {
output_file = argv[m+1];
m+=1;
}else if (arg == "-bin_haloid") {
isHaloIdsBin = true;
haloids_to_be_selected_bin = argv[m+1];
m+=1;
}else if (arg == "-txt_haloid") {
isHaloIdsBin = false;
haloids_to_be_selected_txt = argv[m+1];
m+=1;
}
//else if (arg == "-verbose") { verbose = true;}
else{
printUsage(argv[0]);
exit(0);
}
m++;
}
ifstream dataInputFile_;
if(isIndexBin){
dataInputFile_.open(index_file_bin.c_str(), ios::binary | ios::in);
if(!dataInputFile_.good()){
printf("Datafile error: %s !\n", index_file_bin.c_str());
exit(1);
}
dataInputFile_.read((char*)&numParts_, sizeof(int));
}else{
dataInputFile_.open(index_file_txt.c_str(), ios::in);
if(!dataInputFile_.good()){
printf("Datafile error: %s !\n", index_file_txt.c_str());
exit(1);
}
dataInputFile_ >>numParts_;
}
cout << "Particles: " << numParts_ << endl;
particles_ = new int[numParts_];
//printf("ok\n");
flags_ = new char[numParts_];
//printf("ok1\n");
if(isIndexBin){
dataInputFile_.read((char *) particles_, sizeof(int) * numParts_);
dataInputFile_.close();
}else{
for(int i = 0; i < numParts_; i++){
dataInputFile_ >> particles_[i];
}
dataInputFile_.close();
}
ifstream haloidsStream_;
//printf("%d %s\n", isHaloIdsBin, )
if(isHaloIdsBin){
haloidsStream_.open(haloids_to_be_selected_bin.c_str(), ios::binary);
if(!haloidsStream_.good()){
printf("Halo Id error: %s!\n", haloids_to_be_selected_bin.c_str());
exit(1);
}
haloidsStream_.read((char *) &numOfHalos_, sizeof(int));
}else{
haloidsStream_.open(haloids_to_be_selected_txt.c_str());
if(!haloidsStream_.good()){
printf("Halo Id error: %s!\n", haloids_to_be_selected_txt.c_str());
exit(1);
}
haloidsStream_ >> numOfHalos_;
}
printf("Number of Halos: %d\n", numOfHalos_);
haloIds_ = new int[numOfHalos_];
if(isHaloIdsBin){
haloidsStream_.read((char *) haloIds_, sizeof(int) * numOfHalos_);
haloidsStream_.close();
}else{
for(int i = 0; i < numOfHalos_; i++){
haloidsStream_ >> haloIds_[i];
}
haloidsStream_.close();
}
getFlag();
//output
printf("Output the result...\n");
ofstream dataOutputStream_(output_file.c_str(), ios::binary);
dataOutputStream_.write((char *) &numParts_, sizeof(int));
dataOutputStream_.write((char *) flags_, sizeof(char) * numParts_);
dataOutputStream_.close();
printf("Finished...\n");
delete particles_;
delete flags_;
delete haloIds_;
} | #include <hip/hip_runtime.h>
#include <fstream>
#include <iostream>
#include <string>
#include <cstring>
#include <cstdlib>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/generate.h>
#include <thrust/sort.h>
#include <thrust/copy.h>
#include <thrust/binary_search.h>
#include <thrust/pair.h>
#define GPU_MEM 10000000
using namespace std;
//the particle index in the r200 file
bool isIndexBin = true;
string index_file_txt = "";//"/home/lyang/data/vl2b.00400.r200.index";
string index_file_bin = "";// "/home/lyang/data/vl2b.00400.r200.index";
//the particle file in the AHF particles
bool isAHFPartFileBin = false;
string ahf_part_file_txt = "";//"/home/lyang/halodata/vl_400_rhovesc.z0.000.AHF_particles";
string ahf_part_file_bin = "";//"/home/lyang/halodata/vl_400_rhovesc.z0.000.AHF_particles";
//the output halo flags (a binary file)
string output_file = "";//"vl2b.00400.r200.ahf.haloflags";
//halo ids to be selected
//the first int is a number of total number to be selected
//followed by the list of halo ids
bool isHaloIdsBin = false;
string haloids_to_be_selected_bin = "to_be_seleted.ids";
string haloids_to_be_selected_txt = "";
int * haloParticles_;
int * haloIds_;
int * searchParts_;
int * searchIndex_;
bool * searchResult_;
char * flags_;
int * particles_;
//bool verbose = false;
int numParts_ = 0;
int numOfHalos_ = 0;
void getSearchRes(int requiredSearchPartNum, int numPartsRead_,
thrust::device_vector<int> &dev_searchParts_,
thrust::device_vector<int> &dev_searchResult_,
thrust::device_vector<int> &dev_val){
//do the search
thrust::copy(searchParts_, searchParts_ + requiredSearchPartNum, dev_searchParts_.begin());
thrust::binary_search(dev_val.begin(), dev_val.begin() + numPartsRead_,
dev_searchParts_.begin(),
dev_searchParts_.begin() + requiredSearchPartNum,
dev_searchResult_.begin());
thrust::copy(dev_searchResult_.begin(), dev_searchResult_.begin() + requiredSearchPartNum, searchResult_);
for(int l = 0; l < requiredSearchPartNum; l++){
if(searchResult_[l]){
flags_[searchIndex_[l]] = 1;
}
}
}
void doSearch(int numPartsRead_, thrust::device_vector<int> &dev_searchParts_,
thrust::device_vector<int> &dev_searchResult_,
thrust::device_vector<int> &dev_val){
printf("Start testing %d halo particles...\n", numPartsRead_);
//start filling the tags
//step 1: sorting
printf("Sorting ...\n");
thrust::copy(haloParticles_, haloParticles_ + numPartsRead_, dev_val.begin());
thrust::sort(dev_val.begin(), dev_val.begin() + numPartsRead_);
//step 2: testing
printf("Searching ...\n");
//test every particle whether it's in the array
int requiredSearchPartNum = 0;
for(int k = 0; k < numParts_; k ++){
if(flags_[k] == 0){
searchParts_[requiredSearchPartNum] = particles_[k];
searchIndex_[requiredSearchPartNum] = k;
requiredSearchPartNum ++;
}
if(requiredSearchPartNum >= GPU_MEM){
getSearchRes(requiredSearchPartNum, numPartsRead_,
dev_searchParts_, dev_searchResult_, dev_val);
requiredSearchPartNum = 0;
}
}
if(requiredSearchPartNum > 0){
getSearchRes(requiredSearchPartNum, numPartsRead_,
dev_searchParts_, dev_searchResult_, dev_val);
requiredSearchPartNum = 0;
}
}
//get flags
void getFlag(){
thrust::device_vector<int> dev_searchParts_(GPU_MEM);
thrust::device_vector<int> dev_searchResult_(GPU_MEM);
thrust::device_vector<int> dev_val(GPU_MEM);
thrust::device_vector<int> dev_searchHaloIds_(numOfHalos_);
//thrust::binary_search(input.begin(), input.end(), 0, thrust::less<int>()); // returns true
thrust::copy(haloIds_, haloIds_ + numOfHalos_, dev_searchHaloIds_.begin());
thrust::sort(dev_searchHaloIds_.begin(), dev_searchHaloIds_.begin() + numOfHalos_);
//int currentHalo = 0;
int totalNumHalos = 0;
for(int i = 0; i < numParts_; i++){
flags_[i] = 0;
}
haloParticles_ = new int[GPU_MEM];
searchParts_ = new int[GPU_MEM];
searchIndex_ = new int[GPU_MEM];
searchResult_ = new bool[GPU_MEM];
ifstream haloInputFile_;
if(isAHFPartFileBin){
haloInputFile_.open(ahf_part_file_bin.c_str(), ios::binary | ios::in);
haloInputFile_.read((char *)&totalNumHalos, sizeof(int));
}else{
haloInputFile_.open(ahf_part_file_txt.c_str());
haloInputFile_ >> totalNumHalos;
}
if(!haloInputFile_.good()){
printf("AHF Particle File Error!\n");
exit(1);
}
int numPartsRead_ = 0;
printf("Start reading halo particles...\n", numOfHalos_);
for(int i = 0; i < totalNumHalos; i ++){
int numHaloParts;
if(isAHFPartFileBin){
haloInputFile_.read((char *) &numHaloParts, sizeof(int));
}else{
haloInputFile_ >> numHaloParts;
}
//printf("%d %d\n", i, numHaloParts);
if(thrust::binary_search(dev_searchHaloIds_.begin(),
dev_searchHaloIds_.end(),
i,
thrust::less<int>())){
printf("Halo: %d, Particles: %d.\n", i, numHaloParts);
for(int j = 0; j < numHaloParts; j++){
int partindex;
int ch;
if(isAHFPartFileBin){
haloInputFile_.read((char *) &partindex, sizeof(int));
haloInputFile_.read((char *) &ch, sizeof(int));
}else{
haloInputFile_ >> partindex;
haloInputFile_ >> ch;
}
haloParticles_[numPartsRead_] = partindex;
numPartsRead_ ++;
if(numPartsRead_ >= GPU_MEM){
doSearch(numPartsRead_, dev_searchParts_, dev_searchResult_, dev_val);
numPartsRead_ = 0;
}
}
}else{
string line;
if(isAHFPartFileBin){
haloInputFile_.seekg(sizeof(int) * numHaloParts, ios_base::cur);
}else{
for(int j = 0; j < numHaloParts + 1; j++){
getline(haloInputFile_, line);
//haloInputFile_.ignore(std::numeric_limits<std::streamsize>::max(), '\n');
}
//printf("%s\n", line.c_str());
}
}
}
if(numPartsRead_ > 0){
doSearch(numPartsRead_, dev_searchParts_, dev_searchResult_, dev_val);
numPartsRead_ = 0;
}
printf("\n");
haloInputFile_.close();
delete haloParticles_;
delete searchParts_;
delete searchIndex_;
delete searchResult_;
}
void printUsage(const char * name){
printf("%s \n%s \n%s \n%s \n%s\n", name,
"-[bin/txt]_index <index file>",
"-[bin/txt]_ahf <AHF particle output file>",
"-[bin/txt]_haloid <ids of halo to be selected>",
"-output <outputfile>");
}
int main(int argc, const char **argv){
int m=1;
if(argc < 9){
printUsage(argv[0]);
exit(1);
}
while (m<argc)
{
string arg = argv[m];
if (arg == "-bin_index") {
isIndexBin = true;
index_file_bin = argv[m+1];
m+=1;
}else if (arg == "-txt_index") {
isIndexBin = false;
index_file_txt = argv[m+1];
m+=1;
}else if (arg == "-bin_ahf") {
isAHFPartFileBin = true;
ahf_part_file_bin = argv[m+1];
m+=1;
}else if (arg == "-txt_ahf") {
isAHFPartFileBin = false;
ahf_part_file_txt = argv[m+1];
m+=1;
}else if (arg == "-output") {
output_file = argv[m+1];
m+=1;
}else if (arg == "-bin_haloid") {
isHaloIdsBin = true;
haloids_to_be_selected_bin = argv[m+1];
m+=1;
}else if (arg == "-txt_haloid") {
isHaloIdsBin = false;
haloids_to_be_selected_txt = argv[m+1];
m+=1;
}
//else if (arg == "-verbose") { verbose = true;}
else{
printUsage(argv[0]);
exit(0);
}
m++;
}
ifstream dataInputFile_;
if(isIndexBin){
dataInputFile_.open(index_file_bin.c_str(), ios::binary | ios::in);
if(!dataInputFile_.good()){
printf("Datafile error: %s !\n", index_file_bin.c_str());
exit(1);
}
dataInputFile_.read((char*)&numParts_, sizeof(int));
}else{
dataInputFile_.open(index_file_txt.c_str(), ios::in);
if(!dataInputFile_.good()){
printf("Datafile error: %s !\n", index_file_txt.c_str());
exit(1);
}
dataInputFile_ >>numParts_;
}
cout << "Particles: " << numParts_ << endl;
particles_ = new int[numParts_];
//printf("ok\n");
flags_ = new char[numParts_];
//printf("ok1\n");
if(isIndexBin){
dataInputFile_.read((char *) particles_, sizeof(int) * numParts_);
dataInputFile_.close();
}else{
for(int i = 0; i < numParts_; i++){
dataInputFile_ >> particles_[i];
}
dataInputFile_.close();
}
ifstream haloidsStream_;
//printf("%d %s\n", isHaloIdsBin, )
if(isHaloIdsBin){
haloidsStream_.open(haloids_to_be_selected_bin.c_str(), ios::binary);
if(!haloidsStream_.good()){
printf("Halo Id error: %s!\n", haloids_to_be_selected_bin.c_str());
exit(1);
}
haloidsStream_.read((char *) &numOfHalos_, sizeof(int));
}else{
haloidsStream_.open(haloids_to_be_selected_txt.c_str());
if(!haloidsStream_.good()){
printf("Halo Id error: %s!\n", haloids_to_be_selected_txt.c_str());
exit(1);
}
haloidsStream_ >> numOfHalos_;
}
printf("Number of Halos: %d\n", numOfHalos_);
haloIds_ = new int[numOfHalos_];
if(isHaloIdsBin){
haloidsStream_.read((char *) haloIds_, sizeof(int) * numOfHalos_);
haloidsStream_.close();
}else{
for(int i = 0; i < numOfHalos_; i++){
haloidsStream_ >> haloIds_[i];
}
haloidsStream_.close();
}
getFlag();
//output
printf("Output the result...\n");
ofstream dataOutputStream_(output_file.c_str(), ios::binary);
dataOutputStream_.write((char *) &numParts_, sizeof(int));
dataOutputStream_.write((char *) flags_, sizeof(char) * numParts_);
dataOutputStream_.close();
printf("Finished...\n");
delete particles_;
delete flags_;
delete haloIds_;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
/**
* Various matrix utils using cuda
**/
/**
* Kronecker product of two matrices kernel
* input :
* a : first matrix
* nax, nay : matrix a dimensions
* b: second matrix
* nbx, nby : matrix b dimensions
* results : kronecker product of a and b
**/
__global__ void kronecker(double * a, int nax, int nay, double * b, int nbx, int nby, double * result){
// First we need to find our global threadID
int tPosX = blockIdx.x * blockDim.x + threadIdx.x;
int tPosY = blockIdx.y * blockDim.y + threadIdx.y;
int resSzx = nax * nbx;
//int resSzy = nay * nby;
int idxA = floor((tPosX) / (double)nbx);
int idyA = floor((tPosY) / (double)nby);
int idxB = (tPosX) % nbx;
int idyB = (tPosY) % nby;
// Check if the indices are within range
if (idxA >= nax || idyA > nay || idxB > nbx || idyB > nby)
{
result[tPosX + tPosY * resSzx] = -1;
return;
}
// Multiply appropriate elements
result[tPosX + tPosY * resSzx] = a[idyA * nax + idxA] * b[idyB * nbx + idxB];
} | code for sm_80
Function : _Z9kroneckerPdiiS_iiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ I2F.F64 R4, c[0x0][0x178] ; /* 0x00005e0000047b12 */
/* 0x000e220000201c00 */
/*0020*/ S2R R10, SR_CTAID.X ; /* 0x00000000000a7919 */
/* 0x000e620000002500 */
/*0030*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fe200078e00ff */
/*0040*/ BSSY B0, 0x1f0 ; /* 0x000001a000007945 */
/* 0x000fe40003800000 */
/*0050*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e680000002100 */
/*0060*/ S2R R11, SR_CTAID.Y ; /* 0x00000000000b7919 */
/* 0x000ea80000002600 */
/*0070*/ S2R R14, SR_TID.Y ; /* 0x00000000000e7919 */
/* 0x000ea20000002200 */
/*0080*/ MUFU.RCP64H R3, R5 ; /* 0x0000000500037308 */
/* 0x001e220000001800 */
/*0090*/ IMAD R10, R10, c[0x0][0x0], R9 ; /* 0x000000000a0a7a24 */
/* 0x002fe200078e0209 */
/*00a0*/ DFMA R6, -R4, R2, 1 ; /* 0x3ff000000406742b */
/* 0x001e0c0000000102 */
/*00b0*/ DFMA R6, R6, R6, R6 ; /* 0x000000060606722b */
/* 0x001e0c0000000006 */
/*00c0*/ DFMA R2, R2, R6, R2 ; /* 0x000000060202722b */
/* 0x0010480000000002 */
/*00d0*/ I2F.F64 R6, R10 ; /* 0x0000000a00067312 */
/* 0x001e240000201c00 */
/*00e0*/ DFMA R8, -R4, R2, 1 ; /* 0x3ff000000408742b */
/* 0x002e4c0000000102 */
/*00f0*/ DFMA R2, R2, R8, R2 ; /* 0x000000080202722b */
/* 0x002e0c0000000002 */
/*0100*/ DMUL R8, R6, R2 ; /* 0x0000000206087228 */
/* 0x001e220000000000 */
/*0110*/ FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; /* 0x036000000700780b */
/* 0x000fca0003f2e200 */
/*0120*/ DFMA R12, -R4, R8, R6 ; /* 0x00000008040c722b */
/* 0x001e0c0000000106 */
/*0130*/ DFMA R2, R2, R12, R8 ; /* 0x0000000c0202722b */
/* 0x001e140000000008 */
/*0140*/ FFMA R0, RZ, R5, R3 ; /* 0x00000005ff007223 */
/* 0x001fca0000000003 */
/*0150*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fe20003f04200 */
/*0160*/ IMAD R0, R11, c[0x0][0x4], R14 ; /* 0x000001000b007a24 */
/* 0x004fd800078e020e */
/*0170*/ @P0 BRA P1, 0x1e0 ; /* 0x0000006000000947 */
/* 0x000fea0000800000 */
/*0180*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0006 */
/*0190*/ MOV R12, 0x1e0 ; /* 0x000001e0000c7802 */
/* 0x000fe20000000f00 */
/*01a0*/ IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0007 */
/*01b0*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0004 */
/*01c0*/ IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0005 */
/*01d0*/ CALL.REL.NOINC 0x800 ; /* 0x0000062000007944 */
/* 0x000fea0003c00000 */
/*01e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01f0*/ I2F.F64 R4, c[0x0][0x17c] ; /* 0x00005f0000047b12 */
/* 0x000e220000201c00 */
/*0200*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fe200078e00ff */
/*0210*/ BSSY B0, 0x3a0 ; /* 0x0000018000007945 */
/* 0x000fec0003800000 */
/*0220*/ F2I.F64.FLOOR R11, R2 ; /* 0x00000002000b7311 */
/* 0x000ff00000305100 */
/*0230*/ MUFU.RCP64H R7, R5 ; /* 0x0000000500077308 */
/* 0x001e240000001800 */
/*0240*/ DFMA R8, -R4, R6, 1 ; /* 0x3ff000000408742b */
/* 0x001e0c0000000106 */
/*0250*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*0260*/ DFMA R8, R6, R8, R6 ; /* 0x000000080608722b */
/* 0x0010a40000000006 */
/*0270*/ I2F.F64 R6, R0 ; /* 0x0000000000067312 */
/* 0x001e280000201c00 */
/*0280*/ DFMA R12, -R4, R8, 1 ; /* 0x3ff00000040c742b */
/* 0x004e8c0000000108 */
/*0290*/ DFMA R12, R8, R12, R8 ; /* 0x0000000c080c722b */
/* 0x004e0c0000000008 */
/*02a0*/ DMUL R8, R6, R12 ; /* 0x0000000c06087228 */
/* 0x001e220000000000 */
/*02b0*/ FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; /* 0x036000000700780b */
/* 0x000fca0003f2e200 */
/*02c0*/ DFMA R14, -R4, R8, R6 ; /* 0x00000008040e722b */
/* 0x001e0c0000000106 */
/*02d0*/ DFMA R8, R12, R14, R8 ; /* 0x0000000e0c08722b */
/* 0x001e140000000008 */
/*02e0*/ FFMA R12, RZ, R5, R9 ; /* 0x00000005ff0c7223 */
/* 0x001fca0000000009 */
/*02f0*/ FSETP.GT.AND P0, PT, |R12|, 1.469367938527859385e-39, PT ; /* 0x001000000c00780b */
/* 0x000fda0003f04200 */
/*0300*/ @P0 BRA P1, 0x390 ; /* 0x0000008000000947 */
/* 0x000fea0000800000 */
/*0310*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0006 */
/*0320*/ MOV R12, 0x370 ; /* 0x00000370000c7802 */
/* 0x000fe20000000f00 */
/*0330*/ IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0007 */
/*0340*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0004 */
/*0350*/ IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0005 */
/*0360*/ CALL.REL.NOINC 0x800 ; /* 0x0000049000007944 */
/* 0x002fea0003c00000 */
/*0370*/ IMAD.MOV.U32 R8, RZ, RZ, R2 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0002 */
/*0380*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0003 */
/*0390*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03a0*/ F2I.F64.FLOOR R4, R8 ; /* 0x0000000800047311 */
/* 0x000e220000305100 */
/*03b0*/ ULDC.64 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000a00 */
/*03c0*/ IMAD R3, R0, c[0x0][0x168], RZ ; /* 0x00005a0000037a24 */
/* 0x000fe200078e02ff */
/*03d0*/ ULOP3.LUT UR4, UR5, UR4, URZ, 0xfc, !UPT ; /* 0x0000000405047292 */
/* 0x000fe2000f8efc3f */
/*03e0*/ MOV R2, 0x8 ; /* 0x0000000800027802 */
/* 0x000fe20000000f00 */
/*03f0*/ BSSY B0, 0x7e0 ; /* 0x000003e000007945 */
/* 0x000fe20003800000 */
/*0400*/ IMAD R3, R3, c[0x0][0x178], R10 ; /* 0x00005e0003037a24 */
/* 0x000fc400078e020a */
/*0410*/ IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; /* 0x00000000ff067424 */
/* 0x000fe400078e00ff */
/*0420*/ IMAD.WIDE R2, R3, R2, c[0x0][0x180] ; /* 0x0000600003027625 */
/* 0x000fc800078e0202 */
/*0430*/ IMAD.MOV.U32 R7, RZ, RZ, -0x40100000 ; /* 0xbff00000ff077424 */
/* 0x000fe200078e00ff */
/*0440*/ ISETP.GT.AND P0, PT, R4, c[0x0][0x16c], PT ; /* 0x00005b0004007a0c */
/* 0x001fc80003f04270 */
/*0450*/ ISETP.GE.OR P0, PT, R11, c[0x0][0x168], P0 ; /* 0x00005a000b007a0c */
/* 0x000fc80000706670 */
/*0460*/ ISETP.GT.OR P0, PT, RZ, UR4, P0 ; /* 0x00000004ff007c0c */
/* 0x000fe20008704670 */
/*0470*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd80000000a00 */
/*0480*/ @P0 BRA 0x7d0 ; /* 0x0000034000000947 */
/* 0x000fea0003800000 */
/*0490*/ IABS R6, c[0x0][0x17c] ; /* 0x00005f0000067a13 */
/* 0x000fe40000000000 */
/*04a0*/ IABS R5, c[0x0][0x178] ; /* 0x00005e0000057a13 */
/* 0x000fe40000000000 */
/*04b0*/ I2F.RP R7, R6 ; /* 0x0000000600077306 */
/* 0x000e220000209400 */
/*04c0*/ ISETP.GE.AND P2, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f46270 */
/*04d0*/ ISETP.NE.AND P4, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fca0003f85270 */
/*04e0*/ I2F.RP R14, R5 ; /* 0x00000005000e7306 */
/* 0x000eb00000209400 */
/*04f0*/ MUFU.RCP R7, R7 ; /* 0x0000000700077308 */
/* 0x001e300000001000 */
/*0500*/ MUFU.RCP R14, R14 ; /* 0x0000000e000e7308 */
/* 0x004ea20000001000 */
/*0510*/ IADD3 R12, R7, 0xffffffe, RZ ; /* 0x0ffffffe070c7810 */
/* 0x001fc40007ffe0ff */
/*0520*/ IABS R7, R0 ; /* 0x0000000000077213 */
/* 0x000fca0000000000 */
/*0530*/ F2I.FTZ.U32.TRUNC.NTZ R13, R12 ; /* 0x0000000c000d7305 */
/* 0x0000e2000021f000 */
/*0540*/ IADD3 R8, R14, 0xffffffe, RZ ; /* 0x0ffffffe0e087810 */
/* 0x004fce0007ffe0ff */
/*0550*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x000522000021f000 */
/*0560*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x001fe400078e00ff */
/*0570*/ IMAD.MOV R15, RZ, RZ, -R13 ; /* 0x000000ffff0f7224 */
/* 0x008fe400078e0a0d */
/*0580*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x004fe400078e00ff */
/*0590*/ IMAD R15, R15, R6, RZ ; /* 0x000000060f0f7224 */
/* 0x000fe400078e02ff */
/*05a0*/ IMAD.MOV R16, RZ, RZ, -R9 ; /* 0x000000ffff107224 */
/* 0x012fe400078e0a09 */
/*05b0*/ IMAD.HI.U32 R12, R13, R15, R12 ; /* 0x0000000f0d0c7227 */
/* 0x000fe200078e000c */
/*05c0*/ IABS R13, R10 ; /* 0x0000000a000d7213 */
/* 0x000fc60000000000 */
/*05d0*/ IMAD R17, R16, R5, RZ ; /* 0x0000000510117224 */
/* 0x000fe400078e02ff */
/*05e0*/ IMAD.HI.U32 R12, R12, R7, RZ ; /* 0x000000070c0c7227 */
/* 0x000fc800078e00ff */
/*05f0*/ IMAD.HI.U32 R8, R9, R17, R8 ; /* 0x0000001109087227 */
/* 0x000fc800078e0008 */
/*0600*/ IMAD.MOV.U32 R9, RZ, RZ, R13 ; /* 0x000000ffff097224 */
/* 0x000fe400078e000d */
/*0610*/ IMAD.MOV R12, RZ, RZ, -R12 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0a0c */
/*0620*/ IMAD.HI.U32 R8, R8, R9, RZ ; /* 0x0000000908087227 */
/* 0x000fc800078e00ff */
/*0630*/ IMAD R7, R6, R12, R7 ; /* 0x0000000c06077224 */
/* 0x000fe400078e0207 */
/*0640*/ IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff087224 */
/* 0x000fc600078e0a08 */
/*0650*/ ISETP.GT.U32.AND P0, PT, R6, R7, PT ; /* 0x000000070600720c */
/* 0x000fe20003f04070 */
/*0660*/ IMAD R8, R5, R8, R9 ; /* 0x0000000805087224 */
/* 0x000fca00078e0209 */
/*0670*/ ISETP.GT.U32.AND P1, PT, R5, R8, PT ; /* 0x000000080500720c */
/* 0x000fce0003f24070 */
/*0680*/ @!P0 IMAD.IADD R7, R7, 0x1, -R6 ; /* 0x0000000107078824 */
/* 0x000fca00078e0a06 */
/*0690*/ ISETP.GT.U32.AND P3, PT, R6, R7, PT ; /* 0x000000070600720c */
/* 0x000fe40003f64070 */
/*06a0*/ @!P1 IADD3 R8, R8, -R5, RZ ; /* 0x8000000508089210 */
/* 0x000fe40007ffe0ff */
/*06b0*/ ISETP.GE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f26270 */
/*06c0*/ ISETP.GT.U32.AND P0, PT, R5, R8, PT ; /* 0x000000080500720c */
/* 0x000fce0003f04070 */
/*06d0*/ @!P3 IMAD.IADD R7, R7, 0x1, -R6 ; /* 0x000000010707b824 */
/* 0x000fe200078e0a06 */
/*06e0*/ ISETP.NE.AND P3, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fc60003f65270 */
/*06f0*/ @!P1 IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff079224 */
/* 0x000fe400078e0a07 */
/*0700*/ @!P0 IMAD.IADD R8, R8, 0x1, -R5 ; /* 0x0000000108088824 */
/* 0x000fe400078e0a05 */
/*0710*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fe400078e00ff */
/*0720*/ IMAD.MOV.U32 R0, RZ, RZ, R8 ; /* 0x000000ffff007224 */
/* 0x000fe400078e0008 */
/*0730*/ IMAD R8, R4, c[0x0][0x168], R11 ; /* 0x00005a0004087a24 */
/* 0x000fe400078e020b */
/*0740*/ @!P2 IMAD.MOV R0, RZ, RZ, -R0 ; /* 0x000000ffff00a224 */
/* 0x000fe200078e0a00 */
/*0750*/ @!P3 LOP3.LUT R7, RZ, c[0x0][0x17c], RZ, 0x33, !PT ; /* 0x00005f00ff07ba12 */
/* 0x000fe200078e33ff */
/*0760*/ IMAD.WIDE R8, R8, R5, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fe200078e0205 */
/*0770*/ @!P4 LOP3.LUT R0, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff00ca12 */
/* 0x000fca00078e33ff */
/*0780*/ IMAD R4, R7, c[0x0][0x178], R0 ; /* 0x00005e0007047a24 */
/* 0x000fe400078e0200 */
/*0790*/ LDG.E.64 R6, [R8.64] ; /* 0x0000000408067981 */
/* 0x000ea4000c1e1b00 */
/*07a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fcc00078e0205 */
/*07b0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1b00 */
/*07c0*/ DMUL R6, R4, R6 ; /* 0x0000000604067228 */
/* 0x00404c0000000000 */
/*07d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07e0*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x002fe2000c101b04 */
/*07f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0800*/ FSETP.GEU.AND P0, PT, |R7|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x040fe20003f0e200 */
/*0810*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0e7424 */
/* 0x000fe200078e00ff */
/*0820*/ LOP3.LUT R4, R7, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff07047812 */
/* 0x000fe200078ec0ff */
/*0830*/ IMAD.MOV.U32 R18, RZ, RZ, 0x1 ; /* 0x00000001ff127424 */
/* 0x000fe200078e00ff */
/*0840*/ FSETP.GEU.AND P2, PT, |R9|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000900780b */
/* 0x040fe20003f4e200 */
/*0850*/ BSSY B1, 0xda0 ; /* 0x0000054000017945 */
/* 0x000fe20003800000 */
/*0860*/ LOP3.LUT R5, R4, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000004057812 */
/* 0x000fe200078efcff */
/*0870*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0006 */
/*0880*/ LOP3.LUT R13, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000090d7812 */
/* 0x000fc400078ec0ff */
/*0890*/ LOP3.LUT R20, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007147812 */
/* 0x000fc600078ec0ff */
/*08a0*/ @!P0 DMUL R4, R6, 8.98846567431157953865e+307 ; /* 0x7fe0000006048828 */
/* 0x000e220000000000 */
/*08b0*/ ISETP.GE.U32.AND P1, PT, R13, R20, PT ; /* 0x000000140d00720c */
/* 0x000fc60003f26070 */
/*08c0*/ @!P2 LOP3.LUT R2, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000702a812 */
/* 0x000fe400078ec0ff */
/*08d0*/ MUFU.RCP64H R19, R5 ; /* 0x0000000500137308 */
/* 0x001e220000001800 */
/*08e0*/ SEL R3, R14.reuse, 0x63400000, !P1 ; /* 0x634000000e037807 */
/* 0x040fe40004800000 */
/*08f0*/ @!P2 ISETP.GE.U32.AND P3, PT, R13, R2, PT ; /* 0x000000020d00a20c */
/* 0x000fe20003f66070 */
/*0900*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0008 */
/*0910*/ LOP3.LUT R3, R3, 0x800fffff, R9, 0xf8, !PT ; /* 0x800fffff03037812 */
/* 0x000fe400078ef809 */
/*0920*/ @!P2 SEL R15, R14, 0x63400000, !P3 ; /* 0x634000000e0fa807 */
/* 0x000fe40005800000 */
/*0930*/ @!P2 MOV R16, RZ ; /* 0x000000ff0010a202 */
/* 0x000fc40000000f00 */
/*0940*/ @!P2 LOP3.LUT R15, R15, 0x80000000, R9, 0xf8, !PT ; /* 0x800000000f0fa812 */
/* 0x000fc800078ef809 */
/*0950*/ @!P2 LOP3.LUT R17, R15, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000f11a812 */
/* 0x000fe200078efcff */
/*0960*/ DFMA R22, R18, -R4, 1 ; /* 0x3ff000001216742b */
/* 0x001e220000000804 */
/*0970*/ IMAD.MOV.U32 R15, RZ, RZ, R13 ; /* 0x000000ffff0f7224 */
/* 0x000fc800078e000d */
/*0980*/ @!P2 DFMA R2, R2, 2, -R16 ; /* 0x400000000202a82b */
/* 0x000fc80000000810 */
/*0990*/ DFMA R22, R22, R22, R22 ; /* 0x000000161616722b */
/* 0x001e0c0000000016 */
/*09a0*/ DFMA R18, R18, R22, R18 ; /* 0x000000161212722b */
/* 0x0010620000000012 */
/*09b0*/ @!P2 LOP3.LUT R15, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000030fa812 */
/* 0x000fe200078ec0ff */
/*09c0*/ IMAD.MOV.U32 R22, RZ, RZ, R20 ; /* 0x000000ffff167224 */
/* 0x001fe200078e0014 */
/*09d0*/ @!P0 LOP3.LUT R22, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005168812 */
/* 0x000fe400078ec0ff */
/*09e0*/ IADD3 R20, R15, -0x1, RZ ; /* 0xffffffff0f147810 */
/* 0x000fe20007ffe0ff */
/*09f0*/ DFMA R16, R18, -R4, 1 ; /* 0x3ff000001210742b */
/* 0x002e220000000804 */
/*0a00*/ IADD3 R23, R22, -0x1, RZ ; /* 0xffffffff16177810 */
/* 0x000fe40007ffe0ff */
/*0a10*/ ISETP.GT.U32.AND P0, PT, R20, 0x7feffffe, PT ; /* 0x7feffffe1400780c */
/* 0x000fc60003f04070 */
/*0a20*/ DFMA R16, R18, R16, R18 ; /* 0x000000101210722b */
/* 0x001e220000000012 */
/*0a30*/ ISETP.GT.U32.OR P0, PT, R23, 0x7feffffe, P0 ; /* 0x7feffffe1700780c */
/* 0x000fca0000704470 */
/*0a40*/ DMUL R18, R16, R2 ; /* 0x0000000210127228 */
/* 0x001e0c0000000000 */
/*0a50*/ DFMA R20, R18, -R4, R2 ; /* 0x800000041214722b */
/* 0x001e0c0000000002 */
/*0a60*/ DFMA R16, R16, R20, R18 ; /* 0x000000141010722b */
/* 0x0010620000000012 */
/*0a70*/ @P0 BRA 0xc40 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0a80*/ LOP3.LUT R18, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007127812 */
/* 0x001fc800078ec0ff */
/*0a90*/ ISETP.GE.U32.AND P0, PT, R13.reuse, R18, PT ; /* 0x000000120d00720c */
/* 0x040fe20003f06070 */
/*0aa0*/ IMAD.IADD R8, R13, 0x1, -R18 ; /* 0x000000010d087824 */
/* 0x000fc600078e0a12 */
/*0ab0*/ SEL R13, R14, 0x63400000, !P0 ; /* 0x634000000e0d7807 */
/* 0x000fe40004000000 */
/*0ac0*/ IMNMX R8, R8, -0x46a00000, !PT ; /* 0xb960000008087817 */
/* 0x000fc80007800200 */
/*0ad0*/ IMNMX R8, R8, 0x46a00000, PT ; /* 0x46a0000008087817 */
/* 0x000fca0003800200 */
/*0ae0*/ IMAD.IADD R13, R8, 0x1, -R13 ; /* 0x00000001080d7824 */
/* 0x000fe400078e0a0d */
/*0af0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fc600078e00ff */
/*0b00*/ IADD3 R9, R13, 0x7fe00000, RZ ; /* 0x7fe000000d097810 */
/* 0x000fcc0007ffe0ff */
/*0b10*/ DMUL R18, R16, R8 ; /* 0x0000000810127228 */
/* 0x002e140000000000 */
/*0b20*/ FSETP.GTU.AND P0, PT, |R19|, 1.469367938527859385e-39, PT ; /* 0x001000001300780b */
/* 0x001fda0003f0c200 */
/*0b30*/ @P0 BRA 0xd90 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0b40*/ DFMA R2, R16, -R4, R2 ; /* 0x800000041002722b */
/* 0x000e220000000002 */
/*0b50*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fd200078e00ff */
/*0b60*/ FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720b */
/* 0x041fe40003f0d000 */
/*0b70*/ LOP3.LUT R7, R3, 0x80000000, R7, 0x48, !PT ; /* 0x8000000003077812 */
/* 0x000fc800078e4807 */
/*0b80*/ LOP3.LUT R9, R7, R9, RZ, 0xfc, !PT ; /* 0x0000000907097212 */
/* 0x000fce00078efcff */
/*0b90*/ @!P0 BRA 0xd90 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0ba0*/ IMAD.MOV R3, RZ, RZ, -R13 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a0d */
/*0bb0*/ DMUL.RP R8, R16, R8 ; /* 0x0000000810087228 */
/* 0x000e220000008000 */
/*0bc0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fcc00078e00ff */
/*0bd0*/ DFMA R2, R18, -R2, R16 ; /* 0x800000021202722b */
/* 0x000e460000000010 */
/*0be0*/ LOP3.LUT R7, R9, R7, RZ, 0x3c, !PT ; /* 0x0000000709077212 */
/* 0x001fc600078e3cff */
/*0bf0*/ IADD3 R2, -R13, -0x43300000, RZ ; /* 0xbcd000000d027810 */
/* 0x002fc80007ffe1ff */
/*0c00*/ FSETP.NEU.AND P0, PT, |R3|, R2, PT ; /* 0x000000020300720b */
/* 0x000fc80003f0d200 */
/*0c10*/ FSEL R18, R8, R18, !P0 ; /* 0x0000001208127208 */
/* 0x000fe40004000000 */
/*0c20*/ FSEL R19, R7, R19, !P0 ; /* 0x0000001307137208 */
/* 0x000fe20004000000 */
/*0c30*/ BRA 0xd90 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0c40*/ DSETP.NAN.AND P0, PT, R8, R8, PT ; /* 0x000000080800722a */
/* 0x000e9c0003f08000 */
/*0c50*/ @P0 BRA 0xd70 ; /* 0x0000011000000947 */
/* 0x004fea0003800000 */
/*0c60*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x000e9c0003f08000 */
/*0c70*/ @P0 BRA 0xd40 ; /* 0x000000c000000947 */
/* 0x004fea0003800000 */
/*0c80*/ ISETP.NE.AND P0, PT, R15, R22, PT ; /* 0x000000160f00720c */
/* 0x000fe20003f05270 */
/*0c90*/ IMAD.MOV.U32 R18, RZ, RZ, 0x0 ; /* 0x00000000ff127424 */
/* 0x001fe200078e00ff */
/*0ca0*/ MOV R19, 0xfff80000 ; /* 0xfff8000000137802 */
/* 0x000fd60000000f00 */
/*0cb0*/ @!P0 BRA 0xd90 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0cc0*/ ISETP.NE.AND P0, PT, R15, 0x7ff00000, PT ; /* 0x7ff000000f00780c */
/* 0x000fe40003f05270 */
/*0cd0*/ LOP3.LUT R19, R9, 0x80000000, R7, 0x48, !PT ; /* 0x8000000009137812 */
/* 0x000fe400078e4807 */
/*0ce0*/ ISETP.EQ.OR P0, PT, R22, RZ, !P0 ; /* 0x000000ff1600720c */
/* 0x000fda0004702670 */
/*0cf0*/ @P0 LOP3.LUT R2, R19, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000013020812 */
/* 0x000fe200078efcff */
/*0d00*/ @!P0 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff128224 */
/* 0x000fe400078e00ff */
/*0d10*/ @P0 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff120224 */
/* 0x000fe400078e00ff */
/*0d20*/ @P0 IMAD.MOV.U32 R19, RZ, RZ, R2 ; /* 0x000000ffff130224 */
/* 0x000fe200078e0002 */
/*0d30*/ BRA 0xd90 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0d40*/ LOP3.LUT R19, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000007137812 */
/* 0x001fe200078efcff */
/*0d50*/ IMAD.MOV.U32 R18, RZ, RZ, R6 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0006 */
/*0d60*/ BRA 0xd90 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0d70*/ LOP3.LUT R19, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000009137812 */
/* 0x001fe200078efcff */
/*0d80*/ IMAD.MOV.U32 R18, RZ, RZ, R8 ; /* 0x000000ffff127224 */
/* 0x000fe400078e0008 */
/*0d90*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0da0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x0 ; /* 0x00000000ff0d7424 */
/* 0x000fe400078e00ff */
/*0db0*/ IMAD.MOV.U32 R2, RZ, RZ, R18 ; /* 0x000000ffff027224 */
/* 0x000fc400078e0012 */
/*0dc0*/ IMAD.MOV.U32 R3, RZ, RZ, R19 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0013 */
/*0dd0*/ RET.REL.NODEC R12 0x0 ; /* 0xfffff2200c007950 */
/* 0x000fec0003c3ffff */
/*0de0*/ BRA 0xde0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
/**
* Various matrix utils using cuda
**/
/**
* Kronecker product of two matrices kernel
* input :
* a : first matrix
* nax, nay : matrix a dimensions
* b: second matrix
* nbx, nby : matrix b dimensions
* results : kronecker product of a and b
**/
__global__ void kronecker(double * a, int nax, int nay, double * b, int nbx, int nby, double * result){
// First we need to find our global threadID
int tPosX = blockIdx.x * blockDim.x + threadIdx.x;
int tPosY = blockIdx.y * blockDim.y + threadIdx.y;
int resSzx = nax * nbx;
//int resSzy = nay * nby;
int idxA = floor((tPosX) / (double)nbx);
int idyA = floor((tPosY) / (double)nby);
int idxB = (tPosX) % nbx;
int idyB = (tPosY) % nby;
// Check if the indices are within range
if (idxA >= nax || idyA > nay || idxB > nbx || idyB > nby)
{
result[tPosX + tPosY * resSzx] = -1;
return;
}
// Multiply appropriate elements
result[tPosX + tPosY * resSzx] = a[idyA * nax + idxA] * b[idyB * nbx + idxB];
} | .file "tmpxft_000516ed_00000000-6_kronecker.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z9kroneckerPdiiS_iiS_PdiiS_iiS_
.type _Z36__device_stub__Z9kroneckerPdiiS_iiS_PdiiS_iiS_, @function
_Z36__device_stub__Z9kroneckerPdiiS_iiS_PdiiS_iiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movq %rcx, 24(%rsp)
movl %r8d, 20(%rsp)
movl %r9d, 16(%rsp)
movq 192(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9kroneckerPdiiS_iiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z9kroneckerPdiiS_iiS_PdiiS_iiS_, .-_Z36__device_stub__Z9kroneckerPdiiS_iiS_PdiiS_iiS_
.globl _Z9kroneckerPdiiS_iiS_
.type _Z9kroneckerPdiiS_iiS_, @function
_Z9kroneckerPdiiS_iiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z36__device_stub__Z9kroneckerPdiiS_iiS_PdiiS_iiS_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9kroneckerPdiiS_iiS_, .-_Z9kroneckerPdiiS_iiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9kroneckerPdiiS_iiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9kroneckerPdiiS_iiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
/**
* Various matrix utils using cuda
**/
/**
* Kronecker product of two matrices kernel
* input :
* a : first matrix
* nax, nay : matrix a dimensions
* b: second matrix
* nbx, nby : matrix b dimensions
* results : kronecker product of a and b
**/
__global__ void kronecker(double * a, int nax, int nay, double * b, int nbx, int nby, double * result){
// First we need to find our global threadID
int tPosX = blockIdx.x * blockDim.x + threadIdx.x;
int tPosY = blockIdx.y * blockDim.y + threadIdx.y;
int resSzx = nax * nbx;
//int resSzy = nay * nby;
int idxA = floor((tPosX) / (double)nbx);
int idyA = floor((tPosY) / (double)nby);
int idxB = (tPosX) % nbx;
int idyB = (tPosY) % nby;
// Check if the indices are within range
if (idxA >= nax || idyA > nay || idxB > nbx || idyB > nby)
{
result[tPosX + tPosY * resSzx] = -1;
return;
}
// Multiply appropriate elements
result[tPosX + tPosY * resSzx] = a[idyA * nax + idxA] * b[idyB * nbx + idxB];
} | #include <hip/hip_runtime.h>
#include "includes.h"
/**
* Various matrix utils using cuda
**/
/**
* Kronecker product of two matrices kernel
* input :
* a : first matrix
* nax, nay : matrix a dimensions
* b: second matrix
* nbx, nby : matrix b dimensions
* results : kronecker product of a and b
**/
__global__ void kronecker(double * a, int nax, int nay, double * b, int nbx, int nby, double * result){
// First we need to find our global threadID
int tPosX = blockIdx.x * blockDim.x + threadIdx.x;
int tPosY = blockIdx.y * blockDim.y + threadIdx.y;
int resSzx = nax * nbx;
//int resSzy = nay * nby;
int idxA = floor((tPosX) / (double)nbx);
int idyA = floor((tPosY) / (double)nby);
int idxB = (tPosX) % nbx;
int idyB = (tPosY) % nby;
// Check if the indices are within range
if (idxA >= nax || idyA > nay || idxB > nbx || idyB > nby)
{
result[tPosX + tPosY * resSzx] = -1;
return;
}
// Multiply appropriate elements
result[tPosX + tPosY * resSzx] = a[idyA * nax + idxA] * b[idyB * nbx + idxB];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/**
* Various matrix utils using cuda
**/
/**
* Kronecker product of two matrices kernel
* input :
* a : first matrix
* nax, nay : matrix a dimensions
* b: second matrix
* nbx, nby : matrix b dimensions
* results : kronecker product of a and b
**/
__global__ void kronecker(double * a, int nax, int nay, double * b, int nbx, int nby, double * result){
// First we need to find our global threadID
int tPosX = blockIdx.x * blockDim.x + threadIdx.x;
int tPosY = blockIdx.y * blockDim.y + threadIdx.y;
int resSzx = nax * nbx;
//int resSzy = nay * nby;
int idxA = floor((tPosX) / (double)nbx);
int idyA = floor((tPosY) / (double)nby);
int idxB = (tPosX) % nbx;
int idyB = (tPosY) % nby;
// Check if the indices are within range
if (idxA >= nax || idyA > nay || idxB > nbx || idyB > nby)
{
result[tPosX + tPosY * resSzx] = -1;
return;
}
// Multiply appropriate elements
result[tPosX + tPosY * resSzx] = a[idyA * nax + idxA] * b[idyB * nbx + idxB];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9kroneckerPdiiS_iiS_
.globl _Z9kroneckerPdiiS_iiS_
.p2align 8
.type _Z9kroneckerPdiiS_iiS_,@function
_Z9kroneckerPdiiS_iiS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[4:5], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_load_b64 s[6:7], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cvt_f64_i32_e32 v[2:3], s4
v_cvt_f64_i32_e32 v[6:7], s5
s_or_b32 s3, s5, s4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cvt_f64_i32_e32 v[4:5], v0
v_cvt_f64_i32_e32 v[8:9], v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_scale_f64 v[10:11], null, v[2:3], v[2:3], v[4:5]
v_div_scale_f64 v[12:13], null, v[6:7], v[6:7], v[8:9]
v_div_scale_f64 v[22:23], vcc_lo, v[4:5], v[2:3], v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f64_e32 v[14:15], v[10:11]
v_rcp_f64_e32 v[16:17], v[12:13]
s_waitcnt_depctr 0xfff
v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
v_div_scale_f64 v[18:19], s2, v[8:9], v[6:7], v[8:9]
v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[20:21], v[22:23], v[14:15]
v_mul_f64 v[24:25], v[18:19], v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[10:11], -v[10:11], v[20:21], v[22:23]
v_fma_f64 v[12:13], -v[12:13], v[24:25], v[18:19]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[20:21]
s_mov_b32 vcc_lo, s2
v_div_fmas_f64 v[12:13], v[12:13], v[16:17], v[24:25]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f64 v[2:3], v[10:11], v[2:3], v[4:5]
v_div_fixup_f64 v[4:5], v[12:13], v[6:7], v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_floor_f64_e32 v[2:3], v[2:3]
v_floor_f64_e32 v[4:5], v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_i32_f64_e32 v2, v[2:3]
v_cvt_i32_f64_e32 v5, v[4:5]
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0xbff00000
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_gt_i32_e32 vcc_lo, s6, v2
v_cmp_ge_i32_e64 s2, s7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_cmp_gt_i32 s3, -1
s_cselect_b32 s3, -1, 0
s_and_b32 s3, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_2
s_ashr_i32 s3, s5, 31
s_ashr_i32 s7, s4, 31
s_add_i32 s5, s5, s3
s_add_i32 s8, s4, s7
s_xor_b32 s3, s5, s3
s_xor_b32 s5, s8, s7
v_cvt_f32_u32_e32 v3, s3
v_cvt_f32_u32_e32 v4, s5
s_sub_i32 s7, 0, s3
s_sub_i32 s8, 0, s5
v_ashrrev_i32_e32 v8, 31, v1
v_rcp_iflag_f32_e32 v3, v3
v_rcp_iflag_f32_e32 v4, v4
v_ashrrev_i32_e32 v9, 31, v0
s_load_b64 s[10:11], s[0:1], 0x10
v_add_nc_u32_e32 v10, v1, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v11, v0, v9
v_xor_b32_e32 v10, v10, v8
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v3, 0x4f7ffffe, v3 :: v_dual_mul_f32 v4, 0x4f7ffffe, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v3, v3
v_cvt_u32_f32_e32 v4, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v6, s7, v3
v_mul_lo_u32 v7, s8, v4
s_load_b64 s[8:9], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v6, v3, v6
v_mul_hi_u32 v7, v4, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v3, v3, v6
v_xor_b32_e32 v6, v11, v9
v_add_nc_u32_e32 v4, v4, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v10, v3
v_mul_hi_u32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v3, v3, s3
v_mul_lo_u32 v4, v4, s5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v10, v3
v_sub_nc_u32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v6, s3, v3
v_cmp_le_u32_e32 vcc_lo, s3, v3
v_subrev_nc_u32_e32 v7, s5, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v3, v6, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s5, v4
v_subrev_nc_u32_e32 v6, s3, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, v4, v7, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s3, v3
v_subrev_nc_u32_e32 v7, s5, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v3, v6, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s5, v4
v_xor_b32_e32 v3, v3, v8
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, v4, v7, vcc_lo
v_sub_nc_u32_e32 v8, v3, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v4, v4, v9
v_sub_nc_u32_e32 v3, v4, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mad_u64_u32 v[6:7], null, v5, s6, v[2:3]
v_mad_u64_u32 v[4:5], null, v8, s4, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v7, 31, v6
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 3, v[6:7]
v_lshlrev_b64 v[4:5], 3, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s10, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
s_waitcnt vmcnt(0)
v_mul_f64 v[3:4], v[2:3], v[4:5]
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
s_mul_i32 s2, s4, s6
s_load_b64 s[0:1], s[0:1], 0x20
v_mad_u64_u32 v[5:6], null, v1, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[0:1], 3, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[3:4], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9kroneckerPdiiS_iiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 26
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9kroneckerPdiiS_iiS_, .Lfunc_end0-_Z9kroneckerPdiiS_iiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9kroneckerPdiiS_iiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9kroneckerPdiiS_iiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 26
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/**
* Various matrix utils using cuda
**/
/**
* Kronecker product of two matrices kernel
* input :
* a : first matrix
* nax, nay : matrix a dimensions
* b: second matrix
* nbx, nby : matrix b dimensions
* results : kronecker product of a and b
**/
__global__ void kronecker(double * a, int nax, int nay, double * b, int nbx, int nby, double * result){
// First we need to find our global threadID
int tPosX = blockIdx.x * blockDim.x + threadIdx.x;
int tPosY = blockIdx.y * blockDim.y + threadIdx.y;
int resSzx = nax * nbx;
//int resSzy = nay * nby;
int idxA = floor((tPosX) / (double)nbx);
int idyA = floor((tPosY) / (double)nby);
int idxB = (tPosX) % nbx;
int idyB = (tPosY) % nby;
// Check if the indices are within range
if (idxA >= nax || idyA > nay || idxB > nbx || idyB > nby)
{
result[tPosX + tPosY * resSzx] = -1;
return;
}
// Multiply appropriate elements
result[tPosX + tPosY * resSzx] = a[idyA * nax + idxA] * b[idyB * nbx + idxB];
} | .text
.file "kronecker.hip"
.globl _Z24__device_stub__kroneckerPdiiS_iiS_ # -- Begin function _Z24__device_stub__kroneckerPdiiS_iiS_
.p2align 4, 0x90
.type _Z24__device_stub__kroneckerPdiiS_iiS_,@function
_Z24__device_stub__kroneckerPdiiS_iiS_: # @_Z24__device_stub__kroneckerPdiiS_iiS_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 144(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9kroneckerPdiiS_iiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z24__device_stub__kroneckerPdiiS_iiS_, .Lfunc_end0-_Z24__device_stub__kroneckerPdiiS_iiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9kroneckerPdiiS_iiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9kroneckerPdiiS_iiS_,@object # @_Z9kroneckerPdiiS_iiS_
.section .rodata,"a",@progbits
.globl _Z9kroneckerPdiiS_iiS_
.p2align 3, 0x0
_Z9kroneckerPdiiS_iiS_:
.quad _Z24__device_stub__kroneckerPdiiS_iiS_
.size _Z9kroneckerPdiiS_iiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9kroneckerPdiiS_iiS_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__kroneckerPdiiS_iiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9kroneckerPdiiS_iiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9kroneckerPdiiS_iiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ I2F.F64 R4, c[0x0][0x178] ; /* 0x00005e0000047b12 */
/* 0x000e220000201c00 */
/*0020*/ S2R R10, SR_CTAID.X ; /* 0x00000000000a7919 */
/* 0x000e620000002500 */
/*0030*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fe200078e00ff */
/*0040*/ BSSY B0, 0x1f0 ; /* 0x000001a000007945 */
/* 0x000fe40003800000 */
/*0050*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e680000002100 */
/*0060*/ S2R R11, SR_CTAID.Y ; /* 0x00000000000b7919 */
/* 0x000ea80000002600 */
/*0070*/ S2R R14, SR_TID.Y ; /* 0x00000000000e7919 */
/* 0x000ea20000002200 */
/*0080*/ MUFU.RCP64H R3, R5 ; /* 0x0000000500037308 */
/* 0x001e220000001800 */
/*0090*/ IMAD R10, R10, c[0x0][0x0], R9 ; /* 0x000000000a0a7a24 */
/* 0x002fe200078e0209 */
/*00a0*/ DFMA R6, -R4, R2, 1 ; /* 0x3ff000000406742b */
/* 0x001e0c0000000102 */
/*00b0*/ DFMA R6, R6, R6, R6 ; /* 0x000000060606722b */
/* 0x001e0c0000000006 */
/*00c0*/ DFMA R2, R2, R6, R2 ; /* 0x000000060202722b */
/* 0x0010480000000002 */
/*00d0*/ I2F.F64 R6, R10 ; /* 0x0000000a00067312 */
/* 0x001e240000201c00 */
/*00e0*/ DFMA R8, -R4, R2, 1 ; /* 0x3ff000000408742b */
/* 0x002e4c0000000102 */
/*00f0*/ DFMA R2, R2, R8, R2 ; /* 0x000000080202722b */
/* 0x002e0c0000000002 */
/*0100*/ DMUL R8, R6, R2 ; /* 0x0000000206087228 */
/* 0x001e220000000000 */
/*0110*/ FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; /* 0x036000000700780b */
/* 0x000fca0003f2e200 */
/*0120*/ DFMA R12, -R4, R8, R6 ; /* 0x00000008040c722b */
/* 0x001e0c0000000106 */
/*0130*/ DFMA R2, R2, R12, R8 ; /* 0x0000000c0202722b */
/* 0x001e140000000008 */
/*0140*/ FFMA R0, RZ, R5, R3 ; /* 0x00000005ff007223 */
/* 0x001fca0000000003 */
/*0150*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fe20003f04200 */
/*0160*/ IMAD R0, R11, c[0x0][0x4], R14 ; /* 0x000001000b007a24 */
/* 0x004fd800078e020e */
/*0170*/ @P0 BRA P1, 0x1e0 ; /* 0x0000006000000947 */
/* 0x000fea0000800000 */
/*0180*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0006 */
/*0190*/ MOV R12, 0x1e0 ; /* 0x000001e0000c7802 */
/* 0x000fe20000000f00 */
/*01a0*/ IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0007 */
/*01b0*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0004 */
/*01c0*/ IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0005 */
/*01d0*/ CALL.REL.NOINC 0x800 ; /* 0x0000062000007944 */
/* 0x000fea0003c00000 */
/*01e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01f0*/ I2F.F64 R4, c[0x0][0x17c] ; /* 0x00005f0000047b12 */
/* 0x000e220000201c00 */
/*0200*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fe200078e00ff */
/*0210*/ BSSY B0, 0x3a0 ; /* 0x0000018000007945 */
/* 0x000fec0003800000 */
/*0220*/ F2I.F64.FLOOR R11, R2 ; /* 0x00000002000b7311 */
/* 0x000ff00000305100 */
/*0230*/ MUFU.RCP64H R7, R5 ; /* 0x0000000500077308 */
/* 0x001e240000001800 */
/*0240*/ DFMA R8, -R4, R6, 1 ; /* 0x3ff000000408742b */
/* 0x001e0c0000000106 */
/*0250*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*0260*/ DFMA R8, R6, R8, R6 ; /* 0x000000080608722b */
/* 0x0010a40000000006 */
/*0270*/ I2F.F64 R6, R0 ; /* 0x0000000000067312 */
/* 0x001e280000201c00 */
/*0280*/ DFMA R12, -R4, R8, 1 ; /* 0x3ff00000040c742b */
/* 0x004e8c0000000108 */
/*0290*/ DFMA R12, R8, R12, R8 ; /* 0x0000000c080c722b */
/* 0x004e0c0000000008 */
/*02a0*/ DMUL R8, R6, R12 ; /* 0x0000000c06087228 */
/* 0x001e220000000000 */
/*02b0*/ FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; /* 0x036000000700780b */
/* 0x000fca0003f2e200 */
/*02c0*/ DFMA R14, -R4, R8, R6 ; /* 0x00000008040e722b */
/* 0x001e0c0000000106 */
/*02d0*/ DFMA R8, R12, R14, R8 ; /* 0x0000000e0c08722b */
/* 0x001e140000000008 */
/*02e0*/ FFMA R12, RZ, R5, R9 ; /* 0x00000005ff0c7223 */
/* 0x001fca0000000009 */
/*02f0*/ FSETP.GT.AND P0, PT, |R12|, 1.469367938527859385e-39, PT ; /* 0x001000000c00780b */
/* 0x000fda0003f04200 */
/*0300*/ @P0 BRA P1, 0x390 ; /* 0x0000008000000947 */
/* 0x000fea0000800000 */
/*0310*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0006 */
/*0320*/ MOV R12, 0x370 ; /* 0x00000370000c7802 */
/* 0x000fe20000000f00 */
/*0330*/ IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0007 */
/*0340*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0004 */
/*0350*/ IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0005 */
/*0360*/ CALL.REL.NOINC 0x800 ; /* 0x0000049000007944 */
/* 0x002fea0003c00000 */
/*0370*/ IMAD.MOV.U32 R8, RZ, RZ, R2 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0002 */
/*0380*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0003 */
/*0390*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03a0*/ F2I.F64.FLOOR R4, R8 ; /* 0x0000000800047311 */
/* 0x000e220000305100 */
/*03b0*/ ULDC.64 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000a00 */
/*03c0*/ IMAD R3, R0, c[0x0][0x168], RZ ; /* 0x00005a0000037a24 */
/* 0x000fe200078e02ff */
/*03d0*/ ULOP3.LUT UR4, UR5, UR4, URZ, 0xfc, !UPT ; /* 0x0000000405047292 */
/* 0x000fe2000f8efc3f */
/*03e0*/ MOV R2, 0x8 ; /* 0x0000000800027802 */
/* 0x000fe20000000f00 */
/*03f0*/ BSSY B0, 0x7e0 ; /* 0x000003e000007945 */
/* 0x000fe20003800000 */
/*0400*/ IMAD R3, R3, c[0x0][0x178], R10 ; /* 0x00005e0003037a24 */
/* 0x000fc400078e020a */
/*0410*/ IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; /* 0x00000000ff067424 */
/* 0x000fe400078e00ff */
/*0420*/ IMAD.WIDE R2, R3, R2, c[0x0][0x180] ; /* 0x0000600003027625 */
/* 0x000fc800078e0202 */
/*0430*/ IMAD.MOV.U32 R7, RZ, RZ, -0x40100000 ; /* 0xbff00000ff077424 */
/* 0x000fe200078e00ff */
/*0440*/ ISETP.GT.AND P0, PT, R4, c[0x0][0x16c], PT ; /* 0x00005b0004007a0c */
/* 0x001fc80003f04270 */
/*0450*/ ISETP.GE.OR P0, PT, R11, c[0x0][0x168], P0 ; /* 0x00005a000b007a0c */
/* 0x000fc80000706670 */
/*0460*/ ISETP.GT.OR P0, PT, RZ, UR4, P0 ; /* 0x00000004ff007c0c */
/* 0x000fe20008704670 */
/*0470*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd80000000a00 */
/*0480*/ @P0 BRA 0x7d0 ; /* 0x0000034000000947 */
/* 0x000fea0003800000 */
/*0490*/ IABS R6, c[0x0][0x17c] ; /* 0x00005f0000067a13 */
/* 0x000fe40000000000 */
/*04a0*/ IABS R5, c[0x0][0x178] ; /* 0x00005e0000057a13 */
/* 0x000fe40000000000 */
/*04b0*/ I2F.RP R7, R6 ; /* 0x0000000600077306 */
/* 0x000e220000209400 */
/*04c0*/ ISETP.GE.AND P2, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f46270 */
/*04d0*/ ISETP.NE.AND P4, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fca0003f85270 */
/*04e0*/ I2F.RP R14, R5 ; /* 0x00000005000e7306 */
/* 0x000eb00000209400 */
/*04f0*/ MUFU.RCP R7, R7 ; /* 0x0000000700077308 */
/* 0x001e300000001000 */
/*0500*/ MUFU.RCP R14, R14 ; /* 0x0000000e000e7308 */
/* 0x004ea20000001000 */
/*0510*/ IADD3 R12, R7, 0xffffffe, RZ ; /* 0x0ffffffe070c7810 */
/* 0x001fc40007ffe0ff */
/*0520*/ IABS R7, R0 ; /* 0x0000000000077213 */
/* 0x000fca0000000000 */
/*0530*/ F2I.FTZ.U32.TRUNC.NTZ R13, R12 ; /* 0x0000000c000d7305 */
/* 0x0000e2000021f000 */
/*0540*/ IADD3 R8, R14, 0xffffffe, RZ ; /* 0x0ffffffe0e087810 */
/* 0x004fce0007ffe0ff */
/*0550*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x000522000021f000 */
/*0560*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x001fe400078e00ff */
/*0570*/ IMAD.MOV R15, RZ, RZ, -R13 ; /* 0x000000ffff0f7224 */
/* 0x008fe400078e0a0d */
/*0580*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x004fe400078e00ff */
/*0590*/ IMAD R15, R15, R6, RZ ; /* 0x000000060f0f7224 */
/* 0x000fe400078e02ff */
/*05a0*/ IMAD.MOV R16, RZ, RZ, -R9 ; /* 0x000000ffff107224 */
/* 0x012fe400078e0a09 */
/*05b0*/ IMAD.HI.U32 R12, R13, R15, R12 ; /* 0x0000000f0d0c7227 */
/* 0x000fe200078e000c */
/*05c0*/ IABS R13, R10 ; /* 0x0000000a000d7213 */
/* 0x000fc60000000000 */
/*05d0*/ IMAD R17, R16, R5, RZ ; /* 0x0000000510117224 */
/* 0x000fe400078e02ff */
/*05e0*/ IMAD.HI.U32 R12, R12, R7, RZ ; /* 0x000000070c0c7227 */
/* 0x000fc800078e00ff */
/*05f0*/ IMAD.HI.U32 R8, R9, R17, R8 ; /* 0x0000001109087227 */
/* 0x000fc800078e0008 */
/*0600*/ IMAD.MOV.U32 R9, RZ, RZ, R13 ; /* 0x000000ffff097224 */
/* 0x000fe400078e000d */
/*0610*/ IMAD.MOV R12, RZ, RZ, -R12 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0a0c */
/*0620*/ IMAD.HI.U32 R8, R8, R9, RZ ; /* 0x0000000908087227 */
/* 0x000fc800078e00ff */
/*0630*/ IMAD R7, R6, R12, R7 ; /* 0x0000000c06077224 */
/* 0x000fe400078e0207 */
/*0640*/ IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff087224 */
/* 0x000fc600078e0a08 */
/*0650*/ ISETP.GT.U32.AND P0, PT, R6, R7, PT ; /* 0x000000070600720c */
/* 0x000fe20003f04070 */
/*0660*/ IMAD R8, R5, R8, R9 ; /* 0x0000000805087224 */
/* 0x000fca00078e0209 */
/*0670*/ ISETP.GT.U32.AND P1, PT, R5, R8, PT ; /* 0x000000080500720c */
/* 0x000fce0003f24070 */
/*0680*/ @!P0 IMAD.IADD R7, R7, 0x1, -R6 ; /* 0x0000000107078824 */
/* 0x000fca00078e0a06 */
/*0690*/ ISETP.GT.U32.AND P3, PT, R6, R7, PT ; /* 0x000000070600720c */
/* 0x000fe40003f64070 */
/*06a0*/ @!P1 IADD3 R8, R8, -R5, RZ ; /* 0x8000000508089210 */
/* 0x000fe40007ffe0ff */
/*06b0*/ ISETP.GE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f26270 */
/*06c0*/ ISETP.GT.U32.AND P0, PT, R5, R8, PT ; /* 0x000000080500720c */
/* 0x000fce0003f04070 */
/*06d0*/ @!P3 IMAD.IADD R7, R7, 0x1, -R6 ; /* 0x000000010707b824 */
/* 0x000fe200078e0a06 */
/*06e0*/ ISETP.NE.AND P3, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fc60003f65270 */
/*06f0*/ @!P1 IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff079224 */
/* 0x000fe400078e0a07 */
/*0700*/ @!P0 IMAD.IADD R8, R8, 0x1, -R5 ; /* 0x0000000108088824 */
/* 0x000fe400078e0a05 */
/*0710*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fe400078e00ff */
/*0720*/ IMAD.MOV.U32 R0, RZ, RZ, R8 ; /* 0x000000ffff007224 */
/* 0x000fe400078e0008 */
/*0730*/ IMAD R8, R4, c[0x0][0x168], R11 ; /* 0x00005a0004087a24 */
/* 0x000fe400078e020b */
/*0740*/ @!P2 IMAD.MOV R0, RZ, RZ, -R0 ; /* 0x000000ffff00a224 */
/* 0x000fe200078e0a00 */
/*0750*/ @!P3 LOP3.LUT R7, RZ, c[0x0][0x17c], RZ, 0x33, !PT ; /* 0x00005f00ff07ba12 */
/* 0x000fe200078e33ff */
/*0760*/ IMAD.WIDE R8, R8, R5, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fe200078e0205 */
/*0770*/ @!P4 LOP3.LUT R0, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff00ca12 */
/* 0x000fca00078e33ff */
/*0780*/ IMAD R4, R7, c[0x0][0x178], R0 ; /* 0x00005e0007047a24 */
/* 0x000fe400078e0200 */
/*0790*/ LDG.E.64 R6, [R8.64] ; /* 0x0000000408067981 */
/* 0x000ea4000c1e1b00 */
/*07a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fcc00078e0205 */
/*07b0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1b00 */
/*07c0*/ DMUL R6, R4, R6 ; /* 0x0000000604067228 */
/* 0x00404c0000000000 */
/*07d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07e0*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x002fe2000c101b04 */
/*07f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0800*/ FSETP.GEU.AND P0, PT, |R7|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x040fe20003f0e200 */
/*0810*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0e7424 */
/* 0x000fe200078e00ff */
/*0820*/ LOP3.LUT R4, R7, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff07047812 */
/* 0x000fe200078ec0ff */
/*0830*/ IMAD.MOV.U32 R18, RZ, RZ, 0x1 ; /* 0x00000001ff127424 */
/* 0x000fe200078e00ff */
/*0840*/ FSETP.GEU.AND P2, PT, |R9|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000900780b */
/* 0x040fe20003f4e200 */
/*0850*/ BSSY B1, 0xda0 ; /* 0x0000054000017945 */
/* 0x000fe20003800000 */
/*0860*/ LOP3.LUT R5, R4, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000004057812 */
/* 0x000fe200078efcff */
/*0870*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0006 */
/*0880*/ LOP3.LUT R13, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000090d7812 */
/* 0x000fc400078ec0ff */
/*0890*/ LOP3.LUT R20, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007147812 */
/* 0x000fc600078ec0ff */
/*08a0*/ @!P0 DMUL R4, R6, 8.98846567431157953865e+307 ; /* 0x7fe0000006048828 */
/* 0x000e220000000000 */
/*08b0*/ ISETP.GE.U32.AND P1, PT, R13, R20, PT ; /* 0x000000140d00720c */
/* 0x000fc60003f26070 */
/*08c0*/ @!P2 LOP3.LUT R2, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000702a812 */
/* 0x000fe400078ec0ff */
/*08d0*/ MUFU.RCP64H R19, R5 ; /* 0x0000000500137308 */
/* 0x001e220000001800 */
/*08e0*/ SEL R3, R14.reuse, 0x63400000, !P1 ; /* 0x634000000e037807 */
/* 0x040fe40004800000 */
/*08f0*/ @!P2 ISETP.GE.U32.AND P3, PT, R13, R2, PT ; /* 0x000000020d00a20c */
/* 0x000fe20003f66070 */
/*0900*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0008 */
/*0910*/ LOP3.LUT R3, R3, 0x800fffff, R9, 0xf8, !PT ; /* 0x800fffff03037812 */
/* 0x000fe400078ef809 */
/*0920*/ @!P2 SEL R15, R14, 0x63400000, !P3 ; /* 0x634000000e0fa807 */
/* 0x000fe40005800000 */
/*0930*/ @!P2 MOV R16, RZ ; /* 0x000000ff0010a202 */
/* 0x000fc40000000f00 */
/*0940*/ @!P2 LOP3.LUT R15, R15, 0x80000000, R9, 0xf8, !PT ; /* 0x800000000f0fa812 */
/* 0x000fc800078ef809 */
/*0950*/ @!P2 LOP3.LUT R17, R15, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000f11a812 */
/* 0x000fe200078efcff */
/*0960*/ DFMA R22, R18, -R4, 1 ; /* 0x3ff000001216742b */
/* 0x001e220000000804 */
/*0970*/ IMAD.MOV.U32 R15, RZ, RZ, R13 ; /* 0x000000ffff0f7224 */
/* 0x000fc800078e000d */
/*0980*/ @!P2 DFMA R2, R2, 2, -R16 ; /* 0x400000000202a82b */
/* 0x000fc80000000810 */
/*0990*/ DFMA R22, R22, R22, R22 ; /* 0x000000161616722b */
/* 0x001e0c0000000016 */
/*09a0*/ DFMA R18, R18, R22, R18 ; /* 0x000000161212722b */
/* 0x0010620000000012 */
/*09b0*/ @!P2 LOP3.LUT R15, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000030fa812 */
/* 0x000fe200078ec0ff */
/*09c0*/ IMAD.MOV.U32 R22, RZ, RZ, R20 ; /* 0x000000ffff167224 */
/* 0x001fe200078e0014 */
/*09d0*/ @!P0 LOP3.LUT R22, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005168812 */
/* 0x000fe400078ec0ff */
/*09e0*/ IADD3 R20, R15, -0x1, RZ ; /* 0xffffffff0f147810 */
/* 0x000fe20007ffe0ff */
/*09f0*/ DFMA R16, R18, -R4, 1 ; /* 0x3ff000001210742b */
/* 0x002e220000000804 */
/*0a00*/ IADD3 R23, R22, -0x1, RZ ; /* 0xffffffff16177810 */
/* 0x000fe40007ffe0ff */
/*0a10*/ ISETP.GT.U32.AND P0, PT, R20, 0x7feffffe, PT ; /* 0x7feffffe1400780c */
/* 0x000fc60003f04070 */
/*0a20*/ DFMA R16, R18, R16, R18 ; /* 0x000000101210722b */
/* 0x001e220000000012 */
/*0a30*/ ISETP.GT.U32.OR P0, PT, R23, 0x7feffffe, P0 ; /* 0x7feffffe1700780c */
/* 0x000fca0000704470 */
/*0a40*/ DMUL R18, R16, R2 ; /* 0x0000000210127228 */
/* 0x001e0c0000000000 */
/*0a50*/ DFMA R20, R18, -R4, R2 ; /* 0x800000041214722b */
/* 0x001e0c0000000002 */
/*0a60*/ DFMA R16, R16, R20, R18 ; /* 0x000000141010722b */
/* 0x0010620000000012 */
/*0a70*/ @P0 BRA 0xc40 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0a80*/ LOP3.LUT R18, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007127812 */
/* 0x001fc800078ec0ff */
/*0a90*/ ISETP.GE.U32.AND P0, PT, R13.reuse, R18, PT ; /* 0x000000120d00720c */
/* 0x040fe20003f06070 */
/*0aa0*/ IMAD.IADD R8, R13, 0x1, -R18 ; /* 0x000000010d087824 */
/* 0x000fc600078e0a12 */
/*0ab0*/ SEL R13, R14, 0x63400000, !P0 ; /* 0x634000000e0d7807 */
/* 0x000fe40004000000 */
/*0ac0*/ IMNMX R8, R8, -0x46a00000, !PT ; /* 0xb960000008087817 */
/* 0x000fc80007800200 */
/*0ad0*/ IMNMX R8, R8, 0x46a00000, PT ; /* 0x46a0000008087817 */
/* 0x000fca0003800200 */
/*0ae0*/ IMAD.IADD R13, R8, 0x1, -R13 ; /* 0x00000001080d7824 */
/* 0x000fe400078e0a0d */
/*0af0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fc600078e00ff */
/*0b00*/ IADD3 R9, R13, 0x7fe00000, RZ ; /* 0x7fe000000d097810 */
/* 0x000fcc0007ffe0ff */
/*0b10*/ DMUL R18, R16, R8 ; /* 0x0000000810127228 */
/* 0x002e140000000000 */
/*0b20*/ FSETP.GTU.AND P0, PT, |R19|, 1.469367938527859385e-39, PT ; /* 0x001000001300780b */
/* 0x001fda0003f0c200 */
/*0b30*/ @P0 BRA 0xd90 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0b40*/ DFMA R2, R16, -R4, R2 ; /* 0x800000041002722b */
/* 0x000e220000000002 */
/*0b50*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fd200078e00ff */
/*0b60*/ FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720b */
/* 0x041fe40003f0d000 */
/*0b70*/ LOP3.LUT R7, R3, 0x80000000, R7, 0x48, !PT ; /* 0x8000000003077812 */
/* 0x000fc800078e4807 */
/*0b80*/ LOP3.LUT R9, R7, R9, RZ, 0xfc, !PT ; /* 0x0000000907097212 */
/* 0x000fce00078efcff */
/*0b90*/ @!P0 BRA 0xd90 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0ba0*/ IMAD.MOV R3, RZ, RZ, -R13 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a0d */
/*0bb0*/ DMUL.RP R8, R16, R8 ; /* 0x0000000810087228 */
/* 0x000e220000008000 */
/*0bc0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fcc00078e00ff */
/*0bd0*/ DFMA R2, R18, -R2, R16 ; /* 0x800000021202722b */
/* 0x000e460000000010 */
/*0be0*/ LOP3.LUT R7, R9, R7, RZ, 0x3c, !PT ; /* 0x0000000709077212 */
/* 0x001fc600078e3cff */
/*0bf0*/ IADD3 R2, -R13, -0x43300000, RZ ; /* 0xbcd000000d027810 */
/* 0x002fc80007ffe1ff */
/*0c00*/ FSETP.NEU.AND P0, PT, |R3|, R2, PT ; /* 0x000000020300720b */
/* 0x000fc80003f0d200 */
/*0c10*/ FSEL R18, R8, R18, !P0 ; /* 0x0000001208127208 */
/* 0x000fe40004000000 */
/*0c20*/ FSEL R19, R7, R19, !P0 ; /* 0x0000001307137208 */
/* 0x000fe20004000000 */
/*0c30*/ BRA 0xd90 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0c40*/ DSETP.NAN.AND P0, PT, R8, R8, PT ; /* 0x000000080800722a */
/* 0x000e9c0003f08000 */
/*0c50*/ @P0 BRA 0xd70 ; /* 0x0000011000000947 */
/* 0x004fea0003800000 */
/*0c60*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x000e9c0003f08000 */
/*0c70*/ @P0 BRA 0xd40 ; /* 0x000000c000000947 */
/* 0x004fea0003800000 */
/*0c80*/ ISETP.NE.AND P0, PT, R15, R22, PT ; /* 0x000000160f00720c */
/* 0x000fe20003f05270 */
/*0c90*/ IMAD.MOV.U32 R18, RZ, RZ, 0x0 ; /* 0x00000000ff127424 */
/* 0x001fe200078e00ff */
/*0ca0*/ MOV R19, 0xfff80000 ; /* 0xfff8000000137802 */
/* 0x000fd60000000f00 */
/*0cb0*/ @!P0 BRA 0xd90 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0cc0*/ ISETP.NE.AND P0, PT, R15, 0x7ff00000, PT ; /* 0x7ff000000f00780c */
/* 0x000fe40003f05270 */
/*0cd0*/ LOP3.LUT R19, R9, 0x80000000, R7, 0x48, !PT ; /* 0x8000000009137812 */
/* 0x000fe400078e4807 */
/*0ce0*/ ISETP.EQ.OR P0, PT, R22, RZ, !P0 ; /* 0x000000ff1600720c */
/* 0x000fda0004702670 */
/*0cf0*/ @P0 LOP3.LUT R2, R19, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000013020812 */
/* 0x000fe200078efcff */
/*0d00*/ @!P0 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff128224 */
/* 0x000fe400078e00ff */
/*0d10*/ @P0 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff120224 */
/* 0x000fe400078e00ff */
/*0d20*/ @P0 IMAD.MOV.U32 R19, RZ, RZ, R2 ; /* 0x000000ffff130224 */
/* 0x000fe200078e0002 */
/*0d30*/ BRA 0xd90 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0d40*/ LOP3.LUT R19, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000007137812 */
/* 0x001fe200078efcff */
/*0d50*/ IMAD.MOV.U32 R18, RZ, RZ, R6 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0006 */
/*0d60*/ BRA 0xd90 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0d70*/ LOP3.LUT R19, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000009137812 */
/* 0x001fe200078efcff */
/*0d80*/ IMAD.MOV.U32 R18, RZ, RZ, R8 ; /* 0x000000ffff127224 */
/* 0x000fe400078e0008 */
/*0d90*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0da0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x0 ; /* 0x00000000ff0d7424 */
/* 0x000fe400078e00ff */
/*0db0*/ IMAD.MOV.U32 R2, RZ, RZ, R18 ; /* 0x000000ffff027224 */
/* 0x000fc400078e0012 */
/*0dc0*/ IMAD.MOV.U32 R3, RZ, RZ, R19 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0013 */
/*0dd0*/ RET.REL.NODEC R12 0x0 ; /* 0xfffff2200c007950 */
/* 0x000fec0003c3ffff */
/*0de0*/ BRA 0xde0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9kroneckerPdiiS_iiS_
.globl _Z9kroneckerPdiiS_iiS_
.p2align 8
.type _Z9kroneckerPdiiS_iiS_,@function
_Z9kroneckerPdiiS_iiS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[4:5], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_load_b64 s[6:7], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cvt_f64_i32_e32 v[2:3], s4
v_cvt_f64_i32_e32 v[6:7], s5
s_or_b32 s3, s5, s4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cvt_f64_i32_e32 v[4:5], v0
v_cvt_f64_i32_e32 v[8:9], v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_scale_f64 v[10:11], null, v[2:3], v[2:3], v[4:5]
v_div_scale_f64 v[12:13], null, v[6:7], v[6:7], v[8:9]
v_div_scale_f64 v[22:23], vcc_lo, v[4:5], v[2:3], v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f64_e32 v[14:15], v[10:11]
v_rcp_f64_e32 v[16:17], v[12:13]
s_waitcnt_depctr 0xfff
v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
v_div_scale_f64 v[18:19], s2, v[8:9], v[6:7], v[8:9]
v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[20:21], v[22:23], v[14:15]
v_mul_f64 v[24:25], v[18:19], v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[10:11], -v[10:11], v[20:21], v[22:23]
v_fma_f64 v[12:13], -v[12:13], v[24:25], v[18:19]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[20:21]
s_mov_b32 vcc_lo, s2
v_div_fmas_f64 v[12:13], v[12:13], v[16:17], v[24:25]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f64 v[2:3], v[10:11], v[2:3], v[4:5]
v_div_fixup_f64 v[4:5], v[12:13], v[6:7], v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_floor_f64_e32 v[2:3], v[2:3]
v_floor_f64_e32 v[4:5], v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_i32_f64_e32 v2, v[2:3]
v_cvt_i32_f64_e32 v5, v[4:5]
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0xbff00000
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_gt_i32_e32 vcc_lo, s6, v2
v_cmp_ge_i32_e64 s2, s7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_cmp_gt_i32 s3, -1
s_cselect_b32 s3, -1, 0
s_and_b32 s3, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_2
s_ashr_i32 s3, s5, 31
s_ashr_i32 s7, s4, 31
s_add_i32 s5, s5, s3
s_add_i32 s8, s4, s7
s_xor_b32 s3, s5, s3
s_xor_b32 s5, s8, s7
v_cvt_f32_u32_e32 v3, s3
v_cvt_f32_u32_e32 v4, s5
s_sub_i32 s7, 0, s3
s_sub_i32 s8, 0, s5
v_ashrrev_i32_e32 v8, 31, v1
v_rcp_iflag_f32_e32 v3, v3
v_rcp_iflag_f32_e32 v4, v4
v_ashrrev_i32_e32 v9, 31, v0
s_load_b64 s[10:11], s[0:1], 0x10
v_add_nc_u32_e32 v10, v1, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v11, v0, v9
v_xor_b32_e32 v10, v10, v8
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v3, 0x4f7ffffe, v3 :: v_dual_mul_f32 v4, 0x4f7ffffe, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v3, v3
v_cvt_u32_f32_e32 v4, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v6, s7, v3
v_mul_lo_u32 v7, s8, v4
s_load_b64 s[8:9], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v6, v3, v6
v_mul_hi_u32 v7, v4, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v3, v3, v6
v_xor_b32_e32 v6, v11, v9
v_add_nc_u32_e32 v4, v4, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v10, v3
v_mul_hi_u32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v3, v3, s3
v_mul_lo_u32 v4, v4, s5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v10, v3
v_sub_nc_u32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v6, s3, v3
v_cmp_le_u32_e32 vcc_lo, s3, v3
v_subrev_nc_u32_e32 v7, s5, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v3, v6, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s5, v4
v_subrev_nc_u32_e32 v6, s3, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, v4, v7, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s3, v3
v_subrev_nc_u32_e32 v7, s5, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v3, v6, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s5, v4
v_xor_b32_e32 v3, v3, v8
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, v4, v7, vcc_lo
v_sub_nc_u32_e32 v8, v3, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v4, v4, v9
v_sub_nc_u32_e32 v3, v4, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mad_u64_u32 v[6:7], null, v5, s6, v[2:3]
v_mad_u64_u32 v[4:5], null, v8, s4, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v7, 31, v6
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 3, v[6:7]
v_lshlrev_b64 v[4:5], 3, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s10, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
s_waitcnt vmcnt(0)
v_mul_f64 v[3:4], v[2:3], v[4:5]
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
s_mul_i32 s2, s4, s6
s_load_b64 s[0:1], s[0:1], 0x20
v_mad_u64_u32 v[5:6], null, v1, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[0:1], 3, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[3:4], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9kroneckerPdiiS_iiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 26
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9kroneckerPdiiS_iiS_, .Lfunc_end0-_Z9kroneckerPdiiS_iiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9kroneckerPdiiS_iiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9kroneckerPdiiS_iiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 26
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000516ed_00000000-6_kronecker.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z9kroneckerPdiiS_iiS_PdiiS_iiS_
.type _Z36__device_stub__Z9kroneckerPdiiS_iiS_PdiiS_iiS_, @function
_Z36__device_stub__Z9kroneckerPdiiS_iiS_PdiiS_iiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movq %rcx, 24(%rsp)
movl %r8d, 20(%rsp)
movl %r9d, 16(%rsp)
movq 192(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9kroneckerPdiiS_iiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z9kroneckerPdiiS_iiS_PdiiS_iiS_, .-_Z36__device_stub__Z9kroneckerPdiiS_iiS_PdiiS_iiS_
.globl _Z9kroneckerPdiiS_iiS_
.type _Z9kroneckerPdiiS_iiS_, @function
_Z9kroneckerPdiiS_iiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z36__device_stub__Z9kroneckerPdiiS_iiS_PdiiS_iiS_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9kroneckerPdiiS_iiS_, .-_Z9kroneckerPdiiS_iiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9kroneckerPdiiS_iiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9kroneckerPdiiS_iiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kronecker.hip"
.globl _Z24__device_stub__kroneckerPdiiS_iiS_ # -- Begin function _Z24__device_stub__kroneckerPdiiS_iiS_
.p2align 4, 0x90
.type _Z24__device_stub__kroneckerPdiiS_iiS_,@function
_Z24__device_stub__kroneckerPdiiS_iiS_: # @_Z24__device_stub__kroneckerPdiiS_iiS_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 144(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9kroneckerPdiiS_iiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z24__device_stub__kroneckerPdiiS_iiS_, .Lfunc_end0-_Z24__device_stub__kroneckerPdiiS_iiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9kroneckerPdiiS_iiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9kroneckerPdiiS_iiS_,@object # @_Z9kroneckerPdiiS_iiS_
.section .rodata,"a",@progbits
.globl _Z9kroneckerPdiiS_iiS_
.p2align 3, 0x0
_Z9kroneckerPdiiS_iiS_:
.quad _Z24__device_stub__kroneckerPdiiS_iiS_
.size _Z9kroneckerPdiiS_iiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9kroneckerPdiiS_iiS_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__kroneckerPdiiS_iiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9kroneckerPdiiS_iiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. |
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <ctime>
#include <stdio.h>
#include "stdlib.h"
cudaError_t launchCuda(int *c, const int *a, const int *b, size_t size);
void algorithm(int *c, const int *a, const int *b, size_t size);
int initTime = 0;
__global__ void Bl1(int *X, int *A, int *B)
{
int i = threadIdx.x;
X[i] = 100500;
}
__global__ void Bl2(float **X, float **A, float *B)
{
int i = threadIdx.x;
// c[i] = a[i] + b[i];
}
__global__ void helpBl(float **X, float **A, float *B)
{
}
void TestFunc()
{
printf("blah-blah\n");
}
int cudaTest(const int &size, float &time, float *answer)
{
srand((unsigned)std::time(NULL));
time = initTime;
// answer = new float[size];
for (int i = 0; i < size; ++i)
answer[i] = rand();
return 0;
}
void cudaSetInitTime(int t)
{
initTime = t;
}
int cudaMain(const int &size, float &time, float *answer)
{
const int arraySize = 5;
const int *a = new int[size];
const int *b = new int[size];
int *c = new int[size];
// Add vectors in parallel.
cudaError_t cudaStatus = launchCuda(c, a, b, size);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "addWithCuda failed!");
return 1;
}
for (int i = 0; i < size; ++i)
{
answer[i] = c[i];
}
//printf("{1,2,3,4,5} + {10,20,30,40,50} = {%d,%d,%d,%d,%d}\n",
// c[0], c[1], c[2], c[3], c[4]);
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
cudaStatus = cudaDeviceReset();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceReset failed!");
return 1;
}
return 0;
}
bool loadInput(char *path, float **A, float *B, int &size)
{
return true;
}
void algorithm(int *c, int *a, int *b, size_t size)
{
Bl1<<<1, size>>>(c, a, b);
}
// Helper function for using CUDA to add vectors in parallel.
cudaError_t launchCuda(int *c, const int *a, const int *b, size_t size)
{
int *dev_a = 0;
int *dev_b = 0;
int *dev_c = 0;
cudaError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate GPU buffers for three vectors (two input, one output) .
cudaStatus = cudaMalloc((void**)&dev_c, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_a, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_b, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = cudaMemcpy(dev_a, a, size * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
cudaStatus = cudaMemcpy(dev_b, b, size * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
// Launch a kernel on the GPU with one thread for each element.
algorithm(dev_c, dev_a, dev_b, size);
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = cudaMemcpy(c, dev_c, size * sizeof(int), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
Error:
cudaFree(dev_c);
cudaFree(dev_a);
cudaFree(dev_b);
return cudaStatus;
} | code for sm_80
Function : _Z6helpBlPPfS0_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z3Bl2PPfS0_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z3Bl1PiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R5, 0x18894 ; /* 0x0001889400057802 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0050*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x001fca00078e0203 */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. |
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <ctime>
#include <stdio.h>
#include "stdlib.h"
cudaError_t launchCuda(int *c, const int *a, const int *b, size_t size);
void algorithm(int *c, const int *a, const int *b, size_t size);
int initTime = 0;
__global__ void Bl1(int *X, int *A, int *B)
{
int i = threadIdx.x;
X[i] = 100500;
}
__global__ void Bl2(float **X, float **A, float *B)
{
int i = threadIdx.x;
// c[i] = a[i] + b[i];
}
__global__ void helpBl(float **X, float **A, float *B)
{
}
void TestFunc()
{
printf("blah-blah\n");
}
int cudaTest(const int &size, float &time, float *answer)
{
srand((unsigned)std::time(NULL));
time = initTime;
// answer = new float[size];
for (int i = 0; i < size; ++i)
answer[i] = rand();
return 0;
}
void cudaSetInitTime(int t)
{
initTime = t;
}
int cudaMain(const int &size, float &time, float *answer)
{
const int arraySize = 5;
const int *a = new int[size];
const int *b = new int[size];
int *c = new int[size];
// Add vectors in parallel.
cudaError_t cudaStatus = launchCuda(c, a, b, size);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "addWithCuda failed!");
return 1;
}
for (int i = 0; i < size; ++i)
{
answer[i] = c[i];
}
//printf("{1,2,3,4,5} + {10,20,30,40,50} = {%d,%d,%d,%d,%d}\n",
// c[0], c[1], c[2], c[3], c[4]);
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
cudaStatus = cudaDeviceReset();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceReset failed!");
return 1;
}
return 0;
}
bool loadInput(char *path, float **A, float *B, int &size)
{
return true;
}
void algorithm(int *c, int *a, int *b, size_t size)
{
Bl1<<<1, size>>>(c, a, b);
}
// Helper function for using CUDA to add vectors in parallel.
cudaError_t launchCuda(int *c, const int *a, const int *b, size_t size)
{
int *dev_a = 0;
int *dev_b = 0;
int *dev_c = 0;
cudaError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate GPU buffers for three vectors (two input, one output) .
cudaStatus = cudaMalloc((void**)&dev_c, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_a, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_b, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = cudaMemcpy(dev_a, a, size * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
cudaStatus = cudaMemcpy(dev_b, b, size * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
// Launch a kernel on the GPU with one thread for each element.
algorithm(dev_c, dev_a, dev_b, size);
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = cudaMemcpy(c, dev_c, size * sizeof(int), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
Error:
cudaFree(dev_c);
cudaFree(dev_a);
cudaFree(dev_b);
return cudaStatus;
} | .file "tmpxft_000e6b86_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "blah-blah\n"
.text
.globl _Z8TestFuncv
.type _Z8TestFuncv, @function
_Z8TestFuncv:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z8TestFuncv, .-_Z8TestFuncv
.globl _Z8cudaTestRKiRfPf
.type _Z8cudaTestRKiRfPf, @function
_Z8cudaTestRKiRfPf:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbp
movq %rsi, %rbx
movq %rdx, %r12
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl initTime(%rip), %xmm0
movss %xmm0, (%rbx)
cmpl $0, 0(%rbp)
jle .L6
movl $0, %ebx
.L7:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%r12,%rbx,4)
addq $1, %rbx
cmpl %ebx, 0(%rbp)
jg .L7
.L6:
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z8cudaTestRKiRfPf, .-_Z8cudaTestRKiRfPf
.globl _Z15cudaSetInitTimei
.type _Z15cudaSetInitTimei, @function
_Z15cudaSetInitTimei:
.LFB2059:
.cfi_startproc
endbr64
movl %edi, initTime(%rip)
ret
.cfi_endproc
.LFE2059:
.size _Z15cudaSetInitTimei, .-_Z15cudaSetInitTimei
.globl _Z9loadInputPcPPfS0_Ri
.type _Z9loadInputPcPPfS0_Ri, @function
_Z9loadInputPcPPfS0_Ri:
.LFB2061:
.cfi_startproc
endbr64
movl $1, %eax
ret
.cfi_endproc
.LFE2061:
.size _Z9loadInputPcPPfS0_Ri, .-_Z9loadInputPcPPfS0_Ri
.globl _Z26__device_stub__Z3Bl1PiS_S_PiS_S_
.type _Z26__device_stub__Z3Bl1PiS_S_PiS_S_, @function
_Z26__device_stub__Z3Bl1PiS_S_PiS_S_:
.LFB2088:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3Bl1PiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z26__device_stub__Z3Bl1PiS_S_PiS_S_, .-_Z26__device_stub__Z3Bl1PiS_S_PiS_S_
.globl _Z3Bl1PiS_S_
.type _Z3Bl1PiS_S_, @function
_Z3Bl1PiS_S_:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3Bl1PiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z3Bl1PiS_S_, .-_Z3Bl1PiS_S_
.globl _Z9algorithmPiS_S_m
.type _Z9algorithmPiS_S_m, @function
_Z9algorithmPiS_S_m:
.LFB2062:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbx
movq %rsi, %rbp
movq %rdx, %r12
movl %ecx, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L20:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z26__device_stub__Z3Bl1PiS_S_PiS_S_
jmp .L20
.cfi_endproc
.LFE2062:
.size _Z9algorithmPiS_S_m, .-_Z9algorithmPiS_S_m
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?"
.section .rodata.str1.1
.LC2:
.string "cudaMalloc failed!"
.LC3:
.string "cudaMemcpy failed!"
.section .rodata.str1.8
.align 8
.LC4:
.string "cudaDeviceSynchronize returned error code %d after launching addKernel!\n"
.text
.globl _Z10launchCudaPiPKiS1_m
.type _Z10launchCudaPiPKiS1_m, @function
_Z10launchCudaPiPKiS1_m:
.LFB2063:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r14
movq %rsi, %r12
movq %rdx, %r13
movq %rcx, %rbp
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L35
leaq 0(,%rbp,4), %r15
leaq 16(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L36
movq %rsp, %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L37
leaq 8(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L38
movl $1, %ecx
movq %r15, %rdx
movq %r12, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L39
movl $1, %ecx
movq %r15, %rdx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L40
movq %rbp, %rcx
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movq 16(%rsp), %rdi
call _Z9algorithmPiS_S_m
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L41
movl $2, %ecx
movq %r15, %rdx
movq 16(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
je .L26
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L26
.L35:
movl %eax, %ebx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L26:
movq 16(%rsp), %rdi
call cudaFree@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L42
movl %ebx, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L26
.L37:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L26
.L38:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L26
.L39:
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L26
.L40:
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L26
.L41:
movl %eax, %ecx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L26
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size _Z10launchCudaPiPKiS1_m, .-_Z10launchCudaPiPKiS1_m
.section .rodata.str1.1
.LC5:
.string "addWithCuda failed!"
.LC6:
.string "cudaDeviceReset failed!"
.text
.globl _Z8cudaMainRKiRfPf
.type _Z8cudaMainRKiRfPf, @function
_Z8cudaMainRKiRfPf:
.LFB2060:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %rbx
movslq (%rdi), %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L44
movq %rdx, %r12
salq $2, %rdi
call _Znam@PLT
movq %rax, %r13
movslq (%rbx), %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L60
salq $2, %rdi
call _Znam@PLT
movq %rax, %r14
movslq (%rbx), %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L61
salq $2, %rdi
call _Znam@PLT
movq %rax, %rbp
movslq (%rbx), %rcx
movq %r14, %rdx
movq %r13, %rsi
movq %rax, %rdi
call _Z10launchCudaPiPKiS1_m
testl %eax, %eax
jne .L49
movl $0, %eax
cmpl $0, (%rbx)
jle .L51
.L50:
pxor %xmm0, %xmm0
cvtsi2ssl 0(%rbp,%rax,4), %xmm0
movss %xmm0, (%r12,%rax,4)
addq $1, %rax
cmpl %eax, (%rbx)
jg .L50
.L51:
call cudaDeviceReset@PLT
movl %eax, %edx
movl $0, %eax
testl %edx, %edx
jne .L62
.L43:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
call __cxa_throw_bad_array_new_length@PLT
.L60:
call __cxa_throw_bad_array_new_length@PLT
.L61:
call __cxa_throw_bad_array_new_length@PLT
.L49:
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L43
.L62:
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %eax
jmp .L43
.cfi_endproc
.LFE2060:
.size _Z8cudaMainRKiRfPf, .-_Z8cudaMainRKiRfPf
.globl _Z28__device_stub__Z3Bl2PPfS0_S_PPfS0_S_
.type _Z28__device_stub__Z3Bl2PPfS0_S_PPfS0_S_, @function
_Z28__device_stub__Z3Bl2PPfS0_S_PPfS0_S_:
.LFB2090:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L67
.L63:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L68
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L67:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3Bl2PPfS0_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L63
.L68:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z28__device_stub__Z3Bl2PPfS0_S_PPfS0_S_, .-_Z28__device_stub__Z3Bl2PPfS0_S_PPfS0_S_
.globl _Z3Bl2PPfS0_S_
.type _Z3Bl2PPfS0_S_, @function
_Z3Bl2PPfS0_S_:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z3Bl2PPfS0_S_PPfS0_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z3Bl2PPfS0_S_, .-_Z3Bl2PPfS0_S_
.globl _Z31__device_stub__Z6helpBlPPfS0_S_PPfS0_S_
.type _Z31__device_stub__Z6helpBlPPfS0_S_PPfS0_S_, @function
_Z31__device_stub__Z6helpBlPPfS0_S_PPfS0_S_:
.LFB2092:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L75
.L71:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L76
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L75:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6helpBlPPfS0_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L71
.L76:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2092:
.size _Z31__device_stub__Z6helpBlPPfS0_S_PPfS0_S_, .-_Z31__device_stub__Z6helpBlPPfS0_S_PPfS0_S_
.globl _Z6helpBlPPfS0_S_
.type _Z6helpBlPPfS0_S_, @function
_Z6helpBlPPfS0_S_:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z6helpBlPPfS0_S_PPfS0_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _Z6helpBlPPfS0_S_, .-_Z6helpBlPPfS0_S_
.section .rodata.str1.1
.LC7:
.string "_Z6helpBlPPfS0_S_"
.LC8:
.string "_Z3Bl2PPfS0_S_"
.LC9:
.string "_Z3Bl1PiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2095:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z6helpBlPPfS0_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z3Bl2PPfS0_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z3Bl1PiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2095:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl initTime
.bss
.align 4
.type initTime, @object
.size initTime, 4
initTime:
.zero 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. |
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <ctime>
#include <stdio.h>
#include "stdlib.h"
cudaError_t launchCuda(int *c, const int *a, const int *b, size_t size);
void algorithm(int *c, const int *a, const int *b, size_t size);
int initTime = 0;
__global__ void Bl1(int *X, int *A, int *B)
{
int i = threadIdx.x;
X[i] = 100500;
}
__global__ void Bl2(float **X, float **A, float *B)
{
int i = threadIdx.x;
// c[i] = a[i] + b[i];
}
__global__ void helpBl(float **X, float **A, float *B)
{
}
void TestFunc()
{
printf("blah-blah\n");
}
int cudaTest(const int &size, float &time, float *answer)
{
srand((unsigned)std::time(NULL));
time = initTime;
// answer = new float[size];
for (int i = 0; i < size; ++i)
answer[i] = rand();
return 0;
}
void cudaSetInitTime(int t)
{
initTime = t;
}
int cudaMain(const int &size, float &time, float *answer)
{
const int arraySize = 5;
const int *a = new int[size];
const int *b = new int[size];
int *c = new int[size];
// Add vectors in parallel.
cudaError_t cudaStatus = launchCuda(c, a, b, size);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "addWithCuda failed!");
return 1;
}
for (int i = 0; i < size; ++i)
{
answer[i] = c[i];
}
//printf("{1,2,3,4,5} + {10,20,30,40,50} = {%d,%d,%d,%d,%d}\n",
// c[0], c[1], c[2], c[3], c[4]);
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
cudaStatus = cudaDeviceReset();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceReset failed!");
return 1;
}
return 0;
}
bool loadInput(char *path, float **A, float *B, int &size)
{
return true;
}
void algorithm(int *c, int *a, int *b, size_t size)
{
Bl1<<<1, size>>>(c, a, b);
}
// Helper function for using CUDA to add vectors in parallel.
cudaError_t launchCuda(int *c, const int *a, const int *b, size_t size)
{
int *dev_a = 0;
int *dev_b = 0;
int *dev_c = 0;
cudaError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate GPU buffers for three vectors (two input, one output) .
cudaStatus = cudaMalloc((void**)&dev_c, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_a, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_b, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = cudaMemcpy(dev_a, a, size * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
cudaStatus = cudaMemcpy(dev_b, b, size * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
// Launch a kernel on the GPU with one thread for each element.
algorithm(dev_c, dev_a, dev_b, size);
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = cudaMemcpy(c, dev_c, size * sizeof(int), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
Error:
cudaFree(dev_c);
cudaFree(dev_a);
cudaFree(dev_b);
return cudaStatus;
} |
#include "hip/hip_runtime.h"
#include <ctime>
#include <stdio.h>
#include "stdlib.h"
hipError_t launchCuda(int *c, const int *a, const int *b, size_t size);
void algorithm(int *c, const int *a, const int *b, size_t size);
int initTime = 0;
__global__ void Bl1(int *X, int *A, int *B)
{
int i = threadIdx.x;
X[i] = 100500;
}
__global__ void Bl2(float **X, float **A, float *B)
{
int i = threadIdx.x;
// c[i] = a[i] + b[i];
}
__global__ void helpBl(float **X, float **A, float *B)
{
}
void TestFunc()
{
printf("blah-blah\n");
}
int cudaTest(const int &size, float &time, float *answer)
{
srand((unsigned)std::time(NULL));
time = initTime;
// answer = new float[size];
for (int i = 0; i < size; ++i)
answer[i] = rand();
return 0;
}
void cudaSetInitTime(int t)
{
initTime = t;
}
int cudaMain(const int &size, float &time, float *answer)
{
const int arraySize = 5;
const int *a = new int[size];
const int *b = new int[size];
int *c = new int[size];
// Add vectors in parallel.
hipError_t cudaStatus = launchCuda(c, a, b, size);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "addWithCuda failed!");
return 1;
}
for (int i = 0; i < size; ++i)
{
answer[i] = c[i];
}
//printf("{1,2,3,4,5} + {10,20,30,40,50} = {%d,%d,%d,%d,%d}\n",
// c[0], c[1], c[2], c[3], c[4]);
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
cudaStatus = hipDeviceReset();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceReset failed!");
return 1;
}
return 0;
}
bool loadInput(char *path, float **A, float *B, int &size)
{
return true;
}
void algorithm(int *c, int *a, int *b, size_t size)
{
Bl1<<<1, size>>>(c, a, b);
}
// Helper function for using CUDA to add vectors in parallel.
hipError_t launchCuda(int *c, const int *a, const int *b, size_t size)
{
int *dev_a = 0;
int *dev_b = 0;
int *dev_c = 0;
hipError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate GPU buffers for three vectors (two input, one output) .
cudaStatus = hipMalloc((void**)&dev_c, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_a, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_b, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = hipMemcpy(dev_a, a, size * sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
cudaStatus = hipMemcpy(dev_b, b, size * sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
// Launch a kernel on the GPU with one thread for each element.
algorithm(dev_c, dev_a, dev_b, size);
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = hipMemcpy(c, dev_c, size * sizeof(int), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
Error:
hipFree(dev_c);
hipFree(dev_a);
hipFree(dev_b);
return cudaStatus;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. |
#include "hip/hip_runtime.h"
#include <ctime>
#include <stdio.h>
#include "stdlib.h"
hipError_t launchCuda(int *c, const int *a, const int *b, size_t size);
void algorithm(int *c, const int *a, const int *b, size_t size);
int initTime = 0;
__global__ void Bl1(int *X, int *A, int *B)
{
int i = threadIdx.x;
X[i] = 100500;
}
__global__ void Bl2(float **X, float **A, float *B)
{
int i = threadIdx.x;
// c[i] = a[i] + b[i];
}
__global__ void helpBl(float **X, float **A, float *B)
{
}
void TestFunc()
{
printf("blah-blah\n");
}
int cudaTest(const int &size, float &time, float *answer)
{
srand((unsigned)std::time(NULL));
time = initTime;
// answer = new float[size];
for (int i = 0; i < size; ++i)
answer[i] = rand();
return 0;
}
void cudaSetInitTime(int t)
{
initTime = t;
}
int cudaMain(const int &size, float &time, float *answer)
{
const int arraySize = 5;
const int *a = new int[size];
const int *b = new int[size];
int *c = new int[size];
// Add vectors in parallel.
hipError_t cudaStatus = launchCuda(c, a, b, size);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "addWithCuda failed!");
return 1;
}
for (int i = 0; i < size; ++i)
{
answer[i] = c[i];
}
//printf("{1,2,3,4,5} + {10,20,30,40,50} = {%d,%d,%d,%d,%d}\n",
// c[0], c[1], c[2], c[3], c[4]);
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
cudaStatus = hipDeviceReset();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceReset failed!");
return 1;
}
return 0;
}
bool loadInput(char *path, float **A, float *B, int &size)
{
return true;
}
void algorithm(int *c, int *a, int *b, size_t size)
{
Bl1<<<1, size>>>(c, a, b);
}
// Helper function for using CUDA to add vectors in parallel.
hipError_t launchCuda(int *c, const int *a, const int *b, size_t size)
{
int *dev_a = 0;
int *dev_b = 0;
int *dev_c = 0;
hipError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate GPU buffers for three vectors (two input, one output) .
cudaStatus = hipMalloc((void**)&dev_c, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_a, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_b, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = hipMemcpy(dev_a, a, size * sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
cudaStatus = hipMemcpy(dev_b, b, size * sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
// Launch a kernel on the GPU with one thread for each element.
algorithm(dev_c, dev_a, dev_b, size);
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = hipMemcpy(c, dev_c, size * sizeof(int), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
Error:
hipFree(dev_c);
hipFree(dev_a);
hipFree(dev_b);
return cudaStatus;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3Bl1PiS_S_
.globl _Z3Bl1PiS_S_
.p2align 8
.type _Z3Bl1PiS_S_,@function
_Z3Bl1PiS_S_:
s_load_b64 s[0:1], s[0:1], 0x0
v_dual_mov_b32 v1, 0x18894 :: v_dual_lshlrev_b32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3Bl1PiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3Bl1PiS_S_, .Lfunc_end0-_Z3Bl1PiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3Bl2PPfS0_S_
.globl _Z3Bl2PPfS0_S_
.p2align 8
.type _Z3Bl2PPfS0_S_,@function
_Z3Bl2PPfS0_S_:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3Bl2PPfS0_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z3Bl2PPfS0_S_, .Lfunc_end1-_Z3Bl2PPfS0_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z6helpBlPPfS0_S_
.globl _Z6helpBlPPfS0_S_
.p2align 8
.type _Z6helpBlPPfS0_S_,@function
_Z6helpBlPPfS0_S_:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6helpBlPPfS0_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z6helpBlPPfS0_S_, .Lfunc_end2-_Z6helpBlPPfS0_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3Bl1PiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z3Bl1PiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3Bl2PPfS0_S_
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z3Bl2PPfS0_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6helpBlPPfS0_S_
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z6helpBlPPfS0_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. |
#include "hip/hip_runtime.h"
#include <ctime>
#include <stdio.h>
#include "stdlib.h"
hipError_t launchCuda(int *c, const int *a, const int *b, size_t size);
void algorithm(int *c, const int *a, const int *b, size_t size);
int initTime = 0;
__global__ void Bl1(int *X, int *A, int *B)
{
int i = threadIdx.x;
X[i] = 100500;
}
__global__ void Bl2(float **X, float **A, float *B)
{
int i = threadIdx.x;
// c[i] = a[i] + b[i];
}
__global__ void helpBl(float **X, float **A, float *B)
{
}
void TestFunc()
{
printf("blah-blah\n");
}
int cudaTest(const int &size, float &time, float *answer)
{
srand((unsigned)std::time(NULL));
time = initTime;
// answer = new float[size];
for (int i = 0; i < size; ++i)
answer[i] = rand();
return 0;
}
void cudaSetInitTime(int t)
{
initTime = t;
}
int cudaMain(const int &size, float &time, float *answer)
{
const int arraySize = 5;
const int *a = new int[size];
const int *b = new int[size];
int *c = new int[size];
// Add vectors in parallel.
hipError_t cudaStatus = launchCuda(c, a, b, size);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "addWithCuda failed!");
return 1;
}
for (int i = 0; i < size; ++i)
{
answer[i] = c[i];
}
//printf("{1,2,3,4,5} + {10,20,30,40,50} = {%d,%d,%d,%d,%d}\n",
// c[0], c[1], c[2], c[3], c[4]);
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
cudaStatus = hipDeviceReset();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceReset failed!");
return 1;
}
return 0;
}
bool loadInput(char *path, float **A, float *B, int &size)
{
return true;
}
void algorithm(int *c, int *a, int *b, size_t size)
{
Bl1<<<1, size>>>(c, a, b);
}
// Helper function for using CUDA to add vectors in parallel.
hipError_t launchCuda(int *c, const int *a, const int *b, size_t size)
{
int *dev_a = 0;
int *dev_b = 0;
int *dev_c = 0;
hipError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate GPU buffers for three vectors (two input, one output) .
cudaStatus = hipMalloc((void**)&dev_c, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_a, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_b, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = hipMemcpy(dev_a, a, size * sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
cudaStatus = hipMemcpy(dev_b, b, size * sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
// Launch a kernel on the GPU with one thread for each element.
algorithm(dev_c, dev_a, dev_b, size);
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = hipMemcpy(c, dev_c, size * sizeof(int), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
Error:
hipFree(dev_c);
hipFree(dev_a);
hipFree(dev_b);
return cudaStatus;
} | .text
.file "kernel.hip"
.globl _Z18__device_stub__Bl1PiS_S_ # -- Begin function _Z18__device_stub__Bl1PiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__Bl1PiS_S_,@function
_Z18__device_stub__Bl1PiS_S_: # @_Z18__device_stub__Bl1PiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3Bl1PiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__Bl1PiS_S_, .Lfunc_end0-_Z18__device_stub__Bl1PiS_S_
.cfi_endproc
# -- End function
.globl _Z18__device_stub__Bl2PPfS0_S_ # -- Begin function _Z18__device_stub__Bl2PPfS0_S_
.p2align 4, 0x90
.type _Z18__device_stub__Bl2PPfS0_S_,@function
_Z18__device_stub__Bl2PPfS0_S_: # @_Z18__device_stub__Bl2PPfS0_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3Bl2PPfS0_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z18__device_stub__Bl2PPfS0_S_, .Lfunc_end1-_Z18__device_stub__Bl2PPfS0_S_
.cfi_endproc
# -- End function
.globl _Z21__device_stub__helpBlPPfS0_S_ # -- Begin function _Z21__device_stub__helpBlPPfS0_S_
.p2align 4, 0x90
.type _Z21__device_stub__helpBlPPfS0_S_,@function
_Z21__device_stub__helpBlPPfS0_S_: # @_Z21__device_stub__helpBlPPfS0_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6helpBlPPfS0_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z21__device_stub__helpBlPPfS0_S_, .Lfunc_end2-_Z21__device_stub__helpBlPPfS0_S_
.cfi_endproc
# -- End function
.globl _Z8TestFuncv # -- Begin function _Z8TestFuncv
.p2align 4, 0x90
.type _Z8TestFuncv,@function
_Z8TestFuncv: # @_Z8TestFuncv
.cfi_startproc
# %bb.0:
movl $.Lstr, %edi
jmp puts@PLT # TAILCALL
.Lfunc_end3:
.size _Z8TestFuncv, .Lfunc_end3-_Z8TestFuncv
.cfi_endproc
# -- End function
.globl _Z8cudaTestRKiRfPf # -- Begin function _Z8cudaTestRKiRfPf
.p2align 4, 0x90
.type _Z8cudaTestRKiRfPf,@function
_Z8cudaTestRKiRfPf: # @_Z8cudaTestRKiRfPf
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %rbx
movq %rsi, %r15
movq %rdi, %r14
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
cvtsi2ssl initTime(%rip), %xmm0
movss %xmm0, (%r15)
cmpl $0, (%r14)
jle .LBB4_3
# %bb.1: # %.lr.ph.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
movslq (%r14), %rax
cmpq %rax, %r15
jl .LBB4_2
.LBB4_3: # %._crit_edge
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z8cudaTestRKiRfPf, .Lfunc_end4-_Z8cudaTestRKiRfPf
.cfi_endproc
# -- End function
.globl _Z15cudaSetInitTimei # -- Begin function _Z15cudaSetInitTimei
.p2align 4, 0x90
.type _Z15cudaSetInitTimei,@function
_Z15cudaSetInitTimei: # @_Z15cudaSetInitTimei
.cfi_startproc
# %bb.0:
movl %edi, initTime(%rip)
retq
.Lfunc_end5:
.size _Z15cudaSetInitTimei, .Lfunc_end5-_Z15cudaSetInitTimei
.cfi_endproc
# -- End function
.globl _Z8cudaMainRKiRfPf # -- Begin function _Z8cudaMainRKiRfPf
.p2align 4, 0x90
.type _Z8cudaMainRKiRfPf,@function
_Z8cudaMainRKiRfPf: # @_Z8cudaMainRKiRfPf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %rbx
movq %rdi, %r15
movslq (%rdi), %r12
leaq (,%r12,4), %rax
testq %r12, %r12
movq $-1, %r14
cmovnsq %rax, %r14
movq %r14, %rdi
callq _Znam
movq %rax, %r13
movq %r14, %rdi
callq _Znam
movq %rax, %rbp
movq %r14, %rdi
callq _Znam
movq %rax, %r14
movq %rax, %rdi
movq %r13, %rsi
movq %rbp, %rdx
movq %r12, %rcx
callq _Z10launchCudaPiPKiS1_m
testl %eax, %eax
jne .LBB6_8
# %bb.1: # %.preheader
movl (%r15), %eax
testl %eax, %eax
jle .LBB6_4
# %bb.2: # %.lr.ph.preheader
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB6_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ssl (%r14,%rcx,4), %xmm0
movss %xmm0, (%rbx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB6_3
.LBB6_4: # %._crit_edge
callq hipDeviceReset
movl %eax, %ecx
xorl %eax, %eax
testl %ecx, %ecx
jne .LBB6_5
.LBB6_7:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB6_8:
.cfi_def_cfa_offset 64
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $19, %esi
jmp .LBB6_6
.LBB6_5:
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $22, %esi
.LBB6_6:
movl $1, %edx
callq fwrite@PLT
movl $1, %eax
jmp .LBB6_7
.Lfunc_end6:
.size _Z8cudaMainRKiRfPf, .Lfunc_end6-_Z8cudaMainRKiRfPf
.cfi_endproc
# -- End function
.globl _Z10launchCudaPiPKiS1_m # -- Begin function _Z10launchCudaPiPKiS1_m
.p2align 4, 0x90
.type _Z10launchCudaPiPKiS1_m,@function
_Z10launchCudaPiPKiS1_m: # @_Z10launchCudaPiPKiS1_m
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $32, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rcx, %r14
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %rbx
movq $0, 24(%rsp)
movq $0, 16(%rsp)
movq $0, 8(%rsp)
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB7_15
# %bb.1:
leaq (,%r14,4), %r15
leaq 8(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB7_9
# %bb.2:
leaq 24(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB7_9
# %bb.3:
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB7_9
# %bb.4:
movq 24(%rsp), %rdi
movq %r13, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB7_10
# %bb.5:
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB7_10
# %bb.6:
movq 8(%rsp), %rdi
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
movq %r14, %rcx
callq _Z9algorithmPiS_S_m
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB7_16
# %bb.7:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
testl %eax, %eax
je .LBB7_14
# %bb.8:
movq stderr(%rip), %rcx
movl $.L.str.5, %edi
movl $17, %esi
movl $1, %edx
movl %eax, %ebx
jmp .LBB7_13
.LBB7_9:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.4, %edi
jmp .LBB7_11
.LBB7_10:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.5, %edi
.LBB7_11:
movl $17, %esi
.LBB7_12:
movl $1, %edx
.LBB7_13:
callq fwrite@PLT
.LBB7_14:
movq 8(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movl %ebx, %eax
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB7_15:
.cfi_def_cfa_offset 80
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $63, %esi
jmp .LBB7_12
.LBB7_16:
movq stderr(%rip), %rdi
movl $.L.str.6, %esi
movl %eax, %ebx
movl %eax, %edx
xorl %eax, %eax
callq fprintf
jmp .LBB7_14
.Lfunc_end7:
.size _Z10launchCudaPiPKiS1_m, .Lfunc_end7-_Z10launchCudaPiPKiS1_m
.cfi_endproc
# -- End function
.globl _Z9loadInputPcPPfS0_Ri # -- Begin function _Z9loadInputPcPPfS0_Ri
.p2align 4, 0x90
.type _Z9loadInputPcPPfS0_Ri,@function
_Z9loadInputPcPPfS0_Ri: # @_Z9loadInputPcPPfS0_Ri
.cfi_startproc
# %bb.0:
movb $1, %al
retq
.Lfunc_end8:
.size _Z9loadInputPcPPfS0_Ri, .Lfunc_end8-_Z9loadInputPcPPfS0_Ri
.cfi_endproc
# -- End function
.globl _Z9algorithmPiS_S_m # -- Begin function _Z9algorithmPiS_S_m
.p2align 4, 0x90
.type _Z9algorithmPiS_S_m,@function
_Z9algorithmPiS_S_m: # @_Z9algorithmPiS_S_m
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movl %ecx, %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB9_2
# %bb.1:
movq %r15, 72(%rsp)
movq %r14, 64(%rsp)
movq %rbx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3Bl1PiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB9_2:
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end9:
.size _Z9algorithmPiS_S_m, .Lfunc_end9-_Z9algorithmPiS_S_m
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB10_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB10_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3Bl1PiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3Bl2PPfS0_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6helpBlPPfS0_S_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end10:
.size __hip_module_ctor, .Lfunc_end10-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB11_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB11_2:
retq
.Lfunc_end11:
.size __hip_module_dtor, .Lfunc_end11-__hip_module_dtor
.cfi_endproc
# -- End function
.type initTime,@object # @initTime
.bss
.globl initTime
.p2align 2, 0x0
initTime:
.long 0 # 0x0
.size initTime, 4
.type _Z3Bl1PiS_S_,@object # @_Z3Bl1PiS_S_
.section .rodata,"a",@progbits
.globl _Z3Bl1PiS_S_
.p2align 3, 0x0
_Z3Bl1PiS_S_:
.quad _Z18__device_stub__Bl1PiS_S_
.size _Z3Bl1PiS_S_, 8
.type _Z3Bl2PPfS0_S_,@object # @_Z3Bl2PPfS0_S_
.globl _Z3Bl2PPfS0_S_
.p2align 3, 0x0
_Z3Bl2PPfS0_S_:
.quad _Z18__device_stub__Bl2PPfS0_S_
.size _Z3Bl2PPfS0_S_, 8
.type _Z6helpBlPPfS0_S_,@object # @_Z6helpBlPPfS0_S_
.globl _Z6helpBlPPfS0_S_
.p2align 3, 0x0
_Z6helpBlPPfS0_S_:
.quad _Z21__device_stub__helpBlPPfS0_S_
.size _Z6helpBlPPfS0_S_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "addWithCuda failed!"
.size .L.str.1, 20
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "hipDeviceReset failed!"
.size .L.str.2, 23
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "hipSetDevice failed! Do you have a CUDA-capable GPU installed?"
.size .L.str.3, 64
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "hipMalloc failed!"
.size .L.str.4, 18
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "hipMemcpy failed!"
.size .L.str.5, 18
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "hipDeviceSynchronize returned error code %d after launching addKernel!\n"
.size .L.str.6, 72
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3Bl1PiS_S_"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z3Bl2PPfS0_S_"
.size .L__unnamed_2, 15
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z6helpBlPPfS0_S_"
.size .L__unnamed_3, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "blah-blah"
.size .Lstr, 10
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__Bl1PiS_S_
.addrsig_sym _Z18__device_stub__Bl2PPfS0_S_
.addrsig_sym _Z21__device_stub__helpBlPPfS0_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3Bl1PiS_S_
.addrsig_sym _Z3Bl2PPfS0_S_
.addrsig_sym _Z6helpBlPPfS0_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6helpBlPPfS0_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z3Bl2PPfS0_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z3Bl1PiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R5, 0x18894 ; /* 0x0001889400057802 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0050*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x001fca00078e0203 */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3Bl1PiS_S_
.globl _Z3Bl1PiS_S_
.p2align 8
.type _Z3Bl1PiS_S_,@function
_Z3Bl1PiS_S_:
s_load_b64 s[0:1], s[0:1], 0x0
v_dual_mov_b32 v1, 0x18894 :: v_dual_lshlrev_b32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3Bl1PiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3Bl1PiS_S_, .Lfunc_end0-_Z3Bl1PiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3Bl2PPfS0_S_
.globl _Z3Bl2PPfS0_S_
.p2align 8
.type _Z3Bl2PPfS0_S_,@function
_Z3Bl2PPfS0_S_:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3Bl2PPfS0_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z3Bl2PPfS0_S_, .Lfunc_end1-_Z3Bl2PPfS0_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z6helpBlPPfS0_S_
.globl _Z6helpBlPPfS0_S_
.p2align 8
.type _Z6helpBlPPfS0_S_,@function
_Z6helpBlPPfS0_S_:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6helpBlPPfS0_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z6helpBlPPfS0_S_, .Lfunc_end2-_Z6helpBlPPfS0_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3Bl1PiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z3Bl1PiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3Bl2PPfS0_S_
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z3Bl2PPfS0_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6helpBlPPfS0_S_
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z6helpBlPPfS0_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e6b86_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "blah-blah\n"
.text
.globl _Z8TestFuncv
.type _Z8TestFuncv, @function
_Z8TestFuncv:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z8TestFuncv, .-_Z8TestFuncv
.globl _Z8cudaTestRKiRfPf
.type _Z8cudaTestRKiRfPf, @function
_Z8cudaTestRKiRfPf:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbp
movq %rsi, %rbx
movq %rdx, %r12
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl initTime(%rip), %xmm0
movss %xmm0, (%rbx)
cmpl $0, 0(%rbp)
jle .L6
movl $0, %ebx
.L7:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%r12,%rbx,4)
addq $1, %rbx
cmpl %ebx, 0(%rbp)
jg .L7
.L6:
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z8cudaTestRKiRfPf, .-_Z8cudaTestRKiRfPf
.globl _Z15cudaSetInitTimei
.type _Z15cudaSetInitTimei, @function
_Z15cudaSetInitTimei:
.LFB2059:
.cfi_startproc
endbr64
movl %edi, initTime(%rip)
ret
.cfi_endproc
.LFE2059:
.size _Z15cudaSetInitTimei, .-_Z15cudaSetInitTimei
.globl _Z9loadInputPcPPfS0_Ri
.type _Z9loadInputPcPPfS0_Ri, @function
_Z9loadInputPcPPfS0_Ri:
.LFB2061:
.cfi_startproc
endbr64
movl $1, %eax
ret
.cfi_endproc
.LFE2061:
.size _Z9loadInputPcPPfS0_Ri, .-_Z9loadInputPcPPfS0_Ri
.globl _Z26__device_stub__Z3Bl1PiS_S_PiS_S_
.type _Z26__device_stub__Z3Bl1PiS_S_PiS_S_, @function
_Z26__device_stub__Z3Bl1PiS_S_PiS_S_:
.LFB2088:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3Bl1PiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z26__device_stub__Z3Bl1PiS_S_PiS_S_, .-_Z26__device_stub__Z3Bl1PiS_S_PiS_S_
.globl _Z3Bl1PiS_S_
.type _Z3Bl1PiS_S_, @function
_Z3Bl1PiS_S_:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3Bl1PiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z3Bl1PiS_S_, .-_Z3Bl1PiS_S_
.globl _Z9algorithmPiS_S_m
.type _Z9algorithmPiS_S_m, @function
_Z9algorithmPiS_S_m:
.LFB2062:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbx
movq %rsi, %rbp
movq %rdx, %r12
movl %ecx, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L20:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z26__device_stub__Z3Bl1PiS_S_PiS_S_
jmp .L20
.cfi_endproc
.LFE2062:
.size _Z9algorithmPiS_S_m, .-_Z9algorithmPiS_S_m
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?"
.section .rodata.str1.1
.LC2:
.string "cudaMalloc failed!"
.LC3:
.string "cudaMemcpy failed!"
.section .rodata.str1.8
.align 8
.LC4:
.string "cudaDeviceSynchronize returned error code %d after launching addKernel!\n"
.text
.globl _Z10launchCudaPiPKiS1_m
.type _Z10launchCudaPiPKiS1_m, @function
_Z10launchCudaPiPKiS1_m:
.LFB2063:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r14
movq %rsi, %r12
movq %rdx, %r13
movq %rcx, %rbp
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L35
leaq 0(,%rbp,4), %r15
leaq 16(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L36
movq %rsp, %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L37
leaq 8(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L38
movl $1, %ecx
movq %r15, %rdx
movq %r12, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L39
movl $1, %ecx
movq %r15, %rdx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L40
movq %rbp, %rcx
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movq 16(%rsp), %rdi
call _Z9algorithmPiS_S_m
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L41
movl $2, %ecx
movq %r15, %rdx
movq 16(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
je .L26
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L26
.L35:
movl %eax, %ebx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L26:
movq 16(%rsp), %rdi
call cudaFree@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L42
movl %ebx, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L26
.L37:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L26
.L38:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L26
.L39:
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L26
.L40:
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L26
.L41:
movl %eax, %ecx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L26
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size _Z10launchCudaPiPKiS1_m, .-_Z10launchCudaPiPKiS1_m
.section .rodata.str1.1
.LC5:
.string "addWithCuda failed!"
.LC6:
.string "cudaDeviceReset failed!"
.text
.globl _Z8cudaMainRKiRfPf
.type _Z8cudaMainRKiRfPf, @function
_Z8cudaMainRKiRfPf:
.LFB2060:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %rbx
movslq (%rdi), %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L44
movq %rdx, %r12
salq $2, %rdi
call _Znam@PLT
movq %rax, %r13
movslq (%rbx), %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L60
salq $2, %rdi
call _Znam@PLT
movq %rax, %r14
movslq (%rbx), %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L61
salq $2, %rdi
call _Znam@PLT
movq %rax, %rbp
movslq (%rbx), %rcx
movq %r14, %rdx
movq %r13, %rsi
movq %rax, %rdi
call _Z10launchCudaPiPKiS1_m
testl %eax, %eax
jne .L49
movl $0, %eax
cmpl $0, (%rbx)
jle .L51
.L50:
pxor %xmm0, %xmm0
cvtsi2ssl 0(%rbp,%rax,4), %xmm0
movss %xmm0, (%r12,%rax,4)
addq $1, %rax
cmpl %eax, (%rbx)
jg .L50
.L51:
call cudaDeviceReset@PLT
movl %eax, %edx
movl $0, %eax
testl %edx, %edx
jne .L62
.L43:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
call __cxa_throw_bad_array_new_length@PLT
.L60:
call __cxa_throw_bad_array_new_length@PLT
.L61:
call __cxa_throw_bad_array_new_length@PLT
.L49:
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L43
.L62:
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %eax
jmp .L43
.cfi_endproc
.LFE2060:
.size _Z8cudaMainRKiRfPf, .-_Z8cudaMainRKiRfPf
.globl _Z28__device_stub__Z3Bl2PPfS0_S_PPfS0_S_
.type _Z28__device_stub__Z3Bl2PPfS0_S_PPfS0_S_, @function
_Z28__device_stub__Z3Bl2PPfS0_S_PPfS0_S_:
.LFB2090:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L67
.L63:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L68
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L67:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3Bl2PPfS0_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L63
.L68:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z28__device_stub__Z3Bl2PPfS0_S_PPfS0_S_, .-_Z28__device_stub__Z3Bl2PPfS0_S_PPfS0_S_
.globl _Z3Bl2PPfS0_S_
.type _Z3Bl2PPfS0_S_, @function
_Z3Bl2PPfS0_S_:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z3Bl2PPfS0_S_PPfS0_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z3Bl2PPfS0_S_, .-_Z3Bl2PPfS0_S_
.globl _Z31__device_stub__Z6helpBlPPfS0_S_PPfS0_S_
.type _Z31__device_stub__Z6helpBlPPfS0_S_PPfS0_S_, @function
_Z31__device_stub__Z6helpBlPPfS0_S_PPfS0_S_:
.LFB2092:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L75
.L71:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L76
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L75:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6helpBlPPfS0_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L71
.L76:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2092:
.size _Z31__device_stub__Z6helpBlPPfS0_S_PPfS0_S_, .-_Z31__device_stub__Z6helpBlPPfS0_S_PPfS0_S_
.globl _Z6helpBlPPfS0_S_
.type _Z6helpBlPPfS0_S_, @function
_Z6helpBlPPfS0_S_:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z6helpBlPPfS0_S_PPfS0_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _Z6helpBlPPfS0_S_, .-_Z6helpBlPPfS0_S_
.section .rodata.str1.1
.LC7:
.string "_Z6helpBlPPfS0_S_"
.LC8:
.string "_Z3Bl2PPfS0_S_"
.LC9:
.string "_Z3Bl1PiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2095:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z6helpBlPPfS0_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z3Bl2PPfS0_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z3Bl1PiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2095:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl initTime
.bss
.align 4
.type initTime, @object
.size initTime, 4
initTime:
.zero 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z18__device_stub__Bl1PiS_S_ # -- Begin function _Z18__device_stub__Bl1PiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__Bl1PiS_S_,@function
_Z18__device_stub__Bl1PiS_S_: # @_Z18__device_stub__Bl1PiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3Bl1PiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__Bl1PiS_S_, .Lfunc_end0-_Z18__device_stub__Bl1PiS_S_
.cfi_endproc
# -- End function
.globl _Z18__device_stub__Bl2PPfS0_S_ # -- Begin function _Z18__device_stub__Bl2PPfS0_S_
.p2align 4, 0x90
.type _Z18__device_stub__Bl2PPfS0_S_,@function
_Z18__device_stub__Bl2PPfS0_S_: # @_Z18__device_stub__Bl2PPfS0_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3Bl2PPfS0_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z18__device_stub__Bl2PPfS0_S_, .Lfunc_end1-_Z18__device_stub__Bl2PPfS0_S_
.cfi_endproc
# -- End function
.globl _Z21__device_stub__helpBlPPfS0_S_ # -- Begin function _Z21__device_stub__helpBlPPfS0_S_
.p2align 4, 0x90
.type _Z21__device_stub__helpBlPPfS0_S_,@function
_Z21__device_stub__helpBlPPfS0_S_: # @_Z21__device_stub__helpBlPPfS0_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6helpBlPPfS0_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z21__device_stub__helpBlPPfS0_S_, .Lfunc_end2-_Z21__device_stub__helpBlPPfS0_S_
.cfi_endproc
# -- End function
.globl _Z8TestFuncv # -- Begin function _Z8TestFuncv
.p2align 4, 0x90
.type _Z8TestFuncv,@function
_Z8TestFuncv: # @_Z8TestFuncv
.cfi_startproc
# %bb.0:
movl $.Lstr, %edi
jmp puts@PLT # TAILCALL
.Lfunc_end3:
.size _Z8TestFuncv, .Lfunc_end3-_Z8TestFuncv
.cfi_endproc
# -- End function
.globl _Z8cudaTestRKiRfPf # -- Begin function _Z8cudaTestRKiRfPf
.p2align 4, 0x90
.type _Z8cudaTestRKiRfPf,@function
_Z8cudaTestRKiRfPf: # @_Z8cudaTestRKiRfPf
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %rbx
movq %rsi, %r15
movq %rdi, %r14
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
cvtsi2ssl initTime(%rip), %xmm0
movss %xmm0, (%r15)
cmpl $0, (%r14)
jle .LBB4_3
# %bb.1: # %.lr.ph.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
movslq (%r14), %rax
cmpq %rax, %r15
jl .LBB4_2
.LBB4_3: # %._crit_edge
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z8cudaTestRKiRfPf, .Lfunc_end4-_Z8cudaTestRKiRfPf
.cfi_endproc
# -- End function
.globl _Z15cudaSetInitTimei # -- Begin function _Z15cudaSetInitTimei
.p2align 4, 0x90
.type _Z15cudaSetInitTimei,@function
_Z15cudaSetInitTimei: # @_Z15cudaSetInitTimei
.cfi_startproc
# %bb.0:
movl %edi, initTime(%rip)
retq
.Lfunc_end5:
.size _Z15cudaSetInitTimei, .Lfunc_end5-_Z15cudaSetInitTimei
.cfi_endproc
# -- End function
.globl _Z8cudaMainRKiRfPf # -- Begin function _Z8cudaMainRKiRfPf
.p2align 4, 0x90
.type _Z8cudaMainRKiRfPf,@function
_Z8cudaMainRKiRfPf: # @_Z8cudaMainRKiRfPf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %rbx
movq %rdi, %r15
movslq (%rdi), %r12
leaq (,%r12,4), %rax
testq %r12, %r12
movq $-1, %r14
cmovnsq %rax, %r14
movq %r14, %rdi
callq _Znam
movq %rax, %r13
movq %r14, %rdi
callq _Znam
movq %rax, %rbp
movq %r14, %rdi
callq _Znam
movq %rax, %r14
movq %rax, %rdi
movq %r13, %rsi
movq %rbp, %rdx
movq %r12, %rcx
callq _Z10launchCudaPiPKiS1_m
testl %eax, %eax
jne .LBB6_8
# %bb.1: # %.preheader
movl (%r15), %eax
testl %eax, %eax
jle .LBB6_4
# %bb.2: # %.lr.ph.preheader
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB6_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ssl (%r14,%rcx,4), %xmm0
movss %xmm0, (%rbx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB6_3
.LBB6_4: # %._crit_edge
callq hipDeviceReset
movl %eax, %ecx
xorl %eax, %eax
testl %ecx, %ecx
jne .LBB6_5
.LBB6_7:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB6_8:
.cfi_def_cfa_offset 64
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $19, %esi
jmp .LBB6_6
.LBB6_5:
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $22, %esi
.LBB6_6:
movl $1, %edx
callq fwrite@PLT
movl $1, %eax
jmp .LBB6_7
.Lfunc_end6:
.size _Z8cudaMainRKiRfPf, .Lfunc_end6-_Z8cudaMainRKiRfPf
.cfi_endproc
# -- End function
.globl _Z10launchCudaPiPKiS1_m # -- Begin function _Z10launchCudaPiPKiS1_m
.p2align 4, 0x90
.type _Z10launchCudaPiPKiS1_m,@function
_Z10launchCudaPiPKiS1_m: # @_Z10launchCudaPiPKiS1_m
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $32, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rcx, %r14
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %rbx
movq $0, 24(%rsp)
movq $0, 16(%rsp)
movq $0, 8(%rsp)
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB7_15
# %bb.1:
leaq (,%r14,4), %r15
leaq 8(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB7_9
# %bb.2:
leaq 24(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB7_9
# %bb.3:
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB7_9
# %bb.4:
movq 24(%rsp), %rdi
movq %r13, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB7_10
# %bb.5:
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB7_10
# %bb.6:
movq 8(%rsp), %rdi
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
movq %r14, %rcx
callq _Z9algorithmPiS_S_m
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB7_16
# %bb.7:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
testl %eax, %eax
je .LBB7_14
# %bb.8:
movq stderr(%rip), %rcx
movl $.L.str.5, %edi
movl $17, %esi
movl $1, %edx
movl %eax, %ebx
jmp .LBB7_13
.LBB7_9:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.4, %edi
jmp .LBB7_11
.LBB7_10:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.5, %edi
.LBB7_11:
movl $17, %esi
.LBB7_12:
movl $1, %edx
.LBB7_13:
callq fwrite@PLT
.LBB7_14:
movq 8(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movl %ebx, %eax
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB7_15:
.cfi_def_cfa_offset 80
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $63, %esi
jmp .LBB7_12
.LBB7_16:
movq stderr(%rip), %rdi
movl $.L.str.6, %esi
movl %eax, %ebx
movl %eax, %edx
xorl %eax, %eax
callq fprintf
jmp .LBB7_14
.Lfunc_end7:
.size _Z10launchCudaPiPKiS1_m, .Lfunc_end7-_Z10launchCudaPiPKiS1_m
.cfi_endproc
# -- End function
.globl _Z9loadInputPcPPfS0_Ri # -- Begin function _Z9loadInputPcPPfS0_Ri
.p2align 4, 0x90
.type _Z9loadInputPcPPfS0_Ri,@function
_Z9loadInputPcPPfS0_Ri: # @_Z9loadInputPcPPfS0_Ri
.cfi_startproc
# %bb.0:
movb $1, %al
retq
.Lfunc_end8:
.size _Z9loadInputPcPPfS0_Ri, .Lfunc_end8-_Z9loadInputPcPPfS0_Ri
.cfi_endproc
# -- End function
.globl _Z9algorithmPiS_S_m # -- Begin function _Z9algorithmPiS_S_m
.p2align 4, 0x90
.type _Z9algorithmPiS_S_m,@function
_Z9algorithmPiS_S_m: # @_Z9algorithmPiS_S_m
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movl %ecx, %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB9_2
# %bb.1:
movq %r15, 72(%rsp)
movq %r14, 64(%rsp)
movq %rbx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3Bl1PiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB9_2:
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end9:
.size _Z9algorithmPiS_S_m, .Lfunc_end9-_Z9algorithmPiS_S_m
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB10_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB10_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3Bl1PiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3Bl2PPfS0_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6helpBlPPfS0_S_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end10:
.size __hip_module_ctor, .Lfunc_end10-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB11_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB11_2:
retq
.Lfunc_end11:
.size __hip_module_dtor, .Lfunc_end11-__hip_module_dtor
.cfi_endproc
# -- End function
.type initTime,@object # @initTime
.bss
.globl initTime
.p2align 2, 0x0
initTime:
.long 0 # 0x0
.size initTime, 4
.type _Z3Bl1PiS_S_,@object # @_Z3Bl1PiS_S_
.section .rodata,"a",@progbits
.globl _Z3Bl1PiS_S_
.p2align 3, 0x0
_Z3Bl1PiS_S_:
.quad _Z18__device_stub__Bl1PiS_S_
.size _Z3Bl1PiS_S_, 8
.type _Z3Bl2PPfS0_S_,@object # @_Z3Bl2PPfS0_S_
.globl _Z3Bl2PPfS0_S_
.p2align 3, 0x0
_Z3Bl2PPfS0_S_:
.quad _Z18__device_stub__Bl2PPfS0_S_
.size _Z3Bl2PPfS0_S_, 8
.type _Z6helpBlPPfS0_S_,@object # @_Z6helpBlPPfS0_S_
.globl _Z6helpBlPPfS0_S_
.p2align 3, 0x0
_Z6helpBlPPfS0_S_:
.quad _Z21__device_stub__helpBlPPfS0_S_
.size _Z6helpBlPPfS0_S_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "addWithCuda failed!"
.size .L.str.1, 20
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "hipDeviceReset failed!"
.size .L.str.2, 23
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "hipSetDevice failed! Do you have a CUDA-capable GPU installed?"
.size .L.str.3, 64
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "hipMalloc failed!"
.size .L.str.4, 18
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "hipMemcpy failed!"
.size .L.str.5, 18
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "hipDeviceSynchronize returned error code %d after launching addKernel!\n"
.size .L.str.6, 72
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3Bl1PiS_S_"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z3Bl2PPfS0_S_"
.size .L__unnamed_2, 15
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z6helpBlPPfS0_S_"
.size .L__unnamed_3, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "blah-blah"
.size .Lstr, 10
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__Bl1PiS_S_
.addrsig_sym _Z18__device_stub__Bl2PPfS0_S_
.addrsig_sym _Z21__device_stub__helpBlPPfS0_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3Bl1PiS_S_
.addrsig_sym _Z3Bl2PPfS0_S_
.addrsig_sym _Z6helpBlPPfS0_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //ref: https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#assertion
#include <assert.h>
__global__ void testAssert(void)
{
int is_one = 1;
int should_be_one = 0;
// This will have no effect
assert(is_one);
// This will halt kernel execution
assert(should_be_one);
}
int main(int argc, char* argv[])
{
testAssert<<<1,1>>>();
cudaDeviceSynchronize();
return 0;
}
//[Note]:
//Assertions are for debugging purposes.
//They can affect performance and it is therefore recommended to disable them in production code.
//They can be disabled at compile time by defining the NDEBUG preprocessor macro before including assert.h.
//Note that expression should not be an expression with side effects (something like (++i > 0), for example),
//otherwise disabling the assertion will affect the functionality of the code. | code for sm_80
Function : _Z10testAssertv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //ref: https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#assertion
#include <assert.h>
__global__ void testAssert(void)
{
int is_one = 1;
int should_be_one = 0;
// This will have no effect
assert(is_one);
// This will halt kernel execution
assert(should_be_one);
}
int main(int argc, char* argv[])
{
testAssert<<<1,1>>>();
cudaDeviceSynchronize();
return 0;
}
//[Note]:
//Assertions are for debugging purposes.
//They can affect performance and it is therefore recommended to disable them in production code.
//They can be disabled at compile time by defining the NDEBUG preprocessor macro before including assert.h.
//Note that expression should not be an expression with side effects (something like (++i > 0), for example),
//otherwise disabling the assertion will affect the functionality of the code. | .file "tmpxft_001303ad_00000000-6_test_assertion.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10testAssertvv
.type _Z29__device_stub__Z10testAssertvv, @function
_Z29__device_stub__Z10testAssertvv:
.LFB2052:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10testAssertv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z29__device_stub__Z10testAssertvv, .-_Z29__device_stub__Z10testAssertvv
.globl _Z10testAssertv
.type _Z10testAssertv, @function
_Z10testAssertv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10testAssertvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z10testAssertv, .-_Z10testAssertv
.globl main
.type main, @function
main:
.LFB2027:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z29__device_stub__Z10testAssertvv
jmp .L12
.cfi_endproc
.LFE2027:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10testAssertv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10testAssertv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //ref: https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#assertion
#include <assert.h>
__global__ void testAssert(void)
{
int is_one = 1;
int should_be_one = 0;
// This will have no effect
assert(is_one);
// This will halt kernel execution
assert(should_be_one);
}
int main(int argc, char* argv[])
{
testAssert<<<1,1>>>();
cudaDeviceSynchronize();
return 0;
}
//[Note]:
//Assertions are for debugging purposes.
//They can affect performance and it is therefore recommended to disable them in production code.
//They can be disabled at compile time by defining the NDEBUG preprocessor macro before including assert.h.
//Note that expression should not be an expression with side effects (something like (++i > 0), for example),
//otherwise disabling the assertion will affect the functionality of the code. | //ref: https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#assertion
#include <hip/hip_runtime.h>
#include <assert.h>
__global__ void testAssert(void)
{
int is_one = 1;
int should_be_one = 0;
// This will have no effect
assert(is_one);
// This will halt kernel execution
assert(should_be_one);
}
int main(int argc, char* argv[])
{
testAssert<<<1,1>>>();
hipDeviceSynchronize();
return 0;
}
//[Note]:
//Assertions are for debugging purposes.
//They can affect performance and it is therefore recommended to disable them in production code.
//They can be disabled at compile time by defining the NDEBUG preprocessor macro before including assert.h.
//Note that expression should not be an expression with side effects (something like (++i > 0), for example),
//otherwise disabling the assertion will affect the functionality of the code. |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //ref: https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#assertion
#include <hip/hip_runtime.h>
#include <assert.h>
__global__ void testAssert(void)
{
int is_one = 1;
int should_be_one = 0;
// This will have no effect
assert(is_one);
// This will halt kernel execution
assert(should_be_one);
}
int main(int argc, char* argv[])
{
testAssert<<<1,1>>>();
hipDeviceSynchronize();
return 0;
}
//[Note]:
//Assertions are for debugging purposes.
//They can affect performance and it is therefore recommended to disable them in production code.
//They can be disabled at compile time by defining the NDEBUG preprocessor macro before including assert.h.
//Note that expression should not be an expression with side effects (something like (++i > 0), for example),
//otherwise disabling the assertion will affect the functionality of the code. | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10testAssertv
.globl _Z10testAssertv
.p2align 8
.type _Z10testAssertv,@function
_Z10testAssertv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10testAssertv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10testAssertv, .Lfunc_end0-_Z10testAssertv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10testAssertv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z10testAssertv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //ref: https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#assertion
#include <hip/hip_runtime.h>
#include <assert.h>
__global__ void testAssert(void)
{
int is_one = 1;
int should_be_one = 0;
// This will have no effect
assert(is_one);
// This will halt kernel execution
assert(should_be_one);
}
int main(int argc, char* argv[])
{
testAssert<<<1,1>>>();
hipDeviceSynchronize();
return 0;
}
//[Note]:
//Assertions are for debugging purposes.
//They can affect performance and it is therefore recommended to disable them in production code.
//They can be disabled at compile time by defining the NDEBUG preprocessor macro before including assert.h.
//Note that expression should not be an expression with side effects (something like (++i > 0), for example),
//otherwise disabling the assertion will affect the functionality of the code. | .text
.file "test_assertion.hip"
.globl _Z25__device_stub__testAssertv # -- Begin function _Z25__device_stub__testAssertv
.p2align 4, 0x90
.type _Z25__device_stub__testAssertv,@function
_Z25__device_stub__testAssertv: # @_Z25__device_stub__testAssertv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10testAssertv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z25__device_stub__testAssertv, .Lfunc_end0-_Z25__device_stub__testAssertv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10testAssertv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10testAssertv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10testAssertv,@object # @_Z10testAssertv
.section .rodata,"a",@progbits
.globl _Z10testAssertv
.p2align 3, 0x0
_Z10testAssertv:
.quad _Z25__device_stub__testAssertv
.size _Z10testAssertv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10testAssertv"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__testAssertv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10testAssertv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10testAssertv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10testAssertv
.globl _Z10testAssertv
.p2align 8
.type _Z10testAssertv,@function
_Z10testAssertv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10testAssertv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10testAssertv, .Lfunc_end0-_Z10testAssertv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10testAssertv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z10testAssertv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001303ad_00000000-6_test_assertion.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10testAssertvv
.type _Z29__device_stub__Z10testAssertvv, @function
_Z29__device_stub__Z10testAssertvv:
.LFB2052:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10testAssertv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z29__device_stub__Z10testAssertvv, .-_Z29__device_stub__Z10testAssertvv
.globl _Z10testAssertv
.type _Z10testAssertv, @function
_Z10testAssertv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10testAssertvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z10testAssertv, .-_Z10testAssertv
.globl main
.type main, @function
main:
.LFB2027:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z29__device_stub__Z10testAssertvv
jmp .L12
.cfi_endproc
.LFE2027:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10testAssertv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10testAssertv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test_assertion.hip"
.globl _Z25__device_stub__testAssertv # -- Begin function _Z25__device_stub__testAssertv
.p2align 4, 0x90
.type _Z25__device_stub__testAssertv,@function
_Z25__device_stub__testAssertv: # @_Z25__device_stub__testAssertv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10testAssertv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z25__device_stub__testAssertv, .Lfunc_end0-_Z25__device_stub__testAssertv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10testAssertv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10testAssertv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10testAssertv,@object # @_Z10testAssertv
.section .rodata,"a",@progbits
.globl _Z10testAssertv
.p2align 3, 0x0
_Z10testAssertv:
.quad _Z25__device_stub__testAssertv
.size _Z10testAssertv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10testAssertv"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__testAssertv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10testAssertv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include "cuda.h"
#define max(x,y) ((x) > (y)? (x) : (y))
#define min(x,y) ((x) < (y)? (x) : (y))
#define ceil(a,b) ((a) % (b) == 0 ? (a) / (b) : ((a) / (b)) + 1)
void check_error (const char* message) {
cudaError_t error = cudaGetLastError ();
if (error != cudaSuccess) {
printf ("CUDA error : %s, %s\n", message, cudaGetErrorString (error));
exit(-1);
}
}
__global__ void j2d81pt (double * __restrict__ l_in, double * __restrict__ l_out, int N) {
//Determing the block's indices
int i0 = (int)(blockIdx.x)*(int)(blockDim.x);
int i = max(i0,0) + (int)(threadIdx.x);
int j0 = 4*(int)(blockIdx.y)*(int)(blockDim.y);
int j = max(j0,0) + 4*(int)(threadIdx.y);
double (*in)[8200] = (double (*)[8200]) l_in;
double (*out)[8200] = (double (*)[8200]) l_out;
if (i>=0 & j>=0 & i<=N-9 & j<=N-9) {
double _t_0_ = in[j][i];
_t_0_ += in[j][i+8];
_t_0_ += in[j+8][i];
double _t_15_ = in[j+8][i];
double _t_30_ = in[j+8][i];
double _t_45_ = in[j+8][i];
_t_0_ += in[j+8][i+8];
_t_15_ += in[j+8][i+8];
_t_30_ += in[j+8][i+8];
_t_45_ += in[j+8][i+8];
double outjc0ic0 = _t_0_ * 3.18622;
double _t_4_ = in[j][i+4];
_t_4_ += in[j+4][i+8];
double _t_17_ = in[j+4][i+8];
_t_30_ += in[j+4][i+8];
double _t_43_ = in[j+4][i+8];
_t_4_ += in[j+4][i];
_t_17_ += in[j+4][i];
_t_30_ += in[j+4][i];
_t_43_ += in[j+4][i];
_t_4_ += in[j+8][i+4];
double _t_22_ = in[j+8][i+4];
double _t_39_ = in[j+8][i+4];
double _t_55_ = in[j+8][i+4];
outjc0ic0 += _t_4_ * -0.00508225;
double _t_5_ = in[j+1][i+1];
_t_15_ += in[j+1][i+1];
_t_5_ += in[j+1][i+7];
_t_15_ += in[j+1][i+7];
_t_5_ += in[j+7][i+1];
double _t_20_ = in[j+7][i+1];
double _t_35_ = in[j+7][i+1];
double _t_50_ = in[j+7][i+1];
_t_5_ += in[j+7][i+7];
_t_20_ += in[j+7][i+7];
_t_35_ += in[j+7][i+7];
_t_50_ += in[j+7][i+7];
outjc0ic0 += _t_5_ * 0.00064516;
double _t_8_ = in[j+1][i+4];
double _t_18_ = in[j+1][i+4];
_t_8_ += in[j+4][i+1];
double _t_21_ = in[j+4][i+1];
double _t_34_ = in[j+4][i+1];
double _t_47_ = in[j+4][i+1];
_t_8_ += in[j+4][i+7];
_t_21_ += in[j+4][i+7];
_t_34_ += in[j+4][i+7];
_t_47_ += in[j+4][i+7];
_t_8_ += in[j+7][i+4];
double _t_25_ = in[j+7][i+4];
double _t_41_ = in[j+7][i+4];
double outjp3ic0 = in[j+7][i+4] * 8.10655;
outjc0ic0 += _t_8_ * -0.0723189;
double _t_9_ = in[j+2][i+2];
_t_20_ += in[j+2][i+2];
_t_30_ += in[j+2][i+2];
_t_9_ += in[j+2][i+6];
_t_20_ += in[j+2][i+6];
_t_30_ += in[j+2][i+6];
_t_9_ += in[j+6][i+2];
double _t_24_ = in[j+6][i+2];
_t_39_ += in[j+6][i+2];
double _t_52_ = in[j+6][i+2];
_t_9_ += in[j+6][i+6];
_t_24_ += in[j+6][i+6];
_t_39_ += in[j+6][i+6];
_t_52_ += in[j+6][i+6];
outjc0ic0 += _t_9_ * 0.04;
double _t_11_ = in[j+2][i+4];
_t_22_ += in[j+2][i+4];
double _t_32_ = in[j+2][i+4];
_t_11_ += in[j+4][i+2];
_t_24_ += in[j+4][i+2];
double _t_37_ = in[j+4][i+2];
double _t_48_ = in[j+4][i+2];
_t_11_ += in[j+4][i+6];
_t_24_ += in[j+4][i+6];
_t_37_ += in[j+4][i+6];
_t_48_ += in[j+4][i+6];
_t_11_ += in[j+6][i+4];
double _t_27_ = in[j+6][i+4];
double outjp2ic0 = in[j+6][i+4] * 8.10655;
_t_55_ += in[j+6][i+4];
outjc0ic0 += _t_11_ * 0.56944;
double _t_12_ = in[j+3][i+3];
_t_24_ += in[j+3][i+3];
_t_35_ += in[j+3][i+3];
_t_45_ += in[j+3][i+3];
_t_12_ += in[j+3][i+5];
_t_24_ += in[j+3][i+5];
_t_35_ += in[j+3][i+5];
_t_45_ += in[j+3][i+5];
_t_12_ += in[j+5][i+3];
_t_27_ += in[j+5][i+3];
double _t_40_ = in[j+5][i+3];
_t_52_ += in[j+5][i+3];
_t_12_ += in[j+5][i+5];
_t_27_ += in[j+5][i+5];
_t_40_ += in[j+5][i+5];
_t_52_ += in[j+5][i+5];
outjc0ic0 += _t_12_ * 2.56;
double _t_13_ = in[j+3][i+4];
_t_25_ += in[j+3][i+4];
double _t_36_ = in[j+3][i+4];
double _t_46_ = in[j+3][i+4];
_t_13_ += in[j+4][i+3];
double _t_26_ = in[j+4][i+3];
double _t_38_ = in[j+4][i+3];
double _t_49_ = in[j+4][i+3];
_t_13_ += in[j+4][i+5];
_t_26_ += in[j+4][i+5];
_t_38_ += in[j+4][i+5];
_t_49_ += in[j+4][i+5];
_t_13_ += in[j+5][i+4];
double outjp1ic0 = in[j+5][i+4] * 8.10655;
_t_41_ += in[j+5][i+4];
double _t_53_ = in[j+5][i+4];
outjc0ic0 += _t_13_ * -4.55552;
double _t_1_ = in[j][i+1];
_t_1_ += in[j][i+7];
_t_1_ += in[j+1][i];
double _t_14_ = in[j+1][i];
_t_1_ += in[j+1][i+8];
_t_14_ += in[j+1][i+8];
_t_1_ += in[j+7][i];
double _t_16_ = in[j+7][i];
double _t_31_ = in[j+7][i];
_t_46_ += in[j+7][i];
_t_1_ += in[j+7][i+8];
_t_16_ += in[j+7][i+8];
_t_31_ += in[j+7][i+8];
_t_46_ += in[j+7][i+8];
_t_1_ += in[j+8][i+1];
double _t_19_ = in[j+8][i+1];
_t_34_ += in[j+8][i+1];
_t_49_ += in[j+8][i+1];
_t_1_ += in[j+8][i+7];
_t_19_ += in[j+8][i+7];
_t_34_ += in[j+8][i+7];
_t_49_ += in[j+8][i+7];
outjc0ic0 += _t_1_ * 4.5339;
double _t_2_ = in[j][i+2];
_t_2_ += in[j][i+6];
_t_2_ += in[j+2][i];
_t_15_ += in[j+2][i];
double _t_28_ = in[j+2][i];
_t_2_ += in[j+2][i+8];
_t_15_ += in[j+2][i+8];
_t_28_ += in[j+2][i+8];
_t_2_ += in[j+6][i];
_t_17_ += in[j+6][i];
_t_32_ += in[j+6][i];
_t_45_ += in[j+6][i];
_t_2_ += in[j+6][i+8];
_t_17_ += in[j+6][i+8];
_t_32_ += in[j+6][i+8];
_t_45_ += in[j+6][i+8];
_t_2_ += in[j+8][i+2];
_t_20_ += in[j+8][i+2];
_t_37_ += in[j+8][i+2];
_t_52_ += in[j+8][i+2];
_t_2_ += in[j+8][i+6];
_t_20_ += in[j+8][i+6];
_t_37_ += in[j+8][i+6];
_t_52_ += in[j+8][i+6];
outjc0ic0 += _t_2_ * -0.000357;
double _t_3_ = in[j][i+3];
_t_3_ += in[j][i+5];
_t_3_ += in[j+3][i];
_t_16_ += in[j+3][i];
double _t_29_ = in[j+3][i];
double _t_42_ = in[j+3][i];
_t_3_ += in[j+3][i+8];
_t_16_ += in[j+3][i+8];
_t_29_ += in[j+3][i+8];
_t_42_ += in[j+3][i+8];
_t_3_ += in[j+5][i];
_t_18_ += in[j+5][i];
_t_31_ += in[j+5][i];
double _t_44_ = in[j+5][i];
_t_3_ += in[j+5][i+8];
_t_18_ += in[j+5][i+8];
_t_31_ += in[j+5][i+8];
_t_44_ += in[j+5][i+8];
_t_3_ += in[j+8][i+3];
_t_21_ += in[j+8][i+3];
_t_38_ += in[j+8][i+3];
double _t_54_ = in[j+8][i+3];
_t_3_ += in[j+8][i+5];
_t_21_ += in[j+8][i+5];
_t_38_ += in[j+8][i+5];
_t_54_ += in[j+8][i+5];
outjc0ic0 += _t_3_ * 0.002856;
double _t_6_ = in[j+1][i+2];
_t_16_ += in[j+1][i+2];
_t_6_ += in[j+1][i+6];
_t_16_ += in[j+1][i+6];
_t_6_ += in[j+2][i+1];
_t_19_ += in[j+2][i+1];
_t_29_ += in[j+2][i+1];
_t_6_ += in[j+2][i+7];
_t_19_ += in[j+2][i+7];
_t_29_ += in[j+2][i+7];
_t_6_ += in[j+6][i+1];
_t_21_ += in[j+6][i+1];
_t_36_ += in[j+6][i+1];
_t_49_ += in[j+6][i+1];
_t_6_ += in[j+6][i+7];
_t_21_ += in[j+6][i+7];
_t_36_ += in[j+6][i+7];
_t_49_ += in[j+6][i+7];
_t_6_ += in[j+7][i+2];
double _t_23_ = in[j+7][i+2];
_t_38_ += in[j+7][i+2];
_t_53_ += in[j+7][i+2];
_t_6_ += in[j+7][i+6];
_t_23_ += in[j+7][i+6];
_t_38_ += in[j+7][i+6];
_t_53_ += in[j+7][i+6];
outjc0ic0 += _t_6_ * -0.00508;
double _t_7_ = in[j+1][i+3];
_t_17_ += in[j+1][i+3];
_t_7_ += in[j+1][i+5];
_t_17_ += in[j+1][i+5];
_t_7_ += in[j+3][i+1];
_t_20_ += in[j+3][i+1];
double _t_33_ = in[j+3][i+1];
_t_43_ += in[j+3][i+1];
_t_7_ += in[j+3][i+7];
_t_20_ += in[j+3][i+7];
_t_33_ += in[j+3][i+7];
_t_43_ += in[j+3][i+7];
_t_7_ += in[j+5][i+1];
_t_22_ += in[j+5][i+1];
_t_35_ += in[j+5][i+1];
_t_48_ += in[j+5][i+1];
_t_7_ += in[j+5][i+7];
_t_22_ += in[j+5][i+7];
_t_35_ += in[j+5][i+7];
_t_48_ += in[j+5][i+7];
_t_7_ += in[j+7][i+3];
_t_24_ += in[j+7][i+3];
_t_40_ += in[j+7][i+3];
_t_55_ += in[j+7][i+3];
_t_7_ += in[j+7][i+5];
_t_24_ += in[j+7][i+5];
_t_40_ += in[j+7][i+5];
_t_55_ += in[j+7][i+5];
outjc0ic0 += _t_7_ * 0.04064;
double _t_10_ = in[j+2][i+3];
_t_21_ += in[j+2][i+3];
_t_31_ += in[j+2][i+3];
_t_10_ += in[j+2][i+5];
_t_21_ += in[j+2][i+5];
_t_31_ += in[j+2][i+5];
_t_10_ += in[j+3][i+2];
_t_23_ += in[j+3][i+2];
_t_34_ += in[j+3][i+2];
_t_44_ += in[j+3][i+2];
_t_10_ += in[j+3][i+6];
_t_23_ += in[j+3][i+6];
_t_34_ += in[j+3][i+6];
_t_44_ += in[j+3][i+6];
_t_10_ += in[j+5][i+2];
_t_25_ += in[j+5][i+2];
_t_38_ += in[j+5][i+2];
double _t_51_ = in[j+5][i+2];
_t_10_ += in[j+5][i+6];
_t_25_ += in[j+5][i+6];
_t_38_ += in[j+5][i+6];
_t_51_ += in[j+5][i+6];
_t_10_ += in[j+6][i+3];
_t_26_ += in[j+6][i+3];
_t_41_ += in[j+6][i+3];
_t_54_ += in[j+6][i+3];
_t_10_ += in[j+6][i+5];
_t_26_ += in[j+6][i+5];
_t_41_ += in[j+6][i+5];
_t_54_ += in[j+6][i+5];
outjc0ic0 += _t_10_ * -0.32;
outjc0ic0 += in[j+4][i+4] * 8.10655;
_t_27_ += in[j+4][i+4];
_t_39_ += in[j+4][i+4];
_t_50_ += in[j+4][i+4];
_t_14_ += in[j+9][i];
_t_29_ += in[j+9][i];
_t_45_ += in[j+11][i+3];
_t_45_ += in[j+11][i+5];
outjp3ic0 += _t_45_ * 0.002856;
_t_46_ += in[j+11][i+4];
outjp3ic0 += _t_46_ * -0.00508225;
_t_42_ += in[j+11][i];
_t_42_ += in[j+11][i+8];
outjp3ic0 += _t_42_ * 3.18622;
_t_14_ += in[j+9][i+8];
_t_29_ += in[j+9][i+8];
outjp1ic0 += _t_14_ * 3.18622;
_t_44_ += in[j+9][i];
_t_44_ += in[j+9][i+8];
_t_44_ += in[j+11][i+2];
_t_44_ += in[j+11][i+6];
outjp3ic0 += _t_44_ * -0.000357;
_t_15_ += in[j+9][i+1];
_t_48_ += in[j+9][i+1];
_t_15_ += in[j+9][i+7];
_t_48_ += in[j+9][i+7];
outjp1ic0 += _t_15_ * 4.5339;
_t_33_ += in[j+9][i+1];
_t_33_ += in[j+9][i+7];
outjp2ic0 += _t_33_ * 0.00064516;
_t_16_ += in[j+9][i+2];
_t_16_ += in[j+9][i+6];
outjp1ic0 += _t_16_ * -0.000357;
_t_34_ += in[j+9][i+2];
_t_34_ += in[j+9][i+6];
outjp2ic0 += _t_34_ * -0.00508;
_t_51_ += in[j+9][i+2];
_t_51_ += in[j+9][i+6];
outjp3ic0 += _t_51_ * 0.04;
_t_17_ += in[j+9][i+3];
_t_17_ += in[j+9][i+5];
outjp1ic0 += _t_17_ * 0.002856;
_t_35_ += in[j+9][i+3];
_t_35_ += in[j+9][i+5];
outjp2ic0 += _t_35_ * 0.04064;
_t_52_ += in[j+9][i+3];
_t_52_ += in[j+9][i+5];
outjp3ic0 += _t_52_ * -0.32;
_t_18_ += in[j+9][i+4];
_t_36_ += in[j+9][i+4];
outjp2ic0 += _t_36_ * -0.0723189;
_t_53_ += in[j+9][i+4];
outjp3ic0 += _t_53_ * 0.56944;
outjp1ic0 += _t_18_ * -0.00508225;
outjp1ic0 += _t_19_ * 0.00064516;
outjp1ic0 += _t_20_ * -0.00508;
outjp1ic0 += _t_21_ * 0.04064;
outjp1ic0 += _t_22_ * -0.0723189;
outjp1ic0 += _t_23_ * 0.04;
outjp1ic0 += _t_24_ * -0.32;
outjp1ic0 += _t_25_ * 0.56944;
outjp1ic0 += _t_26_ * 2.56;
outjp1ic0 += _t_27_ * -4.55552;
_t_28_ += in[j+10][i];
_t_28_ += in[j+10][i+8];
outjp2ic0 += _t_28_ * 3.18622;
_t_43_ += in[j+10][i];
_t_43_ += in[j+10][i+8];
_t_43_ += in[j+11][i+1];
_t_43_ += in[j+11][i+7];
outjp3ic0 += _t_43_ * 4.5339;
_t_29_ += in[j+10][i+1];
_t_29_ += in[j+10][i+7];
outjp2ic0 += _t_29_ * 4.5339;
_t_47_ += in[j+10][i+1];
_t_47_ += in[j+10][i+7];
outjp3ic0 += _t_47_ * 0.00064516;
_t_30_ += in[j+10][i+2];
_t_30_ += in[j+10][i+6];
outjp2ic0 += _t_30_ * -0.000357;
_t_48_ += in[j+10][i+2];
_t_48_ += in[j+10][i+6];
outjp3ic0 += _t_48_ * -0.00508;
_t_31_ += in[j+10][i+3];
_t_31_ += in[j+10][i+5];
outjp2ic0 += _t_31_ * 0.002856;
_t_49_ += in[j+10][i+3];
_t_49_ += in[j+10][i+5];
outjp3ic0 += _t_49_ * 0.04064;
_t_32_ += in[j+10][i+4];
_t_50_ += in[j+10][i+4];
outjp3ic0 += _t_50_ * -0.0723189;
outjp2ic0 += _t_32_ * -0.00508225;
outjp2ic0 += _t_37_ * 0.04;
outjp2ic0 += _t_38_ * -0.32;
outjp2ic0 += _t_39_ * 0.56944;
outjp2ic0 += _t_40_ * 2.56;
outjp2ic0 += _t_41_ * -4.55552;
outjp3ic0 += _t_54_ * 2.56;
outjp3ic0 += _t_55_ * -4.55552;
out[j][i] = outjc0ic0;
out[j+1][i] = outjp1ic0;
out[j+2][i] = outjp2ic0;
out[j+3][i] = outjp3ic0;
}
}
extern "C" void host_code (double *h_in, double *h_out, int N) {
double *in;
cudaMalloc (&in, sizeof(double)*N*N);
check_error ("Failed to allocate device memory for in\n");
cudaMemcpy (in, h_in, sizeof(double)*N*N, cudaMemcpyHostToDevice);
double *out;
cudaMalloc (&out, sizeof(double)*N*N);
check_error ("Failed to allocate device memory for out\n");
dim3 blockconfig (16, 8);
dim3 gridconfig (ceil(N, blockconfig.x), ceil(N, 4*blockconfig.y));
j2d81pt<<<gridconfig, blockconfig>>> (in, out, N);
cudaMemcpy (h_out, out, sizeof(double)*N*N, cudaMemcpyDeviceToHost);
cudaFree (in);
cudaFree (out);
} | .file "tmpxft_00191f65_00000000-6_reordered-b.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA error : %s, %s\n"
.text
.globl _Z11check_errorPKc
.type _Z11check_errorPKc, @function
_Z11check_errorPKc:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movq %rbx, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z11check_errorPKc, .-_Z11check_errorPKc
.globl _Z29__device_stub__Z7j2d81ptPdS_iPdS_i
.type _Z29__device_stub__Z7j2d81ptPdS_iPdS_i, @function
_Z29__device_stub__Z7j2d81ptPdS_iPdS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 16(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7j2d81ptPdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z29__device_stub__Z7j2d81ptPdS_iPdS_i, .-_Z29__device_stub__Z7j2d81ptPdS_iPdS_i
.globl _Z7j2d81ptPdS_i
.type _Z7j2d81ptPdS_i, @function
_Z7j2d81ptPdS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7j2d81ptPdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7j2d81ptPdS_i, .-_Z7j2d81ptPdS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Failed to allocate device memory for in\n"
.align 8
.LC2:
.string "Failed to allocate device memory for out\n"
.text
.globl host_code
.type host_code, @function
host_code:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r13
movq %rsi, %r12
movl %edx, %ebp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movslq %edx, %rbx
imulq %rbx, %rbx
salq $3, %rbx
movq %rsp, %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC1(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC2(%rip), %rdi
call _Z11check_errorPKc
movl $1, 24(%rsp)
testb $31, %bpl
jne .L16
movl %ebp, %eax
shrl $5, %eax
.L17:
movl %ebp, %edx
shrl $4, %edx
.L19:
movl %edx, 28(%rsp)
movl %eax, 32(%rsp)
movl $16, 16(%rsp)
movl $8, 20(%rsp)
movl 24(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L20:
movl $2, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl %ebp, %eax
shrl $5, %eax
addl $1, %eax
testb $15, %bpl
je .L17
movl %ebp, %edx
shrl $4, %edx
addl $1, %edx
jmp .L19
.L23:
movl %ebp, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z29__device_stub__Z7j2d81ptPdS_iPdS_i
jmp .L20
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size host_code, .-host_code
.section .rodata.str1.1
.LC3:
.string "_Z7j2d81ptPdS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z7j2d81ptPdS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include "cuda.h"
#define max(x,y) ((x) > (y)? (x) : (y))
#define min(x,y) ((x) < (y)? (x) : (y))
#define ceil(a,b) ((a) % (b) == 0 ? (a) / (b) : ((a) / (b)) + 1)
void check_error (const char* message) {
cudaError_t error = cudaGetLastError ();
if (error != cudaSuccess) {
printf ("CUDA error : %s, %s\n", message, cudaGetErrorString (error));
exit(-1);
}
}
__global__ void j2d81pt (double * __restrict__ l_in, double * __restrict__ l_out, int N) {
//Determing the block's indices
int i0 = (int)(blockIdx.x)*(int)(blockDim.x);
int i = max(i0,0) + (int)(threadIdx.x);
int j0 = 4*(int)(blockIdx.y)*(int)(blockDim.y);
int j = max(j0,0) + 4*(int)(threadIdx.y);
double (*in)[8200] = (double (*)[8200]) l_in;
double (*out)[8200] = (double (*)[8200]) l_out;
if (i>=0 & j>=0 & i<=N-9 & j<=N-9) {
double _t_0_ = in[j][i];
_t_0_ += in[j][i+8];
_t_0_ += in[j+8][i];
double _t_15_ = in[j+8][i];
double _t_30_ = in[j+8][i];
double _t_45_ = in[j+8][i];
_t_0_ += in[j+8][i+8];
_t_15_ += in[j+8][i+8];
_t_30_ += in[j+8][i+8];
_t_45_ += in[j+8][i+8];
double outjc0ic0 = _t_0_ * 3.18622;
double _t_4_ = in[j][i+4];
_t_4_ += in[j+4][i+8];
double _t_17_ = in[j+4][i+8];
_t_30_ += in[j+4][i+8];
double _t_43_ = in[j+4][i+8];
_t_4_ += in[j+4][i];
_t_17_ += in[j+4][i];
_t_30_ += in[j+4][i];
_t_43_ += in[j+4][i];
_t_4_ += in[j+8][i+4];
double _t_22_ = in[j+8][i+4];
double _t_39_ = in[j+8][i+4];
double _t_55_ = in[j+8][i+4];
outjc0ic0 += _t_4_ * -0.00508225;
double _t_5_ = in[j+1][i+1];
_t_15_ += in[j+1][i+1];
_t_5_ += in[j+1][i+7];
_t_15_ += in[j+1][i+7];
_t_5_ += in[j+7][i+1];
double _t_20_ = in[j+7][i+1];
double _t_35_ = in[j+7][i+1];
double _t_50_ = in[j+7][i+1];
_t_5_ += in[j+7][i+7];
_t_20_ += in[j+7][i+7];
_t_35_ += in[j+7][i+7];
_t_50_ += in[j+7][i+7];
outjc0ic0 += _t_5_ * 0.00064516;
double _t_8_ = in[j+1][i+4];
double _t_18_ = in[j+1][i+4];
_t_8_ += in[j+4][i+1];
double _t_21_ = in[j+4][i+1];
double _t_34_ = in[j+4][i+1];
double _t_47_ = in[j+4][i+1];
_t_8_ += in[j+4][i+7];
_t_21_ += in[j+4][i+7];
_t_34_ += in[j+4][i+7];
_t_47_ += in[j+4][i+7];
_t_8_ += in[j+7][i+4];
double _t_25_ = in[j+7][i+4];
double _t_41_ = in[j+7][i+4];
double outjp3ic0 = in[j+7][i+4] * 8.10655;
outjc0ic0 += _t_8_ * -0.0723189;
double _t_9_ = in[j+2][i+2];
_t_20_ += in[j+2][i+2];
_t_30_ += in[j+2][i+2];
_t_9_ += in[j+2][i+6];
_t_20_ += in[j+2][i+6];
_t_30_ += in[j+2][i+6];
_t_9_ += in[j+6][i+2];
double _t_24_ = in[j+6][i+2];
_t_39_ += in[j+6][i+2];
double _t_52_ = in[j+6][i+2];
_t_9_ += in[j+6][i+6];
_t_24_ += in[j+6][i+6];
_t_39_ += in[j+6][i+6];
_t_52_ += in[j+6][i+6];
outjc0ic0 += _t_9_ * 0.04;
double _t_11_ = in[j+2][i+4];
_t_22_ += in[j+2][i+4];
double _t_32_ = in[j+2][i+4];
_t_11_ += in[j+4][i+2];
_t_24_ += in[j+4][i+2];
double _t_37_ = in[j+4][i+2];
double _t_48_ = in[j+4][i+2];
_t_11_ += in[j+4][i+6];
_t_24_ += in[j+4][i+6];
_t_37_ += in[j+4][i+6];
_t_48_ += in[j+4][i+6];
_t_11_ += in[j+6][i+4];
double _t_27_ = in[j+6][i+4];
double outjp2ic0 = in[j+6][i+4] * 8.10655;
_t_55_ += in[j+6][i+4];
outjc0ic0 += _t_11_ * 0.56944;
double _t_12_ = in[j+3][i+3];
_t_24_ += in[j+3][i+3];
_t_35_ += in[j+3][i+3];
_t_45_ += in[j+3][i+3];
_t_12_ += in[j+3][i+5];
_t_24_ += in[j+3][i+5];
_t_35_ += in[j+3][i+5];
_t_45_ += in[j+3][i+5];
_t_12_ += in[j+5][i+3];
_t_27_ += in[j+5][i+3];
double _t_40_ = in[j+5][i+3];
_t_52_ += in[j+5][i+3];
_t_12_ += in[j+5][i+5];
_t_27_ += in[j+5][i+5];
_t_40_ += in[j+5][i+5];
_t_52_ += in[j+5][i+5];
outjc0ic0 += _t_12_ * 2.56;
double _t_13_ = in[j+3][i+4];
_t_25_ += in[j+3][i+4];
double _t_36_ = in[j+3][i+4];
double _t_46_ = in[j+3][i+4];
_t_13_ += in[j+4][i+3];
double _t_26_ = in[j+4][i+3];
double _t_38_ = in[j+4][i+3];
double _t_49_ = in[j+4][i+3];
_t_13_ += in[j+4][i+5];
_t_26_ += in[j+4][i+5];
_t_38_ += in[j+4][i+5];
_t_49_ += in[j+4][i+5];
_t_13_ += in[j+5][i+4];
double outjp1ic0 = in[j+5][i+4] * 8.10655;
_t_41_ += in[j+5][i+4];
double _t_53_ = in[j+5][i+4];
outjc0ic0 += _t_13_ * -4.55552;
double _t_1_ = in[j][i+1];
_t_1_ += in[j][i+7];
_t_1_ += in[j+1][i];
double _t_14_ = in[j+1][i];
_t_1_ += in[j+1][i+8];
_t_14_ += in[j+1][i+8];
_t_1_ += in[j+7][i];
double _t_16_ = in[j+7][i];
double _t_31_ = in[j+7][i];
_t_46_ += in[j+7][i];
_t_1_ += in[j+7][i+8];
_t_16_ += in[j+7][i+8];
_t_31_ += in[j+7][i+8];
_t_46_ += in[j+7][i+8];
_t_1_ += in[j+8][i+1];
double _t_19_ = in[j+8][i+1];
_t_34_ += in[j+8][i+1];
_t_49_ += in[j+8][i+1];
_t_1_ += in[j+8][i+7];
_t_19_ += in[j+8][i+7];
_t_34_ += in[j+8][i+7];
_t_49_ += in[j+8][i+7];
outjc0ic0 += _t_1_ * 4.5339;
double _t_2_ = in[j][i+2];
_t_2_ += in[j][i+6];
_t_2_ += in[j+2][i];
_t_15_ += in[j+2][i];
double _t_28_ = in[j+2][i];
_t_2_ += in[j+2][i+8];
_t_15_ += in[j+2][i+8];
_t_28_ += in[j+2][i+8];
_t_2_ += in[j+6][i];
_t_17_ += in[j+6][i];
_t_32_ += in[j+6][i];
_t_45_ += in[j+6][i];
_t_2_ += in[j+6][i+8];
_t_17_ += in[j+6][i+8];
_t_32_ += in[j+6][i+8];
_t_45_ += in[j+6][i+8];
_t_2_ += in[j+8][i+2];
_t_20_ += in[j+8][i+2];
_t_37_ += in[j+8][i+2];
_t_52_ += in[j+8][i+2];
_t_2_ += in[j+8][i+6];
_t_20_ += in[j+8][i+6];
_t_37_ += in[j+8][i+6];
_t_52_ += in[j+8][i+6];
outjc0ic0 += _t_2_ * -0.000357;
double _t_3_ = in[j][i+3];
_t_3_ += in[j][i+5];
_t_3_ += in[j+3][i];
_t_16_ += in[j+3][i];
double _t_29_ = in[j+3][i];
double _t_42_ = in[j+3][i];
_t_3_ += in[j+3][i+8];
_t_16_ += in[j+3][i+8];
_t_29_ += in[j+3][i+8];
_t_42_ += in[j+3][i+8];
_t_3_ += in[j+5][i];
_t_18_ += in[j+5][i];
_t_31_ += in[j+5][i];
double _t_44_ = in[j+5][i];
_t_3_ += in[j+5][i+8];
_t_18_ += in[j+5][i+8];
_t_31_ += in[j+5][i+8];
_t_44_ += in[j+5][i+8];
_t_3_ += in[j+8][i+3];
_t_21_ += in[j+8][i+3];
_t_38_ += in[j+8][i+3];
double _t_54_ = in[j+8][i+3];
_t_3_ += in[j+8][i+5];
_t_21_ += in[j+8][i+5];
_t_38_ += in[j+8][i+5];
_t_54_ += in[j+8][i+5];
outjc0ic0 += _t_3_ * 0.002856;
double _t_6_ = in[j+1][i+2];
_t_16_ += in[j+1][i+2];
_t_6_ += in[j+1][i+6];
_t_16_ += in[j+1][i+6];
_t_6_ += in[j+2][i+1];
_t_19_ += in[j+2][i+1];
_t_29_ += in[j+2][i+1];
_t_6_ += in[j+2][i+7];
_t_19_ += in[j+2][i+7];
_t_29_ += in[j+2][i+7];
_t_6_ += in[j+6][i+1];
_t_21_ += in[j+6][i+1];
_t_36_ += in[j+6][i+1];
_t_49_ += in[j+6][i+1];
_t_6_ += in[j+6][i+7];
_t_21_ += in[j+6][i+7];
_t_36_ += in[j+6][i+7];
_t_49_ += in[j+6][i+7];
_t_6_ += in[j+7][i+2];
double _t_23_ = in[j+7][i+2];
_t_38_ += in[j+7][i+2];
_t_53_ += in[j+7][i+2];
_t_6_ += in[j+7][i+6];
_t_23_ += in[j+7][i+6];
_t_38_ += in[j+7][i+6];
_t_53_ += in[j+7][i+6];
outjc0ic0 += _t_6_ * -0.00508;
double _t_7_ = in[j+1][i+3];
_t_17_ += in[j+1][i+3];
_t_7_ += in[j+1][i+5];
_t_17_ += in[j+1][i+5];
_t_7_ += in[j+3][i+1];
_t_20_ += in[j+3][i+1];
double _t_33_ = in[j+3][i+1];
_t_43_ += in[j+3][i+1];
_t_7_ += in[j+3][i+7];
_t_20_ += in[j+3][i+7];
_t_33_ += in[j+3][i+7];
_t_43_ += in[j+3][i+7];
_t_7_ += in[j+5][i+1];
_t_22_ += in[j+5][i+1];
_t_35_ += in[j+5][i+1];
_t_48_ += in[j+5][i+1];
_t_7_ += in[j+5][i+7];
_t_22_ += in[j+5][i+7];
_t_35_ += in[j+5][i+7];
_t_48_ += in[j+5][i+7];
_t_7_ += in[j+7][i+3];
_t_24_ += in[j+7][i+3];
_t_40_ += in[j+7][i+3];
_t_55_ += in[j+7][i+3];
_t_7_ += in[j+7][i+5];
_t_24_ += in[j+7][i+5];
_t_40_ += in[j+7][i+5];
_t_55_ += in[j+7][i+5];
outjc0ic0 += _t_7_ * 0.04064;
double _t_10_ = in[j+2][i+3];
_t_21_ += in[j+2][i+3];
_t_31_ += in[j+2][i+3];
_t_10_ += in[j+2][i+5];
_t_21_ += in[j+2][i+5];
_t_31_ += in[j+2][i+5];
_t_10_ += in[j+3][i+2];
_t_23_ += in[j+3][i+2];
_t_34_ += in[j+3][i+2];
_t_44_ += in[j+3][i+2];
_t_10_ += in[j+3][i+6];
_t_23_ += in[j+3][i+6];
_t_34_ += in[j+3][i+6];
_t_44_ += in[j+3][i+6];
_t_10_ += in[j+5][i+2];
_t_25_ += in[j+5][i+2];
_t_38_ += in[j+5][i+2];
double _t_51_ = in[j+5][i+2];
_t_10_ += in[j+5][i+6];
_t_25_ += in[j+5][i+6];
_t_38_ += in[j+5][i+6];
_t_51_ += in[j+5][i+6];
_t_10_ += in[j+6][i+3];
_t_26_ += in[j+6][i+3];
_t_41_ += in[j+6][i+3];
_t_54_ += in[j+6][i+3];
_t_10_ += in[j+6][i+5];
_t_26_ += in[j+6][i+5];
_t_41_ += in[j+6][i+5];
_t_54_ += in[j+6][i+5];
outjc0ic0 += _t_10_ * -0.32;
outjc0ic0 += in[j+4][i+4] * 8.10655;
_t_27_ += in[j+4][i+4];
_t_39_ += in[j+4][i+4];
_t_50_ += in[j+4][i+4];
_t_14_ += in[j+9][i];
_t_29_ += in[j+9][i];
_t_45_ += in[j+11][i+3];
_t_45_ += in[j+11][i+5];
outjp3ic0 += _t_45_ * 0.002856;
_t_46_ += in[j+11][i+4];
outjp3ic0 += _t_46_ * -0.00508225;
_t_42_ += in[j+11][i];
_t_42_ += in[j+11][i+8];
outjp3ic0 += _t_42_ * 3.18622;
_t_14_ += in[j+9][i+8];
_t_29_ += in[j+9][i+8];
outjp1ic0 += _t_14_ * 3.18622;
_t_44_ += in[j+9][i];
_t_44_ += in[j+9][i+8];
_t_44_ += in[j+11][i+2];
_t_44_ += in[j+11][i+6];
outjp3ic0 += _t_44_ * -0.000357;
_t_15_ += in[j+9][i+1];
_t_48_ += in[j+9][i+1];
_t_15_ += in[j+9][i+7];
_t_48_ += in[j+9][i+7];
outjp1ic0 += _t_15_ * 4.5339;
_t_33_ += in[j+9][i+1];
_t_33_ += in[j+9][i+7];
outjp2ic0 += _t_33_ * 0.00064516;
_t_16_ += in[j+9][i+2];
_t_16_ += in[j+9][i+6];
outjp1ic0 += _t_16_ * -0.000357;
_t_34_ += in[j+9][i+2];
_t_34_ += in[j+9][i+6];
outjp2ic0 += _t_34_ * -0.00508;
_t_51_ += in[j+9][i+2];
_t_51_ += in[j+9][i+6];
outjp3ic0 += _t_51_ * 0.04;
_t_17_ += in[j+9][i+3];
_t_17_ += in[j+9][i+5];
outjp1ic0 += _t_17_ * 0.002856;
_t_35_ += in[j+9][i+3];
_t_35_ += in[j+9][i+5];
outjp2ic0 += _t_35_ * 0.04064;
_t_52_ += in[j+9][i+3];
_t_52_ += in[j+9][i+5];
outjp3ic0 += _t_52_ * -0.32;
_t_18_ += in[j+9][i+4];
_t_36_ += in[j+9][i+4];
outjp2ic0 += _t_36_ * -0.0723189;
_t_53_ += in[j+9][i+4];
outjp3ic0 += _t_53_ * 0.56944;
outjp1ic0 += _t_18_ * -0.00508225;
outjp1ic0 += _t_19_ * 0.00064516;
outjp1ic0 += _t_20_ * -0.00508;
outjp1ic0 += _t_21_ * 0.04064;
outjp1ic0 += _t_22_ * -0.0723189;
outjp1ic0 += _t_23_ * 0.04;
outjp1ic0 += _t_24_ * -0.32;
outjp1ic0 += _t_25_ * 0.56944;
outjp1ic0 += _t_26_ * 2.56;
outjp1ic0 += _t_27_ * -4.55552;
_t_28_ += in[j+10][i];
_t_28_ += in[j+10][i+8];
outjp2ic0 += _t_28_ * 3.18622;
_t_43_ += in[j+10][i];
_t_43_ += in[j+10][i+8];
_t_43_ += in[j+11][i+1];
_t_43_ += in[j+11][i+7];
outjp3ic0 += _t_43_ * 4.5339;
_t_29_ += in[j+10][i+1];
_t_29_ += in[j+10][i+7];
outjp2ic0 += _t_29_ * 4.5339;
_t_47_ += in[j+10][i+1];
_t_47_ += in[j+10][i+7];
outjp3ic0 += _t_47_ * 0.00064516;
_t_30_ += in[j+10][i+2];
_t_30_ += in[j+10][i+6];
outjp2ic0 += _t_30_ * -0.000357;
_t_48_ += in[j+10][i+2];
_t_48_ += in[j+10][i+6];
outjp3ic0 += _t_48_ * -0.00508;
_t_31_ += in[j+10][i+3];
_t_31_ += in[j+10][i+5];
outjp2ic0 += _t_31_ * 0.002856;
_t_49_ += in[j+10][i+3];
_t_49_ += in[j+10][i+5];
outjp3ic0 += _t_49_ * 0.04064;
_t_32_ += in[j+10][i+4];
_t_50_ += in[j+10][i+4];
outjp3ic0 += _t_50_ * -0.0723189;
outjp2ic0 += _t_32_ * -0.00508225;
outjp2ic0 += _t_37_ * 0.04;
outjp2ic0 += _t_38_ * -0.32;
outjp2ic0 += _t_39_ * 0.56944;
outjp2ic0 += _t_40_ * 2.56;
outjp2ic0 += _t_41_ * -4.55552;
outjp3ic0 += _t_54_ * 2.56;
outjp3ic0 += _t_55_ * -4.55552;
out[j][i] = outjc0ic0;
out[j+1][i] = outjp1ic0;
out[j+2][i] = outjp2ic0;
out[j+3][i] = outjp3ic0;
}
}
extern "C" void host_code (double *h_in, double *h_out, int N) {
double *in;
cudaMalloc (&in, sizeof(double)*N*N);
check_error ("Failed to allocate device memory for in\n");
cudaMemcpy (in, h_in, sizeof(double)*N*N, cudaMemcpyHostToDevice);
double *out;
cudaMalloc (&out, sizeof(double)*N*N);
check_error ("Failed to allocate device memory for out\n");
dim3 blockconfig (16, 8);
dim3 gridconfig (ceil(N, blockconfig.x), ceil(N, 4*blockconfig.y));
j2d81pt<<<gridconfig, blockconfig>>> (in, out, N);
cudaMemcpy (h_out, out, sizeof(double)*N*N, cudaMemcpyDeviceToHost);
cudaFree (in);
cudaFree (out);
} | #include <stdio.h>
#include "hip/hip_runtime.h"
#define max(x,y) ((x) > (y)? (x) : (y))
#define min(x,y) ((x) < (y)? (x) : (y))
#define ceil(a,b) ((a) % (b) == 0 ? (a) / (b) : ((a) / (b)) + 1)
void check_error (const char* message) {
hipError_t error = hipGetLastError ();
if (error != hipSuccess) {
printf ("CUDA error : %s, %s\n", message, hipGetErrorString (error));
exit(-1);
}
}
__global__ void j2d81pt (double * __restrict__ l_in, double * __restrict__ l_out, int N) {
//Determing the block's indices
int i0 = (int)(blockIdx.x)*(int)(blockDim.x);
int i = max(i0,0) + (int)(threadIdx.x);
int j0 = 4*(int)(blockIdx.y)*(int)(blockDim.y);
int j = max(j0,0) + 4*(int)(threadIdx.y);
double (*in)[8200] = (double (*)[8200]) l_in;
double (*out)[8200] = (double (*)[8200]) l_out;
if (i>=0 & j>=0 & i<=N-9 & j<=N-9) {
double _t_0_ = in[j][i];
_t_0_ += in[j][i+8];
_t_0_ += in[j+8][i];
double _t_15_ = in[j+8][i];
double _t_30_ = in[j+8][i];
double _t_45_ = in[j+8][i];
_t_0_ += in[j+8][i+8];
_t_15_ += in[j+8][i+8];
_t_30_ += in[j+8][i+8];
_t_45_ += in[j+8][i+8];
double outjc0ic0 = _t_0_ * 3.18622;
double _t_4_ = in[j][i+4];
_t_4_ += in[j+4][i+8];
double _t_17_ = in[j+4][i+8];
_t_30_ += in[j+4][i+8];
double _t_43_ = in[j+4][i+8];
_t_4_ += in[j+4][i];
_t_17_ += in[j+4][i];
_t_30_ += in[j+4][i];
_t_43_ += in[j+4][i];
_t_4_ += in[j+8][i+4];
double _t_22_ = in[j+8][i+4];
double _t_39_ = in[j+8][i+4];
double _t_55_ = in[j+8][i+4];
outjc0ic0 += _t_4_ * -0.00508225;
double _t_5_ = in[j+1][i+1];
_t_15_ += in[j+1][i+1];
_t_5_ += in[j+1][i+7];
_t_15_ += in[j+1][i+7];
_t_5_ += in[j+7][i+1];
double _t_20_ = in[j+7][i+1];
double _t_35_ = in[j+7][i+1];
double _t_50_ = in[j+7][i+1];
_t_5_ += in[j+7][i+7];
_t_20_ += in[j+7][i+7];
_t_35_ += in[j+7][i+7];
_t_50_ += in[j+7][i+7];
outjc0ic0 += _t_5_ * 0.00064516;
double _t_8_ = in[j+1][i+4];
double _t_18_ = in[j+1][i+4];
_t_8_ += in[j+4][i+1];
double _t_21_ = in[j+4][i+1];
double _t_34_ = in[j+4][i+1];
double _t_47_ = in[j+4][i+1];
_t_8_ += in[j+4][i+7];
_t_21_ += in[j+4][i+7];
_t_34_ += in[j+4][i+7];
_t_47_ += in[j+4][i+7];
_t_8_ += in[j+7][i+4];
double _t_25_ = in[j+7][i+4];
double _t_41_ = in[j+7][i+4];
double outjp3ic0 = in[j+7][i+4] * 8.10655;
outjc0ic0 += _t_8_ * -0.0723189;
double _t_9_ = in[j+2][i+2];
_t_20_ += in[j+2][i+2];
_t_30_ += in[j+2][i+2];
_t_9_ += in[j+2][i+6];
_t_20_ += in[j+2][i+6];
_t_30_ += in[j+2][i+6];
_t_9_ += in[j+6][i+2];
double _t_24_ = in[j+6][i+2];
_t_39_ += in[j+6][i+2];
double _t_52_ = in[j+6][i+2];
_t_9_ += in[j+6][i+6];
_t_24_ += in[j+6][i+6];
_t_39_ += in[j+6][i+6];
_t_52_ += in[j+6][i+6];
outjc0ic0 += _t_9_ * 0.04;
double _t_11_ = in[j+2][i+4];
_t_22_ += in[j+2][i+4];
double _t_32_ = in[j+2][i+4];
_t_11_ += in[j+4][i+2];
_t_24_ += in[j+4][i+2];
double _t_37_ = in[j+4][i+2];
double _t_48_ = in[j+4][i+2];
_t_11_ += in[j+4][i+6];
_t_24_ += in[j+4][i+6];
_t_37_ += in[j+4][i+6];
_t_48_ += in[j+4][i+6];
_t_11_ += in[j+6][i+4];
double _t_27_ = in[j+6][i+4];
double outjp2ic0 = in[j+6][i+4] * 8.10655;
_t_55_ += in[j+6][i+4];
outjc0ic0 += _t_11_ * 0.56944;
double _t_12_ = in[j+3][i+3];
_t_24_ += in[j+3][i+3];
_t_35_ += in[j+3][i+3];
_t_45_ += in[j+3][i+3];
_t_12_ += in[j+3][i+5];
_t_24_ += in[j+3][i+5];
_t_35_ += in[j+3][i+5];
_t_45_ += in[j+3][i+5];
_t_12_ += in[j+5][i+3];
_t_27_ += in[j+5][i+3];
double _t_40_ = in[j+5][i+3];
_t_52_ += in[j+5][i+3];
_t_12_ += in[j+5][i+5];
_t_27_ += in[j+5][i+5];
_t_40_ += in[j+5][i+5];
_t_52_ += in[j+5][i+5];
outjc0ic0 += _t_12_ * 2.56;
double _t_13_ = in[j+3][i+4];
_t_25_ += in[j+3][i+4];
double _t_36_ = in[j+3][i+4];
double _t_46_ = in[j+3][i+4];
_t_13_ += in[j+4][i+3];
double _t_26_ = in[j+4][i+3];
double _t_38_ = in[j+4][i+3];
double _t_49_ = in[j+4][i+3];
_t_13_ += in[j+4][i+5];
_t_26_ += in[j+4][i+5];
_t_38_ += in[j+4][i+5];
_t_49_ += in[j+4][i+5];
_t_13_ += in[j+5][i+4];
double outjp1ic0 = in[j+5][i+4] * 8.10655;
_t_41_ += in[j+5][i+4];
double _t_53_ = in[j+5][i+4];
outjc0ic0 += _t_13_ * -4.55552;
double _t_1_ = in[j][i+1];
_t_1_ += in[j][i+7];
_t_1_ += in[j+1][i];
double _t_14_ = in[j+1][i];
_t_1_ += in[j+1][i+8];
_t_14_ += in[j+1][i+8];
_t_1_ += in[j+7][i];
double _t_16_ = in[j+7][i];
double _t_31_ = in[j+7][i];
_t_46_ += in[j+7][i];
_t_1_ += in[j+7][i+8];
_t_16_ += in[j+7][i+8];
_t_31_ += in[j+7][i+8];
_t_46_ += in[j+7][i+8];
_t_1_ += in[j+8][i+1];
double _t_19_ = in[j+8][i+1];
_t_34_ += in[j+8][i+1];
_t_49_ += in[j+8][i+1];
_t_1_ += in[j+8][i+7];
_t_19_ += in[j+8][i+7];
_t_34_ += in[j+8][i+7];
_t_49_ += in[j+8][i+7];
outjc0ic0 += _t_1_ * 4.5339;
double _t_2_ = in[j][i+2];
_t_2_ += in[j][i+6];
_t_2_ += in[j+2][i];
_t_15_ += in[j+2][i];
double _t_28_ = in[j+2][i];
_t_2_ += in[j+2][i+8];
_t_15_ += in[j+2][i+8];
_t_28_ += in[j+2][i+8];
_t_2_ += in[j+6][i];
_t_17_ += in[j+6][i];
_t_32_ += in[j+6][i];
_t_45_ += in[j+6][i];
_t_2_ += in[j+6][i+8];
_t_17_ += in[j+6][i+8];
_t_32_ += in[j+6][i+8];
_t_45_ += in[j+6][i+8];
_t_2_ += in[j+8][i+2];
_t_20_ += in[j+8][i+2];
_t_37_ += in[j+8][i+2];
_t_52_ += in[j+8][i+2];
_t_2_ += in[j+8][i+6];
_t_20_ += in[j+8][i+6];
_t_37_ += in[j+8][i+6];
_t_52_ += in[j+8][i+6];
outjc0ic0 += _t_2_ * -0.000357;
double _t_3_ = in[j][i+3];
_t_3_ += in[j][i+5];
_t_3_ += in[j+3][i];
_t_16_ += in[j+3][i];
double _t_29_ = in[j+3][i];
double _t_42_ = in[j+3][i];
_t_3_ += in[j+3][i+8];
_t_16_ += in[j+3][i+8];
_t_29_ += in[j+3][i+8];
_t_42_ += in[j+3][i+8];
_t_3_ += in[j+5][i];
_t_18_ += in[j+5][i];
_t_31_ += in[j+5][i];
double _t_44_ = in[j+5][i];
_t_3_ += in[j+5][i+8];
_t_18_ += in[j+5][i+8];
_t_31_ += in[j+5][i+8];
_t_44_ += in[j+5][i+8];
_t_3_ += in[j+8][i+3];
_t_21_ += in[j+8][i+3];
_t_38_ += in[j+8][i+3];
double _t_54_ = in[j+8][i+3];
_t_3_ += in[j+8][i+5];
_t_21_ += in[j+8][i+5];
_t_38_ += in[j+8][i+5];
_t_54_ += in[j+8][i+5];
outjc0ic0 += _t_3_ * 0.002856;
double _t_6_ = in[j+1][i+2];
_t_16_ += in[j+1][i+2];
_t_6_ += in[j+1][i+6];
_t_16_ += in[j+1][i+6];
_t_6_ += in[j+2][i+1];
_t_19_ += in[j+2][i+1];
_t_29_ += in[j+2][i+1];
_t_6_ += in[j+2][i+7];
_t_19_ += in[j+2][i+7];
_t_29_ += in[j+2][i+7];
_t_6_ += in[j+6][i+1];
_t_21_ += in[j+6][i+1];
_t_36_ += in[j+6][i+1];
_t_49_ += in[j+6][i+1];
_t_6_ += in[j+6][i+7];
_t_21_ += in[j+6][i+7];
_t_36_ += in[j+6][i+7];
_t_49_ += in[j+6][i+7];
_t_6_ += in[j+7][i+2];
double _t_23_ = in[j+7][i+2];
_t_38_ += in[j+7][i+2];
_t_53_ += in[j+7][i+2];
_t_6_ += in[j+7][i+6];
_t_23_ += in[j+7][i+6];
_t_38_ += in[j+7][i+6];
_t_53_ += in[j+7][i+6];
outjc0ic0 += _t_6_ * -0.00508;
double _t_7_ = in[j+1][i+3];
_t_17_ += in[j+1][i+3];
_t_7_ += in[j+1][i+5];
_t_17_ += in[j+1][i+5];
_t_7_ += in[j+3][i+1];
_t_20_ += in[j+3][i+1];
double _t_33_ = in[j+3][i+1];
_t_43_ += in[j+3][i+1];
_t_7_ += in[j+3][i+7];
_t_20_ += in[j+3][i+7];
_t_33_ += in[j+3][i+7];
_t_43_ += in[j+3][i+7];
_t_7_ += in[j+5][i+1];
_t_22_ += in[j+5][i+1];
_t_35_ += in[j+5][i+1];
_t_48_ += in[j+5][i+1];
_t_7_ += in[j+5][i+7];
_t_22_ += in[j+5][i+7];
_t_35_ += in[j+5][i+7];
_t_48_ += in[j+5][i+7];
_t_7_ += in[j+7][i+3];
_t_24_ += in[j+7][i+3];
_t_40_ += in[j+7][i+3];
_t_55_ += in[j+7][i+3];
_t_7_ += in[j+7][i+5];
_t_24_ += in[j+7][i+5];
_t_40_ += in[j+7][i+5];
_t_55_ += in[j+7][i+5];
outjc0ic0 += _t_7_ * 0.04064;
double _t_10_ = in[j+2][i+3];
_t_21_ += in[j+2][i+3];
_t_31_ += in[j+2][i+3];
_t_10_ += in[j+2][i+5];
_t_21_ += in[j+2][i+5];
_t_31_ += in[j+2][i+5];
_t_10_ += in[j+3][i+2];
_t_23_ += in[j+3][i+2];
_t_34_ += in[j+3][i+2];
_t_44_ += in[j+3][i+2];
_t_10_ += in[j+3][i+6];
_t_23_ += in[j+3][i+6];
_t_34_ += in[j+3][i+6];
_t_44_ += in[j+3][i+6];
_t_10_ += in[j+5][i+2];
_t_25_ += in[j+5][i+2];
_t_38_ += in[j+5][i+2];
double _t_51_ = in[j+5][i+2];
_t_10_ += in[j+5][i+6];
_t_25_ += in[j+5][i+6];
_t_38_ += in[j+5][i+6];
_t_51_ += in[j+5][i+6];
_t_10_ += in[j+6][i+3];
_t_26_ += in[j+6][i+3];
_t_41_ += in[j+6][i+3];
_t_54_ += in[j+6][i+3];
_t_10_ += in[j+6][i+5];
_t_26_ += in[j+6][i+5];
_t_41_ += in[j+6][i+5];
_t_54_ += in[j+6][i+5];
outjc0ic0 += _t_10_ * -0.32;
outjc0ic0 += in[j+4][i+4] * 8.10655;
_t_27_ += in[j+4][i+4];
_t_39_ += in[j+4][i+4];
_t_50_ += in[j+4][i+4];
_t_14_ += in[j+9][i];
_t_29_ += in[j+9][i];
_t_45_ += in[j+11][i+3];
_t_45_ += in[j+11][i+5];
outjp3ic0 += _t_45_ * 0.002856;
_t_46_ += in[j+11][i+4];
outjp3ic0 += _t_46_ * -0.00508225;
_t_42_ += in[j+11][i];
_t_42_ += in[j+11][i+8];
outjp3ic0 += _t_42_ * 3.18622;
_t_14_ += in[j+9][i+8];
_t_29_ += in[j+9][i+8];
outjp1ic0 += _t_14_ * 3.18622;
_t_44_ += in[j+9][i];
_t_44_ += in[j+9][i+8];
_t_44_ += in[j+11][i+2];
_t_44_ += in[j+11][i+6];
outjp3ic0 += _t_44_ * -0.000357;
_t_15_ += in[j+9][i+1];
_t_48_ += in[j+9][i+1];
_t_15_ += in[j+9][i+7];
_t_48_ += in[j+9][i+7];
outjp1ic0 += _t_15_ * 4.5339;
_t_33_ += in[j+9][i+1];
_t_33_ += in[j+9][i+7];
outjp2ic0 += _t_33_ * 0.00064516;
_t_16_ += in[j+9][i+2];
_t_16_ += in[j+9][i+6];
outjp1ic0 += _t_16_ * -0.000357;
_t_34_ += in[j+9][i+2];
_t_34_ += in[j+9][i+6];
outjp2ic0 += _t_34_ * -0.00508;
_t_51_ += in[j+9][i+2];
_t_51_ += in[j+9][i+6];
outjp3ic0 += _t_51_ * 0.04;
_t_17_ += in[j+9][i+3];
_t_17_ += in[j+9][i+5];
outjp1ic0 += _t_17_ * 0.002856;
_t_35_ += in[j+9][i+3];
_t_35_ += in[j+9][i+5];
outjp2ic0 += _t_35_ * 0.04064;
_t_52_ += in[j+9][i+3];
_t_52_ += in[j+9][i+5];
outjp3ic0 += _t_52_ * -0.32;
_t_18_ += in[j+9][i+4];
_t_36_ += in[j+9][i+4];
outjp2ic0 += _t_36_ * -0.0723189;
_t_53_ += in[j+9][i+4];
outjp3ic0 += _t_53_ * 0.56944;
outjp1ic0 += _t_18_ * -0.00508225;
outjp1ic0 += _t_19_ * 0.00064516;
outjp1ic0 += _t_20_ * -0.00508;
outjp1ic0 += _t_21_ * 0.04064;
outjp1ic0 += _t_22_ * -0.0723189;
outjp1ic0 += _t_23_ * 0.04;
outjp1ic0 += _t_24_ * -0.32;
outjp1ic0 += _t_25_ * 0.56944;
outjp1ic0 += _t_26_ * 2.56;
outjp1ic0 += _t_27_ * -4.55552;
_t_28_ += in[j+10][i];
_t_28_ += in[j+10][i+8];
outjp2ic0 += _t_28_ * 3.18622;
_t_43_ += in[j+10][i];
_t_43_ += in[j+10][i+8];
_t_43_ += in[j+11][i+1];
_t_43_ += in[j+11][i+7];
outjp3ic0 += _t_43_ * 4.5339;
_t_29_ += in[j+10][i+1];
_t_29_ += in[j+10][i+7];
outjp2ic0 += _t_29_ * 4.5339;
_t_47_ += in[j+10][i+1];
_t_47_ += in[j+10][i+7];
outjp3ic0 += _t_47_ * 0.00064516;
_t_30_ += in[j+10][i+2];
_t_30_ += in[j+10][i+6];
outjp2ic0 += _t_30_ * -0.000357;
_t_48_ += in[j+10][i+2];
_t_48_ += in[j+10][i+6];
outjp3ic0 += _t_48_ * -0.00508;
_t_31_ += in[j+10][i+3];
_t_31_ += in[j+10][i+5];
outjp2ic0 += _t_31_ * 0.002856;
_t_49_ += in[j+10][i+3];
_t_49_ += in[j+10][i+5];
outjp3ic0 += _t_49_ * 0.04064;
_t_32_ += in[j+10][i+4];
_t_50_ += in[j+10][i+4];
outjp3ic0 += _t_50_ * -0.0723189;
outjp2ic0 += _t_32_ * -0.00508225;
outjp2ic0 += _t_37_ * 0.04;
outjp2ic0 += _t_38_ * -0.32;
outjp2ic0 += _t_39_ * 0.56944;
outjp2ic0 += _t_40_ * 2.56;
outjp2ic0 += _t_41_ * -4.55552;
outjp3ic0 += _t_54_ * 2.56;
outjp3ic0 += _t_55_ * -4.55552;
out[j][i] = outjc0ic0;
out[j+1][i] = outjp1ic0;
out[j+2][i] = outjp2ic0;
out[j+3][i] = outjp3ic0;
}
}
extern "C" void host_code (double *h_in, double *h_out, int N) {
double *in;
hipMalloc (&in, sizeof(double)*N*N);
check_error ("Failed to allocate device memory for in\n");
hipMemcpy (in, h_in, sizeof(double)*N*N, hipMemcpyHostToDevice);
double *out;
hipMalloc (&out, sizeof(double)*N*N);
check_error ("Failed to allocate device memory for out\n");
dim3 blockconfig (16, 8);
dim3 gridconfig (ceil(N, blockconfig.x), ceil(N, 4*blockconfig.y));
j2d81pt<<<gridconfig, blockconfig>>> (in, out, N);
hipMemcpy (h_out, out, sizeof(double)*N*N, hipMemcpyDeviceToHost);
hipFree (in);
hipFree (out);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include "hip/hip_runtime.h"
#define max(x,y) ((x) > (y)? (x) : (y))
#define min(x,y) ((x) < (y)? (x) : (y))
#define ceil(a,b) ((a) % (b) == 0 ? (a) / (b) : ((a) / (b)) + 1)
void check_error (const char* message) {
hipError_t error = hipGetLastError ();
if (error != hipSuccess) {
printf ("CUDA error : %s, %s\n", message, hipGetErrorString (error));
exit(-1);
}
}
__global__ void j2d81pt (double * __restrict__ l_in, double * __restrict__ l_out, int N) {
//Determing the block's indices
int i0 = (int)(blockIdx.x)*(int)(blockDim.x);
int i = max(i0,0) + (int)(threadIdx.x);
int j0 = 4*(int)(blockIdx.y)*(int)(blockDim.y);
int j = max(j0,0) + 4*(int)(threadIdx.y);
double (*in)[8200] = (double (*)[8200]) l_in;
double (*out)[8200] = (double (*)[8200]) l_out;
if (i>=0 & j>=0 & i<=N-9 & j<=N-9) {
double _t_0_ = in[j][i];
_t_0_ += in[j][i+8];
_t_0_ += in[j+8][i];
double _t_15_ = in[j+8][i];
double _t_30_ = in[j+8][i];
double _t_45_ = in[j+8][i];
_t_0_ += in[j+8][i+8];
_t_15_ += in[j+8][i+8];
_t_30_ += in[j+8][i+8];
_t_45_ += in[j+8][i+8];
double outjc0ic0 = _t_0_ * 3.18622;
double _t_4_ = in[j][i+4];
_t_4_ += in[j+4][i+8];
double _t_17_ = in[j+4][i+8];
_t_30_ += in[j+4][i+8];
double _t_43_ = in[j+4][i+8];
_t_4_ += in[j+4][i];
_t_17_ += in[j+4][i];
_t_30_ += in[j+4][i];
_t_43_ += in[j+4][i];
_t_4_ += in[j+8][i+4];
double _t_22_ = in[j+8][i+4];
double _t_39_ = in[j+8][i+4];
double _t_55_ = in[j+8][i+4];
outjc0ic0 += _t_4_ * -0.00508225;
double _t_5_ = in[j+1][i+1];
_t_15_ += in[j+1][i+1];
_t_5_ += in[j+1][i+7];
_t_15_ += in[j+1][i+7];
_t_5_ += in[j+7][i+1];
double _t_20_ = in[j+7][i+1];
double _t_35_ = in[j+7][i+1];
double _t_50_ = in[j+7][i+1];
_t_5_ += in[j+7][i+7];
_t_20_ += in[j+7][i+7];
_t_35_ += in[j+7][i+7];
_t_50_ += in[j+7][i+7];
outjc0ic0 += _t_5_ * 0.00064516;
double _t_8_ = in[j+1][i+4];
double _t_18_ = in[j+1][i+4];
_t_8_ += in[j+4][i+1];
double _t_21_ = in[j+4][i+1];
double _t_34_ = in[j+4][i+1];
double _t_47_ = in[j+4][i+1];
_t_8_ += in[j+4][i+7];
_t_21_ += in[j+4][i+7];
_t_34_ += in[j+4][i+7];
_t_47_ += in[j+4][i+7];
_t_8_ += in[j+7][i+4];
double _t_25_ = in[j+7][i+4];
double _t_41_ = in[j+7][i+4];
double outjp3ic0 = in[j+7][i+4] * 8.10655;
outjc0ic0 += _t_8_ * -0.0723189;
double _t_9_ = in[j+2][i+2];
_t_20_ += in[j+2][i+2];
_t_30_ += in[j+2][i+2];
_t_9_ += in[j+2][i+6];
_t_20_ += in[j+2][i+6];
_t_30_ += in[j+2][i+6];
_t_9_ += in[j+6][i+2];
double _t_24_ = in[j+6][i+2];
_t_39_ += in[j+6][i+2];
double _t_52_ = in[j+6][i+2];
_t_9_ += in[j+6][i+6];
_t_24_ += in[j+6][i+6];
_t_39_ += in[j+6][i+6];
_t_52_ += in[j+6][i+6];
outjc0ic0 += _t_9_ * 0.04;
double _t_11_ = in[j+2][i+4];
_t_22_ += in[j+2][i+4];
double _t_32_ = in[j+2][i+4];
_t_11_ += in[j+4][i+2];
_t_24_ += in[j+4][i+2];
double _t_37_ = in[j+4][i+2];
double _t_48_ = in[j+4][i+2];
_t_11_ += in[j+4][i+6];
_t_24_ += in[j+4][i+6];
_t_37_ += in[j+4][i+6];
_t_48_ += in[j+4][i+6];
_t_11_ += in[j+6][i+4];
double _t_27_ = in[j+6][i+4];
double outjp2ic0 = in[j+6][i+4] * 8.10655;
_t_55_ += in[j+6][i+4];
outjc0ic0 += _t_11_ * 0.56944;
double _t_12_ = in[j+3][i+3];
_t_24_ += in[j+3][i+3];
_t_35_ += in[j+3][i+3];
_t_45_ += in[j+3][i+3];
_t_12_ += in[j+3][i+5];
_t_24_ += in[j+3][i+5];
_t_35_ += in[j+3][i+5];
_t_45_ += in[j+3][i+5];
_t_12_ += in[j+5][i+3];
_t_27_ += in[j+5][i+3];
double _t_40_ = in[j+5][i+3];
_t_52_ += in[j+5][i+3];
_t_12_ += in[j+5][i+5];
_t_27_ += in[j+5][i+5];
_t_40_ += in[j+5][i+5];
_t_52_ += in[j+5][i+5];
outjc0ic0 += _t_12_ * 2.56;
double _t_13_ = in[j+3][i+4];
_t_25_ += in[j+3][i+4];
double _t_36_ = in[j+3][i+4];
double _t_46_ = in[j+3][i+4];
_t_13_ += in[j+4][i+3];
double _t_26_ = in[j+4][i+3];
double _t_38_ = in[j+4][i+3];
double _t_49_ = in[j+4][i+3];
_t_13_ += in[j+4][i+5];
_t_26_ += in[j+4][i+5];
_t_38_ += in[j+4][i+5];
_t_49_ += in[j+4][i+5];
_t_13_ += in[j+5][i+4];
double outjp1ic0 = in[j+5][i+4] * 8.10655;
_t_41_ += in[j+5][i+4];
double _t_53_ = in[j+5][i+4];
outjc0ic0 += _t_13_ * -4.55552;
double _t_1_ = in[j][i+1];
_t_1_ += in[j][i+7];
_t_1_ += in[j+1][i];
double _t_14_ = in[j+1][i];
_t_1_ += in[j+1][i+8];
_t_14_ += in[j+1][i+8];
_t_1_ += in[j+7][i];
double _t_16_ = in[j+7][i];
double _t_31_ = in[j+7][i];
_t_46_ += in[j+7][i];
_t_1_ += in[j+7][i+8];
_t_16_ += in[j+7][i+8];
_t_31_ += in[j+7][i+8];
_t_46_ += in[j+7][i+8];
_t_1_ += in[j+8][i+1];
double _t_19_ = in[j+8][i+1];
_t_34_ += in[j+8][i+1];
_t_49_ += in[j+8][i+1];
_t_1_ += in[j+8][i+7];
_t_19_ += in[j+8][i+7];
_t_34_ += in[j+8][i+7];
_t_49_ += in[j+8][i+7];
outjc0ic0 += _t_1_ * 4.5339;
double _t_2_ = in[j][i+2];
_t_2_ += in[j][i+6];
_t_2_ += in[j+2][i];
_t_15_ += in[j+2][i];
double _t_28_ = in[j+2][i];
_t_2_ += in[j+2][i+8];
_t_15_ += in[j+2][i+8];
_t_28_ += in[j+2][i+8];
_t_2_ += in[j+6][i];
_t_17_ += in[j+6][i];
_t_32_ += in[j+6][i];
_t_45_ += in[j+6][i];
_t_2_ += in[j+6][i+8];
_t_17_ += in[j+6][i+8];
_t_32_ += in[j+6][i+8];
_t_45_ += in[j+6][i+8];
_t_2_ += in[j+8][i+2];
_t_20_ += in[j+8][i+2];
_t_37_ += in[j+8][i+2];
_t_52_ += in[j+8][i+2];
_t_2_ += in[j+8][i+6];
_t_20_ += in[j+8][i+6];
_t_37_ += in[j+8][i+6];
_t_52_ += in[j+8][i+6];
outjc0ic0 += _t_2_ * -0.000357;
double _t_3_ = in[j][i+3];
_t_3_ += in[j][i+5];
_t_3_ += in[j+3][i];
_t_16_ += in[j+3][i];
double _t_29_ = in[j+3][i];
double _t_42_ = in[j+3][i];
_t_3_ += in[j+3][i+8];
_t_16_ += in[j+3][i+8];
_t_29_ += in[j+3][i+8];
_t_42_ += in[j+3][i+8];
_t_3_ += in[j+5][i];
_t_18_ += in[j+5][i];
_t_31_ += in[j+5][i];
double _t_44_ = in[j+5][i];
_t_3_ += in[j+5][i+8];
_t_18_ += in[j+5][i+8];
_t_31_ += in[j+5][i+8];
_t_44_ += in[j+5][i+8];
_t_3_ += in[j+8][i+3];
_t_21_ += in[j+8][i+3];
_t_38_ += in[j+8][i+3];
double _t_54_ = in[j+8][i+3];
_t_3_ += in[j+8][i+5];
_t_21_ += in[j+8][i+5];
_t_38_ += in[j+8][i+5];
_t_54_ += in[j+8][i+5];
outjc0ic0 += _t_3_ * 0.002856;
double _t_6_ = in[j+1][i+2];
_t_16_ += in[j+1][i+2];
_t_6_ += in[j+1][i+6];
_t_16_ += in[j+1][i+6];
_t_6_ += in[j+2][i+1];
_t_19_ += in[j+2][i+1];
_t_29_ += in[j+2][i+1];
_t_6_ += in[j+2][i+7];
_t_19_ += in[j+2][i+7];
_t_29_ += in[j+2][i+7];
_t_6_ += in[j+6][i+1];
_t_21_ += in[j+6][i+1];
_t_36_ += in[j+6][i+1];
_t_49_ += in[j+6][i+1];
_t_6_ += in[j+6][i+7];
_t_21_ += in[j+6][i+7];
_t_36_ += in[j+6][i+7];
_t_49_ += in[j+6][i+7];
_t_6_ += in[j+7][i+2];
double _t_23_ = in[j+7][i+2];
_t_38_ += in[j+7][i+2];
_t_53_ += in[j+7][i+2];
_t_6_ += in[j+7][i+6];
_t_23_ += in[j+7][i+6];
_t_38_ += in[j+7][i+6];
_t_53_ += in[j+7][i+6];
outjc0ic0 += _t_6_ * -0.00508;
double _t_7_ = in[j+1][i+3];
_t_17_ += in[j+1][i+3];
_t_7_ += in[j+1][i+5];
_t_17_ += in[j+1][i+5];
_t_7_ += in[j+3][i+1];
_t_20_ += in[j+3][i+1];
double _t_33_ = in[j+3][i+1];
_t_43_ += in[j+3][i+1];
_t_7_ += in[j+3][i+7];
_t_20_ += in[j+3][i+7];
_t_33_ += in[j+3][i+7];
_t_43_ += in[j+3][i+7];
_t_7_ += in[j+5][i+1];
_t_22_ += in[j+5][i+1];
_t_35_ += in[j+5][i+1];
_t_48_ += in[j+5][i+1];
_t_7_ += in[j+5][i+7];
_t_22_ += in[j+5][i+7];
_t_35_ += in[j+5][i+7];
_t_48_ += in[j+5][i+7];
_t_7_ += in[j+7][i+3];
_t_24_ += in[j+7][i+3];
_t_40_ += in[j+7][i+3];
_t_55_ += in[j+7][i+3];
_t_7_ += in[j+7][i+5];
_t_24_ += in[j+7][i+5];
_t_40_ += in[j+7][i+5];
_t_55_ += in[j+7][i+5];
outjc0ic0 += _t_7_ * 0.04064;
double _t_10_ = in[j+2][i+3];
_t_21_ += in[j+2][i+3];
_t_31_ += in[j+2][i+3];
_t_10_ += in[j+2][i+5];
_t_21_ += in[j+2][i+5];
_t_31_ += in[j+2][i+5];
_t_10_ += in[j+3][i+2];
_t_23_ += in[j+3][i+2];
_t_34_ += in[j+3][i+2];
_t_44_ += in[j+3][i+2];
_t_10_ += in[j+3][i+6];
_t_23_ += in[j+3][i+6];
_t_34_ += in[j+3][i+6];
_t_44_ += in[j+3][i+6];
_t_10_ += in[j+5][i+2];
_t_25_ += in[j+5][i+2];
_t_38_ += in[j+5][i+2];
double _t_51_ = in[j+5][i+2];
_t_10_ += in[j+5][i+6];
_t_25_ += in[j+5][i+6];
_t_38_ += in[j+5][i+6];
_t_51_ += in[j+5][i+6];
_t_10_ += in[j+6][i+3];
_t_26_ += in[j+6][i+3];
_t_41_ += in[j+6][i+3];
_t_54_ += in[j+6][i+3];
_t_10_ += in[j+6][i+5];
_t_26_ += in[j+6][i+5];
_t_41_ += in[j+6][i+5];
_t_54_ += in[j+6][i+5];
outjc0ic0 += _t_10_ * -0.32;
outjc0ic0 += in[j+4][i+4] * 8.10655;
_t_27_ += in[j+4][i+4];
_t_39_ += in[j+4][i+4];
_t_50_ += in[j+4][i+4];
_t_14_ += in[j+9][i];
_t_29_ += in[j+9][i];
_t_45_ += in[j+11][i+3];
_t_45_ += in[j+11][i+5];
outjp3ic0 += _t_45_ * 0.002856;
_t_46_ += in[j+11][i+4];
outjp3ic0 += _t_46_ * -0.00508225;
_t_42_ += in[j+11][i];
_t_42_ += in[j+11][i+8];
outjp3ic0 += _t_42_ * 3.18622;
_t_14_ += in[j+9][i+8];
_t_29_ += in[j+9][i+8];
outjp1ic0 += _t_14_ * 3.18622;
_t_44_ += in[j+9][i];
_t_44_ += in[j+9][i+8];
_t_44_ += in[j+11][i+2];
_t_44_ += in[j+11][i+6];
outjp3ic0 += _t_44_ * -0.000357;
_t_15_ += in[j+9][i+1];
_t_48_ += in[j+9][i+1];
_t_15_ += in[j+9][i+7];
_t_48_ += in[j+9][i+7];
outjp1ic0 += _t_15_ * 4.5339;
_t_33_ += in[j+9][i+1];
_t_33_ += in[j+9][i+7];
outjp2ic0 += _t_33_ * 0.00064516;
_t_16_ += in[j+9][i+2];
_t_16_ += in[j+9][i+6];
outjp1ic0 += _t_16_ * -0.000357;
_t_34_ += in[j+9][i+2];
_t_34_ += in[j+9][i+6];
outjp2ic0 += _t_34_ * -0.00508;
_t_51_ += in[j+9][i+2];
_t_51_ += in[j+9][i+6];
outjp3ic0 += _t_51_ * 0.04;
_t_17_ += in[j+9][i+3];
_t_17_ += in[j+9][i+5];
outjp1ic0 += _t_17_ * 0.002856;
_t_35_ += in[j+9][i+3];
_t_35_ += in[j+9][i+5];
outjp2ic0 += _t_35_ * 0.04064;
_t_52_ += in[j+9][i+3];
_t_52_ += in[j+9][i+5];
outjp3ic0 += _t_52_ * -0.32;
_t_18_ += in[j+9][i+4];
_t_36_ += in[j+9][i+4];
outjp2ic0 += _t_36_ * -0.0723189;
_t_53_ += in[j+9][i+4];
outjp3ic0 += _t_53_ * 0.56944;
outjp1ic0 += _t_18_ * -0.00508225;
outjp1ic0 += _t_19_ * 0.00064516;
outjp1ic0 += _t_20_ * -0.00508;
outjp1ic0 += _t_21_ * 0.04064;
outjp1ic0 += _t_22_ * -0.0723189;
outjp1ic0 += _t_23_ * 0.04;
outjp1ic0 += _t_24_ * -0.32;
outjp1ic0 += _t_25_ * 0.56944;
outjp1ic0 += _t_26_ * 2.56;
outjp1ic0 += _t_27_ * -4.55552;
_t_28_ += in[j+10][i];
_t_28_ += in[j+10][i+8];
outjp2ic0 += _t_28_ * 3.18622;
_t_43_ += in[j+10][i];
_t_43_ += in[j+10][i+8];
_t_43_ += in[j+11][i+1];
_t_43_ += in[j+11][i+7];
outjp3ic0 += _t_43_ * 4.5339;
_t_29_ += in[j+10][i+1];
_t_29_ += in[j+10][i+7];
outjp2ic0 += _t_29_ * 4.5339;
_t_47_ += in[j+10][i+1];
_t_47_ += in[j+10][i+7];
outjp3ic0 += _t_47_ * 0.00064516;
_t_30_ += in[j+10][i+2];
_t_30_ += in[j+10][i+6];
outjp2ic0 += _t_30_ * -0.000357;
_t_48_ += in[j+10][i+2];
_t_48_ += in[j+10][i+6];
outjp3ic0 += _t_48_ * -0.00508;
_t_31_ += in[j+10][i+3];
_t_31_ += in[j+10][i+5];
outjp2ic0 += _t_31_ * 0.002856;
_t_49_ += in[j+10][i+3];
_t_49_ += in[j+10][i+5];
outjp3ic0 += _t_49_ * 0.04064;
_t_32_ += in[j+10][i+4];
_t_50_ += in[j+10][i+4];
outjp3ic0 += _t_50_ * -0.0723189;
outjp2ic0 += _t_32_ * -0.00508225;
outjp2ic0 += _t_37_ * 0.04;
outjp2ic0 += _t_38_ * -0.32;
outjp2ic0 += _t_39_ * 0.56944;
outjp2ic0 += _t_40_ * 2.56;
outjp2ic0 += _t_41_ * -4.55552;
outjp3ic0 += _t_54_ * 2.56;
outjp3ic0 += _t_55_ * -4.55552;
out[j][i] = outjc0ic0;
out[j+1][i] = outjp1ic0;
out[j+2][i] = outjp2ic0;
out[j+3][i] = outjp3ic0;
}
}
extern "C" void host_code (double *h_in, double *h_out, int N) {
double *in;
hipMalloc (&in, sizeof(double)*N*N);
check_error ("Failed to allocate device memory for in\n");
hipMemcpy (in, h_in, sizeof(double)*N*N, hipMemcpyHostToDevice);
double *out;
hipMalloc (&out, sizeof(double)*N*N);
check_error ("Failed to allocate device memory for out\n");
dim3 blockconfig (16, 8);
dim3 gridconfig (ceil(N, blockconfig.x), ceil(N, 4*blockconfig.y));
j2d81pt<<<gridconfig, blockconfig>>> (in, out, N);
hipMemcpy (h_out, out, sizeof(double)*N*N, hipMemcpyDeviceToHost);
hipFree (in);
hipFree (out);
} | .text
.file "reordered-b.hip"
.globl _Z11check_errorPKc # -- Begin function _Z11check_errorPKc
.p2align 4, 0x90
.type _Z11check_errorPKc,@function
_Z11check_errorPKc: # @_Z11check_errorPKc
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
callq hipGetLastError
testl %eax, %eax
jne .LBB0_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 16
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rbx, %rsi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end0:
.size _Z11check_errorPKc, .Lfunc_end0-_Z11check_errorPKc
.cfi_endproc
# -- End function
.globl _Z22__device_stub__j2d81ptPdS_i # -- Begin function _Z22__device_stub__j2d81ptPdS_i
.p2align 4, 0x90
.type _Z22__device_stub__j2d81ptPdS_i,@function
_Z22__device_stub__j2d81ptPdS_i: # @_Z22__device_stub__j2d81ptPdS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7j2d81ptPdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z22__device_stub__j2d81ptPdS_i, .Lfunc_end1-_Z22__device_stub__j2d81ptPdS_i
.cfi_endproc
# -- End function
.globl host_code # -- Begin function host_code
.p2align 4, 0x90
.type host_code,@function
host_code: # @host_code
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movq %rsi, %r14
movq %rdi, %r15
movslq %edx, %rbx
imulq %rbx, %rbx
shlq $3, %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB2_1
# %bb.3: # %_Z11check_errorPKc.exit
movq 16(%rsp), %rdi
movq %r15, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB2_4
# %bb.5: # %_Z11check_errorPKc.exit23
movl %ebp, %eax
shrl $4, %eax
leal 1(%rax), %ecx
testb $15, %bpl
cmovel %eax, %ecx
movl %ebp, %eax
shrl $5, %eax
leal 1(%rax), %edi
testb $31, %bpl
cmovel %eax, %edi
shlq $32, %rdi
orq %rcx, %rdi
movabsq $34359738384, %rdx # imm = 0x800000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_7
# %bb.6:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %ebp, 28(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7j2d81ptPdS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_7:
movq 8(%rsp), %rsi
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 160
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
jmp .LBB2_2
.LBB2_4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.2, %esi
.LBB2_2:
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end2:
.size host_code, .Lfunc_end2-host_code
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7j2d81ptPdS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA error : %s, %s\n"
.size .L.str, 21
.type _Z7j2d81ptPdS_i,@object # @_Z7j2d81ptPdS_i
.section .rodata,"a",@progbits
.globl _Z7j2d81ptPdS_i
.p2align 3, 0x0
_Z7j2d81ptPdS_i:
.quad _Z22__device_stub__j2d81ptPdS_i
.size _Z7j2d81ptPdS_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Failed to allocate device memory for in\n"
.size .L.str.1, 41
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Failed to allocate device memory for out\n"
.size .L.str.2, 42
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7j2d81ptPdS_i"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__j2d81ptPdS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7j2d81ptPdS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00191f65_00000000-6_reordered-b.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA error : %s, %s\n"
.text
.globl _Z11check_errorPKc
.type _Z11check_errorPKc, @function
_Z11check_errorPKc:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movq %rbx, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z11check_errorPKc, .-_Z11check_errorPKc
.globl _Z29__device_stub__Z7j2d81ptPdS_iPdS_i
.type _Z29__device_stub__Z7j2d81ptPdS_iPdS_i, @function
_Z29__device_stub__Z7j2d81ptPdS_iPdS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 16(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7j2d81ptPdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z29__device_stub__Z7j2d81ptPdS_iPdS_i, .-_Z29__device_stub__Z7j2d81ptPdS_iPdS_i
.globl _Z7j2d81ptPdS_i
.type _Z7j2d81ptPdS_i, @function
_Z7j2d81ptPdS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7j2d81ptPdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7j2d81ptPdS_i, .-_Z7j2d81ptPdS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Failed to allocate device memory for in\n"
.align 8
.LC2:
.string "Failed to allocate device memory for out\n"
.text
.globl host_code
.type host_code, @function
host_code:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r13
movq %rsi, %r12
movl %edx, %ebp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movslq %edx, %rbx
imulq %rbx, %rbx
salq $3, %rbx
movq %rsp, %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC1(%rip), %rdi
call _Z11check_errorPKc
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC2(%rip), %rdi
call _Z11check_errorPKc
movl $1, 24(%rsp)
testb $31, %bpl
jne .L16
movl %ebp, %eax
shrl $5, %eax
.L17:
movl %ebp, %edx
shrl $4, %edx
.L19:
movl %edx, 28(%rsp)
movl %eax, 32(%rsp)
movl $16, 16(%rsp)
movl $8, 20(%rsp)
movl 24(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L20:
movl $2, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl %ebp, %eax
shrl $5, %eax
addl $1, %eax
testb $15, %bpl
je .L17
movl %ebp, %edx
shrl $4, %edx
addl $1, %edx
jmp .L19
.L23:
movl %ebp, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z29__device_stub__Z7j2d81ptPdS_iPdS_i
jmp .L20
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size host_code, .-host_code
.section .rodata.str1.1
.LC3:
.string "_Z7j2d81ptPdS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z7j2d81ptPdS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "reordered-b.hip"
.globl _Z11check_errorPKc # -- Begin function _Z11check_errorPKc
.p2align 4, 0x90
.type _Z11check_errorPKc,@function
_Z11check_errorPKc: # @_Z11check_errorPKc
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
callq hipGetLastError
testl %eax, %eax
jne .LBB0_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 16
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rbx, %rsi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end0:
.size _Z11check_errorPKc, .Lfunc_end0-_Z11check_errorPKc
.cfi_endproc
# -- End function
.globl _Z22__device_stub__j2d81ptPdS_i # -- Begin function _Z22__device_stub__j2d81ptPdS_i
.p2align 4, 0x90
.type _Z22__device_stub__j2d81ptPdS_i,@function
_Z22__device_stub__j2d81ptPdS_i: # @_Z22__device_stub__j2d81ptPdS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7j2d81ptPdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z22__device_stub__j2d81ptPdS_i, .Lfunc_end1-_Z22__device_stub__j2d81ptPdS_i
.cfi_endproc
# -- End function
.globl host_code # -- Begin function host_code
.p2align 4, 0x90
.type host_code,@function
host_code: # @host_code
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movq %rsi, %r14
movq %rdi, %r15
movslq %edx, %rbx
imulq %rbx, %rbx
shlq $3, %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB2_1
# %bb.3: # %_Z11check_errorPKc.exit
movq 16(%rsp), %rdi
movq %r15, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB2_4
# %bb.5: # %_Z11check_errorPKc.exit23
movl %ebp, %eax
shrl $4, %eax
leal 1(%rax), %ecx
testb $15, %bpl
cmovel %eax, %ecx
movl %ebp, %eax
shrl $5, %eax
leal 1(%rax), %edi
testb $31, %bpl
cmovel %eax, %edi
shlq $32, %rdi
orq %rcx, %rdi
movabsq $34359738384, %rdx # imm = 0x800000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_7
# %bb.6:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %ebp, 28(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7j2d81ptPdS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_7:
movq 8(%rsp), %rsi
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 160
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
jmp .LBB2_2
.LBB2_4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.2, %esi
.LBB2_2:
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end2:
.size host_code, .Lfunc_end2-host_code
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7j2d81ptPdS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA error : %s, %s\n"
.size .L.str, 21
.type _Z7j2d81ptPdS_i,@object # @_Z7j2d81ptPdS_i
.section .rodata,"a",@progbits
.globl _Z7j2d81ptPdS_i
.p2align 3, 0x0
_Z7j2d81ptPdS_i:
.quad _Z22__device_stub__j2d81ptPdS_i
.size _Z7j2d81ptPdS_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Failed to allocate device memory for in\n"
.size .L.str.1, 41
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Failed to allocate device memory for out\n"
.size .L.str.2, 42
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7j2d81ptPdS_i"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__j2d81ptPdS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7j2d81ptPdS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // CUDA programming
// Exercise n. 10
#include <errno.h>
#include <cuda.h>
#include <stdio.h>
#define N_ELEMS 16
#define THREADS 4
// Prototype
__global__ void dot_prod(int *a, int *b, int *c);
__host__ void ints(int *m, int N);
__host__ void print_array(int *a, int N);
int main(void)
{
int *a, *b, *c; // host copies of a, b, c
int *d_a, *d_b, *d_c; // device copies of a, b, c
int size = N_ELEMS * sizeof(int);
// Allocate space for host copies of a, b, c
a = (int *)malloc(size);
b = (int *)malloc(size);
c = (int *)malloc(sizeof(int));
// Setup input values
ints(a, N_ELEMS);
ints(b, N_ELEMS);
// Allocate space for device copies of a, b, c
cudaMalloc((void **)&d_a, size);
cudaMalloc((void **)&d_b, size);
cudaMalloc((void **)&d_c, sizeof(int));
// Copy inputs to device
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
// Call the kernel on GPU
dot_prod<<< N_ELEMS/THREADS, THREADS >>>(d_a, d_b, d_c);
// Copy result back to host
cudaMemcpy(c, d_c, sizeof(int), cudaMemcpyDeviceToHost);
// Check the result
print_array(a, N_ELEMS);
print_array(b, N_ELEMS);
printf("%d\n", *c);
// Cleanup
free(a);
free(b);
free(c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return(EXIT_SUCCESS);
}
// Vector addition (on device)
__global__ void dot_prod(int *a, int *b, int *c)
{
__shared__ int tmp[THREADS];
int index = blockIdx.x * blockDim.x + threadIdx.x;
tmp[threadIdx.x] = a[index] * b[index];
__syncthreads();
if(0 == threadIdx.x)
{
int sum = 0;
for(int i = 0; i < THREADS; i++)
{
sum += tmp[i];
}
atomicAdd(c, sum); // atomic operation to avoid race condition
}
}
// Initialisation
__host__ void ints(int *m, int N)
{
int i;
for(i = 0; i < N; i++)
m[i] = 1;
}
// Print the elements of the array
__host__ void print_array(int *a, int N)
{
for(int i = 0; i < N; i++)
{
printf("%d\t", a[i]);
}
printf("\n");
} | code for sm_80
Function : _Z8dot_prodPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R7 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0207 */
/*0060*/ IMAD.WIDE R4, R2, R3, c[0x0][0x168] ; /* 0x00005a0002047625 */
/* 0x000fc800078e0203 */
/*0070*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe400078e0203 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*00b0*/ IMAD R0, R4, R3, RZ ; /* 0x0000000304007224 */
/* 0x004fca00078e02ff */
/*00c0*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */
/* 0x0001e80000004800 */
/*00d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00f0*/ LDS.128 R4, [RZ] ; /* 0x00000000ff047984 */
/* 0x001e220000000c00 */
/*0100*/ MOV R2, c[0x0][0x170] ; /* 0x00005c0000027a02 */
/* 0x000fc40000000f00 */
/*0110*/ MOV R3, c[0x0][0x174] ; /* 0x00005d0000037a02 */
/* 0x000fe40000000f00 */
/*0120*/ IADD3 R0, R6, R5, R4 ; /* 0x0000000506007210 */
/* 0x001fc80007ffe004 */
/*0130*/ IADD3 R5, R0, R7, RZ ; /* 0x0000000700057210 */
/* 0x000fca0007ffe0ff */
/*0140*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x000fe2000c10e184 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // CUDA programming
// Exercise n. 10
#include <errno.h>
#include <cuda.h>
#include <stdio.h>
#define N_ELEMS 16
#define THREADS 4
// Prototype
__global__ void dot_prod(int *a, int *b, int *c);
__host__ void ints(int *m, int N);
__host__ void print_array(int *a, int N);
int main(void)
{
int *a, *b, *c; // host copies of a, b, c
int *d_a, *d_b, *d_c; // device copies of a, b, c
int size = N_ELEMS * sizeof(int);
// Allocate space for host copies of a, b, c
a = (int *)malloc(size);
b = (int *)malloc(size);
c = (int *)malloc(sizeof(int));
// Setup input values
ints(a, N_ELEMS);
ints(b, N_ELEMS);
// Allocate space for device copies of a, b, c
cudaMalloc((void **)&d_a, size);
cudaMalloc((void **)&d_b, size);
cudaMalloc((void **)&d_c, sizeof(int));
// Copy inputs to device
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
// Call the kernel on GPU
dot_prod<<< N_ELEMS/THREADS, THREADS >>>(d_a, d_b, d_c);
// Copy result back to host
cudaMemcpy(c, d_c, sizeof(int), cudaMemcpyDeviceToHost);
// Check the result
print_array(a, N_ELEMS);
print_array(b, N_ELEMS);
printf("%d\n", *c);
// Cleanup
free(a);
free(b);
free(c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return(EXIT_SUCCESS);
}
// Vector addition (on device)
__global__ void dot_prod(int *a, int *b, int *c)
{
__shared__ int tmp[THREADS];
int index = blockIdx.x * blockDim.x + threadIdx.x;
tmp[threadIdx.x] = a[index] * b[index];
__syncthreads();
if(0 == threadIdx.x)
{
int sum = 0;
for(int i = 0; i < THREADS; i++)
{
sum += tmp[i];
}
atomicAdd(c, sum); // atomic operation to avoid race condition
}
}
// Initialisation
__host__ void ints(int *m, int N)
{
int i;
for(i = 0; i < N; i++)
m[i] = 1;
}
// Print the elements of the array
__host__ void print_array(int *a, int N)
{
for(int i = 0; i < N; i++)
{
printf("%d\t", a[i]);
}
printf("\n");
} | .file "tmpxft_000341df_00000000-6_ex10.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4intsPii
.type _Z4intsPii, @function
_Z4intsPii:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L3
movq %rdi, %rax
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rdx
.L5:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2058:
.size _Z4intsPii, .-_Z4intsPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d\t"
.LC1:
.string "\n"
.text
.globl _Z11print_arrayPii
.type _Z11print_arrayPii, @function
_Z11print_arrayPii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
testl %esi, %esi
jle .L8
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %r12
leaq .LC0(%rip), %rbp
.L9:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L9
.L8:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z11print_arrayPii, .-_Z11print_arrayPii
.globl _Z31__device_stub__Z8dot_prodPiS_S_PiS_S_
.type _Z31__device_stub__Z8dot_prodPiS_S_PiS_S_, @function
_Z31__device_stub__Z8dot_prodPiS_S_PiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8dot_prodPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z31__device_stub__Z8dot_prodPiS_S_PiS_S_, .-_Z31__device_stub__Z8dot_prodPiS_S_PiS_S_
.globl _Z8dot_prodPiS_S_
.type _Z8dot_prodPiS_S_, @function
_Z8dot_prodPiS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8dot_prodPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z8dot_prodPiS_S_, .-_Z8dot_prodPiS_S_
.section .rodata.str1.1
.LC2:
.string "%d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $64, %edi
call malloc@PLT
movq %rax, %rbp
movl $64, %edi
call malloc@PLT
movq %rax, %rbx
movl $4, %edi
call malloc@PLT
movq %rax, %r12
movl $16, %esi
movq %rbp, %rdi
call _Z4intsPii
movl $16, %esi
movq %rbx, %rdi
call _Z4intsPii
leaq 8(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $64, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $64, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 44(%rsp)
movl $1, 48(%rsp)
movl $4, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L21:
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $16, %esi
movq %rbp, %rdi
call _Z11print_arrayPii
movl $16, %esi
movq %rbx, %rdi
call _Z11print_arrayPii
movl (%r12), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z31__device_stub__Z8dot_prodPiS_S_PiS_S_
jmp .L21
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z8dot_prodPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z8dot_prodPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // CUDA programming
// Exercise n. 10
#include <errno.h>
#include <cuda.h>
#include <stdio.h>
#define N_ELEMS 16
#define THREADS 4
// Prototype
__global__ void dot_prod(int *a, int *b, int *c);
__host__ void ints(int *m, int N);
__host__ void print_array(int *a, int N);
int main(void)
{
int *a, *b, *c; // host copies of a, b, c
int *d_a, *d_b, *d_c; // device copies of a, b, c
int size = N_ELEMS * sizeof(int);
// Allocate space for host copies of a, b, c
a = (int *)malloc(size);
b = (int *)malloc(size);
c = (int *)malloc(sizeof(int));
// Setup input values
ints(a, N_ELEMS);
ints(b, N_ELEMS);
// Allocate space for device copies of a, b, c
cudaMalloc((void **)&d_a, size);
cudaMalloc((void **)&d_b, size);
cudaMalloc((void **)&d_c, sizeof(int));
// Copy inputs to device
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
// Call the kernel on GPU
dot_prod<<< N_ELEMS/THREADS, THREADS >>>(d_a, d_b, d_c);
// Copy result back to host
cudaMemcpy(c, d_c, sizeof(int), cudaMemcpyDeviceToHost);
// Check the result
print_array(a, N_ELEMS);
print_array(b, N_ELEMS);
printf("%d\n", *c);
// Cleanup
free(a);
free(b);
free(c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return(EXIT_SUCCESS);
}
// Vector addition (on device)
__global__ void dot_prod(int *a, int *b, int *c)
{
__shared__ int tmp[THREADS];
int index = blockIdx.x * blockDim.x + threadIdx.x;
tmp[threadIdx.x] = a[index] * b[index];
__syncthreads();
if(0 == threadIdx.x)
{
int sum = 0;
for(int i = 0; i < THREADS; i++)
{
sum += tmp[i];
}
atomicAdd(c, sum); // atomic operation to avoid race condition
}
}
// Initialisation
__host__ void ints(int *m, int N)
{
int i;
for(i = 0; i < N; i++)
m[i] = 1;
}
// Print the elements of the array
__host__ void print_array(int *a, int N)
{
for(int i = 0; i < N; i++)
{
printf("%d\t", a[i]);
}
printf("\n");
} | // CUDA programming
// Exercise n. 10
#include <errno.h>
#include <hip/hip_runtime.h>
#include <stdio.h>
#define N_ELEMS 16
#define THREADS 4
// Prototype
__global__ void dot_prod(int *a, int *b, int *c);
__host__ void ints(int *m, int N);
__host__ void print_array(int *a, int N);
int main(void)
{
int *a, *b, *c; // host copies of a, b, c
int *d_a, *d_b, *d_c; // device copies of a, b, c
int size = N_ELEMS * sizeof(int);
// Allocate space for host copies of a, b, c
a = (int *)malloc(size);
b = (int *)malloc(size);
c = (int *)malloc(sizeof(int));
// Setup input values
ints(a, N_ELEMS);
ints(b, N_ELEMS);
// Allocate space for device copies of a, b, c
hipMalloc((void **)&d_a, size);
hipMalloc((void **)&d_b, size);
hipMalloc((void **)&d_c, sizeof(int));
// Copy inputs to device
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
// Call the kernel on GPU
dot_prod<<< N_ELEMS/THREADS, THREADS >>>(d_a, d_b, d_c);
// Copy result back to host
hipMemcpy(c, d_c, sizeof(int), hipMemcpyDeviceToHost);
// Check the result
print_array(a, N_ELEMS);
print_array(b, N_ELEMS);
printf("%d\n", *c);
// Cleanup
free(a);
free(b);
free(c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return(EXIT_SUCCESS);
}
// Vector addition (on device)
__global__ void dot_prod(int *a, int *b, int *c)
{
__shared__ int tmp[THREADS];
int index = blockIdx.x * blockDim.x + threadIdx.x;
tmp[threadIdx.x] = a[index] * b[index];
__syncthreads();
if(0 == threadIdx.x)
{
int sum = 0;
for(int i = 0; i < THREADS; i++)
{
sum += tmp[i];
}
atomicAdd(c, sum); // atomic operation to avoid race condition
}
}
// Initialisation
__host__ void ints(int *m, int N)
{
int i;
for(i = 0; i < N; i++)
m[i] = 1;
}
// Print the elements of the array
__host__ void print_array(int *a, int N)
{
for(int i = 0; i < N; i++)
{
printf("%d\t", a[i]);
}
printf("\n");
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // CUDA programming
// Exercise n. 10
#include <errno.h>
#include <hip/hip_runtime.h>
#include <stdio.h>
#define N_ELEMS 16
#define THREADS 4
// Prototype
__global__ void dot_prod(int *a, int *b, int *c);
__host__ void ints(int *m, int N);
__host__ void print_array(int *a, int N);
int main(void)
{
int *a, *b, *c; // host copies of a, b, c
int *d_a, *d_b, *d_c; // device copies of a, b, c
int size = N_ELEMS * sizeof(int);
// Allocate space for host copies of a, b, c
a = (int *)malloc(size);
b = (int *)malloc(size);
c = (int *)malloc(sizeof(int));
// Setup input values
ints(a, N_ELEMS);
ints(b, N_ELEMS);
// Allocate space for device copies of a, b, c
hipMalloc((void **)&d_a, size);
hipMalloc((void **)&d_b, size);
hipMalloc((void **)&d_c, sizeof(int));
// Copy inputs to device
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
// Call the kernel on GPU
dot_prod<<< N_ELEMS/THREADS, THREADS >>>(d_a, d_b, d_c);
// Copy result back to host
hipMemcpy(c, d_c, sizeof(int), hipMemcpyDeviceToHost);
// Check the result
print_array(a, N_ELEMS);
print_array(b, N_ELEMS);
printf("%d\n", *c);
// Cleanup
free(a);
free(b);
free(c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return(EXIT_SUCCESS);
}
// Vector addition (on device)
__global__ void dot_prod(int *a, int *b, int *c)
{
__shared__ int tmp[THREADS];
int index = blockIdx.x * blockDim.x + threadIdx.x;
tmp[threadIdx.x] = a[index] * b[index];
__syncthreads();
if(0 == threadIdx.x)
{
int sum = 0;
for(int i = 0; i < THREADS; i++)
{
sum += tmp[i];
}
atomicAdd(c, sum); // atomic operation to avoid race condition
}
}
// Initialisation
__host__ void ints(int *m, int N)
{
int i;
for(i = 0; i < N; i++)
m[i] = 1;
}
// Print the elements of the array
__host__ void print_array(int *a, int N)
{
for(int i = 0; i < N; i++)
{
printf("%d\t", a[i]);
}
printf("\n");
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8dot_prodPiS_S_
.globl _Z8dot_prodPiS_S_
.p2align 8
.type _Z8dot_prodPiS_S_,@function
_Z8dot_prodPiS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, 0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v3, v[3:4], off
global_load_b32 v1, v[1:2], off
v_lshlrev_b32_e32 v2, 2, v0
s_waitcnt vmcnt(0)
v_mul_lo_u32 v1, v1, v3
ds_store_b32 v2, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v0, 0
.LBB0_2:
v_mov_b32_e32 v1, s2
s_add_i32 s2, s2, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 16
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v0, v1, v0
s_cbranch_scc0 .LBB0_2
s_mov_b32 s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mbcnt_lo_u32_b32 v1, s2, 0
v_cmp_eq_u32_e32 vcc_lo, 0, v1
s_and_b32 s3, exec_lo, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 exec_lo, s3
s_cbranch_execz .LBB0_5
s_load_b64 s[0:1], s[0:1], 0x10
s_bcnt1_i32_b32 s2, s2
v_mov_b32_e32 v1, 0
v_mul_lo_u32 v0, v0, s2
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v1, v0, s[0:1]
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8dot_prodPiS_S_
.amdhsa_group_segment_fixed_size 16
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8dot_prodPiS_S_, .Lfunc_end0-_Z8dot_prodPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 16
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8dot_prodPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8dot_prodPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // CUDA programming
// Exercise n. 10
#include <errno.h>
#include <hip/hip_runtime.h>
#include <stdio.h>
#define N_ELEMS 16
#define THREADS 4
// Prototype
__global__ void dot_prod(int *a, int *b, int *c);
__host__ void ints(int *m, int N);
__host__ void print_array(int *a, int N);
int main(void)
{
int *a, *b, *c; // host copies of a, b, c
int *d_a, *d_b, *d_c; // device copies of a, b, c
int size = N_ELEMS * sizeof(int);
// Allocate space for host copies of a, b, c
a = (int *)malloc(size);
b = (int *)malloc(size);
c = (int *)malloc(sizeof(int));
// Setup input values
ints(a, N_ELEMS);
ints(b, N_ELEMS);
// Allocate space for device copies of a, b, c
hipMalloc((void **)&d_a, size);
hipMalloc((void **)&d_b, size);
hipMalloc((void **)&d_c, sizeof(int));
// Copy inputs to device
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
// Call the kernel on GPU
dot_prod<<< N_ELEMS/THREADS, THREADS >>>(d_a, d_b, d_c);
// Copy result back to host
hipMemcpy(c, d_c, sizeof(int), hipMemcpyDeviceToHost);
// Check the result
print_array(a, N_ELEMS);
print_array(b, N_ELEMS);
printf("%d\n", *c);
// Cleanup
free(a);
free(b);
free(c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return(EXIT_SUCCESS);
}
// Vector addition (on device)
__global__ void dot_prod(int *a, int *b, int *c)
{
__shared__ int tmp[THREADS];
int index = blockIdx.x * blockDim.x + threadIdx.x;
tmp[threadIdx.x] = a[index] * b[index];
__syncthreads();
if(0 == threadIdx.x)
{
int sum = 0;
for(int i = 0; i < THREADS; i++)
{
sum += tmp[i];
}
atomicAdd(c, sum); // atomic operation to avoid race condition
}
}
// Initialisation
__host__ void ints(int *m, int N)
{
int i;
for(i = 0; i < N; i++)
m[i] = 1;
}
// Print the elements of the array
__host__ void print_array(int *a, int N)
{
for(int i = 0; i < N; i++)
{
printf("%d\t", a[i]);
}
printf("\n");
} | .text
.file "ex10.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $64, %edi
callq malloc
movq %rax, %rbx
movl $64, %edi
callq malloc
movq %rax, %r14
movl $4, %edi
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl $1, (%rbx,%rax,4)
incq %rax
cmpq $16, %rax
jne .LBB0_1
# %bb.2: # %.lr.ph.i18.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_3: # %.lr.ph.i18
# =>This Inner Loop Header: Depth=1
movl $1, (%r14,%rax,4)
incq %rax
cmpq $16, %rax
jne .LBB0_3
# %bb.4: # %_Z4intsPii.exit22
leaq 16(%rsp), %rdi
movl $64, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movq 16(%rsp), %rdi
movl $64, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $64, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967300, %rdi # imm = 0x100000004
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8dot_prodPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_6:
movq (%rsp), %rsi
movl $4, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_7: # %.lr.ph.i23
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r12,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $16, %r12
jne .LBB0_7
# %bb.8: # %_Z11print_arrayPii.exit
movl $10, %edi
callq putchar@PLT
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_9: # %.lr.ph.i27
# =>This Inner Loop Header: Depth=1
movl (%r14,%r12,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $16, %r12
jne .LBB0_9
# %bb.10: # %_Z11print_arrayPii.exit32
movl $10, %edi
callq putchar@PLT
movl (%r15), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z4intsPii # -- Begin function _Z4intsPii
.p2align 4, 0x90
.type _Z4intsPii,@function
_Z4intsPii: # @_Z4intsPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $1, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z4intsPii, .Lfunc_end1-_Z4intsPii
.cfi_endproc
# -- End function
.globl _Z23__device_stub__dot_prodPiS_S_ # -- Begin function _Z23__device_stub__dot_prodPiS_S_
.p2align 4, 0x90
.type _Z23__device_stub__dot_prodPiS_S_,@function
_Z23__device_stub__dot_prodPiS_S_: # @_Z23__device_stub__dot_prodPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8dot_prodPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z23__device_stub__dot_prodPiS_S_, .Lfunc_end2-_Z23__device_stub__dot_prodPiS_S_
.cfi_endproc
# -- End function
.globl _Z11print_arrayPii # -- Begin function _Z11print_arrayPii
.p2align 4, 0x90
.type _Z11print_arrayPii,@function
_Z11print_arrayPii: # @_Z11print_arrayPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB3_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB3_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB3_4: # %._crit_edge
movl $10, %edi
jmp putchar@PLT # TAILCALL
.Lfunc_end3:
.size _Z11print_arrayPii, .Lfunc_end3-_Z11print_arrayPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8dot_prodPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8dot_prodPiS_S_,@object # @_Z8dot_prodPiS_S_
.section .rodata,"a",@progbits
.globl _Z8dot_prodPiS_S_
.p2align 3, 0x0
_Z8dot_prodPiS_S_:
.quad _Z23__device_stub__dot_prodPiS_S_
.size _Z8dot_prodPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d\n"
.size .L.str, 4
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d\t"
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8dot_prodPiS_S_"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__dot_prodPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8dot_prodPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8dot_prodPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R7 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0207 */
/*0060*/ IMAD.WIDE R4, R2, R3, c[0x0][0x168] ; /* 0x00005a0002047625 */
/* 0x000fc800078e0203 */
/*0070*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe400078e0203 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*00b0*/ IMAD R0, R4, R3, RZ ; /* 0x0000000304007224 */
/* 0x004fca00078e02ff */
/*00c0*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */
/* 0x0001e80000004800 */
/*00d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00f0*/ LDS.128 R4, [RZ] ; /* 0x00000000ff047984 */
/* 0x001e220000000c00 */
/*0100*/ MOV R2, c[0x0][0x170] ; /* 0x00005c0000027a02 */
/* 0x000fc40000000f00 */
/*0110*/ MOV R3, c[0x0][0x174] ; /* 0x00005d0000037a02 */
/* 0x000fe40000000f00 */
/*0120*/ IADD3 R0, R6, R5, R4 ; /* 0x0000000506007210 */
/* 0x001fc80007ffe004 */
/*0130*/ IADD3 R5, R0, R7, RZ ; /* 0x0000000700057210 */
/* 0x000fca0007ffe0ff */
/*0140*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x000fe2000c10e184 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8dot_prodPiS_S_
.globl _Z8dot_prodPiS_S_
.p2align 8
.type _Z8dot_prodPiS_S_,@function
_Z8dot_prodPiS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, 0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v3, v[3:4], off
global_load_b32 v1, v[1:2], off
v_lshlrev_b32_e32 v2, 2, v0
s_waitcnt vmcnt(0)
v_mul_lo_u32 v1, v1, v3
ds_store_b32 v2, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v0, 0
.LBB0_2:
v_mov_b32_e32 v1, s2
s_add_i32 s2, s2, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 16
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v0, v1, v0
s_cbranch_scc0 .LBB0_2
s_mov_b32 s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mbcnt_lo_u32_b32 v1, s2, 0
v_cmp_eq_u32_e32 vcc_lo, 0, v1
s_and_b32 s3, exec_lo, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 exec_lo, s3
s_cbranch_execz .LBB0_5
s_load_b64 s[0:1], s[0:1], 0x10
s_bcnt1_i32_b32 s2, s2
v_mov_b32_e32 v1, 0
v_mul_lo_u32 v0, v0, s2
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v1, v0, s[0:1]
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8dot_prodPiS_S_
.amdhsa_group_segment_fixed_size 16
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8dot_prodPiS_S_, .Lfunc_end0-_Z8dot_prodPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 16
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8dot_prodPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8dot_prodPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000341df_00000000-6_ex10.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4intsPii
.type _Z4intsPii, @function
_Z4intsPii:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L3
movq %rdi, %rax
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rdx
.L5:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2058:
.size _Z4intsPii, .-_Z4intsPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d\t"
.LC1:
.string "\n"
.text
.globl _Z11print_arrayPii
.type _Z11print_arrayPii, @function
_Z11print_arrayPii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
testl %esi, %esi
jle .L8
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %r12
leaq .LC0(%rip), %rbp
.L9:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L9
.L8:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z11print_arrayPii, .-_Z11print_arrayPii
.globl _Z31__device_stub__Z8dot_prodPiS_S_PiS_S_
.type _Z31__device_stub__Z8dot_prodPiS_S_PiS_S_, @function
_Z31__device_stub__Z8dot_prodPiS_S_PiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8dot_prodPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z31__device_stub__Z8dot_prodPiS_S_PiS_S_, .-_Z31__device_stub__Z8dot_prodPiS_S_PiS_S_
.globl _Z8dot_prodPiS_S_
.type _Z8dot_prodPiS_S_, @function
_Z8dot_prodPiS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8dot_prodPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z8dot_prodPiS_S_, .-_Z8dot_prodPiS_S_
.section .rodata.str1.1
.LC2:
.string "%d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $64, %edi
call malloc@PLT
movq %rax, %rbp
movl $64, %edi
call malloc@PLT
movq %rax, %rbx
movl $4, %edi
call malloc@PLT
movq %rax, %r12
movl $16, %esi
movq %rbp, %rdi
call _Z4intsPii
movl $16, %esi
movq %rbx, %rdi
call _Z4intsPii
leaq 8(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $64, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $64, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 44(%rsp)
movl $1, 48(%rsp)
movl $4, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L21:
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $16, %esi
movq %rbp, %rdi
call _Z11print_arrayPii
movl $16, %esi
movq %rbx, %rdi
call _Z11print_arrayPii
movl (%r12), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z31__device_stub__Z8dot_prodPiS_S_PiS_S_
jmp .L21
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z8dot_prodPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z8dot_prodPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ex10.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $64, %edi
callq malloc
movq %rax, %rbx
movl $64, %edi
callq malloc
movq %rax, %r14
movl $4, %edi
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl $1, (%rbx,%rax,4)
incq %rax
cmpq $16, %rax
jne .LBB0_1
# %bb.2: # %.lr.ph.i18.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_3: # %.lr.ph.i18
# =>This Inner Loop Header: Depth=1
movl $1, (%r14,%rax,4)
incq %rax
cmpq $16, %rax
jne .LBB0_3
# %bb.4: # %_Z4intsPii.exit22
leaq 16(%rsp), %rdi
movl $64, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movq 16(%rsp), %rdi
movl $64, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $64, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967300, %rdi # imm = 0x100000004
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8dot_prodPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_6:
movq (%rsp), %rsi
movl $4, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_7: # %.lr.ph.i23
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r12,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $16, %r12
jne .LBB0_7
# %bb.8: # %_Z11print_arrayPii.exit
movl $10, %edi
callq putchar@PLT
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_9: # %.lr.ph.i27
# =>This Inner Loop Header: Depth=1
movl (%r14,%r12,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $16, %r12
jne .LBB0_9
# %bb.10: # %_Z11print_arrayPii.exit32
movl $10, %edi
callq putchar@PLT
movl (%r15), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z4intsPii # -- Begin function _Z4intsPii
.p2align 4, 0x90
.type _Z4intsPii,@function
_Z4intsPii: # @_Z4intsPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $1, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z4intsPii, .Lfunc_end1-_Z4intsPii
.cfi_endproc
# -- End function
.globl _Z23__device_stub__dot_prodPiS_S_ # -- Begin function _Z23__device_stub__dot_prodPiS_S_
.p2align 4, 0x90
.type _Z23__device_stub__dot_prodPiS_S_,@function
_Z23__device_stub__dot_prodPiS_S_: # @_Z23__device_stub__dot_prodPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8dot_prodPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z23__device_stub__dot_prodPiS_S_, .Lfunc_end2-_Z23__device_stub__dot_prodPiS_S_
.cfi_endproc
# -- End function
.globl _Z11print_arrayPii # -- Begin function _Z11print_arrayPii
.p2align 4, 0x90
.type _Z11print_arrayPii,@function
_Z11print_arrayPii: # @_Z11print_arrayPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB3_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB3_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB3_4: # %._crit_edge
movl $10, %edi
jmp putchar@PLT # TAILCALL
.Lfunc_end3:
.size _Z11print_arrayPii, .Lfunc_end3-_Z11print_arrayPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8dot_prodPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8dot_prodPiS_S_,@object # @_Z8dot_prodPiS_S_
.section .rodata,"a",@progbits
.globl _Z8dot_prodPiS_S_
.p2align 3, 0x0
_Z8dot_prodPiS_S_:
.quad _Z23__device_stub__dot_prodPiS_S_
.size _Z8dot_prodPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d\n"
.size .L.str, 4
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d\t"
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8dot_prodPiS_S_"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__dot_prodPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8dot_prodPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define tileSize 32
//function for data initialization
void initialization( double *M, double *N, int arow, int acol, int brow, int bcol);
//(for Debugging) prints out the input data
void printInput( double *M, double *N, int arow, int acol, int brow, int bcol);
//(for Debugging) prints out the output data
void printOutput( double *P_C, double *P_G, int arow, int bcol);
//GPU kernels
__global__
__global__ void vectorScaling(const double *A, double s, double *C, int numElements)
{
int gridIndex = blockDim.x * blockIdx.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
for (int i = gridIndex; i<numElements; i+=stride)
{
C[i] = A[i]*s;
}
} | code for sm_80
Function : _Z13vectorScalingPKddPdi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0xc] ; /* 0x0000030000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x310 ; /* 0x0000028000007945 */
/* 0x000fe60003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*00b0*/ IMAD.MOV R9, RZ, RZ, -R0 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a00 */
/*00c0*/ IADD3 R2, R0.reuse, R3, RZ ; /* 0x0000000300027210 */
/* 0x040fe40007ffe0ff */
/*00d0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45070 */
/*00e0*/ LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff077212 */
/* 0x000fc800078e33ff */
/*00f0*/ IADD3 R7, R7, c[0x0][0x178], R0 ; /* 0x00005e0007077a10 */
/* 0x000fe20007ffe000 */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0130*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0140*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x002fc800078e02ff */
/*0150*/ IMAD.HI.U32 R2, R5, R9, R4 ; /* 0x0000000905027227 */
/* 0x000fcc00078e0004 */
/*0160*/ IMAD.HI.U32 R2, R2, R7, RZ ; /* 0x0000000702027227 */
/* 0x000fca00078e00ff */
/*0170*/ IADD3 R4, -R2, RZ, RZ ; /* 0x000000ff02047210 */
/* 0x000fca0007ffe1ff */
/*0180*/ IMAD R7, R0, R4, R7 ; /* 0x0000000400077224 */
/* 0x000fca00078e0207 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f06070 */
/*01a0*/ @P0 IMAD.IADD R7, R7, 0x1, -R0 ; /* 0x0000000107070824 */
/* 0x000fe200078e0a00 */
/*01b0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fc80007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*01d0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*01f0*/ IADD3 R4, R2.reuse, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x040fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0210*/ LOP3.LUT P0, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fda000780c0ff */
/*0220*/ @!P0 BRA 0x300 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0230*/ HFMA2.MMA R6, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff067435 */
/* 0x000fe200000001ff */
/*0240*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fd200078e0004 */
/*0250*/ IMAD.WIDE R4, R3, R6, c[0x0][0x170] ; /* 0x00005c0003047625 */
/* 0x000fc800078e0206 */
/*0260*/ IMAD.WIDE R6, R3, R6, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x000fca00078e0206 */
/*0270*/ LDG.E.64 R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x0000a2000c1e1b00 */
/*0280*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*0290*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*02a0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*02b0*/ IMAD.WIDE R6, R0, 0x8, R6 ; /* 0x0000000800067825 */
/* 0x001fe200078e0206 */
/*02c0*/ DMUL R8, R8, c[0x0][0x168] ; /* 0x00005a0008087a28 */
/* 0x004e0e0000000000 */
/*02d0*/ STG.E.64 [R4.64], R8 ; /* 0x0000000804007986 */
/* 0x0011e4000c101b04 */
/*02e0*/ IMAD.WIDE R4, R0, 0x8, R4 ; /* 0x0000000800047825 */
/* 0x001fe400078e0204 */
/*02f0*/ @P0 BRA 0x270 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0300*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0310*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0320*/ IMAD.MOV.U32 R8, RZ, RZ, 0x8 ; /* 0x00000008ff087424 */
/* 0x002fc800078e00ff */
/*0330*/ IMAD.WIDE R4, R3, R8, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fca00078e0208 */
/*0340*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea2000c1e1b00 */
/*0350*/ IMAD.WIDE R8, R3, R8, c[0x0][0x170] ; /* 0x00005c0003087625 */
/* 0x000fc800078e0208 */
/*0360*/ IMAD.WIDE R10, R0, 0x8, R4 ; /* 0x00000008000a7825 */
/* 0x000fe200078e0204 */
/*0370*/ DMUL R6, R6, c[0x0][0x168] ; /* 0x00005a0006067a28 */
/* 0x004e0e0000000000 */
/*0380*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x0011e8000c101b04 */
/*0390*/ LDG.E.64 R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x000ea2000c1e1b00 */
/*03a0*/ IMAD.WIDE R14, R0, 0x8, R8 ; /* 0x00000008000e7825 */
/* 0x000fc800078e0208 */
/*03b0*/ IMAD.WIDE R16, R0, 0x8, R10 ; /* 0x0000000800107825 */
/* 0x000fe200078e020a */
/*03c0*/ DMUL R12, R12, c[0x0][0x168] ; /* 0x00005a000c0c7a28 */
/* 0x004e4e0000000000 */
/*03d0*/ STG.E.64 [R14.64], R12 ; /* 0x0000000c0e007986 */
/* 0x0023e8000c101b04 */
/*03e0*/ LDG.E.64 R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea2000c1e1b00 */
/*03f0*/ IMAD.WIDE R4, R0, 0x8, R14 ; /* 0x0000000800047825 */
/* 0x000fc800078e020e */
/*0400*/ IMAD.WIDE R20, R0, 0x8, R16 ; /* 0x0000000800147825 */
/* 0x000fe200078e0210 */
/*0410*/ DMUL R18, R18, c[0x0][0x168] ; /* 0x00005a0012127a28 */
/* 0x004e8e0000000000 */
/*0420*/ STG.E.64 [R4.64], R18 ; /* 0x0000001204007986 */
/* 0x0043e8000c101b04 */
/*0430*/ LDG.E.64 R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ea2000c1e1b00 */
/*0440*/ IMAD.WIDE R8, R0.reuse, 0x8, R4 ; /* 0x0000000800087825 */
/* 0x041fe200078e0204 */
/*0450*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0460*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0470*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe20003f06270 */
/*0480*/ DMUL R6, R20, c[0x0][0x168] ; /* 0x00005a0014067a28 */
/* 0x004e0e0000000000 */
/*0490*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x0013ea000c101b04 */
/*04a0*/ @!P0 BRA 0x320 ; /* 0xfffffe7000008947 */
/* 0x000fea000383ffff */
/*04b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04c0*/ BRA 0x4c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define tileSize 32
//function for data initialization
void initialization( double *M, double *N, int arow, int acol, int brow, int bcol);
//(for Debugging) prints out the input data
void printInput( double *M, double *N, int arow, int acol, int brow, int bcol);
//(for Debugging) prints out the output data
void printOutput( double *P_C, double *P_G, int arow, int bcol);
//GPU kernels
__global__
__global__ void vectorScaling(const double *A, double s, double *C, int numElements)
{
int gridIndex = blockDim.x * blockIdx.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
for (int i = gridIndex; i<numElements; i+=stride)
{
C[i] = A[i]*s;
}
} | .file "tmpxft_0004c0cb_00000000-6_vectorScaling.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z13vectorScalingPKddPdiPKddPdi
.type _Z38__device_stub__Z13vectorScalingPKddPdiPKddPdi, @function
_Z38__device_stub__Z13vectorScalingPKddPdiPKddPdi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movsd %xmm0, 16(%rsp)
movq %rsi, 8(%rsp)
movl %edx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13vectorScalingPKddPdi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z13vectorScalingPKddPdiPKddPdi, .-_Z38__device_stub__Z13vectorScalingPKddPdiPKddPdi
.globl _Z13vectorScalingPKddPdi
.type _Z13vectorScalingPKddPdi, @function
_Z13vectorScalingPKddPdi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13vectorScalingPKddPdiPKddPdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13vectorScalingPKddPdi, .-_Z13vectorScalingPKddPdi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13vectorScalingPKddPdi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13vectorScalingPKddPdi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define tileSize 32
//function for data initialization
void initialization( double *M, double *N, int arow, int acol, int brow, int bcol);
//(for Debugging) prints out the input data
void printInput( double *M, double *N, int arow, int acol, int brow, int bcol);
//(for Debugging) prints out the output data
void printOutput( double *P_C, double *P_G, int arow, int bcol);
//GPU kernels
__global__
__global__ void vectorScaling(const double *A, double s, double *C, int numElements)
{
int gridIndex = blockDim.x * blockIdx.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
for (int i = gridIndex; i<numElements; i+=stride)
{
C[i] = A[i]*s;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define tileSize 32
//function for data initialization
void initialization( double *M, double *N, int arow, int acol, int brow, int bcol);
//(for Debugging) prints out the input data
void printInput( double *M, double *N, int arow, int acol, int brow, int bcol);
//(for Debugging) prints out the output data
void printOutput( double *P_C, double *P_G, int arow, int bcol);
//GPU kernels
__global__
__global__ void vectorScaling(const double *A, double s, double *C, int numElements)
{
int gridIndex = blockDim.x * blockIdx.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
for (int i = gridIndex; i<numElements; i+=stride)
{
C[i] = A[i]*s;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define tileSize 32
//function for data initialization
void initialization( double *M, double *N, int arow, int acol, int brow, int bcol);
//(for Debugging) prints out the input data
void printInput( double *M, double *N, int arow, int acol, int brow, int bcol);
//(for Debugging) prints out the output data
void printOutput( double *P_C, double *P_G, int arow, int bcol);
//GPU kernels
__global__
__global__ void vectorScaling(const double *A, double s, double *C, int numElements)
{
int gridIndex = blockDim.x * blockIdx.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
for (int i = gridIndex; i<numElements; i+=stride)
{
C[i] = A[i]*s;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13vectorScalingPKddPdi
.globl _Z13vectorScalingPKddPdi
.p2align 8
.type _Z13vectorScalingPKddPdi,@function
_Z13vectorScalingPKddPdi:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s12, s[0:1], 0x18
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB0_3
s_load_b32 s9, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s9, s8
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[8:9], 3
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_nc_u32_e32 v1, s8, v1
v_add_co_u32 v6, vcc_lo, s2, v2
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s12, v1
v_add_co_u32 v2, s0, v2, s10
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s11, v3, s0
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
v_mul_f64 v[4:5], v[4:5], s[6:7]
global_store_b64 v[6:7], v[4:5], off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13vectorScalingPKddPdi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13vectorScalingPKddPdi, .Lfunc_end0-_Z13vectorScalingPKddPdi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13vectorScalingPKddPdi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13vectorScalingPKddPdi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define tileSize 32
//function for data initialization
void initialization( double *M, double *N, int arow, int acol, int brow, int bcol);
//(for Debugging) prints out the input data
void printInput( double *M, double *N, int arow, int acol, int brow, int bcol);
//(for Debugging) prints out the output data
void printOutput( double *P_C, double *P_G, int arow, int bcol);
//GPU kernels
__global__
__global__ void vectorScaling(const double *A, double s, double *C, int numElements)
{
int gridIndex = blockDim.x * blockIdx.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
for (int i = gridIndex; i<numElements; i+=stride)
{
C[i] = A[i]*s;
}
} | .text
.file "vectorScaling.hip"
.globl _Z28__device_stub__vectorScalingPKddPdi # -- Begin function _Z28__device_stub__vectorScalingPKddPdi
.p2align 4, 0x90
.type _Z28__device_stub__vectorScalingPKddPdi,@function
_Z28__device_stub__vectorScalingPKddPdi: # @_Z28__device_stub__vectorScalingPKddPdi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movsd %xmm0, 64(%rsp)
movq %rsi, 56(%rsp)
movl %edx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13vectorScalingPKddPdi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__vectorScalingPKddPdi, .Lfunc_end0-_Z28__device_stub__vectorScalingPKddPdi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13vectorScalingPKddPdi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13vectorScalingPKddPdi,@object # @_Z13vectorScalingPKddPdi
.section .rodata,"a",@progbits
.globl _Z13vectorScalingPKddPdi
.p2align 3, 0x0
_Z13vectorScalingPKddPdi:
.quad _Z28__device_stub__vectorScalingPKddPdi
.size _Z13vectorScalingPKddPdi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13vectorScalingPKddPdi"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__vectorScalingPKddPdi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13vectorScalingPKddPdi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13vectorScalingPKddPdi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0xc] ; /* 0x0000030000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x310 ; /* 0x0000028000007945 */
/* 0x000fe60003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*00b0*/ IMAD.MOV R9, RZ, RZ, -R0 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a00 */
/*00c0*/ IADD3 R2, R0.reuse, R3, RZ ; /* 0x0000000300027210 */
/* 0x040fe40007ffe0ff */
/*00d0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45070 */
/*00e0*/ LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff077212 */
/* 0x000fc800078e33ff */
/*00f0*/ IADD3 R7, R7, c[0x0][0x178], R0 ; /* 0x00005e0007077a10 */
/* 0x000fe20007ffe000 */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0130*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0140*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x002fc800078e02ff */
/*0150*/ IMAD.HI.U32 R2, R5, R9, R4 ; /* 0x0000000905027227 */
/* 0x000fcc00078e0004 */
/*0160*/ IMAD.HI.U32 R2, R2, R7, RZ ; /* 0x0000000702027227 */
/* 0x000fca00078e00ff */
/*0170*/ IADD3 R4, -R2, RZ, RZ ; /* 0x000000ff02047210 */
/* 0x000fca0007ffe1ff */
/*0180*/ IMAD R7, R0, R4, R7 ; /* 0x0000000400077224 */
/* 0x000fca00078e0207 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f06070 */
/*01a0*/ @P0 IMAD.IADD R7, R7, 0x1, -R0 ; /* 0x0000000107070824 */
/* 0x000fe200078e0a00 */
/*01b0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fc80007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*01d0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*01f0*/ IADD3 R4, R2.reuse, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x040fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0210*/ LOP3.LUT P0, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fda000780c0ff */
/*0220*/ @!P0 BRA 0x300 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0230*/ HFMA2.MMA R6, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff067435 */
/* 0x000fe200000001ff */
/*0240*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fd200078e0004 */
/*0250*/ IMAD.WIDE R4, R3, R6, c[0x0][0x170] ; /* 0x00005c0003047625 */
/* 0x000fc800078e0206 */
/*0260*/ IMAD.WIDE R6, R3, R6, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x000fca00078e0206 */
/*0270*/ LDG.E.64 R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x0000a2000c1e1b00 */
/*0280*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*0290*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*02a0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*02b0*/ IMAD.WIDE R6, R0, 0x8, R6 ; /* 0x0000000800067825 */
/* 0x001fe200078e0206 */
/*02c0*/ DMUL R8, R8, c[0x0][0x168] ; /* 0x00005a0008087a28 */
/* 0x004e0e0000000000 */
/*02d0*/ STG.E.64 [R4.64], R8 ; /* 0x0000000804007986 */
/* 0x0011e4000c101b04 */
/*02e0*/ IMAD.WIDE R4, R0, 0x8, R4 ; /* 0x0000000800047825 */
/* 0x001fe400078e0204 */
/*02f0*/ @P0 BRA 0x270 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0300*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0310*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0320*/ IMAD.MOV.U32 R8, RZ, RZ, 0x8 ; /* 0x00000008ff087424 */
/* 0x002fc800078e00ff */
/*0330*/ IMAD.WIDE R4, R3, R8, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fca00078e0208 */
/*0340*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea2000c1e1b00 */
/*0350*/ IMAD.WIDE R8, R3, R8, c[0x0][0x170] ; /* 0x00005c0003087625 */
/* 0x000fc800078e0208 */
/*0360*/ IMAD.WIDE R10, R0, 0x8, R4 ; /* 0x00000008000a7825 */
/* 0x000fe200078e0204 */
/*0370*/ DMUL R6, R6, c[0x0][0x168] ; /* 0x00005a0006067a28 */
/* 0x004e0e0000000000 */
/*0380*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x0011e8000c101b04 */
/*0390*/ LDG.E.64 R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x000ea2000c1e1b00 */
/*03a0*/ IMAD.WIDE R14, R0, 0x8, R8 ; /* 0x00000008000e7825 */
/* 0x000fc800078e0208 */
/*03b0*/ IMAD.WIDE R16, R0, 0x8, R10 ; /* 0x0000000800107825 */
/* 0x000fe200078e020a */
/*03c0*/ DMUL R12, R12, c[0x0][0x168] ; /* 0x00005a000c0c7a28 */
/* 0x004e4e0000000000 */
/*03d0*/ STG.E.64 [R14.64], R12 ; /* 0x0000000c0e007986 */
/* 0x0023e8000c101b04 */
/*03e0*/ LDG.E.64 R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea2000c1e1b00 */
/*03f0*/ IMAD.WIDE R4, R0, 0x8, R14 ; /* 0x0000000800047825 */
/* 0x000fc800078e020e */
/*0400*/ IMAD.WIDE R20, R0, 0x8, R16 ; /* 0x0000000800147825 */
/* 0x000fe200078e0210 */
/*0410*/ DMUL R18, R18, c[0x0][0x168] ; /* 0x00005a0012127a28 */
/* 0x004e8e0000000000 */
/*0420*/ STG.E.64 [R4.64], R18 ; /* 0x0000001204007986 */
/* 0x0043e8000c101b04 */
/*0430*/ LDG.E.64 R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ea2000c1e1b00 */
/*0440*/ IMAD.WIDE R8, R0.reuse, 0x8, R4 ; /* 0x0000000800087825 */
/* 0x041fe200078e0204 */
/*0450*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0460*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0470*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe20003f06270 */
/*0480*/ DMUL R6, R20, c[0x0][0x168] ; /* 0x00005a0014067a28 */
/* 0x004e0e0000000000 */
/*0490*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x0013ea000c101b04 */
/*04a0*/ @!P0 BRA 0x320 ; /* 0xfffffe7000008947 */
/* 0x000fea000383ffff */
/*04b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04c0*/ BRA 0x4c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13vectorScalingPKddPdi
.globl _Z13vectorScalingPKddPdi
.p2align 8
.type _Z13vectorScalingPKddPdi,@function
_Z13vectorScalingPKddPdi:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s12, s[0:1], 0x18
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB0_3
s_load_b32 s9, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s9, s8
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[8:9], 3
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_nc_u32_e32 v1, s8, v1
v_add_co_u32 v6, vcc_lo, s2, v2
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s12, v1
v_add_co_u32 v2, s0, v2, s10
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s11, v3, s0
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
v_mul_f64 v[4:5], v[4:5], s[6:7]
global_store_b64 v[6:7], v[4:5], off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13vectorScalingPKddPdi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13vectorScalingPKddPdi, .Lfunc_end0-_Z13vectorScalingPKddPdi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13vectorScalingPKddPdi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13vectorScalingPKddPdi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004c0cb_00000000-6_vectorScaling.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z13vectorScalingPKddPdiPKddPdi
.type _Z38__device_stub__Z13vectorScalingPKddPdiPKddPdi, @function
_Z38__device_stub__Z13vectorScalingPKddPdiPKddPdi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movsd %xmm0, 16(%rsp)
movq %rsi, 8(%rsp)
movl %edx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13vectorScalingPKddPdi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z13vectorScalingPKddPdiPKddPdi, .-_Z38__device_stub__Z13vectorScalingPKddPdiPKddPdi
.globl _Z13vectorScalingPKddPdi
.type _Z13vectorScalingPKddPdi, @function
_Z13vectorScalingPKddPdi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13vectorScalingPKddPdiPKddPdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13vectorScalingPKddPdi, .-_Z13vectorScalingPKddPdi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13vectorScalingPKddPdi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13vectorScalingPKddPdi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vectorScaling.hip"
.globl _Z28__device_stub__vectorScalingPKddPdi # -- Begin function _Z28__device_stub__vectorScalingPKddPdi
.p2align 4, 0x90
.type _Z28__device_stub__vectorScalingPKddPdi,@function
_Z28__device_stub__vectorScalingPKddPdi: # @_Z28__device_stub__vectorScalingPKddPdi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movsd %xmm0, 64(%rsp)
movq %rsi, 56(%rsp)
movl %edx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13vectorScalingPKddPdi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__vectorScalingPKddPdi, .Lfunc_end0-_Z28__device_stub__vectorScalingPKddPdi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13vectorScalingPKddPdi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13vectorScalingPKddPdi,@object # @_Z13vectorScalingPKddPdi
.section .rodata,"a",@progbits
.globl _Z13vectorScalingPKddPdi
.p2align 3, 0x0
_Z13vectorScalingPKddPdi:
.quad _Z28__device_stub__vectorScalingPKddPdi
.size _Z13vectorScalingPKddPdi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13vectorScalingPKddPdi"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__vectorScalingPKddPdi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13vectorScalingPKddPdi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // https://github.com/FFmpeg/FFmpeg/blob/master/libavfilter/vf_chromakey.c
#define CUDA_KERNEL_LOOP_x(i,n) \
for(int i = blockIdx.x * blockDim.x + threadIdx.x; \
i < (n); \
i += blockDim.x * gridDim.x)
#define CUDA_KERNEL_LOOP_y(j,m) \
for(int j = blockIdx.y * blockDim.y + threadIdx.y; \
j < (m); \
j += blockDim.y * gridDim.y)
#define FIXNUM(x) lrint((x) * (1 << 10))
#define RGB_TO_U(rgb) (((- FIXNUM(0.16874) * rgb[0] - FIXNUM(0.33126) * rgb[1] + FIXNUM(0.50000) * rgb[2] + (1 << 9) - 1) >> 10) + 128)
#define RGB_TO_V(rgb) ((( FIXNUM(0.50000) * rgb[0] - FIXNUM(0.41869) * rgb[1] - FIXNUM(0.08131) * rgb[2] + (1 << 9) - 1) >> 10) + 128)
#define BGR_TO_U(bgr) (((- FIXNUM(0.16874) * bgr[2] - FIXNUM(0.33126) * bgr[1] + FIXNUM(0.50000) * bgr[0] + (1 << 9) - 1) >> 10) + 128)
#define BGR_TO_V(bgr) ((( FIXNUM(0.50000) * bgr[2] - FIXNUM(0.41869) * bgr[1] - FIXNUM(0.08131) * bgr[0] + (1 << 9) - 1) >> 10) + 128)
#define av_clipd(v, v_min, v_max) (max(min(v, v_max), v_min))
__device__ float do_chromakey_pixel_diff(
float similarity, float blend,
float * diff_list)
{
float diff = 0.0;
int i;
for (i = 0; i < 9; ++i) {
diff += diff_list[i];
}
diff /= 9.0;
if (blend > 0.0001) {
return av_clipd((diff - similarity) / blend, 0.0, 1.0);
} else {
return (diff > similarity) ? 1.0 : 0.0;
}
}
// ---------------------------------------
__global__ void rendering_kernel(const int h, const int w,
const unsigned char * chromakey_bgr, const float * similarity_blend,
unsigned char * img,
float * img_diff)
{
const unsigned char * p_tmp;
int u, v, du, dv;
float diff;
// ---------------------------------------------------------
unsigned char chromakey_uv[2];
chromakey_uv[0] = BGR_TO_U(chromakey_bgr);
chromakey_uv[1] = BGR_TO_V(chromakey_bgr);
// ---------------------------------------------------------
// rgb2uv
CUDA_KERNEL_LOOP_y(jj, h){
CUDA_KERNEL_LOOP_x(ii, w){
int idx_base = jj * w + ii;
p_tmp = img + idx_base * 3;
u = BGR_TO_U(p_tmp);
v = BGR_TO_V(p_tmp);
// diff
du = u - chromakey_uv[0];
dv = v - chromakey_uv[1];
diff = sqrt((du * du + dv * dv) / (255.0 * 255.0 * 2));
img_diff[idx_base] = diff;
}
}
__syncthreads();
// ---------------------------------------------------------
int xo, yo;
int x, y;
float diff_list[9];
const float similarity = similarity_blend[0];
const float blend = similarity_blend[1];
CUDA_KERNEL_LOOP_y(jj, h){
CUDA_KERNEL_LOOP_x(ii, w){
int idx_base = jj * w + ii;
for (yo = 0; yo < 3; ++yo) {
for (xo = 0; xo < 3; ++xo) {
y = jj + yo - 1;
x = ii + xo - 1;
if (x < 0 || x >= w || y < 0 || y >= h)
continue;
int idx_base_tmp = w * y + x;
diff_list[yo * 3 + xo] = img_diff[idx_base_tmp];
}
}
float alpha = do_chromakey_pixel_diff(similarity, blend, diff_list);
img[idx_base * 3 + 0] = img[idx_base * 3 + 0] * alpha;
img[idx_base * 3 + 1] = img[idx_base * 3 + 1] * alpha;
img[idx_base * 3 + 2] = img[idx_base * 3 + 2] * alpha;
}
}
} | .file "tmpxft_00112390_00000000-6_green_rendering_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23do_chromakey_pixel_diffffPf
.type _Z23do_chromakey_pixel_diffffPf, @function
_Z23do_chromakey_pixel_diffffPf:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z23do_chromakey_pixel_diffffPf, .-_Z23do_chromakey_pixel_diffffPf
.globl _Z46__device_stub__Z16rendering_kerneliiPKhPKfPhPfiiPKhPKfPhPf
.type _Z46__device_stub__Z16rendering_kerneliiPKhPKfPhPfiiPKhPKfPhPf, @function
_Z46__device_stub__Z16rendering_kerneliiPKhPKfPhPfiiPKhPKfPhPf:
.LFB2052:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movq %rdx, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16rendering_kerneliiPKhPKfPhPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z46__device_stub__Z16rendering_kerneliiPKhPKfPhPfiiPKhPKfPhPf, .-_Z46__device_stub__Z16rendering_kerneliiPKhPKfPhPfiiPKhPKfPhPf
.globl _Z16rendering_kerneliiPKhPKfPhPf
.type _Z16rendering_kerneliiPKhPKfPhPf, @function
_Z16rendering_kerneliiPKhPKfPhPf:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z16rendering_kerneliiPKhPKfPhPfiiPKhPKfPhPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z16rendering_kerneliiPKhPKfPhPf, .-_Z16rendering_kerneliiPKhPKfPhPf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z16rendering_kerneliiPKhPKfPhPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16rendering_kerneliiPKhPKfPhPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // https://github.com/FFmpeg/FFmpeg/blob/master/libavfilter/vf_chromakey.c
#define CUDA_KERNEL_LOOP_x(i,n) \
for(int i = blockIdx.x * blockDim.x + threadIdx.x; \
i < (n); \
i += blockDim.x * gridDim.x)
#define CUDA_KERNEL_LOOP_y(j,m) \
for(int j = blockIdx.y * blockDim.y + threadIdx.y; \
j < (m); \
j += blockDim.y * gridDim.y)
#define FIXNUM(x) lrint((x) * (1 << 10))
#define RGB_TO_U(rgb) (((- FIXNUM(0.16874) * rgb[0] - FIXNUM(0.33126) * rgb[1] + FIXNUM(0.50000) * rgb[2] + (1 << 9) - 1) >> 10) + 128)
#define RGB_TO_V(rgb) ((( FIXNUM(0.50000) * rgb[0] - FIXNUM(0.41869) * rgb[1] - FIXNUM(0.08131) * rgb[2] + (1 << 9) - 1) >> 10) + 128)
#define BGR_TO_U(bgr) (((- FIXNUM(0.16874) * bgr[2] - FIXNUM(0.33126) * bgr[1] + FIXNUM(0.50000) * bgr[0] + (1 << 9) - 1) >> 10) + 128)
#define BGR_TO_V(bgr) ((( FIXNUM(0.50000) * bgr[2] - FIXNUM(0.41869) * bgr[1] - FIXNUM(0.08131) * bgr[0] + (1 << 9) - 1) >> 10) + 128)
#define av_clipd(v, v_min, v_max) (max(min(v, v_max), v_min))
__device__ float do_chromakey_pixel_diff(
float similarity, float blend,
float * diff_list)
{
float diff = 0.0;
int i;
for (i = 0; i < 9; ++i) {
diff += diff_list[i];
}
diff /= 9.0;
if (blend > 0.0001) {
return av_clipd((diff - similarity) / blend, 0.0, 1.0);
} else {
return (diff > similarity) ? 1.0 : 0.0;
}
}
// ---------------------------------------
__global__ void rendering_kernel(const int h, const int w,
const unsigned char * chromakey_bgr, const float * similarity_blend,
unsigned char * img,
float * img_diff)
{
const unsigned char * p_tmp;
int u, v, du, dv;
float diff;
// ---------------------------------------------------------
unsigned char chromakey_uv[2];
chromakey_uv[0] = BGR_TO_U(chromakey_bgr);
chromakey_uv[1] = BGR_TO_V(chromakey_bgr);
// ---------------------------------------------------------
// rgb2uv
CUDA_KERNEL_LOOP_y(jj, h){
CUDA_KERNEL_LOOP_x(ii, w){
int idx_base = jj * w + ii;
p_tmp = img + idx_base * 3;
u = BGR_TO_U(p_tmp);
v = BGR_TO_V(p_tmp);
// diff
du = u - chromakey_uv[0];
dv = v - chromakey_uv[1];
diff = sqrt((du * du + dv * dv) / (255.0 * 255.0 * 2));
img_diff[idx_base] = diff;
}
}
__syncthreads();
// ---------------------------------------------------------
int xo, yo;
int x, y;
float diff_list[9];
const float similarity = similarity_blend[0];
const float blend = similarity_blend[1];
CUDA_KERNEL_LOOP_y(jj, h){
CUDA_KERNEL_LOOP_x(ii, w){
int idx_base = jj * w + ii;
for (yo = 0; yo < 3; ++yo) {
for (xo = 0; xo < 3; ++xo) {
y = jj + yo - 1;
x = ii + xo - 1;
if (x < 0 || x >= w || y < 0 || y >= h)
continue;
int idx_base_tmp = w * y + x;
diff_list[yo * 3 + xo] = img_diff[idx_base_tmp];
}
}
float alpha = do_chromakey_pixel_diff(similarity, blend, diff_list);
img[idx_base * 3 + 0] = img[idx_base * 3 + 0] * alpha;
img[idx_base * 3 + 1] = img[idx_base * 3 + 1] * alpha;
img[idx_base * 3 + 2] = img[idx_base * 3 + 2] * alpha;
}
}
} | #include <hip/hip_runtime.h>
// https://github.com/FFmpeg/FFmpeg/blob/master/libavfilter/vf_chromakey.c
#define CUDA_KERNEL_LOOP_x(i,n) \
for(int i = blockIdx.x * blockDim.x + threadIdx.x; \
i < (n); \
i += blockDim.x * gridDim.x)
#define CUDA_KERNEL_LOOP_y(j,m) \
for(int j = blockIdx.y * blockDim.y + threadIdx.y; \
j < (m); \
j += blockDim.y * gridDim.y)
#define FIXNUM(x) lrint((x) * (1 << 10))
#define RGB_TO_U(rgb) (((- FIXNUM(0.16874) * rgb[0] - FIXNUM(0.33126) * rgb[1] + FIXNUM(0.50000) * rgb[2] + (1 << 9) - 1) >> 10) + 128)
#define RGB_TO_V(rgb) ((( FIXNUM(0.50000) * rgb[0] - FIXNUM(0.41869) * rgb[1] - FIXNUM(0.08131) * rgb[2] + (1 << 9) - 1) >> 10) + 128)
#define BGR_TO_U(bgr) (((- FIXNUM(0.16874) * bgr[2] - FIXNUM(0.33126) * bgr[1] + FIXNUM(0.50000) * bgr[0] + (1 << 9) - 1) >> 10) + 128)
#define BGR_TO_V(bgr) ((( FIXNUM(0.50000) * bgr[2] - FIXNUM(0.41869) * bgr[1] - FIXNUM(0.08131) * bgr[0] + (1 << 9) - 1) >> 10) + 128)
#define av_clipd(v, v_min, v_max) (max(min(v, v_max), v_min))
__device__ float do_chromakey_pixel_diff(
float similarity, float blend,
float * diff_list)
{
float diff = 0.0;
int i;
for (i = 0; i < 9; ++i) {
diff += diff_list[i];
}
diff /= 9.0;
if (blend > 0.0001) {
return av_clipd((diff - similarity) / blend, 0.0, 1.0);
} else {
return (diff > similarity) ? 1.0 : 0.0;
}
}
// ---------------------------------------
__global__ void rendering_kernel(const int h, const int w,
const unsigned char * chromakey_bgr, const float * similarity_blend,
unsigned char * img,
float * img_diff)
{
const unsigned char * p_tmp;
int u, v, du, dv;
float diff;
// ---------------------------------------------------------
unsigned char chromakey_uv[2];
chromakey_uv[0] = BGR_TO_U(chromakey_bgr);
chromakey_uv[1] = BGR_TO_V(chromakey_bgr);
// ---------------------------------------------------------
// rgb2uv
CUDA_KERNEL_LOOP_y(jj, h){
CUDA_KERNEL_LOOP_x(ii, w){
int idx_base = jj * w + ii;
p_tmp = img + idx_base * 3;
u = BGR_TO_U(p_tmp);
v = BGR_TO_V(p_tmp);
// diff
du = u - chromakey_uv[0];
dv = v - chromakey_uv[1];
diff = sqrt((du * du + dv * dv) / (255.0 * 255.0 * 2));
img_diff[idx_base] = diff;
}
}
__syncthreads();
// ---------------------------------------------------------
int xo, yo;
int x, y;
float diff_list[9];
const float similarity = similarity_blend[0];
const float blend = similarity_blend[1];
CUDA_KERNEL_LOOP_y(jj, h){
CUDA_KERNEL_LOOP_x(ii, w){
int idx_base = jj * w + ii;
for (yo = 0; yo < 3; ++yo) {
for (xo = 0; xo < 3; ++xo) {
y = jj + yo - 1;
x = ii + xo - 1;
if (x < 0 || x >= w || y < 0 || y >= h)
continue;
int idx_base_tmp = w * y + x;
diff_list[yo * 3 + xo] = img_diff[idx_base_tmp];
}
}
float alpha = do_chromakey_pixel_diff(similarity, blend, diff_list);
img[idx_base * 3 + 0] = img[idx_base * 3 + 0] * alpha;
img[idx_base * 3 + 1] = img[idx_base * 3 + 1] * alpha;
img[idx_base * 3 + 2] = img[idx_base * 3 + 2] * alpha;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
// https://github.com/FFmpeg/FFmpeg/blob/master/libavfilter/vf_chromakey.c
#define CUDA_KERNEL_LOOP_x(i,n) \
for(int i = blockIdx.x * blockDim.x + threadIdx.x; \
i < (n); \
i += blockDim.x * gridDim.x)
#define CUDA_KERNEL_LOOP_y(j,m) \
for(int j = blockIdx.y * blockDim.y + threadIdx.y; \
j < (m); \
j += blockDim.y * gridDim.y)
#define FIXNUM(x) lrint((x) * (1 << 10))
#define RGB_TO_U(rgb) (((- FIXNUM(0.16874) * rgb[0] - FIXNUM(0.33126) * rgb[1] + FIXNUM(0.50000) * rgb[2] + (1 << 9) - 1) >> 10) + 128)
#define RGB_TO_V(rgb) ((( FIXNUM(0.50000) * rgb[0] - FIXNUM(0.41869) * rgb[1] - FIXNUM(0.08131) * rgb[2] + (1 << 9) - 1) >> 10) + 128)
#define BGR_TO_U(bgr) (((- FIXNUM(0.16874) * bgr[2] - FIXNUM(0.33126) * bgr[1] + FIXNUM(0.50000) * bgr[0] + (1 << 9) - 1) >> 10) + 128)
#define BGR_TO_V(bgr) ((( FIXNUM(0.50000) * bgr[2] - FIXNUM(0.41869) * bgr[1] - FIXNUM(0.08131) * bgr[0] + (1 << 9) - 1) >> 10) + 128)
#define av_clipd(v, v_min, v_max) (max(min(v, v_max), v_min))
__device__ float do_chromakey_pixel_diff(
float similarity, float blend,
float * diff_list)
{
float diff = 0.0;
int i;
for (i = 0; i < 9; ++i) {
diff += diff_list[i];
}
diff /= 9.0;
if (blend > 0.0001) {
return av_clipd((diff - similarity) / blend, 0.0, 1.0);
} else {
return (diff > similarity) ? 1.0 : 0.0;
}
}
// ---------------------------------------
__global__ void rendering_kernel(const int h, const int w,
const unsigned char * chromakey_bgr, const float * similarity_blend,
unsigned char * img,
float * img_diff)
{
const unsigned char * p_tmp;
int u, v, du, dv;
float diff;
// ---------------------------------------------------------
unsigned char chromakey_uv[2];
chromakey_uv[0] = BGR_TO_U(chromakey_bgr);
chromakey_uv[1] = BGR_TO_V(chromakey_bgr);
// ---------------------------------------------------------
// rgb2uv
CUDA_KERNEL_LOOP_y(jj, h){
CUDA_KERNEL_LOOP_x(ii, w){
int idx_base = jj * w + ii;
p_tmp = img + idx_base * 3;
u = BGR_TO_U(p_tmp);
v = BGR_TO_V(p_tmp);
// diff
du = u - chromakey_uv[0];
dv = v - chromakey_uv[1];
diff = sqrt((du * du + dv * dv) / (255.0 * 255.0 * 2));
img_diff[idx_base] = diff;
}
}
__syncthreads();
// ---------------------------------------------------------
int xo, yo;
int x, y;
float diff_list[9];
const float similarity = similarity_blend[0];
const float blend = similarity_blend[1];
CUDA_KERNEL_LOOP_y(jj, h){
CUDA_KERNEL_LOOP_x(ii, w){
int idx_base = jj * w + ii;
for (yo = 0; yo < 3; ++yo) {
for (xo = 0; xo < 3; ++xo) {
y = jj + yo - 1;
x = ii + xo - 1;
if (x < 0 || x >= w || y < 0 || y >= h)
continue;
int idx_base_tmp = w * y + x;
diff_list[yo * 3 + xo] = img_diff[idx_base_tmp];
}
}
float alpha = do_chromakey_pixel_diff(similarity, blend, diff_list);
img[idx_base * 3 + 0] = img[idx_base * 3 + 0] * alpha;
img[idx_base * 3 + 1] = img[idx_base * 3 + 1] * alpha;
img[idx_base * 3 + 2] = img[idx_base * 3 + 2] * alpha;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16rendering_kerneliiPKhPKfPhPf
.globl _Z16rendering_kerneliiPKhPKfPhPf
.p2align 8
.type _Z16rendering_kerneliiPKhPKfPhPf,@function
_Z16rendering_kerneliiPKhPKfPhPf:
s_clause 0x3
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[8:9], s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x18
s_add_u32 s10, s0, 40
v_bfe_u32 v1, v0, 10, 10
s_addc_u32 s11, s1, 0
s_mov_b32 s13, exec_lo
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mul_i32 s12, s15, s2
s_mul_i32 s15, s3, s2
v_add_nc_u32_e32 v11, s12, v1
v_cmpx_gt_i32_e64 s8, v11
s_cbranch_execz .LBB0_6
s_load_b64 s[2:3], s[0:1], 0x8
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, v11
v_and_b32_e32 v8, 0x3ff, v0
s_mul_i32 s16, s15, s9
s_waitcnt lgkmcnt(0)
s_clause 0x2
global_load_u8 v5, v2, s[2:3] offset:1
global_load_u8 v6, v2, s[2:3] offset:2
global_load_u8 v7, v2, s[2:3]
s_clause 0x1
s_load_b32 s2, s[10:11], 0xc
s_load_b32 s18, s[10:11], 0x0
v_mul_lo_u32 v2, s9, v11
s_mul_i32 s17, s16, 3
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
s_mul_i32 s3, s14, s2
s_mul_i32 s18, s18, s2
v_add_nc_u32_e32 v4, s3, v8
v_add3_u32 v8, v8, v2, s3
s_mul_i32 s19, s18, 3
s_delay_alu instid0(VALU_DEP_2)
v_cmp_gt_i32_e64 s2, s9, v4
s_waitcnt vmcnt(2)
v_readfirstlane_b32 s3, v5
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s20, v6
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s21, v7
v_lshl_add_u32 v5, v8, 1, v8
s_mul_i32 s22, s3, 0xfffffe53
s_lshl_b32 s23, s20, 9
s_mulk_i32 s3, 0xfead
s_mulk_i32 s20, 0xff53
s_mul_i32 s24, s21, 0x3ffad
s_lshl_b32 s21, s21, 9
s_add_i32 s3, s3, s20
s_add_i32 s20, s22, s23
s_add_i32 s3, s3, s21
s_add_i32 s20, s20, s24
s_addk_i32 s3, 0x1ff
s_addk_i32 s20, 0x1ff
s_bfe_u32 s3, s3, 0x8000a
s_bfe_u32 s20, s20, 0x8000a
s_xor_b32 s3, s3, 0xffffff7f
s_xor_b32 s21, s20, 0xffffff7f
s_add_i32 s20, s3, 0x81
s_addk_i32 s21, 0x81
s_mov_b32 s22, 0
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s23
v_add_nc_u32_e32 v3, s15, v3
v_add_nc_u32_e32 v5, s17, v5
v_add_nc_u32_e32 v2, s16, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s8, v3
s_or_b32 s22, vcc_lo, s22
s_and_not1_b32 exec_lo, exec_lo, s22
s_cbranch_execz .LBB0_6
.LBB0_3:
s_and_saveexec_b32 s23, s2
s_cbranch_execz .LBB0_2
v_dual_mov_b32 v6, v5 :: v_dual_mov_b32 v7, v4
s_mov_b32 s24, 0
.LBB0_5:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v9, 31, v6
v_add_co_u32 v8, vcc_lo, s4, v6
v_add_nc_u32_e32 v6, s19, v6
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
s_clause 0x2
global_load_u8 v10, v[8:9], off offset:1
global_load_u8 v16, v[8:9], off offset:2
global_load_u8 v17, v[8:9], off
v_mov_b32_e32 v9, 0
s_waitcnt vmcnt(2)
v_mul_hi_i32_i24_e32 v13, 0xfffffead, v10
s_waitcnt vmcnt(1)
v_lshlrev_b32_e32 v8, 9, v16
v_mul_i32_i24_e32 v12, 0xfffffead, v10
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v18, 9, v17
v_mad_u32_u24 v13, v10, 0x3ff, v13
v_mad_u64_u32 v[14:15], null, v10, 0xfffffe53, v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[8:9], null, v16, 0xffffff53, v[12:13]
v_mad_u32_u24 v10, v10, 0x3ff, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v12, vcc_lo, v14, 0x1ff
v_mad_u32_u24 v9, v16, 0x3ff, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v10, vcc_lo
v_add_co_u32 v10, vcc_lo, v8, v18
v_add_co_ci_u32_e32 v14, vcc_lo, 0, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[8:9], null, v17, 0xffffffad, v[12:13]
v_add_co_u32 v10, vcc_lo, v10, 0x1ff
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v12, vcc_lo, 0, v14, vcc_lo
v_mad_u32_u24 v9, v17, 0x3ff, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_alignbit_b32 v10, v12, v10, 10
v_alignbit_b32 v9, v9, v8, 10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v10, s20, v10
v_add_nc_u32_e32 v12, s21, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v8, v10, v10
v_mad_u64_u32 v[9:10], null, v12, v12, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_i32_e32 v[8:9], v9
v_div_scale_f64 v[12:13], null, 0x40ffc020, 0x40ffc020, v[8:9]
v_div_scale_f64 v[18:19], vcc_lo, v[8:9], 0x40ffc020, v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[14:15], v[12:13]
s_waitcnt_depctr 0xfff
v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0
v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0
v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[16:17], v[18:19], v[14:15]
v_fma_f64 v[12:13], -v[12:13], v[16:17], v[18:19]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[12:13], v[12:13], v[14:15], v[16:17]
v_div_fixup_f64 v[8:9], v[12:13], 0x40ffc020, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[8:9]
v_cndmask_b32_e64 v10, 0, 1, vcc_lo
v_lshlrev_b32_e32 v10, 8, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ldexp_f64 v[8:9], v[8:9], v10
v_cndmask_b32_e64 v10, 0, 0xffffff80, vcc_lo
v_rsq_f64_e32 v[12:13], v[8:9]
v_cmp_class_f64_e64 vcc_lo, v[8:9], 0x260
s_waitcnt_depctr 0xfff
v_mul_f64 v[14:15], v[8:9], v[12:13]
v_mul_f64 v[12:13], v[12:13], 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[16:17], -v[12:13], v[14:15], 0.5
v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[16:17], -v[14:15], v[14:15], v[8:9]
v_fma_f64 v[14:15], v[16:17], v[12:13], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[16:17], -v[14:15], v[14:15], v[8:9]
v_fma_f64 v[12:13], v[16:17], v[12:13], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[12:13], v[12:13], v10
v_dual_cndmask_b32 v9, v13, v9 :: v_dual_cndmask_b32 v8, v12, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cvt_f32_f64_e32 v10, v[8:9]
v_add_nc_u32_e32 v8, v2, v7
v_add_nc_u32_e32 v7, s18, v7
v_ashrrev_i32_e32 v9, 31, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_i32_e32 vcc_lo, s9, v7
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_or_b32 s24, vcc_lo, s24
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v8, s3, s6, v8
v_add_co_ci_u32_e64 v9, s3, s7, v9, s3
global_store_b32 v[8:9], v10, off
s_and_not1_b32 exec_lo, exec_lo, s24
s_cbranch_execnz .LBB0_5
s_branch .LBB0_2
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s13
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s8, v11
s_cbranch_execz .LBB0_27
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v2, 0
v_and_b32_e32 v0, 0x3ff, v0
s_mul_i32 s16, s15, s9
s_mov_b32 s17, 0
s_waitcnt lgkmcnt(0)
global_load_b64 v[9:10], v2, s[0:1]
s_mov_b32 s1, 0x3f1a36e2
s_mov_b32 s0, 0xeb1c432d
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[2:3], v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_cmp_nlt_f64_e64 s0, s[0:1], v[2:3]
s_clause 0x1
s_load_b32 s1, s[10:11], 0xc
s_load_b32 s2, s[10:11], 0x0
v_add3_u32 v3, v1, s12, -1
v_mad_u64_u32 v[1:2], null, s9, v3, v[0:1]
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s1, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s14, s14, s3
v_add_nc_u32_e32 v12, s14, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add3_u32 v13, v1, s14, -1
s_mul_i32 s14, s2, s3
v_cmp_gt_i32_e64 s1, s9, v12
s_branch .LBB0_10
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s19
.LBB0_9:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
s_or_b32 exec_lo, exec_lo, s18
v_add_nc_u32_e32 v11, s15, v11
v_add_nc_u32_e32 v13, s16, v13
v_cmp_le_i32_e32 vcc_lo, s8, v11
s_or_b32 s17, vcc_lo, s17
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s17
s_cbranch_execz .LBB0_27
.LBB0_10:
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s18, s1
s_cbranch_execz .LBB0_9
v_mul_lo_u32 v14, v11, s9
v_dual_mov_b32 v15, v13 :: v_dual_mov_b32 v16, v12
s_mov_b32 s19, 0
s_branch .LBB0_13
.LBB0_12:
v_add_nc_u32_e32 v18, v16, v14
v_add_nc_u32_e32 v15, s14, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v18, v18, 1, v18
v_ashrrev_i32_e32 v19, 31, v18
v_add_co_u32 v18, vcc_lo, s4, v18
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v19, vcc_lo, s5, v19, vcc_lo
s_clause 0x2
global_load_u8 v20, v[18:19], off
global_load_u8 v21, v[18:19], off offset:1
global_load_u8 v22, v[18:19], off offset:2
s_waitcnt vmcnt(2)
v_cvt_f32_ubyte0_e32 v20, v20
s_waitcnt vmcnt(1)
v_cvt_f32_ubyte0_e32 v21, v21
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v22, v22
v_add_nc_u32_e32 v16, s14, v16
v_mul_f32_e32 v20, v17, v20
v_mul_f32_e32 v21, v17, v21
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_f32_e32 v17, v17, v22
v_cmp_le_i32_e32 vcc_lo, s9, v16
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cvt_i32_f32_e32 v20, v20
v_cvt_i32_f32_e32 v21, v21
s_delay_alu instid0(VALU_DEP_4)
v_cvt_i32_f32_e32 v17, v17
s_or_b32 s19, vcc_lo, s19
s_clause 0x2
global_store_b8 v[18:19], v20, off
global_store_b8 v[18:19], v21, off offset:1
global_store_b8 v[18:19], v17, off offset:2
s_and_not1_b32 exec_lo, exec_lo, s19
s_cbranch_execz .LBB0_8
.LBB0_13:
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v17, v15
s_mov_b64 s[10:11], 0
s_mov_b32 s20, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_15
.p2align 6
.LBB0_14:
s_add_i32 s20, s20, 1
v_add_nc_u32_e32 v17, s9, v17
s_add_u32 s10, s10, 3
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s20, 3
s_cbranch_scc0 .LBB0_21
.LBB0_15:
v_add_nc_u32_e32 v18, s20, v11
s_mov_b32 s21, 0
s_mov_b64 s[12:13], s[10:11]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, 1, v18
v_cmp_lt_i32_e64 s2, s8, v18
s_branch .LBB0_18
.p2align 6
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s23
.LBB0_17:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s22
s_add_i32 s21, s21, 1
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s21, 3
s_cbranch_scc0 .LBB0_14
.LBB0_18:
v_add_nc_u32_e32 v18, s21, v16
s_mov_b32 s22, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e32 0, v18
s_cbranch_execz .LBB0_17
v_cmp_lt_i32_e64 s3, s9, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s3, s3, vcc_lo
s_or_b32 s3, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s3, s3, -1
s_and_saveexec_b32 s23, s3
s_cbranch_execz .LBB0_16
v_add_nc_u32_e32 v18, s21, v17
s_mov_b32 m0, s12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v19, 31, v18
v_lshlrev_b64 v[18:19], 2, v[18:19]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v18, s3, s6, v18
v_add_co_ci_u32_e64 v19, s3, s7, v19, s3
global_load_b32 v18, v[18:19], off
s_waitcnt vmcnt(0)
v_movreld_b32_e32 v0, v18
s_branch .LBB0_16
.LBB0_21:
s_set_inst_prefetch_distance 0x2
v_mov_b32_e32 v17, 0
s_mov_b64 s[2:3], 0
.LBB0_22:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
s_mov_b32 m0, s2
s_add_u32 s2, s2, 1
v_movrels_b32_e32 v18, v0
s_addc_u32 s3, s3, 0
s_cmp_lg_u32 s2, 9
v_add_f32_e32 v17, v17, v18
s_cbranch_scc1 .LBB0_22
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v18, null, 0x41100000, 0x41100000, v17
v_div_scale_f32 v21, vcc_lo, v17, 0x41100000, v17
v_rcp_f32_e32 v19, v18
s_waitcnt_depctr 0xfff
v_fma_f32 v20, -v18, v19, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v19, v20, v19
v_mul_f32_e32 v20, v21, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v22, -v18, v20, v21
v_fmac_f32_e32 v20, v22, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v18, -v18, v20, v21
v_div_fmas_f32 v18, v18, v19, v20
s_and_b32 vcc_lo, exec_lo, s0
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v18, v18, 0x41100000, v17
s_cbranch_vccz .LBB0_25
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_f32_e32 vcc_lo, v18, v9
v_cndmask_b32_e64 v17, 0, 1.0, vcc_lo
s_cbranch_execnz .LBB0_12
s_branch .LBB0_26
.LBB0_25:
.LBB0_26:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v17, v18, v9
v_div_scale_f32 v18, null, v10, v10, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v19, v18
s_waitcnt_depctr 0xfff
v_fma_f32 v20, -v18, v19, 1.0
v_fmac_f32_e32 v19, v20, v19
v_div_scale_f32 v20, vcc_lo, v17, v10, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v21, v20, v19
v_fma_f32 v22, -v18, v21, v20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v21, v22, v19
v_fma_f32 v18, -v18, v21, v20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v18, v18, v19, v21
v_div_fixup_f32 v17, v18, v10, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[17:18], v17
v_min_f64 v[17:18], v[17:18], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_f64 v[17:18], v[17:18], 0
v_cvt_f32_f64_e32 v17, v[17:18]
s_branch .LBB0_12
.LBB0_27:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16rendering_kerneliiPKhPKfPhPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 23
.amdhsa_next_free_sgpr 25
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16rendering_kerneliiPKhPKfPhPf, .Lfunc_end0-_Z16rendering_kerneliiPKhPKfPhPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16rendering_kerneliiPKhPKfPhPf
.private_segment_fixed_size: 0
.sgpr_count: 27
.sgpr_spill_count: 0
.symbol: _Z16rendering_kerneliiPKhPKfPhPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 23
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
// https://github.com/FFmpeg/FFmpeg/blob/master/libavfilter/vf_chromakey.c
#define CUDA_KERNEL_LOOP_x(i,n) \
for(int i = blockIdx.x * blockDim.x + threadIdx.x; \
i < (n); \
i += blockDim.x * gridDim.x)
#define CUDA_KERNEL_LOOP_y(j,m) \
for(int j = blockIdx.y * blockDim.y + threadIdx.y; \
j < (m); \
j += blockDim.y * gridDim.y)
#define FIXNUM(x) lrint((x) * (1 << 10))
#define RGB_TO_U(rgb) (((- FIXNUM(0.16874) * rgb[0] - FIXNUM(0.33126) * rgb[1] + FIXNUM(0.50000) * rgb[2] + (1 << 9) - 1) >> 10) + 128)
#define RGB_TO_V(rgb) ((( FIXNUM(0.50000) * rgb[0] - FIXNUM(0.41869) * rgb[1] - FIXNUM(0.08131) * rgb[2] + (1 << 9) - 1) >> 10) + 128)
#define BGR_TO_U(bgr) (((- FIXNUM(0.16874) * bgr[2] - FIXNUM(0.33126) * bgr[1] + FIXNUM(0.50000) * bgr[0] + (1 << 9) - 1) >> 10) + 128)
#define BGR_TO_V(bgr) ((( FIXNUM(0.50000) * bgr[2] - FIXNUM(0.41869) * bgr[1] - FIXNUM(0.08131) * bgr[0] + (1 << 9) - 1) >> 10) + 128)
#define av_clipd(v, v_min, v_max) (max(min(v, v_max), v_min))
__device__ float do_chromakey_pixel_diff(
float similarity, float blend,
float * diff_list)
{
float diff = 0.0;
int i;
for (i = 0; i < 9; ++i) {
diff += diff_list[i];
}
diff /= 9.0;
if (blend > 0.0001) {
return av_clipd((diff - similarity) / blend, 0.0, 1.0);
} else {
return (diff > similarity) ? 1.0 : 0.0;
}
}
// ---------------------------------------
__global__ void rendering_kernel(const int h, const int w,
const unsigned char * chromakey_bgr, const float * similarity_blend,
unsigned char * img,
float * img_diff)
{
const unsigned char * p_tmp;
int u, v, du, dv;
float diff;
// ---------------------------------------------------------
unsigned char chromakey_uv[2];
chromakey_uv[0] = BGR_TO_U(chromakey_bgr);
chromakey_uv[1] = BGR_TO_V(chromakey_bgr);
// ---------------------------------------------------------
// rgb2uv
CUDA_KERNEL_LOOP_y(jj, h){
CUDA_KERNEL_LOOP_x(ii, w){
int idx_base = jj * w + ii;
p_tmp = img + idx_base * 3;
u = BGR_TO_U(p_tmp);
v = BGR_TO_V(p_tmp);
// diff
du = u - chromakey_uv[0];
dv = v - chromakey_uv[1];
diff = sqrt((du * du + dv * dv) / (255.0 * 255.0 * 2));
img_diff[idx_base] = diff;
}
}
__syncthreads();
// ---------------------------------------------------------
int xo, yo;
int x, y;
float diff_list[9];
const float similarity = similarity_blend[0];
const float blend = similarity_blend[1];
CUDA_KERNEL_LOOP_y(jj, h){
CUDA_KERNEL_LOOP_x(ii, w){
int idx_base = jj * w + ii;
for (yo = 0; yo < 3; ++yo) {
for (xo = 0; xo < 3; ++xo) {
y = jj + yo - 1;
x = ii + xo - 1;
if (x < 0 || x >= w || y < 0 || y >= h)
continue;
int idx_base_tmp = w * y + x;
diff_list[yo * 3 + xo] = img_diff[idx_base_tmp];
}
}
float alpha = do_chromakey_pixel_diff(similarity, blend, diff_list);
img[idx_base * 3 + 0] = img[idx_base * 3 + 0] * alpha;
img[idx_base * 3 + 1] = img[idx_base * 3 + 1] * alpha;
img[idx_base * 3 + 2] = img[idx_base * 3 + 2] * alpha;
}
}
} | .text
.file "green_rendering_kernel.hip"
.globl _Z31__device_stub__rendering_kerneliiPKhPKfPhPf # -- Begin function _Z31__device_stub__rendering_kerneliiPKhPKfPhPf
.p2align 4, 0x90
.type _Z31__device_stub__rendering_kerneliiPKhPKfPhPf,@function
_Z31__device_stub__rendering_kerneliiPKhPKfPhPf: # @_Z31__device_stub__rendering_kerneliiPKhPKfPhPf
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16rendering_kerneliiPKhPKfPhPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z31__device_stub__rendering_kerneliiPKhPKfPhPf, .Lfunc_end0-_Z31__device_stub__rendering_kerneliiPKhPKfPhPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16rendering_kerneliiPKhPKfPhPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16rendering_kerneliiPKhPKfPhPf,@object # @_Z16rendering_kerneliiPKhPKfPhPf
.section .rodata,"a",@progbits
.globl _Z16rendering_kerneliiPKhPKfPhPf
.p2align 3, 0x0
_Z16rendering_kerneliiPKhPKfPhPf:
.quad _Z31__device_stub__rendering_kerneliiPKhPKfPhPf
.size _Z16rendering_kerneliiPKhPKfPhPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16rendering_kerneliiPKhPKfPhPf"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__rendering_kerneliiPKhPKfPhPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16rendering_kerneliiPKhPKfPhPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00112390_00000000-6_green_rendering_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23do_chromakey_pixel_diffffPf
.type _Z23do_chromakey_pixel_diffffPf, @function
_Z23do_chromakey_pixel_diffffPf:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z23do_chromakey_pixel_diffffPf, .-_Z23do_chromakey_pixel_diffffPf
.globl _Z46__device_stub__Z16rendering_kerneliiPKhPKfPhPfiiPKhPKfPhPf
.type _Z46__device_stub__Z16rendering_kerneliiPKhPKfPhPfiiPKhPKfPhPf, @function
_Z46__device_stub__Z16rendering_kerneliiPKhPKfPhPfiiPKhPKfPhPf:
.LFB2052:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movq %rdx, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16rendering_kerneliiPKhPKfPhPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z46__device_stub__Z16rendering_kerneliiPKhPKfPhPfiiPKhPKfPhPf, .-_Z46__device_stub__Z16rendering_kerneliiPKhPKfPhPfiiPKhPKfPhPf
.globl _Z16rendering_kerneliiPKhPKfPhPf
.type _Z16rendering_kerneliiPKhPKfPhPf, @function
_Z16rendering_kerneliiPKhPKfPhPf:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z16rendering_kerneliiPKhPKfPhPfiiPKhPKfPhPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z16rendering_kerneliiPKhPKfPhPf, .-_Z16rendering_kerneliiPKhPKfPhPf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z16rendering_kerneliiPKhPKfPhPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16rendering_kerneliiPKhPKfPhPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "green_rendering_kernel.hip"
.globl _Z31__device_stub__rendering_kerneliiPKhPKfPhPf # -- Begin function _Z31__device_stub__rendering_kerneliiPKhPKfPhPf
.p2align 4, 0x90
.type _Z31__device_stub__rendering_kerneliiPKhPKfPhPf,@function
_Z31__device_stub__rendering_kerneliiPKhPKfPhPf: # @_Z31__device_stub__rendering_kerneliiPKhPKfPhPf
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16rendering_kerneliiPKhPKfPhPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z31__device_stub__rendering_kerneliiPKhPKfPhPf, .Lfunc_end0-_Z31__device_stub__rendering_kerneliiPKhPKfPhPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16rendering_kerneliiPKhPKfPhPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16rendering_kerneliiPKhPKfPhPf,@object # @_Z16rendering_kerneliiPKhPKfPhPf
.section .rodata,"a",@progbits
.globl _Z16rendering_kerneliiPKhPKfPhPf
.p2align 3, 0x0
_Z16rendering_kerneliiPKhPKfPhPf:
.quad _Z31__device_stub__rendering_kerneliiPKhPKfPhPf
.size _Z16rendering_kerneliiPKhPKfPhPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16rendering_kerneliiPKhPKfPhPf"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__rendering_kerneliiPKhPKfPhPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16rendering_kerneliiPKhPKfPhPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "stdio.h"
#include "assert.h"
#include "math.h"
#include <iostream>
using namespace std;
#define N 100000
#define BLOCK_SIZE 1024
#define MAX_ERR 1e-6
__global__ void add(int *a, int *b, int *c, int count)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < count)
{
c[idx] = a[idx] + b[idx];
}
}
int main()
{
int *ha, *hb, *hc;
int *da, *db, *dc;
ha = (int *)malloc(sizeof(int) * N);
hb = (int *)malloc(sizeof(int) * N);
hc = (int *)malloc(sizeof(int) * N);
for (int i = 0; i < N; i++)
{
ha[i] = -i;
hb[i] = i * i;
}
cudaMalloc((void **)&da, sizeof(int) * N);
cudaMalloc((void **)&db, sizeof(int) * N);
cudaMalloc((void **)&dc, sizeof(int) * N);
cudaMemcpy(da, ha, sizeof(int) * N, cudaMemcpyHostToDevice);
cudaMemcpy(db, hb, sizeof(int) * N, cudaMemcpyHostToDevice);
add<<<(N + BLOCK_SIZE) / BLOCK_SIZE, BLOCK_SIZE>>>(da, db, dc, N);
cudaMemcpy(hc, dc, sizeof(int) * N, cudaMemcpyDeviceToHost);
for (int i = 0; i < N; i++)
{
assert(abs(hc[i] - ha[i] - hb[i]) < MAX_ERR);
}
cout << "passed" << endl;
free(ha);
free(hb);
free(hc);
cudaFree(da);
cudaFree(db);
cudaFree(dc);
return 0;
} | code for sm_80
Function : _Z3addPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "stdio.h"
#include "assert.h"
#include "math.h"
#include <iostream>
using namespace std;
#define N 100000
#define BLOCK_SIZE 1024
#define MAX_ERR 1e-6
__global__ void add(int *a, int *b, int *c, int count)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < count)
{
c[idx] = a[idx] + b[idx];
}
}
int main()
{
int *ha, *hb, *hc;
int *da, *db, *dc;
ha = (int *)malloc(sizeof(int) * N);
hb = (int *)malloc(sizeof(int) * N);
hc = (int *)malloc(sizeof(int) * N);
for (int i = 0; i < N; i++)
{
ha[i] = -i;
hb[i] = i * i;
}
cudaMalloc((void **)&da, sizeof(int) * N);
cudaMalloc((void **)&db, sizeof(int) * N);
cudaMalloc((void **)&dc, sizeof(int) * N);
cudaMemcpy(da, ha, sizeof(int) * N, cudaMemcpyHostToDevice);
cudaMemcpy(db, hb, sizeof(int) * N, cudaMemcpyHostToDevice);
add<<<(N + BLOCK_SIZE) / BLOCK_SIZE, BLOCK_SIZE>>>(da, db, dc, N);
cudaMemcpy(hc, dc, sizeof(int) * N, cudaMemcpyDeviceToHost);
for (int i = 0; i < N; i++)
{
assert(abs(hc[i] - ha[i] - hb[i]) < MAX_ERR);
}
cout << "passed" << endl;
free(ha);
free(hb);
free(hc);
cudaFree(da);
cudaFree(db);
cudaFree(dc);
return 0;
} | .file "tmpxft_0013dfc1_00000000-6_task1_2.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z3addPiS_S_iPiS_S_i
.type _Z27__device_stub__Z3addPiS_S_iPiS_S_i, @function
_Z27__device_stub__Z3addPiS_S_iPiS_S_i:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z27__device_stub__Z3addPiS_S_iPiS_S_i, .-_Z27__device_stub__Z3addPiS_S_iPiS_S_i
.globl _Z3addPiS_S_i
.type _Z3addPiS_S_i, @function
_Z3addPiS_S_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3addPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3addPiS_S_i, .-_Z3addPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "passed"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $400000, %edi
call malloc@PLT
movq %rax, %rbp
movl $400000, %edi
call malloc@PLT
movq %rax, %rbx
movl $400000, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %eax
.L12:
movl %eax, %edx
negl %edx
movl %edx, 0(%rbp,%rax,4)
movl %eax, %edx
imull %eax, %edx
movl %edx, (%rbx,%rax,4)
addq $1, %rax
cmpq $100000, %rax
jne .L12
leaq 8(%rsp), %rdi
movl $400000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $400000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $400000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $400000, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $400000, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $98, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $400000, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $100000, %eax
.L14:
subl $1, %eax
jne .L14
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $100000, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z27__device_stub__Z3addPiS_S_iPiS_S_i
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "stdio.h"
#include "assert.h"
#include "math.h"
#include <iostream>
using namespace std;
#define N 100000
#define BLOCK_SIZE 1024
#define MAX_ERR 1e-6
__global__ void add(int *a, int *b, int *c, int count)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < count)
{
c[idx] = a[idx] + b[idx];
}
}
int main()
{
int *ha, *hb, *hc;
int *da, *db, *dc;
ha = (int *)malloc(sizeof(int) * N);
hb = (int *)malloc(sizeof(int) * N);
hc = (int *)malloc(sizeof(int) * N);
for (int i = 0; i < N; i++)
{
ha[i] = -i;
hb[i] = i * i;
}
cudaMalloc((void **)&da, sizeof(int) * N);
cudaMalloc((void **)&db, sizeof(int) * N);
cudaMalloc((void **)&dc, sizeof(int) * N);
cudaMemcpy(da, ha, sizeof(int) * N, cudaMemcpyHostToDevice);
cudaMemcpy(db, hb, sizeof(int) * N, cudaMemcpyHostToDevice);
add<<<(N + BLOCK_SIZE) / BLOCK_SIZE, BLOCK_SIZE>>>(da, db, dc, N);
cudaMemcpy(hc, dc, sizeof(int) * N, cudaMemcpyDeviceToHost);
for (int i = 0; i < N; i++)
{
assert(abs(hc[i] - ha[i] - hb[i]) < MAX_ERR);
}
cout << "passed" << endl;
free(ha);
free(hb);
free(hc);
cudaFree(da);
cudaFree(db);
cudaFree(dc);
return 0;
} | #include <hip/hip_runtime.h>
#include "stdio.h"
#include "assert.h"
#include "math.h"
#include <iostream>
using namespace std;
#define N 100000
#define BLOCK_SIZE 1024
#define MAX_ERR 1e-6
__global__ void add(int *a, int *b, int *c, int count)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < count)
{
c[idx] = a[idx] + b[idx];
}
}
int main()
{
int *ha, *hb, *hc;
int *da, *db, *dc;
ha = (int *)malloc(sizeof(int) * N);
hb = (int *)malloc(sizeof(int) * N);
hc = (int *)malloc(sizeof(int) * N);
for (int i = 0; i < N; i++)
{
ha[i] = -i;
hb[i] = i * i;
}
hipMalloc((void **)&da, sizeof(int) * N);
hipMalloc((void **)&db, sizeof(int) * N);
hipMalloc((void **)&dc, sizeof(int) * N);
hipMemcpy(da, ha, sizeof(int) * N, hipMemcpyHostToDevice);
hipMemcpy(db, hb, sizeof(int) * N, hipMemcpyHostToDevice);
add<<<(N + BLOCK_SIZE) / BLOCK_SIZE, BLOCK_SIZE>>>(da, db, dc, N);
hipMemcpy(hc, dc, sizeof(int) * N, hipMemcpyDeviceToHost);
for (int i = 0; i < N; i++)
{
assert(abs(hc[i] - ha[i] - hb[i]) < MAX_ERR);
}
cout << "passed" << endl;
free(ha);
free(hb);
free(hc);
hipFree(da);
hipFree(db);
hipFree(dc);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "stdio.h"
#include "assert.h"
#include "math.h"
#include <iostream>
using namespace std;
#define N 100000
#define BLOCK_SIZE 1024
#define MAX_ERR 1e-6
__global__ void add(int *a, int *b, int *c, int count)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < count)
{
c[idx] = a[idx] + b[idx];
}
}
int main()
{
int *ha, *hb, *hc;
int *da, *db, *dc;
ha = (int *)malloc(sizeof(int) * N);
hb = (int *)malloc(sizeof(int) * N);
hc = (int *)malloc(sizeof(int) * N);
for (int i = 0; i < N; i++)
{
ha[i] = -i;
hb[i] = i * i;
}
hipMalloc((void **)&da, sizeof(int) * N);
hipMalloc((void **)&db, sizeof(int) * N);
hipMalloc((void **)&dc, sizeof(int) * N);
hipMemcpy(da, ha, sizeof(int) * N, hipMemcpyHostToDevice);
hipMemcpy(db, hb, sizeof(int) * N, hipMemcpyHostToDevice);
add<<<(N + BLOCK_SIZE) / BLOCK_SIZE, BLOCK_SIZE>>>(da, db, dc, N);
hipMemcpy(hc, dc, sizeof(int) * N, hipMemcpyDeviceToHost);
for (int i = 0; i < N; i++)
{
assert(abs(hc[i] - ha[i] - hb[i]) < MAX_ERR);
}
cout << "passed" << endl;
free(ha);
free(hb);
free(hc);
hipFree(da);
hipFree(db);
hipFree(dc);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_i
.globl _Z3addPiS_S_i
.p2align 8
.type _Z3addPiS_S_i,@function
_Z3addPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_i, .Lfunc_end0-_Z3addPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "stdio.h"
#include "assert.h"
#include "math.h"
#include <iostream>
using namespace std;
#define N 100000
#define BLOCK_SIZE 1024
#define MAX_ERR 1e-6
__global__ void add(int *a, int *b, int *c, int count)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < count)
{
c[idx] = a[idx] + b[idx];
}
}
int main()
{
int *ha, *hb, *hc;
int *da, *db, *dc;
ha = (int *)malloc(sizeof(int) * N);
hb = (int *)malloc(sizeof(int) * N);
hc = (int *)malloc(sizeof(int) * N);
for (int i = 0; i < N; i++)
{
ha[i] = -i;
hb[i] = i * i;
}
hipMalloc((void **)&da, sizeof(int) * N);
hipMalloc((void **)&db, sizeof(int) * N);
hipMalloc((void **)&dc, sizeof(int) * N);
hipMemcpy(da, ha, sizeof(int) * N, hipMemcpyHostToDevice);
hipMemcpy(db, hb, sizeof(int) * N, hipMemcpyHostToDevice);
add<<<(N + BLOCK_SIZE) / BLOCK_SIZE, BLOCK_SIZE>>>(da, db, dc, N);
hipMemcpy(hc, dc, sizeof(int) * N, hipMemcpyDeviceToHost);
for (int i = 0; i < N; i++)
{
assert(abs(hc[i] - ha[i] - hb[i]) < MAX_ERR);
}
cout << "passed" << endl;
free(ha);
free(hb);
free(hc);
hipFree(da);
hipFree(db);
hipFree(dc);
return 0;
} | .text
.file "task1_2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addPiS_S_i # -- Begin function _Z18__device_stub__addPiS_S_i
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_i,@function
_Z18__device_stub__addPiS_S_i: # @_Z18__device_stub__addPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_i, .Lfunc_end0-_Z18__device_stub__addPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $400000, %edi # imm = 0x61A80
callq malloc
movq %rax, %rbx
movl $400000, %edi # imm = 0x61A80
callq malloc
movq %rax, %r14
movl $400000, %edi # imm = 0x61A80
callq malloc
movq %rax, %r15
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%rbx,%rcx,4)
movl %ecx, %edx
imull %ecx, %edx
movl %edx, (%r14,%rcx,4)
incq %rcx
decl %eax
cmpq $100000, %rcx # imm = 0x186A0
jne .LBB1_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
leaq 16(%rsp), %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
leaq 8(%rsp), %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
movq 24(%rsp), %rdi
movl $400000, %edx # imm = 0x61A80
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $400000, %edx # imm = 0x61A80
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967394, %rdi # imm = 0x100000062
leaq 926(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $100000, 36(%rsp) # imm = 0x186A0
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3addPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $400000, %edx # imm = 0x61A80
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB1_9
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB1_7
# %bb.6:
movzbl 67(%r12), %eax
jmp .LBB1_8
.LBB1_7:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_9:
.cfi_def_cfa_offset 192
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_i,@object # @_Z3addPiS_S_i
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_i
.p2align 3, 0x0
_Z3addPiS_S_i:
.quad _Z18__device_stub__addPiS_S_i
.size _Z3addPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "passed"
.size .L.str, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_i"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_i
.globl _Z3addPiS_S_i
.p2align 8
.type _Z3addPiS_S_i,@function
_Z3addPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_i, .Lfunc_end0-_Z3addPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013dfc1_00000000-6_task1_2.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z3addPiS_S_iPiS_S_i
.type _Z27__device_stub__Z3addPiS_S_iPiS_S_i, @function
_Z27__device_stub__Z3addPiS_S_iPiS_S_i:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z27__device_stub__Z3addPiS_S_iPiS_S_i, .-_Z27__device_stub__Z3addPiS_S_iPiS_S_i
.globl _Z3addPiS_S_i
.type _Z3addPiS_S_i, @function
_Z3addPiS_S_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3addPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3addPiS_S_i, .-_Z3addPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "passed"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $400000, %edi
call malloc@PLT
movq %rax, %rbp
movl $400000, %edi
call malloc@PLT
movq %rax, %rbx
movl $400000, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %eax
.L12:
movl %eax, %edx
negl %edx
movl %edx, 0(%rbp,%rax,4)
movl %eax, %edx
imull %eax, %edx
movl %edx, (%rbx,%rax,4)
addq $1, %rax
cmpq $100000, %rax
jne .L12
leaq 8(%rsp), %rdi
movl $400000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $400000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $400000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $400000, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $400000, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $98, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $400000, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $100000, %eax
.L14:
subl $1, %eax
jne .L14
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $100000, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z27__device_stub__Z3addPiS_S_iPiS_S_i
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "task1_2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addPiS_S_i # -- Begin function _Z18__device_stub__addPiS_S_i
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_i,@function
_Z18__device_stub__addPiS_S_i: # @_Z18__device_stub__addPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_i, .Lfunc_end0-_Z18__device_stub__addPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $400000, %edi # imm = 0x61A80
callq malloc
movq %rax, %rbx
movl $400000, %edi # imm = 0x61A80
callq malloc
movq %rax, %r14
movl $400000, %edi # imm = 0x61A80
callq malloc
movq %rax, %r15
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%rbx,%rcx,4)
movl %ecx, %edx
imull %ecx, %edx
movl %edx, (%r14,%rcx,4)
incq %rcx
decl %eax
cmpq $100000, %rcx # imm = 0x186A0
jne .LBB1_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
leaq 16(%rsp), %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
leaq 8(%rsp), %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
movq 24(%rsp), %rdi
movl $400000, %edx # imm = 0x61A80
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $400000, %edx # imm = 0x61A80
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967394, %rdi # imm = 0x100000062
leaq 926(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $100000, 36(%rsp) # imm = 0x186A0
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3addPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $400000, %edx # imm = 0x61A80
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB1_9
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB1_7
# %bb.6:
movzbl 67(%r12), %eax
jmp .LBB1_8
.LBB1_7:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_9:
.cfi_def_cfa_offset 192
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_i,@object # @_Z3addPiS_S_i
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_i
.p2align 3, 0x0
_Z3addPiS_S_i:
.quad _Z18__device_stub__addPiS_S_i
.size _Z3addPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "passed"
.size .L.str, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_i"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //pass
//--blockDim=[1,128] --gridDim=[512,6]
#include <cuda.h>
//////////////////////////////////////////////////////////////////////////////
//// THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
//// ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
//// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
//// PARTICULAR PURPOSE.
////
//// Copyright (c) Microsoft Corporation. All rights reserved
//////////////////////////////////////////////////////////////////////////////
//----------------------------------------------------------------------------
// File: Convolution.cpp
//
// Implement C++ AMP based simple and tiled version of Convolution filter used in
// image processing.
//----------------------------------------------------------------------------
#define DEFAULT_WIDTH 512
#define DEFAULT_HEIGHT 512
// TILE_SIZE should be multiple of both DEFAULT_WIDTH and DEFAULT_HEIGHT
#define TILE_SIZE 128
#define width DEFAULT_WIDTH
#define height DEFAULT_HEIGHT
#define clamp(a, b, c) ((a) < (b) ? (b) : ((a) > (c) ? (c) : (a)))
#define dim_to_convolve y
#define radius 7
//----------------------------------------------------------------------------
// Tile implementation of convolution filter along different dimension
//----------------------------------------------------------------------------
__global__ void convolution_tiling(const float* img, const float* filter, float* result)
{
__shared__ float local_buf[TILE_SIZE];
int idx_convolve = (blockIdx.dim_to_convolve)*(TILE_SIZE - 2 * radius) + (int)(threadIdx.dim_to_convolve) - radius;
int max_idx_convolve = height;
float sum = 0.0f;
int a_idxY = blockIdx.y;
int a_idxX = blockIdx.x;
a_idxY = clamp(idx_convolve, 0, max_idx_convolve-1);
if (idx_convolve < (max_idx_convolve + radius))
{
local_buf[threadIdx.dim_to_convolve] = img[a_idxY*width + a_idxX];
}
#ifndef MUTATION
/* BUGINJECT: REMOVE_BARRIER, DOWN */
__syncthreads();
#endif
if ((int)(threadIdx.dim_to_convolve) >= radius && (int)(threadIdx.dim_to_convolve) < (TILE_SIZE - radius) && idx_convolve < max_idx_convolve)
{
for (int k = -radius; k <= radius; k++)
{
int k_idx = k + radius;
sum += local_buf[threadIdx.dim_to_convolve + k]*filter[k_idx];
}
result[a_idxY*width + a_idxX] = sum;
}
} | code for sm_80
Function : _Z18convolution_tilingPKfS0_Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R13, SR_TID.Y ; /* 0x00000000000d7919 */
/* 0x000e220000002200 */
/*0020*/ S2UR UR6, SR_CTAID.X ; /* 0x00000000000679c3 */
/* 0x000e620000002500 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ BSSY B0, 0x140 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*0050*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000ea20000002600 */
/*0060*/ IADD3 R0, R13, -0x7, RZ ; /* 0xfffffff90d007810 */
/* 0x001fca0007ffe0ff */
/*0070*/ IMAD R2, R3, 0x72, R0 ; /* 0x0000007203027824 */
/* 0x004fca00078e0200 */
/*0080*/ ISETP.GT.AND P1, PT, R2.reuse, 0x206, PT ; /* 0x000002060200780c */
/* 0x040fe40003f24270 */
/*0090*/ ISETP.GT.AND P0, PT, R2, 0x1ff, PT ; /* 0x000001ff0200780c */
/* 0x000fc80003f04270 */
/*00a0*/ ISETP.GT.U32.OR P0, PT, R0, 0x71, P0 ; /* 0x000000710000780c */
/* 0x000fe40000704470 */
/*00b0*/ IMNMX R0, R2, 0x1ff, PT ; /* 0x000001ff02007817 */
/* 0x000fc80003800200 */
/*00c0*/ IMNMX R0, RZ, R0, !PT ; /* 0x00000000ff007217 */
/* 0x000fe20007800200 */
/*00d0*/ @P1 BRA 0x130 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*00e0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x002fe200000001ff */
/*00f0*/ LEA R2, R0, UR6, 0x9 ; /* 0x0000000600027c11 */
/* 0x000fd2000f8e48ff */
/*0100*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0203 */
/*0110*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0120*/ STS [R13.X4], R2 ; /* 0x000000020d007388 */
/* 0x0041e40000004800 */
/*0130*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*0140*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0150*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0160*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x001fe20000000f00 */
/*0170*/ LDS R25, [R13.X4+-0x1c] ; /* 0xffffe4000d197984 */
/* 0x000e220000004800 */
/*0180*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fc60000000f00 */
/*0190*/ LDS R27, [R13.X4+-0x18] ; /* 0xffffe8000d1b7984 */
/* 0x000e680000004800 */
/*01a0*/ LDG.E R22, [R2.64] ; /* 0x0000000402167981 */
/* 0x000428000c1e1900 */
/*01b0*/ LDG.E R26, [R2.64+0x4] ; /* 0x00000404021a7981 */
/* 0x000468000c1e1900 */
/*01c0*/ LDG.E R21, [R2.64+0x8] ; /* 0x0000080402157981 */
/* 0x0004e8000c1e1900 */
/*01d0*/ LDG.E R16, [R2.64+0xc] ; /* 0x00000c0402107981 */
/* 0x000528000c1e1900 */
/*01e0*/ LDG.E R15, [R2.64+0x10] ; /* 0x00001004020f7981 */
/* 0x000568000c1e1900 */
/*01f0*/ LDG.E R12, [R2.64+0x14] ; /* 0x00001404020c7981 */
/* 0x000568000c1e1900 */
/*0200*/ LDG.E R11, [R2.64+0x18] ; /* 0x00001804020b7981 */
/* 0x000568000c1e1900 */
/*0210*/ LDG.E R10, [R2.64+0x1c] ; /* 0x00001c04020a7981 */
/* 0x000568000c1e1900 */
/*0220*/ LDG.E R9, [R2.64+0x20] ; /* 0x0000200402097981 */
/* 0x000568000c1e1900 */
/*0230*/ LDG.E R8, [R2.64+0x24] ; /* 0x0000240402087981 */
/* 0x000568000c1e1900 */
/*0240*/ LDG.E R7, [R2.64+0x28] ; /* 0x0000280402077981 */
/* 0x000568000c1e1900 */
/*0250*/ LDG.E R6, [R2.64+0x2c] ; /* 0x00002c0402067981 */
/* 0x000568000c1e1900 */
/*0260*/ LDG.E R5, [R2.64+0x30] ; /* 0x0000300402057981 */
/* 0x000568000c1e1900 */
/*0270*/ LDG.E R4, [R2.64+0x34] ; /* 0x0000340402047981 */
/* 0x000568000c1e1900 */
/*0280*/ LDG.E R14, [R2.64+0x38] ; /* 0x00003804020e7981 */
/* 0x000568000c1e1900 */
/*0290*/ LDS R24, [R13.X4+-0x14] ; /* 0xffffec000d187984 */
/* 0x000ee80000004800 */
/*02a0*/ LDS R23, [R13.X4+-0x10] ; /* 0xfffff0000d177984 */
/* 0x000f280000004800 */
/*02b0*/ LDS R20, [R13.X4+-0xc] ; /* 0xfffff4000d147984 */
/* 0x000f680000004800 */
/*02c0*/ LDS R17, [R13.X4+-0x8] ; /* 0xfffff8000d117984 */
/* 0x000e280000004800 */
/*02d0*/ LDS R18, [R13.X4+-0x4] ; /* 0xfffffc000d127984 */
/* 0x000e280000004800 */
/*02e0*/ LDS R19, [R13.X4] ; /* 0x000000000d137984 */
/* 0x000e280000004800 */
/*02f0*/ LDS R3, [R13.X4+0x8] ; /* 0x000008000d037984 */
/* 0x004fe80000004800 */
/*0300*/ LDS R2, [R13.X4+0xc] ; /* 0x00000c000d027984 */
/* 0x000fe20000004800 */
/*0310*/ FFMA R25, R22, R25, RZ ; /* 0x0000001916197223 */
/* 0x001fc600000000ff */
/*0320*/ LDS R22, [R13.X4+0x4] ; /* 0x000004000d167984 */
/* 0x000e220000004800 */
/*0330*/ FFMA R25, R26, R27, R25 ; /* 0x0000001b1a197223 */
/* 0x002fc80000000019 */
/*0340*/ FFMA R25, R21, R24, R25 ; /* 0x0000001815197223 */
/* 0x008fe40000000019 */
/*0350*/ LDS R21, [R13.X4+0x10] ; /* 0x000010000d157984 */
/* 0x000e640000004800 */
/*0360*/ FFMA R16, R16, R23, R25 ; /* 0x0000001710107223 */
/* 0x010fe40000000019 */
/*0370*/ LDS R24, [R13.X4+0x14] ; /* 0x000014000d187984 */
/* 0x000ea40000004800 */
/*0380*/ FFMA R16, R15, R20, R16 ; /* 0x000000140f107223 */
/* 0x020fe40000000010 */
/*0390*/ LDS R23, [R13.X4+0x18] ; /* 0x000018000d177984 */
/* 0x000ee40000004800 */
/*03a0*/ FFMA R12, R12, R17, R16 ; /* 0x000000110c0c7223 */
/* 0x000fc40000000010 */
/*03b0*/ LDS R15, [R13.X4+0x1c] ; /* 0x00001c000d0f7984 */
/* 0x000f240000004800 */
/*03c0*/ FFMA R11, R11, R18, R12 ; /* 0x000000120b0b7223 */
/* 0x000fc8000000000c */
/*03d0*/ FFMA R10, R10, R19, R11 ; /* 0x000000130a0a7223 */
/* 0x000fc8000000000b */
/*03e0*/ FFMA R9, R9, R22, R10 ; /* 0x0000001609097223 */
/* 0x001fc8000000000a */
/*03f0*/ FFMA R3, R8, R3, R9 ; /* 0x0000000308037223 */
/* 0x000fc80000000009 */
/*0400*/ FFMA R2, R7, R2, R3 ; /* 0x0000000207027223 */
/* 0x000fe20000000003 */
/*0410*/ LEA R3, R0, UR6, 0x9 ; /* 0x0000000600037c11 */
/* 0x000fe2000f8e48ff */
/*0420*/ HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff007435 */
/* 0x000fe400000001ff */
/*0430*/ FFMA R2, R6, R21, R2 ; /* 0x0000001506027223 */
/* 0x002fc80000000002 */
/*0440*/ FFMA R2, R5, R24, R2 ; /* 0x0000001805027223 */
/* 0x004fc80000000002 */
/*0450*/ FFMA R4, R4, R23, R2 ; /* 0x0000001704047223 */
/* 0x008fe40000000002 */
/*0460*/ IMAD.WIDE R2, R3, R0, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fc800078e0200 */
/*0470*/ FFMA R15, R14, R15, R4 ; /* 0x0000000f0e0f7223 */
/* 0x010fca0000000004 */
/*0480*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x000fe2000c101904 */
/*0490*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04a0*/ BRA 0x4a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //pass
//--blockDim=[1,128] --gridDim=[512,6]
#include <cuda.h>
//////////////////////////////////////////////////////////////////////////////
//// THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
//// ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
//// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
//// PARTICULAR PURPOSE.
////
//// Copyright (c) Microsoft Corporation. All rights reserved
//////////////////////////////////////////////////////////////////////////////
//----------------------------------------------------------------------------
// File: Convolution.cpp
//
// Implement C++ AMP based simple and tiled version of Convolution filter used in
// image processing.
//----------------------------------------------------------------------------
#define DEFAULT_WIDTH 512
#define DEFAULT_HEIGHT 512
// TILE_SIZE should be multiple of both DEFAULT_WIDTH and DEFAULT_HEIGHT
#define TILE_SIZE 128
#define width DEFAULT_WIDTH
#define height DEFAULT_HEIGHT
#define clamp(a, b, c) ((a) < (b) ? (b) : ((a) > (c) ? (c) : (a)))
#define dim_to_convolve y
#define radius 7
//----------------------------------------------------------------------------
// Tile implementation of convolution filter along different dimension
//----------------------------------------------------------------------------
__global__ void convolution_tiling(const float* img, const float* filter, float* result)
{
__shared__ float local_buf[TILE_SIZE];
int idx_convolve = (blockIdx.dim_to_convolve)*(TILE_SIZE - 2 * radius) + (int)(threadIdx.dim_to_convolve) - radius;
int max_idx_convolve = height;
float sum = 0.0f;
int a_idxY = blockIdx.y;
int a_idxX = blockIdx.x;
a_idxY = clamp(idx_convolve, 0, max_idx_convolve-1);
if (idx_convolve < (max_idx_convolve + radius))
{
local_buf[threadIdx.dim_to_convolve] = img[a_idxY*width + a_idxX];
}
#ifndef MUTATION
/* BUGINJECT: REMOVE_BARRIER, DOWN */
__syncthreads();
#endif
if ((int)(threadIdx.dim_to_convolve) >= radius && (int)(threadIdx.dim_to_convolve) < (TILE_SIZE - radius) && idx_convolve < max_idx_convolve)
{
for (int k = -radius; k <= radius; k++)
{
int k_idx = k + radius;
sum += local_buf[threadIdx.dim_to_convolve + k]*filter[k_idx];
}
result[a_idxY*width + a_idxX] = sum;
}
} | .file "tmpxft_0016ba03_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z18convolution_tilingPKfS0_PfPKfS0_Pf
.type _Z44__device_stub__Z18convolution_tilingPKfS0_PfPKfS0_Pf, @function
_Z44__device_stub__Z18convolution_tilingPKfS0_PfPKfS0_Pf:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18convolution_tilingPKfS0_Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z18convolution_tilingPKfS0_PfPKfS0_Pf, .-_Z44__device_stub__Z18convolution_tilingPKfS0_PfPKfS0_Pf
.globl _Z18convolution_tilingPKfS0_Pf
.type _Z18convolution_tilingPKfS0_Pf, @function
_Z18convolution_tilingPKfS0_Pf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z18convolution_tilingPKfS0_PfPKfS0_Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18convolution_tilingPKfS0_Pf, .-_Z18convolution_tilingPKfS0_Pf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18convolution_tilingPKfS0_Pf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18convolution_tilingPKfS0_Pf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //pass
//--blockDim=[1,128] --gridDim=[512,6]
#include <cuda.h>
//////////////////////////////////////////////////////////////////////////////
//// THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
//// ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
//// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
//// PARTICULAR PURPOSE.
////
//// Copyright (c) Microsoft Corporation. All rights reserved
//////////////////////////////////////////////////////////////////////////////
//----------------------------------------------------------------------------
// File: Convolution.cpp
//
// Implement C++ AMP based simple and tiled version of Convolution filter used in
// image processing.
//----------------------------------------------------------------------------
#define DEFAULT_WIDTH 512
#define DEFAULT_HEIGHT 512
// TILE_SIZE should be multiple of both DEFAULT_WIDTH and DEFAULT_HEIGHT
#define TILE_SIZE 128
#define width DEFAULT_WIDTH
#define height DEFAULT_HEIGHT
#define clamp(a, b, c) ((a) < (b) ? (b) : ((a) > (c) ? (c) : (a)))
#define dim_to_convolve y
#define radius 7
//----------------------------------------------------------------------------
// Tile implementation of convolution filter along different dimension
//----------------------------------------------------------------------------
__global__ void convolution_tiling(const float* img, const float* filter, float* result)
{
__shared__ float local_buf[TILE_SIZE];
int idx_convolve = (blockIdx.dim_to_convolve)*(TILE_SIZE - 2 * radius) + (int)(threadIdx.dim_to_convolve) - radius;
int max_idx_convolve = height;
float sum = 0.0f;
int a_idxY = blockIdx.y;
int a_idxX = blockIdx.x;
a_idxY = clamp(idx_convolve, 0, max_idx_convolve-1);
if (idx_convolve < (max_idx_convolve + radius))
{
local_buf[threadIdx.dim_to_convolve] = img[a_idxY*width + a_idxX];
}
#ifndef MUTATION
/* BUGINJECT: REMOVE_BARRIER, DOWN */
__syncthreads();
#endif
if ((int)(threadIdx.dim_to_convolve) >= radius && (int)(threadIdx.dim_to_convolve) < (TILE_SIZE - radius) && idx_convolve < max_idx_convolve)
{
for (int k = -radius; k <= radius; k++)
{
int k_idx = k + radius;
sum += local_buf[threadIdx.dim_to_convolve + k]*filter[k_idx];
}
result[a_idxY*width + a_idxX] = sum;
}
} | //pass
//--blockDim=[1,128] --gridDim=[512,6]
#include <hip/hip_runtime.h>
//////////////////////////////////////////////////////////////////////////////
//// THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
//// ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
//// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
//// PARTICULAR PURPOSE.
////
//// Copyright (c) Microsoft Corporation. All rights reserved
//////////////////////////////////////////////////////////////////////////////
//----------------------------------------------------------------------------
// File: Convolution.cpp
//
// Implement C++ AMP based simple and tiled version of Convolution filter used in
// image processing.
//----------------------------------------------------------------------------
#define DEFAULT_WIDTH 512
#define DEFAULT_HEIGHT 512
// TILE_SIZE should be multiple of both DEFAULT_WIDTH and DEFAULT_HEIGHT
#define TILE_SIZE 128
#define width DEFAULT_WIDTH
#define height DEFAULT_HEIGHT
#define clamp(a, b, c) ((a) < (b) ? (b) : ((a) > (c) ? (c) : (a)))
#define dim_to_convolve y
#define radius 7
//----------------------------------------------------------------------------
// Tile implementation of convolution filter along different dimension
//----------------------------------------------------------------------------
__global__ void convolution_tiling(const float* img, const float* filter, float* result)
{
__shared__ float local_buf[TILE_SIZE];
int idx_convolve = (blockIdx.dim_to_convolve)*(TILE_SIZE - 2 * radius) + (int)(threadIdx.dim_to_convolve) - radius;
int max_idx_convolve = height;
float sum = 0.0f;
int a_idxY = blockIdx.y;
int a_idxX = blockIdx.x;
a_idxY = clamp(idx_convolve, 0, max_idx_convolve-1);
if (idx_convolve < (max_idx_convolve + radius))
{
local_buf[threadIdx.dim_to_convolve] = img[a_idxY*width + a_idxX];
}
#ifndef MUTATION
/* BUGINJECT: REMOVE_BARRIER, DOWN */
__syncthreads();
#endif
if ((int)(threadIdx.dim_to_convolve) >= radius && (int)(threadIdx.dim_to_convolve) < (TILE_SIZE - radius) && idx_convolve < max_idx_convolve)
{
for (int k = -radius; k <= radius; k++)
{
int k_idx = k + radius;
sum += local_buf[threadIdx.dim_to_convolve + k]*filter[k_idx];
}
result[a_idxY*width + a_idxX] = sum;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //pass
//--blockDim=[1,128] --gridDim=[512,6]
#include <hip/hip_runtime.h>
//////////////////////////////////////////////////////////////////////////////
//// THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
//// ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
//// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
//// PARTICULAR PURPOSE.
////
//// Copyright (c) Microsoft Corporation. All rights reserved
//////////////////////////////////////////////////////////////////////////////
//----------------------------------------------------------------------------
// File: Convolution.cpp
//
// Implement C++ AMP based simple and tiled version of Convolution filter used in
// image processing.
//----------------------------------------------------------------------------
#define DEFAULT_WIDTH 512
#define DEFAULT_HEIGHT 512
// TILE_SIZE should be multiple of both DEFAULT_WIDTH and DEFAULT_HEIGHT
#define TILE_SIZE 128
#define width DEFAULT_WIDTH
#define height DEFAULT_HEIGHT
#define clamp(a, b, c) ((a) < (b) ? (b) : ((a) > (c) ? (c) : (a)))
#define dim_to_convolve y
#define radius 7
//----------------------------------------------------------------------------
// Tile implementation of convolution filter along different dimension
//----------------------------------------------------------------------------
__global__ void convolution_tiling(const float* img, const float* filter, float* result)
{
__shared__ float local_buf[TILE_SIZE];
int idx_convolve = (blockIdx.dim_to_convolve)*(TILE_SIZE - 2 * radius) + (int)(threadIdx.dim_to_convolve) - radius;
int max_idx_convolve = height;
float sum = 0.0f;
int a_idxY = blockIdx.y;
int a_idxX = blockIdx.x;
a_idxY = clamp(idx_convolve, 0, max_idx_convolve-1);
if (idx_convolve < (max_idx_convolve + radius))
{
local_buf[threadIdx.dim_to_convolve] = img[a_idxY*width + a_idxX];
}
#ifndef MUTATION
/* BUGINJECT: REMOVE_BARRIER, DOWN */
__syncthreads();
#endif
if ((int)(threadIdx.dim_to_convolve) >= radius && (int)(threadIdx.dim_to_convolve) < (TILE_SIZE - radius) && idx_convolve < max_idx_convolve)
{
for (int k = -radius; k <= radius; k++)
{
int k_idx = k + radius;
sum += local_buf[threadIdx.dim_to_convolve + k]*filter[k_idx];
}
result[a_idxY*width + a_idxX] = sum;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18convolution_tilingPKfS0_Pf
.globl _Z18convolution_tilingPKfS0_Pf
.p2align 8
.type _Z18convolution_tilingPKfS0_Pf,@function
_Z18convolution_tilingPKfS0_Pf:
v_bfe_u32 v1, v0, 10, 10
s_mulk_i32 s15, 0x72
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v2, v1, s15, -7
v_min_i32_e32 v0, 0x1ff, v2
v_cmp_lt_i32_e32 vcc_lo, -1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v0, 9, v0
v_cndmask_b32_e32 v0, 0, v0, vcc_lo
v_cmpx_gt_i32_e32 0x207, v2
s_cbranch_execz .LBB0_2
s_load_b64 s[4:5], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, s14, v0
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v3, v[3:4], off
v_lshlrev_b32_e32 v4, 2, v1
s_waitcnt vmcnt(0)
ds_store_b32 v4, v3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s2, exec_lo
v_cmpx_lt_u32_e32 6, v1
s_cbranch_execz .LBB0_7
v_cmp_gt_u32_e32 vcc_lo, 0x79, v1
v_cmp_gt_i32_e64 s2, 0x200, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_7
s_load_b64 s[2:3], s[0:1], 0x8
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v2, 2, v1
s_movk_i32 s4, 0xffe4
.LBB0_5:
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v3, s4, v2
s_waitcnt lgkmcnt(0)
s_load_b32 s5, s[2:3], 0x0
s_add_i32 s4, s4, 4
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
ds_load_b32 v3, v3
s_cmp_eq_u32 s4, 32
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v1, s5, v3
s_cbranch_scc0 .LBB0_5
s_load_b64 s[0:1], s[0:1], 0x10
v_add_nc_u32_e32 v2, s14, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[2:3], v1, off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18convolution_tilingPKfS0_Pf
.amdhsa_group_segment_fixed_size 512
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18convolution_tilingPKfS0_Pf, .Lfunc_end0-_Z18convolution_tilingPKfS0_Pf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 512
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18convolution_tilingPKfS0_Pf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18convolution_tilingPKfS0_Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //pass
//--blockDim=[1,128] --gridDim=[512,6]
#include <hip/hip_runtime.h>
//////////////////////////////////////////////////////////////////////////////
//// THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
//// ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
//// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
//// PARTICULAR PURPOSE.
////
//// Copyright (c) Microsoft Corporation. All rights reserved
//////////////////////////////////////////////////////////////////////////////
//----------------------------------------------------------------------------
// File: Convolution.cpp
//
// Implement C++ AMP based simple and tiled version of Convolution filter used in
// image processing.
//----------------------------------------------------------------------------
#define DEFAULT_WIDTH 512
#define DEFAULT_HEIGHT 512
// TILE_SIZE should be multiple of both DEFAULT_WIDTH and DEFAULT_HEIGHT
#define TILE_SIZE 128
#define width DEFAULT_WIDTH
#define height DEFAULT_HEIGHT
#define clamp(a, b, c) ((a) < (b) ? (b) : ((a) > (c) ? (c) : (a)))
#define dim_to_convolve y
#define radius 7
//----------------------------------------------------------------------------
// Tile implementation of convolution filter along different dimension
//----------------------------------------------------------------------------
__global__ void convolution_tiling(const float* img, const float* filter, float* result)
{
__shared__ float local_buf[TILE_SIZE];
int idx_convolve = (blockIdx.dim_to_convolve)*(TILE_SIZE - 2 * radius) + (int)(threadIdx.dim_to_convolve) - radius;
int max_idx_convolve = height;
float sum = 0.0f;
int a_idxY = blockIdx.y;
int a_idxX = blockIdx.x;
a_idxY = clamp(idx_convolve, 0, max_idx_convolve-1);
if (idx_convolve < (max_idx_convolve + radius))
{
local_buf[threadIdx.dim_to_convolve] = img[a_idxY*width + a_idxX];
}
#ifndef MUTATION
/* BUGINJECT: REMOVE_BARRIER, DOWN */
__syncthreads();
#endif
if ((int)(threadIdx.dim_to_convolve) >= radius && (int)(threadIdx.dim_to_convolve) < (TILE_SIZE - radius) && idx_convolve < max_idx_convolve)
{
for (int k = -radius; k <= radius; k++)
{
int k_idx = k + radius;
sum += local_buf[threadIdx.dim_to_convolve + k]*filter[k_idx];
}
result[a_idxY*width + a_idxX] = sum;
}
} | .text
.file "kernel.hip"
.globl _Z33__device_stub__convolution_tilingPKfS0_Pf # -- Begin function _Z33__device_stub__convolution_tilingPKfS0_Pf
.p2align 4, 0x90
.type _Z33__device_stub__convolution_tilingPKfS0_Pf,@function
_Z33__device_stub__convolution_tilingPKfS0_Pf: # @_Z33__device_stub__convolution_tilingPKfS0_Pf
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18convolution_tilingPKfS0_Pf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z33__device_stub__convolution_tilingPKfS0_Pf, .Lfunc_end0-_Z33__device_stub__convolution_tilingPKfS0_Pf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18convolution_tilingPKfS0_Pf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18convolution_tilingPKfS0_Pf,@object # @_Z18convolution_tilingPKfS0_Pf
.section .rodata,"a",@progbits
.globl _Z18convolution_tilingPKfS0_Pf
.p2align 3, 0x0
_Z18convolution_tilingPKfS0_Pf:
.quad _Z33__device_stub__convolution_tilingPKfS0_Pf
.size _Z18convolution_tilingPKfS0_Pf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18convolution_tilingPKfS0_Pf"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__convolution_tilingPKfS0_Pf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18convolution_tilingPKfS0_Pf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18convolution_tilingPKfS0_Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R13, SR_TID.Y ; /* 0x00000000000d7919 */
/* 0x000e220000002200 */
/*0020*/ S2UR UR6, SR_CTAID.X ; /* 0x00000000000679c3 */
/* 0x000e620000002500 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ BSSY B0, 0x140 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*0050*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000ea20000002600 */
/*0060*/ IADD3 R0, R13, -0x7, RZ ; /* 0xfffffff90d007810 */
/* 0x001fca0007ffe0ff */
/*0070*/ IMAD R2, R3, 0x72, R0 ; /* 0x0000007203027824 */
/* 0x004fca00078e0200 */
/*0080*/ ISETP.GT.AND P1, PT, R2.reuse, 0x206, PT ; /* 0x000002060200780c */
/* 0x040fe40003f24270 */
/*0090*/ ISETP.GT.AND P0, PT, R2, 0x1ff, PT ; /* 0x000001ff0200780c */
/* 0x000fc80003f04270 */
/*00a0*/ ISETP.GT.U32.OR P0, PT, R0, 0x71, P0 ; /* 0x000000710000780c */
/* 0x000fe40000704470 */
/*00b0*/ IMNMX R0, R2, 0x1ff, PT ; /* 0x000001ff02007817 */
/* 0x000fc80003800200 */
/*00c0*/ IMNMX R0, RZ, R0, !PT ; /* 0x00000000ff007217 */
/* 0x000fe20007800200 */
/*00d0*/ @P1 BRA 0x130 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*00e0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x002fe200000001ff */
/*00f0*/ LEA R2, R0, UR6, 0x9 ; /* 0x0000000600027c11 */
/* 0x000fd2000f8e48ff */
/*0100*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0203 */
/*0110*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0120*/ STS [R13.X4], R2 ; /* 0x000000020d007388 */
/* 0x0041e40000004800 */
/*0130*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*0140*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0150*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0160*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x001fe20000000f00 */
/*0170*/ LDS R25, [R13.X4+-0x1c] ; /* 0xffffe4000d197984 */
/* 0x000e220000004800 */
/*0180*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fc60000000f00 */
/*0190*/ LDS R27, [R13.X4+-0x18] ; /* 0xffffe8000d1b7984 */
/* 0x000e680000004800 */
/*01a0*/ LDG.E R22, [R2.64] ; /* 0x0000000402167981 */
/* 0x000428000c1e1900 */
/*01b0*/ LDG.E R26, [R2.64+0x4] ; /* 0x00000404021a7981 */
/* 0x000468000c1e1900 */
/*01c0*/ LDG.E R21, [R2.64+0x8] ; /* 0x0000080402157981 */
/* 0x0004e8000c1e1900 */
/*01d0*/ LDG.E R16, [R2.64+0xc] ; /* 0x00000c0402107981 */
/* 0x000528000c1e1900 */
/*01e0*/ LDG.E R15, [R2.64+0x10] ; /* 0x00001004020f7981 */
/* 0x000568000c1e1900 */
/*01f0*/ LDG.E R12, [R2.64+0x14] ; /* 0x00001404020c7981 */
/* 0x000568000c1e1900 */
/*0200*/ LDG.E R11, [R2.64+0x18] ; /* 0x00001804020b7981 */
/* 0x000568000c1e1900 */
/*0210*/ LDG.E R10, [R2.64+0x1c] ; /* 0x00001c04020a7981 */
/* 0x000568000c1e1900 */
/*0220*/ LDG.E R9, [R2.64+0x20] ; /* 0x0000200402097981 */
/* 0x000568000c1e1900 */
/*0230*/ LDG.E R8, [R2.64+0x24] ; /* 0x0000240402087981 */
/* 0x000568000c1e1900 */
/*0240*/ LDG.E R7, [R2.64+0x28] ; /* 0x0000280402077981 */
/* 0x000568000c1e1900 */
/*0250*/ LDG.E R6, [R2.64+0x2c] ; /* 0x00002c0402067981 */
/* 0x000568000c1e1900 */
/*0260*/ LDG.E R5, [R2.64+0x30] ; /* 0x0000300402057981 */
/* 0x000568000c1e1900 */
/*0270*/ LDG.E R4, [R2.64+0x34] ; /* 0x0000340402047981 */
/* 0x000568000c1e1900 */
/*0280*/ LDG.E R14, [R2.64+0x38] ; /* 0x00003804020e7981 */
/* 0x000568000c1e1900 */
/*0290*/ LDS R24, [R13.X4+-0x14] ; /* 0xffffec000d187984 */
/* 0x000ee80000004800 */
/*02a0*/ LDS R23, [R13.X4+-0x10] ; /* 0xfffff0000d177984 */
/* 0x000f280000004800 */
/*02b0*/ LDS R20, [R13.X4+-0xc] ; /* 0xfffff4000d147984 */
/* 0x000f680000004800 */
/*02c0*/ LDS R17, [R13.X4+-0x8] ; /* 0xfffff8000d117984 */
/* 0x000e280000004800 */
/*02d0*/ LDS R18, [R13.X4+-0x4] ; /* 0xfffffc000d127984 */
/* 0x000e280000004800 */
/*02e0*/ LDS R19, [R13.X4] ; /* 0x000000000d137984 */
/* 0x000e280000004800 */
/*02f0*/ LDS R3, [R13.X4+0x8] ; /* 0x000008000d037984 */
/* 0x004fe80000004800 */
/*0300*/ LDS R2, [R13.X4+0xc] ; /* 0x00000c000d027984 */
/* 0x000fe20000004800 */
/*0310*/ FFMA R25, R22, R25, RZ ; /* 0x0000001916197223 */
/* 0x001fc600000000ff */
/*0320*/ LDS R22, [R13.X4+0x4] ; /* 0x000004000d167984 */
/* 0x000e220000004800 */
/*0330*/ FFMA R25, R26, R27, R25 ; /* 0x0000001b1a197223 */
/* 0x002fc80000000019 */
/*0340*/ FFMA R25, R21, R24, R25 ; /* 0x0000001815197223 */
/* 0x008fe40000000019 */
/*0350*/ LDS R21, [R13.X4+0x10] ; /* 0x000010000d157984 */
/* 0x000e640000004800 */
/*0360*/ FFMA R16, R16, R23, R25 ; /* 0x0000001710107223 */
/* 0x010fe40000000019 */
/*0370*/ LDS R24, [R13.X4+0x14] ; /* 0x000014000d187984 */
/* 0x000ea40000004800 */
/*0380*/ FFMA R16, R15, R20, R16 ; /* 0x000000140f107223 */
/* 0x020fe40000000010 */
/*0390*/ LDS R23, [R13.X4+0x18] ; /* 0x000018000d177984 */
/* 0x000ee40000004800 */
/*03a0*/ FFMA R12, R12, R17, R16 ; /* 0x000000110c0c7223 */
/* 0x000fc40000000010 */
/*03b0*/ LDS R15, [R13.X4+0x1c] ; /* 0x00001c000d0f7984 */
/* 0x000f240000004800 */
/*03c0*/ FFMA R11, R11, R18, R12 ; /* 0x000000120b0b7223 */
/* 0x000fc8000000000c */
/*03d0*/ FFMA R10, R10, R19, R11 ; /* 0x000000130a0a7223 */
/* 0x000fc8000000000b */
/*03e0*/ FFMA R9, R9, R22, R10 ; /* 0x0000001609097223 */
/* 0x001fc8000000000a */
/*03f0*/ FFMA R3, R8, R3, R9 ; /* 0x0000000308037223 */
/* 0x000fc80000000009 */
/*0400*/ FFMA R2, R7, R2, R3 ; /* 0x0000000207027223 */
/* 0x000fe20000000003 */
/*0410*/ LEA R3, R0, UR6, 0x9 ; /* 0x0000000600037c11 */
/* 0x000fe2000f8e48ff */
/*0420*/ HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff007435 */
/* 0x000fe400000001ff */
/*0430*/ FFMA R2, R6, R21, R2 ; /* 0x0000001506027223 */
/* 0x002fc80000000002 */
/*0440*/ FFMA R2, R5, R24, R2 ; /* 0x0000001805027223 */
/* 0x004fc80000000002 */
/*0450*/ FFMA R4, R4, R23, R2 ; /* 0x0000001704047223 */
/* 0x008fe40000000002 */
/*0460*/ IMAD.WIDE R2, R3, R0, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fc800078e0200 */
/*0470*/ FFMA R15, R14, R15, R4 ; /* 0x0000000f0e0f7223 */
/* 0x010fca0000000004 */
/*0480*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x000fe2000c101904 */
/*0490*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04a0*/ BRA 0x4a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18convolution_tilingPKfS0_Pf
.globl _Z18convolution_tilingPKfS0_Pf
.p2align 8
.type _Z18convolution_tilingPKfS0_Pf,@function
_Z18convolution_tilingPKfS0_Pf:
v_bfe_u32 v1, v0, 10, 10
s_mulk_i32 s15, 0x72
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v2, v1, s15, -7
v_min_i32_e32 v0, 0x1ff, v2
v_cmp_lt_i32_e32 vcc_lo, -1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v0, 9, v0
v_cndmask_b32_e32 v0, 0, v0, vcc_lo
v_cmpx_gt_i32_e32 0x207, v2
s_cbranch_execz .LBB0_2
s_load_b64 s[4:5], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, s14, v0
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v3, v[3:4], off
v_lshlrev_b32_e32 v4, 2, v1
s_waitcnt vmcnt(0)
ds_store_b32 v4, v3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s2, exec_lo
v_cmpx_lt_u32_e32 6, v1
s_cbranch_execz .LBB0_7
v_cmp_gt_u32_e32 vcc_lo, 0x79, v1
v_cmp_gt_i32_e64 s2, 0x200, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_7
s_load_b64 s[2:3], s[0:1], 0x8
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v2, 2, v1
s_movk_i32 s4, 0xffe4
.LBB0_5:
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v3, s4, v2
s_waitcnt lgkmcnt(0)
s_load_b32 s5, s[2:3], 0x0
s_add_i32 s4, s4, 4
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
ds_load_b32 v3, v3
s_cmp_eq_u32 s4, 32
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v1, s5, v3
s_cbranch_scc0 .LBB0_5
s_load_b64 s[0:1], s[0:1], 0x10
v_add_nc_u32_e32 v2, s14, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[2:3], v1, off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18convolution_tilingPKfS0_Pf
.amdhsa_group_segment_fixed_size 512
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18convolution_tilingPKfS0_Pf, .Lfunc_end0-_Z18convolution_tilingPKfS0_Pf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 512
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18convolution_tilingPKfS0_Pf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18convolution_tilingPKfS0_Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016ba03_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z18convolution_tilingPKfS0_PfPKfS0_Pf
.type _Z44__device_stub__Z18convolution_tilingPKfS0_PfPKfS0_Pf, @function
_Z44__device_stub__Z18convolution_tilingPKfS0_PfPKfS0_Pf:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18convolution_tilingPKfS0_Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z18convolution_tilingPKfS0_PfPKfS0_Pf, .-_Z44__device_stub__Z18convolution_tilingPKfS0_PfPKfS0_Pf
.globl _Z18convolution_tilingPKfS0_Pf
.type _Z18convolution_tilingPKfS0_Pf, @function
_Z18convolution_tilingPKfS0_Pf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z18convolution_tilingPKfS0_PfPKfS0_Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18convolution_tilingPKfS0_Pf, .-_Z18convolution_tilingPKfS0_Pf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18convolution_tilingPKfS0_Pf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18convolution_tilingPKfS0_Pf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z33__device_stub__convolution_tilingPKfS0_Pf # -- Begin function _Z33__device_stub__convolution_tilingPKfS0_Pf
.p2align 4, 0x90
.type _Z33__device_stub__convolution_tilingPKfS0_Pf,@function
_Z33__device_stub__convolution_tilingPKfS0_Pf: # @_Z33__device_stub__convolution_tilingPKfS0_Pf
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18convolution_tilingPKfS0_Pf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z33__device_stub__convolution_tilingPKfS0_Pf, .Lfunc_end0-_Z33__device_stub__convolution_tilingPKfS0_Pf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18convolution_tilingPKfS0_Pf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18convolution_tilingPKfS0_Pf,@object # @_Z18convolution_tilingPKfS0_Pf
.section .rodata,"a",@progbits
.globl _Z18convolution_tilingPKfS0_Pf
.p2align 3, 0x0
_Z18convolution_tilingPKfS0_Pf:
.quad _Z33__device_stub__convolution_tilingPKfS0_Pf
.size _Z18convolution_tilingPKfS0_Pf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18convolution_tilingPKfS0_Pf"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__convolution_tilingPKfS0_Pf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18convolution_tilingPKfS0_Pf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <cmath>
#include <chrono>
#include <random>
#include <limits>
#include <cuda.h>
typedef std::chrono::high_resolution_clock Clock;
#define NUM_TEST 10000000
#define NUM_BLOCKS 1
#define NUM_THREADS 256
#define K 100
using namespace std;
// Helper function for modular exponentiation.
// Returns a^e (mode n)
__device__ unsigned long long modexp(unsigned long long a, unsigned long long e, unsigned long long n) {
unsigned long long res = 1;
a = a % n; // Compute a mod n first (if a > n)
while (e > 0)
{
// exponent is odd
if (e & 1)
res = (res * a) % n;
// exponent is even
e = e >> 1; // Shift right one (divide by 2)
a = (a * a) % n; // Set a = a^2 mod n
}
return res;
}
// Called each iteration of witness loop.
// Returns false if composite or true if probably prime
__device__ bool witnessTest(unsigned long long d, unsigned long long n, float random_num) {
// Pick a random number in [2..n-2]
// Corner cases make sure that n > 4
unsigned long long a = random_num * (n-4) + 2;
unsigned long long x = modexp(a, d, n);
if (x == 1ULL || x == n-1)
return true;
// Iterate r times (2^r * d = n - 1)
while (d != n-1) {
x = (x * x) % n;
d *= 2ULL;
if (x == 1ULL) {
return false;
}
if (x == n-1) {
return true;
}
}
// Return composite
return false;
}
// See: https://en.wikipedia.org/wiki/Miller%E2%80%93Rabin_primality_test
// Returns true if k-probably prime (k is a parameter that determines accuracy)
// Returns false if composite
__global__ void millerRabinPrimalityTest(unsigned long long *nums, unsigned len, bool *isPrime, unsigned long long k, float *random_nums) {
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx >= len) return;
int n = nums[idx];
if (n == 4ULL) {
isPrime[idx] = false;
return;
}
if (n <= 3ULL) {
isPrime[idx] = true;
return;
}
// Find r such that n = 2^d * r + 1 for some r >= 1
unsigned long long d = n - 1;
while (d % 2 == 0ULL) {
d /= 2ULL;
}
// Witness loop to repeat k times
for (unsigned long long i = 0; i < k; i++) {
if (!witnessTest(d, n, random_nums[k])){
isPrime[idx] = false;
return;
}
}
isPrime[idx] = true;
}
void random_test() {
random_device rd;
mt19937_64 eng(rd());
uniform_int_distribution<unsigned long> distr;
float *random_nums = new float[K];
for (int i=0; i<K; i++) {
random_nums[i] = (float) distr(eng) / (ULONG_MAX);
}
cout << "Starting Miller-Rabin CUDA test for " << NUM_TEST << " numbers with parameter k = " << K << ". Tests primality with accuracy " << (1 - (1/pow(4, K))) << "." << endl;
auto begin = Clock::now();
vector<unsigned long long> test;
for (int i = 0; i < NUM_TEST; i++) {
test.push_back(distr(eng));
}
unsigned long long *d_nums;
bool *d_isPrime;
float *d_random_nums;
bool *isPrime = new bool[NUM_TEST];
cudaMalloc((void **) &d_random_nums, K * sizeof(float));
cudaMalloc((void **) &d_isPrime, NUM_TEST * sizeof(bool));
cudaMalloc((void **) &d_nums, NUM_TEST * sizeof(unsigned long long));
cudaMemcpy((void *) d_nums, test.data(), NUM_TEST * sizeof(unsigned long long), cudaMemcpyHostToDevice);
cudaMemcpy((void *) d_random_nums, random_nums, K * sizeof(float), cudaMemcpyHostToDevice);
millerRabinPrimalityTest<<<(NUM_TEST + NUM_THREADS - 1)/NUM_THREADS, NUM_THREADS>>>(d_nums, test.size(), d_isPrime, K, d_random_nums);
cudaMemcpy(isPrime, d_isPrime, NUM_TEST * sizeof(bool), cudaMemcpyDeviceToHost);
auto end = Clock::now();
auto totalDuration = chrono::duration_cast<chrono::nanoseconds>(end - begin).count();
auto avgDuration = ((double) totalDuration) / NUM_TEST;
cout << "Total Time: " << totalDuration << " nanoseconds" << endl;
cout << "Average Time per iteration: " << avgDuration << " nanoseconds" << endl;
cudaFree(d_isPrime);
cudaFree(d_nums);
cudaFree(d_random_nums);
delete[] isPrime;
}
void single_test() {
random_device rd;
mt19937_64 eng(rd());
uniform_int_distribution<unsigned long> distr;
float *random_nums = new float[K];
for (int i=0; i<K; i++) {
random_nums[i] = (float) distr(eng) / (ULONG_MAX);
}
int numTest = 10;
cout << "Starting Miller-Rabin CUDA test for " << numTest << " numbers with parameter k = " << K << ". Tests primality with accuracy " << (1 - (1/pow(4, K))) << "." << endl;
auto begin = Clock::now();
vector<unsigned long long> test;
for (int i = 0; i < numTest; i++) {
test.push_back(distr(eng));
}
unsigned long long *d_nums;
bool *d_isPrime;
float *d_random_nums;
bool *isPrime = new bool[numTest];
cudaMalloc((void **) &d_random_nums, K * sizeof(float));
cudaMalloc((void **) &d_isPrime, numTest * sizeof(bool));
cudaMalloc((void **) &d_nums, numTest * sizeof(unsigned long long));
cudaMemcpy((void *) d_nums, test.data(), numTest * sizeof(unsigned long long), cudaMemcpyHostToDevice);
cudaMemcpy((void *) d_random_nums, random_nums, K * sizeof(float), cudaMemcpyHostToDevice);
millerRabinPrimalityTest<<<(numTest + NUM_THREADS - 1)/NUM_THREADS, NUM_THREADS>>>(d_nums, test.size(), d_isPrime, K, d_random_nums);
cudaMemcpy(isPrime, d_isPrime, numTest * sizeof(bool), cudaMemcpyDeviceToHost);
auto end = Clock::now();
for (int i=0; i<numTest; i++) {
cout << test[i] << " is prime: " << isPrime[i] << endl;
}
auto totalDuration = chrono::duration_cast<chrono::nanoseconds>(end - begin).count();
auto avgDuration = ((double) totalDuration) / numTest;
cout << "Total Time: " << totalDuration << " nanoseconds" << endl;
cout << "Average Time per iteration: " << avgDuration << " nanoseconds" << endl;
cudaFree(d_isPrime);
cudaFree(d_nums);
cudaFree(d_random_nums);
delete[] isPrime;
}
int main(int argc, char const *argv[]) {
random_test();
return 0;
} | code for sm_80
Function : _Z24millerRabinPrimalityTestPyjPbyPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R23, RZ, RZ, 0x8 ; /* 0x00000008ff177424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R22, R0, R23, c[0x0][0x160] ; /* 0x0000580000167625 */
/* 0x000fcc00078e0217 */
/*0090*/ LDG.E R22, [R22.64] ; /* 0x0000000816167981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IADD3 R12, P1, R0, c[0x0][0x170], RZ ; /* 0x00005c00000c7a10 */
/* 0x000fc80007f3e0ff */
/*00b0*/ LEA.HI.X.SX32 R13, R0, c[0x0][0x174], 0x1, P1 ; /* 0x00005d00000d7a11 */
/* 0x000fe400008f0eff */
/*00c0*/ ISETP.NE.U32.AND P0, PT, R22, 0x4, PT ; /* 0x000000041600780c */
/* 0x004fc80003f05070 */
/*00d0*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fda0003f05300 */
/*00e0*/ @!P0 BRA 0xd20 ; /* 0x00000c3000008947 */
/* 0x000fea0003800000 */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R22, 0x4, PT ; /* 0x000000041600780c */
/* 0x000fe40003f06070 */
/*0100*/ SHF.R.S32.HI R23, RZ, 0x1f, R22 ; /* 0x0000001fff177819 */
/* 0x000fc80000011416 */
/*0110*/ ISETP.GE.U32.AND.EX P0, PT, R23, RZ, PT, P0 ; /* 0x000000ff1700720c */
/* 0x000fda0003f06100 */
/*0120*/ @!P0 BRA 0xcf0 ; /* 0x00000bc000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R0, R22, -0x1, RZ ; /* 0xffffffff16007810 */
/* 0x000fe20007ffe0ff */
/*0140*/ BSSY B0, 0x1f0 ; /* 0x000000a000007945 */
/* 0x000fe60003800000 */
/*0150*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fe40000011400 */
/*0160*/ LOP3.LUT R2, R0.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100027812 */
/* 0x040fe200078ec0ff */
/*0170*/ IMAD.MOV.U32 R11, RZ, RZ, R0 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0000 */
/*0180*/ SHF.R.U64 R0, R0, 0x1, R3.reuse ; /* 0x0000000100007819 */
/* 0x100fe20000001203 */
/*0190*/ IMAD.MOV.U32 R10, RZ, RZ, R3.reuse ; /* 0x000000ffff0a7224 */
/* 0x100fe200078e0003 */
/*01a0*/ ISETP.NE.U32.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe40003f05070 */
/*01b0*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc40000011603 */
/*01c0*/ ISETP.NE.U32.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fda0003f05100 */
/*01d0*/ @P0 BRA 0x160 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*01e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01f0*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe20003f05070 */
/*0200*/ BSSY B0, 0xca0 ; /* 0x00000a9000007945 */
/* 0x000fe60003800000 */
/*0210*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fda0003f05300 */
/*0220*/ @!P0 BRA 0xc90 ; /* 0x00000a6000008947 */
/* 0x000fea0003800000 */
/*0230*/ ULDC.64 UR6, c[0x0][0x178] ; /* 0x00005e0000067ab9 */
/* 0x000fe40000000a00 */
/*0240*/ ULDC.64 UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fe40000000a00 */
/*0250*/ ULEA UR4, UP0, UR6, UR4, 0x2 ; /* 0x0000000406047291 */
/* 0x000fc8000f80103f */
/*0260*/ ULEA.HI.X UR5, UR6, UR5, UR7, 0x2, UP0 ; /* 0x0000000506057291 */
/* 0x000fe400080f1407 */
/*0270*/ IMAD.U32 R14, RZ, RZ, UR4 ; /* 0x00000004ff0e7e24 */
/* 0x000fc8000f8e00ff */
/*0280*/ IMAD.U32 R15, RZ, RZ, UR5 ; /* 0x00000005ff0f7e24 */
/* 0x000fca000f8e00ff */
/*0290*/ LDG.E R7, [R14.64] ; /* 0x000000080e077981 */
/* 0x000ea2000c1e1900 */
/*02a0*/ IADD3 R2, P0, R22.reuse, -0x4, RZ ; /* 0xfffffffc16027810 */
/* 0x040fe20007f1e0ff */
/*02b0*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */
/* 0x000fe200000001ff */
/*02c0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe400078e00ff */
/*02d0*/ IADD3.X R3, R23.reuse, -0x1, RZ, P0, !PT ; /* 0xffffffff17037810 */
/* 0x040fe400007fe4ff */
/*02e0*/ IADD3 R9, P0, R22, -0x1, RZ ; /* 0xffffffff16097810 */
/* 0x000fe40007f1e0ff */
/*02f0*/ I2F.U64 R2, R2 ; /* 0x0000000200027312 */
/* 0x000ea40000301000 */
/*0300*/ IADD3.X R6, R23, -0x1, RZ, P0, !PT ; /* 0xffffffff17067810 */
/* 0x000fe200007fe4ff */
/*0310*/ FFMA R7, R2, R7, 2 ; /* 0x4000000002077423 */
/* 0x004fca0000000007 */
/*0320*/ ISETP.NE.U32.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f05070 */
/*0330*/ BSSY B1, 0x8b0 ; /* 0x0000057000017945 */
/* 0x000fe20003800000 */
/*0340*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fc400078e00ff */
/*0350*/ ISETP.NE.AND.EX P0, PT, R10, RZ, PT, P0 ; /* 0x000000ff0a00720c */
/* 0x000fe20003f05300 */
/*0360*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fd800078e00ff */
/*0370*/ @!P0 BRA 0x8a0 ; /* 0x0000052000008947 */
/* 0x000fea0003800000 */
/*0380*/ F2I.U64.TRUNC R2, R7 ; /* 0x0000000700027311 */
/* 0x000e22000020d800 */
/*0390*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fe400078e00ff */
/*03a0*/ IMAD.MOV.U32 R24, RZ, RZ, R11 ; /* 0x000000ffff187224 */
/* 0x000fe400078e000b */
/*03b0*/ IMAD.MOV.U32 R25, RZ, RZ, R10 ; /* 0x000000ffff197224 */
/* 0x000fe400078e000a */
/*03c0*/ IMAD.MOV.U32 R0, RZ, RZ, R3 ; /* 0x000000ffff007224 */
/* 0x001fe200078e0003 */
/*03d0*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fc80000000f00 */
/*03e0*/ LOP3.LUT R14, R0, R23, RZ, 0xfc, !PT ; /* 0x00000017000e7212 */
/* 0x000fe200078efcff */
/*03f0*/ BSSY B2, 0x5b0 ; /* 0x000001b000027945 */
/* 0x000fe60003800000 */
/*0400*/ ISETP.NE.U32.AND P0, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fda0003f05070 */
/*0410*/ @!P0 BRA 0x470 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0420*/ MOV R20, 0x440 ; /* 0x0000044000147802 */
/* 0x000fe40000000f00 */
/*0430*/ CALL.REL.NOINC 0xd40 ; /* 0x0000090000007944 */
/* 0x000fea0003c00000 */
/*0440*/ IMAD.MOV.U32 R14, RZ, RZ, R0 ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e0000 */
/*0450*/ IMAD.MOV.U32 R15, RZ, RZ, R17 ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e0011 */
/*0460*/ BRA 0x5a0 ; /* 0x0000013000007947 */
/* 0x000fea0003800000 */
/*0470*/ I2F.U32.RP R0, R22 ; /* 0x0000001600007306 */
/* 0x000e220000209000 */
/*0480*/ IMAD.MOV R17, RZ, RZ, -R22 ; /* 0x000000ffff117224 */
/* 0x000fe200078e0a16 */
/*0490*/ ISETP.NE.U32.AND P1, PT, R22, RZ, PT ; /* 0x000000ff1600720c */
/* 0x000fcc0003f25070 */
/*04a0*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*04b0*/ IADD3 R14, R0, 0xffffffe, RZ ; /* 0x0ffffffe000e7810 */
/* 0x001fcc0007ffe0ff */
/*04c0*/ F2I.FTZ.U32.TRUNC.NTZ R15, R14 ; /* 0x0000000e000f7305 */
/* 0x000064000021f000 */
/*04d0*/ HFMA2.MMA R14, -RZ, RZ, 0, 0 ; /* 0x00000000ff0e7435 */
/* 0x001fe200000001ff */
/*04e0*/ IMAD R17, R17, R15, RZ ; /* 0x0000000f11117224 */
/* 0x002fd200078e02ff */
/*04f0*/ IMAD.HI.U32 R15, R15, R17, R14 ; /* 0x000000110f0f7227 */
/* 0x000fcc00078e000e */
/*0500*/ IMAD.HI.U32 R15, R15, R2, RZ ; /* 0x000000020f0f7227 */
/* 0x000fc800078e00ff */
/*0510*/ IMAD.MOV R15, RZ, RZ, -R15 ; /* 0x000000ffff0f7224 */
/* 0x000fc800078e0a0f */
/*0520*/ IMAD R17, R22, R15, R2 ; /* 0x0000000f16117224 */
/* 0x000fe400078e0202 */
/*0530*/ IMAD.MOV.U32 R15, RZ, RZ, RZ ; /* 0x000000ffff0f7224 */
/* 0x000fc600078e00ff */
/*0540*/ ISETP.GE.U32.AND P0, PT, R17, R22, PT ; /* 0x000000161100720c */
/* 0x000fda0003f06070 */
/*0550*/ @P0 IMAD.IADD R17, R17, 0x1, -R22 ; /* 0x0000000111110824 */
/* 0x000fca00078e0a16 */
/*0560*/ ISETP.GE.U32.AND P0, PT, R17, R22, PT ; /* 0x000000161100720c */
/* 0x000fda0003f06070 */
/*0570*/ @P0 IMAD.IADD R17, R17, 0x1, -R22 ; /* 0x0000000111110824 */
/* 0x000fe200078e0a16 */
/*0580*/ @!P1 LOP3.LUT R17, RZ, R22, RZ, 0x33, !PT ; /* 0x00000016ff119212 */
/* 0x000fca00078e33ff */
/*0590*/ IMAD.MOV.U32 R14, RZ, RZ, R17 ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e0011 */
/*05a0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*05b0*/ LOP3.LUT R0, R24, 0x1, RZ, 0xc0, !PT ; /* 0x0000000118007812 */
/* 0x000fe200078ec0ff */
/*05c0*/ BSSY B2, 0x800 ; /* 0x0000023000027945 */
/* 0x000fe60003800000 */
/*05d0*/ ISETP.NE.U32.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc80003f05070 */
/*05e0*/ ISETP.NE.U32.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fda0003f05100 */
/*05f0*/ @P0 BRA 0x7f0 ; /* 0x000001f000000947 */
/* 0x000fea0003800000 */
/*0600*/ IMAD R0, R15, R4.reuse, RZ ; /* 0x000000040f007224 */
/* 0x080fe400078e02ff */
/*0610*/ IMAD.WIDE.U32 R16, R14, R4, RZ ; /* 0x000000040e107225 */
/* 0x000fc800078e00ff */
/*0620*/ IMAD R3, R14, R3, R0 ; /* 0x000000030e037224 */
/* 0x000fca00078e0200 */
/*0630*/ IADD3 R0, R17, R3, RZ ; /* 0x0000000311007210 */
/* 0x000fc80007ffe0ff */
/*0640*/ LOP3.LUT R2, R0, R23, RZ, 0xfc, !PT ; /* 0x0000001700027212 */
/* 0x000fc800078efcff */
/*0650*/ ISETP.NE.U32.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05070 */
/*0660*/ @!P0 BRA 0x6d0 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*0670*/ IMAD.MOV.U32 R2, RZ, RZ, R16 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0010 */
/*0680*/ MOV R20, 0x6a0 ; /* 0x000006a000147802 */
/* 0x000fe40000000f00 */
/*0690*/ CALL.REL.NOINC 0xd40 ; /* 0x000006a000007944 */
/* 0x000fea0003c00000 */
/*06a0*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*06b0*/ IMAD.MOV.U32 R3, RZ, RZ, R17 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0011 */
/*06c0*/ BRA 0x7f0 ; /* 0x0000012000007947 */
/* 0x000fea0003800000 */
/*06d0*/ I2F.U32.RP R17, R22 ; /* 0x0000001600117306 */
/* 0x000e220000209000 */
/*06e0*/ IMAD.MOV R19, RZ, RZ, -R22 ; /* 0x000000ffff137224 */
/* 0x000fe200078e0a16 */
/*06f0*/ ISETP.NE.U32.AND P1, PT, R22, RZ, PT ; /* 0x000000ff1600720c */
/* 0x000fcc0003f25070 */
/*0700*/ MUFU.RCP R17, R17 ; /* 0x0000001100117308 */
/* 0x001e240000001000 */
/*0710*/ IADD3 R2, R17, 0xffffffe, RZ ; /* 0x0ffffffe11027810 */
/* 0x001fcc0007ffe0ff */
/*0720*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0730*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0740*/ IMAD R19, R19, R3, RZ ; /* 0x0000000313137224 */
/* 0x002fc800078e02ff */
/*0750*/ IMAD.HI.U32 R19, R3, R19, R2 ; /* 0x0000001303137227 */
/* 0x000fcc00078e0002 */
/*0760*/ IMAD.HI.U32 R0, R19, R16, RZ ; /* 0x0000001013007227 */
/* 0x000fca00078e00ff */
/*0770*/ IADD3 R3, -R0, RZ, RZ ; /* 0x000000ff00037210 */
/* 0x000fca0007ffe1ff */
/*0780*/ IMAD R4, R22, R3, R16 ; /* 0x0000000316047224 */
/* 0x000fe400078e0210 */
/*0790*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fc600078e00ff */
/*07a0*/ ISETP.GE.U32.AND P0, PT, R4, R22, PT ; /* 0x000000160400720c */
/* 0x000fda0003f06070 */
/*07b0*/ @P0 IMAD.IADD R4, R4, 0x1, -R22 ; /* 0x0000000104040824 */
/* 0x000fca00078e0a16 */
/*07c0*/ ISETP.GE.U32.AND P0, PT, R4, R22, PT ; /* 0x000000160400720c */
/* 0x000fda0003f06070 */
/*07d0*/ @P0 IMAD.IADD R4, R4, 0x1, -R22 ; /* 0x0000000104040824 */
/* 0x000fe200078e0a16 */
/*07e0*/ @!P1 LOP3.LUT R4, RZ, R22, RZ, 0x33, !PT ; /* 0x00000016ff049212 */
/* 0x000fe400078e33ff */
/*07f0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0800*/ SHF.R.U64 R24, R24, 0x1, R25.reuse ; /* 0x0000000118187819 */
/* 0x100fe20000001219 */
/*0810*/ IMAD R19, R15, R14.reuse, RZ ; /* 0x0000000e0f137224 */
/* 0x080fe200078e02ff */
/*0820*/ SHF.R.U32.HI R25, RZ, 0x1, R25 ; /* 0x00000001ff197819 */
/* 0x000fe20000011619 */
/*0830*/ IMAD.WIDE.U32 R16, R14, R14, RZ ; /* 0x0000000e0e107225 */
/* 0x000fe200078e00ff */
/*0840*/ ISETP.NE.U32.AND P0, PT, R24, RZ, PT ; /* 0x000000ff1800720c */
/* 0x000fc60003f05070 */
/*0850*/ IMAD R19, R14, R15, R19 ; /* 0x0000000f0e137224 */
/* 0x000fe200078e0213 */
/*0860*/ ISETP.NE.AND.EX P0, PT, R25, RZ, PT, P0 ; /* 0x000000ff1900720c */
/* 0x000fe20003f05300 */
/*0870*/ IMAD.MOV.U32 R2, RZ, RZ, R16 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0010 */
/*0880*/ IMAD.IADD R0, R17, 0x1, R19 ; /* 0x0000000111007824 */
/* 0x000fd400078e0213 */
/*0890*/ @P0 BRA 0x3e0 ; /* 0xfffffb4000000947 */
/* 0x000fea000383ffff */
/*08a0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*08b0*/ ISETP.NE.U32.AND P1, PT, R4.reuse, R9, PT ; /* 0x000000090400720c */
/* 0x040fe20003f25070 */
/*08c0*/ BSSY B1, 0xc30 ; /* 0x0000036000017945 */
/* 0x000fe20003800000 */
/*08d0*/ ISETP.EQ.U32.AND P2, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fe40003f42070 */
/*08e0*/ ISETP.NE.AND.EX P1, PT, R3.reuse, R6, PT, P1 ; /* 0x000000060300720c */
/* 0x040fe40003f25310 */
/*08f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0900*/ ISETP.EQ.OR.EX P1, PT, R3, RZ, !P1, P2 ; /* 0x000000ff0300720c */
/* 0x000fda0004f22720 */
/*0910*/ @P1 BRA 0xc20 ; /* 0x0000030000001947 */
/* 0x000fea0003800000 */
/*0920*/ MOV R14, R11 ; /* 0x0000000b000e7202 */
/* 0x000fe20000000f00 */
/*0930*/ IMAD.MOV.U32 R15, RZ, RZ, R10 ; /* 0x000000ffff0f7224 */
/* 0x000fc600078e000a */
/*0940*/ ISETP.NE.U32.AND P1, PT, R14, R9, PT ; /* 0x000000090e00720c */
/* 0x000fe40003f25070 */
/*0950*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*0960*/ ISETP.NE.AND.EX P1, PT, R15, R6, PT, P1 ; /* 0x000000060f00720c */
/* 0x000fda0003f25310 */
/*0970*/ @!P1 BRA 0xc20 ; /* 0x000002a000009947 */
/* 0x000fea0003800000 */
/*0980*/ IMAD R0, R3, R4.reuse, RZ ; /* 0x0000000403007224 */
/* 0x080fe200078e02ff */
/*0990*/ BSSY B2, 0xb90 ; /* 0x000001f000027945 */
/* 0x000fe20003800000 */
/*09a0*/ IMAD.WIDE.U32 R16, R4, R4, RZ ; /* 0x0000000404107225 */
/* 0x000fc800078e00ff */
/*09b0*/ IMAD R3, R4, R3, R0 ; /* 0x0000000304037224 */
/* 0x000fc800078e0200 */
/*09c0*/ IMAD.IADD R0, R17, 0x1, R3 ; /* 0x0000000111007824 */
/* 0x000fca00078e0203 */
/*09d0*/ LOP3.LUT R2, R0, R23, RZ, 0xfc, !PT ; /* 0x0000001700027212 */
/* 0x000fc800078efcff */
/*09e0*/ ISETP.NE.U32.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f25070 */
/*09f0*/ @!P1 BRA 0xa60 ; /* 0x0000006000009947 */
/* 0x000fea0003800000 */
/*0a00*/ IMAD.MOV.U32 R2, RZ, RZ, R16 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0010 */
/*0a10*/ MOV R20, 0xa30 ; /* 0x00000a3000147802 */
/* 0x000fe40000000f00 */
/*0a20*/ CALL.REL.NOINC 0xd40 ; /* 0x0000031000007944 */
/* 0x000fea0003c00000 */
/*0a30*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*0a40*/ IMAD.MOV.U32 R3, RZ, RZ, R17 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0011 */
/*0a50*/ BRA 0xb80 ; /* 0x0000012000007947 */
/* 0x000fea0003800000 */
/*0a60*/ I2F.U32.RP R17, R22 ; /* 0x0000001600117306 */
/* 0x000e220000209000 */
/*0a70*/ IADD3 R19, RZ, -R22, RZ ; /* 0x80000016ff137210 */
/* 0x000fe40007ffe0ff */
/*0a80*/ ISETP.NE.U32.AND P2, PT, R22, RZ, PT ; /* 0x000000ff1600720c */
/* 0x000fca0003f45070 */
/*0a90*/ MUFU.RCP R17, R17 ; /* 0x0000001100117308 */
/* 0x001e240000001000 */
/*0aa0*/ IADD3 R2, R17, 0xffffffe, RZ ; /* 0x0ffffffe11027810 */
/* 0x001fcc0007ffe0ff */
/*0ab0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0ac0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0ad0*/ IMAD R19, R19, R3, RZ ; /* 0x0000000313137224 */
/* 0x002fc800078e02ff */
/*0ae0*/ IMAD.HI.U32 R19, R3, R19, R2 ; /* 0x0000001303137227 */
/* 0x000fcc00078e0002 */
/*0af0*/ IMAD.HI.U32 R0, R19, R16, RZ ; /* 0x0000001013007227 */
/* 0x000fc800078e00ff */
/*0b00*/ IMAD.MOV R3, RZ, RZ, -R0 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a00 */
/*0b10*/ IMAD R4, R22, R3, R16 ; /* 0x0000000316047224 */
/* 0x000fe200078e0210 */
/*0b20*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fc800000001ff */
/*0b30*/ ISETP.GE.U32.AND P1, PT, R4, R22, PT ; /* 0x000000160400720c */
/* 0x000fda0003f26070 */
/*0b40*/ @P1 IMAD.IADD R4, R4, 0x1, -R22 ; /* 0x0000000104041824 */
/* 0x000fca00078e0a16 */
/*0b50*/ ISETP.GE.U32.AND P1, PT, R4, R22, PT ; /* 0x000000160400720c */
/* 0x000fda0003f26070 */
/*0b60*/ @P1 IMAD.IADD R4, R4, 0x1, -R22 ; /* 0x0000000104041824 */
/* 0x000fe200078e0a16 */
/*0b70*/ @!P2 LOP3.LUT R4, RZ, R22, RZ, 0x33, !PT ; /* 0x00000016ff04a212 */
/* 0x000fe400078e33ff */
/*0b80*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0b90*/ ISETP.NE.U32.AND P1, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fc80003f25070 */
/*0ba0*/ ISETP.NE.AND.EX P1, PT, R3, RZ, PT, P1 ; /* 0x000000ff0300720c */
/* 0x000fda0003f25310 */
/*0bb0*/ @!P1 BRA 0xc20 ; /* 0x0000006000009947 */
/* 0x000fea0003800000 */
/*0bc0*/ ISETP.NE.U32.AND P0, PT, R4, R9, PT ; /* 0x000000090400720c */
/* 0x000fe40003f05070 */
/*0bd0*/ SHF.L.U64.HI R15, R14.reuse, 0x1, R15 ; /* 0x000000010e0f7819 */
/* 0x040fe2000001020f */
/*0be0*/ IMAD.SHL.U32 R14, R14, 0x2, RZ ; /* 0x000000020e0e7824 */
/* 0x000fe200078e00ff */
/*0bf0*/ ISETP.NE.AND.EX P0, PT, R3, R6, PT, P0 ; /* 0x000000060300720c */
/* 0x000fda0003f05300 */
/*0c00*/ @P0 BRA 0x940 ; /* 0xfffffd3000000947 */
/* 0x000fea000383ffff */
/*0c10*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fd00003f0e170 */
/*0c20*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0c30*/ IADD3 R8, P1, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fca0007f3e0ff */
/*0c40*/ IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff057224 */
/* 0x000fe200008e0605 */
/*0c50*/ @P0 BRA 0xcd0 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0c60*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0c */
/* 0x000fc80003f06070 */
/*0c70*/ ISETP.GE.U32.AND.EX P0, PT, R5, c[0x0][0x17c], PT, P0 ; /* 0x00005f0005007a0c */
/* 0x000fda0003f06100 */
/*0c80*/ @!P0 BRA 0x320 ; /* 0xfffff69000008947 */
/* 0x000fea000383ffff */
/*0c90*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0ca0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fca00078e00ff */
/*0cb0*/ STG.E.U8 [R12.64], R6 ; /* 0x000000060c007986 */
/* 0x000fe2000c101108 */
/*0cc0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0cd0*/ STG.E.U8 [R12.64], RZ ; /* 0x000000ff0c007986 */
/* 0x000fe2000c101108 */
/*0ce0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0cf0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fca00078e00ff */
/*0d00*/ STG.E.U8 [R12.64], R6 ; /* 0x000000060c007986 */
/* 0x000fe2000c101108 */
/*0d10*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d20*/ STG.E.U8 [R12.64], RZ ; /* 0x000000ff0c007986 */
/* 0x000fe2000c101108 */
/*0d30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d40*/ MOV R28, R22 ; /* 0x00000016001c7202 */
/* 0x000fe20000000f00 */
/*0d50*/ IMAD.MOV.U32 R29, RZ, RZ, R23 ; /* 0x000000ffff1d7224 */
/* 0x000fc800078e0017 */
/*0d60*/ I2F.U64.RP R26, R28 ; /* 0x0000001c001a7312 */
/* 0x000e300000309000 */
/*0d70*/ MUFU.RCP R26, R26 ; /* 0x0000001a001a7308 */
/* 0x001e240000001000 */
/*0d80*/ IADD3 R17, R26, 0x1ffffffe, RZ ; /* 0x1ffffffe1a117810 */
/* 0x001fcc0007ffe0ff */
/*0d90*/ F2I.U64.TRUNC R16, R17 ; /* 0x0000001100107311 */
/* 0x000e24000020d800 */
/*0da0*/ IMAD.WIDE.U32 R18, R16, R22, RZ ; /* 0x0000001610127225 */
/* 0x001fc800078e00ff */
/*0db0*/ IMAD R19, R16, R23, R19 ; /* 0x0000001710137224 */
/* 0x000fe200078e0213 */
/*0dc0*/ IADD3 R21, P1, RZ, -R18, RZ ; /* 0x80000012ff157210 */
/* 0x000fc60007f3e0ff */
/*0dd0*/ IMAD R19, R17, R22, R19 ; /* 0x0000001611137224 */
/* 0x000fe400078e0213 */
/*0de0*/ IMAD.HI.U32 R18, R16, R21, RZ ; /* 0x0000001510127227 */
/* 0x000fc800078e00ff */
/*0df0*/ IMAD.X R27, RZ, RZ, ~R19, P1 ; /* 0x000000ffff1b7224 */
/* 0x000fe400008e0e13 */
/*0e00*/ IMAD.MOV.U32 R19, RZ, RZ, R16 ; /* 0x000000ffff137224 */
/* 0x000fc800078e0010 */
/*0e10*/ IMAD.WIDE.U32 R18, P1, R16, R27, R18 ; /* 0x0000001b10127225 */
/* 0x000fc80007820012 */
/*0e20*/ IMAD R16, R17.reuse, R27, RZ ; /* 0x0000001b11107224 */
/* 0x040fe400078e02ff */
/*0e30*/ IMAD.HI.U32 R21, P2, R17, R21, R18 ; /* 0x0000001511157227 */
/* 0x000fc80007840012 */
/*0e40*/ IMAD.HI.U32 R27, R17, R27, RZ ; /* 0x0000001b111b7227 */
/* 0x000fe200078e00ff */
/*0e50*/ IADD3 R19, P3, R16, R21, RZ ; /* 0x0000001510137210 */
/* 0x000fc60007f7e0ff */
/*0e60*/ IMAD.X R17, R27, 0x1, R17, P1 ; /* 0x000000011b117824 */
/* 0x000fe400008e0611 */
/*0e70*/ IMAD.WIDE.U32 R26, R19, R22, RZ ; /* 0x00000016131a7225 */
/* 0x000fc600078e00ff */
/*0e80*/ IADD3.X R17, RZ, RZ, R17, P3, P2 ; /* 0x000000ffff117210 */
/* 0x000fe20001fe4411 */
/*0e90*/ IMAD R16, R19, R23, R27 ; /* 0x0000001713107224 */
/* 0x000fe200078e021b */
/*0ea0*/ IADD3 R21, P1, RZ, -R26, RZ ; /* 0x8000001aff157210 */
/* 0x000fc60007f3e0ff */
/*0eb0*/ IMAD R16, R17, R22, R16 ; /* 0x0000001611107224 */
/* 0x000fe400078e0210 */
/*0ec0*/ IMAD.HI.U32 R18, R19, R21, RZ ; /* 0x0000001513127227 */
/* 0x000fc600078e00ff */
/*0ed0*/ IADD3.X R16, RZ, ~R16, RZ, P1, !PT ; /* 0x80000010ff107210 */
/* 0x000fca0000ffe4ff */
/*0ee0*/ IMAD.WIDE.U32 R18, P1, R19, R16, R18 ; /* 0x0000001013127225 */
/* 0x000fcc0007820012 */
/*0ef0*/ IMAD.HI.U32 R21, P2, R17, R21, R18 ; /* 0x0000001511157227 */
/* 0x000fc80007840012 */
/*0f00*/ IMAD R18, R17.reuse, R16.reuse, RZ ; /* 0x0000001011127224 */
/* 0x0c0fe400078e02ff */
/*0f10*/ IMAD.HI.U32 R16, R17, R16, RZ ; /* 0x0000001011107227 */
/* 0x000fc600078e00ff */
/*0f20*/ IADD3 R21, P3, R18, R21, RZ ; /* 0x0000001512157210 */
/* 0x000fe20007f7e0ff */
/*0f30*/ IMAD.X R19, R16, 0x1, R17, P1 ; /* 0x0000000110137824 */
/* 0x000fe400008e0611 */
/*0f40*/ IMAD.MOV.U32 R17, RZ, RZ, RZ ; /* 0x000000ffff117224 */
/* 0x000fe400078e00ff */
/*0f50*/ IMAD.HI.U32 R16, R21, R2, RZ ; /* 0x0000000215107227 */
/* 0x000fe200078e00ff */
/*0f60*/ IADD3.X R19, RZ, RZ, R19, P3, P2 ; /* 0x000000ffff137210 */
/* 0x000fca0001fe4413 */
/*0f70*/ IMAD.WIDE.U32 R16, R21, R0, R16 ; /* 0x0000000015107225 */
/* 0x000fc800078e0010 */
/*0f80*/ IMAD R18, R19.reuse, R0, RZ ; /* 0x0000000013127224 */
/* 0x040fe400078e02ff */
/*0f90*/ IMAD.HI.U32 R17, P1, R19, R2, R16 ; /* 0x0000000213117227 */
/* 0x000fc80007820010 */
/*0fa0*/ IMAD.HI.U32 R19, R19, R0, RZ ; /* 0x0000000013137227 */
/* 0x000fe200078e00ff */
/*0fb0*/ IADD3 R21, P2, R18, R17, RZ ; /* 0x0000001112157210 */
/* 0x000fc60007f5e0ff */
/*0fc0*/ IMAD.X R19, RZ, RZ, R19, P1 ; /* 0x000000ffff137224 */
/* 0x000fe400008e0613 */
/*0fd0*/ IMAD.WIDE.U32 R16, R21, R22, RZ ; /* 0x0000001615107225 */
/* 0x000fc800078e00ff */
/*0fe0*/ IMAD.X R19, RZ, RZ, R19, P2 ; /* 0x000000ffff137224 */
/* 0x000fe400010e0613 */
/*0ff0*/ IMAD R21, R21, R23, R17 ; /* 0x0000001715157224 */
/* 0x000fe200078e0211 */
/*1000*/ IADD3 R17, P2, -R16, R2, RZ ; /* 0x0000000210117210 */
/* 0x000fc60007f5e1ff */
/*1010*/ IMAD R19, R19, R22.reuse, R21 ; /* 0x0000001613137224 */
/* 0x080fe200078e0215 */
/*1020*/ ISETP.GE.U32.AND P1, PT, R17, R22, PT ; /* 0x000000161100720c */
/* 0x000fe20003f26070 */
/*1030*/ IMAD.MOV.U32 R21, RZ, RZ, 0x0 ; /* 0x00000000ff157424 */
/* 0x000fc600078e00ff */
/*1040*/ IADD3.X R16, ~R19, R0, RZ, P2, !PT ; /* 0x0000000013107210 */
/* 0x000fe400017fe5ff */
/*1050*/ IADD3 R0, P2, -R22, R17, RZ ; /* 0x0000001116007210 */
/* 0x000fe40007f5e1ff */
/*1060*/ ISETP.GE.U32.AND.EX P1, PT, R16, R23, PT, P1 ; /* 0x000000171000720c */
/* 0x000fc60003f26110 */
/*1070*/ IMAD.X R2, R16, 0x1, ~R23.reuse, P2 ; /* 0x0000000110027824 */
/* 0x100fe200010e0e17 */
/*1080*/ SEL R19, R0, R17, P1 ; /* 0x0000001100137207 */
/* 0x000fe40000800000 */
/*1090*/ ISETP.NE.U32.AND P2, PT, R22, RZ, PT ; /* 0x000000ff1600720c */
/* 0x000fe40003f45070 */
/*10a0*/ SEL R2, R2, R16, P1 ; /* 0x0000001002027207 */
/* 0x000fe40000800000 */
/*10b0*/ IADD3 R0, P3, -R22, R19, RZ ; /* 0x0000001316007210 */
/* 0x000fe40007f7e1ff */
/*10c0*/ ISETP.GE.U32.AND P1, PT, R19, R22, PT ; /* 0x000000161300720c */
/* 0x000fe40003f26070 */
/*10d0*/ ISETP.NE.AND.EX P2, PT, R23, RZ, PT, P2 ; /* 0x000000ff1700720c */
/* 0x000fe20003f45320 */
/*10e0*/ IMAD.X R17, R2.reuse, 0x1, ~R23, P3 ; /* 0x0000000102117824 */
/* 0x040fe200018e0e17 */
/*10f0*/ ISETP.GE.U32.AND.EX P1, PT, R2, R23, PT, P1 ; /* 0x000000170200720c */
/* 0x000fc80003f26110 */
/*1100*/ SEL R0, R0, R19, P1 ; /* 0x0000001300007207 */
/* 0x000fe40000800000 */
/*1110*/ SEL R17, R17, R2, P1 ; /* 0x0000000211117207 */
/* 0x000fe40000800000 */
/*1120*/ SEL R0, R0, 0xffffffff, P2 ; /* 0xffffffff00007807 */
/* 0x000fe40001000000 */
/*1130*/ SEL R17, R17, 0xffffffff, P2 ; /* 0xffffffff11117807 */
/* 0x000fe20001000000 */
/*1140*/ RET.REL.NODEC R20 0x0 ; /* 0xffffeeb014007950 */
/* 0x000fec0003c3ffff */
/*1150*/ BRA 0x1150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cmath>
#include <chrono>
#include <random>
#include <limits>
#include <cuda.h>
typedef std::chrono::high_resolution_clock Clock;
#define NUM_TEST 10000000
#define NUM_BLOCKS 1
#define NUM_THREADS 256
#define K 100
using namespace std;
// Helper function for modular exponentiation.
// Returns a^e (mode n)
__device__ unsigned long long modexp(unsigned long long a, unsigned long long e, unsigned long long n) {
unsigned long long res = 1;
a = a % n; // Compute a mod n first (if a > n)
while (e > 0)
{
// exponent is odd
if (e & 1)
res = (res * a) % n;
// exponent is even
e = e >> 1; // Shift right one (divide by 2)
a = (a * a) % n; // Set a = a^2 mod n
}
return res;
}
// Called each iteration of witness loop.
// Returns false if composite or true if probably prime
__device__ bool witnessTest(unsigned long long d, unsigned long long n, float random_num) {
// Pick a random number in [2..n-2]
// Corner cases make sure that n > 4
unsigned long long a = random_num * (n-4) + 2;
unsigned long long x = modexp(a, d, n);
if (x == 1ULL || x == n-1)
return true;
// Iterate r times (2^r * d = n - 1)
while (d != n-1) {
x = (x * x) % n;
d *= 2ULL;
if (x == 1ULL) {
return false;
}
if (x == n-1) {
return true;
}
}
// Return composite
return false;
}
// See: https://en.wikipedia.org/wiki/Miller%E2%80%93Rabin_primality_test
// Returns true if k-probably prime (k is a parameter that determines accuracy)
// Returns false if composite
__global__ void millerRabinPrimalityTest(unsigned long long *nums, unsigned len, bool *isPrime, unsigned long long k, float *random_nums) {
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx >= len) return;
int n = nums[idx];
if (n == 4ULL) {
isPrime[idx] = false;
return;
}
if (n <= 3ULL) {
isPrime[idx] = true;
return;
}
// Find r such that n = 2^d * r + 1 for some r >= 1
unsigned long long d = n - 1;
while (d % 2 == 0ULL) {
d /= 2ULL;
}
// Witness loop to repeat k times
for (unsigned long long i = 0; i < k; i++) {
if (!witnessTest(d, n, random_nums[k])){
isPrime[idx] = false;
return;
}
}
isPrime[idx] = true;
}
void random_test() {
random_device rd;
mt19937_64 eng(rd());
uniform_int_distribution<unsigned long> distr;
float *random_nums = new float[K];
for (int i=0; i<K; i++) {
random_nums[i] = (float) distr(eng) / (ULONG_MAX);
}
cout << "Starting Miller-Rabin CUDA test for " << NUM_TEST << " numbers with parameter k = " << K << ". Tests primality with accuracy " << (1 - (1/pow(4, K))) << "." << endl;
auto begin = Clock::now();
vector<unsigned long long> test;
for (int i = 0; i < NUM_TEST; i++) {
test.push_back(distr(eng));
}
unsigned long long *d_nums;
bool *d_isPrime;
float *d_random_nums;
bool *isPrime = new bool[NUM_TEST];
cudaMalloc((void **) &d_random_nums, K * sizeof(float));
cudaMalloc((void **) &d_isPrime, NUM_TEST * sizeof(bool));
cudaMalloc((void **) &d_nums, NUM_TEST * sizeof(unsigned long long));
cudaMemcpy((void *) d_nums, test.data(), NUM_TEST * sizeof(unsigned long long), cudaMemcpyHostToDevice);
cudaMemcpy((void *) d_random_nums, random_nums, K * sizeof(float), cudaMemcpyHostToDevice);
millerRabinPrimalityTest<<<(NUM_TEST + NUM_THREADS - 1)/NUM_THREADS, NUM_THREADS>>>(d_nums, test.size(), d_isPrime, K, d_random_nums);
cudaMemcpy(isPrime, d_isPrime, NUM_TEST * sizeof(bool), cudaMemcpyDeviceToHost);
auto end = Clock::now();
auto totalDuration = chrono::duration_cast<chrono::nanoseconds>(end - begin).count();
auto avgDuration = ((double) totalDuration) / NUM_TEST;
cout << "Total Time: " << totalDuration << " nanoseconds" << endl;
cout << "Average Time per iteration: " << avgDuration << " nanoseconds" << endl;
cudaFree(d_isPrime);
cudaFree(d_nums);
cudaFree(d_random_nums);
delete[] isPrime;
}
void single_test() {
random_device rd;
mt19937_64 eng(rd());
uniform_int_distribution<unsigned long> distr;
float *random_nums = new float[K];
for (int i=0; i<K; i++) {
random_nums[i] = (float) distr(eng) / (ULONG_MAX);
}
int numTest = 10;
cout << "Starting Miller-Rabin CUDA test for " << numTest << " numbers with parameter k = " << K << ". Tests primality with accuracy " << (1 - (1/pow(4, K))) << "." << endl;
auto begin = Clock::now();
vector<unsigned long long> test;
for (int i = 0; i < numTest; i++) {
test.push_back(distr(eng));
}
unsigned long long *d_nums;
bool *d_isPrime;
float *d_random_nums;
bool *isPrime = new bool[numTest];
cudaMalloc((void **) &d_random_nums, K * sizeof(float));
cudaMalloc((void **) &d_isPrime, numTest * sizeof(bool));
cudaMalloc((void **) &d_nums, numTest * sizeof(unsigned long long));
cudaMemcpy((void *) d_nums, test.data(), numTest * sizeof(unsigned long long), cudaMemcpyHostToDevice);
cudaMemcpy((void *) d_random_nums, random_nums, K * sizeof(float), cudaMemcpyHostToDevice);
millerRabinPrimalityTest<<<(numTest + NUM_THREADS - 1)/NUM_THREADS, NUM_THREADS>>>(d_nums, test.size(), d_isPrime, K, d_random_nums);
cudaMemcpy(isPrime, d_isPrime, numTest * sizeof(bool), cudaMemcpyDeviceToHost);
auto end = Clock::now();
for (int i=0; i<numTest; i++) {
cout << test[i] << " is prime: " << isPrime[i] << endl;
}
auto totalDuration = chrono::duration_cast<chrono::nanoseconds>(end - begin).count();
auto avgDuration = ((double) totalDuration) / numTest;
cout << "Total Time: " << totalDuration << " nanoseconds" << endl;
cout << "Average Time per iteration: " << avgDuration << " nanoseconds" << endl;
cudaFree(d_isPrime);
cudaFree(d_nums);
cudaFree(d_random_nums);
delete[] isPrime;
}
int main(int argc, char const *argv[]) {
random_test();
return 0;
} | #include <iostream>
#include <cmath>
#include <chrono>
#include <random>
#include <limits>
#include <hip/hip_runtime.h>
typedef std::chrono::high_resolution_clock Clock;
#define NUM_TEST 10000000
#define NUM_BLOCKS 1
#define NUM_THREADS 256
#define K 100
using namespace std;
// Helper function for modular exponentiation.
// Returns a^e (mode n)
__device__ unsigned long long modexp(unsigned long long a, unsigned long long e, unsigned long long n) {
unsigned long long res = 1;
a = a % n; // Compute a mod n first (if a > n)
while (e > 0)
{
// exponent is odd
if (e & 1)
res = (res * a) % n;
// exponent is even
e = e >> 1; // Shift right one (divide by 2)
a = (a * a) % n; // Set a = a^2 mod n
}
return res;
}
// Called each iteration of witness loop.
// Returns false if composite or true if probably prime
__device__ bool witnessTest(unsigned long long d, unsigned long long n, float random_num) {
// Pick a random number in [2..n-2]
// Corner cases make sure that n > 4
unsigned long long a = random_num * (n-4) + 2;
unsigned long long x = modexp(a, d, n);
if (x == 1ULL || x == n-1)
return true;
// Iterate r times (2^r * d = n - 1)
while (d != n-1) {
x = (x * x) % n;
d *= 2ULL;
if (x == 1ULL) {
return false;
}
if (x == n-1) {
return true;
}
}
// Return composite
return false;
}
// See: https://en.wikipedia.org/wiki/Miller%E2%80%93Rabin_primality_test
// Returns true if k-probably prime (k is a parameter that determines accuracy)
// Returns false if composite
__global__ void millerRabinPrimalityTest(unsigned long long *nums, unsigned len, bool *isPrime, unsigned long long k, float *random_nums) {
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx >= len) return;
int n = nums[idx];
if (n == 4ULL) {
isPrime[idx] = false;
return;
}
if (n <= 3ULL) {
isPrime[idx] = true;
return;
}
// Find r such that n = 2^d * r + 1 for some r >= 1
unsigned long long d = n - 1;
while (d % 2 == 0ULL) {
d /= 2ULL;
}
// Witness loop to repeat k times
for (unsigned long long i = 0; i < k; i++) {
if (!witnessTest(d, n, random_nums[k])){
isPrime[idx] = false;
return;
}
}
isPrime[idx] = true;
}
void random_test() {
random_device rd;
mt19937_64 eng(rd());
uniform_int_distribution<unsigned long> distr;
float *random_nums = new float[K];
for (int i=0; i<K; i++) {
random_nums[i] = (float) distr(eng) / (ULONG_MAX);
}
cout << "Starting Miller-Rabin CUDA test for " << NUM_TEST << " numbers with parameter k = " << K << ". Tests primality with accuracy " << (1 - (1/pow(4, K))) << "." << endl;
auto begin = Clock::now();
vector<unsigned long long> test;
for (int i = 0; i < NUM_TEST; i++) {
test.push_back(distr(eng));
}
unsigned long long *d_nums;
bool *d_isPrime;
float *d_random_nums;
bool *isPrime = new bool[NUM_TEST];
hipMalloc((void **) &d_random_nums, K * sizeof(float));
hipMalloc((void **) &d_isPrime, NUM_TEST * sizeof(bool));
hipMalloc((void **) &d_nums, NUM_TEST * sizeof(unsigned long long));
hipMemcpy((void *) d_nums, test.data(), NUM_TEST * sizeof(unsigned long long), hipMemcpyHostToDevice);
hipMemcpy((void *) d_random_nums, random_nums, K * sizeof(float), hipMemcpyHostToDevice);
millerRabinPrimalityTest<<<(NUM_TEST + NUM_THREADS - 1)/NUM_THREADS, NUM_THREADS>>>(d_nums, test.size(), d_isPrime, K, d_random_nums);
hipMemcpy(isPrime, d_isPrime, NUM_TEST * sizeof(bool), hipMemcpyDeviceToHost);
auto end = Clock::now();
auto totalDuration = chrono::duration_cast<chrono::nanoseconds>(end - begin).count();
auto avgDuration = ((double) totalDuration) / NUM_TEST;
cout << "Total Time: " << totalDuration << " nanoseconds" << endl;
cout << "Average Time per iteration: " << avgDuration << " nanoseconds" << endl;
hipFree(d_isPrime);
hipFree(d_nums);
hipFree(d_random_nums);
delete[] isPrime;
}
void single_test() {
random_device rd;
mt19937_64 eng(rd());
uniform_int_distribution<unsigned long> distr;
float *random_nums = new float[K];
for (int i=0; i<K; i++) {
random_nums[i] = (float) distr(eng) / (ULONG_MAX);
}
int numTest = 10;
cout << "Starting Miller-Rabin CUDA test for " << numTest << " numbers with parameter k = " << K << ". Tests primality with accuracy " << (1 - (1/pow(4, K))) << "." << endl;
auto begin = Clock::now();
vector<unsigned long long> test;
for (int i = 0; i < numTest; i++) {
test.push_back(distr(eng));
}
unsigned long long *d_nums;
bool *d_isPrime;
float *d_random_nums;
bool *isPrime = new bool[numTest];
hipMalloc((void **) &d_random_nums, K * sizeof(float));
hipMalloc((void **) &d_isPrime, numTest * sizeof(bool));
hipMalloc((void **) &d_nums, numTest * sizeof(unsigned long long));
hipMemcpy((void *) d_nums, test.data(), numTest * sizeof(unsigned long long), hipMemcpyHostToDevice);
hipMemcpy((void *) d_random_nums, random_nums, K * sizeof(float), hipMemcpyHostToDevice);
millerRabinPrimalityTest<<<(numTest + NUM_THREADS - 1)/NUM_THREADS, NUM_THREADS>>>(d_nums, test.size(), d_isPrime, K, d_random_nums);
hipMemcpy(isPrime, d_isPrime, numTest * sizeof(bool), hipMemcpyDeviceToHost);
auto end = Clock::now();
for (int i=0; i<numTest; i++) {
cout << test[i] << " is prime: " << isPrime[i] << endl;
}
auto totalDuration = chrono::duration_cast<chrono::nanoseconds>(end - begin).count();
auto avgDuration = ((double) totalDuration) / numTest;
cout << "Total Time: " << totalDuration << " nanoseconds" << endl;
cout << "Average Time per iteration: " << avgDuration << " nanoseconds" << endl;
hipFree(d_isPrime);
hipFree(d_nums);
hipFree(d_random_nums);
delete[] isPrime;
}
int main(int argc, char const *argv[]) {
random_test();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <iostream>
#include <cmath>
#include <chrono>
#include <random>
#include <limits>
#include <hip/hip_runtime.h>
typedef std::chrono::high_resolution_clock Clock;
#define NUM_TEST 10000000
#define NUM_BLOCKS 1
#define NUM_THREADS 256
#define K 100
using namespace std;
// Helper function for modular exponentiation.
// Returns a^e (mode n)
__device__ unsigned long long modexp(unsigned long long a, unsigned long long e, unsigned long long n) {
unsigned long long res = 1;
a = a % n; // Compute a mod n first (if a > n)
while (e > 0)
{
// exponent is odd
if (e & 1)
res = (res * a) % n;
// exponent is even
e = e >> 1; // Shift right one (divide by 2)
a = (a * a) % n; // Set a = a^2 mod n
}
return res;
}
// Called each iteration of witness loop.
// Returns false if composite or true if probably prime
__device__ bool witnessTest(unsigned long long d, unsigned long long n, float random_num) {
// Pick a random number in [2..n-2]
// Corner cases make sure that n > 4
unsigned long long a = random_num * (n-4) + 2;
unsigned long long x = modexp(a, d, n);
if (x == 1ULL || x == n-1)
return true;
// Iterate r times (2^r * d = n - 1)
while (d != n-1) {
x = (x * x) % n;
d *= 2ULL;
if (x == 1ULL) {
return false;
}
if (x == n-1) {
return true;
}
}
// Return composite
return false;
}
// See: https://en.wikipedia.org/wiki/Miller%E2%80%93Rabin_primality_test
// Returns true if k-probably prime (k is a parameter that determines accuracy)
// Returns false if composite
__global__ void millerRabinPrimalityTest(unsigned long long *nums, unsigned len, bool *isPrime, unsigned long long k, float *random_nums) {
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx >= len) return;
int n = nums[idx];
if (n == 4ULL) {
isPrime[idx] = false;
return;
}
if (n <= 3ULL) {
isPrime[idx] = true;
return;
}
// Find r such that n = 2^d * r + 1 for some r >= 1
unsigned long long d = n - 1;
while (d % 2 == 0ULL) {
d /= 2ULL;
}
// Witness loop to repeat k times
for (unsigned long long i = 0; i < k; i++) {
if (!witnessTest(d, n, random_nums[k])){
isPrime[idx] = false;
return;
}
}
isPrime[idx] = true;
}
void random_test() {
random_device rd;
mt19937_64 eng(rd());
uniform_int_distribution<unsigned long> distr;
float *random_nums = new float[K];
for (int i=0; i<K; i++) {
random_nums[i] = (float) distr(eng) / (ULONG_MAX);
}
cout << "Starting Miller-Rabin CUDA test for " << NUM_TEST << " numbers with parameter k = " << K << ". Tests primality with accuracy " << (1 - (1/pow(4, K))) << "." << endl;
auto begin = Clock::now();
vector<unsigned long long> test;
for (int i = 0; i < NUM_TEST; i++) {
test.push_back(distr(eng));
}
unsigned long long *d_nums;
bool *d_isPrime;
float *d_random_nums;
bool *isPrime = new bool[NUM_TEST];
hipMalloc((void **) &d_random_nums, K * sizeof(float));
hipMalloc((void **) &d_isPrime, NUM_TEST * sizeof(bool));
hipMalloc((void **) &d_nums, NUM_TEST * sizeof(unsigned long long));
hipMemcpy((void *) d_nums, test.data(), NUM_TEST * sizeof(unsigned long long), hipMemcpyHostToDevice);
hipMemcpy((void *) d_random_nums, random_nums, K * sizeof(float), hipMemcpyHostToDevice);
millerRabinPrimalityTest<<<(NUM_TEST + NUM_THREADS - 1)/NUM_THREADS, NUM_THREADS>>>(d_nums, test.size(), d_isPrime, K, d_random_nums);
hipMemcpy(isPrime, d_isPrime, NUM_TEST * sizeof(bool), hipMemcpyDeviceToHost);
auto end = Clock::now();
auto totalDuration = chrono::duration_cast<chrono::nanoseconds>(end - begin).count();
auto avgDuration = ((double) totalDuration) / NUM_TEST;
cout << "Total Time: " << totalDuration << " nanoseconds" << endl;
cout << "Average Time per iteration: " << avgDuration << " nanoseconds" << endl;
hipFree(d_isPrime);
hipFree(d_nums);
hipFree(d_random_nums);
delete[] isPrime;
}
void single_test() {
random_device rd;
mt19937_64 eng(rd());
uniform_int_distribution<unsigned long> distr;
float *random_nums = new float[K];
for (int i=0; i<K; i++) {
random_nums[i] = (float) distr(eng) / (ULONG_MAX);
}
int numTest = 10;
cout << "Starting Miller-Rabin CUDA test for " << numTest << " numbers with parameter k = " << K << ". Tests primality with accuracy " << (1 - (1/pow(4, K))) << "." << endl;
auto begin = Clock::now();
vector<unsigned long long> test;
for (int i = 0; i < numTest; i++) {
test.push_back(distr(eng));
}
unsigned long long *d_nums;
bool *d_isPrime;
float *d_random_nums;
bool *isPrime = new bool[numTest];
hipMalloc((void **) &d_random_nums, K * sizeof(float));
hipMalloc((void **) &d_isPrime, numTest * sizeof(bool));
hipMalloc((void **) &d_nums, numTest * sizeof(unsigned long long));
hipMemcpy((void *) d_nums, test.data(), numTest * sizeof(unsigned long long), hipMemcpyHostToDevice);
hipMemcpy((void *) d_random_nums, random_nums, K * sizeof(float), hipMemcpyHostToDevice);
millerRabinPrimalityTest<<<(numTest + NUM_THREADS - 1)/NUM_THREADS, NUM_THREADS>>>(d_nums, test.size(), d_isPrime, K, d_random_nums);
hipMemcpy(isPrime, d_isPrime, numTest * sizeof(bool), hipMemcpyDeviceToHost);
auto end = Clock::now();
for (int i=0; i<numTest; i++) {
cout << test[i] << " is prime: " << isPrime[i] << endl;
}
auto totalDuration = chrono::duration_cast<chrono::nanoseconds>(end - begin).count();
auto avgDuration = ((double) totalDuration) / numTest;
cout << "Total Time: " << totalDuration << " nanoseconds" << endl;
cout << "Average Time per iteration: " << avgDuration << " nanoseconds" << endl;
hipFree(d_isPrime);
hipFree(d_nums);
hipFree(d_random_nums);
delete[] isPrime;
}
int main(int argc, char const *argv[]) {
random_test();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24millerRabinPrimalityTestPyjPbyPf
.globl _Z24millerRabinPrimalityTestPyjPbyPf
.p2align 8
.type _Z24millerRabinPrimalityTestPyjPbyPf,@function
_Z24millerRabinPrimalityTestPyjPbyPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_40
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s10, exec_lo
v_mov_b32_e32 v12, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_mov_b32 s2, 0
s_mov_b32 s3, 4
global_load_b32 v4, v[3:4], off
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ne_u64_e64 s[2:3], v[3:4]
s_cbranch_execz .LBB0_39
v_ashrrev_i32_e32 v6, 31, v4
v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v12, 1
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_u64_e32 3, v[5:6]
s_cbranch_execz .LBB0_38
v_add_co_u32 v0, vcc_lo, v3, 0
v_add_co_ci_u32_e32 v9, vcc_lo, -1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v10, 31, v9
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, v9 :: v_dual_mov_b32 v8, v10
v_and_b32_e32 v0, 1, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshrrev_b64 v[9:10], 1, v[7:8]
v_cmp_eq_u32_e32 vcc_lo, 1, v0
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_4
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[4:5], s[0:1], 0x18
s_mov_b64 s[6:7], 0
s_waitcnt lgkmcnt(0)
s_cmp_eq_u64 s[4:5], 0
s_cbranch_scc1 .LBB0_37
v_cvt_f32_u32_e32 v0, v5
v_cvt_f32_u32_e32 v3, v6
v_add_co_u32 v9, vcc_lo, v5, -4
v_add_co_ci_u32_e32 v10, vcc_lo, -1, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_fmamk_f32 v0, v3, 0x4f800000, v0 :: v_dual_mov_b32 v11, 0
s_load_b64 s[8:9], s[0:1], 0x20
v_clz_i32_u32_e32 v3, v10
v_cmp_ne_u64_e64 s2, 0, v[7:8]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v0, v0
s_lshl_b64 s[12:13], s[4:5], 2
v_min_u32_e32 v3, 32, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[9:10], v3, v[9:10]
v_sub_nc_u32_e32 v3, 32, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v12, 0x5f7ffffc, v0
v_min_u32_e32 v0, 1, v9
v_mul_f32_e32 v9, 0x2f800000, v12
s_waitcnt lgkmcnt(0)
s_add_u32 s8, s8, s12
s_addc_u32 s9, s9, s13
v_or_b32_e32 v0, v10, v0
v_trunc_f32_e32 v13, v9
v_add_co_u32 v9, vcc_lo, v5, -1
v_add_co_ci_u32_e32 v10, vcc_lo, -1, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cvt_f32_u32_e32 v0, v0
v_fmac_f32_e32 v12, 0xcf800000, v13
v_cvt_u32_f32_e32 v21, v13
s_mov_b32 s12, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ldexp_f32 v0, v0, v3
v_cvt_u32_f32_e32 v3, v12
s_branch .LBB0_8
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, exec_lo, s13
s_or_b32 s12, s3, s12
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execz .LBB0_36
.LBB0_8:
v_mov_b32_e32 v13, 1
v_mov_b32_e32 v14, 0
s_and_saveexec_b32 s13, s2
s_cbranch_execz .LBB0_22
s_load_b32 s3, s[8:9], 0x0
s_mov_b32 s14, 0
s_waitcnt lgkmcnt(0)
v_fma_f32 v12, s3, v0, 2.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_trunc_f32_e32 v12, v12
v_mul_f32_e32 v13, 0x2f800000, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_floor_f32_e32 v15, v13
v_mov_b32_e32 v13, 1
v_mov_b32_e32 v14, 0
v_fmac_f32_e32 v12, 0xcf800000, v15
v_cvt_u32_f32_e32 v20, v15
v_dual_mov_b32 v16, v8 :: v_dual_mov_b32 v15, v7
s_delay_alu instid0(VALU_DEP_3)
v_cvt_u32_f32_e32 v19, v12
s_branch .LBB0_12
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s3
.LBB0_11:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
s_or_b32 exec_lo, exec_lo, s15
v_mul_lo_u32 v12, v17, v18
v_mad_u64_u32 v[19:20], null, v17, v17, 0
v_lshrrev_b64 v[17:18], 1, v[15:16]
v_cmp_gt_u64_e32 vcc_lo, 2, v[15:16]
v_dual_mov_b32 v15, v17 :: v_dual_mov_b32 v16, v18
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add3_u32 v20, v20, v12, v12
s_or_b32 s14, vcc_lo, s14
s_and_not1_b32 exec_lo, exec_lo, s14
s_cbranch_execz .LBB0_21
.LBB0_12:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_or_b32_e32 v12, v20, v6
s_mov_b32 s3, exec_lo
v_cmpx_ne_u64_e32 0, v[11:12]
s_xor_b32 s15, exec_lo, s3
s_cbranch_execz .LBB0_14
v_sub_co_u32 v12, vcc_lo, 0, v5
v_sub_co_ci_u32_e32 v26, vcc_lo, 0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[17:18], null, v12, v3, 0
v_mul_lo_u32 v22, v26, v3
v_mul_lo_u32 v23, v12, v21
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v28, v3, v17
v_mad_u64_u32 v[24:25], null, v21, v17, 0
v_add3_u32 v27, v18, v23, v22
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[22:23], null, v3, v27, 0
v_mad_u64_u32 v[17:18], null, v21, v27, 0
v_add_co_u32 v22, vcc_lo, v28, v22
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v23, vcc_lo, 0, v23, vcc_lo
v_add_co_u32 v22, vcc_lo, v22, v24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v22, vcc_lo, v23, v25, vcc_lo
v_add_co_ci_u32_e32 v18, vcc_lo, 0, v18, vcc_lo
v_add_co_u32 v17, vcc_lo, v22, v17
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v18, vcc_lo, 0, v18, vcc_lo
v_add_co_u32 v27, vcc_lo, v3, v17
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v28, vcc_lo, v21, v18, vcc_lo
v_mul_lo_u32 v22, v26, v27
v_mad_u64_u32 v[17:18], null, v12, v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v12, v12, v28
v_mul_hi_u32 v26, v27, v17
v_mad_u64_u32 v[24:25], null, v28, v17, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v12, v18, v12, v22
v_mad_u64_u32 v[22:23], null, v27, v12, 0
v_mad_u64_u32 v[17:18], null, v28, v12, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v12, vcc_lo, v26, v22
v_add_co_ci_u32_e32 v22, vcc_lo, 0, v23, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v12, vcc_lo, v12, v24
v_add_co_ci_u32_e32 v12, vcc_lo, v22, v25, vcc_lo
v_add_co_ci_u32_e32 v18, vcc_lo, 0, v18, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v12, vcc_lo, v12, v17
v_add_co_ci_u32_e32 v17, vcc_lo, 0, v18, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v12, vcc_lo, v27, v12
v_add_co_ci_u32_e32 v26, vcc_lo, v28, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v27, v19, v12
v_mad_u64_u32 v[22:23], null, v20, v12, 0
v_mad_u64_u32 v[17:18], null, v19, v26, 0
v_mad_u64_u32 v[24:25], null, v20, v26, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v12, vcc_lo, v27, v17
v_add_co_ci_u32_e32 v17, vcc_lo, 0, v18, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v12, vcc_lo, v12, v22
v_add_co_ci_u32_e32 v12, vcc_lo, v17, v23, vcc_lo
v_add_co_ci_u32_e32 v17, vcc_lo, 0, v25, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v12, vcc_lo, v12, v24
v_add_co_ci_u32_e32 v22, vcc_lo, 0, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v23, v6, v12
v_mad_u64_u32 v[17:18], null, v5, v12, 0
v_mul_lo_u32 v12, v5, v22
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v17, vcc_lo, v19, v17
v_add3_u32 v12, v18, v12, v23
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v18, v20, v12
v_sub_co_ci_u32_e64 v18, s3, v18, v6, vcc_lo
v_sub_co_ci_u32_e32 v12, vcc_lo, v20, v12, vcc_lo
v_sub_co_u32 v19, vcc_lo, v17, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_subrev_co_ci_u32_e64 v20, s3, 0, v18, vcc_lo
v_cmp_ge_u32_e64 s3, v17, v5
v_sub_co_ci_u32_e32 v18, vcc_lo, v18, v6, vcc_lo
v_cmp_ge_u32_e32 vcc_lo, v12, v6
v_cndmask_b32_e64 v22, 0, -1, s3
v_cmp_ge_u32_e64 s3, v19, v5
v_cndmask_b32_e64 v25, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, v20, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v23, 0, -1, s3
v_cmp_ge_u32_e64 s3, v20, v6
v_cndmask_b32_e64 v24, 0, -1, s3
v_cmp_eq_u32_e64 s3, v12, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v23, v24, v23, vcc_lo
v_sub_co_u32 v24, vcc_lo, v19, v5
v_subrev_co_ci_u32_e32 v18, vcc_lo, 0, v18, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v23
v_cndmask_b32_e64 v22, v25, v22, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v18, v20, v18 :: v_dual_cndmask_b32 v19, v19, v24
v_cmp_ne_u32_e32 vcc_lo, 0, v22
s_delay_alu instid0(VALU_DEP_2)
v_dual_cndmask_b32 v18, v12, v18 :: v_dual_cndmask_b32 v17, v17, v19
.LBB0_14:
s_and_not1_saveexec_b32 s3, s15
s_cbranch_execz .LBB0_16
v_cvt_f32_u32_e32 v12, v4
v_sub_nc_u32_e32 v17, 0, v4
v_mov_b32_e32 v18, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v12, v12
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v12, 0x4f7ffffe, v12
v_cvt_u32_f32_e32 v12, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v17, v17, v12
v_mul_hi_u32 v17, v12, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v12, v12, v17
v_mul_hi_u32 v12, v19, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v12, v12, v4
v_sub_nc_u32_e32 v12, v19, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v17, v12, v4
v_cmp_ge_u32_e32 vcc_lo, v12, v4
v_cndmask_b32_e32 v12, v12, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v17, v12, v4
v_cmp_ge_u32_e32 vcc_lo, v12, v4
v_cndmask_b32_e32 v17, v12, v17, vcc_lo
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s3
v_and_b32_e32 v12, 1, v15
s_mov_b32 s15, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 1, v12
s_cbranch_execz .LBB0_11
v_mul_lo_u32 v12, v18, v13
v_mul_lo_u32 v14, v17, v14
v_mad_u64_u32 v[19:20], null, v17, v13, 0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v20, v20, v14, v12
v_or_b32_e32 v12, v20, v6
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ne_u64_e32 0, v[11:12]
s_xor_b32 s16, exec_lo, s3
s_cbranch_execz .LBB0_19
v_sub_co_u32 v26, vcc_lo, 0, v5
v_sub_co_ci_u32_e32 v27, vcc_lo, 0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[12:13], null, v26, v3, 0
v_mul_lo_u32 v14, v27, v3
v_mul_lo_u32 v22, v26, v21
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v29, v3, v12
v_add3_u32 v28, v13, v22, v14
v_mad_u64_u32 v[22:23], null, v21, v12, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[13:14], null, v3, v28, 0
v_mad_u64_u32 v[24:25], null, v21, v28, 0
v_add_co_u32 v12, vcc_lo, v29, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v14, vcc_lo
v_add_co_u32 v12, vcc_lo, v12, v22
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v12, vcc_lo, v13, v23, vcc_lo
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v25, vcc_lo
v_add_co_u32 v12, vcc_lo, v12, v24
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v13, vcc_lo
v_add_co_u32 v28, vcc_lo, v3, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v29, vcc_lo, v21, v13, vcc_lo
v_mul_lo_u32 v14, v27, v28
v_mad_u64_u32 v[12:13], null, v26, v28, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v22, v26, v29
v_mul_hi_u32 v27, v28, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add3_u32 v26, v13, v22, v14
v_mad_u64_u32 v[22:23], null, v29, v12, 0
v_mad_u64_u32 v[13:14], null, v28, v26, 0
v_mad_u64_u32 v[24:25], null, v29, v26, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v12, vcc_lo, v27, v13
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v14, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v12, vcc_lo, v12, v22
v_add_co_ci_u32_e32 v12, vcc_lo, v13, v23, vcc_lo
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v25, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v12, vcc_lo, v12, v24
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v14, vcc_lo, v28, v12
v_add_co_ci_u32_e32 v26, vcc_lo, v29, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v27, v19, v14
v_mad_u64_u32 v[22:23], null, v20, v14, 0
v_mad_u64_u32 v[12:13], null, v19, v26, 0
v_mad_u64_u32 v[24:25], null, v20, v26, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v12, vcc_lo, v27, v12
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v12, vcc_lo, v12, v22
v_add_co_ci_u32_e32 v12, vcc_lo, v13, v23, vcc_lo
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v25, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v14, vcc_lo, v12, v24
v_add_co_ci_u32_e32 v22, vcc_lo, 0, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v23, v6, v14
v_mad_u64_u32 v[12:13], null, v5, v14, 0
v_mul_lo_u32 v14, v5, v22
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v12, vcc_lo, v19, v12
v_add3_u32 v13, v13, v14, v23
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v14, v20, v13
v_sub_co_ci_u32_e64 v14, s3, v14, v6, vcc_lo
v_sub_co_ci_u32_e32 v13, vcc_lo, v20, v13, vcc_lo
v_sub_co_u32 v19, vcc_lo, v12, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_subrev_co_ci_u32_e64 v20, s3, 0, v14, vcc_lo
v_cmp_ge_u32_e64 s3, v12, v5
v_sub_co_ci_u32_e32 v14, vcc_lo, v14, v6, vcc_lo
v_cmp_ge_u32_e32 vcc_lo, v13, v6
v_cndmask_b32_e64 v22, 0, -1, s3
v_cmp_ge_u32_e64 s3, v19, v5
v_cndmask_b32_e64 v25, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, v20, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v23, 0, -1, s3
v_cmp_ge_u32_e64 s3, v20, v6
v_cndmask_b32_e64 v24, 0, -1, s3
v_cmp_eq_u32_e64 s3, v13, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v23, v24, v23, vcc_lo
v_sub_co_u32 v24, vcc_lo, v19, v5
v_subrev_co_ci_u32_e32 v14, vcc_lo, 0, v14, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v23
v_cndmask_b32_e64 v22, v25, v22, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v14, v20, v14 :: v_dual_cndmask_b32 v19, v19, v24
v_cmp_ne_u32_e32 vcc_lo, 0, v22
s_delay_alu instid0(VALU_DEP_2)
v_dual_cndmask_b32 v14, v13, v14 :: v_dual_cndmask_b32 v13, v12, v19
.LBB0_19:
s_and_not1_saveexec_b32 s3, s16
s_cbranch_execz .LBB0_10
v_cvt_f32_u32_e32 v12, v4
v_sub_nc_u32_e32 v13, 0, v4
v_mov_b32_e32 v14, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v12, v12
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v12, 0x4f7ffffe, v12
v_cvt_u32_f32_e32 v12, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v13, v13, v12
v_mul_hi_u32 v13, v12, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v12, v12, v13
v_mul_hi_u32 v12, v19, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v12, v12, v4
v_sub_nc_u32_e32 v12, v19, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v13, v12, v4
v_cmp_ge_u32_e32 vcc_lo, v12, v4
v_cndmask_b32_e32 v12, v12, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v13, v12, v4
v_cmp_ge_u32_e32 vcc_lo, v12, v4
v_cndmask_b32_e32 v13, v12, v13, vcc_lo
s_branch .LBB0_10
.LBB0_21:
s_or_b32 exec_lo, exec_lo, s14
.LBB0_22:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s13
v_cmp_ne_u64_e32 vcc_lo, 1, v[13:14]
v_cmp_ne_u64_e64 s3, v[13:14], v[9:10]
s_mov_b32 s13, -1
s_mov_b32 s15, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, vcc_lo, s3
s_and_saveexec_b32 s14, s3
s_cbranch_execz .LBB0_34
v_dual_mov_b32 v16, v8 :: v_dual_mov_b32 v15, v7
s_mov_b32 s16, 0
s_mov_b32 s15, 0
s_branch .LBB0_26
.LBB0_24:
s_or_b32 exec_lo, exec_lo, s22
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 s19, s19, exec_lo
s_and_b32 s21, s21, exec_lo
s_and_not1_b32 s18, s18, exec_lo
s_and_b32 s3, s3, exec_lo
s_or_b32 s19, s19, s21
s_or_b32 s18, s18, s3
.LBB0_25:
s_or_b32 exec_lo, exec_lo, s20
s_xor_b32 s3, s19, -1
s_and_b32 s20, exec_lo, s18
v_mov_b32_e32 v12, s16
s_or_b32 s15, s20, s15
s_and_not1_b32 s17, s17, exec_lo
s_and_b32 s3, s3, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s17, s17, s3
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execz .LBB0_33
.LBB0_26:
s_or_b32 s19, s19, exec_lo
s_or_b32 s18, s18, exec_lo
s_mov_b32 s20, exec_lo
v_cmpx_ne_u64_e64 v[15:16], v[9:10]
s_cbranch_execz .LBB0_25
v_mul_lo_u32 v12, v13, v14
v_mad_u64_u32 v[17:18], null, v13, v13, 0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v18, v18, v12, v12
v_or_b32_e32 v12, v18, v6
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ne_u64_e32 0, v[11:12]
s_xor_b32 s21, exec_lo, s3
s_cbranch_execz .LBB0_29
v_sub_co_u32 v24, vcc_lo, 0, v5
v_sub_co_ci_u32_e32 v25, vcc_lo, 0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[12:13], null, v24, v3, 0
v_mul_lo_u32 v14, v25, v3
v_mul_lo_u32 v19, v24, v21
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v27, v3, v12
v_add3_u32 v26, v13, v19, v14
v_mad_u64_u32 v[19:20], null, v21, v12, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[13:14], null, v3, v26, 0
v_mad_u64_u32 v[22:23], null, v21, v26, 0
v_add_co_u32 v12, vcc_lo, v27, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v14, vcc_lo
v_add_co_u32 v12, vcc_lo, v12, v19
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v12, vcc_lo, v13, v20, vcc_lo
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v23, vcc_lo
v_add_co_u32 v12, vcc_lo, v12, v22
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v13, vcc_lo
v_add_co_u32 v26, vcc_lo, v3, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v27, vcc_lo, v21, v13, vcc_lo
v_mul_lo_u32 v14, v25, v26
v_mad_u64_u32 v[12:13], null, v24, v26, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v19, v24, v27
v_mul_hi_u32 v25, v26, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add3_u32 v24, v13, v19, v14
v_mad_u64_u32 v[19:20], null, v27, v12, 0
v_mad_u64_u32 v[13:14], null, v26, v24, 0
v_mad_u64_u32 v[22:23], null, v27, v24, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v12, vcc_lo, v25, v13
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v14, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v12, vcc_lo, v12, v19
v_add_co_ci_u32_e32 v12, vcc_lo, v13, v20, vcc_lo
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v23, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v12, vcc_lo, v12, v22
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v14, vcc_lo, v26, v12
v_add_co_ci_u32_e32 v24, vcc_lo, v27, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v25, v17, v14
v_mad_u64_u32 v[19:20], null, v18, v14, 0
v_mad_u64_u32 v[12:13], null, v17, v24, 0
v_mad_u64_u32 v[22:23], null, v18, v24, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v12, vcc_lo, v25, v12
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v12, vcc_lo, v12, v19
v_add_co_ci_u32_e32 v12, vcc_lo, v13, v20, vcc_lo
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v23, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v14, vcc_lo, v12, v22
v_add_co_ci_u32_e32 v19, vcc_lo, 0, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v20, v6, v14
v_mad_u64_u32 v[12:13], null, v5, v14, 0
v_mul_lo_u32 v14, v5, v19
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v12, vcc_lo, v17, v12
v_add3_u32 v13, v13, v14, v20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v14, v18, v13
v_sub_co_ci_u32_e64 v14, s3, v14, v6, vcc_lo
v_sub_co_ci_u32_e32 v13, vcc_lo, v18, v13, vcc_lo
v_sub_co_u32 v17, vcc_lo, v12, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_subrev_co_ci_u32_e64 v18, s3, 0, v14, vcc_lo
v_cmp_ge_u32_e64 s3, v12, v5
v_sub_co_ci_u32_e32 v14, vcc_lo, v14, v6, vcc_lo
v_cmp_ge_u32_e32 vcc_lo, v13, v6
v_cndmask_b32_e64 v19, 0, -1, s3
v_cmp_ge_u32_e64 s3, v17, v5
v_cndmask_b32_e64 v23, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, v18, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v20, 0, -1, s3
v_cmp_ge_u32_e64 s3, v18, v6
v_cndmask_b32_e64 v22, 0, -1, s3
v_cmp_eq_u32_e64 s3, v13, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v20, v22, v20, vcc_lo
v_sub_co_u32 v22, vcc_lo, v17, v5
v_subrev_co_ci_u32_e32 v14, vcc_lo, 0, v14, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v20
v_cndmask_b32_e64 v19, v23, v19, s3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v17, v17, v22, vcc_lo
v_cndmask_b32_e32 v14, v18, v14, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e32 vcc_lo, 0, v19
v_dual_cndmask_b32 v14, v13, v14 :: v_dual_cndmask_b32 v13, v12, v17
.LBB0_29:
s_and_not1_saveexec_b32 s3, s21
s_cbranch_execz .LBB0_31
v_cvt_f32_u32_e32 v12, v4
v_sub_nc_u32_e32 v13, 0, v4
v_mov_b32_e32 v14, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v12, v12
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v12, 0x4f7ffffe, v12
v_cvt_u32_f32_e32 v12, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v13, v13, v12
v_mul_hi_u32 v13, v12, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v12, v12, v13
v_mul_hi_u32 v12, v17, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v12, v12, v4
v_sub_nc_u32_e32 v12, v17, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v13, v12, v4
v_cmp_ge_u32_e32 vcc_lo, v12, v4
v_cndmask_b32_e32 v12, v12, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v13, v12, v4
v_cmp_ge_u32_e32 vcc_lo, v12, v4
v_cndmask_b32_e32 v13, v12, v13, vcc_lo
.LBB0_31:
s_or_b32 exec_lo, exec_lo, s3
s_mov_b32 s3, -1
s_mov_b32 s21, -1
s_mov_b32 s22, exec_lo
v_cmpx_ne_u64_e32 1, v[13:14]
s_cbranch_execz .LBB0_24
v_cmp_eq_u64_e32 vcc_lo, v[13:14], v[9:10]
v_lshlrev_b64 v[15:16], 1, v[15:16]
s_xor_b32 s21, exec_lo, -1
s_or_not1_b32 s3, vcc_lo, exec_lo
s_branch .LBB0_24
.LBB0_33:
s_or_b32 exec_lo, exec_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_or_not1_b32 s15, s17, exec_lo
.LBB0_34:
s_or_b32 exec_lo, exec_lo, s14
s_and_saveexec_b32 s3, s15
s_cbranch_execz .LBB0_7
s_add_u32 s6, s6, 1
s_addc_u32 s7, s7, 0
v_mov_b32_e32 v12, 1
s_cmp_eq_u64 s[6:7], s[4:5]
s_cselect_b32 s13, -1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_or_not1_b32 s13, s13, exec_lo
s_branch .LBB0_7
.LBB0_36:
s_or_b32 exec_lo, exec_lo, s12
s_branch .LBB0_38
.LBB0_37:
v_mov_b32_e32 v12, 1
.LBB0_38:
s_or_b32 exec_lo, exec_lo, s11
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
global_store_b8 v[0:1], v12, off
.LBB0_40:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24millerRabinPrimalityTestPyjPbyPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 30
.amdhsa_next_free_sgpr 23
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24millerRabinPrimalityTestPyjPbyPf, .Lfunc_end0-_Z24millerRabinPrimalityTestPyjPbyPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24millerRabinPrimalityTestPyjPbyPf
.private_segment_fixed_size: 0
.sgpr_count: 25
.sgpr_spill_count: 0
.symbol: _Z24millerRabinPrimalityTestPyjPbyPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 30
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void add( double *a, double *b, double *c, int n )
{
int tid = threadIdx.x + blockIdx.x * blockDim.x;
// handle the data at this index
while (tid < n) {
c[tid] = a[tid] + b[tid];
tid += blockDim.x * gridDim.x;
}
//printf("Value of *ip variable: %f\n", a[tid] );
} | code for sm_80
Function : _Z3addPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R9, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0209 */
/*0090*/ IMAD.WIDE R4, R0.reuse, R9.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0209 */
/*00a0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD.WIDE R8, R0, R9, c[0x0][0x170] ; /* 0x00005c0000087625 */
/* 0x000fe200078e0209 */
/*00d0*/ MOV R11, c[0x0][0x0] ; /* 0x00000000000b7a02 */
/* 0x000fca0000000f00 */
/*00e0*/ IMAD R0, R11, c[0x0][0xc], R0 ; /* 0x000003000b007a24 */
/* 0x000fca00078e0200 */
/*00f0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06270 */
/*0100*/ DADD R6, R4, R2 ; /* 0x0000000004067229 */
/* 0x004e0e0000000002 */
/*0110*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x0011ea000c101b04 */
/*0120*/ @!P0 BRA 0x70 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void add( double *a, double *b, double *c, int n )
{
int tid = threadIdx.x + blockIdx.x * blockDim.x;
// handle the data at this index
while (tid < n) {
c[tid] = a[tid] + b[tid];
tid += blockDim.x * gridDim.x;
}
//printf("Value of *ip variable: %f\n", a[tid] );
} | .file "tmpxft_0007b200_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z3addPdS_S_iPdS_S_i
.type _Z27__device_stub__Z3addPdS_S_iPdS_S_i, @function
_Z27__device_stub__Z3addPdS_S_iPdS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z3addPdS_S_iPdS_S_i, .-_Z27__device_stub__Z3addPdS_S_iPdS_S_i
.globl _Z3addPdS_S_i
.type _Z3addPdS_S_i, @function
_Z3addPdS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3addPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3addPdS_S_i, .-_Z3addPdS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void add( double *a, double *b, double *c, int n )
{
int tid = threadIdx.x + blockIdx.x * blockDim.x;
// handle the data at this index
while (tid < n) {
c[tid] = a[tid] + b[tid];
tid += blockDim.x * gridDim.x;
}
//printf("Value of *ip variable: %f\n", a[tid] );
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void add( double *a, double *b, double *c, int n )
{
int tid = threadIdx.x + blockIdx.x * blockDim.x;
// handle the data at this index
while (tid < n) {
c[tid] = a[tid] + b[tid];
tid += blockDim.x * gridDim.x;
}
//printf("Value of *ip variable: %f\n", a[tid] );
} |
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